MC33981_10 [FREESCALE]
Single High Side Switch; 单一的高边开关
| 型号： | MC33981_10 |
| 厂家： | 
Freescale |
| 描述： | Single High Side Switch |
| 文件： | 总40页 (文件大小：4031K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MC33981
Rev. 11.0, 7/2012
Freescale Semiconductor
Technical Data
Single High Side Switch
(4.0 mOhm), PWM clock up to
60 kHz
33981
The 33981 is a high frequency, self-protected 4.0 m RDS(ON) high
side switch used to replace electromechanical relays, fuses, and
discrete devices in power management applications.
HIGH SIDE SWITCH
The 33981 can be controlled by pulse-width modulation (PWM) with
a frequency up to 60 kHz. It is designed for harsh environments, and it
includes self-recovery features. The 33981 is suitable for loads with high
inrush current, as well as motors and all types of resistive and inductive
loads.
The 33981 is packaged in a 12 x 12 mm non-leaded power-enhanced
PQFN package with exposed tabs.
Features
Bottom View
• Single 4.0 m RDS(ON) maximum high side switch
• PWM capability up to 60 kHz with duty cycle from 5% to 100%
• Very low standby current
• Slew-rate control with external capacitor
• Over-current and over-temperature protection, under-voltage
shutdown, and fault reporting
FK (Pb-Free Suffix)
98ARL10521D
16-PIN PQFN (12 X 12)
ORDERING INFORMATION
• Reverse battery protection
• Gate drive signal for external low side N-channel MOSFET with
protection features
Device
(Add R2 Suffix for
Tape and Reel)
Temperature
Package
Range (T )
A
• Output current monitoring
• Temperature feedback
MC33981BHFK
MC33981ABHFK
-40 to 125 °C
16 PQFN
V
DD
V
PWR
V
DD
33981
CONF
VPWR
CBOOT
I/O
I/O
FS
INLS
EN
OUT
DLS
I/O
MCU
I/O
INHS
A/D
A/D
TEMP
CSNS
M
GLS
OCLS SR GND
Figure 1. 33981 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2007 - 2012. All rights reserved.
DEVICE VARIATIONS
DEVICE VARIATIONS
Table 1. Device Peak Solder Temperature
Description (1)
Device
MC33981BHFK
MC33981ABHFK
Notes
Original BOM and lower Peak Package Temperature solderability.
Improved BOM and higher Peak Package Temperature solderability.
1. PPT values can be found on Freescale’s web site, or contact sales. Reference Peak Package Reflow
(7)
Temperature During Reflow(6)
,
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Analog Integrated Circuit Device Data
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Freescale Semiconductor
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VPWR
Under-voltage
Detection
Temperature
Feedback
TEMP
SR
CBOOT
OUT
Bootstrap Supply
Gate Driver
Slew Rate Control
FS
EN
Current Protection
Logic
OUT Current
Recopy
INHS
INLS
Over-temperature
Detection
Low Side
Gate Driver
and Protection
GLS
DLS
5.0V
RDWN
ICONF
IDWN
5.0 V
IOCLS
Cross-
Conduction
CONF
GND
CSNS
OCLS
Figure 2. 33981 Simplified Internal Block Diagram
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Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
PIN CONNECTIONS
Package Transparent Top View
GND
13
VPWR
14
15
16
OUT
OUT
Figure 3. Pin Connections
Table 2. PIN DEFINITIONS
Descriptions of the pins listed in the table below can be found in the Functional Description section located on page 15.
Pin
Number
Pin
Function
Pin Name
Formal Name
Definition
This pin is used to generate a ground-referenced voltage for the
microcontroller (MCU) to monitor output current.
1
CSNS
Reports
Output Current Monitoring
This pin is used by the MCU to monitor board temperature.
This pin is used to place the device in a low-current Sleep mode.
2
3
TEMP
EN
Reports
Input
Temperature Feedback
Enable
(Active High)
This input pin is used to control the output of the device.
This pin monitors fault conditions and is active LOW.
4
5
INHS
FS
Input
Serial Input High Side
Reports
Fault Status
(Active Low)
This pin is used to control an external low side N-channel MOSFET.
This input manages MOSFET N-channel cross-conduction.
6
7
INLS
CONF
OCLS
DLS
Input
Input
Serial Input Low Side
Configuration Input
Low Side Overload
Drain Low Side
This pin sets the V protection level of the external low side MOSFET.
DS
8
Input
This pin is the drain of the external low side N-channel MOSFET.
9
Input
This output pin drives the gate of the external low side N-channel
MOSFET.
10
GLS
Output
Low Side Gate
This pin controls the output slew rate.
11
12
SR
CBOOT
GND
Input
Input
Slew Rate Control
Bootstrap Capacitor
Ground
This pin provides the high pulse current to drive the device.
This is the ground pin of the device.
13
Ground
Input
This pin is the source input of operational power for the device.
14
VPWR
OUT
Positive Power Supply
Output
These pins provide a protected high side power output to the load
connected to the device.
15, 16
Output
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Analog Integrated Circuit Device Data
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Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
ELECTRICAL RATINGS
Power Supply Voltage
Steady-state
VPWR
V
V
-16 to 41
Input/Output Pins Voltage(2)
INHS, INLS,
CONF, CSNS, FS,
TEMP, EN
-0.3 to 7.0
Output Voltage
Positive
VOUT
V
41.0
-5.0
Negative
Continuous Output Current(3)
CSNS Input Clamp Current
EN Input Clamp Current
SR Voltage
IOUT
ICL(CSNS)
ICL(EN)
VSR
40.0
A
mA
mA
V
15.0
2.5
-0.3 to 54.0
-0.3 to 54.0
-5.0 to 7.0
-0.3 to 15.0
-5.0 to 41.0
CBOOT Voltage
CBOOT
VOCLS
VGLS
V
OCLS Voltage
V
Low Side Gate Voltage
Low Side Drain Voltage
V
VDLS
V
ESD Voltage(4)
VESD
V
±2000
Human Body Model (HBM)
Charge Device Model (CDM)
Corner Pins (1, 12, 15, 16)
All Other Pins (2-11, 13-14)
±750
±500
Notes
2. Exceeding voltage limits on INHS, INLS, CONF, CSNS, FS, TEMP, and EN pins may cause a malfunction or permanent damage to the
device.
3. Continuous high side output rating as long as maximum junction temperature is not exceeded. Calculation of maximum output current
using package thermal resistance is required.
4. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ) and the Charge Device
Model (CDM), Robotic (CZAP = 4.0 pF).
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Analog Integrated Circuit Device Data
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ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
THERMAL RATINGS
Operating Temperature
Ambient
°C
TA
TJ
-40 to 125
-40 to 150
Junction
Storage Temperature
TSTG
-55 to 150
C
Thermal Resistance(5)
Junction to Power Die Case
Junction to Ambient
(7)
C/W
RJC
RJA
1.0
30.0
Peak Package Reflow Temperature During Reflow(6)
,
TPPRT
Note 7
°C
Notes
5. Device mounted on a 2s2p test board per JEDEC JESD51-2.
6. Pin soldering temperature limit is for 40 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
7. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
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Analog Integrated Circuit Device Data
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Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics
Characteristics noted under conditions 6.0 V VPWR 27 V, -40 C TA 125 C, unless otherwise noted. Typical values
noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUT (VPWR)
Battery Supply Voltage Range
Fully Operational
VPWR
V
6.0
4.5
–
–
27.0
27.0
Extended(8)
VPWR Supply Current
IPWR(ON)
IPWR(SBY)
IPWR(SLEEP)
mA
mA
A
INHS = 1 and OUT Open, INLS = 0
–
–
10.0
10.0
12.0
12.0
VPWR Supply Current
INHS = INLS = 0, EN = 5.0 V, OUT Connected to GND
Sleep-state Supply Current
(VPWR < 14 V, EN = 0 V, OUT Connected to GND)
TA = 25 C
–
–
–
–
5.0
TA = 125 C
50.0
Under-voltage Shutdown
Under-voltage Hysteresis
VPWR(UV)
2.0
4.0
4.5
0.3
V
V
VPWR(UVHYS)
0.05
0.15
POWER OUTPUT (IOUT, VPWR)
Output Drain-to-Source ON Resistance (IOUT = 20 A, TA = 25 C)
RDS(ON)25
m
m
VPWR = 6.0 V
VPWR = 9.0 V
VPWR = 13.0 V
–
–
–
–
–
–
6.0
5.0
4.0
Output Drain-to-Source ON Resistance (IOUT = 20 A, TA = 150 C)
RDS(ON)150
VPWR = 6.0 V
VPWR = 9.0 V
VPWR = 13.0 V
–
–
–
–
–
–
10.2
8.5
6.8
Output Source-to-Drain ON Resistance (IOUT = -20 A, TA = 25 C)(9)
RSD(ON)
m
A
VPWR = - 12 V
–
75
–
–
8.0
125
–
Output Over-current Detection Level
9.0 V < VPWR < 16 V
IOCH
100
Current Sense Ratio
CSR
–
9.0 V < VPWR < 16 V, CSNS < 4.5 V
1/20000
Current Sense Ratio (CSR) Accuracy
9.0 V < VPWR < 16 V, CSNS < 4.5 V
Output Current
CSR_ACC
%
-20
-15
–
–
20
15
5.0 A
15 A, 20 A, and 30 A
Notes
8. OUT can be commanded fully on, PWM is available at room. Low Side Gate driver is available. Protections and Diagnosis are not
available. Min/max parameters are not guaranteed.
9. Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VPWR
.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
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ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 6.0 V VPWR 27 V, -40 C TA 125 C, unless otherwise noted. Typical values
noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT (VPWR) (continued)
Current Sense Voltage Clamp
ICSNS = 15 mA
VCL(CSNS)
V
4.5
0
6.0
13
7.0
17
Current Sense Leakage(10)
ILEAK(CSNS)
A
INHS = 1 with OUT opened of load or INHS = 0
Over-temperature Shutdown
TSD
160
5.0
175
–
190
20
°C
Over-temperature Shutdown Hysteresis(11)
TSDHYS
C
LOW SIDE GATE DRIVER (VPWR, VGLS, VOCLS)
Low Side Gate Voltage
VPWR = 6.0 V
VGLS
V
5.0
8.0
5.4
8.4
6.0
9.0
VPWR = 9.0 V
12.0
12.0
12.4
12.4
13.0
13.0
VPWR = 13 V
VPWR = 27 V
Low Side Gate Sinked Current
VGLS = 2.0 V, VPWR = 13 V
IGLSNEG
IGLSPOS
VDS_LS
mA
mA
mV
–
–
100
100
–
–
–
Low Side Gate Sourced Current
VGLS = 2.0 V, VPWR = 13 V
Low Side Overload Detection Level versus Low Side Drain Voltage
VOCLS - VDLS, (VOCLS V
-50
+50
CONTROL INTERFACE (CONF, INHS, INLS, EN, OCLS)
Input Logic High-voltage (CONF, INHS, INLS)
Input Logic Low-voltage (CONF, INHS, INLS)
Input Logic Voltage Hysteresis (CONF, INHS, INLS)
Input Logic Active Pull-down Current (INHS, INLS)
Enable Pull-down Resistor (EN)
VIH
VIL
3.3
–
–
–
V
V
–
1.0
VINHYS
IDWN
RDWN
VEN
100
5.0
100
600
10
1200
20
mV
A
k
V
200
2.5
400
Enable Voltage Threshold (EN)
Input Clamp Voltage (EN)
IEN < 2.5 mA
VCLEN
V
7.0
-2.0
50
–
–
14
-0.3
200
20
Input Forward Voltage (EN)
Input Active Pull-up Current (OCLS)
Input Active Pull-up Current (CONF)
Notes
VF(EN)
IOCLSp
ICONF
V
100
10
A
A
5.0
10. This parameter is achieved by the design characterization by measuring a statistically relevant sample size across process variations
but not tested in production.
11. Parameter is guaranteed by process monitoring but is not production tested.
33981
Analog Integrated Circuit Device Data
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Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 6.0 V VPWR 27 V, -40 C TA 125 C, unless otherwise noted. Typical values
noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
CONTROL INTERFACE (CONF, INHS, INLS, EN, OCLS) (continued)
FS Tri-state Capacitance(12)
CFS
–
–
–
20
pF
V
FS Low-state Output Voltage
IFS = -1.6 mA
VFSL
0.2
0.4
Temperature Feedback
V
V
TFEED
TA = 25°C for VPWR = 14 V
3.35
-8.5
3.45
-8.9
3.55
-9.3
Temperature Feedback Derating(12)
DTFEED
mV/°C
Notes
12. Parameter is guaranteed by process monitoring but is not production tested.
33981
Analog Integrated Circuit Device Data
Freescale Semiconductor
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ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions 6.0 V VPWR 27 V, -40 C TA 125 C, unless otherwise noted. Typical values
noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
CONTROL INTERFACE AND POWER OUTPUT TIMING (CBOOT, VPWR)
Charge Blanking Time (CBOOT)(14)
tON
10
25
50
s
Output Rising Slew Rate
SR
V/s
R
V
= 13 V, from 10% to 90% of V
SR Capacitor = 4.7 nF,
SR Capacitor = 4.7 nF,
PWR
OUT,
OUT,
R = 5.0
L
8.0
16
35
Output Falling Slew Rate
SR
V/s
F
V
= 13 V, from 90% to 10% of V
PWR
R = 5.0
L
8.0
16
35
Output Turn-ON Delay Time(15)
tDLYON
ns
ns
V
= 13 V, SR Capacitor = 4.7 nF
200
400
700
PWR
Output Turn-OFF Delay Time(16)
= 13 V, SR Capacitor = 4.7 nF
tDLYOFF
V
500
1000
1500
PWR
Input Switching Frequency(13)
Output PWM ratio at 60 kHz(17)
Time to Reset Fault Diagnosis
f
–
20
–
60
95
kHz
%
PWM
R
5.0
PWM
tRSTDIAG
s
(overload on high side or external low side)
Output Over-current Detection Time
Notes
100
1.0
200
10
400
20
tOCH
s
13. The MC33981 fully operates down to DC. To reset a latched Fault the INHS pin must go low for the “Time to reset Fault Diagnosis”
(tRSTDIAG).
14. Values for CBOOT=100 nF. Refer to Sleep Mode on page 16. Parameter is guaranteed by design and not production tested.
15. Turn-ON delay time measured from rising edge of INHS that turns the output ON to V
= 0.5 V with R = 5.0 resistive load.
L
OUT
16. Turn-OFF delay time measured from falling edge of INHS that turns the output OFF to V
= V
-0.5 V with R = 5.0 resistive load.
PWR L
OUT
17. The ratio is measured at VOUT = 50% VPWR without SR capacitor. The device is capable of 100% duty cycle.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
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ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
INHS
5.0 V
0.0 V
V
OUT
R
V
- 0.5 V
PWM
50%V
PWR
PWR
0.5 V
tDLY(OFF)
tDLY(ON)
V
OUT
90% Vout
10% Vout
SRF
SRR
Figure 4. Time Delays Functional Diagrams
EN
t
After
ON
FS
5.0 V
CONF
INHS
INLS
OUT
GLS
Figure 5. Normal Mode, Cross-Conduction Management
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ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
EN
t
ON After
FS
CONF
0.0 V
High Side ON
INHS
High Side OFF
INLS
OUT
GLS
Figure 6. Normal Mode, Independent High Side and Low Side
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Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES
ELECTRICAL PERFORMANCE CURVES
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
-50
0
50
100
150
200
Temperature (°C)
vs. Temperature at VPWR = 13 V
Figure 7. Typical R
DS(ON)
10.0
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
4.5
6.0
9.0
12.0
12.5 13.0
(V)
14.0 17.0
21.0
V
PWR
Figure 8. Typical Sleep-state Supply Current vs. V
at 150 °C
PWR
1600
1400
1200
1000
800
600
400
200
0
6.0
SR Capacitor (nF)
8.0
4.0
10
0
2.0
Figure 9. VOUT Rise Time vs. SR Capacitor From 10% to 90% of VOUT at 25 °C and VPWR = 13 V
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Freescale Semiconductor
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ELECTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES
1600
1400
1200
1000
800
600
400
200
0
8.0
4.0
6.0
10
0
2.0
SR Capacitor (nF)
Figure 10. VOUT Fall Time vs. SR Capacitor From 10% to 90% of VOUT at 25 °C and VPWR = 13 V
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Analog Integrated Circuit Device Data
Freescale Semiconductor
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FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33981 is a high-frequency self-protected silicon
4.0 mRDS(ON) high side switch used to replace
electromechanical relays, fuses, and discrete devices in
power management applications. The 33981 can be
controlled by pulse-width modulation (PWM) with a frequency
up to 60 kHz. It is designed for harsh environments, and it
includes self-recovery features.
The 33981 is suitable for loads with high inrush current, as
well as motors and all types of resistive and inductive loads.
A dedicated parallel input is available for an external low side
control with protection features and cross-conduction
management.
FUNCTIONAL PIN DESCRIPTIONS
two MOSFETs are controlled independently. When CONF is
at VDD 5.0 V, the two MOSFETs cannot be on at the same
time.
OUTPUT CURRENT MONITORING (CSNS)
This pin is used to output a current proportional to the high
side OUT current and is used externally to generate a
ground-referenced voltage for the microcontroller (MCU) to
monitor OUT current.
LOW SIDE OVERLOAD (OCLS)
This pin sets the VDS protection level of the external low
side MOSFET. This pin has an active internal pull-up current
source. It must be connected to an external resistor.
TEMPERATURE FEEDBACK (TEMP)
This pin reports an analog value proportional to the
temperature of the GND flag (pin 13). It is used by the MCU
to monitor board temperature.
DRAIN LOW SIDE (DLS)
This pin is the drain of the external low side N-channel
MOSFET. Its monitoring allows protection features: low side
short protection and VPWR short protection.
ENABLE [ACTIVE HIGH] (EN)
This is an input used to place the device in a low-current
Sleep Mode. This pin has an active passive internal pull-
down.
LOW SIDE GATE (GLS)
This pin is an output used to drive the gate of the external
low side N-channel MOSFET.
INPUT HIGH SIDE (INHS)
The input pin is used to directly control the OUT. This input
has an active internal pull-down current source and requires
CMOS logic levels.
SLEW RATE CONTROL (SR)
A capacitor connected between this pin and ground is
used to control the output slew rate.
FAULT STATUS (FS)
BOOTSTRAP CAPACITOR (CBOOT)
This pin is an open drain-configured output requiring an
external pull-up resistor to VDD (5.0 V) for fault reporting.
When a device fault condition is detected, this pin is active
LOW.
A capacitor connected between this pin and OUT is used
to switch the OUT in PWM mode.
GROUND (GND)
INPUT LOW SIDE (INLS)
This pin is the ground for the logic and analog circuitry of
the device.
This input pin is used to directly control an external low
side N-channel MOSFET and has an active internal pull-
down current source and requires CMOS logic levels. It can
be controlled independently of the INHS depending of CONF
pin.
POSITIVE POWER SUPPLY (VPWR)
This pin connects to the positive power supply and is the
source input of operational power for the device. The VPWR
pin is a backside surface mount tab of the package.
CONFIGURATION INPUT (CONF)
This input pin is used to manage the cross-conduction
between the internal high side N-channel MOSFET and the
external low side N-channel MOSFET. The pin has an active
internal pull-up current source. When CONF is at 0 V, the
OUTPUT (OUT)
Protected high side power output to the load. Output pins
must be connected in parallel for operation.
33981
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
The 33981 has 2 operating modes: Sleep and Normal
depending on EN input.
NORMAL MODE
The 33981 will go to the Normal operating mode when the
EN pin is logic [1]. The INHS and INLS commands will be
disabled tON after the EN transitions to logic [1] to enable the
charge of the bootstrap capacitor.
SLEEP MODE
Sleep Mode is the state of the 33981 when the EN is
logic [0]. In this mode, OUT, the gate driver for the external
MOSFET, and all unused internal circuitry are off to minimize
current draw.
Table 6. Operating Modes
Condition
Sleep
CONF INHS INLS OUT
GLS
x
FS
H
EN
Comments
Device is in Sleep Mode. The OUT and low side gate are OFF.
x
x
x
x
L
Normal mode. High side and low side are controlled
Normal
L
H
H
H
H
H
H
independently. The high side and the low side are both on.
Normal mode. High side and low side are controlled
independently. The high side and the low side are both off.
Normal
Normal
Normal
Normal
L
L
L
L
L
H
L
L
L
L
H
L
H
H
H
H
H
H
H
H
Normal mode. Half-bridge configuration. The high side is off
and the low side is on.
Normal mode. Half-bridge configuration. The high side is on
and the low side is off.
L
H
H
Normal mode. Cross-conduction management is activated.
Half-bridge configuration.
H
PWM
H
PWM PWM_bar
H = High level
L = Low level
x = Don’t care
PWM_bar = Opposite of pulse-width modulation signal.
PROTECTION AND DIAGNOSTIC FEATURES
temperature falls below TSD. This cycle will continue until the
UNDER-VOLTAGE
offending load is removed. FS pin transition to logic [1] will be
disabled typically tON after to enable the charge of the
bootstrap capacitor.
The 33981 incorporates under-voltage protection. In case
of VPWR<VPWR(UV), the OUT is switched OFF until the power
supply rises to VPWR(UV)+VPWR(UVHYS). The latched fault are
reset below VPWR(UV). The FS output pin reports the under-
voltage fault in real time.
Over-temperature faults force the TEMP pin to 0 V.
OVER-CURRENT FAULT ON HIGH SIDE
OVER-TEMPERATURE FAULT
The OUT pin has an over-current high-detection level
called IOCH for maximum device protection. If at any time the
current reaches this level, OUT will stay OFF and the CSNS
pin will go to 0V. The OUT pin is reset (and the fault is
The 33981 incorporates over-temperature detection and
shutdown circuitry on OUT. Over-temperature detection also
protects the low side gate driver (GLS pin). Over-temperature
detection occurs when OUT is in the ON or OFF state and
GLS is at high or low level.
delatched) by a logic [0] at the INHS pin for at least tRST(DIAG)
.
When INHS goes to 0 V, CSNS goes to 5.0 V.
In Figure 15, the OUT pin is short-circuited to 0V. When
the current reaches IOCH, OUT is turned OFF within tOCH
owing to internal logic circuit.
For OUT, an over-temperature fault condition results in
OUT turning OFF until the temperature falls below TSD. This
cycle will continue indefinitely until the offending load is
removed. Figure 12 and Figure 18 show an over-temperature
on OUT.
OVER-LOAD FAULT ON LOW SIDE
An over-temperature fault on the low side gate drive
results in OUT turning OFF and the GLS going to 0V until the
This fault detection is active when INLS is logic [1]. Low
side overload protection does not measure the current
33981
Analog Integrated Circuit Device Data
16
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
directly but rather its effects on the low side MOSFET. When
VDLS > VOCLS, the GLS pin goes to 0 V and the OCLS
internal current source is disconnected and OCLS goes to
0 V. The GLS pin and the OCLS pin are reset (and the fault
is delatched) by a logic [0] at the INLS pin for at least
When the device is in the sleep mode, this bootstrap supply
is off to minimize current consumption.
HIGH SIDE GATE DRIVER
The high side gate driver switches the bootstrap capacitor
voltage to the gate of the MOSFET. The driver circuit has a
low-impedance drive to ensure that the MOSFET remains
OFF in the presence of fast falling dV/dt transients on the
OUT pin.
t
RST(DIAG). Figure 13 and Figure 14 illustrate the behavior in
case of overload on the low side gate driver.
When connected to an external resistor, the OCLS pin with
its internal current source sets the VOCLS level. By changing
the external resistance, the protection level can be adjusted
depending on low side characteristics. A 33 k resistor gives
a VDS level of 3.3 V typical.
This bootstrap capacitor connected between the power
supply and the CBOOT pin provides the high pulse current to
drive the device. The voltage across this capacitor is limited
to about 13 V typical.
This protection circuitry measures the voltage between the
drain of the low side (DLS pin) and the 33981 ground (GND
pin). For this reason it is key that the low side source, the
33981 ground, and the external resistance ground
connection are connected together in order to prevent false
error detection due to ground shifts.
An external capacitor connected between pins SR and
GND is used to control the slew rate at the OUT pin. Figure 9
and Figure 10 give VOUT rise and fall time versus different SR
capacitors.
The maximum OCLS voltage being 4.0 V, a resistor bridge
on DLS must be used to detect a higher voltage across the
low side.
LOW SIDE GATE DRIVER
The low side control circuitry is PWM capable. It can drive
a standard MOSFET with an R
as low as 10.0 m at a
DS(ON)
frequency up to 60 kHz. The V is internally clamped at
GS
CONFIGURATION
12 V typically to protect the gate of the MOSFET. The GLS
pin is protected against short by a local over-temperature
sensor.
The CONF pin manages the cross-conduction between
the internal MOSFET and the external low side MOSFET.
With the CONF pin at 0 V, the two MOSFETs can be
independently controlled. A load can be placed between the
high side and the low side.
THERMAL FEEDBACK
The 33981 has an analog feedback output (TEMP pin) that
provides a value in inverse proportion to the temperature of
the GND flag (pin 13). The controlling microcontroller can
“read” the temperature proportional voltage with its analog-
to-digital converter (ADC). This can be used to provide real-
time monitoring of the PC board temperature to optimize the
motor speed and to protect the whole electronic system.
TEMP pin value is VTFEED with a negative temperature
With the CONF pin at 5.0 V, the two MOSFETs cannot be
on at the same time. They are in half-bridge configuration as
shown in the 33981 Simplified Application Diagram. If INHS
and INLS are at 5.0 V at the same time, INHS has priority and
OUT will be at VPWR. If INHS changes from 5.0 V to 0 V with
INLS at 5.0 V, GLS will go to high state as soon as the VGS
of the internal MOSFET is lower than 2.0 V typically. A half-
bridge application could consist in sending PWM signal to the
INHS pin and 5.0 V to the INLS pin with the CONF pin at
5.0 V.
coefficient of DT
.
FEED
REVERSE BATTERY
Figure 20, illustrates the simplified application diagram in
the 33981 Simplified Application Diagram with a DC motor
and external low side. The CONF and INLS pins are at 5.0 V.
When INHS is at 5.0 V, current is flowing in the motor. When
INHS goes to 0 V, the load current recirculates in the external
low side.
The 33981 survives the application of reverse battery
voltage as low as -16 V. Under these conditions, the output’s
gate is enhanced to decrease device power dissipation. No
additional passive components are required. The 33981
survives these conditions until the maximum junction rating is
reached.
In the case of reverse battery in a half-bridge application,
a direct current passes through the external freewheeling
diode and the internal high side.
BOOTSTRAP SUPPLY
Bootstrap supply provides current to charge the bootstrap
capacitor through the VPWR pin. A short time is required after
the application of power to the device to charge the bootstrap
capacitor. A typical value for this capacitor is 100 nF. An
internal charge pump allows continuous MOSFET drive.
As Figure 11 shows, it is essential to protect this power
line. The proposed solution is an external N-channel low side
with its gate tied to battery voltage through a resistor. A high
side in the VPWR line could be another solution.
33981
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
GROUND (GND) DISCONNECT PROTECTION
V
V
DD
PWR
If the DC motor module ground is disconnected from load
ground, the device protects itself and safely turns OFF the
output regardless of the output state at the time of
disconnection. A 10 k resistor needs to be added between
the EN pin and the rest of the circuitry in order to ensure the
device turns off in case of ground disconnect and to prevent
exceeding this pin’s maximum ratings.
33981
MCU
No current
GND OUT
FAULT REPORTING
Diode
This 33981 indicates the faults below as they occur by
driving the FS pin to logic [0]:
V
M
PWR
10.0 k
• Over-temperature fault
• Over-current fault on OUT
• Overload fault on the external low side MOSFET
The FS pin will return to logic [1] when the over
temperature fault condition is removed. The two other faults
are latched.
Figure 11. Reverse Battery Protection
33981
Analog Integrated Circuit Device Data
18
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
Table 7. Functional Truth Table in Fault Mode
Conditions
CONF INHS INLS OUT
GLS
FS
EN
TEMP CSNS OCLS
Comments
The 33981 is currently in Fault mode.
The OUT is OFF. TEMP at 0V
indicates this fault. Once the fault is
removed 33981 recovers its normal
mode.
Over-temperature
on OUT
x
x
x
L
x
x
L
L
L
x
H
L
H
L
L
x
x
x
x
L
x
x
x
x
L
The 33981 is currently in Fault mode.
The OUT is OFF and GLS is at 0V.
TEMP at 0V indicates this fault. Once
the fault is removed 33981 recovers its
Normal Mode.
Over-temperature
on GLS
x
x
L
x
L
L
L
L
H
H
H
The 33981 is currently in Fault mode.
The OUT is OFF. It is reset by a
logic [0] at INHS for at least tRST(DIAG)
When INHS goes to 0V, CSNS goes to
5.0 V.
Over-current
on OUT
H
L
L
H
.
The 33981 is currently in Fault mode.
GLS is at 0 V and OCLS internal
current source is off. The external
resistance connected between OCLS
and GND pin will pull OCLS pin to 0V.
The fault is reset by a logic [0] at INLS
Overload
on External Low
Side MOSFET
for at least tRST(DIAG)
.
H = High level
L = Low level
x = Don’t care
33981
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
EN
5.0 V
5.0 V
CONF
INHS
INLS
OUT
0.0 V
GLS
FS
5.0 V
5.0 V
0.0 V
0.0 V
0.0 V
TEMP
TSD
TSD
Temperature
OUT
Hysteresis
Hysteresis
High Side ON
High Side OFF
Thermal Shutdown
on OUT
Thermal Shutdown
on OUT
Figure 12. Over-temperature on Output
33981
Analog Integrated Circuit Device Data
20
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
5.0 V
5.0 V
EN
INLS
0.0 V
tRST(DIAG)
GLS
0.0 VLow Side OFF
5.0 V
FS
0.0 V
0.0 V
OCLS
V
V
VDS_LS
DS_LS = OCLS
Case 1: Overload Removed
Overload on Low Side
Figure 13. Overload on Low Side Gate Drive, Case 1
5.0 V
EN
INLS
0.0 V
tRST(DIAG)
GLS
0.0 V Low Side OFF
FS
0.0 V
OCLS
0.0 V
V
V
DS_LS = OCLS
Case 2: Low Side Still Overloaded
VDS_LS
Overload on Low Side
Figure 14. Overload on Low Side Gate Drive, Case 2
33981
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
5.0 V
EN
INHS
0.0 V
tRST(DIAG)
OUT
FS
0.0 V
5.0 V
0.0 V
VCL (CSNS)
CSNS
0.0 V
I
OCH
Fault Removed
IOUT
Over-current on High Side
Figure 15. Over-current on Output
Figure 16. High Side Over-current
33981
Analog Integrated Circuit Device Data
22
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
Current in Motor
Recirculation in Low Side
Figure 17. Cross-Conduction with Low Side
Over-temperature
INHS
TEMP
OUT
IOUT
Figure 18. Over-temperature on OUT
33981
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
Figure 19. Maximum Operating Frequency for SR Capacitor of 4.7 nF
33981
Analog Integrated Circuit Device Data
24
Freescale Semiconductor
TYPICAL APPLICATIONS
INTRODUCTION
TYPICAL APPLICATIONS
INTRODUCTION
Figure 20 shows a typical application for the 33981. A brush DC motor is connected to the output. A low side gate driver is
used for the freewheeling phase. Typical values for external capacitors and resistors are given.
.
VPWR
VPWR
VDD
VDD
330 F
33981
100 nF
VPWR
SR
Voltage regulator
1.0 k
2.2 nF
10 k
CBOOT
100 nF
CONF
FS
OUT
DLS
I/O
10 k
INLS
EN
I/O
I/O
10 k
10 k
MCU
I/O
INHS
TEMP
CSNS
OCLS
A/D
A/D
M
GLS
GND
1.0 k
33 k
Figure 20. 33981 Typical Application Diagram
EMC AND EMI RECOMMENDATIONS
the output and, therefore, reduce electromagnetic
perturbations.
INTRODUCTION
This section relates the EMC capability for 33981, high
frequency high-current high side switch. This device is a self-
protected silicon switch used to replace electromechanical
relays, fuses, and discrete circuits in power management
applications.
In standard configuration, the motor current recirculation is
handled by an external freewheeling diode. To reduce global
power dissipation, the freewheeling diode can be replaced by
an external discrete MOSFET in low side configuration. The
IC integrates a gate driver that controls and protects this
external MOSFET in the event of short-circuit to battery. The
product manages the cross conduction between the internal
high side and the external low side when used in a half-bridge
configuration. The two MOSFETs can be controlled
This section presents the key features of the device and its
targeted applications. The automotive standard to measure
conducted and radiated emissions is provided. Concrete
measurements on the 33981 and improvements to reduce
electromagnetic emission are described.
independently when the CONF pin is at 0 V. To eliminates
fuses, the device is self-protected from severe short-circuits
(100 A typical) with an innovative over-current strategy.
DEVICE FEATURES
This 33981 is a 4.0 m self-protected, high side switch
digitally controlled from a microcontroller (MCU) with
extended diagnostics, able to drive DC motors up to 60 kHz.
The 33981 has a current feedback for real-time monitoring
of the load current through an MCU analog/digital converter
to facilitate closed-loop operation for motor speed control.
A bootstrap architecture has been used to provide fast
transient gate voltage in order to reach 4.0 m RDS(ON)
maximum at room temperature. In parallel, a charge pump is
implemented to offer continuous on-state capability. This
dual current supply of the high side MOSFET allows a duty
cycle from 5% to 100%. An external capacitor connected
between pins SR and GND is used to control the slew rate at
The 33981 has an analog thermal feedback that can be
used by the MCU to monitor PC board temperature to
optimize the motor control and to protect the entire electronic
system. Therefore, an over-temperature shutdown feature
protects the IC against high overload condition.
Figure 21 illustrates the typical application diagram.
33981
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
TYPICAL APPLICATIONS
EMC AND EMI RECOMMENDATIONS
HOW TO MEASURE ELECTROMAGNETIC
EMISSION ACCORDING TO THE CISPR25
One EMC standard in the automotive world (at system
level) is the CISPR25, edited by the International
Electrotechnical Commission. This standard describes the
measurement method to measure both conducted and
radiated emission.
CONDUCTED EMISSION MEASUREMENT
Conducted emission is the emission produced by the
device on the battery cable. The test bench is described by
CISPR25 (see Figure 23).
The Line Impedance Stabilization Network (LISN), also
called artificial network (AN), in a given frequency range
(150 kHz to 108 MHz), provides a specified load impedance
for the measurement of disturbance voltages and isolates the
equipment under test (EUT) from the supply in that frequency
range.
Figure 21. Typical Application Diagram
APPLICATION
Engine cooling, air conditioning, and fuel pump are the
targeted automotive applications for the 33981. Conventional
solutions are designed with discrete components that are not
optimized in terms of component board size, protection, and
diagnostics. The 33981 is the right candidate to develop
lighter and more compact units.
2000+ 200mm
Contact to
Ground Plane
DC motor speed adjustment allows optimization of energy
consumption by reducing supply voltage, hence the mean
voltage applied to the motor. The commonly used control
technique is pulse wide modulation (PWM) where the
average voltage is proportional to the duty cycle. Most
applications require a PWM frequency of at least 20 kHz to
avoid audible noise. Figure 22 illustrates typical waveforms
when switching the 33981 at 20 kHz with a duty cycle of 80%.
LISN
+
Ground
Power Supply
BF Generator
-
Out
EUT
Load
Non-Conductive
Material
High Side Driver Signal
Electrical to Optical
Converter
Coaxial Cable
Ground Plane in Copper
12V Power Supply
The output voltage (OUT) and current in the motor (IMOTOR
waveforms are represented.
)
Spectrum Analyzer
Figure 23. Test Bench for Conducted Emission
The EUT must operate under typical loading and other
conditions just as it must in the vehicle so maximum emission
state occurs. These operating conditions must be clearly
defined in the test plan to ensure that both supplier and
customer are performing identical tests.
OUT
For the testing described in this application note, the out
pin of the 33981 was connected to an inductive load (0.47
+ 1.0 H) switching at 20 kHz with a duty cycle of 80%. The
output current was 17 A continuous.
Imotor (10A/div)
MC33981 OFF
MC33981 ON
The ground return of the EUT to the chassis must be as
short as possible. The power supply is 13.5 V.
RADIATED EMISSION MEASUREMENT
The radiated emission measurement consists of
measuring the electromagnetic radiation produced by the
equipment under test. CISPR 25 gives the schematic test
bench described in Figure .
Figure 22. Current and Voltage waveforms
33981
Analog Integrated Circuit Device Data
26
Freescale Semiconductor
TYPICAL APPLICATIONS
EMC AND EMI RECOMMENDATIONS
To measure radiated emission over all frequency ranges,
several antenna types must be used:
BOARD SETUP
The initial configuration of our 33981 board is represented
in Figure 25.
• 0.15 MHz to 30 MHz: 1.0 m vertical monopole in
vertical polarization.
• 30 MHz to 200 MHz: a biconical antenna used in
vertical and horizontal polarization.
• 200 MHz to 1,000 MHz: a log-periodic antenna used in
vertical and horizontal polarization.
No SR capacitor is used. Therefore, the obtained
switching times are the maximum values. A capacitor of
1000 F is connected between VPWR and GND.
GND
Out
V
PWR
33981
Figure 25. 33981 Initial Configuration
CONDUCTED MEASUREMENTS
TEST SETUP
Key
To perform a conducted emission measurement in
accordance with the CISPR 25 standard, the test bench in
Figure 26 was developed.
1
EUT (grounded locally if
required in test plan)
8
Biconical antenna
2
3
Test harness
–
–
Load simulator (placement
and ground connection)
10 High quality double-
shielded coaxial cable
(50 )
4
Power supply (location
optional)
11 Bulkhead connector
Power Supply
LISN
Measurement
Point for
Conducted
Emission
5
6
Artificial Network (AN)
12 Measuring instrument
13 RF absorber material
Ground plane (bonded to
shielded enclosure)
EUT
7
Low relative permittivity
support ( 1.4)
14 Stimulation and monitoring
system
Non-Conductive
Material
Load (1.0 mH + 0.47 Ω)
Figure 24. Test Bench for Radiated Emission
Optical PWM Signal
EMC RESULTS AND IMPROVEMENTS
The 33981 OUT is connected to an inductive load (0.47
+ 1.0mH) switching at 20 kHz with duty = 80%. The current in
the load was 17 A continuous.
Figure 26. Conducted Emission Test Setup
33981
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
TYPICAL APPLICATIONS
EMC AND EMI RECOMMENDATIONS
EFFECTS OF SOME PARAMETERS
RC Out
Filter C2
RC In
Filter
PI
Filter
The conducted emissions level rise with the duty cycle.
When the duty increases the di/dt on the VPWR line is higher.
The device has to deliver more current and provide more
energy. Figure 27 describes the effect of duty cycle increase
on the VPWR current waveform. The conducted emission
level rises with the output frequency. This is due to the
increasing number of commutations.
C3
Duty Cycle
Increase
C1
SR
I(t) on VBAT
t
Figure 27. VPWR Current
HOW TO REDUCE ELECTROMAGNETIC EMISSION
By adjusting the slew rate of the device during turn ON and
turn OFF with SR capacitor, the electromagnetic emissions
can be reduced.
Figure 29. Enhanced Board
The chart in Figure 30 shows the spectrum of the
enhanced board and the initial board. The improvement is
appreciatively 15 dB to 20 dB in the all frequency range. The
enhanced board is now in accordance with the Class 3 limits
of the CISPR25 standard for conducted emission.
Conductive emission tests were performed (taking care of
the board filtering and routing that have a big impact on EMC
performances).
An optimized solution was found by adding the following
external components to the initial board:
• PI filter on the VPWR: 2 x 3 F and 3.5H
• RC IN filter between VPWR and GND: a 2.0 resistor in
series with a 100 nF capacitor
• RC Out filter between OUT and GND: a 4.7 resistor
in series with a 100 nF capacitor
• Capacitor C1 of 10 nF between VPWR and GND
• Capacitor C2 of 10 nF between OUT and GND
• Capacitor C3 of 10 nF between OUT and VPWR
• Capacitor SR of 3.3 nF
C3 = 10 nF
RC In Filter
RC Out Filter
PI filter
Figure 30. Conducted Emission Spectrum for 33981
RADIATED MEASUREMENTS
3.5 μH
OUT
VBAT
33981
3000 μF
This test was performed in order to evaluate the
characteristic of the device relating to radiated emission.
Measurements have been done in accordance with the
CISPR 25 standard as shown in Figure 31. The tested board
was the EMC enhanced board.
SR
3.3 nF
GND
Figure 28. 33981 with Filter
The EMC enhanced board with adapted value filter is
represented in Figure 29.
33981
Analog Integrated Circuit Device Data
28
Freescale Semiconductor
TYPICAL APPLICATIONS
POWER DISSIPATION
1.5 m Length
of Cable
CISPR
Class 3
Limits
Anechoic
Chamber
33981
Emission
LISN and
Inductive Load
EUT
Figure 32. Radiated Emission Spectrum for 33981
CONCLUSION
1 m Vertical
Monopole
Antenna
Figure 31. Radiated Emission Test Set-up
This document explains how to measure conducted and
radiated emission in accordance with the automotive
CISPR25 standard. Measurements were performed on the
33981 in real application conditions, when driving an
inductive load. An optimized filtering solution was put in place
to have the tested system in accordance with the Class 3
limits. The same method can be used with other PC boards.
The results of these measurements are represented in
Figure 32. The enhanced board is in accordance with the
Class 3 limits of the CISPR25 standard for radiated emission.
POWER DISSIPATION
product manages the cross conduction between the internal
high side and the external low side when used in a half-bridge
configuration. The two MOSFETs can be controlled
independently when the CONF pin is at 0 V. To eliminates
fuses, the device is self-protected from severe short-circuits
(100 A typical) with an innovative over-current strategy.
INTRODUCTION
This section relates to the power dissipation capability for
33981, high frequency high-current high side switch. This
device is a self-protected silicon switch used to replace
electromechanical relays, fuses, and discrete circuits in
power management applications.
The 33981 has a current feedback for real-time monitoring
of the load current through an MCU analog/digital converter
to facilitate closed-loop operation for motor speed control.
This section presents the key features of the device and its
targeted applications. The theoretical calculations for power
dissipation and die junction temperatures are determined in
this document for inductive loads. A concrete example with
DC motor driven by the 33981 is analyzed in DC Motor 200W.
The 33981 has an analog thermal feedback that can be
used by the MCU to monitor PC board temperature to
optimize the motor control and to protect the entire electronic
system. Therefore, an over-temperature shutdown feature
protects the IC against high overload condition.
DEVICE FEATURES
This 33981 is a 4.0 m self-protected, high side switch
digitally controlled from a microcontroller (MCU) with
extended diagnostics, able to drive DC motors up to 60 kHz.
Figure 33 illustrates the typical application diagram.
A bootstrap architecture has been used to provide fast
transient gate voltage in order to reach 4.0 m RDS(ON)
maximum at room temperature. In parallel, a charge pump is
implemented to offer continuous on-state capability. This
dual current supply of the high side MOSFET allows a duty
cycle from 5% to 100%. An external capacitor connected
between pins SR and GND is used to control the slew rate at
the output and, therefore, reduce electromagnetic
perturbations.
In standard configuration, the motor current recirculation is
handled by an external freewheeling diode. To reduce global
power dissipation, the freewheeling diode can be replaced by
an external discrete MOSFET in low side configuration. The
IC integrates a gate driver that controls and protects this
external MOSFET in the event of short-circuit to battery. The
Figure 33. Typical Application Diagram
33981
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
TYPICAL APPLICATIONS
POWER DISSIPATION
The analysis that follows assumes an inductive load and
assumes that the current is constant in the load.
APPLICATION
Engine cooling, air conditioning, and fuel pump are the
targeted automotive applications for the 33981. Conventional
solutions are designed with discrete components that are not
optimized in terms of component board size, protection, and
diagnostics. The 33981 is the right candidate to develop
lighter and more compact units.
The case being considered in this paper is inductive load
and the hypothesis is that the current is constant in the load.
ON-STATE LOSSES
The mean on-state loss periods in the 33981 can be
calculated as follows:
Pon_state = a · RDS(ON) · IOUT2 where ‘a’ is the duty cycle.
The adjustment of the DC motor speed allows optimizing
of energy consumption. It is realized by chopping the supply
voltage, hence the mean voltage, applied to the motor. The
commonly used control technique is pulse wide modulation
(PWM) where the average voltage is proportional to the duty
cycle. Most applications require a PWM frequency of at least
20 kHz to avoid audible noise. Figure 34 illustrates typical
waveforms when switching the 33981 at 20 kHz with a duty
cycle of 80%. The output voltage (OUT) and current in the
motor (IMOTOR) waveforms are represented.
The critical parameter is the on resistance (RDS(ON)) that
increases with temperature. The 33981 has a maximum
RDS(ON) at 25 ºC of 4.0 m and its deviation with
temperature is only 1.7 as shown in Figure 35.
7
6
5
4
3
2
1
0
OUT
-50
0
50
100
150
200
Imotor (10A/div)
Temperature (°C)
Figure 35. RDS(ON) vs. Temperature
MC33981 OFF
MC33981 ON
SWITCHING LOSSES
The mean switching losses in the 33981 can be calculated
as follows:
Pswitching = (tON . FREQ . VPWR . IOUT) / 2 + (tOFF . FREQ .
VPWR . IOUT) / 2
where tON OFF is the turn on/off time.
/t
The switching time is a critical parameter. The 33981
provides adjustable slew rates through an external capacitor
(SR) that slow down the rise and fall times to reduce the
electromagnetic emissions. However, this adjustment will
have an impact on power dissipation. Figure 36 gives the
positive (SRR) and negative (SRF) slew rate versus different
values of SR. This is illustrated in Figure 37.
Figure 34. Current and Voltage waveforms
POWER DISSIPATION
The 33981 power dissipation is the sum of two kinds of
losses:
• On-State losses when device is fully ON,
• Switching losses when the device switches ON and
OFF.
33981
Analog Integrated Circuit Device Data
30
Freescale Semiconductor
TYPICAL APPLICATIONS
POWER DISSIPATION
RECIRCULATION PHASE
In standard configuration, the motor current recirculation is
handled by an external freewheeling diode. With the 33981,
the freewheeling diode can be replaced by an external low-
side discrete MOSFET.
120
100
80
60
40
20
0
0
1
2.2
3.3
4.7
6.8
The power dissipation during the recirculation phase is
calculated as follows for the diode and the low-side MOSFET
respectively:
Pdiode = (1-a) . VF . IOUT
where ‘a’ is the duty cycle
4.5
6
9
14
27
2
Vbat
Pmosfet_ls = (1-a) . RDS(ON)_ls . IOUT
where RDS(ON)_ls is the on resistance of the low side.
APPLICATIONS EXAMPLES
EXCEL TOOL
90
80
70
60
50
40
30
20
10
0
0
1
2.2
3.3
4.7
6.8
An excel tool has been created with all the above formulas
to calculate the dissipated power and the junction
temperature knowing the application conditions. An example
of the interface is given in Figure 38. The parameters to enter
concern the load, the high side device, the recirculation, and
the board. They are VPWR, DC current in the load (Imax for
100% of duty cycle), PWM frequency, 33981 RDS(ON) at
150 ºC, SR capacitor, low side RDS(ON) at 150 ºC, ambient
temperature, and thermal impedance.
4.5
6
9
14
27
Vbat
Figure 36. Positive and Negative Slew Rate
vs. SR Capacitor
INPUTS
Vpwr
Imax
12
20
V
A
Load
Frequency
20 KHz
RDSON
@150°C
6.8mOhm
High Side
Device (HS)
SR
Capacitor
0
nF
Low Side Characteristics
Recirculation
Board
RDSON
@150°C
20 mOhm
Figure 37. OUT switching vs. SR Capacitor
JUNCTION TEMPERATURE
Rthja
15°C/W
85°C
T ambiant
The junction temperature of the 33981 can be calculated
knowing the power dissipation and the thermal
characteristics of the PC board with this formula:
Figure 38. Excel Tool
The calculations are done with the maximum RDS(ON) for
the 33981 and the low side. The current is also considered
constant in the load. The model taken for the VF of the diode
is (0.4 + 0.01 . IOUT) Volts.
TJ = TA + (Pon_state + Pswitching). RTHJA
where TJ is the junction temperature, TA the ambient
temperature, and RTHJA the thermal impedance junction to
ambient.
The listed conditions in Figure 38 are the ones chosen for
the entire document.
33981
Analog Integrated Circuit Device Data
Freescale Semiconductor
31
TYPICAL APPLICATIONS
POWER DISSIPATION
DC MOTOR 200W
INFLUENCE OF SR CAPACITOR
A concrete example is the 33981. A 200 W DC motor, a
frequency of 20 kHz, and an ambient temperature of 85 ºC
are chosen. The 33981 is evaluated using the following
board. The thermal impedance of the board is in the range of
15 ºC/W.
The SR capacitor value has an impact on these switching
losses. Figure 41 illustrates the percentage of the switching
losses versus the total power dissipation for the same load
conditions as Figure 38. The higher the SR capacitor value,
the higher the switching losses. They can be more than 50%
of the total power dissipation in the 33981 with a 4.7 nF
capacitor and is a basic applications trade-off. A compromise
should be found between the power dissipation and the
electromagnetic capability (EMC) performance.
6
Pswitching
Pon
5
4
3
2
1
0
Figure 39. 33981 Evaluation Board
POWER DISSIPATION
0
2.2
3.3
4.7
Csr (nF)
Figure 41. Power Switching vs. SR Capacitor
Figure 40 illustrates the power dissipation in the 33981.
The conditions are listed in Figure 38. Maximum power
dissipation of 3.1 W is obtained with a duty of 95%.
RECIRCULATION PHASE
Figure 42 illustrates the power dissipation for the two
recirculation approaches, diode or low side MOSFET. The
power dissipation gain for the entire system when using the
low side instead of the diode can reach up to 1.5 W with a
duty cycle of 50%.
MC33981 Power Dissipation
3.5
Pon_state
P switching
3.0
Ptotal
Total Board Power Dissipation
2.5
2.0
1.5
1.0
0.5
0
4.5
4.0
3.5
3.0
Power HS
Power Diode
2.5
Power Total Board with Diode
2.0
Power LS
Power Total Board with LS
1.5
1.0
0.5
0.0
0
10 20 30 40 50 60 70 80 90 100
Ratio PWM %
0
10
20
30
40
50
60
70
80
90
100
Duty Cycle (%)
Figure 42. Total Board Power Dissipation
Figure 40. Power Dissipation (Pon and Pswitching) vs.
Duty Cycle
33981
Analog Integrated Circuit Device Data
32
Freescale Semiconductor
TYPICAL APPLICATIONS
POWER DISSIPATION
JUNCTION TEMPERATURE
CONCLUSION
The junction temperature of the 33981 versus duty cycle
for the condition listed in Figure 38, is given in Figure 43. The
maximum obtained junction temperature is 132 ºC with a duty
cycle of 95%. This value is far from the 150ºC maximum
guaranteed junction.
Knowing the application conditions, this document
explained how to calculate power dissipation during on-state
and switching phases and the junction temperature for the
33981 when controlling a DC motor. A concrete example with
a 200 W DC motor was given in DC Motor 200W. The same
principle can be used for other DC motors and other
environmental conditions.
140.00
120.00
100.00
80.00
60.00
40.00
20.00
0.00
0
10
20
30
40
50
60
70
80
90
100
Duty cycle (%)
Figure 43. Junction Temperature vs. Duty Cycle
33981
Analog Integrated Circuit Device Data
Freescale Semiconductor
33
PACKAGING
SOLDERING INFORMATION
PACKAGING
SOLDERING INFORMATION
The 33981 is packaged in a surface mount power package (PQFN), intended to be soldered directly on the printed circuit
board. The AN2467 provides guidelines for Printed Circuit Board design and assembly.
PACKAGING DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using “98ARL10521D”.
Dimensions shown are provided for reference ONLY.
FK SUFFIX
16-PIN PQFN
98ARL10521D
ISSUE C
33981
Analog Integrated Circuit Device Data
34
Freescale Semiconductor
PACKAGING
PACKAGING DIMENSIONS
FK SUFFIX
16-PIN PQFN
98ARL10521D
ISSUE C
33981
Analog Integrated Circuit Device Data
Freescale Semiconductor
35
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 3.0)
ADDITIONAL DOCUMENTATION
33981
THERMAL ADDENDUM (REV 3.0)
INTRODUCTION
This thermal addendum is provided as a supplement to the 33981 technical
datasheet. The addendum provides thermal performance information that may be
critical in the design and development of system applications. All electrical,
application, and packaging information is provided in the datasheet.
16-PIN
PQFN
PACKAGING AND THERMAL CONSIDERATIONS
This package is a dual die package. There are two heat sources in the package
independently heating with P1 and P2. This results in two junction temperatures,
TJ1 and TJ2, and a thermal resistance matrix with RJAmn
.
For m, n = 1, RJA11 is the thermal resistance from Junction 1 to the reference
temperature while only heat source 1 is heating with P1.
98ARL10521D
16-PIN PQFN
12 MM X 12 MM
For m = 1, n = 2, RJA12 is the thermal resistance from Junction 1 to the
reference temperature while heat source 2 is heating with P2. This applies to
RJ21 and RJ22, respectively.
Note For package dimensions, refer to
98ARL10521D.
RJA11 RJA12
RJA21 RJA22
TJ1
TJ2
P1
P2
.
=
The stated values are solely for a thermal performance comparison of one package to another in a standardized environment.
This methodology is not meant to and will not predict the performance of a package in an application-specific environment. Stated
values were obtained by measurement and simulation according to the standards listed below.
STANDARDS
Table 8. Thermal Performance Comparison
1 = Power Chip, 2 = Logic Chip [C/W]
Thermal
m = 1,
n = 1
m = 1, n = 2
m = 2, n = 1
m = 2,
n = 2
Resistance
(1), (2)
22
7.0
62
18
4.0
48
41
27
81
1.0
JAmn
0.2 mm spacing
between PCB pads
(2), (3)
JBmn
(1), (4)
JAmn
(5)
<1.0
0.0
JCmn
Notes
0.2 mm spacing
1. Per JEDEC JESD51-2 at natural convection, still air
condition.
between PCB pads
2. 2s2p thermal test board per JEDEC JESD51-7and
JESD51-5.
Note: Recommended via diameter is 0.5 mm. PTH (plated through
hole) via must be plugged / filled with epoxy or solder mask in order
to minimize void formation and to avoid any solder wicking into the
via.
3. Per JEDEC JESD51-8, with the board temperature on the
center trace near the power outputs.
4. Single layer thermal test board per JEDEC JESD51-3 and
JESD51-5.
Figure 44. Surface mount for power PQFN
with exposed pads
5. Thermal resistance between the die junction and the
exposed pad, “infinite” heat sink attached to exposed pad.
33981
Analog Integrated Circuit Device Data
36
Freescale Semiconductor
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 3.0)
Transparent Top View
GND
13
A
VPWR
14
15
16
OUT
OUT
33981 Pin Connections
16-Pin PQFN
0.90 mm Pitch
12.0mm x 12.0mm Body
with exposed pads
Figure 45. Thermal Test Board
Device on Thermal Test Board
Table 9. Thermal Resistance Performance
Material:
Single layer printed circuit board
1 = Power Chip, 2 = Logic Chip (C/W)
FR4, 1.6 mm thickness
Area A
(mm2)
Thermal
Resistance
Cu traces, 0.07 mm thickness
m = 1,
n = 1
m = 1, n = 2
m = 2, n = 1
m = 2,
n = 2
Outline:
Area A:
80 mm x 100 mm board area,
including edge connector for thermal
testing
0
66
47
43
51
37
34
84
73
70
JAmn
300
600
Cu heat-spreading areas on board
surface
RJA is the thermal resistance between die junction and
ambient air
Ambient Conditions: Natural convection, still air
This device is a dual die package. Index m indicates the
die that is heated. Index n refers to the number of the die
where the junction temperature is sensed.
33981
Analog Integrated Circuit Device Data
Freescale Semiconductor
37
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 3.0)
90
80
70
60
50
40
30
20
10
0
R
R
x
JA11
JA22
R
JA12 = R
JA21
0
300
600
Heat spreading area [mm²]
A
Figure 46. Device on Thermal Test Board RJA
100
10
1
R
x
JA11
R
JA22
R
JA12 = R
JA21
0.1
1.00E-03 1.00E-02 1.00E-01 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04
Time[s]
Figure 47. Transient Thermal Resistance RJA
,
1 W Step response,Device on Thermal Test Board Area A = 600(mm2)
33981
Analog Integrated Circuit Device Data
Freescale Semiconductor
38
REVISION HISTORY
REVISION HISTORY
Revision
Date
Description of Changes
•
•
•
•
Implemented Revision History page
1/2006
3.0
Made content updates and changes
Converted to Freescale format
Added Thermal Addendum
•
•
Made minor content changes to pages 6 and 7.
Updated to Product Preview status
3/2006
5/2006
4.0
5.0
•
•
Changed Part Number from PC33981PNA to MC33981BPNA in the ordering information
Changed Electrical Characteristics, Maximum Ratings, Table 2, Maximum Ratings, Electrical
Ratings, OCLS Voltage, from “-5.0 to 5.0” to “-5.0 to 7.0” (page 5).
•
Changed Electrical Characteristics, Static Electrical Characteristics, Table 3, Static Electrical
Characteristics, Low Side Gate Driver (VPWR, VGLS, VOCLS), Low-Side Overload Detection
Level versus Low-Side Drain Voltage Minimum, from “-75” to “-50” and Maximum from “+75” to
“+50” (page 8).
•
•
Changed Electrical Characteristics, Dynamic Electrical Characteristics, Table 4, Dynamic Electrical
Characteristics, Control Interface and Power Output Timing (CBOOT, VPWR), Input Switching
Frequency, Minimum from “20” to “-” and Typical from “-” to “20” (page 10).
Updated to Advanced status
•
•
•
•
Changed CSNS Input Clamp Current in MAXIMUM RATINGS
Changed Figure 11, Reverse Battery Protection
Removed unnecessary line in Figure 14, Overload on Low Side Gate Drive, Case 2
Corrected label in Figure 28, 33981 with Filter
5/2007
6.0
7.0
•
•
•
Updated Freescale form and style
Minor text corrections.
10/2008
Added Current Sense Leakage(10)
6/2009
10/2010
5/2012
•
•
Corrected Reference to Figure 15 on Page 13.
Reworded Notes 5 and 11.
8.0
9.0
•
•
•
•
Updated Orderable part number from MC33981BPNA to MC33981BHFK
Updated (6)
Updated soldering information
10.0
Updated Freescale form and style
•
•
Added MC33981ABHFK to the ordering information
Added Device Variations table
7/2012
11.0
33981
Analog Integrated Circuit Device Data
Freescale Semiconductor
39
Information in this document is provided solely to enable system and software
implementers to use Freescale products. There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits on the
information in this document.
How to Reach Us:
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Freescale reserves the right to make changes without further notice to any products
herein. Freescale makes no warranty, representation, or guarantee regarding the
suitability of its products for any particular purpose, nor does Freescale assume any
liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental
damages. “Typical” parameters that may be provided in Freescale data sheets and/or
specifications can and do vary in different applications, and actual performance may
vary over time. All operating parameters, including “typicals,” must be validated for
each customer application by customer’s technical experts. Freescale does not convey
any license under its patent rights nor the rights of others. Freescale sells products
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Freescale, the Freescale logo, AltiVec, C-5, CodeTest, CodeWarrior, ColdFire, C-Ware,
Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, Qorivva, StarCore, and
Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off.
Airfast, BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, MagniV, MXC, Platform in a
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Semiconductor, Inc. All other product or service names are the property of their
respective owners.
© 2012 Freescale Semiconductor, Inc.
Document Number: MC33981
Rev. 11.0
7/2012
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