MC44BS374T1AD_技术文档

Document Number: MC44CC373

Rev 3.2, 04/2009

Freescale Semiconductor

CMOS Audio/Video RF Modulators

MC44CC373CA

MC44CC373CAS

MC44CC374CA

MC44CC374T1A

The MC44CC373 / MC44CC374 CMOS family of RF modulators is the latest

generation of the legacy MC44BS373/4 family of devices.

The MC44CC373/MC44CC374 RF modulators are designed for use in VCRs,

set-top boxes, and similar devices.They support multiple standards, and can be

programmed to support PAL, SECAM, or NTSC formats.

The devices are programmed by a high-speed I²C Bus.

A programmable, internal PLL, with on-chip LC tank covers the full UHF range.

The modulators incorporate a programmable, on-chip, sound subcarrier oscil-

lator that covers all broadcast standards. No external tank circuit components

are required, reducing PCB complexity and the need for external adjustments.

The PLL obtains its reference from a low cost 4 MHz crystal oscillator.

The devices are available in a 16-pin SOIC, Pb-free package. These parts are

functionally equivalent to the MC44BS373/4 series, but are not direct drop-in re-

placements.

CMOS AUDIO/VIDEO

RF MODULATORS

All devices now include the AUX_INfound previously only on the 20-pin pack-

age option of the MC44BS373. This is a direct input for a modulated subcarrier

and is useful in BTSC or NICAM stereo sound or other subcarrier applications.

The MC44CC373CASEF has a secondary I²C address for applications using

two modulators on one I²C Bus.

EF SUFFIX

SOIC-16 PACKAGE

CASE 751B-05

Features

•

Multi-TV standard support: NTSC, PAL, SECAM (B/G,

I, D/K, L, M/N).

•

Auxiliary input bypasses AM/FM modulators for

NICAM or BTSC applications.

•

UHF operation (460MHz to 880MHz)

Video modulation depth (96% typ. in system L and

85% typ. in the other standards)

Programmable UHF oscillator and sound subcarrier

oscillator.

•

Programmable Peak White Clip levels

•

On-chip tank circuits. No external varicaps inductors or

tuned components required.

On-chip video test pattern generator with sound test

signal (1 kHz)

•

Program control via 800 kHz high-speed I²C-bus.

•

Low-power standby mode

Programmable Sound reference frequency (31.25 kHz

or 62.5 kHz)

Output inhibit during PLL Lock-up at power-ON

Logical output port controlled by I²C-bus

•

Direct sound modulator input (FM and AM).

ORDERING INFORMATION

I²C

Write

Address

Default

(2)

PAL or

NTSC

Capability Capability

SECAM

(system L)

Replaces Part

Number

RF_OUT

Orderable Part Number⁽¹⁾

AUX_IN

Frequency

(dBμV)

(MHz)

MC44BS373CAD

MC44CC373CAEF, R2

MC44BS373CAEF

MC44BS373CAFC

MC44BS374CAD

MC44BS374CAEF

MC44BS374T1D

MC44BS374T1EF

MC44BS374T1AD

MC44BS374T1AEF

591.25

89

0xCA

Yes

MC44CC373CASEF, R2

MC44CC374CAEF, R2

591.25

89

0xCE

0xCA

Yes

No

Yes

871.25

89

0xCA

Yes

No

Yes

MC44CC374T1AEF, R2

1. All orderable parts are in a 16-pin SOIC, with temperature range of 0°C to +70°C ambient. For tape and reel, add the R2 suffix.

2. Refer to application note to obtain 82 dBμV or other RF levels.

This document contains certain information on a new product.

Specifications and information herein are subject to change without notice.

PIN DESCRIPTIONS

16-Pin SOIC Package

SCL

AUX

SDA

GND

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

IN

PLLFLT

LOP

XTAL

No Connect

PREEM

V

CC

RF_OUT

GND

AUDIO

IN

SPLFLT

V

VIDEO

IN

CC

Figure 1. Pin Connections

Table 1. SO16 Package Pin Descriptions

Pin Name

Description

Comments

Number

1

SDA

I²C data

Ground

Bidirectional serial data I/O port for setting configuration. Compatible with

0-5 V and 0-3.3 V I²C-bus.

2

3

GND

LOP

Logical output port

Open collector output. Controlled by a single bit in the control register.

4 MHz crystal.

controlled by I²C bus

4

5

XTAL

PREEMP

AUDIO_IN

SPLFLT

VIDEO_IN

V_CC

Crystal

Pre-emphasis capacitor

Audio input

6

> 20 kΩ input impedance.

7

Sound PLL loop filter

Video input

8

1 Volt peak-to-peak baseband video input

3.3 volt power input.

9

Supply voltage

Ground

10

11

12

13

14

15

16

GND

RF_OUT

V_CC

TV output signal

Supply voltage

No Connection

RF PLL loop filter

Auxiliary Input

I²C clock

A 75 Ω composite video output signal

3.3 Volt power input.

NC

Do not make any connection to this pin.

PLLFLT

AUX_IN

SCL

Subcarrier input for stereo and NICAM applications

Serial control port data clock. Compatible with 0-5 V and 0-3.3 V I²C bus.

MC44CC373

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Freescale Semiconductor

FUNCTIONAL OVERVIEW

Figure 2 shows a simplified block diagram of the

MC44CC373CA and MC44CC374CA modulators.

There are three main sections:

An on-chip simple video test pattern generator with an au-

dio test signal is included, but is not shown in the block dia-

gram.

The MC44CC373/4CA operates as a multi-standard mod-

ulator and can handle the following systems using the same

external circuit components: B/G, I, D/K, L, M/N.

The different orderable part numbers provide: a choice in

the pre-programmed power-up default channel frequency,

the output power level and a pre-programmed secondary I²C

address.

1. A high speed I²C-compatible bus section for control and

programming.

2. A PLL section to synthesize the UHF output channel

frequency.

3. A modulator section, which accepts audio and video

inputs and modulates the RF carrier

VIDEO_IN

SPLLFLT

8

7

Peak

White Clip

MODULATOR

SECTION

Clamp

kHz

V_CC12

31.25/62.5

L/BG

Video

Modulator

AUDIO_IN

PREEM

6

5

Sound

Oscillator

and FM

Sound

PFD

Audio

Amplifier

Modulator

RF_OUT

11

3

V_CC

9

Program

Divider

LPF

ALC

10

GND

FM

AM

LOP

L/BG

RF Sound

Modulator

AM Modulator

AUX_IN

15

13

VCO and PLL SECTION

BUS SECTION

VHF Dividers

NO

CONNECT

XO Prescaler

÷1, 2 or 4

UHF OSC

(2 x F_o)

SCL

SDA

÷2

16

1

High Speed

I²C Bus

Receiver

Program

Divider

÷N11:N0

Ref Divider

128

Prescaler ÷8

Phase

Comp.

XCO

÷

31.25 kHz

4

14

2

GND

PLLFLT

XTAL

(4 MHz)

Figure 2. MC44CC373/374 Simplified Block Diagram

MC44CC373

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3

MODES OF OPERATION AND FUNCTIONAL DESCRIPTION

POWER ON SETTINGS

At power-on, the modulators are configured with pre-programmed default settings as listed in Table 2.

Table 2. Power On Default Settings

Operating Mode

Part Number

Default Values

MC44CC373CA

MC44CC373CAS

MC44CC374CA

MC44CC374T1A

UHF oscillator frequency (MHz)

RF_OUTpower (dBμV)⁽¹⁾

591.25

89

591.25

89

591.25

89

871.25

89

Sound frequency (MHz)

Sound reference frequency (kHz)

Logic Output Port (logic level)

Picture to sound ratio (dB)

Peak White Clip (state)

5.5

31.25

Low

12

31.25

Low

12

31.25

Low

12

31.25

Low

12

On

System Standards

B/G

1. Refer to application note to obtain 82 dBμV or other RF levels.

POWER ON RESET

A power-on reset circuit holds the digital portion in reset

until the power supply has stabilized. Additionally a delay of

approximately 2 seconds allows the crystal oscillator to stabi-

lize before the digital section begins normal operation.

TRANSIENT OUTPUT INHIBIT

CRYSTAL REFERENCE OSCILLATOR

To minimize the risk of interference to other channels while

the UHF PLL is acquiring a lock on the desired frequency, the

Sound and Video modulators are turned OFF during a time

out period in two cases: Power On and UHF oscillator power

On (OSC bit switched from OFF to normal operation). There

is a time out of 262 ms until the output is enabled. This lets

the UHF PLL settle to its programmed frequency.

The reference crystal frequency is 4.0 MHz, the same as

for the legacy modulators.

The reference crystal oscillator if followed by a fixed di-

vide-by-128, resulting in a reference frequency of 31.25 kHz

for the phase detector.

UHF PLL SECTION

The UHF VCO runs at twice the desired RF frequency and

is divided by 2 before it is sent to the divide-by-8 prescaler

and then the programmable divider.

The programmable divider division-ratio is controlled by

the state of control bits N0 to N11 and is the binary number

for the number of 250 kHz steps in the desired RF_OUTfre-

quency. The divider-ratio N for a desired frequency F (in

MHz) is given by:

STANDBY MODES

During standby mode, the modulator is switched to low

power consumption. The sound oscillator, UHF oscillator, and

the video and sound modulator section’s bias are internally

turned OFF. The I²C bus section remains active.

The standby mode is set with a combination of 3 bits:

OSC=1, SO=1 and ATT=1 for MC44CC373/374CAxxx

OSC=0, SO=1 and ATT=1 for MC44CC374T1Axx

Programming of the Frequency Registers or the Optional

Control Registers is not allowed in Standby Mode.

(2 × F) 128

----------------- ---------

N =

×

16

4

with:

SYSTEM L OR B/G SELECTION

The SYSL enable control bit internally switches the follow-

ing functions:

N = 2048 × N11 + 1024 × N10 + …… + 4 × N2 + 2 × N1 + N0

•

SYSL = 0 enables B/G system

— Video modulation polarity: Negative

— Sound modulation: FM

NOTE:

Programming a division-ratio N = 0 is not allowed.

Programming of the N value must be performed while

the modulator is in normal mode, not standby mode.

•

SYSL = 1 enables L system

— Video modulation polarity: Positive

— Sound modulation AM

MC44CC373

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UHF OSCILLATOR-VHF RANGE

VIDEO SECTION - PEAK WHITE CLIP

For VHF range operation, the UHF oscillator can be inter-

nally divided by: 2, 4, 8, or 16. This is accomplished via the

special test mode bits, X2:X0.

The modulators require the following for proper video func-

tionality:

•

A composite video input with negative going sync

pulses

NOTE:

•

A nominal video level of < 1.14 V

The MC44CC373/374 modulators are intended for

UHF operation. Using the digital dividers for VHF

operation will cause additional spurious content in the

RF_OUT. Performance specifications for VHF operation

are not provided. The user must provide external

filtering on RF_OUTto meet their VHF spurious

requirements.

This signal is AC-coupled to the video input where the

sync tip level is clamped.

The video signal is then passed to a Peak White Clip

(PWC) circuit. The PWC circuit function soft-clips the top of

the video waveform, if the sync tip amplitude to peak white

clip goes too high. This avoids carrier over-modulation by the

video.

The Peak White Clip level may be set via the Option Con-

trol Register 2, bits PW1:PW0. Clipping can be disabled by

software via bit PWC in the Control register.

SOUND SECTION

The sound oscillator is fully integrated and does not re-

quire any external components. An internal low-pass filter

and matched structure provide very low harmonics levels.

The sound modulator system consists of an FM modulator

incorporating the sound subcarrier oscillator. An AM modula-

tor is also included in the MC44CC373/374xxxx devices and

is enabled by the SYSL control bit for use in system L appli-

cations. The audio input signal is AC-coupled into the ampli-

fier, which then drives the modulators.

The sound reference divider is programmed by control bit

SRF, resulting in a reference frequency of 31.25 kHz or

62.5 kHz. The sound subcarrier frequency is selected by con-

trol bits SFD1:SFD0. The subcarrier frequencies are 4.5, 5.5,

6.0 or 6.5 MHz. The power-up default value is 5.5 MHz.

A capacitor is connected to the external pin, PREEM, to

set the pre-emphasis time constant for the application. Infor-

mation on the selection of this filter may be found later in this

document under applications information.

TEST PATTERN GENERATOR

The modulators have a simple test pattern generator, that

may be enabled under I²C bus control, to permit a TV receiv-

er to easily tune to the modulator output. The pattern consists

of two white vertical bars on a black background and a 1 kHz

audio test signal.

The video test pattern consists of two signals generated by

the Digital section. One controls the sync pulse circuitry, and

the other controls the luminance circuitry. These signals are

logic levels that drive the video circuitry which creates a com-

posite signal with the proper levels for sync pulses and lumi-

nance as shown in Figure 4.

TE2

7/10

LOGIC OUTPUT PORT (LOP)

The LOP pin controls any logic function. The primary ap-

plications for the LOP are to control an external attenuator or

an external switch, between the antenna input and TV output.

A typical attenuator application with PIN diode is shown in

Figure 3. The LOP pin switches the PIN attenuator depend-

ing on the signal strength of the Antenna Input. This reduces

the risks of intermodulation in certain areas. The LOP can

also be used as an OFF position bypass switch or for other

logic functions in the application.

3/10

TE1

4.75μs

10

20 24 2830

40 44

50

60 64

0

TIMEINµS.

Figure 4. Test Pattern Generator

Vcc

Antenna

Input

TV Out

LOP pin

Figure 3. Typical Attenuator Application with Pin Diode

MC44CC373

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5

ELECTRICAL SPECIFICATIONS

Table 3. Absolute Maximum Ratings

Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to

these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-

maximum-rated conditions is not implied.

Characteristic

Symbol

Min

Max

Units

Supply Voltage

V_CC

V_INI₂_C

V_IN

–0.3

–65

—

+3.6

+5.5

V

I²C Input Voltage (SCL and SDA pins)

Any Other Input Voltage

V_CC+ 0.3

+150

V

Storage Temperature Range

Junction Temperature

T_stg

T_J

°C

+105

Table 4. General Specifications

Characteristic

Symbol

Min

Typ

Max

Units

ESD Protection (Charge Device Model)

ESD Protection (Human Body Model)⁽¹⁾

Latch-Up Immunity

CDM

HBM

LU

500

2000

200

—

V

—

mA

°C/W

Thermal Resistance from Junction to Ambient

R_ΘJA

102

1. JEDEC JESD22-A114D.

Table 5. Recommended Operating Conditions

Characteristic

Symbol

Min

Typ

Max

Units

Supply Voltage

V_CC

I_CC

—

+3.0

65

15

3

+3.3

85

+3.6

98

V

Total supply current (all sections active)

Total standby mode supply current

Test pattern sync pulse width

Sound comparator charge pump current

mA

μS

22

30

4.7

6.5

While locking

When locked

—

1

—

3.9

1

7

1.5

μA

RF comparator charge pump current

—

1.2

1.6

2

mA

Logic Output Port

Saturation voltage at I_OL=2 mA

Leakage current

V_OL

I_OH

—

160

—

300

1

mV

μA

Ambient Temperature

T_A

0

—

+70

°C

NOTE: Crystal specification reference information

Frequency = 4 MHz

Mode = Parallel Resonance

Load Capacitance = 27 pF

Motional Resistance = 10 Ohms Typical (100 Ohms Maximum Starting)

MC44CC373

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PERFORMANCE CHARACTERISTICS

Unless otherwise stated, all performance characteristics

are for:

The parameters listed are based on the type of test condi-

tions found in the column Type.

•

Power Supply, V_CC= 3.3 V

•

A = 100% tested

Ambient Temperature, T_A= 25^oC

Video Input 1.0 V_(pp)10-step grayscale.

RF inputs/outputs into 75 Ω load.

B = 100% Correlation tested

C = Characterized on samples

D = Design parameter

See "Characterization Measurement Conditions" on

page 18 for each C type parameter.

NOTE:

Specifications only valid for envelope demodulation.

Table 6. High Frequency Characteristics

Parameter

Test Conditions⁽¹⁾

Device

Min

Typ

Max

Unit

Type

RF_OUToutput level⁽²⁾

Output signal from modulator

section

MC44CC373CA

MC44CC374CA

MC44CC374T1A

83

89

93

dBμV

B

UHF oscillator frequency

VHF range

460

45

—

880

460

MHz

A

B

UHF oscillator internally

divided

RF_OUToutput attenuation

During transient output inhibit,

or when ATT bit is set to 1.

50

60

—

dBc

B

Sound subcarrier harmonics (Fp+n∗Fs) Reference picture carrier.

—

−63

−54

−65

−40

—

dBc

C

Second harmonic of chroma subcarrier Using red EBU bar.

Chroma/Sound intermodulation:

Using red EBU bar.

—

Fp+ (Fsnd − Fchr)

Out-of-band (UHF picture carrier)

spurious (Fo = 460 - 880MHz)

1/4∗Fo, 1/2∗Fo,

3/4∗Fo, 3/2∗Fo

—

12

30

dBμV

C

Output measured from

40 MHz to 1 GHz.

Fo (picture carrier) harmonics⁽²⁾⁽³⁾

In band spurious (Fo@5MHz)

2nd harmonic

3rd harmonic

—

66

69

74

78

dBμV

C

No video/sound modulation.

—

−65

dBc

1. See Performance Measurement Test Set-ups, Table 9.

2. Refer to application note to obtain 82 dBμV or other RF levels and to reduce picture carrier harmonics.

3. Picture carrier harmonics are highly dependent on PCB layout and decoupling capacitors.

MC44CC373

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7

Table 7. Video Performance Characteristics

Parameter

Test Conditions⁽¹⁾

Min

Typ

Max

Unit

Type

Video bandwidth

Video input level

Reference 0 dB at 100 kHz, measured at 5 MHz.

−0.5

—

0.1

1.0

10

0.5

1.5

dB

V_CVBS

μA

C

D

A

B

75Ω load

Video input current

Video input impedance

Peak White Clip

8

12

75

92

110

97.5

KΩ

Video Modulation depth for video=1.4 V_CVBSat

default (01) PWC level

90.5

94

%

No sound modulation,100% white video.

Using CCIR Rec.567 weighting filter.

53

55

—

dB

C

Video S/N

Differential Phase

Differential Gain

+5

—

−5

deg

%

C

PWC bit set to 0. CCIR Test Line 310, worst of first

4 out of 5 steps.

−5

5

Luma/Sync ratio

Input ratio 7.0:3.0

6.8/3.2

75

—

7.2/2.8

88

—

%

B

PAL video modulation depth

(SYSL = 0)

1.0 Volt Peak-to-Peak input.

83

SECAM video modulation depth

(SYSL = 1)

Gain set to default

90

96

99

%

B

1. See Performance Measurement Test Set-ups, Table 22.

Table 8. Audio Performance Characteristics

Parameter

Test Conditions⁽¹⁾

Min

Typ

Max

Unit

Type

Picture-to-Sound ratio

Audio modulation index

PS bit 0 setting

9

—

19

dB

A

Using specific pre-emphasis circuit,

audio input level=200 mV_rms-audio frequency=1 kHz

AM modulation: SECAM Fs=6.5MHz

76

95

80

86

%

A

FM modulation: Fs=5.5, 6or 6.5MHz

100

104

100% modulation= ±50 kHz FM deviation

FM modulation: NTSC Fs=4.5MHz

100% modulation=±25 kHz FM deviation

95

60

100

71

104

80

%

KΩ

dB

A

Audio input impedance

A

C

Audio Frequency response

Reference 0dB at 1 kHz,

using specified pre-emphasis circuit,

measure from 50 Hz to 15 kHz

−2.5

—

+2.0

Audio Frequency response

No pre-emphasis. Measure from 50 Hz to 50 kHz

±0.5

—

+2.0

1

dB

%

C

Audio Distortion FM (THD only)

At 1 kHz, 100% modulation (±50 kHz).

—

0.5

Pre-emphasis. No video.

Audio Distortion AM (THD only)

Audio S/N with Sync Buzz FM

At 1 kHz, 100% modulation

Pre-emphasis. No video

—

1.5

54

2.5

—

%

C

Ref 1 kHz, 50% modulation (±25 kHz)

EBU color bars Video signal,

50

dB

using CCIR 468.2 weighting filter. Pre-emphasis.

Audio S/N with Sync Buzz AM

Reference 1 kHz, 85% modulation

Video input EBU color bar 75%

Audio BW 40 Hz - 15 kHz

45

50

—

dB

C

Weighting filter CCIR468-2. Pre-emphasis.

Total Harmonic Distortion (THD)

Signal-to-Noise Ratio (SNR)

No Pre-emphasis

—

0.1

—

%

C

No Pre-emphasis. 50 Hz to 50 kHz BW

58

dB

1. See Performance Measurement Test Set-ups, Table 22.

MC44CC373

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8

2

HIGH SPEED I C CONTROL INTERFACE OPERATION

The modulator chip’s digital control interface is compatible

Status data can be read back from the modulator chip. The

output status data is clocked out on the falling edge of SCL

and is valid on the rising edge, with the MSB first.

with the I²C bus standard. The two pins used for the I²C bus

are the clock (SCL) and data (SDA). The data pin is bidirec-

tional.

The I²C interface lines are 5 Volt tolerant. Therefore, they

can be pulled up to 5 Volts, if required, to interface with the

microprocessor in a given application.

IC Device Address

Since the I²C bus is a two-wire bus that does not have a

separate chip-select line, each IC on the bus has a unique

address. This address must be sent each time an IC is com-

municated with. The address is the first seven bits that are

sent to the IC as shown in Table 9. The eighth bit sent is the

R/W bit, it determines whether the master will read from or

write to the IC.

NOTE:

If the MC44CC373/4 modulator is powered down, it

will load the I²C bus by means of leakage current

passing through the stacked ESD protection diodes

on the SCL and SDA pins.

Table 9. IC Address Byte Format

The input control data stream is clocked in on the rising

edge of SCL, with the most significant bit, MSB, first. The sev-

en-bit IC Address and R/W bit are in the first byte sent. This

allows the IC to determine if it is the device that is being com-

municated with. After that, an even number of control data

bytes, 8-bits each, sent to configure the IC. The data stored

in the input control register is loaded into the appropriate de-

vice registers during the acknowledge, ACK, bit time.

The Master controls the clock line, whether writing to the

part or reading from it. After each byte that is sent, the device

that receives it, sends an acknowledge bit back to the master.

After the last data byte and ACK, the master sends a Stop

Condition to terminate the write cycle.

7

6

5

4

3

2

1

0

Read/

Write

IC Address

A6

1

A5

1

A4

0

A3

0

A2

1

A1

X

A0

1

R/W

X

Address bit A1 selects one of two possible addresses. The

chip address is defined by the orderable part number as listed

in Table 10. The RW bit determines if the master is requesting

a read or write. RW = 0 = write and RW = 1 = read.

Table 10. Chip Address by Orderable Part Number

IC Address Byte

Orderable Part Number

A1

RW

Mode

Binary

Hex

0

1

0

1

0

1

Write

Read

Write

Read

1100_1010

1100_1011

1100_1110

1100_1111

0xCA

0xCB

0xCE

0xCF

MC44CC373CA, MC44CC374CA,

MC44CC374T1A

MC44CC373CAS

I²C Write Mode Format

In the write mode, each ninth data bit is an acknowledge

bit (ACK) as shown in Figure 5. During this time, the Master

lets go of the bus, the external pull-up resistor pulls the signal

high and sends a logic 1 and the Modulator circuit (slave) an-

swers on the data line by pulling it low.

set to a logic 0. This allows the frequency or the control infor-

mation to be sent first as shown inn Examples 3,and 4.

The MC44BS373/4 legacy family of RF modulators re-

quired only two words of data (four bytes) for full configura-

tion. The new CMOS devices have two additional (optional)

control words that can be used to access some new features.

These features include changing the output power, using a

different frequency crystal, and adjusting the peak white clip

levels. These new Option Control words do not need to be

sent unless access to these new features is desired. The de-

fault values for these functions will allow the device to work

the same way as the MC44BS373/4 devices did.

Example 5 shows how the new Option Control words are

to be sent. OC1 follows the Control word and OC2 follows

OC1.

Besides the first byte with the chip address, the circuit

needs two or more data bytes for operation.

The programming of the MC44CC37xxxxx devices is sim-

ilar to the legacy devices. That is, they may be programmed

with either two or four data bytes, after the chip address.

Table 11 shows the permitted data bytes, and the order in

which they can be sent, to program the MC44CC373/374 de-

vices. Examples 1 and 2 are the same as the legacy modula-

tors.

The control data bytes all contain an address function bit

(the MSB) which lets the IC distinguish between the frequen-

cy information and control information. If the address function

bit is a logic 1, the following bytes contain control information.

The frequency information has the address function bit that is

Example 6 shows the Frequency word being sent first fol-

lowed by the Control bytes.

MC44CC373

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Freescale Semiconductor

9

The following rules apply for the sequences of data bytes

for incoming (write) information:

always be sent after the C1,C0 control data without a

stop condition in between.

•

If an odd number of data bytes are received, the last

one is ignored.

•

The optional control register two, most significant and

least significant bytes, OC2M, OC2L, data must be

sent directly after the OC1M, OC1L data without a

stop condition in between.

•

If nine data bytes are received, the ninth and following

ones are ignored, and the last ACK pulse is sent at the

end of the eighth data byte.

The Control and Frequency information may be sent

as separate I2C write sequences. (Example 1 or

Example 5 followed/preceeded by Example 2).

•

The optional control register one, most significant and

least significant bytes, OC1M, OC1L, data must

Table 11. MC44CC373/4 Programming Sequence (Incoming Information)

Legacy Devices Data Bytes

Example 1

Example 2

Example 3

Example 4

STA

CA

C1

FM

C1

FM

C0

FL

C0

FL

STO

FM

FL

C0

STO

C1

MC44CC37xxxxxx Devices using the Option Control Bytes

Example 5

Example 6

STA

CA

C1

C0

FL

OC1M

C1

OC1L

C0

OC2M

OC1M

OC2L

OC1L

STO

FM

OC2M

OC2L

STO

Abbreviations:

STA = Start condition

CA = Chip Address

FM = Frequency information, most significant (high order) bits

FL = Frequency information, least significant (low order) bits

C1 = Control information, most significant (high order) bits

CO = Control information, least significant (low order) bits

OC1M = Optional Control 1 information, most significant (high order) bits

OC1L= Optional Control 1 information, least significant (low order) bits

OC2M = Optional Control 2 information, most significant (high order) bits

OC2L = Optional Control 2 information, least significant (low order) bits

STO = Stop condition

I²C Read Mode Format

To read back the status data, the read address shown in

Table 10 is sent by the master. The modulator then responds

with an ACK followed by a byte containing status information

on the RF oscillator out-of-frequency range.

MC44CC373

Digital Home

Freescale Semiconductor

10

2

I C BIT MAPPING SUMMARY

WRITE MODE

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ACK

see

Table 9

CA-CHIP ADDRESS

1

0

1

0

ACK

FM-High Order Bits

FL-Low Order Bits

0

N5

1

TPEN

N4

AUX

OSC

0

N11

N3

SO

ATT

0

N10

N2

LOP

SFD1

0

N9

N1

PS

SFD0

0

N8

N0

X3

SREF

0

N7

X1

X2

X5

0

N6

X0

SYSL

X4

ACK

C1-High Order Bits

C0-Low Order Bits

PWC

1

OC1M-High Order Bits

OC1L-Low Order Bits

OC2M-High Order Bits

OC2L-Low Order Bits

0

1

0

PW1

PW0

READ MODE

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ACK

see

Table 9

CHIP ADDRESS

R-Status Byte

1

0

1

ACK

—

Y2

Y1

OOR

Bit Name

Description

AUX

ATT

Auxiliary sound input enable/disable.

Modulator output attenuated-sound and video modulators ON/OFF

Logic Output Port

LOP

N0…N11

OSC

UHF frequency programming bits, in steps of 250 kHz

UHF oscillator ON/OFF

OOR

RF oscillator out-of-frequency range information

Picture-to-sound carrier ratio

PS

PWC

Peak White Clip enable/disable

SFD0, 1

PW0, PW1

SO

Sound subcarrier frequency control bits

Peak White Clip Level. (see Table 20)

Sound Oscillator ON/OFF

SREF

SYSL

TPEN

X5…X0

Y1, Y2

Sound PLL Reference frequency

System L enable-selects AM sound and positive video modulation. (MC44CC373/374xxxx only)

Test pattern enable-picture and sound

Test mode bits-All bits are 0 for normal operation. (see Table 18)

RF oscillator operating range information

MC44CC373

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Freescale Semiconductor

11

2

I C PROGRAMMING SUMMARY TABLES

Sound

UHF

SFD1 SFD0

Sound Subcarrier Freq (MHz)

OSC

UHF Oscillator

0

1

0

1

0

1

4.5

5.5

6.0

6.5

MC44CC373/

374CAxxx

MC44CC374T1Axx

0

1

Normal operation.

UHF oscillator disabled.

Normal operation.

UHF oscillator disabled.

When UHF oscillator is disabled, do not program the

frequency register N; also writing to Option Control Registers

1 and 2 is not allowed.

PS

Picture-to-Sound Ratio (dB)

0

1

12

16

ATT

Modulator Output Attenuation

SO

Sound Oscillator

0

1

Normal operation

0

1

Sound oscillator ON (Normal mode)

Modulator output attenuation (sound and video

modulators sections bias turned OFF.

Sound oscillation disabled (oscillator and PLL section

bias turned OFF)

AUX

Auxiliary Audio Input

Sound PLL

SREF

0

1

AUX input disabled (normal mode)

AUX input enabled

Description

0

1

Sound Reference frequency = 31.25 kHz

Sound Reference frequency = 62.5 kHz

Video

SYSL

System L/BG Selection

Standby Mode

SYSL only applies to MC44CC373/374xxxx

OSC

SO ATT

Combination of 3-bits

0

1

System B/G enabled, System L disabled (FM sound and

negative video modulation)

1

Modulator standby mode

(MC44CC373/374CAxx)

System L enabled, System B/G disabled (AM sound and

positive video modulation)

0

1

Modulator standby mode

(MC44CC374T1Axx)

PWC

Peak White Clip

Do not program the frequency register N value and Optional Control

Registers during standby mode.

0

1

Peak White Clip ON (System B/G)

Peak White Clip OFF (System L)

Logic Output Port

PW1

PW0

Peak White Clip Level

0

1

0

1

LOP

Description

0

1.0 Volt - Default

0

1

Pin 3 is low voltage

Pin 3 is high impedance

1

TPEN

Test Pattern Signal

0

1

Test pattern signal OFF (normal operation)

Test pattern signal ON (picture and sound)

MC44CC373

Digital Home

12

Freescale Semiconductor

2

INTER-IC (I C) INTERFACE TIMING

Master Writes to Slave

MSB

IC Address R/W

LSB

Byte 2

Byte 1

Additional Control Bytes

S

P

S

Slave

Ack

Slave

Ack

Slave

Ack

Slave

Ack

SDA

SCL

AD7 AD1

0

R15 R8

R7 R0

R15 R8

R7

t_BUF

t_HD;STA

t_f

t_HIGH

t_LOW

t_SU;STO

t_HD;DAT

Start

Condition

Stop

Condition

t_SU;DAT

t_r

Sample

Input

Master Reads from Slave

MSB

IC Address R/W

LSB

Status Byte

S

P

Slave

Ack

D7

SDA

SCL

AD7 AD1

1

D6 D5 D4 D3 D2 D1 D0

Master

Not Ack

t_SP

Start

Condition

Stop

Condition

Figure 5. I²C Timing Diagram

Table 12. I²C Interface Bus Specifications

Parameter

Symbol

Min.

Max.

Units

Low Level Output Voltage

High Level Input Voltage

V_OL

V_IH

0

0.7V_CC

−0.5

—

0.4

V

V_CCmax+0.5

Low Level Input Voltage

V_IL

0.3 V_CC

5.5

—

V

Absolute Max Input Voltage

Hysteresis of Schmitt trigger inputs

Capacitance for each I/O pin⁽¹⁾

Pulse width of spikes filtered out

SCL Frequency

—

V

V_hys

C_IN

0.05V_CC

—

V

10

pF

nS

kHz

nS

uS

nS

t_SP

0

50

f_SCLK

t_HD;STA

t_SU;STA

t_SU;DAT

t_HD;DAT

t_SU;STO

t_LOW

t_HIGH

t_r

0

800

—

Hold time Start condition

500

Set-up time for repeated start

Data Set-up time

500

—

100

—

Data Hold time

0

—

Set-up time for Stop condition

Low period of the SCL clock

High period of the SCL clock

Rise time of both SDA and SCL

Fall time of both SDA and SCL

Bus free time between Stop and Start

500

—

0.6

—

0.6

—

20+ 0.1C_b

200

300

—

t_f

t_BUF

1. C_b= total capacitance of one bus line in pF.

MC44CC373

Digital Home

Freescale Semiconductor

13

CONTROL AND DATA REGISTER - DEFINITIONS

The legacy MC44BS373/4 modulators had two 16-bit con-

these bits when upgrading a legacy system with the new

trol registers (Control and Frequency) and one data/status

register. The new MC44CC373/374 family has the same reg-

ister configuration and may be programmed with the same

program software as the legacy devices. This backward com-

patibility allows a faster migration to new product redesigns.

There are some additional control features that may be used

in new designs. However, it is not necessary to program

modulator family.

CONTROL REGISTER FORMAT

The control register format is shown in Figure 6 and the

descriptions for the High-order and Low-order bits (bytes) are

listed in Table 13 and Table 14 respectively.

MSB

LSB

R15

1

R14

0

R13

0

R12

0

R11

0

R10

0

R9

0

R8

0

R7

0

R6

0

R5

0

R4

0

R3

1

R2

0

R1

0

R0

0

Reset

State

1

AUX

SO

LOP

PS

X3

X2

SYSL PWC OSC

ATT SFD1 SFD0 SREF

X5

X4

Adr

TEST MODE

Figure 6. Control Register Format

Table 13. Control Register (High-order) Bit Description Table 14. Control Register (Low-order) Bit Description

Bit Name

Description

Bit Name

Description

15

Adr

Address Function bit. Must be set to a logic 1.

Gates the AUX_INpin

Peak White Clip enable/disable

7

6

PWC

OSC

0

1

Peak White Clip on (system B/G).

Peak White Clip off (system L).

14

AUX

0

1

Disable AUX_INpin.

Enable AUX_INpin.

UHF oscillator On/Off

Sound Oscillator On/Off

MC44CC373/ MC44CC374T1Axx

374CAxxx

0

1

Sound oscillator is on (normal mode).

13

SO

0

1

Normal

operation.

UHF oscillator disabled.

Sound oscillator is disabled (osc and PLL

section bias is turned off).

UHF oscillator Normal operation.

disabled.

Logic Output Port

12

11

LOP

PS

0

1

LOP pin is low voltage.

LOP pin is high impedance.

Modulator output attenuated.

0

1

Normal operation.

5

ATT

Picture-to-sound carrier ratio

Modulator output attenuation (sound and

video modulator sections bias is turned off).

0

1

Picture-to-sound carrier ratio is 12 dB.

Picture-to-sound carrier ratio is 16 dB.

Sound subcarrier frequency control bits.

SFD1 SFD0

Frequency

4

3

2

SFD1

SFD0

SREF

Test Mode bits, must be set to logic 0 for normal

operation.

10

9

X3

X2

0

1

0

1

0

1

4.5 MHz

5.5 MHz

6.0 MHz

6.5 MHz

Test Mode bit. May be used for VHF divider

System L Enable - Selects AM sound and positive

video modulation. (Applies to MC44CC373xxx

devices only. For the MC44CC374xxx devices this

bit is set to 0 and may not be modified).

Sound PLL reference frequency

8

SYSL

0

System B/G enabled (FM sound and

negative video modulation).

0

1

Sound reference frequency = 31.25 kHz

Sound reference frequency = 62.5 kHz

1

System L enabled (AM sound and positive

video modulation).

1

0

X5

X4

Test Mode bits, must be set to logic 0 for normal

operation.

MC44CC373

Digital Home

14

Freescale Semiconductor

FREQUENCY REGISTER FORMAT

The format for the frequency register is shown in Figure 7.

The descriptions for the High-order and Low-order bits

(bytes) are listed in Table 15 and Table 16 respectively.

MSB

LSB

R15

0

R14

0

R13

R12

N10

R11

N9

R10

See Table 17 for the default (reset) value.

N8 N7 N6 N5 N4 N3

R9

R8

R7

R6

R5

R4

N2

R3

N1

R2

N0

R1

0

R0

Reset

State

0

TPEN N11

X1

X0

Adr

Test

Ptrn

TEST MODE

N Counter

Figure 7. Frequency Register Format

Table 15. Frequency Register (High-order) Bit Descrip-

tion

Table 16. Frequency Register (Low-order) Bit Descrip-

tion

Bit Name

Description

Bit Name

Description

15

Adr

Address Function bit. Must be set to a logic 0.

Test Pattern Enable.

7

6

5

4

3

2

1

0

N5

N4

N3

N2

N1

N0

X5

X4

14 TPEN

0

1

Test pattern signal off (normal operation).

Test pattern signal on (picture and sound).

N Counter program bits, N5:N0.

13

12

11

10

9

N11

N10

N9

Test Mode bits, must be set to logic 0 for normal

operation. May be used for VHF divider.

N Counter program bits, N11:N6.

N8

N7

8

N6

The N Counter bits determine what UHF frequency is

used. N11:N0 is the binary number of 250 kHz steps in the

desired RF_OUTfrequency F. With:

NOTE:

Programming a division-ratio N = 0 is not allowed.

At power up the modulator will assume a default value for

the N Counter. The default is determined at time of manufac-

ture and is listed in Table 17 by the orderable part number.

N = 2048 × N11 + 1024 × N10 + …… + 4 × N2 + 2 × N1 + N0

Table 17. Power-On Default Values for N Counter by Orderable Part Number

N Counter Value

Orderable Part Number

Frequency

591.25

Decimal

Hex

Binary

MC44CC373CAEF, MC44CC373CASEF,

MC44CC374CAEF

2365

0x93D

1001 0011 1101

MC44CC374T1AEF

871.25

3485

0xD9D

1101 1001 1101

MC44CC373

Digital Home

Freescale Semiconductor

15

The Test Mode bits, X5:X0, found in the frequency and

control registers, control 15 different test mode states. Only

four of these states have an application use. All other states

are intended for manufacturing test purposes only.

The test mode states defined by X2:X0 in Table 18 may be

used to operate the modulator in the in VHF range.

It should be noted that operation in the VHF range has

a high spurious content due to the digital dividers.

Filtering of the RF_OUTsignal may be required to meet

desired performance specifications. Performance

data is not provided for VHF operation.

Table 18. Test Modes usable for VHF operation

X5

0

X4

0

X3

0

X2

0

X1

0

X0

0

Description

Normal Operation

0

1

RF/2

0

1

0

RF4

0

1

RF/8

0

1

0

RF/16

x

1

x

The 11 other test mode states are reserved for manufacturing test purposes.

OPTION CONTROL REGISTER 1 FORMAT

The format for the Optional Control Register 1, OCR1, is

shown in Figure 8. Bits R14:R0 are not defined for system

applications. They are for manufacturing test only. For nor-

mal operation these bits must be set to a logic 0. When

UHF oscillator is disabled, do not write to Option Control Reg-

ister 1 and 2. Any other time, writing to Option Control Regis-

ters 1 and 2 is allowed.

MSB

LSB

R15

1

R14

0

R13

0

R12

0

R11

0

R10

0

R9

0

R8

0

R7

0

R6

0

R5

0

R4

0

R3

0

R2

0

R1

0

R0

0

Reset

State

1

Reserved for manufacturing test purposes only

Adr

Figure 8. Option Control Register 1 Format

Table 19. Option Control Register 1, Bit Description

Bit

Name

Description

15

14-8

7-0

Adr

—

Address Function bit. Must be set to a logic 1.

Reserved for manufacturing test.

—

Reserved for manufacturing test.

MC44CC373

Digital Home

16

Freescale Semiconductor

OPTION CONTROL REGISTER 2 FORMAT

applications. They are for manufacturing test only. For nor-

mal operation these bits must be set as defined by the re-

set state.

The format for the Optional Control Register 2, OCR2, is

shown in Figure 9. Bits R14:R2 are not defined for system

MSB

LSB

R15

1

R14

0

R13

0

R12

0

R11

0

R10

0

R9

0

R8

0

R7

0

R6

0

R5

0

R4

0

R3

0

R2

1

R1

0

R0

1

Reset

State

1

Reserved for manufacturing test purposes only

PW1 PW0

Adr

Peak White

clip level

Figure 9. Option Control Register 2 Format

Table 20. Option Control Register 2, Bit Description

The Peak White Clip level may be set by setting bit PW1

and PW0 as listed in Table 20. The default (power-up) setting

is 1.0 volts.

Bit Name

Description

When UHF oscillator is disabled, do not write to Option

Control Registers 1 and 2. Any other time, writing to Option

Control Registers 1 and 2 is allowed.

15

Adr

—

Address Function bit. Must be set to a logic 1.

Reserved for manufacturing test.

Peak White Clip level

14-2

PW1 PW0

Video Modulation Depth

for video = 1.4 VCVBS

1

0

PW1

PW0

0

1

0

1

0

1

90%

94%

91%

92.5%

Table 21. Status Byte Bit Description

DATA/STATUS REGISTER FORMAT

The data/status read back format is shown in Figure 10.

The first byte contains the status information on the RF oscil-

lator out-of-frequency range and is the same format used by

the legacy devices. Therefore, current legacy software will be

unaffected as it will only read back this most significant byte.

During manufacturing test, additional two byte registers

are read back without sending a stop condition. This read

back data has no significance to end system applications.

Therefore if it is read by a master, it should be ignored.

The bit description for the status byte is listed in Table 21.

Bit

Name

Description

R7:R3

-

Reserved

Frequency Too High / Too Low

0

VCO out of range, frequency too

low, only valid if OOR=1

R2

Y1

1

VCO out of range, frequency too

high, only valid if OOR=1

Low/High VCO Active

R1

R0

Y2

0

1

High VCO is active

Low VCO is active

MSB

LSB

UHF Osc Out of Freq. Range

R7

-

R6

-

R5

R4

-

R3

-

R2

Y2

R1

Y1

R0

OOR

0

1

Normal operation, VCO in range

VCO out of range

-

OOR

Reserved

OSC Status

Figure 10. Status/Data Register Format

MC44CC373

Digital Home

Freescale Semiconductor

17

CHARACTERIZATION MEASUREMENT CONDITIONS

The default configuration unless otherwise specified:

•

Picture-to-sound carrier ratio = 12 dB

•

Peak White Clip enabled

System L disabled

UHF oscillator ON

Test pattern disabled

Sound and video modulators ON

Sound subcarrier frequency = 5.5 MHz

Sound Oscillator ON

All test mode bits are ‘0’

Frequency from channel 21 to 69

RF Inputs / Output into 75Ω Load using a 75 to 50 Ω

transformation.

Sound PLL reference frequency = 31.25 kHz

Logic Output Port LOW

•

Video Input 1Vpp.

Audio pre-emphasis circuit enabled.

Table 22. Performance Measurement Test Set-ups

Device and Signals Set-up

Measurement Set-up

RF_OUTOutput Level

Video: 10 steps grey scale

No audio

Measured picture carrier in dBμV with a Spectrum Analyzer using a 75 to 50 Ω

transformation, all cables losses and transformation pads having been

calibrated.

Measurement used as a reference for other tests: RFout_Ref

RF_OUTOutput Attenuation

ATT bit = 1

Measure in dBc picture carrier at ATT=1 with reference to picture carrier at

ATT=0

No Video signal

No Audio signal

Sound Subcarrier Harmonics

Video: 10 steps grey scale

No Audio signal

Measure in dBc second and third sound harmonics levels in reference to

picture carrier (RFout_Ref).

Picture carrier

Sound carrier

Sound

2nd harm

Sound

3rd harm

Fo

+5.5MHz +11MHz +16.5MHz

Second Harmonics of Chroma Subcarrier

No audio

Measure in dBc, in reference to picture carrier (RFout_Ref), second harmonic

of chroma at channel frequency plus 2 times chroma frequency, resulting in the

following spectrum.

Video: a 700m V_(PP)4.43 MHz sinusoidal

signal is inserted on the black level of active

video area.

Picture carrier

Sound

carrier

Chroma

carrier

Chroma 2nd

Harmonic

Frequency

4.43 MHz

700 mV

pp

Fo

+4.43MHz +5.5MHz

+8.86MHz

MC44CC373

Digital Home

Freescale Semiconductor

18

Table 22. Performance Measurement Test Set-ups (continued)

Device and Signals Set-up

Measurement Set-up

Chroma/Sound Intermodulation

No audio signal

Measure in dBc, in reference to picture carrier (RFout_Ref), intermodulation

product at channel frequency plus the sound carrier frequency (+5.5 MHz)

minus the chroma frequency (−4.43 MHz), resulting in the following spectrum.

Video: 700 mV_(PP)4.43 MHz sinusoidal signal

inserted on the black level of active video

area.This is generated using a Video

Generator and inserting the required

frequency from a RF Signal generator.

Intermodulation product is at the channel frequency +1.07 MHz.

Picture carrier

Sound

Chroma

carrier

Frequency

4.43 MHz

Chroma/Sound

Intermod.

700 mV

pp

+1.07MHz

+4.43MHz +5.5MHz

Fo

Picture Carrier Harmonics

No Video signal

No Audio signal

Measure in dBc, in reference to picture carrier (RFout_Ref), second and third

harmonic of channel frequency, resulting in the following spectrum.

Picture carrier

3rd harmonic

2nd harmonic

Fo

2Fo

3Fo

Out of Band Spurious

No Video signal

No Audio signal

Measure in dBμV spurious levels at 0.25, 0.5, 0.75 and 1.5 times channel

frequency, resulting in the following spectrum

Measure from 40 MHz to 1 GHz (Fo = 460 - 880 MHz).

Picture carrier

Spurious

Fo/4

Fo/2 Fo*3/4

Fo

Fo*3/2

MC44CC373

Digital Home

Freescale Semiconductor

19

Table 22. Performance Measurement Test Set-ups (continued)

Device and Signals Set-up

Measurement Set-up

In Band Spurious

No Video signal

No Audio signal

Measure in dBc, in reference to picture carrier (RFout_Ref), spurious levels

falling into video bandwidth starting from ±100 kHz from the picture carrier up

to ±5 MHz.

Video Bandwidth

No audio

The Video signal is demodulated on the spectrum analyzer, and the peak level

of the 100 kHz signal is measured as a reference. The frequency is then swept

from 100 kHz to 5 MHz, and then the difference in dB from the 100 kHz

reference level is measured.

Video: 600m V_(PP)sinusoidal signal inserted

on the black level of active video area.

Weighted Video Signal to Noise

Video: 100% White video signal - 1 V_(PP)

No Audio signal

.

The Video Analyzer measures the ratio between the amplitude of the active

area of the video signal (700mV) and the noise level in Vrms on a video black

level which is show below.

This is measured using a Demodulator in B/G

(using a CCIR Rec. 567 weighting network,

100 kHz to 5 MHz band with sound trap and

envelope detection, and a Video Analyzer.

Video S/N is calculated as 20 x log(700 /N) in dB.

N

noise level in V

rms

Unweighted Video Signal to Noise

Same as above.

Same as above with CCIR filter disabled.

Video Differential Phase

Video: 5 step Grey Scale- 1 V_(PP)

No Audio signal

.

On line CCIR 330, the video analyzer DP measure consists of calculating the

difference of the Chroma phase at the black level and the different chroma

subcarrier phase angles at each step of the greyscale. The largest positive or

negative difference indicates the distortion.

This is measured using a Demodulator in B/G

(using a CCIR Rec. 567 weighting network,

100 kHz to 5 MHz band with sound trap, and

envelope detection, and a Analyzer.

the largest positive or negative difference

DIFF PHASE =

* 100%

the phase at position 0

The video analyzer method takes the worst step from the first 4 steps.

MC44CC373

Digital Home

Freescale Semiconductor

20

Table 22. Performance Measurement Test Set-ups (continued)

Device and Signals Set-up

Measurement Set-up

Video Differential Gain

Video: 5 step Grey Scale- 1 V_(PP)

.

On line CCIR 330 shown below, the video analyzer DG measure consists of

calculating the difference of the Chroma amplitude at the black level and the

different amplitudes at each step of the greyscale. The largest positive or

negative difference indicates the distortion.

No Audio signal

This is measured using a Demodulator in B/G

(using a CCIR Rec. 567 weighting network,

100 kHz to 5 MHz band with sound trap and

envelope detection, and a Video Analyzer.

0

1 2 3 4 5

5-step greyscale with Chroma, line CCIR330

the largest positive or negative difference

DIFF GAIN

=

* 100%

the amplitude at position 0

The video analyzer method takes the worst step from the first 4 steps.

Video Modulation Depth

No Audio signal

This is measured using a Spectrum Analyzer with a TV Trigger option, allowing

demodulation and triggering on any specified TV Line. The analyzer is centred

on the maximum peak of the Video signal and reduced to zero Hertz span in

Linear mode to demodulate the Video carrier.

Video: 10 step grey scale

A (mV)

B (mV)

TV Line Demodulated by Spectrum Analyzer-BG standard

The Modulation Depth is calculated as (A − B) / A x 100 in %

Same measurement method for L standard, with inverted video.

Picture to Sound ratio

No Video signal

Measure in dBc sound carrier in reference to picture carrier (RFout_Ref) for PS

bit = 0 (PS = 12 dB typical) and for PS bit = 1 (PS = 16dB).

No Audio Signal

PS bit set to 0 and 1

Picture carrier

Sound carrier

Fo

+5.5Mhz

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21

Table 22. Performance Measurement Test Set-ups (continued)

Device and Signals Set-up

Measurement Set-up

Audio Modulation Index - FM Modulation

Video: Black Sync

The audio signal 205 mV at 1 kHz is supplied by the Audio Analyzer, and the

FM demodulated signal deviation is indicated on the Demodulator in kHz peak.

Audio signal: 1 kHz, 205 mV_rms

.

This value is then converted in % of FM deviation, based on specified

standards.

This is measured using a Demodulator in B/G

and an Audio Analyzer at 1 kHz

Audio Frequency Response

Video: Black Sync

The audio signal 1 kHz 100 mV_rmsis supplied by the Audio Analyzer,

demodulated by the Demodulator and the audio analyzer measures the AC

amplitude of this demodulated audio signal: this value is taken as a reference

(0 dB).

The audio signal is then swept from 50 Hz to 15 kHz, and demodulated AC

amplitude is measured in dB relative to the 1 kHz reference.

Audio signal: 50 Hz to 15 kHz, 100 mV_rms

This is measured using a Demodulator in B/G

and an Audio Analyzer.

Audio pre-emphasis and de-emphasis circuits are engaged, all audio analyzer

filters are switched OFF.

Audio Distortion FM

Audio: 1 kHz, adjustable level

Video: Black Sync

The input arms detector of the Audio Analyzer converts the ac level of the

combined signal + noise + distortion to dc. It then removes the fundamental

signal (1 kHz) after having measured the frequency. The output rms detector

converts the residual noise + distortion to dc. The dc voltmeter measures both

dc signals and calculates the ratio in% of the two signals.

This is measured using a UHF Demodulator in

B/G and an Audio Analyzer at 1 kHz. The

output level of the audio analyzer is varied to

obtain a deviation of 50 kHz indicated on the

Demodulator.

ADist = (Distortion + Noise) ⁄ (Distortion + Noise + Signal)

Audio Signal to Noise

Audio: 1 kHz, adjustable level

Video: EBU Color Bars

The Audio Analyzer alternately turns ON and OFF its internal audio source to

make a measure of the Audio signal plus noise and then another measure of

only the noise.

This is measured using a Demodulator in B/G

and an Audio Analyzer at 1 kHz. The output

level of the Audio analyzer is varied to obtain

a Modulation Deviation of 25 kHz indicated on

the Demodulator.

The measurement is made using the internal CCIR468-2 Filter of the Audio

Analyzer together with the internal 30 +/−2 kHz (60 dB/decade) Lowpass

filters.

The demodulator uses a quasi-parallel demodulation as is the case in a normal

TV set. In this mode the Nyquist filter is bypassed and the video carrier is used

without added delay to effectuate intercarrier conversion. In this mode the

phase noise information fully cancels out and the true S/N can be measured.

ASN(dB) = 20 × log(Signal + Noise) ⁄ (Noise)

MC44CC373

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22

Freescale Semiconductor

PIN CIRCUIT SCHEMATICS

V

CC

V

CC

V

CC

Pin 8: VIDEO_IN

500

10K

Pin 1: SDA

V

CC

V

CC

75

V

CC

Pin 11: RF Output

8K

Pin 3: LOP

V

CC

Pin 14: PLLFLT

Pin 4: XTAL

V

CC

V

CC

Pin 15: AUX_IN

Pin 5: PREM

10k

audio

11.8k

V

CC

V

CC

V

CC

50k

Pin 16: SCL

Pin 6: AUDIO_IN

V

CC

Pin 7: SPLLFLT

Figure 11. Pin Circuit Schematics

MC44CC373

23

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Freescale Semiconductor

EVALUATION BOARD SCHEMATIC

2

Figure 12. Evaluation Board Schematic

MC44CC373

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Freescale Semiconductor

PACKAGE DIMENSIONS

Figure 13. SOIC-16 Package Dimensions

MC44CC373

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Freescale Semiconductor

Figure 14. SOIC-16 Package Dimensions - continued

MC44CC373

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26

PRODUCT DOCUMENTATION

Refer to the following documents to aid your design process.

Application Notes

To be updated.

•

MC44CC373

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27

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How to Reach Us:

Home Page:

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Information in this document is provided solely to enable system and software

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Freescale Semiconductor reserves the right to make changes without further notice to

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Freescale Semiconductor assume any liability arising out of the application or use of any

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MC44CC373

Rev 3.2

04/2009


型号：	MC44BS374T1AD
厂家：	Freescale
描述：	CMOS Audio/Video RF Modulators CMOS音频/视频射频调制器射频调制器商用集成电路光电二极管信息通信管理
文件：	总28页 (文件大小：429K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC44BS374T1AD [FREESCALE]

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