MC56F8025E_技术文档

Document Number: MC56F8025PB

Rev. 0, 09/2006

Freescale Semiconductor

Product Brief

56F8025 Digital Signal Controller

Product Brief

Contents

1

56F8025 Description

1

2

3

4

5

6

7

56F8025 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Digital Signal Controller Core . . . . . . . . . . . . . . . . . . . . . 3

Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Peripheral Circuits for 56F8025. . . . . . . . . . . . . . . . . . . . 3

Recommended Operating Conditions . . . . . . . . . . . . . . . 5

Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . 6

56F8025 Package and Pin-Out . . . . . . . . . . . . . . . . . . . . 7

The 56F8025 is a member of the 56800E core-based

family of Digital Signal Controllers (DSCs). It

combines, on a single chip, the processing power of a

DSP and the functionality of a microcontroller with a

flexible set of peripherals to create an extremely

cost-effective solution. Because of its low cost,

configuration flexibility, and compact program code, the

56F8025 is well-suited for many applications. The

56F8025 includes many peripherals that are especially

useful for industrial control, motion control, home

appliances, general-purpose inverters, smart sensors, fire

and security systems, switched-mode power supply,

power management, and medical monitoring

applications.

The 56800E core is based on a dual Harvard-style

architecture consisting of three execution units operating

in parallel, allowing as many as six operations per

instruction cycle. The MCU-style programming model

and optimized instruction set allow straightforward

generation of efficient, compact DSP and control code.

The instruction set is also highly efficient for C

compilers to enable rapid development of optimized

control applications.

• Preliminary—Subject to Change Without Notice

56F8025 Description

The 56F8025 supports program execution from internal memories. Two data operands can be accessed

from the on-chip data RAM per instruction cycle. The 56F8025 also offers up to 35 General-Purpose

Input/Output (GPIO) lines, depending on peripheral configuration.

The 56F8025 Digital Signal Controller includes 32KB of Program Flash and 4KB of Unified

Data/Program RAM. Program Flash memory can be independently bulk erased or erased in pages.

Program Flash page erase size is 512 Bytes (256 Words).

A full set of programmable peripherals — PWM, ADCs, QSCI, QSPI, I2C, PIT, Quad Timers, DACs, and

analog comparators — supports various applications. Each peripheral can be independently shut down to

save power. Any pin in these peripherals can also be used as General Purpose Input/Outputs (GPIOs).

RESET or

GPIOA

V

2

V

2

V

SSA

CAP

DD

SS_IO

DDA

4

3

JTAG/EOnCE

Port or

GPIOD

Digital Reg

Low-Voltage

Supervisor

Analog Reg

PWM

or TMRA or CMP

or GPIOA

11

16-Bit

56800E Core

Data ALU

Program Controller

and Hardware

Looping Unit

Address

Generation Unit

Bit

Manipulation

Unit

16 x 16 + 36 -> 36-Bit MAC

Three 16-bit Input Registers

Four 36-bit Accumulators

DAC

AD0

PAB

PDB

CDBR

CDBW

4

Memory

R/W Control

ADC

or CMP

XDB2

XAB1

XAB2

Program Memory

16K x 16 Flash

or GPIOC

System Bus

Control

AD1

PAB

Unified Data /

Program RAM

2K x 16

PDB

CDBR

CDBW

Programmable

Interval

Timer

IPBus Bridge (IPBB)

QSCI

QSPI

or PWM

2

or PWM

I C

2

or I C

2

or I C

or CMP

or GPIOB

XTAL, CLKIN, or

GPIOD

P

or TMRA

or GPIOB

System

Integration

Module

or TMRA

or GPIOB

Interrupt

Controller

COP/

Watchdog

O

S

C

Clock

Generator*

R

EXTAL or GPIOD

*Includes On-Chip

Relaxation Oscillator

2

4

3

Figure 1. 56F8025 Block Diagram

56F8025 Digital Signal Controller Product Brief, Rev. 0

Preliminary—Subject to Change Without Notice

2

Freescale Semiconductor

Digital Signal Controller Core

2

Digital Signal Controller Core

Efficient 16-bit 56800E family Digital Signal Controller (DSC) engine with dual Harvard

architecture

•

As many as 32 Million Instructions Per Second (MIPS) at 32MHz core frequency

Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)

Four 36-bit accumulators, including extension bits

32-bit arithmetic and logic multi-bit shifter

Parallel instruction set with unique DSP addressing modes

Hardware DO and REP loops

Three internal address buses

Four internal data buses

Instruction set supports both DSP and controller functions

Controller-style addressing modes and instructions for compact code

Efficient C compiler and local variable support

Software subroutine and interrupt stack with depth limited only by memory

JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent

real-time debugging

3

4

Memory

•

Dual Harvard architecture permits as many as three simultaneous accesses to program and data

memory

Flash security and protection that prevent unauthorized users from gaining access to the internal

Flash

On-chip memory

— 32KB of Program Flash

— 4KB of Unified Data/Program RAM

EEPROM emulation capability using Flash

•

Peripheral Circuits for 56F8025

One multi-function six-output Pulse Width Modulator (PWM) module

— Up to 96MHz PWM operating clock

— 15 bits of resolution

— Center-aligned and edge-aligned PWM signal mode

— Four programmable fault inputs with programmable digital filter

— Double-buffered PWM registers

— Each complementary PWM signal pair allows selection of a PWM supply source from:

– PWM generator

– External GPIO

– Internal timers

– Analog comparator outputs

– ADC conversion result which compares with values of ADC high- and low-limit registers

to set PWM output

56F8025 Digital Signal Controller Product Brief, Rev. 0

Freescale Semiconductor

3

Preliminary—Subject to Change Without Notice

Peripheral Circuits for 56F8025

•

Two independent 12-bit Analog-to-Digital Converters (ADCs)

— 2 x 4 channel inputs

— Supports both simultaneous and sequential conversions

— ADC conversions can be synchronized by both PWM and timer modules

— Sampling rate up to 2.67MSPS

— 16-word result buffer registers

•

Two internal 12-bit Digital-to-Analog Converters (DACs)

— 2 microsecond settling time when output swing from rail to rail

— Automatic waveform generation generates square, triangle and sawtooth waveforms with

programmable period, update rate, and range

One 16-bit multi-purpose Quad Timer module (TMR)

— Up to 96MHz operating clock

— Eight independent 16-bit counter/timers with cascading capability

— Each timer has capture and compare capability

— Up to 12 operating modes

•

One Queued Serial Communication Interface (QSCI) with LIN Slave functionality

— Full-duplex or single-wire operation

— Two receiver wake-up methods:

– Idle line

– Address mark

— Four-bytes-deep FIFOs are available on both transmitter and receiver

•

One Queued Serial Peripheral Interfaces (QSPI)

— Full-duplex operation

— Master and slave modes

— Four-words-deep FIFOs available on both transmitter and receiver

— Programmable Length Transactions (2 to 16 bits)

2

One Inter-Integrated Circuit (I C) port

— Operates up to 400kbps

— Supports both master and slave operation

— Supports both 10-bit address mode and broadcasting mode

Three 16-bit Programmable Interval Timers (PITs)

•

Two analog Comparators (CMPs)

— Selectable input source includes external pins, DACs

— Programmable output polarity

— Output can drive Timer input, PWM fault input, PWM source, external pin output and trigger

ADCs

56F8025 Digital Signal Controller Product Brief, Rev. 0

4

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

Recommended Operating Conditions

— Output falling and rising edge detection able to generate interrupts

•

Computer Operating Properly (COP)/Watchdog timer capable of selecting different clock sources

Up to 35 General-Purpose I/O (GPIO) pins with 5V tolerance

Integrated Power-On Reset (POR) and Low-Voltage Interrupt (LVI) module

Phase Lock Loop (PLL) provides a high-speed clock to the core and peripherals

Clock sources:

— On-chip relaxation oscillator

— External clock: Crystal oscillator, ceramic resonator, and external clock source

JTAG/EOnCE debug programming interface for real-time debugging

•

5

Recommended Operating Conditions

Table 1. Recommended Operating Conditions

(V

= 0V, V

= 0V, V = 0V)

REFL x

SSA

SS

Characteristic

Symbol

Notes

Min

Typ

Max

Unit

Supply voltage

V_DD,

3

3.3

3.6

V

V_DDA

ADC Reference Voltage High

V_REFHx

ΔV_DD

3.0

-0.1

-0.3

V_DDA

0.1

V

Voltage difference V_{DD_IO}to V_DDA

Voltage difference V_{SS_IO}to V_SSA

0

ΔV_SS

0.3

Device Clock Frequency

Using relaxation oscillator

Using external clock source

FSYSCLK

1

0

32

MHz

Input Voltage High (digital inputs)

Input Voltage Low (digital inputs)

V_IH

V_IL

Pin Groups 1, 2

Pin Group 4

2.0

5.5

0.8

V

-0.3

Oscillator Input Voltage High

V_IHOSC

XTAL not driven by an external clock

XTAL driven by an external clock source

V_DDA- 0.8

2.0

V_DDA+ 0.3

V

Oscillator Input Voltage Low

Analog Input Voltage

V_ILOSC

V_IA

Pin Group 4

Pin Group 3

-0.3

0.0

0.8

V

V_DDA

56F8025 Digital Signal Controller Product Brief, Rev. 0

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

5

Product Documentation

Table 1. Recommended Operating Conditions (continued)

(V

= 0V, V

= 0V, V = 0V)

REFL x

SSA

SS

Characteristic

Symbol

I_OH

Notes

Min

Typ

Max

Unit

Output Source Current High at V_OHmin.)¹

Pin Group 1

—

-4

-8

mA

When programmed for low drive strength

When programmed for high drive strength

Output Source Current Low (at V_OLmax.)¹

I_OL

Pin Groups 1, 2

—

4

8

mA

When programmed for low drive strength

When programmed for high drive strength

Ambient Operating Temperature

(Automotive)

T_A

N_F

-40

125

105

—

°C

Ambient Operating Temperature

(Extended Industrial)

Flash Endurance

(Program Erase Cycles)

T_A= -40°C to

125°C

10,000

cycles

Flash Data Retention

T_R

T_J<= 70°C

average

15

—

years

1

Total chip source or sink current cannot exceed 75mA

6

Product Documentation

The documents listed in Table 2 are required for a complete description and proper design with the

56F8025. Documentation is available from local Freescale distributors, Freescale Semiconductor sales

offices, Freescale Literature Distribution Centers, or online at:

http://www.freescale.com

Table 2. 56F8025 Chip Documentation

Topic

DSP56800E

Description

Order Number

DSP56800ERM

Detailed description of the 56800E family architecture,

16-bit Digital Signal Controller core processor, and the

instruction set

Reference Manual

56F802X and 56F803X

Peripheral Reference

Manual

Detailed description of peripherals of the 56F802x and

56F803x family of devices

MC56F80XXRM

56F80XXBLUG

56F802X and 56F803X

Serial Bootloader User

Guide

Detailed description of the Serial Bootloader in the

56F802x and 56F803x family of devices

56F8025

Technical Data Sheet

Electrical and timing specifications, pin descriptions,

and package descriptions (this document)

MC56F8025

56F8025

Errata

Details any chip issues that might be present

MC56F8025E

56F8025 Digital Signal Controller Product Brief, Rev. 0

Preliminary—Subject to Change Without Notice

6

Freescale Semiconductor

56F8025 Package and Pin-Out

7

56F8025 Package and Pin-Out

ORIENTATION

GPIOB6 / RXD0 / SDA / CLKIN

MARK

GPIOA3 / PWM3

GPIOB1 / SS0 / SDA

GPIOB7 / TXD0 / SCL

GPIOA2 / PWM2

PIN 34

GPIOA4 / PWM4 / TA2 / FAULT1

GPIOB0 / SCLK0 / SCL

PIN 1

GPIOB5 / TA1 / FAULT3 / CLKIN

GPIOA9 / FAULT2 / TA3 / CINB1

GPIOA11 / CINB2

V

DD_IO

SS_IO

GPIOC4 / ANB0 & CINB3

GPIOC5 / ANB1

GPIOA5 / PWM5 / TA3 / FAULTA2

GPIOA8 / FAULTA1 / TA2 / CINA1

GPIOA10 / CINA2

GPIOC6 / ANB2 / V

REFHB

PIN 23

PIN 12

GPIOC7 / ANB3 / V

GPIOA6 / FAULT0 / TA0

REFLB

V

GPIOB2 / MISO0 / TA2 / PSRC0

DDA

Figure 2. Top View, 56F8025 48-Pin LQFP Package

Peripheral pins in bold identify the reset state in Table 3.

56F8025 Digital Signal Controller Product Brief, Rev. 0

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

7

56F8025 Package and Pin-Out

1

Table 3. 56F8025 44-Pin LQFP Package Identification by Pin Number

#

Signal Name

V_SSA

Signal Name

V_CAP

1

2

GPIOB6

RXD0 / SDA / CLKIN

12

13

23

24

GPIOB2

MISO0 / TA2 / PSRC0

34

35

GPIOB1

GPIOC3

GPIOA6

V_{DD_IO}

SS0 / SDA

ANA3 / V_REFLA

FAULT0 / TA0

3

GPIOB7

14

GPIOC2

25

GPIOA10

36

V_{SS_IO}

TXD0 / SCL

ANA2 / V_REFHA

CINA2

4

5

6

7

8

9

GPIOB5

TA1 / FAULT3 / CLKIN

15

16

17

18

19

20

GPIOC1

ANA1

26

27

28

29

30

31

GPIOA8

FAULT1 / TA2 / CINA1

37

38

39

40

41

42

GPIOD5

XTAL / CLKIN

GPIOA9

FAULT2 / TA3 / CINB1

GPIOC0

ANA0 & CINA3

GPIOA5

PWM5 / TA3 / FAULT2

GPIOD4

EXTAL

GPIOA11

CINB2

V_{SS_IO}

GPIOA1

PWM1

GPIOC4

ANB0 &CINB3

V_CAP

V_{DD_IO}

GPIOA0

PWM0

GPIOC5

ANB1

TCI

GPIOD2

GPIOB0

SCLK0 / SCL

TDI

GPIOD0

GPIOC6

GPIOB10

GPIOA4

GPIOB11

ANB2 / V_REFHB

COUTA_A

PWM4 / TA2 / FAULT1

COUTB_A

10

11

GPIOC7

ANB3 / V_REFLB

21

22

RESET

GPIOA7

32

33

GPIOA2

PWM2

43

44

TMS

GPIOD3

V_DDA

GPIOB3

MOSI0 / TA3 /

PSRC1

GPIOA3

PWM3

TDO

GPIOD1

1

Alternate signals are in italic

56F8025 Digital Signal Controller Product Brief, Rev. 0

Preliminary—Subject to Change Without Notice

8

Freescale Semiconductor

56F8025 Package and Pin-Out

Figure 3. 56F8025 44-Pin LQFP Mechanical Information

Please see www.freescale.com for the most current case outline.

56F8025 Digital Signal Controller Product Brief, Rev. 0

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

9

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56F8025 Digital Signal Controller Product Brief, Rev. 0

Preliminary—Subject to Change Without Notice

10

Freescale Semiconductor

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56F8025 Digital Signal Controller Product Brief, Rev. 0

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

11

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Document Number: MC56F8025PB

Rev. 0

09/2006

Preliminary—Subject to Change Without Notice


型号：	MC56F8025E
厂家：	Freescale
描述：	Digital Signal Controller Product Brief 数字信号控制器产品简介控制器
文件：	总12页 (文件大小：165K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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