MC56F8367MPYE [FREESCALE]
16-bit Digital Signal Controllers; 16位数字信号控制器
| 型号： | MC56F8367MPYE |
| 厂家： | 
Freescale |
| 描述： | 16-bit Digital Signal Controllers |
| 文件： | 总180页 (文件大小：2743K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
56F8367/56F8167
Data Sheet
Preliminary Technical Data
56F8300
16-bit Digital Signal Controllers
MC56F8367
Rev. 3.0
09/2005
freescale.com
Document Revision History
Version History
Description of Change
Rev 0
Pre-release, Alpha customers only
Initial Public Release
Rev 1.0
Rev 2.0
Added output voltage maximum value and note to clarify in Table 10-1.; also removed
overall life expectancy note, since life expectancy is dependent on customer usage and
must be determined by reliability engineering. Clarified value and unit measure for
Maximum allowed PD in Table 10-3. Corrected note about average value for Flash Data
Retention in Table 10-4. Added new RoHS-compliant orderable part numbers in
Table 13-1.
Rev 3.0
Added 160MAPBGA information, TA equation updated in Table 10-4 and additional minor
edits throughout data sheet
Please see http://www.freescale.com for the most current Data Sheet revision.
56F8367 Technical Data, Rev. 3.0
2
Freescale Semiconductor
Preliminary
56F8367/56F8167 General Description
Note: Features in italics are NOT available in the 56F8167 device.
• Up to 60 MIPS at 60MHz core frequency
• Temperature Sensor
• DSP and MCU functionality in a unified,
C-efficient architecture
• Up to two Quadrature Decoders
• Optional on-chip regulator
• Access up to 4MB of off-chip program and 32MB of
data memory
• Up to two FlexCAN modules
• Two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interfaces (SPIs)
• Up to four general-purpose Quad Timers
• Computer Operating Properly (COP) / Watchdog
• Chip Select Logic for glueless interface to ROM and
SRAM
• 512KB of Program Flash
• 4KB of Program RAM
• 32KB of Data Flash
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• 32KB of Data RAM
• Up to 76 GPIO lines
• 32KB Boot Flash
• 160-pin LQFP Package and 160 MAPBGA
• Up to two 6-channel PWM modules
• Four 4-channel, 12-bit ADCs
OCR_DIS
* Configuration
shown for on-chip
2.5V regulator
EMI_MODE
RSTO
VPP
2
VCAP VDD
VSS VDDA
VSSA
EXTBOOT
5
RESET
4
7
6
2
6
6
JTAG/
EOnCE
Port
PWM Outputs
Digital Reg
Analog Reg
PWMA
Current Sense Inputs
or GPIOC
3
4
Low Voltage
Supervisor
16-Bit
56800E Core
Fault Inputs
Program Controller
and
Hardware Looping Unit
Address
Generation Unit
Data ALU
Bit
Manipulation
Unit
PWM Outputs
PWMB
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
3
4
Current Sense Inputs
or GPIOD
Fault Inputs
PAB
PDB
CDBR
CDBW
4
4
AD0
ADCA
AD1
R/W Control
6
2
8
5
Memory
Program Memory
256K x 16 Flash
2K x 16 RAM
A0-5 or GPIOA8-13
A6-7 or GPIOE2-3
VREF
XDB2
XAB1
XAB2
4
4
External
Address Bus
Switch
AD0
AD1
ADCB
A8-15 or GPIOA0-7
4
3
GPIOB0-3 (A16-19)
System Bus
Control
PAB
Boot ROM
16K x 16 Flash
Temp_Sense
GPIOB4 (A20, prescaler_clock)
PDB
Quadrature
Decoder 0 or
Quad
Timer A or
GPIOC
GPIOB5-7 (A21-23, clk0-3**)
CDBR
CDBW
D
ata Memory
16K x 16 Flash
4K x 16 Flash
7
9
4
D0-6 or GPIOF9-15
D7-15 or GPIOF0-8
External Data
Bus Switch
WR
Quadrature
Decoder 1 or
Quad
Timer B or
SPI1 or
RD
4
GPIOD2-5 or CS4 -7
Bus Control
4
2
PS / CS0 (GPIOD8)
DS / CS1 (GPIOD9)
IPBus Bridge (IPBB)
GPIOC
Quad
Timer C or
GPIOE
Peripheral
Device Selects
GPIO or EMI CS or
FlexCAN2
GPIOD0 (CS2 or CAN2_TX)
GPIOD1 (CS3 or CAN2_RX)
RW
Control
IPAB
IPWDB
IPRDB
Decoding
Peripherals
Quad
Timer D or
GPIOE
4
2
Clock
resets
PLL
FlexCAN
P
O
R
System
Integration
Module
O
SPI0 or
GPIOE
SCI1 or
GPIOD
SCI0 or
GPIOE
COP/
Interrupt
Clock
XTAL
S
Generator
C
Watchdog Controller
EXTAL
**See Table 2-2
for explanation
4
2
2
CLKMODE
IRQA IRQB
CLKO
56F8367/56F8167 Block Diagram
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
3
Table of Contents
Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . .5
Part 8: General Purpose Input/Output
1.1. 56F8367/56F8167 Features . . . . . . . . . . . . . 5
1.2. Device Description . . . . . . . . . . . . . . . . . . . . 7
1.3. Award-Winning Development Environment . 9
1.4. Architecture Block Diagram. . . . . . . . . . . . . 10
1.5. Product Documentation. . . . . . . . . . . . . . . . 14
1.6. Data Sheet Conventions . . . . . . . . . . . . . . . 14
(GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . 132
8.2. Memory Maps . . . . . . . . . . . . . . . . . . . . . .132
8.3. Configuration. . . . . . . . . . . . . . . . . . . . . . . 132
Part 9: Joint Test Action Group (JTAG) . 137
9.1. 56F8367 Information . . . . . . . . . . . . . . . . .137
Part 2: Signal/Connection Descriptions . . .15
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2. Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . 18
Part 10: Specifications . . . . . . . . . . . . . . . 137
10.1. General Characteristics . . . . . . . . . . . . . .137
10.2. DC Electrical Characteristics . . . . . . . . . .141
10.3. AC Electrical Characteristics . . . . . . . . . .145
10.4. Flash Memory Characteristics . . . . . . . . .145
10.5. External Clock Operation Timing . . . . . . 146
10.6. Phase Locked Loop Timing . . . . . . . . . . .146
10.7. Crystal Oscillator Timing . . . . . . . . . . . . . 147
10.8. External Memory Interface Timing . . . . . .147
10.9. Reset, Stop, Wait, Mode Select, and Interrupt
Timing . . . . . . . . . . . . . . . . . . . . .150
Part 3: On-Chip Clock Synthesis (OCCS) . .38
3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.2. External Clock Operation . . . . . . . . . . . . . . 38
3.3. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Part 4: Memory Operating Modes (MEM) . .40
4.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.2. Program Map. . . . . . . . . . . . . . . . . . . . . . . . 41
4.3. Interrupt Vector Table . . . . . . . . . . . . . . . . . 42
4.4. Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.5. Flash Memory Map . . . . . . . . . . . . . . . . . . . 46
4.6. EOnCE Memory Map . . . . . . . . . . . . . . . . . 48
4.7. Peripheral Memory Mapped Registers . . . . 49
4.8. Factory Programmed Memory . . . . . . . . . . 79
10.10. Serial Peripheral Interface (SPI) Timing .152
10.11. Quad Timer Timing . . . . . . . . . . . . . . . .156
10.12. Quadrature Decoder Timing . . . . . . . . . .156
10.13. Serial Communication Interface
(SCI) Timing . . . . . . . . . . . . . . . .157
10.14. Controller Area Network (CAN) Timing .158
10.15. JTAG Timing . . . . . . . . . . . . . . . . . . . . . 158
10.16. Analog-to-Digital Converter
(ADC) Parameters . . . . . . . . . . . .160
10.17. Equivalent Circuit for ADC Inputs . . . . . .163
10.18. Power Consumption . . . . . . . . . . . . . . . 163
Part 5: Interrupt Controller (ITCN) . . . . . . . .80
5.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.3. Functional Description. . . . . . . . . . . . . . . . . 80
5.4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . 82
5.5. Operating Modes . . . . . . . . . . . . . . . . . . . . 82
5.6. Register Descriptions . . . . . . . . . . . . . . . . . 83
5.7. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Part 11: Packaging . . . . . . . . . . . . . . . . . . . 165
11.1. 56F8367 Package and Pin-Out Information 165
11.2. 56F8167 Package and Pin-Out Information 172
Part 6: System Integration Module (SIM) .110
6.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.3. Operating Modes . . . . . . . . . . . . . . . . . . . 111
6.4. Operating Mode Register . . . . . . . . . . . . . 111
6.5. Register Descriptions . . . . . . . . . . . . . . . . 112
6.6. Clock Generation Overview. . . . . . . . . . . . 126
6.7. Power Down Modes Overview . . . . . . . . . 127
6.8. Stop and Wait Mode Disable Function . . . 128
6.9. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Part 12: Design Considerations . . . . . . . . 176
12.1. Thermal Design Considerations . . . . . . . .176
12.2. Electrical Design Considerations . . . . . . .177
12.3. Power Distribution and I/O Ring
12.4. Implementation . . . . . . . . . . . . . . . . . . . . .178
Part 13: Ordering Information . . . . . . . . . 179
Part 7: Security Features . . . . . . . . . . . . . .129
7.1. Operation with Security Enabled. . . . . . . . 129
7.2. Flash Access Blocking Mechanisms . . . . . 129
56F8367 Technical Data, Rev. 3.0
4
Freescale Semiconductor
Preliminary
56F8367/56F8167 Features
Part 1 Overview
1.1 56F8367/56F8167 Features
1.1.1
Core
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Efficient 16-bit 56800E family controller engine with dual Harvard architecture
Up to 60 Million Instructions Per Second (MIPS) at 60MHz core frequency
Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
Four 36-bit accumulators, including extension bits
Arithmetic and logic multi-bit shifter
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three internal address buses and one external address bus
Four internal data buses and one external data bus
Instruction set supports both DSP and controller functions
Controller-style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/EOnCE debug programming interface
1.1.2
Differences Between Devices
Table 1-1 outlines the key differences between the 56F8367 and 56F8167 devices.
Table 1-1 Device Differences
Feature
56F8367
56F8167
Guaranteed Speed
Program RAM
Data Flash
60MHz/60 MIPS
40MHZ/40MIPS
Not Available
Not Available
1 x 6
4KB
32KB
2 x 6
2
PWM
CAN
Not Available
2
Quad Timer
4
Quadrature Decoder
Temperature Sensor
Dedicated GPIO
2 x 4
1
1 x 4
Not Available
7
—
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
5
1.1.3
Memory
Note: Features in italics are NOT available in the 56F8167 device.
•
•
•
Harvard architecture permits as many as three simultaneous accesses to program and data memory
Flash security protection feature
On-chip memory, including a low-cost, high-volume Flash solution
— 512KB of Program Flash
— 4KB of Program RAM
— 32KB of Data Flash
— 32KB of Data RAM
— 32KB of Boot Flash
•
Off-chip memory expansion capabilities provide a simple method for interfacing additional external
memory and/or peripheral devices
— Access up to 4MB of external program memory or 32MB of external data memory
— Chip select logic for glueless interface to ROM and SRAM
EEPROM emulation capability
•
1.1.4
Peripheral Circuits
Note: Features in italics are NOT available in the 56F8167 device.
•
Pulse Width Modulator:
— In the 56F8367, two Pulse Width Modulator modules, each with six PWM outputs, three Current Sense
inputs, and three Fault inputs; fault-tolerant design with dead time insertion; supports both
center-aligned and edge-aligned modes
— In the 56F8167, one Pulse Width Modulator module, with six PWM outputs, three Current Sense inputs,
and three Fault inputs; fault-tolerant design with dead time insertion; supports both center-aligned and
edge-aligned modes
•
•
Four 12-bit, Analog-to-Digital Converters (ADCs), which support four simultaneous conversions with
quad, 4-pin multiplexed inputs; ADC and PWM modules can be synchronized through Timer C, channels
2 and 3
Quadrature Decoder:
— In the 56F8367, two four-input Quadrature Decoders or two additional Quad Timers
— In the 56F8167, one four-input Quadrature Decoder, which works in conjunction with Quad Timer A
•
Temperature Sensor can be connected, on the board, to any of the ADC inputs to monitor the on-chip
temperature
•
Quad Timer:
— In the 56F8367, four dedicated general-purpose Quad Timers totaling six dedicated pins: Timer C with
two pins and Timer D with four pins
— In the 56F8167, two general-purpose Quad Timers; Timer A works in conjunction with Quadrature
Decoder 0 or GPIO and Timer C works in conjunction with GPIO
•
Up to two FlexCAN (CAN Version 2.0 B-compliant ) modules with 2-pin port for transmit and receive
56F8367 Technical Data, Rev. 3.0
6
Freescale Semiconductor
Preliminary
Device Description
•
•
Two Serial Communication Interfaces (SCIs), each with two pins (or four additional GPIO lines)
Up to two Serial Peripheral Interfaces (SPIs), both with configurable 4-pin port (or eight additional GPIO
lines)
— In the 56F8367, SPI1 can also be used as Quadrature Decoder 1, Quad Timer B or GPIO
— In the 56F8167, SPI1 can alternately be used only as GPIO
Computer Operating Properly (COP) / Watchdog timer
•
•
•
•
•
•
•
•
Two dedicated external interrupt pins
Up to 76 General Purpose I/O (GPIO) pins
External reset input pin for hardware reset
External reset output pin for system reset
Integrated Low-Voltage Interrupt Module
JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent debugging
Software-programmable, Phase Lock Loop (PLL)-based frequency synthesizer for the core clock
1.1.5
Energy Information
•
•
•
•
•
•
Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
On-board 3.3V down to 2.6V voltage regulator for powering internal logic and memories; can be disabled
On-chip regulators for digital and analog circuitry to lower cost and reduce noise
Wait and Stop modes available
ADC smart power management
Each peripheral can be individually disabled to save power
1.2 Device Description
The 56F8367 and 56F8167 are members of the 56800E core-based family of controllers. Each combines,
on a single chip, the processing power of a Digital Signal Processor (DSP) and the functionality of a
microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because
of its low cost, configuration flexibility, and compact program code, the 56F8367 and 56F8167 are
well-suited for many applications. The device includes many peripherals that are especially useful for
motion control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and
control, automotive control (56F8367 only), engine management, noise suppression, remote utility
metering, industrial control for power, lighting, and automation applications.
The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and
optimized instruction set allow straightforward generation of efficient, compact DSP and control code.
The instruction set is also highly efficient for C/C++ Compilers to enable rapid development of optimized
control applications.
The 56F8367 and 56F8167 support program execution from internal or external memories. Two data
operands can be accessed from the on-chip data RAM per instruction cycle. These devices also provide
two external dedicated interrupt lines and up to 76 General Purpose Input/Output (GPIO) lines, depending
on peripheral configuration.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
7
1.2.1
56F8367 Features
The 56F8367 controller includes 512KB of Program Flash and 32KB of Data Flash (each programmable
through the JTAG port) with 4KB of Program RAM and 32KB of Data RAM. It also supports program
execution from external memory.
A total of 32KB of Boot Flash is incorporated for easy customer inclusion of field-programmable software
routines that can be used to program the main Program and Data Flash memory areas. Both Program and
Data Flash memories can be independently bulk erased or erased in page sizes. Program Flash page erase
size is 1KB. Boot and Data Flash page erase size is 512 bytes. The Boot Flash memory can also be either
bulk or page erased.
A key application-specific feature of the 56F8367 is the inclusion of two Pulse Width Modulator (PWM)
modules. These modules each incorporate three complementary, individually programmable PWM signal
output pairs (each module is also capable of supporting six independent PWM functions, for a total of 12
PWM outputs) to enhance motor control functionality. Complementary operation permits programmable
dead time insertion, distortion correction via current sensing by software, and separate top and bottom
output polarity control. The up-counter value is programmable to support a continuously variable PWM
frequency. Edge-aligned and center-aligned synchronous pulse width control (0% to 100% modulation) is
supported. The device is capable of controlling most motor types: ACIM (AC Induction Motors); both
BDC and BLDC (Brush and Brushless DC motors); SRM and VRM (Switched and Variable Reluctance
Motors); and stepper motors. The PWMs incorporate fault protection and cycle-by-cycle current limiting
with sufficient output drive capability to directly drive standard optoisolators. A “smoke-inhibit”,
write-once protection feature for key parameters is also included. A patented PWM waveform distortion
correction circuit is also provided. Each PWM is double-buffered and includes interrupt controls to permit
integral reload rates to be programmable from 1 to 16. The PWM modules provide a reference output to
synchronize the Analog-to-Digital Converters through two channels of Quad Timer C.
The 56F8367 incorporates two Quadrature Decoders capable of capturing all four transitions on the
two-phase inputs, permitting generation of a number proportional to actual position. Speed computation
capabilities accommodate both fast- and slow-moving shafts. An integrated watchdog timer in the
Quadrature Decoder can be programmed with a time-out value to alarm when no shaft motion is detected.
Each input is filtered to ensure only true transitions are recorded.
This controller also provides a full set of standard programmable peripherals that include two Serial
Communications Interfaces (SCIs); two Serial Peripheral Interfaces (SPIs); and four Quad Timers. Any of
these interfaces can be used as General Purpose Input/Outputs (GPIOs) if that function is not required.
Two Flex Controller Area Network (FlexCAN) interfaces (CAN Version 2.0 B-compliant) and an internal
interrupt controller are a part of the 56F8367.
1.2.2
56F8167 Features
The 56F8167 controller includes 128KB of Program Flash, programmable through the JTAG port, with
8KB of Data RAM. It also supports program execution from external memory.
A total of 8KB of Boot Flash is incorporated for easy customer inclusion of field-programmable software
routines that can be used to program the main Program Flash memory area, which can be independently
56F8367 Technical Data, Rev. 3.0
8
Freescale Semiconductor
Preliminary
Award-Winning Development Environment
bulk erased or erased in pages. Program Flash page erase size is 1KB. Boot Flash page erase size is 512
bytes and the Boot Flash memory can also be either bulk or page erased.
A key application-specific feature of the 56F8167 is the inclusion of one Pulse Width Modulator (PWM)
module. This module incorporates three complementary, individually programmable PWM signal output
pairs and can also support six independent PWM functions to enhance motor control functionality.
Complementary operation permits programmable dead time insertion, distortion correction via current
sensing by software, and separate top and bottom output polarity control. The up-counter value is
programmable to support a continuously variable PWM frequency. Edge-aligned and center-aligned
synchronous pulse width control (0% to 100% modulation) is supported. The device is capable of
controlling most motor types: ACIM (AC Induction Motors); both BDC and BLDC (Brush and Brushless
DC motors); SRM and VRM (Switched and Variable Reluctance Motors); and stepper motors. The PWM
incorporates fault protection and cycle-by-cycle current limiting with sufficient output drive capability to
directly drive standard optoisolators. A “smoke-inhibit”, write-once protection feature for key parameters
is also included. A patented PWM waveform distortion correction circuit is also provided. Each PWM is
double-buffered and includes interrupt controls to permit integral reload rates to be programmable from 1
to 16. The PWM module provides reference outputs to synchronize the Analog-to-Digital Converters
through two channels of Quad Timer C.
The 56F8167 incorporates a Quadrature Decoder capable of capturing all four transitions on the two-phase
inputs, permitting generation of a number proportional to actual position. Speed computation capabilities
accommodate both fast- and slow-moving shafts. An integrated watchdog timer in the Quadrature Decoder
can be programmed with a time-out value to alert when no shaft motion is detected. Each input is filtered
to ensure only true transitions are recorded.
This controller also provides a full set of standard programmable peripherals that include two Serial
Communications Interfaces (SCIs); two Serial Peripheral Interfaces (SPIs); and two Quad Timers. Any of
these interfaces can be used as General Purpose Input/Outputs (GPIOs) if that function is not required. An
internal interrupt controller is also a part of the 56F8167.
1.3 Award-Winning Development Environment
TM
Processor Expert
(PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use
component-based software application creation with an expert knowledge system.
The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards
will support concurrent engineering. Together, PE, CodeWarrior and EVMs create a complete, scalable
tools solution for easy, fast, and efficient development.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
9
1.4 Architecture Block Diagram
Note: Features in italics are NOT available in the 56F8167 device and are shaded in the following figures.
The 56F8367/56F8167 architecture is shown in Figure 1-1 and Figure 1-2. Figure 1-1 illustrates how the
56800E system buses communicate with internal memories, the external memory interface and the IPBus
Bridge. Table 1-2 lists the internal buses in the 56800E architecture and provides a brief description of
their function. Figure 1-2 shows the peripherals and control blocks connected to the IPBus Bridge. The
figures do not show the on-board regulator and power and ground signals. They also do not show the
multiplexing between peripherals or the dedicated GPIOs. Please see Part 2, Signal/Connection
Descriptions, to see which signals are multiplexed with those of other peripherals.
Also shown in Figure 1-2 are connections between the PWM, Timer C and ADC blocks. These
connections allow the PWM and/or Timer C to control the timing of the start of ADC conversions. The
Timer C channel indicated can generate periodic start (SYNC) signals to the ADC to start its conversions.
In another operating mode, the PWM load interrupt (SYNC output) signal is routed internally to the Timer
C input channel as indicated. The timer can then be used to introduce a controllable delay before
generating its output signal. The timer output then triggers the ADC. To fully understand this interaction,
please see the 56F8300 Peripheral User Manual for clarification on the operation of all three of these
peripherals.
56F8367 Technical Data, Rev. 3.0
10
Freescale Semiconductor
Preliminary
Architecture Block Diagram
5
JTAG / EOnCE
Boot
Flash
pdb_m[15:0]
pab[20:0]
Program
Flash
Program
RAM
cdbw[31:0]
56800E
24
Address
Data
CHIP
TAP
Controller
EMI
16
10
Control
TAP
Linking
Module
Data RAM
Data Flash
xab1[23:0]
xab2[23:0]
ExternalJTAG
Port
cdbr_m[31:0]
xdb2_m[15:0]
To Flash
Control Logic
IPBus
Bridge
Flash
Memory
Module
NOT available on the 56F8167 device.
IPBus
Figure 1-1 System Bus Interfaces
Note:
Note:
Flash memories are encapsulated within the Flash Memory (FM) Module . Flash control is
accomplished by the I/O to the FM over the peripheral bus, while reads and writes are completed
between the core and the Flash memories.
The primary data RAM port is 32 bits wide. Other data ports are 16 bits.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
11
To/From IPBus Bridge
Interrupt
Controller
CLKGEN
(OSC/PLL)
Low Voltage Interrupt
POR & LVI
System POR
RESET
Timer A
4
Quadrature Decoder 0
Timer D
SIM
4
COP Reset
Timer B
COP
2
2
4
FlexCAN
FlexCAN2
Quadrature Decoder 1
SPI 1
13
PWMA
GPIO A
GPIO B
GPIO C
GPIO D
GPIO E
GPIO F
SYNC Output
13
PWMB
SYNC Output
ch3i
ch2i
2
Timer C
ch3o
ch2o
8
ADCB
ADCA
4
SPI 0
SCI 0
8
2
1
2
TEMP_SENSE
SCI 1
Note: ADC A and ADC B use the same voltage
IPBus
NOT available on the 56F8167 device.
reference circuit with VREFH, VREFP, VREFMID
VREFN, and VREFLO pins.
,
Figure 1-2 Peripheral Subsystem
56F8367 Technical Data, Rev. 3.0
12
Freescale Semiconductor
Preliminary
Architecture Block Diagram
Table 1-2 Bus Signal Names
Name
Function
Program Memory Interface
pdb_m[15:0] Program data bus for instruction word fetches or read operations.
cdbw[15:0]
Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus
are used for writes to program memory.)
pab[20:0]
Program memory address bus. Data is returned on pdb_m bus.
Primary Data Memory Interface Bus
cdbr_m[31:0] Primary core data bus for memory reads. Addressed via xab1 bus.
cdbw[31:0]
xab1[23:0]
Primary core data bus for memory writes. Addressed via xab1 bus.
Primary data address bus. Capable of addressing bytes1, words, and long data types. Data is written
on cdbw and returned on cdbr_m. Also used to access memory-mapped I/O.
Secondary Data Memory Interface
xdb2_m[15:0] Secondary data bus used for secondary data address bus xab2 in the dual memory reads.
xab2[23:0]
Secondary data address bus used for the second of two simultaneous accesses. Capable of
addressing only words. Data is returned on xdb2_m.
Peripheral Interface Bus
IPBus [15:0] Peripheral bus accesses all on-chip peripherals registers. This bus operates at the same clock rate
as the Primary Data Memory and therefore generates no delays when accessing the processor.
Write data is obtained from cdbw. Read data is provided to cdbr_m.
1. Byte accesses can only occur in the bottom half of the memory address space. The MSB of the address will be forced
to 0.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
13
1.5 Product Documentation
The documents in Table 1-2 are required for a complete description and proper design with the
56F8367/56F8167 devices. Documentation is available from local Freescale distributors, Freescale
semiconductor sales offices, Freescale Literature Distribution Centers, or online at
http://www.freescale.com.
Table 1-3 Chip Documentation
Topic
DSP56800E
Description
Order Number
Detailed description of the 56800E family architecture,
and 16-bit controller core processor and the instruction
set
DSP56800EERM
Reference Manual
56F8300 Peripheral User
Manual
Detailed description of peripherals of the 56F8300
devices
MC56F8300UM
MC56F83xxBLUM
MC56F8367
56F8300 SCI/CAN
Bootloader User Manual
Detailed description of the SCI/CAN Bootloaders
56F8300 family of devices
56F8367/56F8167
Technical Data Sheet
Electrical and timing specifications, pin descriptions,
and package descriptions (this document)
Errata
Details any chip issues that might be present
MC56F8367E
MC56F8167E
1.6 Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.
“asserted”
“deasserted”
Examples:
A high true (active high) signal is high or a low true (active low) signal is low.
A high true (active high) signal is low or a low true (active low) signal is high.
Voltage1
Signal/Symbol
Logic State
True
Signal State
Asserted
PIN
PIN
PIN
PIN
VIL/VOL
False
Deasserted
Asserted
VIH/VOH
VIH/VOH
VIL/VOL
True
False
Deasserted
1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
56F8367 Technical Data, Rev. 3.0
14
Freescale Semiconductor
Preliminary
Introduction
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F8367 and 56F8167 are organized into functional groups, as detailed
in Table 2-1 and as illustrated in Figure 2-1. In Table 2-2, each table row describes the signal or signals
present on a pin.
Table 2-1 Functional Group Pin Allocations
Number of Pins in Package
Functional Group
56F8367
56F8167
Power (VDD or VDDA
)
9
9
Power Option Control
1
7
1
7
Ground (VSS or VSSA
)
Supply Capacitors1 & VPP
6
6
PLL and Clock
4
24
16
10
6
4
24
16
10
6
Address Bus
Data Bus
Bus Control
Interrupt and Program Control
Pulse Width Modulator (PWM) Ports
Serial Peripheral Interface (SPI) Port 0
Serial Peripheral Interface (SPI) Port 1
26
4
13
4
—
4
4
Quadrature Decoder Port 02
Quadrature Decoder Port 13
4
4
4
—
4
Serial Communications Interface (SCI) Ports2
CAN Ports
2
21
6
—
21
2
Analog to Digital Converter (ADC) Ports
Timer Module Ports
JTAG/Enhanced On-Chip Emulation (EOnCE)
Temperature Sense
5
5
1
—
7
Dedicated GPIO
—
1. If the on-chip regulator is disabled, the VCAP pins serve as 2.5V VDD_CORE power inputs
2. Alternately, can function as Quad Timer pins
3. Pins in this section can function as Quad Timer, SPI #1, or GPIO
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
15
V
DD_IO
Power
Power
7
1
1
6
PHASEA0 (TA0, GPIOC4)
PHASEB0 (TA1, GPIOC5)
INDEX0 (TA2, GPIOC6)
HOME0 (TA3, GPIOC7)
V
Quadrature
Decoder 0
or Quad
1
1
1
1
DDA_OSC_PLL
V
V
DDA_ADC
Power
V
SS
Ground
Ground
Timer A
SSA_ADC
1
1
56F8367
OCR_DIS
SCLK0
1
1
1
1
SPI0 or
GPIO
MOSI0 (GPIOE5)
MISO0 (GPIOE6)
SS0 (GPIOE7)
*V
1 - V
4
2
Other
Supply
Ports
CAP
CAP
4
2
V
1 & V
PP
PP
CLKMODE
EXTAL
XTAL
1
1
Quadrature
Decoder 1 or
Quad Timer B
or SPI 1 or
GPIO
PHASEA1(TB0, SCLK1, GPIOC0)
PHASEB1 (TB1, MOSI1, GPIOC1)
INDEX1 (TB2, MISO1, GPIOC2)
HOME1 (TB3, SS1, GPIOC3)
PLL
and
Clock
1
1
1
1
1
1
CLKO
A0 - A5 (GPIOA8 - 13)
A6 - A7 (GPIOE2 - 3)
A8 - A15 (GPIOA0 - 7)
6
2
PWMA0 - 5
6
3
4
ISA0 - 2 (GPIOC8 - 10)
FAULTA0 - 3
PWMA
PWMB
External
Address
Bus
8
8
1
1
1
1
GPIOB0 - 7 (A16 - 23)
GPIOB4 (A20, prescaler_clock)
GPIOB5 (A21, SYS_CLK)
or GPIO
PWMB0 - 5
6
ISB0 - 2 (GPIOD10 - 12)
FAULTB0 - 3
GPIOB6 (A22, SYS_CLK2)
GPIOB7 (A23, oscillator_clock)
3
4
D0 - D6 (GPIOF9 - 15)
D7 - D15 (GPIOF0 - 8)
External
Data Bus
7
9
ANA0 - 7
8
ADCA
ADCB
V
REF
5
8
ANB0 - 7
RD
1
1
WR
Temperature
Sense
Temp_Sense
PS/CS0 (GPIODF8)
DS/CS1 (GPIOFD9)
1
1
1
1
External
Bus
Control
CAN_RX
CAN_TX
GPIOD0 (CS2, CAN2_TX)
1
1
FlexCAN
GPIOD1 (CS3, CAN2_RX)
GPIOD2 - 5 (CS4 - 7)
1
4
Quad Timer
C and D or
GPIO
TC0 - 1 (GPIOE8 - 9)
2
4
TXD0 (GPIOE0)
RXD0 (GPIOE1)
SCI 0 or
GPIO
1
1
TD0 - 3 (GPIOE10 - 13)
TXD1 (GPIOD6)
RXD1 (GPIOD7)
SCI 1 or
GPIOD
1
1
IRQA
1
IRQB
1
1
TCK
TMS
TDI
EXTBOOT
EMI_MODE
INTERRUPT/
PROGRAM
CONTROL
1
1
1
JTAG/
EOnCE
Port
1
RESET
RSTO
TDO
TRST
1
1
1
1
* When the on-chip regulator is disabled, these four pins become 2.5V V
.
DD_CORE
1
Figure 2-1 56F8367 Signals Identified by Functional Group (160-pin LQFP)
1. Alternate pin functionality is shown in parenthesis; pin direction/type shown is the default functionality.
56F8367 Technical Data, Rev. 3.0
16
Freescale Semiconductor
Preliminary
Introduction
V
DD_IO
Power
Power
Quadrature
PHASEA0 (TA0, GPIOC4)
PHASEB0 (TA1, GPIOC5)
INDEX0 (TA2, GPIOC6)
HOME0 (TA3, GPIOC7)
7
1
1
1
1
1
V
Decoder 0
or Quad
Timer A or
GPIO
DDA_ADC
V
DDA_OSC_PLL
Power
1
6
V
Ground
Ground
SS
V
SSA_ADC
1
1
56F8167
OCR_DIS
SCLK0
1
1
1
1
SPI0 or
GPIO
MOSI0 (GPIOE5)
MISO0 (GPIOE6)
SS0 (GPIOE7)
*V
1 - V
4
CAP
Other
Supply
Ports
CAP
4
2
V
1 & V
2
PP
PP
CLKMODE
EXTAL
XTAL
1
1
(SCLK1, GPIOC0)
(MOSI1, GPIOC1)
(MISO1, GPIOC2)
(SS1, GPIOC3)
PLL
and
Clock
1
1
1
1
SPI 1 or
GPIO
1
1
CLKO
A0 - A5 (GPIOA8 - 13)
A6 - A7 (GPIOE2 - 3)
A8 - A15 (GPIOA0 - 7)
6
2
(GPIOC8 - 10)
GPIO
3
External
Address
Bus
8
4
1
1
1
1
GPIOB0 - 3 (A16 - 19)
GPIOB4 (A20, prescaler_clock)
GPIOB5 (A21, SYS_CLK)
PWMB0 - 5
or GPIO
6
3
4
PWMB or
GPIO
ISB0 - 2 (GPIOD10 - 12)
FAULTB0 - 3
GPIOB6 (A22, SYS_CLK2)
GPIOB7 (A23, oscillator_clock)
ADCA
ADCB
ANA0 - 7
External
Data Bus
or GPIO
8
D0 - D6 (GPIOF9 - 15)
D7 - D15 (GPIOF0 - 8)
7
9
V
REF
5
8
ANB0 - 7
RD
WR
1
1
1
1
6
External
Bus
Control or
GPIO
PS (CS0, GPIOD8)
DS (CS1, GPIOD9)
GPIOD0 - 5 (CS2 - 7)
TXD0 (GPIOE0)
RXD0 (GPIOE1)
SCI 0 or
GPIO
1
1
QUAD
TIMER C or
GPIO
TC0 - 1 (GPIOE8 - 9)
(GPIOE10 - 13)
2
4
TXD1 (GPIOD6)
RXD1 (GPIOD7)
SCI 1
or GPIO
1
1
IRQA
1
IRQB
1
1
TCK
TMS
TDI
1
1
1
EXTBOOT
EMI_MODE
INTERRUPT
/ PROGRAM
CONTROL
JTAG/
EOnCE
Port
1
RESET
RSTO
TDO
TRST
1
1
1
1
* When the on-chip regulator is disabled, these four pins become 2.5V V
.
DD_CORE
1
Figure 2-2 56F8167 Signals Identified by Functional Group (160-pin LQFP)
1. Alternate pin functionality is shown in parenthesis; pin direction/type shown is the default functionality.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
17
2.2 Signal Pins
After reset, each pin is configured for its primary function (listed first). Any alternate functionality must
be programmed.
Note: Signals in italics are NOT available in the 56F8167 device.
Note: The 160 Map Ball Grid Array is not available in the 56F8167 device.
If the “State During Reset” lists more than one state for a pin, the first state is the actual reset state. Other
states show the reset condition of the alternate function, which you get if the alternate pin function is
selected without changing the configuration of the alternate peripheral. For example, the A8/GPIOA0 pin
shows that it is tri-stated during reset. If the GPIOA_PER is changed to select the GPIO function of the
pin, it will become an input if no other registers are changed.
Note: LQFP Pin numbers and MBGA Ball numbers do not always correlate in Table 2-2. Please contact
factory for exact correlation.
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA
State
During
Reset
Signal
Name
Pin
No.
Ball No.
Type
Signal Description
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDDA_ADC
1,16
31,42
77,96
134
F4,K5
E5,K7
E9,K10
F11
Supply
I/O Power — This pin supplies 3.3V power to the chip I/O interface
and also the Processor core throught the on-chip voltage regulator, if it
is enabled.
114
92
C14
K13
Supply
Supply
ADC Power — This pin supplies 3.3V power to the ADC modules. It
must be connected to a clean analog power supply.
VDDA_OSC_
Oscillator and PLL Power — This pin supplies 3.3V power to the
OSC and to the internal regulator that in turn supplies the Phase
Locked Loop. It must be connected to a clean analog power supply.
PLL
VSS
VSS
VSS
VSS
VSS
VSS
27,41
74,80 G11,E7
125
160
J4,K11
Supply
VSS — These pins provide ground for chip logic and I/O drivers.
J11,E6
56F8367 Technical Data, Rev. 3.0
18
Freescale Semiconductor
Preliminary
Signal Pins
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA
State
During
Reset
Signal
Name
Pin
No.
Ball No.
Type
Signal Description
VSSA_ADC
OCR_DIS
115
D12
K14
Supply
Input
ADC Analog Ground — This pin supplies an analog ground to the
ADC modules.
91
Input
On-Chip Regulator Disable —
Tie this pin to VSS to enable the on-chip regulator
Tie this pin to VDD to disable the on-chip regulator
This pin is intended to be a static DC signal from power-up to
shut down. Do not try to toggle this pin for power savings during
operation.
VCAP1*
VCAP2*
VCAP3*
VCAP4*
62
144
95
K8
E8
Supply
Supply
VCAP1 - 4 — When OCR_DIS is tied to VSS (regulator enabled),
connect each pin to a 2.2µF or greater bypass capacitor in order to
bypass the core logic voltage regulator, required for proper chip
operation. When OCR_DIS is tied to VDD (regulator disabled), these
H11
G4
pins become VDD_CORE and should be connected to a regulated 2.5V
power supply.
15
Note: This bypass is required even if the chip is powered with an
external supply.
* When the on-chip regulator is disabled, these four pins become 2.5V VDD_CORE
.
VPP
1
2
141
2
A7
C2
Input
Input
VPP1 - 2 — These pins should be left unconnected as an open circuit
for normal functionality.
VPP
CLKMODE
99
H12
Input
Input
Clock Input Mode Selection — This input determines the function of
the XTAL and EXTAL pins.
1 = External clock input on XTAL is used to directly drive the input
clock of the chip. The EXTAL pin should be grounded.
0 = A crystal or ceramic resonator should be connected between XTAL
and EXTAL.
EXTAL
XTAL
94
93
J12
Input
Input
External Crystal Oscillator Input — This input can be connected to
an 8MHz external crystal. Tie this pin low if XTAL is driven by an
external clock source.
K12
Input/
Chip-drive Crystal Oscillator Output — This output connects the internal crystal
Output
n
oscillator output to an external crystal.
If an external clock is used, XTAL must be used as the input and
EXTAL connected to GND.
The input clock can be selected to provide the clock directly to the
core. This input clock can also be selected as the input clock for the
on-chip PLL.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
19
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA
State
During
Reset
Signal
Name
Pin
No.
Ball No.
Type
Signal Description
CLKO
3
D3
Output
Tri-Stated Clock Output — This pin outputs a buffered clock signal. Using the
SIM CLKO Select Register (SIM_CLKOSR), this pin can be
programmed as any of the following: disabled, CLK_MSTR (system
clock), IPBus clock, oscillator output, prescaler clock and postscaler
clock. Other signals are also available for test purposes.
See Part 6.5.7 for details.
A0
154
C3
Output
Tri-stated Address Bus — A0 - A5 specify six of the address lines for external
program or data memory accesses.
Depending upon the state of the DRV bit in the EMI bus control register
(BCR), A0 - A5 and EMI control signals are tri-stated when the external
bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
(GPIOA8)
Input/
Input
Port A GPIO — These six GPIO pins can be individually programmed
Output
as input or output pins.
A1
(GPIOA9)
10
11
12
13
14
17
E3
E4
F2
F1
F3
G1
After reset, the default state is Address Bus.
A2
(GPIOA10)
To deactivate the internal pull-up resistor, clear the appropriate GPIO
bit in the GPIOA_PUR register.
A3
(GPIOA11)
Example: GPIOA8, clear bit 8 in the GPIOA_PUR register.
A4
(GPIOA12)
A5
(GPIOA13)
A6
Output
Tri-stated Address Bus — A6 - A7 specify two of the address lines for external
program or data memory accesses.
Depending upon the state of the DRV bit in the EMI bus control register
(BCR), A6 - A7 and EMI control signals are tri-stated when the external
bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
(GPIOE2)
Schmitt
Input/
Output
Input
Port E GPIO — These two GPIO pins can be individually programmed
as input or output pins.
A7
(GPIOE3)
18
G3
After reset, the default state is Address Bus.
To deactivate the internal pull-up resistor, clear the appropriate GPIO
bit in the GPIOE_PUR register.
Example: GPIOE2, clear bit 2 in the GPIOE_PUR register.
56F8367 Technical Data, Rev. 3.0
20
Freescale Semiconductor
Preliminary
Signal Pins
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA
State
During
Reset
Signal
Name
Pin
No.
Ball No.
Type
Signal Description
A8
19
G2
Output
Tri-stated Address Bus— A8 - A15 specify eight of the address lines for external
program or data memory accesses.
Depending upon the state of the DRV bit in the EMI bus control register
(BCR), A8 - A15 and EMI control signals are tri-stated when the external
bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
(GPIOA0)
Schmitt
Input/
Output
Input
Port A GPIO — These eight GPIO pins can be individually
programmed as input or output pins.
A9
(GPIOA1)
20
21
22
23
24
25
26
H1
H2
H4
H3
J1
After reset, the default state is Address Bus.
A10
(GPIOA2)
To deactivate the internal pull-up resistor, clear the appropriate GPIO
bit in the GPIOA_PUR register.
A11
(GPIOA3)
Example: GPIOA0, clear bit 0 in the GPIOA_PUR register.
A12
(GPIOA4)
A13
(GPIOA5)
A14
(GPIOA6)
J2
A15
J3
(GPIOA7)
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
21
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA
State
During
Reset
Signal
Name
Pin
No.
Ball No.
Type
Signal Description
GPIOB0
33
L1
Schmitt
Input/
Input
Port B GPIO — These four GPIO pins can be programmed as input or
output pins.
Output
(A16)
Output
Tri-stated Address Bus — A16 - A19 specify one of the address lines for
external program or data memory accesses.
GPIOB1
(A17)
34
35
36
L3
L2
Depending upon the state of the DRV bit in the EMI bus control register
(BCR), A16 - A19 and EMI control signals are tri-stated when the external
bus is inactive.
GPIOB2
(A18)
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
GPIOB3
(A19)
M1
After reset, the startup state of GPIOB0 - GPIOB3 (GPIO or address)
is determined as a function of EXTBOOT, EMI_MODE and the Flash
security setting. See Table 4-4 for further information on when this pin
is configured as an address pin at reset. In all cases, this state may be
changed by writing to GPIOB_PER.
To deactivate the internal pull-up resistor, clear the appropriate GPIO
bit in the GPIOB_PUR register.
GPIOB4
(A20)
37
M2
Schmitt
Input/
Output
Input
Port B GPIO — These four GPIO pins can be programmed as input or
output pins.
Output
Tri-stated Address Bus — A20 - A23 specify one of the address lines for
external program or data memory accesses.
Depending upon the state of the DRV bit in the EMI bus control register
(BCR), A20–A23 and EMI control signals are tri-stated when the external
bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
(prescaler_
clock)
Output
Output
Clock Outputs — can be used to monitor the prescaler_clock,
SYS_CLK, SYS_CLK2 or oscillator_clock on GPIOB4 through
GPIOB7, respectively.
GPIOB5
(A21)
(SYS_CLK)
46
47
N4
P3
After reset, the default state is GPIO.
These pins can also be used to extend the external address bus to its
full length or to view any of several system clocks. In these cases, the
GPIO_B_PER can be used to individually disable the GPIO. The
CLKOSR register in the SIM ( see Part 6.5.7) can then be used to
choose between address and clock functions.
GPIOB6
(A22)
(SYS_CLK2
)
GPIOB7
(A23)
48
M4
(oscillator_
clock)
56F8367 Technical Data, Rev. 3.0
22
Freescale Semiconductor
Preliminary
Signal Pins
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA
State
During
Reset
Signal
Name
Pin
No.
Ball No.
Type
Signal Description
D0
70
P10
Input/
Tri-stated Data Bus — D0 - D6 specify part of the data for external program or data
Output
memory accesses.
Depending upon the state of the DRV bit in the EMI bus control register
(BCR), D0–D6 are tri-stated when the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
(GPIOF9)
Input/
Input
Port F GPIO — These seven GPIO pins can be individually
Output
programmed as input or output pins.
D1
(GPIOF10)
71
83
86
88
89
90
N10
P14
L13
L14
L12
L11
After reset, these pins default to the EMI Data Bus function.
D2
(GPIOF11)
To deactivate the internal pull-up resistor, clear the appropriate GPIO
bit in the GPIOF_PUR register.
D3
(GPIOF12)
Example: GPIOF9, clear bit 9 in the GPIOF_PUR register.
D4
(GPIOF13)
D5
(GPIOF14)
D6
(GPIOF15)
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
23
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA
State
During
Reset
Signal
Name
Pin
No.
Ball No.
Type
Signal Description
D7
28
K1
Input/
Tri-stated Data Bus — D7 - D15 specify part of the data for external program or
Output
data memory accesses.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), D7 - D15 are tri-stated when the external bus is
inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
(GPIOF0)
Input/
Input
Port F GPIO — These nine GPIO pins can be individually
Output
programmed as input or output pins.
D8
(GPIOF1)
29
30
K3
K2
K4
A5
A4
B5
C4
A3
P5
At reset, these pins default to Data Bus functionality.
D9
(GPIOF2)
To deactivate the internal pull-up resistor, clear the appropriate GPIO
bit in the GPIOF_PUR register.
D10
(GPIOF3)
32
Example: GPIOF0, clear bit 0 in the GPIOF_PUR register.
D11
(GPIOF4)
149
150
151
152
153
52
D12
(GPIOF5)
D13
(GPIOF6)
D14
(GPIOF7)
D15
(GPIOF8)
RD
Output
Tri-stated Read Enable — RD is asserted during external memory read cycles.
When RD is asserted low, pins D0 - D15 become inputs and an
external device is enabled onto the data bus. When RD is deasserted
high, the external data is latched inside the device. When RD is
asserted, it qualifies the A0 - A23, PS, DS, and CSn pins. RD can be
connected directly to the OE pin of a static RAM or ROM.
Depending upon the state of the DRV bit in the EMI bus control register
(BCR), RD is tri-stated when the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
To deactivate the internal pull-up resistor, set the CTRL bit in the
SIM_PUDR register.
56F8367 Technical Data, Rev. 3.0
24
Freescale Semiconductor
Preliminary
Signal Pins
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA
State
During
Reset
Signal
Name
Pin
No.
Ball No.
Type
Signal Description
WR
51
L4
Output
Tri-stated Write Enable — WR is asserted during external memory write cycles.
When WR is asserted low, pins D0 - D15 become outputs and the
device puts data on the bus. When WR is deasserted high, the
external data is latched inside the external device. When WR is
asserted, it qualifies the A0 - A23, PS, DS, and CSn pins. WR can be
connected directly to the WE pin of a static RAM.
Depending upon the state of the DRV bit in the EMI bus control register
(BCR), WR is tri-stated when the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
To deactivate the internal pull-up resistor, set the CTRL bit in the
SIM_PUDR register.
PS
53
N6
Output
Tri-stated Program Memory Select — This signal is actually CS0 in the EMI,
which is programmed at reset for compatibility with the 56F80x PS
signal. PS is asserted low for external program memory access.
(CS0)
Depending upon the state of the DRV bit in the EMI bus control register
(BCR), CS0 is tri-stated when the external bus is inactive.
CS0 resets to provide the PS function as defined on the 56F80x
devices.
(GPIOD8)
Input/
Input
Port D GPIO — This GPIO pin can be individually programmed as an
Output
input or output pin.
To deactivate the internal pull-up resistor, clear bit 8 in the
GPIOD_PUR register.
DS
54
L5
Outpu
Tri-stated Data Memory Select — This signal is actually CS1 in the EMI, which
is programmed at reset for compatibility with the 56F80x DS signal. DS
is asserted low for external data memory access.
(CS1)
Depending upon the state of the DRV bit in the EMI bus control register
(BCR), CS1 is tri-stated when the external bus is inactive.
CS1 resets to provide the DS function as defined on the 56F80x
devices.
(GPIOD9)
Input/
Input
Port D GPIO — This GPIO pin can be individually programmed as an
Outputt
input or output pin.
To deactivate the internal pull-up resistor, clear bit 9 in the
GPIOD_PUR register.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
25
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA
State
During
Reset
Signal
Name
Pin
No.
Ball No.
Type
Signal Description
GPIOD0
(CS2)
55
P6
Input/
Output
Input
Port D GPIO — This GPIO pin can be individually programmed as an
input or output pin.
Output
Tri-stated Chip Select — CS2 may be programmed within the EMI module to act
as a chip select for specific areas of the external memory map.
Depending upon the state of the DRV bit in the EMI Bus Control
Register (BCR), CS2 is tri-stated when the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
(CAN2_TX)
Open
Drain
Output
FlexCAN2 Transmit Data — CAN output.
Output
At reset, this pin is configured as GPIO. This configuration can be
changed by setting bit 0 in the GPIO_D_PER register. Then change bit
4 in the SIM_GPS register to select the desired peripheral function.
To deactivate the internal pull-up resistor, clear bit 0 in the
GPIOD_PUR register.
GPIOD1
(CS3)
56
L6
Schmitt
Input/
Output
Input
Port D GPIO — This GPIO pin can be individually programmed as an
input or output pin.
Output
Tri-stated Chip Select — CS3 may be programmed within the EMI module to act
as a chip select for specific areas of the external memory map.
Depending upon the state of the DRV bit in the EMI Bus Control
Register (BCR), CS3 is tri-stated when the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
(CAN2_RX)
Schmitt
Input
Input
FlexCAN2 Receive Data — This is the CAN input. This pin has an
internal pull-up resistor.
At reset, this pin is configured as GPIO. This configuration can be
changed by setting bit 1 in the GPIO_D_PER register. Then change bit
5 in the SIM_GPS register to select the desired peripheral function.
To deactivate the internal pull-up resistor, clear bit 1 in the
GPIOD_PUR register.
56F8367 Technical Data, Rev. 3.0
26
Freescale Semiconductor
Preliminary
Signal Pins
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA
State
During
Reset
Signal
Name
Pin
No.
Ball No.
Type
Signal Description
GPIOD2
57
K6
Input/
Input
Port D GPIO — These four GPIO pins can be individually programmed
Output
as input or output pins.
(CS4)
Output
Tri-stated Chip Select — CS4 - CS7 may be programmed within the EMI module
to act as chip selects for specific areas of the external memory map.
GPIOD3
(CS5)
58
59
60
N7
P7
L7
Depending upon the state of the DRV bit in the EMI bus control register
(BCR), CS4 - CS7 are tri-stated when the external bus is inactive.
GPIOD4
(CS6)
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
GPIOD5
(CS7)
At reset, these pins are configured as GPIO.
To deactivate the internal pull-up resistor, clear the appropriate GPIO
bit in the GPIOD_PUR register.
Example: GPIOD2, clear bit 2 in the GPIOD_PUR register.
TXD0
4
B1
D2
P4
Output
Tri-stated Transmit Data — SCI0 transmit data output
(GPIOE0)
Input/
Output
Input
Port E GPIO — This GPIO pin can be individually programmed as an
input or output pin.
After reset, the default state is SCI output.
To deactivate the internal pull-up resistor, clear bit 0 in the
GPIOE_PUR register.
RXD0
5
Input
Input
Input
Receive Data — SCI0 receive data input
(GPIOE1)
Input/
Output
Port E GPIO — This GPIO pin can be individually programmed as an
input or output pin.
After reset, the default state is SCI output.
To deactivate the internal pull-up resistor, clear bit 1 in the
GPIOE_PUR register.
TXD1
49
Output
Tri-stated Transmit Data — SCI1 transmit data output
(GPIOD6)
Input/
Input
Port D GPIO — This GPIO pin can be individually programmed as an
Output
input or output pin.
After reset, the default state is SCI output.
To deactivate the internal pull-up resistor, clear bit 6 in the
GPIOD_PUR register.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
27
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA
State
During
Reset
Signal
Name
Pin
No.
Ball No.
Type
Signal Description
RXD1
50
N5
Input
Input
Input
Receive Data — SCI1 receive data input
(GPIOD7)
Input/
Port D GPIO — This GPIO pin can be individually programmed as an
Output
input or output pin.
After reset, the default state is SCI input.
To deactivate the internal pull-up resistor, clear bit 7 in the
GPIOD_PUR register.
TCK
TMS
137
138
D8
A8
Schmitt
Input
Input,
Test Clock Input — This input pin provides a gated clock to
pulled low synchronize the test logic and shift serial data to the JTAG/EOnCE
internally port. The pin is connected internally to a pull-down resistor.
Schmitt
Input
Input,
pulled
high
Test Mode Select Input — This input pin is used to sequence the
JTAG TAP controller’s state machine. It is sampled on the rising edge
of TCK and has an on-chip pull-up resistor.
internally
To deactivate the internal pull-up resistor, set the JTAG bit in the
SIM_PUDR register.
TDI
139
B8
Schmitt
Input
Input,
pulled
high
Test Data Input — This input pin provides a serial input data stream to
the JTAG/EOnCE port. It is sampled on the rising edge of TCK and
has an on-chip pull-up resistor.
internally
To deactivate the internal pull-up resistor, set the JTAG bit in the
SIM_PUDR register.
TDO
140
136
D7
D9
Output
Tri-stated Test Data Output — This tri-stateable output pin provides a serial
output data stream from the JTAG/EOnCE port. It is driven in the
shift-IR and shift-DR controller states, and changes on the falling edge
of TCK.
TRST
Schmitt
Input
Input,
pulled
high
Test Reset — As an input, a low signal on this pin provides a reset
signal to the JTAG TAP controller. To ensure complete hardware
reset, TRST should be asserted whenever RESET is asserted. The
internally only exception occurs in a debugging environment when a hardware
device reset is required and the JTAG/EOnCE module must not be
reset. In this case, assert RESET, but do not assert TRST.
To deactivate the internal pull-up resistor, set the JTAG bit in the
SIM_PUDR register.
56F8367 Technical Data, Rev. 3.0
28
Freescale Semiconductor
Preliminary
Signal Pins
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA
State
During
Reset
Signal
Name
Pin
No.
Ball No.
Type
Signal Description
Phase A — Quadrature Decoder 0, PHASEA input
TA0 — Timer A, Channel 0
PHASEA0
(TA0)
155
A2
Schmitt
Input
Input
Input
Schmitt
Input/
Output
(GPIOC4)
Schmitt
Input/
Input
Port C GPIO — This GPIO pin can be individually programmed as an
input or output pin.
Output
After reset, the default state is PHASEA0.
To deactivate the internal pull-up resistor, clear bit 4 of the
GPIOC_PUR register.
PHASEB0
(TA1)
156
B4
Schmitt
Input
Input
Input
Phase B — Quadrature Decoder 0, PHASEB input
Schmitt
Input/
TA1 — Timer A, Channel
Output
(GPIOC5)
Schmitt
Input/
Input
Port C GPIO — This GPIO pin can be individually programmed as an
input or output pin.
Output
After reset, the default state is PHASEB0.
To deactivate the internal pull-up resistor, clear bit 5 of the
GPIOC_PUR register.
INDEX0
(TA2)
157
A1
Schmitt
Input
Input
Input
Index — Quadrature Decoder 0, INDEX input
Schmitt
Input/
TA2 — Timer A, Channel 2
Output
(GPOPC6)
Schmitt
Input/
Input
Port C GPIO — This GPIO pin can be individually programmed as an
input or output pin.
Output
After reset, the default state is INDEX0.
To deactivate the internal pull-up resistor, clear bit 6 of the
GPIOC_PUR register.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
29
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA
State
During
Reset
Signal
Name
Pin
No.
Ball No.
Type
Signal Description
Home — Quadrature Decoder 0, HOME input
TA3 — Timer A, Channel 3
HOME0
(TA3)
158
B3
Schmitt
Input
Input
Input
Schmitt
Input/
Output
(GPIOC7)
Schmitt
Input/
Input
Port C GPIO — This GPIO pin can be individually programmed as an
input or output pin.
Output
After reset, the default state is HOME0.
To deactivate the internal pull-up resistor, clear bit 7 of the
GPIOC_PUR register.
SCLK0
146
A6
Schmitt
Input/
Output
Input
Input
SPI 0 Serial Clock — In the master mode, this pin serves as an
output, clocking slaved listeners. In slave mode, this pin serves as the
data clock input.
(GPIOE4)
Schmitt
Input/
Port E GPIO — This GPIO pin can be individually programmed as an
input or output pin.
Output
After reset, the default state is SCLK0.
To deactivate the internal pull-up resistor, clear bit 4 in the
GPIOE_PUR register.
MOSI0
148
D4
Input/
Output
Tri-stated SPI 0 Master Out/Slave In — This serial data pin is an output from a
master device and an input to a slave device. The master device
places data on the MOSI line a half-cycle before the clock edge the
slave device uses to latch the data.
(GPIOE5)
Input/
Input
Port E GPIO — This GPIO pin can be individually programmed as an
Output
input or output pin.
After reset, the default state is MOSI0.
To deactivate the internal pull-up resistor, clear bit 5 in the
GPIOE_PUR register.
56F8367 Technical Data, Rev. 3.0
30
Freescale Semiconductor
Preliminary
Signal Pins
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA
State
During
Reset
Signal
Name
Pin
No.
Ball No.
Type
Signal Description
MISO0
147
B6
Input/
Output
Input
SPI 0 Master In/Slave Out — This serial data pin is an input to a
master device and an output from a slave device. The MISO line of a
slave device is placed in the high-impedance state if the slave device
is not selected. The slave device places data on the MISO line a
half-cycle before the clock edge the master device uses to latch the
data.
(GPIOE6)
Input/
Input
Port E GPIO — This GPIO pin can be individually programmed as an
Output
input or output pin.
After reset, the default state is MISO0.
To deactivate the internal pull-up resistor, clear bit 6 in the
GPIOE_PUR register.
SS0
145
D5
Input
Input
Input
SPI 0 Slave Select — SS0 is used in slave mode to indicate to the SPI
module that the current transfer is to be received.
(GPIOE7)
Input/
Port E GPIO — This GPIO pin can be individually programmed as
Output
input or output pin.
After reset, the default state is SS0.
To deactivate the internal pull-up resistor, clear bit 7 in the
GPIOE_PUR register.
PHASEA1
(TB0)
6
C1
Schmitt
Input
Input
Input
Phase A1 — Quadrature Decoder 1, PHASEA input for decoder 1.
Schmitt
Input/
TB0 — Timer B, Channel 0
Output
(SCLK1)
Schmitt
Input/
Output
Input
Input
SPI 1 Serial Clock — In the master mode, this pin serves as an
output, clocking slaved listeners. In slave mode, this pin serves as the
data clock input. To activate the SPI function, set the PHSA_ALT bit in
the SIM_GPS register. For details, see Part 6.5.8.
(GPIOC0)
Schmitt
Input/
Port C GPIO — This GPIO pin can be individually programmed as an
input or output pin.
Output
In the 56F8367, the default state after reset is PHASEA1.
In the 56F8167, the default state is not one of the functions offered and
must be reconfigured.
To deactivate the internal pull-up resistor, clear bit 0 in the
GPIOC_PUR register.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
31
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA
State
During
Reset
Signal
Name
Pin
No.
Ball No.
Type
Signal Description
Phase B1 — Quadrature Decoder 1, PHASEB input for decoder 1.
TB1 — Timer B, Channel 1
PHASEB1
(TB1)
7
D1
Schmitt
Input
Input
Input
Schmitt
Input/
Output
(MOSI1)
Schmitt
Input/
Output
Tri-stated SPI 1 Master Out/Slave In — This serial data pin is an output from a
master device and an input to a slave device. The master device
places data on the MOSI line a half-cycle before the clock edge the
slave device uses to latch the data. To activate the SPI function, set
the PHSB_ALT bit in the SIM_GPS register. For details, see Part
6.5.8.
(GPIOC1)
Schmitt
Input/
Input
Port C GPIO — This GPIO pin can be individually programmed as an
input or output pin.
Output
In the 56F8367, the default state after reset is PHASEB1.
In the 56F8167, the default state is not one of the functions offered and
must be reconfigured.
To deactivate the internal pull-up resistor, clear bit 1 in the
GPIOC_PUR register.
INDEX1
(TB2)
8
E2
Schmitt
Input
Input
Input
Index1 — Quadrature Decoder 1, INDEX input
Schmitt
Input/
TB2 — Timer B, Channel 2
Output
(MISO1)
Schmitt
Input/
Output
Input
SPI 1 Master In/Slave Out — This serial data pin is an input to a
master device and an output from a slave device. The MISO line of a
slave device is placed in the high-impedance state if the slave device
is not selected. The slave device places data on the MISO line a
half-cycle before the clock edge the master device uses to latch the
data. To activate the SPI function, set the INDEX_ALT bit in the
SIM_GPS register. For details, see Part 6.5.8.
(GPIOC2)
Schmitt
Input/
Input
Port C GPIO — This GPIO pin can be individually programmed as an
input or output pin.
Output
In the 56F8367, the default state after reset is INDEX1.
In the 56F8167, the default state is not one of the functions offered and
must be reconfigured.
To deactivate the internal pull-up resistor, clear bit 2 in the
GPIOC_PUR register.
56F8367 Technical Data, Rev. 3.0
32
Freescale Semiconductor
Preliminary
Signal Pins
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA
State
During
Reset
Signal
Name
Pin
No.
Ball No.
Type
Signal Description
Home — Quadrature Decoder 1, HOME input
TB3 — Timer B, Channel 3
HOME1
(TB3)
9
E1
Schmitt
Input
Input
Input
Schmitt
Input/
Output
(SS1)
Schmitt
Input
Input
Input
SPI 1 Slave Select — In the master mode, this pin is used to arbitrate
multiple masters. In slave mode, this pin is used to select the slave. To
activate the SPI function, set the HOME_ALT bit in the SIM_GPS
register. For details, see Part 6.5.8.
(GPIOC3)
Schmitt
Input/
Port C GPIO — This GPIO pin can be individually programmed as an
input or output pin.
Output
In the 56F8367, the default state after reset is HOME1.
In the 56F8167, the default state is not one of the functions offered and
must be reconfigured.
To deactivate the internal pull-up resistor, clear bit 3 in the
GPIOC_PUR register.
PWMA0
PWMA1
PWMA2
PWMA3
PWMA4
PWMA5
ISA0
73
75
M11
P12
N11
M12
P13
N12
A11
Output
Tri-State PWMA0 - 5 — These are six PWMA outputs.
76
78
79
81
126
Schmitt
Input
Input
Input
ISA0 - 2 — These three input current status pins are used for
top/bottom pulse width correction in complementary channel operation
for PWMA.
(GPIOC8)
Schmitt
Input/
Output
Port C GPIO — These GPIO pins can be individually programmed as
input or output pins.
ISA1
(GPIOC9)
127
128
C11
D11
In the 56F8367, these pins default to ISA functionality after reset.
ISA2
(GPIOC10)
In the 56F8167, the default state is not one of the functions offered and
must be reconfigured.
To deactivate the internal pull-up resistor, clear the appropriate bit of
the GPIOC_PUR register. For details, see Part 6.5.8.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
33
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA
State
During
Reset
Signal
Name
Pin
No.
Ball No.
Type
Signal Description
FAULTA0
FAULTA1
FAULTA2
82
84
85
N13
N14
M13
Schmitt
Input
Input
FAULTA0 - 2 — These three fault input pins are used for disabling
selected PWMA outputs in cases where fault conditions originate
off-chip.
To deactivate the internal pull-up resistor, set the PWMA0 bit in the
SIM_PUDR register. For details, see Part 6.5.8.
FAULTA3
87
M14
Schmitt
Input
Input
FAULTA3 — This fault input pin is used for disabling selected PWMA
outputs in cases where fault conditions originate off-chip.
To deactivate the internal pull-up resistor, set the PWMA1 bit in the
SIM_PUDR register. See Part 6.5.6 for details.
PWMB0
PWMB1
PWMB2
PWMB3
PWMB4
PWMB5
ISB0
38
39
40
43
44
45
61
N1
P1
N2
N3
P2
M3
N8
Output
Tri-State PWMB0 - 5 — Six PWMB output pins.
Schmitt
Input
Input
Input
ISB0 - 2 — These three input current status pins are used for
top/bottom pulse width correction in complementary channel operation
for PWMB.
(GPIOD10)
Schmitt
Input/
Output
Port D GPIO — These GPIO pins can be individually programmed as
input or output pins.
ISB1
(GPIOD11)
63
64
L8
P8
At reset, these pins default to ISB functionality.
ISB2
(GPIOD12)
To deactivate the internal pull-up resistor, clear the appropriate bit of
the GPIOD_PUR register. For details, see Part 6.5.8.
FAULTB0
FAULTB1
FAULTB2
FAULTB3
ANA0
67
68
N9
L9
Schmitt
Input
Input
Input
FAULTB0 - 3 — These four fault input pins are used for disabling
selected PWMB outputs in cases where fault conditions originate
off-chip.
69
L10
P11
G13
H13
G12
F13
To deactivate the internal pull-up resistor, set the PWMB bit in the
SIM_PUDR register. For details, see Part 6.5.8.
72
100
101
102
103
Input
ANA0 - 3 — Analog inputs to ADC A, channel 0
ANA1
ANA2
ANA3
56F8367 Technical Data, Rev. 3.0
34
Freescale Semiconductor
Preliminary
Signal Pins
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA
State
During
Reset
Signal
Name
Pin
No.
Ball No.
Type
Signal Description
ANA4
ANA5
ANA6
ANA7
VREFH
104
105
106
107
113
F12
H14
G14
E13
D14
Input
Input
ANA4 - 7 — Analog inputs to ADC A, channel 1
Input
Input
VREFH — Analog Reference Voltage High. VREFH must be less than or
equal to VDDA_ADC.
VREFP
VREFMID
VREFN
112
111
110
109
D13
E14
F14
E12
Input/
Output
Input/
Output
VREFP, VREFMID & VREFN — Internal pins for voltage reference which
are brought off-chip so they can be bypassed. Connect to a 0.1µF low
ESR capacitor.
VREFLO
Input
Input
Input
Input
VREFLO — Analog Reference Voltage Low. This should normally be
connected to a low-noise VSS
.
ANB0
ANB1
ANB2
ANB3
ANB4
ANB5
ANB6
ANB7
116
117
118
119
120
121
122
123
C13
B14
C12
B13
A14
A13
B12
A12
E11
ANB0 - 3 — Analog inputs to ADC B, channel 0
Input
Input
ANB4 - 7 — Analog inputs to ADC B, channel 1
TEMP_SEN 108
Output
Output
Input
Temperature Sense Diode — This signal connects to an on-chip
diode that can be connected to one of the ADC inputs and used to
monitor the temperature of the die. Must be bypassed with a 0.01µF
capacitor.
SE
CAN_RX
CAN_TX
143
142
B7
D6
Schmitt
Input
FlexCAN Receive Data — This is the CAN input. This pin has an
internal pull-up resistor.
To deactivate the internal pull-up resistor, set the CAN bit in the
SIM_PUDR register.
Open
Drain
Open
Drain
FlexCAN Transmit Data — CAN output
Output
Output
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
35
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA
State
During
Reset
Signal
Name
Pin
No.
Ball No.
Type
Signal Description
TC0
133
A9
Schmitt
Input/
Input
TC0 — Timer C, Channel 0 and 1
Output
(GPIOE8)
Schmitt
Input/
Output
Input
Port E GPIO — These GPIO pins can be individually programmed as
input or output pins.
TC1
(GPIOE9)
135
129
B9
At reset, these pins default to Timer functionality.
To deactivate the internal pull-up resistor, clear the appropriate bit of
the GPIOE_PUR register.
TD0
B10
Schmitt
Input/
Output
Input
Input
TD0 - 3— Timer D, Channels 0, 1, 2 and 3
(GPIOE10)
Schmitt
Input/
Output
Port E GPIO — These GPIO pins can be individually programmed as
input or output pins.
TD1
(GPIOE11)
130
131
132
A10
D10
E10
At reset, these pins default to Timer functionality.
TD2
(GPIOE12)
To deactivate the internal pull-up resistor, clear the appropriate bit of
the GPIOE_PUR register. See Part 6.5.6 for details.
TD3
(GPIOE13)
IRQA
IRQB
65
66
K9
P9
Schmitt
Input
Input
External Interrupt Request A and B — The IRQA and IRQB inputs
are asynchronous external interrupt requests during Stop and Wait
mode operation. During other operating modes, they are synchronized
external interrupt requests, which indicate an external device is
requesting service. They can be programmed to be level-sensitive or
negative-edge triggered.
To deactivate the internal pull-up resistor, set the IRQ bit in the
SIM_PUDR register. See Part 6.5.6 for details.
56F8367 Technical Data, Rev. 3.0
36
Freescale Semiconductor
Preliminary
Signal Pins
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA
State
During
Reset
Signal
Name
Pin
No.
Ball No.
Type
Signal Description
RESET
98
J14
Schmitt
Input
Input
Reset — This input is a direct hardware reset on the processor. When
RESET is asserted low, the device is initialized and placed in the reset
state. A Schmitt trigger input is used for noise immunity. When the
RESET pin is deasserted, the initial chip operating mode is latched
from the EXTBOOT pin. The internal reset signal will be deasserted
synchronous with the internal clocks after a fixed number of internal
clocks.
To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware device reset is required and the
JTAG/EOnCE module must not be reset. In this case, assert RESET
but do not assert TRST.
Note: The internal Power-On Reset will assert on initial power-up.
To deactivate the internal pull-up resistor, set the RESET bit in the
SIM_PUDR register. See Part 6.5.6 for details.
RSTO
97
J13
Output
Output
Input
Reset Output — This output reflects the internal reset state of the
chip.
EXTBOOT
124
B11
Schmitt
Input
External Boot — This input is tied to VDD to force the device to boot
from off-chip memory (assuming that the on-chip Flash memory is not
in a secure state). Otherwise, it is tied to ground. For details, see
Table 4-4.
Note: When this pin is tied low, the customer boot software should
disable the internal pull-up resistor by setting the XBOOT bit of the
SIM_PUDR; see Part 6.5.6.
EMI_MODE 159
B2
Schmitt
Input
Input
External Memory Mode — This input is tied to VDD in order to enable
an extra four address lines, for a total of 20 address lines out of reset.
This function is also affected by EXTBOOT and the Flash security
mode. For details, see Table 4-4.
If a 20-bit address bus is not desired, then this pin is tied to ground.
Note: When this pin is tied low, the customer boot software should
disable the internal pull-up resistor by setting the EMI_MODE bit of the
SIM_PUDR; see Part 6.5.6.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
37
Part 3 On-Chip Clock Synthesis (OCCS)
3.1 Introduction
Refer to the OCCS chapter of the 56F8300 Peripheral User Manual for a full description of the OCCS.
The material contained here identifies the specific features of the OCCS design. Figure 3-1 shows the
specific OCCS block diagram to reference in the OCCS chapter of the 56F8300 Peripheral User Manual.
CLKMODE
XTAL
ZSRC
Crystal
OSC
Prescaler CLK
PLLCOD
SYS_CLK2
Source to SIM
EXTAL
PLLCID
PLLDB
PLL
F
F
OUT/2
OUT
Prescaler
÷ (1,2,4,8
Postscaler
÷ (1,2,4,8)
Postscaler CLK
÷
2
x (1 to 128)
)
Bus
Interface
Bus Interface & Control
LCK
Lock
Detector
Loss of Reference
Clock Interrupt
Loss of
Reference
Clock
Detector
Figure 3-1 OCCS Block Diagram
3.2 External Clock Operation
The system clock can be derived from an external crystal, ceramic resonator, or an external system clock
signal. To generate a reference frequency using the internal oscillator, a reference crystal or ceramic
resonator must be connected between the EXTAL and XTAL pins.
3.2.1
Crystal Oscillator
The internal oscillator is also designed to interface with a parallel-resonant crystal resonator in the
frequency range specified for the external crystal in Table 10-13. A recommended crystal oscillator circuit
is shown in Figure 3-2. Follow the crystal supplier’s recommendations when selecting a crystal, since
crystal parameters determine the component values required to provide maximum stability and reliable
start-up. The crystal and associated components should be mounted as near as possible to the EXTAL and
XTAL pins to minimize output distortion and start-up stabilization time.
56F8367 Technical Data, Rev. 3.0
38
Freescale Semiconductor
Preliminary
External Clock Operation
Crystal Frequency = 4 - 8MHz (optimized for 8MHz)
EXTAL XTAL EXTAL XTAL
RZ RZ
Sample External Crystal Parameters:
Rz = 750 KΩ
Note: If the operating temperature range is limited to
CLKMODE = 0
below 85oC (105oC junction), then Rz = 10 Meg Ω
CL1
CL2
Figure 3-2 Connecting to a Crystal Oscillator
Note:
The OCCS_COHL bit must be set to 1 when a crystal oscillator is used. The reset condition on the
OCCS_COHL bit is 0. Please see the COHL bit in the Oscillator Control (OSCTL) register, discussed
in the 56F8300 Peripheral User Manual.
3.2.2
Ceramic Resonator (Default)
It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system
design can tolerate the reduced signal integrity. A typical ceramic resonator circuit is shown in Figure 3-3.
Refer to the supplier’s recommendations when selecting a ceramic resonator and associated components.
The resonator and components should be mounted as near as possible to the EXTAL and XTAL pins.
Resonator Frequency = 4 - 8MHz (optimized for 8MHz)
3 Terminal
2 Terminal
Sample External Ceramic Resonator Parameters:
Rz = 750 KΩ
EXTAL XTAL
RZ
EXTAL XTAL
RZ
CLKMODE = 0
CL1
CL2
C1
C2
Figure 3-3 Connecting a Ceramic Resonator
Note:
The OCCS_COHL bit must be set to 0 when a ceramic resonator is used. The reset condition on the
OCCS_COHL bit is 0. Please see the COHL bit in the Oscillator Control (OSCTL) register, discussed
in the 56F8300 Peripheral User Manual.
3.2.3
External Clock Source
The recommended method of connecting an external clock is given in Figure 3-4. The external clock
source is connected to XTAL and the EXTAL pin is grounded. When using an external clock source, set
the OCCS_COHL bit high as well.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
39
Note: When using an external clocking source with
this configuration, the input “CLKMODE” should be
high and the COHL bit in the OSCTL register
should be set to 1.
XTAL
EXTAL
VSS
External
Clock
Figure 3-4 Connecting an External Clock Register
3.3 Registers
When referring to the register definitions for the OCCS in the 56F8300 Peripheral User Manual, use the
register definitions without the internal Relaxation Oscillator, since the 56F8367/56F8167 do NOT
contain this oscillator.
Part 4 Memory Operating Modes (MEM)
4.1 Introduction
The 56F8367 and 56F8167 devices are 16-bit motor-control chips based on the 56800E core. These parts
use a Harvard-style architecture with two independent memory spaces for Data and Program. On-chip
RAM and Flash memory are used in both spaces.
This chapter provides memory maps for:
•
•
Program Address Space including the Interrupt Vector Table
Data Address Space including the EOnCE Memory and Peripheral Memory Maps
On-chip memory sizes for each device are summarized in Table 4-1. Flash memories’ restrictions are
identified in the “Use Restrictions” column of Table 4-1.
Note: Data Flash and Program RAM are NOT available on the 56F8167 device.
Table 4-1 Chip Memory Configurations
On-Chip Memory
56F8367
56F8167
Use Restrictions
Program Flash
512KB
512KB
Erase/Program via Flash interface unit and word writes to
CDBW
Data Flash
32KB
—
Erase/Program via Flash interface unit and word writes to
CDBW. Data Flash can be read via one of CDBR or XDB2, but
not both simultaneously
Program RAM
Data RAM
4KB
32KB
32KB
—
None
32KB
32KB
None
Program Boot Flash
Erase/Program via Flash Interface unit and word to CDWB
56F8367 Technical Data, Rev. 3.0
40
Freescale Semiconductor
Preliminary
Program Map
4.2 Program Map
The operating mode control bits (MA and MB) in the Operating Mode Register (OMR) control the
Program memory map. At reset, these bits are set as indicated in Table 4-2. Table 4-4 shows the memory
map configurations that are possible at reset. After reset, the OMR MA bit can be changed and will have
an effect on the P-space memory map, as shown in Table 4-3. Changing the OMR MB bit will have no
effect.
Table 4-2 OMR MB/MA Value at Reset
OMR MB =
OMR MA =
Flash Secured
State1, 2
Chip Operating Mode
EXTBOOT Pin
Mode 0 – Internal Boot; EMI is configured to use 16 address lines; Flash Memory is
secured; external P-space is not allowed; the EOnCE is disabled
0
0
0
Not valid; cannot boot externally if the Flash is secured and will actually configure to
00 state
1
Mode 0 – Internal Boot; EMI is configured to use 16 address lines
1
1
0
1
Mode 1 – External Boot; Flash Memory is not secured; EMI configuration is
determined by the state of the EMI_MODE pin
1. This bit is only configured at reset. If the Flash secured state changes, this will not be reflected in MB until the next reset.
2. Changing MB in software will not affect Flash memory security.
Table 4-3 Changing OMR MA Value During Normal Operation
OMR MA
Chip Operating Mode
Use internal P-space memory map configuration
Use external P-space memory map configuration – If MB = 0 at reset, changing this bit has no effect.
0
1
The device’s external memory interface (EMI) can operate much like the 56F80x family’s EMI, or it can
be operated in a mode similar to that used on other products in the 56800E family. Initially, CS0 and CS1
are configured as PS and DS, in a mode compatible with earlier 56800 devices.
Eighteen address lines are required to shadow the first 192K of internal program space when booting
externally for development purposes. Therefore, the entire complement of on-chip memory cannot be
accessed using a 16-bit 56800-compatible address bus. To address this situation, the EMI_MODE pin can
be used to configure four GPIO pins as Address[19:16] upon reset (Software reconfiguration of the highest
address lines [A20-23] is required if the full address range is to be used.)
The EMI_MODE bit also affects the reset vector address, as provided in Table 4-4. Additional pins must
be configured as address or chip select signals to access addresses at P: $10 0000 and above.
Note: Program RAM is NOT available on the 56F8167 device.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
41
Table 4-4 Program Memory Map at Reset
Mode 11 (MA = 1)
Mode 0 (MA = 0)
Begin/End
Address
Internal Boot
External Boot
EMI_MODE = 02,3
EMI_MODE = 14
Internal Boot
16-Bit External Address Bus
16-Bit External Address Bus
20-Bit External Address Bus
External Program Memory6
P:$1F FFFF
P:$10 0000
External Program Memory5
External Program Memory5
P:$0F FFFF
P:$05 0000
P:$04 FFFF
P:$04 F800
On-Chip Program RAM
4KB
P:$04 F7FF
P:$04 4000
Reserved
92KB
P:$04 3FFF
P:$04 0000
Boot Flash
32KB
COP Reset Address = 04 0002
Boot Location = 04 0000
Boot Flash
32KB
(Not Used for Boot in this Mode)
External Program Memory
COP Reset Address = 04 00027
Boot Location = 04 00007
Internal Program Flash8
256KB
Internal Program Flash
256KB
P:$03 FFFF
P:$02 0000
P:$01 FFFF
P:$01 0000
Internal Program Flash
128KB
Internal Program Flash8
256KB
P:$00 FFFF
P:$00 0000
External Program Memory
COP Reset Address = 00 0002
Boot Location = 00 0000
1. If Flash Security Mode is enabled, EXTBOOT Mode 1 cannot be used. See Security Features, Part 7.
2. This mode provides maximum compatibility with 56F80x parts while operating externally.
3. “EMI_MODE = 0” when EMI_MODE pin is tied to ground at boot up.
4. “EMI_MODE = 1” when EMI_MODE pin is tied to VDD at boot up.
5. Not accessible in reset configuration, since the address is above P:$00 FFFF. The higher bit address/GPIO (and/or chip
selects) pins must be reconfigured before this external memory is accessible.
6. Not accessible in reset configuration, since the address is above P:$0F FFFF. The higher bit address/GPIO (and/or chip
selects) pins must be reconfigured before this external memory is accessible.
7. Booting from this external address allows prototyping of the internal Boot Flash.
8. Two independent program flash blocks allow one to be programmed/erased while executing from another. Each block must
have its own mass erase.
4.3 Interrupt Vector Table
Table 4-5 provides the reset and interrupt priority structure, including on-chip peripherals. The table is
organized with higher-priority vectors at the top and lower-priority interrupts lower in the table. The
priority of an interrupt can be assigned to different levels, as indicated, allowing some control over
interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For a selected priority
level, the lowest vector number has the highest priority.
56F8367 Technical Data, Rev. 3.0
42
Freescale Semiconductor
Preliminary
Interrupt Vector Table
The location of the vector table is determined by the Vector Base Address (VBA) register. Please see Part
5.6.11 for the reset value of the VBA.
In some configurations, the reset address and COP reset address will correspond to vector 0 and 1 of the
interrupt vector table. In these instances, the first two locations in the vector table must contain branch or
JMP instructions. All other entries must contain JSR instructions.
Note: PWMA, FlexCAN, Quadrature Decoder 1, and Quad Timers B and D are NOT available on the
56F8167 device.
1
Table 4-5 Interrupt Vector Table Contents
Vector
Number
Priority
Level
Vector Base
Address +
Peripheral
Interrupt Function
Reserved for Reset Overlay2
Reserved for COP Reset Overlay2
Illegal Instruction
core
2
3
4
5
6
7
3
3
P:$04
P:$06
P:$08
P:$0A
P:$0C
P:$0E
core
core
core
core
core
SW Interrupt 3
3
HW Stack Overflow
Misaligned Long Word Access
OnCE Step Counter
OnCE Breakpoint Unit 0
Reserved
3
1-3
1-3
core
core
core
9
1-3
1-3
1-3
P:$12
P:$14
P:$16
OnCE Trace Buffer
OnCE Transmit Register Empty
OnCE Receive Register Full
Reserved
10
11
core
core
core
core
core
14
15
16
17
18
2
1
P:$1C
P:$1E
P:$20
P:$22
P:$24
SW Interrupt 2
SW Interrupt 1
0
SW Interrupt 0
0-2
0-2
IRQA
IRQB
Reserved
LVI
PLL
FM
FM
FM
20
21
22
23
24
0-2
0-2
0-2
0-2
0-2
P:$28
P:$2A
P:$2C
P:$2E
P:$30
Low-Voltage Detector (power sense)
PLL
FM Access Error Interrupt
FM Command Complete
FM Command, data and address Buffers Empty
Reserved
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
43
1
Table 4-5 Interrupt Vector Table Contents (Continued)
Vector
Number
Priority
Level
Vector Base
Address +
Peripheral
Interrupt Function
FLEXCAN
FLEXCAN
FLEXCAN
FLEXCAN
GPIOF
26
27
28
29
30
31
32
33
34
35
0-2
0-2
0-2
0-2
0-2
0-2
0-2
0-2
0-2
0-2
P:$34
P:$36
P:$38
P:$3A
P:$3C
P:$3E
P:$40
P:$42
P:$44
P:$46
FLEXCAN Bus Off
FLEXCAN Error
FLEXCAN Wake Up
FLEXCAN Message Buffer Interrupt
GPIO F
GPIOE
GPIO E
GPIOD
GPIO D
GPIOC
GPIO C
GPIOB
GPIO B
GPIOA
GPIO A
Reserved
SPI1
SPI1
SPI0
SPI0
SCI1
SCI1
38
39
40
41
42
43
0-2
0-2
0-2
0-2
0-2
0-2
P:$4C
P:$4E
P:$50
P:$52
P:$54
P:$56
SPI 1 Receiver Full
SPI 1 Transmitter Empty
SPI 0 Receiver Full
SPI 0 Transmitter Empty
SCI 1 Transmitter Empty
SCI 1 Transmitter Idle
Reserved
SCI1
45
46
47
48
49
50
0-2
0-2
0-2
0-2
0-2
0-2
P:$5A
P:$5C
P:$5E
P:$60
P:$62
P:$64
SCI 1 Receiver Error
SCI 1 Receiver Full
Quadrature Decoder #1 Home Switch or Watchdog
Quadrature Decoder #1 INDEX Pulse
Quadrature Decoder #0 Home Switch or Watchdog
Quadrature Decoder #0 INDEX Pulse
Reserved
SCI1
DEC1
DEC1
DEC0
DEC0
TMRD
TMRD
TMRD
TMRD
TMRC
TMRC
TMRC
TMRC
TMRB
52
53
54
55
56
57
58
59
60
0-2
0-2
0-2
0-2
0-2
0-2
0-2
0-2
0-2
P:$68
P:$6A
P:$6C
P:$6E
P:$70
P:$72
P:$74
P:$76
P:$78
Timer D, Channel 0
Timer D, Channel 1
Timer D, Channel 2
Timer D, Channel 3
Timer C, Channel 0
Timer C, Channel 1
Timer C, Channel 2
Timer C, Channel 3
Timer B, Channel 0
56F8367 Technical Data, Rev. 3.0
44
Freescale Semiconductor
Preliminary
Interrupt Vector Table
1
Table 4-5 Interrupt Vector Table Contents (Continued)
Vector
Number
Priority
Level
Vector Base
Address +
Peripheral
Interrupt Function
TMRB
TMRB
TMRB
TMRA
TMRA
TMRA
TMRA
SCI0
61
62
63
64
65
66
67
68
69
0-2
0-2
0-2
0-2
0-2
0-2
0-2
0-2
0-2
P:$7A
P:$7C
P:$7E
P:$80
P:$82
P:$84
P:$86
P:$88
P:$8A
Timer B, Channel 1
Timer B, Channel 2
Timer B, Channel 3
Timer A, Channel 0
Timer A, Channel 1
Timer A, Channel 2
Timer A, Channel 3
SCI 0 Transmitter Empty
SCI 0 Transmitter Idle
Reserved
SCI0
SCI0
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
0-2
0-2
0-2
0-2
0-2
0-2
0-2
0-2
0-2
0-2
- 1
P:$8E
P:$90
P:$92
P:$94
P:$96
P:$98
P:$9A
P:$9C
P:$9E
P:$A0
P:$A2
P:$A4
P:$A6
P:$A8
P:$AA
SCI 0 Receiver Error
SCI 0 Receiver Full
SCI0
ADCB
ADC B Conversion Compete / End of Scan
ADC A Conversion Complete / End of Scan
ADC B Zero Crossing or Limit Error
ADC A Zero Crossing or Limit Error
Reload PWM B
ADCA
ADCB
ADCA
PWMB
PWMA
PWMB
PWMA
core
Reload PWM A
PWM B Fault
PWM A Fault
SW Interrupt LP
FLEXCAN2
FLEXCAN2
FLEXCAN2
FLEXCAN2
0-2
0-2
0-2
0-2
FlexCAN Bus Off
FlexCAN Error
FlexCAN Wake Up
FlexCAN Message Buffer Interrupt
1. Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced from the
vector table, providing only 19 bits of address.
2. If the VBA is set to $0200 (or VBA = 0000 for Mode 1, EMI_MODE = 0), the first two locations of the vector table are the chip
reset addresses; therefore, these locations are not interrupt vectors.
2.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
45
4.4 Data Map
Note: Data Flash is NOT available on the 56F8167 device.
1
Table 4-6 Data Memory Map
Begin/End
Address
EX = 02
EX = 1
X:$FF FFFF
X:$FF FF00
EOnCE
256 locations allocated
EOnCE
256 locations allocated
X:$FF FEFF
X:$01 0000
External Memory
External Memory
X:$00 FFFF
X:$00 F000
On-Chip Peripherals
4096 locations allocated
On-Chip Peripherals
4096 locations allocated
X:$00 EFFF
X:$00 8000
External Memory
External Memory
X:$00 7FFF
X:$00 4000
On-Chip Data Flash
32KB
X:$00 3FFF
X:$00 0000
On-Chip Data RAM
32KB3
1. All addresses are 16-bit Word addresses, not byte addresses.
2. In the Operation Mode Register (OMR).
3. The Data RAM is organized as an 8K x 32-bit memory to allow single-cycle, long-word operations.
4.5 Flash Memory Map
Figure 4-1 illustrates the Flash Memory (FM) map on the system bus.
The Flash Memory is divided into three functional blocks. The Program and boot memories reside on the
Program Memory buses. They are controlled by one set of banked registers. Data Memory Flash resides
on the Data Memory buses and is controlled separately by its own set of banked registers.
The top nine words of the Program Memory Flash are treated as special memory locations. The content of
these words is used to control the operation of the Flash Controller. Because these words are part of the
Flash Memory content, their state is maintained during power down and reset. During chip initialization,
the content of these memory locations is loaded into Flash Memory control registers, detailed in the Flash
Memory chapter of the 56F8300 Peripheral User Manual. These configuration parameters are located
between $03_FFF7 and $03_FFFF.
56F8367 Technical Data, Rev. 3.0
46
Freescale Semiconductor
Preliminary
Flash Memory Map
Program Memory
Data Memory
FM_BASE + $14
FM_BASE + $00
BOOT_FLASH_START + $3FFF
Banked Registers
32KB
Boot
Unbanked Registers
BOOT_FLASH_START = $04_0000
PROG_FLASH_START + $03_FFFF
FM_PROG_MEM_TOP = $01_FFFF
Configure Field
DATA_FLASH_START + $3FFF
DATA_FLASH_START + $0000
256KB
Program
32KB
Note: Data Flash is
NOT available in the
56F8167 device.
BLOCK 1 Odd (2 Bytes) $02_0003
BLOCK 1 Even (2 Bytes) $02_0002
BLOCK 1 Odd (2 Bytes) $02_0001
BLOCK 1 Even (2 Bytes) $02_0000
PROG_FLASH_START + $02_0000
PROG_FLASH_START + $01_FFFF
256KB
Program
BLOCK 0 Odd (2 Bytes) $00_0003
BLOCK 0 Even (2 Bytes) $00_0002
BLOCK 0 Odd (2 Bytes) $00_0001
BLOCK 0 Even (2 Bytes) $00_0000
PROG_FLASH_START = $00_0000
Figure 4-1 Flash Array Memory Maps
Table 4-7 shows the page and sector sizes used within each Flash memory block on the chip.
Note: Data Flash is NOT available on the 56F8167 device.
Table 4-7 Flash Memory Partitions
Flash Size
Sectors
Sector Size
Page Size
Program Flash
Data Flash
512KB
32KB
32KB
16
16
4
16K x 16 bits
1024 x 16 bits
4K x 16 bits
1024 x 16 bits
256 x 16 bits
512 x 16 bits
Boot Flash
Please see 56F8300 Peripheral User Manual for additional Flash information.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
47
4.6 EOnCE Memory Map
Table 4-8 EOnCE Memory Map
Address
Register Acronym
Register Name
Reserved
X:$FF FF8A
X:$FF FF8E
OESCR
External Signal Control Register
Reserved
OBCNTR
Breakpoint Unit [0] Counter
Reserved
X:$FF FF90
X:$FF FF91
X:$FF FF92
X:$FF FF93
X:$FF FF94
X:$FF FF95
X:$FF FF96
X:$FF FF97
X:$FF FF98
X:$FF FF99
X:$FF FF9A
X:$FF FF9B
X:$FF FF9C
X:$FF FF9D
X:$FF FF9E
X:$FF FF9F
:X:$FF FFA0
OBMSK (32 bits)
Breakpoint 1 Unit [0] Mask Register
Breakpoint 1 Unit [0] Mask Register
Breakpoint 2 Unit [0] Address Register
Breakpoint 2 Unit [0] Address Register
Breakpoint 1 Unit [0] Address Register
Breakpoint 1 Unit [0] Address Register
Breakpoint Unit [0] Control Register
Breakpoint Unit [0] Control Register
Trace Buffer Register Stages
Trace Buffer Register Stages
Trace Buffer Pointer Register
Trace Buffer Control Register
Peripheral Base Address Register
Status Register
—
OBAR2 (32 bits)
—
OBAR1 (24 bits)
—
OBCR (24 bits)
—
OTB (21-24 bits/stage)
—
OTBPR (8 bits)
OTBCR
OBASE (8 bits)
OSR
OSCNTR (24 bits)
—
Instruction Step Counter
Instruction Step Counter
OCR (bits)
Control Register
Reserved
X:$FF FFFC
X:$FF FFFD
X:$FF FFFE
X:$FF FFFF
OCLSR (8 bits)
Core Lock / Unlock Status Register
Transmit and Receive Status and Control Register
Transmit Register / Receive Register
OTXRXSR (8 bits)
OTX / ORX (32 bits)
OTX1 / ORX1
Transmit Register Upper Word
Receive Register Upper Word
56F8367 Technical Data, Rev. 3.0
48
Freescale Semiconductor
Preliminary
Peripheral Memory Mapped Registers
4.7 Peripheral Memory Mapped Registers
On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may
be accessed with the same addressing modes used for ordinary Data memory, except all peripheral
registers should be read/written using word accesses only.
Table 4-9 summarizes base addresses for the set of peripherals on the 56F8367 and 56F8167 devices.
Peripherals are listed in order of the base address.
The following tables list all of the peripheral registers required to control or access the peripherals.
Note: Features in italics are NOT available on the 56F8167 device.
Table 4-9 Data Memory Peripheral Base Address Map Summary
Peripheral
Prefix
Base Address
Table Number
External Memory Interface
Timer A
EMI
X:$00 F020
X:$00 F040
X:$00 F080
X:$00 F0C0
X:$00 F100
X:$00 F140
X:$00 F160
X:$00 F180
X:$00 F190
X:$00 F1A0
X:$00 F200
X:$00 F240
X:$00 F270
X:$00 F280
X:$00 F290
X:$00 F2A0
X:$00 F2B0
X:$00 F2C0
X:$00 F2D0
X:$00 F2E0
X:$00 F300
X:$00 F310
X:$00 F320
X:$00 F330
X:$00 F340
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
4-23
4-24
4-25
4-26
4-27
4-28
4-29
4-30
4-31
4-32
4-33
4-34
TMRA
TMRB
TMRC
TMRD
PWMA
PWMB
DEC0
DEC1
ITCN
Timer B
Timer C
Timer D
PWM A
PWM B
Quadrature Decoder 0
Quadrature Decoder 1
ITCN
ADC A
ADCA
ADCB
ADC B
Temperature Sensor
SCI #0
TSENSOR
SCI0
SCI #1
SCI1
SPI #0
SPI0
SPI #1
SPI1
COP
COP
PLL, OSC
GPIO Port A
GPIO Port B
GPIO Port C
GPIO Port D
GPIO Port E
GPIO Port F
CLKGEN
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
GPIOF
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
49
Table 4-9 Data Memory Peripheral Base Address Map Summary (Continued)
Peripheral
Prefix
Base Address
Table Number
SIM
SIM
LVI
FM
X:$00 F350
X:$00 F360
X:$00 F400
X:$00 F800
X:$00 FA00
4-35
4-36
4-37
4-38
4-39
Power Supervisor
FM
FlexCAN
FC
FlexCAN2
FC2
Table 4-10 External Memory Integration Registers Address Map
(EMI_BASE = $00 F020)
Register Acronym Address Offset
Register Description
Reset Value
Chip Select Base Address Register 0
0x0004 = 64K when EXTBOOT = 0 or
EMI_MODE = 0
CSBAR 0
$0
0x0008 = 1M when EMI_MODE = 1
(Selects entire program space for
SC0)
Chip Select Base Address Register 1
0x0004 = 64K when EMI_MODE = 0
0x0008 = 1M when EMI_MODE = 1
CSBAR 1
$1
(Selects A0 - 19 addressable data
space for CS1)
Chip Select Base Address Register 2
Chip Select Base Address Register 3
Chip Select Base Address Register 4
Chip Select Base Address Register 5
Chip Select Base Address Register 6
Chip Select Base Address Register 7
Chip Select Option Register 0
CSBAR 2
CSBAR 3
CSBAR 4
CSBAR 5
CSBAR 6
CSBAR 7
CSOR 0
$2
$3
$4
$5
$6
$7
$8
0x5FCB programmed for chip select
for program space, word wide, read
and write, 11 waits
Chip Select Option Register 1
0x5FAB programmed for chip select
for data space, word wide, read and
write, 11 waits
CSOR 1
$9
Chip Select Option Register 2
Chip Select Option Register 3
Chip Select Option Register 4
Chip Select Option Register 5
Chip Select Option Register 6
Chip Select Option Register 7
CSOR 2
CSOR 3
CSOR 4
CSOR 5
CSOR 6
CSOR 7
$A
$B
$C
$D
$E
$F
56F8367 Technical Data, Rev. 3.0
50
Freescale Semiconductor
Preliminary
Peripheral Memory Mapped Registers
Table 4-10 External Memory Integration Registers Address Map (Continued)
(EMI_BASE = $00 F020)
Register Acronym Address Offset
Register Description
Chip Select Timing Control Register 0
Chip Select Timing Control Register 1
Chip Select Timing Control Register 2
Chip Select Timing Control Register 3
Chip Select Timing Control Register 4
Chip Select Timing Control Register 5
Chip Select Timing Control Register 6
Chip Select Timing Control Register 7
Bus Control Register
Reset Value
CSTC 0
CSTC 1
CSTC 2
CSTC 3
CSTC 4
CSTC 5
CSTC 6
CSTC 7
BCR
$10
$11
$12
$13
$14
$15
$16
$17
$18
0x016B sets the default number of
wait states to 11 for both read and
write accesses
Table 4-11 Quad Timer A Registers Address Map
(TMRA_BASE = $00 F040)
Register Acronym
Address Offset
Register Description
Compare Register 1
TMRA0_CMP1
TMRA0_CMP2
TMRA0_CAP
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
Compare Register 2
Capture Register
TMRA0_LOAD
TMRA0_HOLD
TMRA0_CNTR
TMRA0_CTRL
TMRA0_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMRA0_CMPLD1
TMRA0_CMPLD2
TMRA0_COMSCR
TMRA1_CMP1
TMRA1_CMP2
TMRA1_CAP
TMRA1_LOAD
TMRA1_HOLD
TMRA1_CNTR
TMRA1_CTRL
TMRA1_SCR
$10
$11
$12
$13
$14
$15
$16
$17
Compare Register 1
Compare Register 2
Capture Register
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
51
Table 4-11 Quad Timer A Registers Address Map (Continued)
(TMRA_BASE = $00 F040)
Register Acronym
Address Offset
Register Description
Comparator Load Register 1
TMRA1_CMPLD1
TMRA1_CMPLD2
TMRA1_COMSCR
$18
$19
$1A
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMRA2_CMP1
TMRA2_CMP2
TMRA2_CAP
$20
$21
$22
$23
$24
$25
$26
$27
$28
$29
$2A
Compare Register 1
Compare Register 2
Capture Register
TMRA2_LOAD
TMRA2_HOLD
TMRA2_CNTR
TMRA2_CTRL
TMRA2_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMRA2_CMPLD1
TMRA2_CMPLD2
TMRA2_COMSCR
TMRA3_CMP1
TMRA3_CMP2
TMRA3_CAP
$30
$31
$32
$33
$34
$35
$36
$37
$38
$39
$3A
Compare Register 1
Compare Register 2
Capture Register
TMRA3_LOAD
TMRA3_HOLD
TMRA3_CNTR
TMRA3_CTRL
TMRA3_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
TMRA3_CMPLD1
TMRA3_CMPLD2
TMRA3_COMSCR
Table 4-12 Quad Timer B Registers Address Map
(TMRB_BASE = $00 F080)
Quad Timer B is NOT available in the 56F8167 device
Register Acronym
Address Offset
Register Description
Compare Register 1
TMRB0_CMP1
TMRB0_CMP2
TMRB0_CAP
TMRB0_LOAD
TMRB0_HOLD
$0
$1
$2
$3
$4
Compare Register 2
Capture Register
Load Register
Hold Register
56F8367 Technical Data, Rev. 3.0
52
Freescale Semiconductor
Preliminary
Peripheral Memory Mapped Registers
Table 4-12 Quad Timer B Registers Address Map (Continued)
(TMRB_BASE = $00 F080)
Quad Timer B is NOT available in the 56F8167 device
Register Acronym
Address Offset
Register Description
TMRB0_CNTR
TMRB0_CTRL
$5
$6
$7
$8
$9
$A
Counter Register
Control Register
TMRB0_SCR
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMRB0_CMPLD1
TMRB0_CMPLD2
TMRB0_COMSCR
TMRB1_CMP1
TMRB1_CMP2
TMRB1_CAP
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1A
Compare Register 1
Compare Register 2
Capture Register
TMRB1_LOAD
TMRB1_HOLD
TMRB1_CNTR
TMRB1_CTRL
TMRB1_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMRB1_CMPLD1
TMRB1_CMPLD2
TMRB1_COMSCR
TMRB2_CMP1
TMRB2_CMP2
TMRB2_CAP
$20
$21
$22
$23
$24
$25
$26
$27
$28
$29
$2A
Compare Register 1
Compare Register 2
Capture Register
TMRB2_LOAD
TMRB2_HOLD
TMRB2_CNTR
TMRB2_CTRL
TMRB2_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMRB2_CMPLD1
TMRB2_CMPLD2
TMRB2_COMSCR
TMRB3_CMP1
TMRB3_CMP2
$30
$31
Compare Register 1
Compare Register 2
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
53
Table 4-12 Quad Timer B Registers Address Map (Continued)
(TMRB_BASE = $00 F080)
Quad Timer B is NOT available in the 56F8167 device
Register Acronym
Address Offset
Register Description
TMRB3_CAP
$32
$33
$34
$35
$36
$37
$38
$39
$3A
Capture Register
Load Register
TMRB3_LOAD
TMRB3_HOLD
TMRB3_CNTR
TMRB3_CTRL
TMRB3_SCR
Hold Register
Counter Register
Control Register
Status and Control Register
TMRB3_CMPLD1
TMRB3_CMPLD2
TMRB3_COMSCR
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Table 4-13 Quad Timer C Registers Address Map
(TMRC_BASE = $00 F0C0)
Register Acronym
Address Offset
Register Description
Compare Register 1
TMRC0_CMP1
TMRC0_CMP2
TMRC0_CAP
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
Compare Register 2
Capture Register
TMRC0_LOAD
TMRC0_HOLD
TMRC0_CNTR
TMRC0_CTRL
TMRC0_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMRC0_CMPLD1
TMRC0_CMPLD2
TMRC0_COMSCR
TMRC1_CMP1
TMRC1_CMP2
TMRC1_CAP
TMRC1_LOAD
TMRC1_HOLD
TMRC1_CNTR
TMRC1_CTRL
TMRC1_SCR
$10
$11
$12
$13
$14
$15
$16
$17
Compare Register 1
Compare Register 2
Capture Register
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
56F8367 Technical Data, Rev. 3.0
54
Freescale Semiconductor
Preliminary
Peripheral Memory Mapped Registers
Table 4-13 Quad Timer C Registers Address Map (Continued)
(TMRC_BASE = $00 F0C0)
Register Acronym
Address Offset
$18
Register Description
Comparator Load Register 1
TMRC1_CMPLD1
TMRC1_CMPLD2
TMRC1_COMSCR
$19
$1A
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMRC2_CMP1
TMRC2_CMP2
TMRC2_CAP
$20
$21
$22
$23
$24
$25
$26
$27
$28
$29
$2A
Compare Register 1
Compare Register 2
Capture Register
TMRC2_LOAD
TMRC2_HOLD
TMRC2_CNTR
TMRC2_CTRL
TMRC2_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMRC2_CMPLD1
TMRC2_CMPLD2
TMRC2_COMSCR
TMRC3_CMP1
TMRC3_CMP2
TMRC3_CAP
$30
$31
$32
$33
$34
$35
$36
$37
$38
$39
$3A
Compare Register 1
Compare Register 2
Capture Register
TMRC3_LOAD
TMRC3_HOLD
TMRC3_CNTR
TMRC3_CTRL
TMRC3_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
TMRC3_CMPLD1
TMRC3_CMPLD2
TMRC3_COMSCR
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
55
Table 4-14 Quad Timer D Registers Address Map
(TMRD_BASE = $00 F100)
Quad Timer D is NOT available in the 56F8167 device
Register Acronym
Address Offset
Register Description
Compare Register 1
TMRD0_CMP1
TMRD0_CMP2
TMRD0_CAP
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
Compare Register 2
Capture Register
TMRD0_LOAD
TMRD0_HOLD
TMRD0_CNTR
TMRD0_CTRL
TMRD0_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMRD0_CMPLD1
TMRD0_CMPLD2
TMRD0_COMSCR
TMRD1_CMP1
TMRD1_CMP2
TMRD1_CAP
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1A
Compare Register 1
Compare Register 2
Capture Register
TMRD1_LOAD
TMRD1_HOLD
TMRD1_CNTR
TMRD1_CTRL
TMRD1_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMRD1_CMPLD1
TMRD1_CMPLD2
TMRD1_COMSCR
TMRD2_CMP1
TMRD2_CMP2
TMRD2_CAP
TMRD2_LOAD
TMRD2_HOLD
TMRD2_CNTR
TMRD2_CTRL
TMRD2_SCR
$20
$21
$22
$23
$24
$25
$26
$27
Compare Register 1
Compare Register 2
Capture Register
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
56F8367 Technical Data, Rev. 3.0
56
Freescale Semiconductor
Preliminary
Peripheral Memory Mapped Registers
Table 4-14 Quad Timer D Registers Address Map (Continued)
(TMRD_BASE = $00 F100)
Quad Timer D is NOT available in the 56F8167 device
Register Acronym
Address Offset
Register Description
Comparator Load Register 1
TMRD2_CMPLD1
TMRD2_CMPLD2
TMRD2_COMSCR
$28
$29
$2A
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMRD3_CMP1
TMRD3_CMP2
TMRD3_CAP
$30
$31
$32
$33
$34
$35
$36
$37
$38
$39
$3A
Compare Register 1
Compare Register 2
Capture Register
TMRD3_LOAD
TMRD3_HOLD
TMRD3_CNTR
TMRD3_CTRL
TMRD3_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
TMRD3_CMPLD1
TMRD3_CMPLD2
TMRD3_COMSCR
Table 4-15 Pulse Width Modulator A Registers Address Map
(PWMA_BASE = $00 F140)
PWMA is NOT available in the 56F8167 device
Register Acronym
Address Offset
Register Description
PWMA_PMCTL
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
$C
Control Register
PWMA_PMFCTL
PWMA_PMFSA
Fault Control Register
Fault Status Acknowledge Register
Output Control Register
Counter Register
PWMA_PMOUT
PWMA_PMCNT
PWMA_PWMCM
PWMA_PWMVAL0
PWMA_PWMVAL1
PWMA_PWMVAL2
PWMA_PWMVAL3
PWMA_PWMVAL4
PWMA_PWMVAL5
PWMA_PMDEADTM
Counter Modulo Register
Value Register 0
Value Register 1
Value Register 2
Value Register 3
Value Register 4
Value Register 5
Dead Time Register
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
57
Table 4-15 Pulse Width Modulator A Registers Address Map (Continued)
(PWMA_BASE = $00 F140)
PWMA is NOT available in the 56F8167 device
Register Acronym
Address Offset
Register Description
Disable Mapping Register 1
PWMA_PMDISMAP1
PWMA_PMDISMAP2
PWMA_PMCFG
$D
$E
Disable Mapping Register 2
Configure Register
$F
PWMA_PMCCR
$10
$11
$12
Channel Control Register
PWMA_PMPORT
PWMA_PMICCR
Port Register
PWM Internal Correction Control Register
Table 4-16 Pulse Width Modulator B Registers Address Map
(PWMB_BASE = $00 F160)
Register Acronym
Address Offset
Register Description
PWMB_PMCTL
$0
$1
Control Register
PWMB_PMFCTL
PWMB_PMFSA
Fault Control Register
Fault Status Acknowledge Register
Output Control Register
Counter Register
$2
PWMB_PMOUT
$3
PWMB_PMCNT
$4
PWMB_PWMCM
PWMB_PWMVAL0
PWMB_PWMVAL1
PWMB_PWMVAL2
PWMB_PWMVAL3
PWMB_PWMVAL4
PWMB_PWMVAL5
PWMB_PMDEADTM
PWMB_PMDISMAP1
PWMB_PMDISMAP2
PWMB_PMCFG
$5
Counter Modulo Register
Value Register 0
$6
$7
Value Register 1
$8
Value Register 2
$9
Value Register 3
$A
$B
$C
$D
$E
$F
$10
$11
$12
Value Register 4
Value Register 5
Dead Time Register
Disable Mapping Register 1
Disable Mapping Register 2
Configure Register
PWMB_PMCCR
Channel Control Register
PWMB_PMPORT
PWMB_PMICCR
Port Register
PWM Internal Correction Control Register
56F8367 Technical Data, Rev. 3.0
58
Freescale Semiconductor
Preliminary
Peripheral Memory Mapped Registers
Table 4-17 Quadrature Decoder 0 Registers Address Map
(DEC0_BASE = $00 F180)
Register Acronym
Address Offset
$0
Register Description
Decoder Control Register
DEC0_DECCR
DEC0_FIR
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
$C
$D
Filter Interval Register
DEC0_WTR
DEC0_POSD
DEC0_POSDH
DEC0_REV
DEC0_REVH
DEC0_UPOS
DEC0_LPOS
DEC0_UPOSH
DEC0_LPOSH
DEC0_UIR
Watchdog Time-out Register
Position Difference Counter Register
Position Difference Counter Hold Register
Revolution Counter Register
Revolution Hold Register
Upper Position Counter Register
Lower Position Counter Register
Upper Position Hold Register
Lower Position Hold Register
Upper Initialization Register
Lower Initialization Register
Input Monitor Register
DEC0_LIR
DEC0_IMR
Table 4-18 Quadrature Decoder 1 Registers Address Map
(DEC1_BASE = $00 F190)
Quadrature Decoder 1 is NOT available in the 56F8167 device
Register Acronym
Address Offset
Register Description
Decoder Control Register
DEC1_DECCR
DEC1_FIR
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
$C
$D
Filter Interval Register
DEC1_WTR
DEC1_POSD
DEC1_POSDH
DEC1_REV
Watchdog Time-out Register
Position Difference Counter Register
Position Difference Counter Hold Register
Revolution Counter Register
Revolution Hold Register
DEC1_REVH
DEC1_UPOS
DEC1_LPOS
DEC1_UPOSH
DEC1_LPOSH
DEC1_UIR
Upper Position Counter Register
Lower Position Counter Register
Upper Position Hold Register
Lower Position Hold Register
Upper Initialization Register
Lower Initialization Register
Input Monitor Register
DEC1_LIR
DEC1_IMR
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
59
Table 4-19 Interrupt Control Registers Address Map
(ITCN_BASE = $00 F1A0)
Register Acronym
IPR 0
Address Offset
Register Description
Interrupt Priority Register 0
$0
$1
IPR 1
Interrupt Priority Register 1
Interrupt Priority Register 2
Interrupt Priority Register 3
Interrupt Priority Register 4
Interrupt Priority Register 5
Interrupt Priority Register 6
Interrupt Priority Register 7
Interrupt Priority Register 8
Interrupt Priority Register 9
Vector Base Address Register
Fast Interrupt Match Register 0
Fast Interrupt Vector Address Low 0 Register
Fast Interrupt Vector Address High 0 Register
Fast Interrupt Match Register 1
Fast Interrupt Vector Address Low 1 Register
Fast Interrupt Vector Address High 1 Register
IRQ Pending Register 0
IPR 2
$2
IPR 3
$3
IPR 4
$4
IPR 5
$5
IPR 6
$6
IPR 7
$7
IPR 8
$8
IPR 9
$9
VBA
$A
$B
$C
$D
$E
$F
FIM0
FIVAL0
FIVAH0
FIM1
FIVAL1
FIVAH1
IRQP 0
IRQP 1
IRQP 2
IRQP 3
IRQP 4
IRQP 5
$10
$11
$12
$13
$14
$15
$16
IRQ Pending Register 1
IRQ Pending Register 2
IRQ Pending Register 3
IRQ Pending Register 4
IRQ Pending Register 5
Reserved
ICTL
$1D
$1F
Interrupt Control Register
Reserved
IPR10
Interrupt Priority Register 10
56F8367 Technical Data, Rev. 3.0
60
Freescale Semiconductor
Preliminary
Peripheral Memory Mapped Registers
Table 4-20 Analog-to-Digital Converter Registers Address Map
(ADCA_BASE = $00 F200)
Register Acronym
Address Offset
$0
Register Description
Control Register 1
ADCA_CR 1
ADCA_CR 2
$1
$2
Control Register 2
ADCA_ZCC
Zero Crossing Control Register
Channel List Register 1
Channel List Register 2
Sample Disable Register
Status Register
ADCA_LST 1
ADCA_LST 2
ADCA_SDIS
$3
$4
$5
ADCA_STAT
$6
ADCA_LSTAT
ADCA_ZCSTAT
ADCA_RSLT 0
ADCA_RSLT 1
ADCA_RSLT 2
ADCA_RSLT 3
ADCA_RSLT 4
ADCA_RSLT 5
ADCA_RSLT 6
ADCA_RSLT 7
ADCA_LLMT 0
ADCA_LLMT 1
ADCA_LLMT 2
ADCA_LLMT 3
ADCA_LLMT 4
ADCA_LLMT 5
ADCA_LLMT 6
ADCA_LLMT 7
ADCA_HLMT 0
ADCA_HLMT 1
ADCA_HLMT 2
ADCA_HLMT 3
ADCA_HLMT 4
ADCA_HLMT 5
ADCA_HLMT 6
$7
Limit Status Register
Zero Crossing Status Register
Result Register 0
$8
$9
$A
Result Register 1
$B
Result Register 2
$C
Result Register 3
$D
Result Register 4
$E
Result Register 5
$F
Result Register 6
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1A
$1B
$1C
$1D
$1E
$1F
Result Register 7
Low Limit Register 0
Low Limit Register 1
Low Limit Register 2
Low Limit Register 3
Low Limit Register 4
Low Limit Register 5
Low Limit Register 6
Low Limit Register 7
High Limit Register 0
High Limit Register 1
High Limit Register 2
High Limit Register 3
High Limit Register 4
High Limit Register 5
High Limit Register 6
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
61
Table 4-20 Analog-to-Digital Converter Registers Address Map (Continued)
(ADCA_BASE = $00 F200)
Register Acronym
Address Offset
Register Description
High Limit Register 7
ADCA_HLMT 7
ADCA_OFS 0
ADCA_OFS 1
ADCA_OFS 2
ADCA_OFS 3
ADCA_OFS 4
ADCA_OFS 5
ADCA_OFS 6
ADCA_OFS 7
ADCA_POWER
ADCA_CAL
$20
$21
$22
$23
$24
$25
$26
$27
$28
$29
$2A
Offset Register 0
Offset Register 1
Offset Register 2
Offset Register 3
Offset Register 4
Offset Register 5
Offset Register 6
Offset Register 7
Power Control Register
ADC Calibration Register
Table 4-21 Analog-to-Digital Converter Registers Address Map
(ADCB_BASE = $00 F240)
Register Acronym
Address Offset
Register Description
Control Register 1
ADCB_CR 1
$0
$1
ADCB_CR 2
Control Register 2
ADCB_ZCC
$2
Zero Crossing Control Register
Channel List Register 1
Channel List Register 2
Sample Disable Register
Status Register
ADCB_LST 1
ADCB_LST 2
ADCB_SDIS
$3
$4
$5
ADCB_STAT
ADCB_LSTAT
ADCB_ZCSTAT
ADCB_RSLT 0
ADCB_RSLT 1
ADCB_RSLT 2
ADCB_RSLT 3
ADCB_RSLT 4
ADCB_RSLT 5
ADCB_RSLT 6
ADCB_RSLT 7
ADCB_LLMT 0
ADCB_LLMT 1
$6
$7
Limit Status Register
Zero Crossing Status Register
Result Register 0
$8
$9
$A
$B
$C
$D
$E
$F
$10
$11
$12
Result Register 1
Result Register 2
Result Register 3
Result Register 4
Result Register 5
Result Register 6
Result Register 7
Low Limit Register 0
Low Limit Register 1
56F8367 Technical Data, Rev. 3.0
62
Freescale Semiconductor
Preliminary
Peripheral Memory Mapped Registers
Table 4-21 Analog-to-Digital Converter Registers Address Map (Continued)
(ADCB_BASE = $00 F240)
Register Acronym
Address Offset
$13
Register Description
Low Limit Register 2
ADCB_LLMT 2
ADCB_LLMT 3
ADCB_LLMT 4
ADCB_LLMT 5
ADCB_LLMT 6
ADCB_LLMT 7
ADCB_HLMT 0
ADCB_HLMT 1
ADCB_HLMT 2
ADCB_HLMT 3
ADCB_HLMT 4
ADCB_HLMT 5
ADCB_HLMT 6
ADCB_HLMT 7
ADCB_OFS 0
ADCB_OFS 1
ADCB_OFS 2
ADCB_OFS 3
ADCB_OFS 4
ADCB_OFS 5
ADCB_OFS 6
ADCB_OFS 7
ADCB_POWER
ADCB_CAL
$14
$15
$16
$17
$18
$19
$1A
$1B
$1C
$1D
$1E
$1F
$20
$21
$22
$23
$24
$25
$26
$27
$28
$29
$2A
Low Limit Register 3
Low Limit Register 4
Low Limit Register 5
Low Limit Register 6
Low Limit Register 7
High Limit Register 0
High Limit Register 1
High Limit Register 2
High Limit Register 3
High Limit Register 4
High Limit Register 5
High Limit Register 6
High Limit Register 7
Offset Register 0
Offset Register 1
Offset Register 2
Offset Register 3
Offset Register 4
Offset Register 5
Offset Register 6
Offset Register 7
Power Control Register
ADC Calibration Register
Table 4-22 Temperature Sensor Register Address Map
(TSENSOR_BASE = $00 F270)
Temperature Sensor is NOT available in the 56F8167 device
Register Acronym
Address Offset
Register Description
TSENSOR_CNTL
$0
Control Register
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
63
Table 4-23 Serial Communication Interface 0 Registers Address Map
(SCI0_BASE = $00 F280)
Register Acronym
Address Offset
Register Description
Baud Rate Register
SCI0_SCIBR
SCI0_SCICR
$0
$1
Control Register
Reserved
SCI0_SCISR
SCI0_SCIDR
$3
$4
Status Register
Data Register
Table 4-24 Serial Communication Interface 1 Registers Address Map
(SCI1_BASE = $00 F290)
Register Acronym
Address Offset
Register Description
Baud Rate Register
SCI1_SCIBR
SCI1_SCICR
$0
$1
Control Register
Reserved
SCI1_SCISR
SCI1_SCIDR
$3
$4
Status Register
Data Register
Table 4-25 Serial Peripheral Interface 0 Registers Address Map
(SPI0_BASE = $00 F2A0)
Register Acronym
Address Offset
Register Description
Status and Control Register
SPI0_SPSCR
SPI0_SPDSR
SPI0_SPDRR
SPI0_SPDTR
$0
$1
$2
$3
Data Size Register
Data Receive Register
Data Transmitter Register
Table 4-26 Serial Peripheral Interface 1 Registers Address Map
(SPI1_BASE = $00 F2B0)
Register Acronym
Address Offset
Register Description
Status and Control Register
SPI1_SPSCR
SPI1_SPDSR
SPI1_SPDRR
SPI1_SPDTR
$0
$1
$2
$3
Data Size Register
Data Receive Register
Data Transmitter Register
56F8367 Technical Data, Rev. 3.0
64
Freescale Semiconductor
Preliminary
Peripheral Memory Mapped Registers
Table 4-27 Computer Operating Properly Registers Address Map
(COP_BASE = $00 F2C0)
Register Acronym
Address Offset
$0
Register Description
COPCTL
COPTO
Control Register
$1
$2
Time Out Register
Counter Register
COPCTR
Table 4-28 Clock Generation Module Registers Address Map
(CLKGEN_BASE = $00 F2D0)
Register Acronym
PLLCR
Address Offset
Register Description
$0
$1
$2
Control Register
PLLDB
PLLSR
Divide-By Register
Status Register
Reserved
SHUTDOWN
OSCTL
$4
$5
Shutdown Register
Oscillator Control Register
Table 4-29 GPIOA Registers Address Map
(GPIOA_BASE = $00 F2E0)
Address Offset
Register Description
Reset Value
0 x 3FFF
0 x 0000
0 x 0000
0 x 3FFF
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 3FFF
—
Register Acronym
GPIOA_PUR
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
Pull-up Enable Register
GPIOA_DR
Data Register
GPIOA_DDR
Data Direction Register
Peripheral Enable Register
Interrupt Assert Register
Interrupt Enable Register
Interrupt Polarity Register
Interrupt Pending Register
Interrupt Edge-Sensitive Register
Push-Pull Mode Register
Raw Data Input Register
GPIOA_PER
GPIOA_IAR
GPIOA_IENR
GPIOA_IPOLR
GPIOA_IPR
GPIOA_IESR
GPIOA_PPMODE
GPIOA_RAWDATA
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
65
Table 4-30 GPIOB Registers Address Map
(GPIOB_BASE = $00 F300)
Register Acronym
Address Offset
Register Description
Pull-up Enable Register
Reset Value
GPIOB_PUR
GPIOB_DR
GPIOB_DDR
GPIOB_PER
$0
$1
$2
$3
0 x 00FF
0 x 0000
0 x 0000
Data Register
Data Direction Register
Peripheral Enable Register
0 x 000F for 20-bit EMI
address at reset.
0 x 0000 for all other cases.
See Table 4-4 for details.
0 x 0000
GPIOB_IAR
$4
$5
$6
$7
$8
$9
$A
Interrupt Assert Register
Interrupt Enable Register
Interrupt Polarity Register
Interrupt Pending Register
Interrupt Edge-Sensitive Register
Push-Pull Mode Register
Raw Data Input Register
GPIOB_IENR
GPIOB_IPOLR
GPIOB_IPR
0 x 0000
0 x 0000
0 x 0000
GPIOB_IESR
GPIOB_PPMODE
GPIOB_RAWDATA
0 x 0000
0 x 0000
—
Table 4-31 GPIOC Registers Address Map
(GPIOC_BASE = $00F310)
Register Acronym
Address Offset
Register Description
Pull-up Enable Register
Reset Value
GPIOC_PUR
GPIOC_DR
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
0 x 07FF
0 x 0000
0 x 0000
0 x 07FF
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 07FF
—
Data Register
GPIOC_DDR
GPIOC_PER
GPIOC_IAR
Data Direction Register
Peripheral Enable Register
Interrupt Assert Register
Interrupt Enable Register
Interrupt Polarity Register
Interrupt Pending Register
Interrupt Edge-Sensitive Register
Push-Pull Mode Register
Raw Data Input Register
GPIOC_IENR
GPIOC_IPOLR
GPIOC_IPR
GPIOC_IESR
GPIOC_PPMODE
GPIOC_RAWDATA
56F8367 Technical Data, Rev. 3.0
66
Freescale Semiconductor
Preliminary
Peripheral Memory Mapped Registers
Table 4-32 GPIOD Registers Address Map
(GPIOD_BASE = $00 F320)
Register Acronym
Address Offset
Register Description
Pull-up Enable Register
Reset Value
GPIOD_PUR
GPIOD_DR
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
0 x 1FFF
0 x 0000
0 x 0000
0 x 1FC0
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 0000
Data Register
GPIOD_DDR
GPIOD_PER
GPIOD_IAR
Data Direction Register
Peripheral Enable Register
Interrupt Assert Register
Interrupt Enable Register
Interrupt Polarity Register
Interrupt Pending Register
Interrupt Edge-Sensitive Register
Push-Pull Mode Register
Raw Data Input Register
GPIOD_IENR
GPIOD_IPOLR
GPIOD_IPR
GPIOD_IESR
GPIOD_PPMODE
GPIOD_RAWDATA
—
Table 4-33 GPIOE Registers Address Map
(GPIOE_BASE = $00 F330)
Register Acronym
Address Offset
Register Description
Pull-up Enable Register
Reset Value
GPIOE_PUR
GPIOE_DR
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
0 x 3FFF
0 x 0000
0 x 0000
0 x 3FFF
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 3FFF
—
Data Register
GPIOE_DDR
GPIOE_PER
GPIOE_IAR
Data Direction Register
Peripheral Enable Register
Interrupt Assert Register
Interrupt Enable Register
Interrupt Polarity Register
Interrupt Pending Register
Interrupt Edge-Sensitive Register
Push-Pull Mode Register
Raw Data Input Register
GPIOE_IENR
GPIOE_IPOLR
GPIOE_IPR
GPIOE_IESR
GPIOE_PPMODE
GPIOE_RAWDATA
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
67
Table 4-34 GPIOF Registers Address Map
(GPIOF_BASE = $00 F340)
Register Acronym
Address Offset
Register Description
Pull-up Enable Register
Reset Value
GPIOF_PUR
GPIOF_DR
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
0 x FFFF
0 x 0000
0 x 0000
0 x FFFF
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x FFFF
—
Data Register
GPIOF_DDR
GPIOF_PER
GPIOF_IAR
Data Direction Register
Peripheral Enable Register
Interrupt Assert Register
Interrupt Enable Register
Interrupt Polarity Register
Interrupt Pending Register
Interrupt Edge-Sensitive Register
Push-Pull Mode Register
Raw Data Input Register
GPIOF_IENR
GPIOF_IPOLR
GPIOF_IPR
GPIOF_IESR
GPIOF_PPMODE
GPIOF_RAWDATA
Table 4-35 System Integration Module Registers Address Map
(SIM_BASE = $00 F350)
Register Acronym
Address Offset
Register Description
SIM_CONTROL
SIM_RSTSTS
SIM_SCR0
$0
$1
$2
$3
$4
$5
$6
$7
$8
Control Register
Reset Status Register
Software Control Register 0
Software Control Register 1
Software Control Register 2
Software Control Register 3
Most Significant Half JTAG ID
Least Significant Half JTAG ID
Pull-up Disable Register
SIM_SCR1
SIM_SCR2
SIM_SCR3
SIM_MSH_ID
SIM_LSH_ID
SIM_PUDR
Reserved
SIM_CLKOSR
SIM_GPS
$A
$B
$C
$D
$E
$F
Clock Out Select Register
Quad Decoder 1 / Timer B / SPI 1 Select Register
Peripheral Clock Enable Register
I/O Short Address Location High Register
I/O Short Address Location Low Register
Peripheral Clock Enable Register 2
SIM_PCE
SIM_ISALH
SIM_ISALL
SIM_PCE2
56F8367 Technical Data, Rev. 3.0
68
Freescale Semiconductor
Preliminary
Peripheral Memory Mapped Registers
Table 4-36 Power Supervisor Registers Address Map
(LVI_BASE = $00 F360)
Register Acronym
Address Offset
Register Description
LVI_CONTROL
LVI_STATUS
$0
$1
Control Register
Status Register
Table 4-37 Flash Module Registers Address Map
(FM_BASE = $00 F400)
Register Acronym
Address Offset
Register Description
Clock Divider Register
FMCLKD
FMMCR
$0
$1
Module Control Register
Reserved
FMSECH
FMSECL
$3
$4
Security High Half Register
Security Low Half Register
Reserved
Reserved
FMPROT
$10
$11
Protection Register (Banked)
Protection Boot Register (Banked)
Reserved
FMPROTB
FMUSTAT
FMCMD
$13
$14
User Status Register (Banked)
Command Register (Banked)
Reserved
Reserved
16-Bit Information Option Register 0
Hot temperature ADC reading of Temperature Sensor;
value set during factory test
FMOPT 0
$1A
16-Bit Information Option Register 1
Not used
FMOPT 1
FMOPT 2
$1B
$1C
16-Bit Information Option Register 2
Room temperature ADC reading of Temperature Sensor;
value set during factory test
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
69
Table 4-38 FlexCAN Registers Address Map
(FC_BASE = $00 F800)
FlexCAN is NOT available in the 56F8167 device
Register Acronym
FCMCR
Address Offset
Register Description
Module Configuration Register
$0
Reserved
FCCTL0
FCCTL1
FCTMR
$3
$4
$5
$6
Control Register 0 Register
Control Register 1 Register
Free-Running Timer Register
Maximum Message Buffer Configuration Register
Reserved
FCMAXMB
FCRXGMASK_H
FCRXGMASK_L
FCRX14MASK_H
FCRX14MASK_L
FCRX15MASK_H
FCRX15MASK_L
$8
$9
$A
$B
$C
$D
Receive Global Mask High Register
Receive Global Mask Low Register
Receive Buffer 14 Mask High Register
Receive Buffer 14 Mask Low Register
Receive Buffer 15 Mask High Register
Receive Buffer 15 Mask Low Register
Reserved
FCSTATUS
$10
$11
$12
$13
Error and Status Register
FCIMASK1
Interrupt Masks 1 Register
Interrupt Flags 1 Register
FCIFLAG1
FCR/T_ERROR_CNTRS
Receive and Transmit Error Counters Register
Reserved
Reserved
Reserved
FCMB0_CONTROL
FCMB0_ID_HIGH
FCMB0_ID_LOW
FCMB0_DATA
$40
$41
$42
$43
$44
$45
$46
Message Buffer 0 Control / Status Register
Message Buffer 0 ID High Register
Message Buffer 0 ID Low Register
Message Buffer 0 Data Register
Message Buffer 0 Data Register
Message Buffer 0 Data Register
Message Buffer 0 Data Register
Reserved
FCMB0_DATA
FCMB0_DATA
FCMB0_DATA
FCMSB1_CONTROL
FCMSB1_ID_HIGH
FCMSB1_ID_LOW
$48
$49
$4A
Message Buffer 1 Control / Status Register
Message Buffer 1 ID High Register
Message Buffer 1 ID Low Register
56F8367 Technical Data, Rev. 3.0
70
Freescale Semiconductor
Preliminary
Peripheral Memory Mapped Registers
Table 4-38 FlexCAN Registers Address Map (Continued)
(FC_BASE = $00 F800)
FlexCAN is NOT available in the 56F8167 device
Register Acronym
FCMB1_DATA
Address Offset
Register Description
Message Buffer 1 Data Register
$4B
$4C
$4D
$4E
FCMB1_DATA
FCMB1_DATA
FCMB1_DATA
Message Buffer 1 Data Register
Message Buffer 1 Data Register
Message Buffer 1 Data Register
Reserved
FCMB2_CONTROL
FCMB2_ID_HIGH
FCMB2_ID_LOW
FCMB2_DATA
$50
$51
$52
$53
$54
$55
$56
Message Buffer 2 Control / Status Register
Message Buffer 2 ID High Register
Message Buffer 2 ID Low Register
Message Buffer 2 Data Register
Message Buffer 2 Data Register
Message Buffer 2 Data Register
Message Buffer 2 Data Register
Reserved
FCMB2_DATA
FCMB2_DATA
FCMB2_DATA
FCMB3_CONTROL
FCMB3_ID_HIGH
FCMB3_ID_LOW
FCMB3_DATA
$58
$59
$5A
$5B
$5C
$5D
$5E
Message Buffer 3 Control / Status Register
Message Buffer 3 ID High Register
Message Buffer 3 ID Low Register
Message Buffer 3 Data Register
Message Buffer 3 Data Register
Message Buffer 3 Data Register
Message Buffer 3 Data Register
Reserved
FCMB3_DATA
FCMB3_DATA
FCMB3_DATA
FCMB4_CONTROL
FCMB4_ID_HIGH
FCMB4_ID_LOW
FCMB4_DATA
$60
$61
$62
$63
$64
$65
$66
Message Buffer 4 Control / Status Register
Message Buffer 4 ID High Register
Message Buffer 4 ID Low Register
Message Buffer 4 Data Register
Message Buffer 4 Data Register
Message Buffer 4 Data Register
Message Buffer 4 Data Register
Reserved
FCMB4_DATA
FCMB4_DATA
FCMB4_DATA
FCMB5_CONTROL
FCMB5_ID_HIGH
FCMB5_ID_LOW
$68
$69
$6A
Message Buffer 5 Control / Status Register
Message Buffer 5 ID High Register
Message Buffer 5 ID Low Register
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
71
Table 4-38 FlexCAN Registers Address Map (Continued)
(FC_BASE = $00 F800)
FlexCAN is NOT available in the 56F8167 device
Register Acronym
FCMB5_DATA
Address Offset
Register Description
Message Buffer 5 Data Register
$6B
$6C
$6D
$6E
FCMB5_DATA
FCMB5_DATA
FCMB5_DATA
Message Buffer 5 Data Register
Message Buffer 5 Data Register
Message Buffer 5 Data Register
Reserved
FCMB6_CONTROL
FCMB6_ID_HIGH
FCMB6_ID_LOW
FCMB6_DATA
$70
$71
$72
$73
$74
$75
$76
Message Buffer 6 Control / Status Register
Message Buffer 6 ID High Register
Message Buffer 6 ID Low Register
Message Buffer 6 Data Register
Message Buffer 6 Data Register
Message Buffer 6 Data Register
Message Buffer 6 Data Register
Reserved
FCMB6_DATA
FCMB6_DATA
FCMB6_DATA
FCMB7_CONTROL
FCMB7_ID_HIGH
FCMB7_ID_LOW
FCMB7_DATA
$78
$79
$7A
$7B
$7C
$7D
$7E
Message Buffer 7 Control / Status Register
Message Buffer 7 ID High Register
Message Buffer 7 ID Low Register
Message Buffer 7 Data Register
Message Buffer 7 Data Register
Message Buffer 7 Data Register
Message Buffer 7 Data Register
Reserved
FCMB7_DATA
FCMB7_DATA
FCMB7_DATA
FCMB8_CONTROL
FCMB8_ID_HIGH
FCMB8_ID_LOW
FCMB8_DATA
$80
$81
$82
$83
$84
$85
$86
Message Buffer 8 Control / Status Register
Message Buffer 8 ID High Register
Message Buffer 8 ID Low Register
Message Buffer 8 Data Register
Message Buffer 8 Data Register
Message Buffer 8 Data Register
Message Buffer 8 Data Register
Reserved
FCMB8_DATA
FCMB8_DATA
FCMB8_DATA
FCMB9_CONTROL
FCMB9_ID_HIGH
FCMB9_ID_LOW
$88
$89
$8A
Message Buffer 9 Control / Status Register
Message Buffer 9 ID High Register
Message Buffer 9 ID Low Register
56F8367 Technical Data, Rev. 3.0
72
Freescale Semiconductor
Preliminary
Peripheral Memory Mapped Registers
Table 4-38 FlexCAN Registers Address Map (Continued)
(FC_BASE = $00 F800)
FlexCAN is NOT available in the 56F8167 device
Register Acronym
FCMB9_DATA
Address Offset
Register Description
Message Buffer 9 Data Register
$8B
$8C
$8D
$8E
FCMB9_DATA
FCMB9_DATA
FCMB9_DATA
Message Buffer 9 Data Register
Message Buffer 9 Data Register
Message Buffer 9 Data Register
Reserved
FCMB10_CONTROL
FCMB10_ID_HIGH
FCMB10_ID_LOW
FCMB10_DATA
FCMB10_DATA
FCMB10_DATA
FCMB10_DATA
$90
$91
$92
$93
$94
$95
$96
Message Buffer 10 Control / Status Register
Message Buffer 10 ID High Register
Message Buffer 10 ID Low Register
Message Buffer 10 Data Register
Message Buffer 10 Data Register
Message Buffer 10 Data Register
Message Buffer 10 Data Register
Reserved
FCMB11_CONTROL
FCMB11_ID_HIGH
FCMB11_ID_LOW
FCMB11_DATA
FCMB11_DATA
FCMB11_DATA
FCMB11_DATA
$98
$99
$9A
$9B
$9C
$9D
$9E
Message Buffer 11 Control / Status Register
Message Buffer 11 ID High Register
Message Buffer 11 ID Low Register
Message Buffer 11 Data Register
Message Buffer 11 Data Register
Message Buffer 11 Data Register
Message Buffer 11 Data Register
Reserved
FCMB12_CONTROL
FCMB12_ID_HIGH
FCMB12_ID_LOW
FCMB12_DATA
FCMB12_DATA
FCMB12_DATA
FCMB12_DATA
$A0
$A1
$A2
$A3
$A4
$A5
$A6
Message Buffer 12 Control / Status Register
Message Buffer 12 ID High Register
Message Buffer 12 ID Low Register
Message Buffer 12 Data Register
Message Buffer 12 Data Register
Message Buffer 12 Data Register
Message Buffer 12 Data Register
Reserved
FCMB13_CONTROL
FCMB13_ID_HIGH
FCMB13_ID_LOW
$A8
$A9
$AA
Message Buffer 13 Control / Status Register
Message Buffer 13 ID High Register
Message Buffer 13 ID Low Register
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
73
Table 4-38 FlexCAN Registers Address Map (Continued)
(FC_BASE = $00 F800)
FlexCAN is NOT available in the 56F8167 device
Register Acronym
FCMB13_DATA
Address Offset
Register Description
Message Buffer 13 Data Register
$AB
$AC
$AD
$AE
FCMB13_DATA
FCMB13_DATA
FCMB13_DATA
Message Buffer 13 Data Register
Message Buffer 13 Data Register
Message Buffer 13 Data Register
Reserved
FCMB14_CONTROL
FCMB14_ID_HIGH
FCMB14_ID_LOW
FCMB14_DATA
FCMB14_DATA
FCMB14_DATA
FCMB14_DATA
$B0
$B1
$B2
$B3
$B4
$B5
$B6
Message Buffer 14 Control / Status Register
Message Buffer 14 ID High Register
Message Buffer 14 ID Low Register
Message Buffer 14 Data Register
Message Buffer 14 Data Register
Message Buffer 14 Data Register
Message Buffer 14 Data Register
Reserved
FCMB15_CONTROL
FCMB15_ID_HIGH
FCMB15_ID_LOW
FCMB15_DATA
FCMB15_DATA
FCMB15_DATA
FCMB15_DATA
$B8
$B9
$BA
$BB
$BC
$BD
$BE
Message Buffer 15 Control / Status Register
Message Buffer 15 ID High Register
Message Buffer 15 ID Low Register
Message Buffer 15 Data Register
Message Buffer 15 Data Register
Message Buffer 15 Data Register
Message Buffer 15 Data Register
Reserved
Table 4-39 FlexCAN2 Registers Address Map
(FC2_BASE = $00 FA00)
FlexCAN2 is NOT available in the 56F8167 device
Register Acronym
FC2MCR
Address Offset
Register Description
Module Configuration Register
$0
Reserved
FC2CTL0
$3
$4
$5
$6
$7
$8
Control Register 0 Register
Control Register 1 Register
Free-Running Timer Register
Maximum Message Buffer Configuration Register
Interrupt Masks 2 Register
FC2CTL1
FC2TMR
FC2MAXMB
FC2IMASK2
FC2RXGMASK_H
Receive Global Mask High Register
56F8367 Technical Data, Rev. 3.0
74
Freescale Semiconductor
Preliminary
Peripheral Memory Mapped Registers
Table 4-39 FlexCAN2 Registers Address Map (Continued)
(FC2_BASE = $00 FA00)
FlexCAN2 is NOT available in the 56F8167 device
Register Acronym
FC2RXGMASK_L
Address Offset
Register Description
$9
$A
$B
$C
$D
Receive Global Mask Low Register
Receive Buffer 14 Mask High Register
Receive Buffer 14 Mask Low Register
Receive Buffer 15 Mask High Register
Receive Buffer 15 Mask Low Register
Reserved
FC2RX14MASK_H
FC2RX14MASK_L
FC2RX15MASK_H
FC2RX15MASK_L
FC2STATUS
$10
$11
$12
$13
Error and Status Register
FC2IMASK1
Interrupt Masks 1 Register
FC2IFLAG1
Interrupt Flags 1 Register
FC2R/T_ERROR_CNTRS
Receive and Transmit Error Counters Register
Reserved
FC2IFLAG 2
$1B
Interrupt Flags 2 Register
Reserved
FC2MB0_CONTROL
FC2MB0_ID_HIGH
FC2MB0_ID_LOW
FC2MB0_DATA
FC2MB0_DATA
FC2MB0_DATA
FC2MB0_DATA
$40
$41
$42
$43
$44
$45
$46
Message Buffer 0 Control / Status Register
Message Buffer 0 ID High Register
Message Buffer 0 ID Low Register
Message Buffer 0 Data Register
Message Buffer 0 Data Register
Message Buffer 0 Data Register
Message Buffer 0 Data Register
Reserved
FC2MSB1_CONTROL
FC2MSB1_ID_HIGH
FC2MSB1_ID_LOW
FC2MB1_DATA
$48
$49
$4A
$4B
$4C
$4D
$4E
Message Buffer 1 Control / Status Register
Message Buffer 1 ID High Register
Message Buffer 1 ID Low Register
Message Buffer 1 Data Register
Message Buffer 1 Data Register
Message Buffer 1 Data Register
Message Buffer 1 Data Register
Reserved
FC2MB1_DATA
FC2MB1_DATA
FC2MB1_DATA
FC2MB2_CONTROL
FC2MB2_ID_HIGH
FC2MB2_ID_LOW
$50
$51
$52
Message Buffer 2 Control / Status Register
Message Buffer 2 ID High Register
Message Buffer 2 ID Low Register
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
75
Table 4-39 FlexCAN2 Registers Address Map (Continued)
(FC2_BASE = $00 FA00)
FlexCAN2 is NOT available in the 56F8167 device
Register Acronym
FC2MB2_DATA
Address Offset
Register Description
Message Buffer 2 Data Register
$53
$54
$55
$56
FC2MB2_DATA
FC2MB2_DATA
FC2MB2_DATA
Message Buffer 2 Data Register
Message Buffer 2 Data Register
Message Buffer 2 Data Register
Reserved
FC2MB3_CONTROL
FC2MB3_ID_HIGH
FC2MB3_ID_LOW
FC2MB3_DATA
FC2MB3_DATA
FC2MB3_DATA
FC2MB3_DATA
$58
$59
$5A
$5B
$5C
$5D
$5E
Message Buffer 3 Control / Status Register
Message Buffer 3 ID High Register
Message Buffer 3 ID Low Register
Message Buffer 3 Data Register
Message Buffer 3 Data Register
Message Buffer 3 Data Register
Message Buffer 3 Data Register
Reserved
FC2MB4_CONTROL
FC2MB4_ID_HIGH
FC2MB4_ID_LOW
FC2MB4_DATA
FC2MB4_DATA
FC2MB4_DATA
FC2MB4_DATA
$60
$61
$62
$63
$64
$65
$66
Message Buffer 4 Control / Status Register
Message Buffer 4 ID High Register
Message Buffer 4 ID Low Register
Message Buffer 4 Data Register
Message Buffer 4 Data Register
Message Buffer 4 Data Register
Message Buffer 4 Data Register
Reserved
FC2MB5_CONTROL
FC2MB5_ID_HIGH
FC2MB5_ID_LOW
FC2MB5_DATA
FC2MB5_DATA
FC2MB5_DATA
FC2MB5_DATA
$68
$69
$6A
$6B
$6C
$6D
$6E
Message Buffer 5 Control / Status Register
Message Buffer 5 ID High Register
Message Buffer 5 ID Low Register
Message Buffer 5 Data Register
Message Buffer 5 Data Register
Message Buffer 5 Data Register
Message Buffer 5 Data Register
Reserved
FC2MB6_CONTROL
FC2MB6_ID_HIGH
FC2MB6_ID_LOW
$70
$71
$72
Message Buffer 6 Control / Status Register
Message Buffer 6 ID High Register
Message Buffer 6 ID Low Register
56F8367 Technical Data, Rev. 3.0
76
Freescale Semiconductor
Preliminary
Peripheral Memory Mapped Registers
Table 4-39 FlexCAN2 Registers Address Map (Continued)
(FC2_BASE = $00 FA00)
FlexCAN2 is NOT available in the 56F8167 device
Register Acronym
FC2MB6_DATA
Address Offset
Register Description
Message Buffer 6 Data Register
$73
$74
$75
$76
FC2MB6_DATA
FC2MB6_DATA
FC2MB6_DATA
Message Buffer 6 Data Register
Message Buffer 6 Data Register
Message Buffer 6 Data Register
Reserved
FC2MB7_CONTROL
FC2MB7_ID_HIGH
FC2MB7_ID_LOW
FC2MB7_DATA
FC2MB7_DATA
FC2MB7_DATA
FC2MB7_DATA
$78
$79
$7A
$7B
$7C
$7D
$7E
Message Buffer 7 Control / Status Register
Message Buffer 7 ID High Register
Message Buffer 7 ID Low Register
Message Buffer 7 Data Register
Message Buffer 7 Data Register
Message Buffer 7 Data Register
Message Buffer 7 Data Register
Reserved
FC2MB8_CONTROL
FC2MB8_ID_HIGH
FC2MB8_ID_LOW
FC2MB8_DATA
FC2MB8_DATA
FC2MB8_DATA
FC2MB8_DATA
$80
$81
$82
$83
$84
$85
$86
Message Buffer 8 Contro l /Status Register
Message Buffer 8 ID High Register
Message Buffer 8 ID Low Register
Message Buffer 8 Data Register
Message Buffer 8 Data Register
Message Buffer 8 Data Register
Message Buffer 8 Data Register
Reserved
FC2MB9_CONTROL
FC2MB9_ID_HIGH
FC2MB9_ID_LOW
FC2MB9_DATA
FC2MB9_DATA
FC2MB9_DATA
FC2MB9_DATA
$88
$89
$8A
$8B
$8C
$8D
$8E
Message Buffer 9 Control / Status Register
Message Buffer 9 ID High Register
Message Buffer 9 ID Low Register
Message Buffer 9 Data Register
Message Buffer 9 Data Register
Message Buffer 9 Data Register
Message Buffer 9 Data Register
Reserved
FC2MB10_CONTROL
FC2MB10_ID_HIGH
FC2MB10_ID_LOW
$90
$91
$92
Message Buffer 10 Control / Status Register
Message Buffer 10 ID High Register
Message Buffer 10 ID Low Register
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
77
Table 4-39 FlexCAN2 Registers Address Map (Continued)
(FC2_BASE = $00 FA00)
FlexCAN2 is NOT available in the 56F8167 device
Register Acronym
FC2MB10_DATA
Address Offset
Register Description
Message Buffer 10 Data Register
$93
$94
$95
$96
FC2MB10_DATA
FC2MB10_DATA
FC2MB10_DATA
Message Buffer 10 Data Register
Message Buffer 10 Data Register
Message Buffer 10 Data Register
Reserved
FC2MB11_CONTROL
FC2MB11_ID_HIGH
FC2MB11_ID_LOW
FC2MB11_DATA
FC2MB11_DATA
FC2MB11_DATA
FC2MB11_DATA
$98
$99
$9A
$9B
$9C
$9D
$9E
Message Buffer 11 Control / Status Register
Message Buffer 11 ID High Register
Message Buffer 11 ID Low Register
Message Buffer 11 Data Register
Message Buffer 11 Data Register
Message Buffer 11 Data Register
Message Buffer 11 Data Register
Reserved
FC2MB12_CONTROL
FC2MB12_ID_HIGH
FC2MB12_ID_LOW
FC2MB12_DATA
FC2MB12_DATA
FC2MB12_DATA
FC2MB12_DATA
$A0
$A1
$A2
$A3
$A4
$A5
$A6
Message Buffer 12 Control / Status Register
Message Buffer 12 ID High Register
Message Buffer 12 ID Low Register
Message Buffer 12 Data Register
Message Buffer 12 Data Register
Message Buffer 12 Data Register
Message Buffer 12 Data Register
Reserved
FC2MB13_CONTROL
FC2MB13_ID_HIGH
FC2MB13_ID_LOW
FC2MB13_DATA
FC2MB13_DATA
FC2MB13_DATA
FC2MB13_DATA
$A8
$A9
$AA
$AB
$AC
$AD
$AE
Message Buffer 13 Control / Status Register
Message Buffer 13 ID High Register
Message Buffer 13 ID Low Register
Message Buffer 13 Data Register
Message Buffer 13 Data Register
Message Buffer 13 Data Register
Message Buffer 13 Data Register
Reserved
FC2MB14_CONTROL
FC2MB14_ID_HIGH
FC2MB14_ID_LOW
$B0
$B1
$B2
Message Buffer 14 Control / Status Register
Message Buffer 14 ID High Register
Message Buffer 14 ID Low Register
56F8367 Technical Data, Rev. 3.0
78
Freescale Semiconductor
Preliminary
Factory Programmed Memory
Table 4-39 FlexCAN2 Registers Address Map (Continued)
(FC2_BASE = $00 FA00)
FlexCAN2 is NOT available in the 56F8167 device
Register Acronym
FC2MB14_DATA
Address Offset
Register Description
Message Buffer 14 Data Register
$B3
$B4
$B5
$B6
FC2MB14_DATA
FC2MB14_DATA
FC2MB14_DATA
Message Buffer 14 Data Register
Message Buffer 14 Data Register
Message Buffer 14 Data Register
Reserved
FC2MB15_CONTROL
FC2MB15_ID_HIGH
FC2MB15_ID_LOW
FC2MB15_DATA
FC2MB15_DATA
FC2MB15_DATA
FC2MB15_DATA
$B8
$B9
$BA
$BB
$BC
$BD
$BE
Message Buffer 15 Control / Status Register
Message Buffer 15 ID High Register
Message Buffer 15 ID Low Register
Message Buffer 15 Data Register
Message Buffer 15 Data Register
Message Buffer 15 Data Register
Message Buffer 15 Data Register
Reserved
4.8 Factory Programmed Memory
The Boot Flash memory block is programmed during manufacturing with a default Serial Bootloader
program. The Serial Bootloader application can be used to load a user application into the Program and
Data Flash (NOT available in the 56F8167 device) memories of the device. The 56F83xx SCI/CAN
Bootloader User Manual (MC56F83xxBLUM) provides detailed information on this firmware. An
application note, Production Flash Programming (AN1973), details how the Serial Bootloader program
can be used to perform production Flash programming of the on-board Flash memories as well as other
potential methods.
Like all the Flash memory blocks, the Boot Flash can be erased and programmed by the user. The Serial
Bootloader application is programmed as an aid to the end user, but is not required to be used or maintained
in the Boot Flash memory.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
79
Part 5 Interrupt Controller (ITCN)
5.1 Introduction
The Interrupt Controller (ITCN) module is used to arbitrate between various interrupt requests (IRQs), to
signal to the 56800E core when an interrupt of sufficient priority exists, and what address to jump in order
to service this interrupt.
5.2 Features
The ITCN module design includes these distinctive features:
•
•
•
•
Programmable priority levels for each IRQ
Two programmable Fast Interrupts
Notification to SIM module to restart clocks out of Wait and Stop modes
Drives initial address on the address bus after reset
For further information, see Table 4-5, Interrupt Vector Table Contents.
5.3 Functional Description
The Interrupt Controller is a slave on the IPBus. It contains registers allowing each of the 86 interrupt
sources to be set to one of four priority levels, excluding certain interrupts of fixed priority. Next, all of
the interrupt requests of a given level are priority encoded to determine the lowest numerical value of the
active interrupt requests for that level. Within a given priority level, 0 is the highest priority, while number
85 is the lowest.
5.3.1
Normal Interrupt Handling
Once the ITCN has determined that an interrupt is to be serviced and which interrupt has the highest
priority, an interrupt vector address is generated. Normal interrupt handling concatenates the VBA and the
vector number to determine the vector address. In this way, an offset is generated into the vector table for
each interrupt.
5.3.2
Interrupt Nesting
Interrupt exceptions may be nested to allow an IRQ of higher priority than the current exception to be
serviced. The following tables define the nesting requirements for each priority level.
Table 5-1 Interrupt Mask Bit Definition
SR[9]1
SR[8]1
Permitted Exceptions
Masked Exceptions
None
0
0
1
1
0
1
0
1
Priorities 0, 1, 2, 3
Priorities 1, 2, 3
Priorities 2, 3
Priority 3
Priority 0
Priorities 0, 1
Priorities 0, 1, 2
1. Core status register bits indicating current interrupt mask within the core.
56F8367 Technical Data, Rev. 3.0
80
Freescale Semiconductor
Preliminary
Functional Description
Table 5-2. Interrupt Priority Encoding
Current Interrupt Priority
Level
Required Nested
Exception Priority
IPIC_LEVEL[1:0]1
00
01
01
11
No Interrupt or SWILP
Priority 0
Priorities 0, 1, 2, 3
Priorities 1, 2, 3
Priorities 2, 3
Priority 3
Priority 1
Priorities 2 or 3
1. See IPIC field definition in Part 5.6.30.2
5.3.3
Fast Interrupt Handling
Fast interrupts are described in the DSP56800E Reference Manual. The interrupt controller recognizes
fast interrupts before the core does.
A fast interrupt is defined (to the ITCN) by:
1. Setting the priority of the interrupt as level 2, with the appropriate field in the IPR registers
2. Setting the FIMn register to the appropriate vector number
3. Setting the FIVALn and FIVAHn registers with the address of the code for the fast interrupt
When an interrupt occurs, its vector number is compared with the FIM0 and FIM1 register values. If a
match occurs, and it is a level 2 interrupt, the ITCN handles it as a fast interrupt. The ITCN takes the vector
address from the appropriate FIVALn and FIVAHn registers, instead of generating an address that is an
offset from the VBA.
The core then fetches the instruction from the indicated vector adddress and if it is not a JSR, the core starts
its fast interrupt handling.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
81
5.4 Block Diagram
any0
Priority
Level
Level 0
82->7
Priority
Encoder
7
2->4
INT1
Decode
INT
VAB
IPIC
CONTROL
any3
Level 3
Priority
Level
IACK
SR[9:8]
82->7
Priority
Encoder
7
PIC_EN
2->4
INT82
Decode
Figure 5-1 Interrupt Controller Block Diagram
5.5 Operating Modes
The ITCN module design contains two major modes of operation:
•
Functional Mode
The ITCN is in this mode by default.
•
Wait and Stop Modes
During Wait and Stop modes, the system clocks and the 56800E core are turned off. The ITCN will signal
a pending IRQ to the System Integration Module (SIM) to restart the clocks and service the IRQ. An IRQ
can only wake up the core if the IRQ is enabled prior to entering the Wait or Stop mode. Also, the IRQA
and IRQB signals automatically become low-level sensitive in these modes even if the control register bits
are set to make them falling-edge sensitive. This is because there is no clock available to detect the falling
edge.
A peripheral which requires a clock to generate interrupts will not be able to generate interrupts during Stop
mode. The FlexCAN module can wake the device from Stop mode, and a reset will do just that, or IRQA
and IRQB can wake it up.
56F8367 Technical Data, Rev. 3.0
82
Freescale Semiconductor
Preliminary
Register Descriptions
5.6 Register Descriptions
A register address is the sum of a base address and an address offset. The base address is defined at the
system level and the address offset is defined at the module level. The ITCN peripheral has 24 registers.
Table 5-3 ITCN Register Summary
(ITCN_BASE = $00F1A0)
Register
Acronym
Base Address +
Register Name
Interrupt Priority Register 0
Section Location
IPR0
$0
$1
5.6.1
5.6.2
Interrupt Priority Register 1
Interrupt Priority Register 2
Interrupt Priority Register 3
Interrupt Priority Register 4
Interrupt Priority Register 5
Interrupt Priority Register 6
Interrupt Priority Register 7
Interrupt Priority Register 8
Interrupt Priority Register 9
Vector Base Address Register
Fast Interrupt 0 Match Register
Fast Interrupt 0 Vector Address Low Register
Fast Interrupt 0 Vector Address High Register
Fast Interrupt 1 Match Register
Fast Interrupt 1 Vector Address Low Register
Fast Interrupt 1 Vector Address High Register
IRQ Pending Register 0
IPR1
IPR2
$2
5.6.3
IPR3
$3
5.6.4
IPR4
$4
5.6.5
IPR5
$5
5.6.6
IPR6
$6
5.6.7
IPR7
$7
5.6.8
IPR8
$8
5.6.9
IPR9
$9
5.6.10
5.6.11
5.6.12
5.6.13
5.6.14
5.6.15
5.6.16
5.6.17
5.6.18
5.6.19
5.6.20
5.6.21
5.6.22
5.6.23
VBA
$A
$B
$C
$D
$E
$F
FIM0
FIVAL0
FIVAH0
FIM1
FIVAL1
FIVAH1
IRQP0
IRQP1
IRQP2
IRQP3
IRQP4
IRQP5
$10
$11
$12
$13
$14
$15
$16
IRQ Pending Register 1
IRQ Pending Register 2
IRQ Pending Register 3
IRQ Pending Register 4
IRQ Pending Register 5
Reserved
Interrupt Control Register
ICTL
$1D
$1F
5.6.30
5.6.32
Reserved
IPR10
Interrupt Priority Register 10
Note: The IPR10 is NOT available in the 56F8167 device.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
83
Add. Register
Offset Name
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
R
0
0
0
0
0
0
0
0
0
0
0
0
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
$C
$D
$E
$F
IPR0
IPR1
BKPT_U0 IPL
STPCNT IPL
0
0
0
0
0
0
0
0
0
0
RX_REG IPL
TX_REG IPL
IRQB IPL
TRBUF IPL
IRQA IPL
W
R
0
0
IPR2
FMCBE IPL
FMCC IPL
FMERR IPL
LOCK IPL
LVI IPL
W
R
0
0
GPIOD
IPL
GPIOE
IPL
GPIOF
IPL
IPR3
FCMSGBUF IPL FCWKUP IPL
FCERR IPL
FCBOFF IPL
W
R
0
0
0
0
0
0
SPI1_RCV
IPL
GPIOA
IPL
GPIOB
IPL
GPIOC
IPL
IPR4
SPI0_RCV IPL SPI1_XMIT IPL
DEC1_XIRQ IPL DEC1_HIRQ IPL
W
R
SCI1_RCV
IPL
IPR5
SCI1_RERR IPL
TMRD1 IPL
SCI1_TIDL IPL SCI1_XMIT IPL SPI0_XMIT IPL
W
R
0
0
IPR6
TMRC0 IPL
TMRA0 IPL
TMRD3 IPL
TMRB3 IPL
TMRD2 IPL
TMRB2 IPL
TMRD0 IPL
TMRB0 IPL
DEC0_XIRQ IPL DEC0_HIRQ IPL
W
R
IPR7
TMRB1 IPL
TMRC3 IPL
TMRA3 IPL
TMRC2 IPL
TMRA2 IPL
TMRC1 IPL
TMRA1 IPL
W
R
0
0
IPR8
SCI0_RCV IPL SCI0_RERR IPL
SCI0_TIDL IPL SCI0_XMIT IPL
PWMB_RL IPL ADCA_ZC IPL
W
R
PWMA_RL
IPL
IPR9
PWMA F IPL
PWMB F IPL
0
ABCB_ZC IPL
ADCA_CC IPL
ADCB_CC IPL
W
R
0
0
0
0
VBA
VECTOR BASE ADDRESS
W
R
0
0
0
0
0
0
0
VBA0
FIVAL0
FIVAH0
FIM1
FIVAL1
FAST INTERRUPT 0
W
R
FAST INTERRUPT 0 VECTOR ADDRESS LOW
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FAST INTERRUPT 0 VECTOR
ADDRESS HIGH
W
R
FAST INTERRUPT 1
W
R
FAST INTERRUPT 1 VECTOR
ADDRESS LOW
W
Figure 5-2 ITCN Register Map Summary
56F8367 Technical Data, Rev. 3.0
84
Freescale Semiconductor
Preliminary
Register Descriptions
Add. Register
Offset Name
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
R
0
0
0
0
0
0
0
0
0
0
0
FAST INTERRUPT 1 VECTOR
ADDRESS HIGH
$10
$11
$12
$13
$14
$15
FIVAH1
IRQP0
IRQP1
IRQP2
IRQP3
IRQP4
PENDING [16:2]
1
W
R
PENDING [32:17]
W
R
PENDING [48:33]
PENDING [64:49]
PENDING [80:65]
W
R
W
R
W
PEND-
ING
[81]
R
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
$16
IRQP5
W
Reserved
ICTL
IRQB
STATE STATE
IRQA
R
INT
0
IPIC
VAB
0
IRQB
EDG
IRQA
EDG
$1D
$1F
INT_DIS
W
Reserved
IPR10
R
0
0
0
0
0
0
FLEXCAN2
MSGBUG IPL
FLEXCAN2
WKUP IPL
FLEXCAN2 ERR
IPL
FLEXCAN2
BOFF IPL
W
= Reserved
Figure 5-2 ITCN Register Map Summary
5.6.1
Interrupt Priority Register 0 (IPR0)
Base + $0
Read
15
0
14
0
13
12
11
10
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
BKPT_U0IPL
STPCNT IPL
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-3 Interrupt Priority Register 0 (IPR0)
5.6.1.1
Reserved—Bits 15–14
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.1.2
EOnCE Breakpoint Unit 0 Interrupt Priority Level (BKPT_U0 IPL)—
Bits13–12
This field is used to set the interrupt priority levels for IRQs. This IRQ is limited to priorities 1 through 3.
It is disabled by default.
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 1
10 = IRQ is priority level 2
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
85
•
11 = IRQ is priority level 3
5.6.1.3
EOnCE Step Counter Interrupt Priority Level (STPCNT IPL)— Bits 11–10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.
It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 1
10 = IRQ is priority level 2
11 = IRQ is priority level 3
5.6.1.4
Reserved—Bits 9–0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.2
Interrupt Priority Register 1 (IPR1)
Base + $1
Read
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
4
3
2
1
0
RX_REG IPL TX_REG IPL
TRBUF IPL
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-4 Interrupt Priority Register 1 (IPR1)
5.6.2.1
Reserved—Bits 15–6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.2.2
EOnCE Receive Register Full Interrupt Priority Level
(RX_REG IPL)—Bits 5–4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.
It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 1
10 = IRQ is priority level 2
11 = IRQ is priority level 3
5.6.2.3
EOnCE Transmit Register Empty Interrupt Priority Level
(TX_REG IPL)—Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.
It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 1
10 = IRQ is priority level 2
11 = IRQ is priority level 3
56F8367 Technical Data, Rev. 3.0
86
Freescale Semiconductor
Preliminary
Register Descriptions
5.6.2.4
EOnCE Trace Buffer Interrupt Priority Level (TRBUF IPL)—Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.
It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 1
10 = IRQ is priority level 2
11 = IRQ is priority level 3
5.6.3
Interrupt Priority Register 2 (IPR2)
Base + $2
Read
15
14
13
12
11
10
9
8
7
6
0
5
0
4
0
3
2
1
0
FMCBE IPL
FMCC IPL
FMERR IPL
LOCK IPL
LVI IPL
IRQB IPL
IRQA IPL
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-5 Interrupt Priority Register 2 (IPR2)
5.6.3.1
Flash Memory Command, Data, Address Buffers Empty Interrupt
Priority Level (FMCBE IPL)—Bits 15–14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.3.2
Flash Memory Command Complete Priority Level (FMCC IPL)—
Bits 13–12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.3.3
Flash Memory Error Interrupt Priority Level (FMERR IPL)—Bits 11–10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
87
5.6.3.4
PLL Loss of Lock Interrupt Priority Level (LOCK IPL)—Bits 9–8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.3.5
Low Voltage Detector Interrupt Priority Level (LVI IPL)—Bits 7–6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.3.6
Reserved—Bits 5–4
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.3.7
External IRQ B Interrupt Priority Level (IRQB IPL)—Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.3.8
External IRQ A Interrupt Priority Level (IRQA IPL)—Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.4
Interrupt Priority Register 3 (IPR3)
Base + $3
Read
15 14 13 12 11 10
GPIOD IPL GPIOE IPL GPIOFIPL
9
8
7
6
5
4
3
2
1
0
0
0
FCMSGBUF IPL
FCWKUP IPL
FCERR IPL
FCBOFF IPL
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-6 Interrupt Priority Register 3 (IPR3)
56F8367 Technical Data, Rev. 3.0
88
Freescale Semiconductor
Preliminary
Register Descriptions
5.6.4.1
GPIOD Interrupt Priority Level (GPIOD IPL)—Bits 15–14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.4.2
GPIOE Interrupt Priority Level (GPIOE IPL)—Bits 13–12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.4.3
GPIOF Interrupt Priority Level (GPIOF IPL)—Bits 11–10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.4.4
FlexCAN Message Buffer Interrupt Priority Level (FCMSGBUF IPL)—
Bits 9–8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.4.5
FlexCAN Wake Up Interrupt Priority Level (FCWKUP IPL)—Bits 7–6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
89
5.6.4.6
FlexCAN Error Interrupt Priority Level (FCERR IPL)— Bits 5–4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.4.7
FlexCAN Bus Off Interrupt Priority Level (FCBOFF IPL)— Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.4.8
Reserved—Bits 1–0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.5
Interrupt Priority Register 4 (IPR4)
Base + $4
Read
15
14
13
12
11
10
9
0
8
0
7
0
6
0
5
4
3
2
1
0
SPI0_RCV
IPL
SPI1_XMIT
IPL
SPI1_RCV
IPL
GPIOA IPL
GPIOB IPL
GPIOC IPL
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-7 Interrupt Priority Register 4 (IPR4)
SPI0 Receiver Full Interrupt Priority Level (SPI0_RCV IPL)—Bits 15–14
5.6.5.1
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.5.2
SPI1 Transmit Empty Interrupt Priority Level (SPI1_XMIT IPL)—
Bits 13–12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
56F8367 Technical Data, Rev. 3.0
90
Freescale Semiconductor
Preliminary
Register Descriptions
•
•
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.5.3
SPI1 Receiver Full Interrupt Priority Level (SPI1_RCV IPL)—Bits 11–10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.5.4
Reserved—Bits 9–6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.5.5
GPIOA Interrupt Priority Level (GPIOA IPL)—Bits 5–4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.5.6
GPIOB Interrupt Priority Level (GPIOB IPL)—Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.5.7
GPIOC Interrupt Priority Level (GPIOC IPL)—Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
91
5.6.6
Interrupt Priority Register 5 (IPR5)
Base + $5
Read
15
14
13
12
11
10
9
8
7
0
6
0
5
4
3
2
1
0
DEC1_XIRQ DEC1_HIRQ
IPL IPL
SCI1_RCV
IPL
SCI1_RERR
IPL
SCI1_TIDL
IPL
SCI1_XMIT
IPL
SPI0_XMIT
IPL
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-8 Interrupt Priority Register 5 (IPR5)
5.6.6.1
Quadrature Decoder 1 INDEX Pulse Interrupt Priority Level (DEC1_XIRQ
IPL)—Bits 15–14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.6.2
Quadrature Decoder 1 HOME Signal Transition or Watchdog Timer
Interrupt Priority Level (DEC1_HIRQ IPL)—Bits 13–12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.6.3
SCI1 Receiver Full Interrupt Priority Level (SCI1_RCV IPL)—Bits 11–10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.6.4
SCI1 Receiver Error Interrupt Priority Level (SCI1_RERR IPL)—Bits 9–8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
56F8367 Technical Data, Rev. 3.0
92
Freescale Semiconductor
Preliminary
Register Descriptions
5.6.6.5
Reserved—Bits 7–6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.6.6
SCI1 Transmitter Idle Interrupt Priority Level (SCI1_TIDL IPL)—Bits 5–4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.6.7
SCI1 Transmitter Empty Interrupt Priority Level (SCI1_XMIT IPL)—
Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.6.8
SPI0 Transmitter Empty Interrupt Priority Level (SPI_XMIT IPL)—
Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.7
Interrupt Priority Register 6 (IPR6)
Base + $6
Read
15
14
13
12
11
10
9
8
7
6
5
0
4
0
3
2
1
0
DEC0_XIRQ
IPL
DEC0_HIRQ
IPL
TMRC0 IPL
TMRD3 IPL
TMRD2 IPL
TMRD1 IPL
TMRD0 IPL
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-9 Interrupt Priority Register 6 (IPR6)
Timer C, Channel 0 Interrupt Priority Level (TMRC0 IPL)—Bits 15–14
5.6.7.1
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
00 = IRQ disabled (default)
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
93
•
•
•
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.7.2
Timer D, Channel 3 Interrupt Priority Level (TMRD3 IPL)—Bits 13–12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.7.3
Timer D, Channel 2 Interrupt Priority Level (TMRD2 IPL)—Bits 11–10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.7.4
Timer D, Channel 1 Interrupt Priority Level (TMRD1 IPL)—Bits 9–8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.7.5
Timer D, Channel 0 Interrupt Priority Level (TMRD0 IPL)—Bits 7–6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.7.6
Reserved—Bits 5–4
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.7.7
Quadrature Decoder 0, INDEX Pulse Interrupt Priority Level
(DEC0_XIRQ IPL)—Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
56F8367 Technical Data, Rev. 3.0
94
Freescale Semiconductor
Preliminary
Register Descriptions
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.7.8
Quadrature Decoder 0, HOME Signal Transition or Watchdog Timer
Interrupt Priority Level (DEC0_HIRQ IPL)—Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.8
Interrupt Priority Register 7 (IPR7)
Base + $7
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TMRA0 IPL
TMRB3 IPL
TMRB2 IPL
TMRB1 IPL
TMRB0 IPL
TMRC3 IPL
TMRC2 IPL
TMRC1 IPL
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-10 Interrupt Priority Register (IPR7)
Timer A, Channel 0 Interrupt Priority Level (TMRA0 IPL)—Bits 15–14
5.6.8.1
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.8.2
Timer B, Channel 3 Interrupt Priority Level (TMRB3 IPL)—Bits 13–12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
95
5.6.8.3
Timer B, Channel 2 Interrupt Priority Level (TMRB2 IPL)—Bits 11–10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.8.4
Timer B, Channel 1 Interrupt Priority Level (TMRB1 IPL)—Bits 9–8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.8.5
Timer B, Channel 0 Interrupt Priority Level (TMRB0 IPL)—Bits 7–6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.8.6
Timer C, Channel 3 Interrupt Priority Level (TMRC3 IPL)—Bits 5–4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.8.7
Timer C, Channel 2 Interrupt Priority Level (TMRC2 IPL)—Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
56F8367 Technical Data, Rev. 3.0
96
Freescale Semiconductor
Preliminary
Register Descriptions
5.6.8.8
Timer C, Channel 1 Interrupt Priority Level (TMRC1 IPL)—Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.9
Interrupt Priority Register 8 (IPR8)
Base + $8
Read
15
14
13
12
11
0
10
0
9
8
7
6
5
4
3
2
1
0
SCI0_RCV
IPL
SCI0_RERR
IPL
SCI0_TIDL
IPL
SCI0_XMIT
IPL
TMRA3 IPL
TMRA2 IPL
TMRA1 IPL
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-11 Interrupt Priority Register 8 (IPR8)
SCI0 Receiver Full Interrupt Priority Level (SCI0_RCV IPL)—Bits 15–14
5.6.9.1
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.9.2
SCI0 Receiver Error Interrupt Priority Level (SCI0_RERR IPL)—
Bits 13–12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.9.3
Reserved—Bits 11–10
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.9.4
SCI0 Transmitter Idle Interrupt Priority Level (SCI0_TIDL IPL)—Bits 9–8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
97
•
•
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.9.5
SCI0 Transmitter Empty Interrupt Priority Level (SCI0_XMIT IPL)—
Bits 7–6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.9.6
Timer A, Channel 3 Interrupt Priority Level (TMRA3 IPL)—Bits 5–4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.9.7
Timer A, Channel 2 Interrupt Priority Level (TMRA2 IPL)—Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.9.8
Timer A, Channel 1 Interrupt Priority Level (TMRA1 IPL)—Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
56F8367 Technical Data, Rev. 3.0
98
Freescale Semiconductor
Preliminary
Register Descriptions
5.6.10 Interrupt Priority Register 9 (IPR9)
Base + $9
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PWMA_RL
IPL
ADCA_CC
IPL
ADCB_CC
IPL
PWMA_F IPL PWMB_F IPL
PWM_RL IPL ADCA_ZC IPL ABCB_ZC IPL
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-12 Interrupt Priority Register 9 (IPR9)
5.6.10.1 PWM A Fault Interrupt Priority Level (PWMA_F IPL)—Bits 15–14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.10.2 PWM B Fault Interrupt Priority Level (PWMB_F IPL)—Bits 13–12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.10.3 Reload PWM A Interrupt Priority Level (PWMA_RL IPL)—Bits 11–10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.10.4 Reload PWM B Interrupt Priority Level (PWMB_RL IPL)—Bits 9–8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
99
5.6.10.5 ADC A Zero Crossing or Limit Error Interrupt Priority Level
(ADCA_ZC IPL)—Bits 7–6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 0.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.10.6 ADC B Zero Crossing or Limit Error Interrupt Priority Level
(ADCB_ZC IPL)—Bits 5–4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.10.7 ADC A Conversion Complete Interrupt Priority Level
(ADCA_CC IPL)—Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.10.8 ADC B Conversion Complete Interrupt Priority Level
(ADCB_CC IPL)—Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
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Freescale Semiconductor
Preliminary
Register Descriptions
5.6.11 Vector Base Address Register (VBA)
Base + $A
Read
15
0
14
0
13
0
12
11
10
9
8
7
6
5
4
0
3
0
2
0
1
0
0
0
VECTOR BASE ADDRESS
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
Figure 5-13 Vector Base Address Register (VBA)
5.6.11.1 Reserved—Bits 15–13
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.11.2 Interrupt Vector Base Address (VECTOR BASE ADDRESS)—
Bits 12–0
The contents of this register determine the location of the Vector Address Table. The value in this register
is used as the upper 13 bits of the interrupt Vector Address Bus (VAB[20:0]). The lower eight bits are
determined based upon the highest-priority interrupt. They are then appended onto VBA before presenting
the full VAB to the 56800E core; see Part 5.3.1 for details.
5.6.12 Fast Interrupt 0 Match Register (FIM0)
Base + $B
Read
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
5
4
3
2
1
0
0
0
FAST INTERRUPT 0
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-14 Fast Interrupt 0 Match Register (FIM0)
5.6.12.1 Reserved—Bits 15–7
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.12.2 Fast Interrupt 0 Vector Number (FAST INTERRUPT 0)—Bits 6–0
This value determines which IRQ will be a Fast Interrupt 0. Fast interrupts vector directly to a service
routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table
first; see Part 5.3.3. IRQs used as fast interrupts must be set to priority level 2. Unexpected results will
occur if a fast interrupt vector is set to any other priority. Fast interrupts automatically become the
highest-priority level 2 interrupt, regardless of their location in the interrupt table, prior to being declared
as fast interrupt. Fast interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each
IRQ, refer to Table 4-5.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
101
5.6.13 Fast Interrupt 0 Vector Address Low Register (FIVAL0)
Base + $C
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
1
0
0
0
FAST INTERRUPT 0 VECTOR ADDRESS LOW
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-15 Fast Interrupt 0 Vector Address Low Register (FIVAL0)
5.6.13.1 Fast Interrupt 0 Vector Address Low (FIVAL0)—Bits 15–0
The lower 16 bits of the vector address are used for Fast Interrupt 0. This register is combined with
FIVAH0 to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.
5.6.14 Fast Interrupt 0 Vector Address High Register (FIVAH0)
Base + $D
Read
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
3
2
1
0
0
FAST INTERRUPT 0 VECTOR
ADDRESS HIGH
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-16 Fast Interrupt 0 Vector Address High Register (FIVAH0)
5.6.14.1 Reserved—Bits 15–5
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.14.2 Fast Interrupt 0 Vector Address High (FIVAH0)—Bits 4–0
The upper five bits of the vector address are used for Fast Interrupt 0. This register is combined with
FIVAL0 to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.
5.6.15 Fast Interrupt 1 Match Register (FIM1)
Base + $E
Read
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
5
4
3
2
1
0
0
0
FAST INTERRUPT 1
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 5-17 Fast Interrupt 1 Match Register (FIM1)
5.6.15.1 Reserved—Bits 15–7
This bit field is reserved or not implemented. It is read as 0, but cannot be modified by writing.
5.6.15.2 Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)—Bits 6–0
This value determines which IRQ will be a Fast Interrupt 1. Fast interrupts vector directly to a service
routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table
first; see Part 5.3.3. IRQs used as fast interrupts must be set to priority level 2. Unexpected results will
occur if a fast interrupt vector is set to any other priority. Fast interrupts automatically become the
56F8367 Technical Data, Rev. 3.0
102
Freescale Semiconductor
Preliminary
Register Descriptions
highest-priority level 2 interrupt, regardless of their location in the interrupt table, prior to being declared
as fast interrupt. Fast interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each
IRQ, refer to Table 4-5.
5.6.16 Fast Interrupt 1 Vector Address Low Register (FIVAL1)
Base + $F
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
FAST INTERRUPT 1 VECTOR
ADDRESS LOW
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-18 Fast Interrupt 1 Vector Address Low Register (FIVAL1)
5.6.16.1 Fast Interrupt 1 Vector Address Low (FIVAL1)—Bits 15–0
The lower 16 bits of vector address are used for Fast Interrupt 1. This register is combined with FIVAH1
to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.
5.6.17 Fast Interrupt 1 Vector Address High Register (FIVAH1)
Base + $10
Read
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
3
2
1
0
0
FAST INTERRUPT 1 VECTOR
ADDRESS HIGH
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-19 Fast Interrupt 1 Vector Address High Register (FIVAH1)
5.6.17.1 Reserved—Bits 15–5
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.17.2 Fast Interrupt 1 Vector Address High (FIVAH1)—Bits 4–0
The upper five bits of vector address are used for Fast Interrupt 1. This register is combined with FIVAL1
to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
103
5.6.18 IRQ Pending 0 Register (IRQP0)
Base + $11
Read
15
14
13
12
11
10
9
8
7
6
1
5
1
4
1
3
1
2
1
1
1
0
1
PENDING [16:2]
Write
RESET
1
1
1
1
1
1
1
1
1
1
Figure 5-20 IRQ Pending 0 Register (IRQP0)
5.6.18.1 IRQ Pending (PENDING)—Bits 16–2
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2
through 81.
•
•
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
5.6.18.2 Reserved—Bit 0
This bit is reserved or not implemented. It is read as 1 and cannot be modified by writing.
5.6.19 IRQ Pending 1 Register (IRQP1)
$Base + $12
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
1
2
1
1
1
0
1
PENDING [32:17]
Write
1
1
1
1
1
1
1
1
1
1
1
1
RESET
Figure 5-21 IRQ Pending 1 Register (IRQP1)
5.6.19.1 IRQ Pending (PENDING)—Bits 32–17
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2
through 81.
•
•
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
5.6.20 IRQ Pending 2 Register (IRQP2)
Base + $13
Read
15
14
13
12
11
10
9
8
7
6
1
5
1
4
1
3
1
2
1
1
1
0
1
PENDING [48:33]
Write
1
1
1
1
1
1
1
1
1
RESET
Figure 5-22 IRQ Pending 2 Register (IRQP2)
5.6.20.1 IRQ Pending (PENDING)—Bits 48–33
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2
through 81.
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104
Freescale Semiconductor
Preliminary
Register Descriptions
•
•
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
5.6.21 IRQ Pending 3 Register (IRQP3)
Base + $14
Read
15
14
13
12
11
10
9
8
7
6
1
5
1
4
1
3
1
2
1
1
1
0
1
PENDING [64:49]
Write
RESET
1
1
1
1
1
1
1
1
1
Figure 5-23 IRQ Pending 3 Register (IRQP3)
5.6.21.1 IRQ Pending (PENDING)—Bits 64–49
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2
through 81.
•
•
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
5.6.22 IRQ Pending 4 Register (IRQP4)
Base + $15
Read
15
14
13
12
11
10
9
8
7
6
1
5
1
4
1
3
1
2
1
1
1
0
1
PENDING [80:65]
Write
RESET
1
1
1
1
1
1
1
1
1
Figure 5-24 IRQ Pending 4 Register (IRQP4)
5.6.22.1 IRQ Pending (PENDING)—Bits 80–65
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2
through 81.
•
•
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
5.6.23 IRQ Pending 5 Register (IRQP5)
Base + $16
Read
15
1
14
1
13
1
12
1
11
1
10
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
0
1
PENDING[85:81]
Write
1
1
1
1
1
1
1
1
1
1
1
1
1
RESET
Figure 5-25 IRQ Pending Register 5 (IRQP5)
5.6.23.1 Reserved—Bits 96–86
This bit field is reserved or not implemented. The bits are read as 1 and cannot be modified by writing.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
105
5.6.23.2 IRQ Pending (PENDING)—Bits 81–85
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2
through 85.
•
•
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
5.6.24 Reserved—Base + 17
5.6.25 Reserved—Base + 18
5.6.26 Reserved—Base + 19
5.6.27 Reserved—Base + 1A
5.6.28 Reserved—Base + 1B
5.6.29 Reserved—Base + 1C
5.6.30 ITCN Control Register (ICTL)
Base + $1D
Read
15
14
13
12 11 10
9
8
7
6
0
5
INT_DIS
0
4
1
3
2
1
0
INT
IPIC
VAB
IRQB STATE IRQA STATE
IRQB IRQA
EDG
EDG
Write
0
0
0
1
0
0
0
0
0
1
1
1
0
0
RESET
Figure 5-26 ITCN Control Register (ICTL)
5.6.30.1 Interrupt (INT)—Bit 15
This read-only bit reflects the state of the interrupt to the 56800E core.
•
•
0 = No interrupt is being sent to the 56800E core
1 = An interrupt is being sent to the 56800E core
5.6.30.2 Interrupt Priority Level (IPIC)—Bits 14–13
These read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800E
core at the time the last IRQ was taken. This field is only updated when the 56800E core jumps to a new
interrupt service routine.
Note:
Nested interrupts may cause this field to be updated before the original interrupt service routine can
read it.
•
•
•
•
00 = Required nested exception priority levels are 0, 1, 2, or 3
01 = Required nested exception priority levels are 1, 2, or 3
10 = Required nested exception priority levels are 2 or 3
11 = Required nested exception priority level is 3
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Freescale Semiconductor
Preliminary
Register Descriptions
5.6.30.3 Vector Number - Vector Address Bus (VAB)—Bits 12–6
This read-only field shows the vector number (VAB[7:1]) used at the time the last IRQ was taken. This
field is only updated when the 56800E core jumps to a new interrupt service routine.
Note:
Nested interrupts may cause this field to be updated before the original interrupt service routine can
read it.
5.6.30.4 Interrupt Disable (INT_DIS)—Bit 5
This bit allows all interrupts to be disabled.
•
•
0 = Normal operation (default)
1 = All interrupts disabled
5.6.30.5 Reserved—Bit 4
This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.
5.6.30.6 IRQB State Pin (IRQB STATE)—Bit 3
This read-only bit reflects the state of the external IRQB pin.
5.6.30.7 IRQA State Pin (IRQA STATE)—Bit 2
This read-only bit reflects the state of the external IRQA pin.
5.6.30.8 IRQB Edge Pin (IRQB Edg)—Bit 1
This bit controls whether the external IRQB interrupt is edge- or level-sensitive. During Stop and Wait
modes, it is automatically level-sensitive.
•
•
0 = IRQB interrupt is a low-level sensitive (default)
1 = IRQB interrupt is falling-edge sensitive
5.6.30.9 IRQA Edge Pin (IRQA Edg)—Bit 0
This bit controls whether the external IRQA interrupt is edge- or level-sensitive. During Stop and Wait
modes, it is automatically level-sensitive.
•
•
0 = IRQA interrupt is a low-level sensitive (default)
1 = IRQA interrupt is falling-edge sensitive
5.6.31 Reserved—Base + $1E
5.6.32 Interrupt Priority Register 10 (IPR10)
Base + $1F
Read
15
0
14
0
13
0
12 11 10
9
0
8
0
7
6
5
4
3
2
1
0
0
0
0
FLEXCAN2_
MSGBUF IPL
FLEXCAN2_
WKUP IPL
FLEXCAN2_
BOFF IPL
FLEXCAN2_
ERR IPL
Write
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Note: This register is NOT available in the 56F8167 device.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
107
5.6.32.1 Reserved—Bits 15 - 8
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.32.2 FlexCAN2 Message Buffer Interrupt Priority Level
(FlexCAN2_MSGBUF IPL)—Bits 7 - 6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.32.3 FlexCAN2 Wake Up Interrupt Priority Level (FlexCAN2_WKUP IPL)—
Bits 5 - 4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.32.4 FlexCAN2 Error Interrupt Priority Level (FlexCAN2_ERR IPL)—Bits 3 - 2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.32.5 FlexCAN2 Bus-Off Interrupt Priority Level (FlexCAN2_BOFF IPL)—
Bits 1 - 0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.7 Resets
5.7.1
Reset Handshake Timing
The ITCN provides the 56800E core with a reset vector address whenever RESET is asserted. The reset
56F8367 Technical Data, Rev. 3.0
108
Freescale Semiconductor
Preliminary
Resets
vector will be presented until the second rising clock edge after RESET is released.
5.7.2
ITCN After Reset
After reset, all of the ITCN registers are in their default states. This means all interrupts are disabled,
except the core IRQs with fixed priorities:
•
•
•
•
•
•
•
•
Illegal Instruction
SW Interrupt 3
HW Stack Overflow
Misaligned Long Word Access
SW Interrupt 2
SW Interrupt 1
SW Interrupt 0
SW Interrupt LP
These interrupts are enabled at their fixed priority levels.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
109
Part 6 System Integration Module (SIM)
6.1 Overview
The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls
distribution of resets and clocks and provides a number of control features. The system integration module
is responsible for the following functions:
•
•
•
•
•
•
•
Reset sequencing
Clock generation & distribution
Stop/Wait control
Pull-up Enables for Selected Peripherals
System status registers
Registers for software access to the JTAG ID of the chip
Enforcing Flash security
These are discussed in more detail in the sections that follow.
6.2 Features
The SIM has the following features:
•
•
•
Flash security feature prevents unauthorized access to code/data contained in on-chip Flash memory
Power-saving clock gating for peripheral
Three power modes (Run, Wait, Stop) to control power utilization
— Stop mode shuts down 56800E core, system clock, peripheral clock, and PLL operation
— Stop mode entry can optionally disable PLL and Oscillator (low power vs. fast restart); must be done
explicitly
— Wait mode shuts down the 56800E core, and unnecessary system clock operation
— Run mode supports full part operation
•
•
Controls to enable/disable the 56800E core WAIT and STOP instructions
Calculates base delay for reset extension based upon POR or RESET operations. Reset delay will be either
3 x 32 clocks for reset, except for POR, which is 2 clock cycles.
21
•
•
•
•
•
Controls reset sequencing after reset
Software-initiated reset
Four 16-bit registers reset only by a Power-On Reset usable for general purpose software control
System Control Register
Registers for software access to the JTAG ID of the chip
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110
Freescale Semiconductor
Preliminary
Operating Modes
6.3 Operating Modes
Since the SIM is responsible for distributing clocks and resets across the chip, it must understand the
various chip operating modes and take appropriate action. These are:
•
Reset Mode, which has two submodes:
— POR and RESET operation
The 56800E core and all peripherals are reset. This occurs when the internal POR is asserted or the
RESET pin is asserted.
— COP reset and software reset operation
The 56800E core and all peripherals are reset. The MA bit within the OMR is not changed. This allows
the software to determine the boot mode (internal or external boot) to be used on the next reset.
•
•
Run Mode
This is the primary mode of operation for this device. In this mode, the 56800E controls chip operation
Debug Mode
The 56800E is controlled via JTAG/EOnCE when in debug mode. All peripherals, except the COP and
PWMs, continue to run. COP is disabled and PWM outputs are optionally switched off to disable any motor
from being driven; see the PWM chapter in the 56F8300 Peripheral User Manual for details.
•
•
Wait Mode
In Wait mode, the core clock and memory clocks are disabled. Optionally, the COP can be stopped.
Similarly, it is an option to switch off PWM outputs to disable any motor from being driven. All other
peripherals continue to run.
Stop Mode
When in Stop mode, the 56800E core, memory, and most peripheral clocks are shut down. Optionally, the
COP and CAN can be stopped. For lowest power consumption in Stop mode, the PLL can be shut down.
This must be done explicitly before entering Stop mode, since there is no automatic mechanism for this. The
CAN (along with any non-gated interrupt) is capable of waking the chip up from Stop mode, but is not fully
functional in Stop mode.
6.4 Operating Mode Register
Bit
15
NL
R/W
0
14
13
12
11
10
9
0
8
CM
R/W
0
7
XP
R/W
0
6
SD
R/W
0
5
R
4
SA
R/W
0
3
EX
R/W
0
2
0
1
MB
R/W
X
0
MA
R/W
X
Type
R/W
0
RESET
0
0
0
0
0
0
Figure 6-1 OMR
The reset state for MB and MA will depend on the Flash secured state. See Part 4.2 and Part 7 for detailed
information on how the Operating Mode Register (OMR) MA and MB bits operate in this device. For all
other bits, see the DSP56800E Reference Manual.
Note:
The OMR is not a Memory Map register; it is directly accessible in code through the acronym OMR.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
111
6.5 Register Descriptions
Table 6-1 SIM Registers
(SIM_BASE = $00 F350)
Address Offset
Address Acronym
Register Name
Section Location
Base + $0
Base + $1
Base + $2
Base + $3
Base + $4
Base + $5
Base + $6
Base + $7
Base + $8
SIM_CONTROL
SIM_RSTSTS
SIM_SCR0
Control Register
6.5.1
6.5.2
6.5.3
6.5.3
6.5.3
6.5.3
6.5.4
6.5.5
6.5.6
Reset Status Register
Software Control Register 0
Software Control Register 1
Software Control Register 2
Software Control Register 3
Most Significant Half of JTAG ID
Least Significant Half of JTAG ID
Pull-up Disable Register
SIM_SCR1
SIM_SCR2
SIM_SCR3
SIM_MSH_ID
SIM_LSH_ID
SIM_PUDR
Reserved
Base + $A
Base + $B
Base + $C
Base + $D
Base + $E
Base + $F
SIM_CLKOSR
SIM_GPS
CLKO Select Register
6.5.7
6.5.8
GPIO Peripheral Select Register
Peripheral Clock Enable Register
I/O Short Address Location High Register
I/O Short Address Location Low Register
Peripheral Clock Enable Register 2
SIM_PCE
6.5.9
SIM_ISALH
SIM_ISALL
SIM_PCE2
6.5.10
6.5.10
6.5.11
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112
Freescale Semiconductor
Preliminary
Register Descriptions
Add.
Offset
Register
Name
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
R
0
0
0
0
0
0
0
0
0
SIM_
CONTROL
EMI_ ONCE
MODE EBL0
SW
RST
STOP_
DISABLE
WAIT_
DISABLE
$0
$1
$2
$3
$4
$5
$6
$7
$8
0
0
0
0
0
0
0
0
0
0
0
0
SIM_
RSTSTS
SWR COPR EXTR POR
W
R
SIM_SCR0
SIM_SCR1
SIM_SCR2
SIM_SCR3
FIELD
FIELD
FIELD
FIELD
W
R
W
R
W
R
W
R
0
1
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
1
1
0
0
1
1
1
0
1
0
0
0
1
0
SIM_MSH_
ID
W
R
SIM_LSH_ID
W
R
PWMA
1
EMI_
MODE
PWMA
0
SIM_PUDR
Reserved
CAN
RESET IRQ XBOOT PWMB
CTRL
JTAG
W
R
W
R
0
0
0
0
0
0
0
0
0
0
0
0
SIM_
CLKOSR
$A
$B
$C
$D
$E
$F
A23
0
A22
0
A21
0
A20 CLKDIS
CLKOSEL
C2
0
SIM_GPS
SIM_PCE
D1
D0
C3
C1
C0
W
R
PWM PWM
B
EMI
1
ADCB ADCA CAN DEC1 DEC0 TMRD TMRC TMRB TMRA SCI1
SCI0 SPI1
SPI0
1
A
W
R
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
SIM_ISALH
SIM_ISALL
SIM_PCE2
ISAL[23:22]
W
R
ISAL[21:6]
W
R
0
0
0
0
0
0
0
0
0
0
0
0
CAN2
W
= Reserved
Figure 6-2 SIM Register Map Summary
6.5.1
SIM Control Register (SIM_CONTROL)
Base + $0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
5
4
3
2
1
0
Read
Write
EMI_ ONCE SW
MODE EBL
STOP_
DISABLE
WAIT_
DISABLE
RST
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-3 SIM Control Register (SIM_CONTROL)
Reserved—Bits 15–7
6.5.1.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
113
6.5.1.2
EMI_MODE (EMI_MODE)—Bit 6
This bit reflects the current (non-clocked) state of the EMI_MODE pin. During reset, this bit, coupled with
the EXTBOOT signal, is used to initialize address bits [19:16] either as GPIO or as address. These settings
can be explicitly overwritten using the appropriate GPIO peripheral enable register at any time after reset.
In addition, this pin can be used as a general purpose input pin after reset.
•
•
0 = External address bits [19:16] are initially programmed as GPIO
1 = When booted with EXTBOOT = 1, A[19:16] are initially programmed as address. If EXTBOOT is 0,
they are initialized as GPIO.
6.5.1.3
OnCE Enable (OnCE EBL)—Bit 5
•
•
0 = OnCE clock to 56800E core enabled when core TAP is enabled
1 = OnCE clock to 56800E core is always enabled
6.5.1.4
Software Reset (SW RST)—Bit 4
This bit is always read as 0. Writing a 1 to this bit will cause the part to reset.
6.5.1.5
Stop Disable (STOP_DISABLE)—Bits 3–2
•
•
00 - Stop mode will be entered when the 56800E core executes a STOP instruction
01 - The 56800E STOP instruction will not cause entry into Stop mode; STOP_DISABLE can be
reprogrammed in the future
•
•
10 - The 56800E STOP instruction will not cause entry into Stop mode; STOP_DISABLE can then only be
changed by resetting the device
11 - Same operation as 10
6.5.1.6
Wait Disable (WAIT_DISABLE)—Bits 1–0
•
•
00 - Wait mode will be entered when the 56800E core executes a WAIT instruction
01 - The 56800E WAIT instruction will not cause entry into Wait mode; WAIT_DISABLE can be
reprogrammed in the future
•
10 - The HawkV2 WAIT instruction will not cause entry into Wait mode; WAIT_DISABLE can then only
be changed by resetting the device
•
11 - Same operation as 10
6.5.2
SIM Reset Status Register (SIM_RSTSTS)
Bits in this register are set upon any system reset and are initialized only by a Power-On Reset (POR). A
reset (other than POR) will only set bits in the register; bits are not cleared. Only software should clear this
register.
Base + $1
Read
15
0
14
0
13
O
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
4
3
2
1
0
0
0
SWR COPR
EXTR POR
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-4 SIM Reset Status Register (SIM_RSTSTS)
56F8367 Technical Data, Rev. 3.0
114
Freescale Semiconductor
Preliminary
Register Descriptions
6.5.2.1
Reserved—Bits 15–6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.2.2
Software Reset (SWR)—Bit 5
When 1, this bit indicates that the previous reset occurred as a result of a software reset (write to SW RST
bit in the SIM_CONTROL register). This bit will be cleared by any hardware reset or by software. Writing
a 0 to this bit position will set the bit, while writing a 1 to the bit will clear it.
6.5.2.3
COP Reset (COPR)—Bit 4
When 1, the COPR bit indicates the Computer Operating Properly (COP) timer-generated reset has
occurred. This bit will be cleared by a Power-On Reset or by software. Writing a 0 to this bit position will
set the bit, while writing a 1 to the bit will clear it.
6.5.2.4
External Reset (EXTR)—Bit 3
If 1, the EXTR bit indicates an external system reset has occurred. This bit will be cleared by a Power-On
Reset or by software. Writing a 0 to this bit position will set the bit, while writing a 1 to the bit position
will clear it. Basically, when the EXTR bit is 1, the previous system reset was caused by the external
RESET pin being asserted low.
6.5.2.5
Power-On Reset (POR)—Bit 2
When 1, the POR bit indicates a Power-On Reset occurred some time in the past. This bit can only be
cleared by software or by another type of reset. Writing a 0 to this bit will set the bit while writing a 1 to
the bit position will clear the bit. In summary, if the bit is 1, the previous system reset was due to a
Power-On Reset.
6.5.2.6
Reserved—Bits 1–0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.3
SIM Software Control Registers (SIM_SCR0, SIM_SCR1, SIM_SCR2,
and SIM_SCR3)
Only SIM_SCR0 is shown below. SIM_SCR1, SIM_SCR2, and SIM_SCR3 are identical in functionality.
Base + $2
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
1
0
0
0
FIELD
0
Write
0
0
0
0
0
0
0
0
0
0
0
0
POR
Figure 6-5 SIM Software Control Register 0 (SIM_SCR0)
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
115
6.5.3.1
Software Control Data 1 (FIELD)—Bits 15–0
This register is reset only by the Power-On Reset (POR). It has no part-specific functionality and is
intended for use by a software developer to contain data that will be unaffected by the other reset sources
(RESET pin, software reset, and COP reset).
6.5.4
Most Significant Half of JTAG ID (SIM_MSH_ID)
This read-only register displays the most significant half of the JTAG ID for the chip. This register reads
$01D6.
Base + $6
Read
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
1
7
1
6
1
5
0
4
1
3
0
2
1
1
1
0
0
Write
RESET
0
0
0
0
0
0
0
1
1
1
0
1
0
1
1
0
Figure 6-6 Most Significant Half of JTAG ID (SIM_MSH_ID)
6.5.5
Least Significant Half of JTAG ID (SIM_LSH_ID)
This read-only register displays the least significant half of the JTAG ID for the chip. This register reads
$D01D.
Base + $7
Read
15
1
14
1
13
0
12
1
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
1
3
1
2
1
1
0
0
1
Write
RESET
1
1
0
1
0
0
0
0
0
0
0
1
1
1
0
1
Figure 6-7 Least Significant Half of JTAG ID (SIM_LSH_ID)
6.5.6
SIM Pull-up Disable Register (SIM_PUDR)
Most of the pins on the chip have on-chip pull-up resistors. Pins which can operate as GPIO can have these
resistors disabled via the GPIO function. Non-GPIO pins can have their pull-ups disabled by setting the
appropriate bit in this register. Disabling pull-ups is done on a peripheral-by-peripheral basis (for pins not
muxed with GPIO). Each bit in the register (see Figure 6-8) corresponds to a functional group of pins. See
Table 2-2 to identify which pins can deactivate the internal pull-up resistor.
Base + $8 15
14
13
12
11
10
9
8
7
6
0
5
CTRL
0
4
0
3
JTAG
0
2
0
1
0
0
0
Read
Write
0
EMI_
MODE
PWMA1 CAN
RESET IRQ XBOOT PWMB PWMA0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 6-8 SIM Pull-up Disable Register (SIM_PUDR)
56F8367 Technical Data, Rev. 3.0
116
Freescale Semiconductor
Preliminary
Register Descriptions
6.5.6.1
Reserved —Bit 15
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.6.2
PWMA1—Bit 14
This bit controls the pull-up resistors on the FAULTA3 pin.
6.5.6.3
CAN—Bit 13
This bit controls the pull-up resistors on the CAN_RX pin.
6.5.6.4
EMI_MODE—Bit 12
This bit controls the pull-up resistors on the EMI_MODE pin.
6.5.6.5
RESET—Bit 11
This bit controls the pull-up resistors on the RESET pin.
6.5.6.6
IRQ—Bit 10
This bit controls the pull-up resistors on the IRQA and IRQB pins.
6.5.6.7
XBOOT—Bit 9
This bit controls the pull-up resistors on the EXTBOOT pin.
Note:
In this package, this input pin is double-bonded with the adjacent V pin and this bit should be
SS
changed to a 1 in order to reduce power consumption.
6.5.6.8
PWMB—Bit 8
This bit controls the pull-up resistors on the FAULTB0, FAULTB1, FAULTB2, and FAULTB3 pins.
6.5.6.9 PWMA0—Bit 7
This bit controls the pull-up resistors on the FAULTA0, FAULTA1, and FAULTA2 pins.
6.5.6.10 Reserved—Bit 6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.6.11 CTRL—Bit 5
This bit controls the pull-up resistors on the WR and RD pins.
6.5.6.12 Reserved—Bit 4
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
117
6.5.6.13 JTAG—Bit 3
This bit controls the pull-up resistors on the TRST, TMS and TDI pins.
6.5.6.14 Reserved—Bit 2–0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.7
CLKO Select Register (SIM_CLKOSR)
The CLKO select register can be used to multiplex out any one of the clocks generated inside the clock
generation and SIM modules. The default value is SYS_CLK. All other clocks primarily muxed out are
for test purposes only, and are subject to significant phase shift at high frequencies.
The upper four bits of the GPIOB register can function as GPIO, [A23:20], or as additional clock output
signals. GPIO has priority and is enabled/disabled via the GPIOB_PER. If GPIOB[7:4] are programmed
to operate as peripheral outputs, then the choice between [A23:20] and additional clock outputs is done
here in the CLKOSR. The default state is for the peripheral function of GPIOB[7:4] to be programmed as
[A23:20]. This can be changed by altering [A23:20] as shown in Figure 6-9.
Base + $A
Read
15
0
14
0
13
0
12
0
11
0
10
0
9
A23
0
8
A22
0
7
A21
0
6
A20
0
5
4
3
0
2
CLKOSEL
0
1
0
0
0
CLK
DIS
Write
RESET
0
0
0
0
0
0
1
0
Figure 6-9 CLKO Select Register (SIM_CLKOSR)
6.5.7.1
Reserved—Bits 15–10
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.7.2
Alternate GPIOB Peripheral Function for A23 (A23)—Bit 9
•
•
0 = Peripheral output function of GPIOB7 is defined to be A23
1 = Peripheral output function of GPIOB7 is defined to be the oscillator_clock (MSTR_OSC in Figure 3-4)
6.5.7.3
Alternate GPIOB Peripheral Function for A22 (A22)—Bit 8
•
•
0 = Peripheral output function of GPIOB6 is defined to be A22
1 = Peripheral output function of GPIOB6 is defined to be SYS_CLK2
6.5.7.4
Alternate GPIOB Peripheral Function for A21 (A21)—Bit 7
•
•
0 = Peripheral output function of GPIOB5 is defined to be A21
1 = Peripheral output function of GPIOB5 is defined to be SYS_CLK
6.5.7.5
Alternate GPIOB Peripheral Function fpr A20 (A20)—Bit 6
•
•
0 = Peripheral output function of GPIOB4 is defined to be A20
1 = Peripheral output function of GPIOB4 is defined to be the prescaler_clock (FREF in Figure 3-4)
56F8367 Technical Data, Rev. 3.0
118
Freescale Semiconductor
Preliminary
Register Descriptions
6.5.7.6
Clockout Disable (CLKDIS)—Bit 5
•
•
0 = CLKOUT output is enabled and will output the signal indicated by CLKOSEL
1 = CLKOUT is tri-stated
6.5.7.7
CLockout Select (CLKOSEL)—Bits 4–0
Selects clock to be muxed out on the CLKO pin.
•
•
•
•
•
•
•
•
•
00000 = SYS_CLK (from OCCS - DEFAULT)
00001 = Reserved for factory test—56800E clock
00010 = Reserved for factory test—XRAM clock
00011 = Reserved for factory test—PFLASH odd clock
00100 = Reserved for factory test—PFLASH even clock
00101 = Reserved for factory test—BFLASH clock
00110 = Reserved for factory test—DFLASH clock
00111 = Oscillator output
01000 = F (from OCCS)
out
•
•
•
•
•
•
•
•
•
01001 = Reserved for factory test—IPB clock
01010 = Reserved for factory test—Feedback (from OCCS, this is path to PLL)
01011 = Reserved for factory test—Prescaler clock (from OCCS)
01100 = Reserved for factory test—Postscaler clock (from OCCS)
01101 = Reserved for factory test—SYS_CLK2 (from OCCS)
01110 = Reserved for factory test—SYS_CLK_DIV2
01111 = Reserved for factory test—SYS_CLK_D
10000 = ADCA clock
10001 = ADCB clock
6.5.8
GPIO Peripheral Select Register (SIM_GPS)
Some GPIO pads can have more than one peripheral selected as the alternate function instead of GPIO.
For these pads, this register selects which of the alternate peripherals are actually selected for the GPIO
peripheral function. This applies to GPIOC, pins 0-3, and to GPIOD, pins 0 and 1.
The GPIOC Peripheral Select register can be used to multiplex out any one of the three alternate
peripherals for GPIOC. The default peripheral is Quad Decoder 1 and Quad Timer B (NOT available in
the 56F8167 device); these peripherals work together.
The four I/O pins associated with GPIOC can function as GPIO, Quad Decoder 1/Quad TimerB , or as
SPI 1 signals. GPIO is not the default and is enabled/disabled via the GPIOC_PER, as shown in
Figure 6-10 and Table 6-2. When GPIOC[3:0] are programmed to operate as peripheral I/O, then the
choice between decoder/timer and SPI inputs/outputs is made in the SIM_GPS register and in conjunction
with the Quad Timer Status and Control Registers (SCR). The default state is for the peripheral function
of GPIOC[3:0] to be programmed as decoder functions. This can be changed by altering the appropriate
controls in the indicated registers.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
119
GPIOC_PER Register
GPIO Controlled
0
1
I/O Pad Control
SIM_ GPS Register
0
1
Quad Timer Controlled
SPI Controlled
Figure 6-10 Overall Control of GPIOC Pads Using SIM_GPS Control
1
Table 6-2 Control of GPIOC Pads Using SIM_GPS Control
Control Registers
Pin Function
Comments
GPIO Input
0
0
1
0
1
—
—
0
—
—
0
GPIO Output
Quad Timer Input / Quad
Decoder Input 2
—
See the “Switch Matrix for Inputs to the Timer”
table in the 56F8300 Peripheral User Manual
for the definition of timer inputs based on the
Quad Decoder mode configuration.
Quad Timer Output / Quad
Decoder Input 3
1
—
0
1
SPI input
1
1
—
—
1
1
—
—
See SPI controls for determining the direction
of each of the SPI pins.
SPI output
1. This applies to the four pins that serve as Quad Decoder / Quad Timer / SPI / GPIOC functions. A separate set of control bits is
used for each pin.
2. Reset configuration
3. Quad Decoder pins are always inputs and function in conjunction with the Quad Timer pins.
Two Input/Output pins associated with GPIOD can function as GPIO, EMI (default peripheral) or CAN2
(NOT available on the 56F8167 device) signals. GPIO is the default and is enabled/disabled via the
GPIOD_PER, as shown in Figure 6-11 and Table 6-3. When GPIOD[1:0] are programmed to operate as
peripheral input/output, then the choice between EMI and CAN2 inputs/outputs is made here in the GPS.
56F8367 Technical Data, Rev. 3.0
120
Freescale Semiconductor
Preliminary
Register Descriptions
GPIOD_PER Register
GPIO Controlled
0
1
I/O Pad Control
SIM_ GPS Register
0
1
EMI Controlled
CAN2 Controlled
Figure 6-11 Overall Control of GPIOD Pads Using SIM_GPS Control
1
Table 6-3 Control of GPIOD Pads Using SIM_GPS Control
Control Registers
Pin Function
Comments
GPIO Input
0
0
1
1
0
1
—
—
0
GPIO Output
EMI I/O
—
—
EMI CSn pins are always outputs
CAN2
1
CAN2_TX is always an output
CAN2_RX is always an input
1. This applies to the two pins that serve as EMI CSn / CAN2 / GPIOD functions. A separate set of control bits is used for
each pin.
Base + $B
Read
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
D1
0
4
D0
0
3
C3
0
2
C2
0
1
C1
0
0
C0
0
Write
0
0
0
0
0
0
0
0
0
0
RESET
Figure 6-12 GPIO Peripheral Select Register (SIM_GPS)
Reserved—Bits 15–6
6.5.8.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
121
6.5.8.2
GPIOD1 (D1)—Bit 5
This bit selects the alternate function for GPIOD1.
•
•
0 = CS3
1 = CAN2_RX
6.5.8.3
GPIOD0 (D0)—Bit 4
•
•
0 = CS2
1 = CAN2_TX
6.5.8.4
GPIOC3 (C3)—Bit 3
This bit selects the alternate function for GPIOC3.
•
0 = HOME1/TB3 (default - see “Switch Matrix Mode” bits of the Quad Decoder DECCR register in the
56F8300 Peripheral User Manual)
•
1 = SS1
6.5.8.5
GPIOC2 (C2)—Bit 2
This bit selects the alternate function for GPIOC2.
•
•
0 = INDEX1/TB2 (default)
1 = MISO1
6.5.8.6
GPIOC1 (C1)—Bit 1
This bit selects the alternate function for GPIOC1.
•
•
0 = PHASEB1/TB1 (default)
1 = MOSI1
6.5.8.7
GPIOC0 (C0)—Bit 0
This bit selects the alternate function for GPIOC0.
•
•
0 = PHASEA1/TB0 (default)
1 = SCLK1
6.5.9
Peripheral Clock Enable Register (SIM_PCE)
The Peripheral Clock Enable register is used enable or disable clocks to the peripherals as a power savings
feature. The clocks can be individually controlled for each peripheral on the chip.
Base + $C
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EMI ADCB ADCA CAN DEC1 DEC0 TMRD TMRC TMRB TMRA SCI 1 SCI 0 SPI 1 SPI 0 PWMB PWMA
Write
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RESET
Figure 6-13 Peripheral Clock Enable Register (SIM_PCE)
56F8367 Technical Data, Rev. 3.0
122
Freescale Semiconductor
Preliminary
Register Descriptions
6.5.9.1
External Memory Interface Enable (EMI)—Bit 15
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.2
Analog-to-Digital Converter B Enable (ADCB)—Bit 14
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.3
Analog-to-Digital Converter A Enable (ADCA)—Bit 13
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.4
FlexCAN Enable (CAN)—Bit 12
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.5
Decoder 1 Enable (DEC1)—Bit 11
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.6
Decoder 0 Enable (DEC0)—Bit 10
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.7
Quad Timer D Enable (TMRD)—Bit 9
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.8
Quad Timer C Enable (TMRC)—Bit 8
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
123
6.5.9.9
Quad Timer B Enable (TMRB)—Bit 7
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.10 Quad Timer A Enable (TMRA)—Bit 6
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.11 Serial Communications Interface 1 Enable (SCI1)—Bit 5
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.12 Serial Communications Interface 0 Enable (SCI0)—Bit 4
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.13 Serial Peripheral Interface 1 Enable (SPI1)—Bit 3
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.14 Serial Peripheral Interface 0 Enable (SPI0)—Bit 2
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.15 Pulse Width Modulator B Enable (PWMB)—1
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.16 Pulse Width Modulator A Enable (PWMA)—0
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
56F8367 Technical Data, Rev. 3.0
124
Freescale Semiconductor
Preliminary
Register Descriptions
6.5.10 I/O Short Address Location Register (SIM_ISALH and SIM_ISALL)
The I/O Short Address Location registers are used to specify the memory referenced via the I/O short
address mode. The I/O short address mode allows the instruction to specify the lower six bits of address;
the upper address bits are not directly controllable. This register set allows limited control of the full
address, as shown in Figure 6-14.
Note:
If this register is set to something other than the top of memory (EOnCE register space) and the EX bit
in the OMR is set to 1, the JTAG port cannot access the on-chip EOnCE registers, and debug functions
will be affected.
Instruction Portion
“Hard Coded” Address Portion
6 Bits from I/O Short Address Mode Instruction
16 Bits from SIM_ISALL Register
2 bits from SIM_ISALH Register
Full 24-Bit for Short I/O Address
Figure 6-14 I/O Short Address Determination
With this register set, an interrupt driver can set the SIM_ISALL register pair to point to its peripheral
registers and then use the I/O Short addressing mode to reference them. The ISR should restore this register
to its previous contents prior to returning from interrupt.
Note:
Note:
The default value of this register set points to the EOnCE registers.
The pipeline delay between setting this register set and using short I/O addressing with the new value
is three cycles.
Base + $D
Read
15
1
14
1
13
1
12
1
11
1
10
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
0
ISAL[23:22]
Write
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RESET
Figure 6-15 I/O Short Address Location High Register (SIM_ISALH)
6.5.10.1 Input/Output Short Address Low (ISAL[23:22])—Bit 1–0
This field represents the upper two address bits of the “hard coded” I/O short address.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
125
Base + $E
Read
15
1
14
1
13
1
12
1
11
1
10
1
9
1
8
7
6
1
5
1
4
1
3
1
2
1
1
1
0
1
ISAL[21:6]
Write
1
1
RESET
Figure 6-16 I/O Short Address Location Low Register (SIM_ISAL)
6.5.10.2 Input/Output Short Address Low (ISAL[21:6])—Bit 15–0
This field represents the lower 16 address bits of the “hard coded” I/O short address.
6.5.11 Peripheral Clock Enable Register 2 (SIM_PCE2)
The Peripheral Clock Enable Register 2 is used to enable or disable clocks to the peripherals as a
power-saving feaure. The clocks can be individually controller for each peripheral on the chip.
Base + $D
Read
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
CAN
2
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
RESET
6.5.11.1 Reserved—Bits 15–1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.11.2 CAN2 Enable—Bit 0
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.6 Clock Generation Overview
The SIM uses an internal master clock from the OCCS (CLKGEN) module to produce the peripheral and
system (core and memory) clocks. The maximum master clock frequency is 120MHz. Peripheral and
system clocks are generated at half the master clock frequency and therefore at a maximum 60MHz. The
SIM provides power modes (Stop, Wait) and clock enables (SIM_PCE register, CLK_DIS, ONCE_EBL)
to control which clocks are in operation. The OCCS, power modes, and clock enables provide a flexible
means to manage power consumption.
56F8367 Technical Data, Rev. 3.0
126
Freescale Semiconductor
Preliminary
Power Down Modes Overview
Power utilization can be minimized in several ways. In the OCCS, crystal oscillator, and PLL may be shut
down when not in use. When the PLL is in use, its prescaler and postscaler can be used to limit PLL and
master clock frequency. Power modes permit system and/or peripheral clocks to be disabled when unused.
Clock enables provide the means to disable individual clocks. Some peripherals provide further controls
to disable unused sub-functions. Refer to Part 3 On-Chip Clock Synthesis (OCCS), and the 56F8300
Peripheral User Manual for further details.
6.7 Power Down Modes Overview
The 56F8367/56F8167 operate in one of three power-down modes as shown in Table 6-3
.
Table 6-4 Clock Operation in Power Down Modes
Mode
Run
Core Clocks
Active
Peripheral Clocks
Description
Device is fully functional
Active
Active
Peripherals are active and can produce interrupts if they
have not been masked off.
Wait
Core and memory
clocks disabled
Interrupts will cause the core to come out of its
suspended state and resume normal operation.
Typically used for power-conscious applications.
The only possible recoveries from Stop mode are:
1. CAN traffic (1st message will be lost)
2. Non-clocked interrupts
3. COP reset
Stop
System clocks continue to be generated in
the SIM, but most are gated prior to
reaching memory, core and peripherals.
4. External reset
5. Power-on reset
All peripherals, except the COP/watchdog timer, run off the IPBus clock frequency, which is the same as
the main processor frequency in this architecture. The maximum frequency of operation is
SYS_CLK = 60MHz.
Refer to the PCE register in Part 6.5.9 and ADC power modes. Power is a function of the system
frequency which can be controlled through the OCCS.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
127
6.8 Stop and Wait Mode Disable Function
Permanent
Disable
D
Q
D-FLOP
C
56800E
Reprogrammable
Disable
STOP_DIS
D
Q
D-FLOP
Clock
C
R
Select
Note: Wait disable circuit is similar
Reset
Figure 6-17 Stop Disable Circuit
The 56800E core contains both STOP and WAIT instructions. Both put the CPU to sleep. For lowest
power consumption in Stop mode, the PLL can be shut down. This must be done explicitly before entering
Stop mode, since there is no automatic mechanism for this. When the PLL is shut down, the 56800E
system clock must be set equal to the oscillator output.
Some applications require the 56800E STOP/WAIT instructions be disabled. To disable those
instructions, write to the SIM control register (SIM_CONTROL) described in Part 6.5.1. This procedure
can be on either a permanent or temporary basis. Permanently assigned applications last only until their
next reset.
6.9 Resets
The SIM supports four sources of reset. The two asynchronous sources are the external reset pin and the
Power-On Reset (POR). The two synchronous sources are the software reset, which is generated within
the SIM itself by writting to the SIM_CONTROL register, and the COP reset.
Reset begins with the assertion of any of the reset sources. Release of reset to various blocks is sequenced
21
to permit proper operation of the device. A POR reset is first extended for 2 clock cycles to permit
stabilization of the clock source, followed by a 32 clock window in which SIM clocking is initiated. It is
then followed by a 32 clock window in which peripherals are released to implement Flash security, and,
finally, followed by a 32 clock window in which the core is initialized. After completion of the described
reset sequence, application code will begin execution.
Resets may be asserted asynchronously, but are always released internally on a rising edge of the system
clock.
56F8367 Technical Data, Rev. 3.0
128
Freescale Semiconductor
Preliminary
Operation with Security Enabled
Part 7 Security Features
The 56F8367/56F8167 offer security features intended to prevent unauthorized users from reading the
contents of the Flash Memory (FM) array. The Flash security consists of several hardware interlocks that
block the means by which an unauthorized user could gain access to the Flash array.
However, part of the security must lie with the user’s code. An extreme example would be user’s code that
dumps the contents of the internal program, as this code would defeat the purpose of security. At the same
time, the user may also wish to put a “backdoor” in his program. As an example, the user downloads a
security key through the SCI, allowing access to a programming routine that updates parameters stored in
another section of the Flash.
7.1 Operation with Security Enabled
Once the user has programmed the Flash with his application code, the device can be secured by
programming the security bytes located in the FM configuration field, which occupies a portion of the FM
array. These non-volatile bytes will keep the part secured through reset and through power-down of the
device. Only two bytes within this field are used to enable or disable security. Refer to the Flash Memory
section in the 56F8300 Peripheral User Manual for the state of the security bytes and the resulting state
of security. When Flash security mode is enabled in accordance with the method described in the Flash
Memory module specification, the device will disable external P-space accesses restricting code execution
to internal memory, disable EXTBOOT=1 mode, and disable the core EOnCE debug capabilities. Normal
program execution is otherwise unaffected.
7.2 Flash Access Blocking Mechanisms
The 56F8367/56F8167 have several operating functional and test modes. Effective Flash security must
address operating mode selection and anticipate modes in which the on-chip Flash can be compromised
and read without explicit user permission. Methods to block these are outlined in the next subsections.
7.2.1
Forced Operating Mode Selection
At boot time, the SIM determines in which functional modes the device will operate. These are:
•
•
•
Internal Boot Mode
External Boot Mode
Secure Mode
When Flash security is enabled as described in the Flash Memory module specification, the device will
boot in internal boot mode, disable all access to external P-space, and start executing code from the Boot
Flash at address 0x02_0000.
This security affords protection only to applications in which the device operates in internal Flash security
mode. Therefore, the security feature cannot be used unless all executing code resides on-chip.
When security is enabled, any attempt to override the default internal operating mode by asserting the
EXTBOOT pin in conjunction with reset will be ignored.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
129
7.2.2
Disabling EOnCE Access
On-chip Flash can be read by issuing commands across the EOnCE port, which is the debug interface for
the 56800E core. The TRST, TCLK, TMS, TDO, and TDI pins comprise a JTAG interface onto which the
EOnCE port functionality is mapped. When the device boots, the chip-level JTAG TAP (Test Access Port)
is active and provides the chip’s boundary scan capability and access to the ID register.
Proper implementation of Flash security requires that no access to the EOnCE port is provided when
security is enabled. The 56800E core has an input which disables reading of internal memory via the
JTAG/EOnCE. The FM sets this input at reset to a value determined by the contents of the FM security
bytes.
7.2.3
Flash Lockout Recovery
If a user inadvertently enables Flash security on the device, a built-in lockout recovery mechanism can be
used to reenable access to the device. This mechanism completely reases all on-chip Flash, thus disabling
Flash security. Access to this recovery mechanism is built into CodeWarrior via an instruction in memory
configuration (.cfg) files. Add, or uncomment the following configuration command:
unlock_flash_on_connect 1
For more information, please see CodeWarrior MC56F83xx/DSP5685x Family Targeting Manual.
The LOCKOUT_RECOVERY instruction has an associated 7-bit Data Register (DR) that is used to
control the clock divider circuit within the FM module. This divider, FM_CLKDIV[6:0], is used to control
the period of the clock used for timed events in the FM erase algorithm. This register must be set with
appropriate values before the lockout sequence can begin. Refer to the JTAG section of the 56F8300
Peripheral User Manual for more details on setting this register value.
The value of the JTAG FM_CLKDIV[6:0] will replace the value of the FM register FMCLKD that divides
down the system clock for timed events, as illustrated in Figure 7-1. FM_CLKDIV[6] will map to the
PRDIV8 bit, and FM_CLKDIV[5:0] will map to the DIV[5:0] bits. The combination of PRDIV8 and DIV
must divide the FM input clock down to a frequency of 150kHz-200kHz. The “Writing the FMCLKD
Register” section in the Flash Memory chapter of the 56F8300 Peripheral User Manual gives specific
equations for calculating the correct values.
56F8367 Technical Data, Rev. 3.0
130
Freescale Semiconductor
Preliminary
Flash Access Blocking Mechanisms
Flash Memory
SYS_CLK
2
input
clock
DIVIDER
7
FMCLKD
7
7
FM_CLKDIV
FM_ERASE
JTAG
Figure 7-1 JTAG to FM Connection for Lockout Recovery
Two examples of FM_CLKDIV calculations follow.
EXAMPLE 1: If the system clock is the 8MHz crystal frequency because the PLL has not been set up,
the input clock will be below 12.8MHz, so PRDIV8 = FM_CLKDIV[6] = 0. Using the following equation
yields a DIV value of 19 for a clock of 200kHz, and a DIV value of 20 for a clock of 190kHz. This
translates into an FM_CLKDIV[6:0] value of $13 or $14, respectively.
SYS_CLK
( )
(2)
150[kHz]
200[kHz]
<
<
(DIV + 1)
EXAMPLE 2: In this example, the system clock has been set up with a value of 32MHz, making the FM
input clock 16MHz. Because that is greater than 12.8MHz, PRDIV8 = FM_CLKDIV[6] = 1. Using the
following equation yields a DIV value of 9 for a clock of 200kHz, and a DIV value of 10 for a clock of
181kHz. This translates to an FM_CLKDIV[6:0] value of $49 or $4A, respectively.
SYS_CLK
( )
(2)(8)
150[kHz]
200[kHz]
<
<
(DIV + 1)
Once the LOCKOUT_RECOVERY instruction has been shifted into the instruction register, the clock
divider value must be shifted into the corresponding 7-bit data register. After the data register has been
updated, the user must transition the TAP controller into the RUN-TEST/IDLE state for the lockout
sequence to commence. The controller must remain in this state until the erase sequence has completed.
For details, see the JTAG Section in the 56F8300 Peripheral User Manual.
Note:
Once the lockout recovery sequence has completed, the user must reset both the JTAG TAP controller
(by asserting TRST) and the device (by asserting external chip reset) to return to normal unsecured
operation.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
131
7.2.4
Product Analysis
The recommended method of unsecuring a programmed device for product analysis of field failures is via
the backdoor key access. The customer would need to supply Technical Support with the backdoor key
and the protocol to access the backdoor routine in the Flash. Additionally, the KEYEN bit that allows
backdoor key access must be set.
An alternative method for performing analysis on a secured microcontroller would be to mass-erase and
reprogram the Flash with the original code, but modify the security bytes.
To insure that a customer does not inadvertently lock himself out of the device during programming, it is
recommended that he program the backdoor access key first, his application code second, and the security
bytes within the FM configuration field last.
Part 8 General Purpose Input/Output (GPIO)
8.1 Introduction
This section is intended to supplement the GPIO information found in the 56F8300 Peripheral User
Manual and contains only chip-specific information. This information supercedes the generic information
in the 56F8300 Peripheral User Manual.
8.2 Memory Maps
The width of the GPIO port defines how many bits are implemented in each of the GPIO registers. Based
on this and the default function of each of the GPIO pins, the reset values of the GPIOx_PUR and
GPIOx_PER registers will change from port to port. Table 8-3 defines the actual reset values of these
registers.
8.3 Configuration
There are six GPIO ports defined on the 56F8367/56F8167. The width of each port and the associated
peripheral function is shown in Table 8-1 and Table 8-2. The specific mapping of GPIO port pins is
shown in Table 8-3.
Table 8-1 56F8367 GPIO Ports Configuration
Available
Pins in
56F8367
GPIO
Port
Port
Width
Peripheral Function
Reset Function
A
B
C
14
8
14
8
14 pins - EMI Address pins
EMI Address
EMI Address
8 pins - EMI Address pins
11
11
4 pins -DEC1 / TMRB / SPI1
4 pins -DEC0 / TMRA
DEC1 / TMRB
DEC0 / TMRA
3 pins -PWMA current sense
PWMA current sense
56F8367 Technical Data, Rev. 3.0
132
Freescale Semiconductor
Preliminary
Configuration
Table 8-1 56F8367 GPIO Ports Configuration (Continued)
Available
Pins in
56F8367
GPIO
Port
Port
Width
Peripheral Function
Reset Function
D
13
14
13
14
6 pins - EMI CSn
2 pins - SCI1
2 pins - EMI CSn
EMI Chip Selects
SCI1
EMI Chip Selects
PWMB current sense
3 pins -PWMB current sense
E
SCI0
2 pins - SCI0
EMI Address
SPI0
2 pins - EMI Address pins
4 pins - SPI0
TMRC
2 pins - TMRC
TMRD
4 pins - TMRD
F
16
16
16 pins - EMI Data
EMI Data
Table 8-2 56F8167 GPIO Ports Configuration
Available
Pins in
56F8167
GPIO
Port
Port
Width
Peripheral Function
Reset Function
14 pins - EMI Address pins
A
B
C
14
8
14
8
EMI Address
EMI Address
8 pins - EMI Address pins
4 pins - SPI1
11
11
SPI1
4 pins - DEC0 / TMRA
3 pins - Dedicated GPIO
DEC0 / TMRA
GPIO
6 pins - EMI CSn
2 pins - SCI1
2 pins - EMI CSn
3 pins -PWMB current sense
D
E
13
14
13
14
EMI Chip Selects
SCI1
EMI Chip Selects
PWMB current sense
SCI0
2 pins - SCI0
EMI Address
SPI0
2 pins - EMI Address pins
4 pins - SPI0
TMRC
GPIO
2 pins - TMRC
4 pins - Dedicated GPIO
16 pins - EMI Data
F
16
16
EMI Data
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
133
Table 8-3 GPIO External Signals Map
Pins in italics are NOT available in the 56F8167 device
Reset
Function
Functional Signal
Package Pin
GPIO Port
GPIO Bit
0
1
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
A8
A9
19
20
21
22
23
24
25
26
154
10
11
12
13
14
33
2
A10
A11
A12
A13
A14
A15
A0
3
4
5
6
GPIOA
7
8
9
A1
10
11
12
13
0
A2
A3
A4
A5
GPIO1
GPIO1
GPIO1
A16
1
2
3
A17
A18
A19
34
35
36
GPIO1
GPIO
GPIO
GPIO
GPIO
GPIOB
4
5
6
7
A20 / Prescaler_clock
A21 / SYS_CLK
37
46
47
48
A22 / SYS_CLK2
A23 / Oscillator_Clock
1This is a function of the EMI_MODE, EXTBOOT, and Flash security settings at reset.
56F8367 Technical Data, Rev. 3.0
134
Freescale Semiconductor
Preliminary
Configuration
Table 8-3 GPIO External Signals Map (Continued)
Pins in italics are NOT available in the 56F8167 device
Reset
GPIO Port
GPIO Bit
Functional Signal
Package Pin
Function
Peripheral
Peripheral
Peripheral
Peripheral
PhaseA1 / TB0 / SCLK11
PhaseB1 / TB1 / MOSI11
Index1 / TB2 / MISO11
0
1
2
3
6
7
8
9
Home1 / TB3 / SSI11
PHASEA0 / TA0
PHASEB0 / TA1
Index0 / TA2
Home0 / TA3
ISA0
4
5
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
GPIO
155
156
157
158
126
127
128
55
GPIOC
6
7
8
9
ISA1
10
0
ISA2
CS2 / CAN2_TX
CS3 / CAN2_RX
CS4
1
GPIO
56
2
GPIO
57
3
GPIO
CS5
58
4
GPIO
CS6
59
5
GPIO
CS7
60
GPIOD
6
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
TXD1
49
7
RXD1
50
8
PS / CS0
DS / CS1
ISB0
53
9
54
10
11
12
61
ISB1
63
ISB2
64
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
135
Table 8-3 GPIO External Signals Map (Continued)
Pins in italics are NOT available in the 56F8167 device
Reset
Function
GPIO Port
GPIO Bit
Functional Signal
Package Pin
0
1
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
TXD0
RXD0
A6
4
5
2
17
3
A7
18
4
SCLK0
MOSI0
MISO0
SS0
TC0
TC1
TD0
TD1
TD2
TD3
D7
146
148
147
145
133
135
129
130
131
132
28
5
6
GPIOE
7
8
9
10
11
12
13
0
1
D8
29
2
D9
30
3
D10
D11
D12
D13
D14
D15
D0
32
4
149
150
151
152
153
70
5
6
7
GPIOF
8
9
10
11
12
13
14
15
D1
71
D2
83
D3
86
D4
88
D5
89
D6
90
1. See Part 6.5.8 to determine how to select peripherals from this set
56F8367 Technical Data, Rev. 3.0
136
Freescale Semiconductor
Preliminary
56F8367 Information
Part 9 Joint Test Action Group (JTAG)
9.1 56F8367 Information
Please contact your Freescale marketing representative or authorized distributor for
device/package-specific BSDL information.
Part 10 Specifications
10.1 General Characteristics
The 56F8367/56F8167 are fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital
inputs. The term “5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process
technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture
of devices designed for 3.3V and 5V power supplies. In such sytems, a bus may carry both 3.3V- and
5V-compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V
± 10% during normal operation without causing damage). This 5V-tolerant capability therefore offers the
power savings of 3.3V I/O levels combined with the ability to receive 5V levels without damage.
Absolute maximum ratings in Table 10-1 are stress ratings only, and functional operation at the maximum
is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to
the device.
Note: All specifications meet both Automotive and Industrial requirements unless individual
specifications are listed.
Note: The 56F8167 device is guaranteed to 40HMz and specified to meet Industrial requirements only.
CAUTION
This device contains protective circuitry to guard
against damage due to high static voltage or electrical
fields. However, normal precautions are advised to
avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit.
Reliability of operation is enhanced if unused inputs are
tied to an appropriate voltage level.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
137
Note: The 56F8167 device is specified to meet Industrial requirements only; CAN is NOT available on the
56F8167 device.
Table 10-1 Absolute Maximum Ratings
(VSS = VSSA_ADC = 0)
Characteristic
Supply Voltage
Symbol
Notes
Min
-0.3
-0.3
Max
4.0
Unit
V
VDD_IO
VDDA_ADC,
VREFH
VREFH must be less than or
equal to VDDA_ADC
4.0
V
ADC Supply Voltage
VDDA_OSC_PLL
VDD_CORE
VIN
-0.3
-0.3
-0.3
-0.3
-0.3
4.0
3.0
6.0
4.0
V
V
V
V
V
Oscillator / PLL Supply Voltage
Internal Logic Core Supply Voltage
Input Voltage (digital)
OCR_DIS is High
Pin Groups 1, 2, 5, 6, 9, 10
Pin Groups 11, 12, 13
VINA
Input Voltage (analog)
Pin Groups 1, 2, 3, 5, 6, 7, 8
VOUT
4.0
6.01
Output Voltage
Pin Group 4
VOD
TA
-0.3
-40
-40
-40
-40
-55
-55
6.0
125
105
150
125
150
150
V
Output Voltage (open drain)
°C
°C
°C
°C
°C
°C
Ambient Temperature (Automotive)
Ambient Temperature (Industrial)
Junction Temperature (Automotive)
Junction Temperature (Industrial)
TA
TJ
TJ
TSTG
TSTG
Storage Temperature (Automotive)
Storage Temperature (Industrial)
1. If corresponding GPIO pin is configured as open drain.
Note: Pins in italics are NOT available in the 56F8167 device.
Pin Group 1: TXD0-1, RXD0-1, SS0, MISO0, MOSI0
Pin Group 2: PHASEA0, PHASEA1, PHASEB0, PHASEB1, INDEX0, INDEX1, HOME0, HOME1, ISB0-2, ISA0-2, TD2-3, TC0-1, SCLK0
Pin Group 3: RSTO, TDO
Pin Group 4: CAN_TX
Pin Group 5: A0-5, D0-15, GPIOD0-5, PS, DS
Pin Group 6: A6-15, GPIOB0-7, TD0-1
Pin Group 7: CLKO, WR, RD
Pin Group 8: PWMA0-5, PWMB0-5
Pin Group 9: IRQA, IRQB, RESET, EXTBOOT, TRST, TMS, TDI, CAN_RX, EMI_MODE, FAULTA0-3, FAULTB0-3
Pin Group 10: TCK
Pin Group 11: XTAL, EXTAL
Pin Group 12: ANA0-7, ANB0-7
Pin Group 13: OCR_DIS, CLKMODE
56F8367 Technical Data, Rev. 3.0
138
Freescale Semiconductor
Preliminary
General Characteristics
Table 10-2 56F8367/56F8167 ElectroStatic Discharge (ESD) Protection
Characteristic
Min
2000
200
Typ
—
Max
—
Unit
V
ESD for Human Body Model (HBM)
ESD for Machine Model (MM)
—
—
V
500
—
—
V
ESD for Charge Device Model (CDM)
6
Table 10-3 Thermal Characteristics
Value
Value
Characteristic
Comments
Symbol
Unit
Notes
160-pin LQFP
160MAPBGA
Junction to ambient
RθJA
38.5
39.90
°C/W
2
Natural convection
RθJMA
Junction to ambient (@1m/sec)
35.4
33
46.8
TBD
°C/W
°C/W
2
RθJMA
(2s2p)
Junction to ambient
Natural convection
Four layer board (2s2p)
Four layer board (2s2p)
1, 2
RθJMA
(2s2p)
Junction to ambient (@1m/sec)
31.5
TBD
°C/W
1, 2
RθJC
ΨJT
Junction to case
8.6
0.8
TBD
TBD
°C/W
°C/W
W
3
Junction to center of case
I/O pin power dissipation
Power dissipation
4, 5
P I/O
P D
User-determined
P D = (IDD x VDD + P I/O
(TJ - TA) / R
JA7
)
W
PDMAX
Maximum allowed PD
W
θ
1. Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application. Determined on 2s2p ther-
mal test board.
2. Junction to ambient thermal resistance, Theta-JA (RθJA) was simulated to be equivalent to the JEDEC specification JESD51-2
in a horizontal configuration in natural convection. Theta-JA was also simulated on a thermal test board with two internal planes
(2s2p, where “s” is the number of signal layers and “p” is the number of planes) per JESD51-6 and JESD51-7. The correct name
for Theta-JA for forced convection or with the non-single layer boards is Theta-JMA.
3. Junction to case thermal resistance, Theta-JC (RθJC ), was simulated to be equivalent to the measured values using the cold
plate technique with the cold plate temperature used as the "case" temperature. The basic cold plate measurement technique is
described by MIL-STD 883D, Method 1012.1. This is the correct thermal metric to use to calculate thermal performance when
the package is being used with a heat sink.
4. Thermal Characterization Parameter, Psi-JT (ΨJT ), is the "resistance" from junction to reference point thermocouple on top cen-
ter of case as defined in JESD51-2. ΨJT is a useful value to use to estimate junction temperature in steady-state customer en-
vironments.
5. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature,
ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
6. See Part 12.1 for more details on thermal design considerations.
7. TJ = Junction temperature
TA = Ambient temperature
TBD = numbers will be available late Q4 2005
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
139
Note: The 56F8167 device is guaranteed to 40HMz and specified to meet Industrial requirements only;
CAN is NOT available on the 56F8167 device.
Table 10-4 Recommended Operating Conditions
(VREFLO = 0V, VSS = VSSA_ADC = 0V, VDDA = VDDA_ADC = VDDA_OSC_PLL
)
Characteristic
Supply voltage
Symbol
Notes
Min
3
Typ
3.3
3.3
Max
3.6
Unit
V
VDD_IO
V
VDDA_ADC,
VREFH
VREFH must be less than or
3
3.6
ADC Supply Voltage
equal to V
DDA_ADC
V
V
VDDA_OSC
3
3.3
2.5
3.6
Oscillator / PLL Supply Voltage
_PLL
OCR_DIS is High
VDD_CORE
2.25
2.75
Internal Logic Core Supply
Voltage
MHz
V
FSYSCLK
VIH
0
—
—
—
—
60
Device Clock Frequency
Input High Voltage (digital)
Input High Voltage (analog)
Pin Groups 1, 2, 5, 6, 9, 10
Pin Group 13
2
2
5.5
V
VIHA
VDDA+0.3
VDDA+0.3
Pin Group 11
V
VIHC
VDDA-0.8
Input High Voltage (XTAL/EXTAL,
XTAL is not driven by an external
clock)
Pin Group 11
V
VIHC
2
—
—
VDDA+0.3
0.8
Input high voltage (XTAL/EXTAL,
XTAL is driven by an external clock)
Pin Groups
1, 2, 5, 6, 9, 10, 11, 13
V
VIL
-0.3
Input Low Voltage
Pin Groups 1, 2, 3
Pin Groups 5, 6, 7
Pin Group 8
mA
IOH
—
—
—
—
—
—
-40
—
—
—
—
—
—
—
-4
-8
-12
4
Output High Source Current
VOH = 2.4V (VOH min.)
Pin Groups 1, 2, 3, 4
Pin Groups 5, 6, 7
Pin Group 8
mA
IOL
Output Low Sink Current
VOL = 0.4V (VOL max)
8
12
°C
°C
TA
TA
Ambient Operating Temperature
(Automotive)
125 = 150
-
(R X P )
θJA
D
-40
—
Ambient Operating Temperature
(Industrial)
105 = 125
-
(R X P )
θJA
D
T
T
= -40°C to 125°C
= -40°C to 105°C
Cycles
Cycles
Years
NF
NF
TR
1000
1000
15
—
—
—
—
Flash Endurance (Automotive)
(Program Erase Cycles)
A
A
—
—
Flash Endurance (Industrial)
(Program Erase Cycles)
T <= 85°C avg
Flash Data Retention
J
Note: Total chip source or sink current cannot exceed 200mA
See Pin Groups in Table 10-1.
56F8367 Technical Data, Rev. 3.0
140
Freescale Semiconductor
Preliminary
DC Electrical Characteristics
10.2 DC Electrical Characteristics
Note: The 56F8167 device is specified to meet Industrial requirements only; CAN is NOT available on the
56F8167 device.
Table 10-5 DC Electrical Characteristics
At Recommended Operating Conditions;see Table 10-4
Test
Conditions
Characteristic
Symbol
Notes
Min
Typ
Max
Unit
V
V
I
= I
VOH
VOL
IIH
2.4
—
—
—
0
—
0.4
Output High Voltage
Output Low Voltage
OH
OHmax
OLmax
I
= I
OL
Pin Groups 1, 2, 5, 6, 9
Pin Group 10
µA
V
V
= 3.0V to 5.5V
= 3.0V to 5.5V
—
+/- 2.5
Digital Input Current High
pull-up enabled or disabled
IN
µA
IIH
40
80
160
Digital Input Current High
with pull-down
IN
Pin Group 13
Pin Group 12
µA
µA
µA
V
= V
= V
IIHA
IIHADC
IIL
—
—
0
0
+/- 2.5
+/- 10
-500
Analog Input Current High
ADC Input Current High
IN
IN
DDA
DDA
V
Pin Groups 1, 2, 5, 6, 9
V
V
V
= 0V
-200
-100
Digital Input Current Low
pull-up enabled
IN
IN
IN
Pin Groups 1, 2, 5, 6, 9
Pin Group 10
µA
µA
= 0V
= 0V
IIL
—
—
0
0
+/- 2.5
+/- 2.5
Digital Input Current Low
pull-up disabled
IIL
Digital Input Current Low
with pull-down
Pin Group 13
Pin Group 12
µA
µA
µA
V
V
= 0V
= 0V
IILA
—
—
—
0
0
0
+/- 2.5
+/- 10
+/- 2.5
Analog Input Current Low
ADC Input Current Low
IN
IN
IILADC
IEXTAL
V
= V
or 0V
DDA
EXTAL Input Current Low
clock input
IN
CLKMODE = High
CLKMODE = Low
µA
µA
µA
V
V
= V
= V
or 0V
or 0V
IXTAL
—
—
—
0
—
0
+/- 2.5
200
XTAL Input Current Low
clock input
IN
IN
DDA
DDA
Pin Groups
1, 2, 3, 4, 5, 6, 7, 8,14
V
= 3.0V to
OUT
IOZ
VHYS
CINC
+/- 2.5
Output Current
High Impedance State
5.5V or 0V
Pin Groups
2, 6, 9, 10
V
—
—
—
0.3
4.5
5.5
—
—
—
—
Schmitt Trigger Input
Hysteresis
pF
pF
—
—
Input Capacitance
(EXTAL/XTAL)
COUTC
Output Capacitance
(EXTAL/XTAL)
pF
pF
CIN
—
—
6
6
—
—
—
—
Input Capacitance
Output Capacitance
COUT
See Pin Groups in Table 10-1.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
141
Table 10-6 Power-On Reset Low Voltage Parameters
Characteristic
POR Trip Point
Symbol
Min
1.75
—
Typ
1.8
Max
1.9
—
Units
V
V
POR
VEI2.5
VEI3.3
LVI, 2.5 volt Supply, trip point1
2.14
LVI, 3.3 volt supply, trip point2
Bias Current
—
—
2.7
—
V
I bias
110
130
µA
1. When VDD_CORE drops below VEI2.5, an interrupt is generated.
2. When VDD_CORE drops below VEI3.3, an interrupt is generated.
Table 10-7 Current Consumption per Power Supply Pin (Typical)
On-Chip Regulator Enabled (OCR_DIS = Low)
1
IDD_ADC
IDD_OSC_PLL
Mode
Test Conditions
• 60MHz Device Clock
IDD_IO
RUN1_MAC
155mA
50mA
2.5mA
• All peripheral clocks are enabled
• All peripherals running
• Continuous MAC instructions with fetches from
Data RAM
• ADC powered on and clocked
• 60MHz Device Clock
Wait3
Stop1
91mA
6mA
70µA
0µA
2.5mA
• All peripheral clocks are enabled
• ADC powered off
• 8MHz Device Clock
• All peripheral clocks are off
• ADC powered off
165µA
• PLL powered off
• External Clock is off
• All peripheral clocks are off
• ADC powered off
Stop2
5.1mA
0µA
155µA
• PLL powered off
1. No Output Switching
2. Includes Processor Core current supplied by internal voltage regulator
56F8367 Technical Data, Rev. 3.0
142
Freescale Semiconductor
Preliminary
DC Electrical Characteristics
Table 10-8 Current Consumption per Power Supply Pin (Typical)
On-Chip Regulator Disabled (OCR_DIS = High)
1
IDD_Core
IDD_ADC
IDD_OSC_PLL
Mode
Test Conditions
• 60MHz Device Clock
IDD_IO
RUN1_MAC
150mA
13µA
50mA
2.5mA
• All peripheral clocks are enabled
• All peripherals running
• Continuous MAC instructions with
fetches from Data RAM
• ADC powered on and clocked
• 60MHz Device Clock
Wait3
Stop1
86mA
13µA
13µA
70µA
0µA
2.5mA
• All peripheral clocks are enabled
• ADC powered off
• 8MHz Device Clock
• All peripheral clocks are off
• ADC powered off
950µA
165µA
• PLL powered off
• External Clock is off
• All peripheral clocks are off
• ADC powered off
Stop2
100µA
13µA
0µA
155µA
• PLL powered off
1. No Output Switching
Table 10-9. Regulator Parameters
Characteristic
Symbol
Min
Typical
Max
Unit
Unloaded Output Voltage
(0mA Load)
VRNL
2.25
—
2.75
V
Loaded Output Voltage
(200 mA load)
VRL
VR
2.25
2.25
—
—
2.75
2.75
V
V
Line Regulation @ 250 mA load
(VDD33 ranges from 3.0 to 3.6)
Short Circuit Current
Iss
—
—
700
mA
( output shorted to ground)
Bias Current
I bias
Ipd
—
—
—
5.8
0
7
2
mA
µA
Power-down Current
Short-Circuit Tolerance
TRSC
—
30
minutes
(output shorted to ground)
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
143
Table 10-10. PLL Parameters
Characteristics
PLL Start-up time
Symbol
TPS
Min
0.3
0.1
120
—
Typical
0.5
Max
10
Unit
ms
ms
ps
Resonator Start-up time
Min-Max Period Variation
Peak-to-Peak Jitter
TRS
0.18
—
1
TPV
200
175
2
TPJ
—
ps
Bias Current
IBIAS
IPD
—
1.5
mA
µA
Quiescent Current, power-down mode
—
100
150
10.2.1 Temperature Sense
Note: Temperature Sensor is NOT available in the 56F8167 device.
Table 10-11 Temperature Sense Parametrics
Characteristics
Slope (Gain)1
Symbol
m
Min
—
Typical
7.762
26
Max
—
Unit
mV/°C
°C
Room Trim Temp. 1, 2
TRT
24
28
Hot Trim Temp. (Industrial)1,2
Hot Trim Temp. (Automotive)1,2
THT
122
147
—
125
128
153
—
°C
THT
150
°C
Output Voltage @
VDDA_ADC = 3.3V, TJ =0°C1
VTS0
1.370
V
Supply Voltage
VDDA_ADC
IDD-OFF
IDD-ON
3.0
—
3.3
—
—
0
3.6
10
V
Supply Current - OFF
Supply Current - ON
µA
µA
°C
—
250
6.7
Accuracy3,1 from -40°C to 150°C
Using VTS = mT + VTS0
TACC
-6.7
Resolution4, 5,1
RES
—
0.104
—
°C / bit
1. Includes the ADC conversion of the analog Temperature Sense voltage.
2. The ADC is not calibrated for the conversion of the Temperature Sensor trim value stored in the Flash Memory at
FMOPT0 and FMOPT1.
3. See Application Note, AN1980, for methods to increase accuracy.
4. Assuming a 12-bit range from 0V to 3.3V.
(V
=
- V
) X 1
m
5. Typical resolution calculated using equation, R
REFH
12
REFLO
ES
2
56F8367 Technical Data, Rev. 3.0
144
Freescale Semiconductor
Preliminary
AC Electrical Characteristics
10.3 AC Electrical Characteristics
Tests are conducted using the input levels specified in Table 10-5. Unless otherwise specified,
propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured
between the 10% and 90% points, as shown in Figure 10-1.
Low
VIL
High
VIH
90%
50%
10%
Input Signal
Midpoint1
Fall Time
Note: The midpoint is VIL + (VIH – VIL)/2.
Rise Time
Figure 10-1 Input Signal Measurement References
Figure 10-2 shows the definitions of the following signal states:
•
•
•
Active state, when a bus or signal is driven, and enters a low impedance state
Tri-stated, when a bus or signal is placed in a high impedance state
Data Valid state, when a signal level has reached V or V
OL
OH
•
Data Invalid state, when a signal level is in transition between V and V
OL OH
Data2 Valid
Data2
Data1 Valid
Data1
Data3 Valid
Data3
Data
Tri-stated
Data Invalid State
Data Active
Data Active
Figure 10-2 Signal States
10.4 Flash Memory Characteristics
Table 10-12 Flash Timing Parameters
Characteristic
Symbol
prog
erase
me
Min
Typ
Max
Unit
µs
20
—
—
Program time1
T
20
—
—
—
—
Erase time2
ms
ms
T
100
Mass erase time
T
1. There is additional overhead which is part of the programming sequence. See the 56F8300 Peripheral User Manual
for details. Program time is per 16-bit word in Flash memory. Two words at a time can be programmed within the Pro-
gram Flash Module, as it contains two interleaved memories.
2. Specifies page erase time. There are 512 bytes per page in the Data and Boot Flash memories. The Program Flash
Module uses two interleaved Flash memories, increasing the effective page size to 1024 bytes.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
145
10.5 External Clock Operation Timing
1
Table 10-13 External Clock Operation Timing Requirements
Characteristic
Symbol
fosc
Min
Typ
Max
Unit
Frequency of operation (external clock driver)2
Clock Pulse Width3
0
—
—
—
—
120
—
MHz
ns
tPW
3.0
—
—
External clock input rise time4
trise
10
ns
External clock input fall time5
tfall
10
ns
1. Parameters listed are guaranteed by design.
2. See Figure 10-3 for details on using the recommended connection of an external clock driver.
3. The high or low pulse width must be no smaller than 8.0ns or the chip will not function.
4. External clock input rise time is measured from 10% to 90%.
5. External clock input fall time is measured from 90% to 10%.
VIH
External
Clock
90%
50%
10%
90%
50%
10%
VIL
tfall
trise
tPW
tPW
Note: The midpoint is VIL + (VIH – VIL)/2.
Figure 10-3 External Clock Timing
10.6 Phase Locked Loop Timing
Table 10-14 PLL Timing
Characteristic
Symbol
fosc
Min
4
Typ
8
Max
8
Unit
MHz
MHz
External reference crystal frequency for the PLL1
PLL output frequency2 (fOUT
)
fop
160
—
260
PLL stabilization time3 -40° to +125°C
tplls
—
1
10
ms
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
correctly. The PLL is optimized for 8MHz input crystal.
2. ZCLK may not exceed 60MHz. For additional information on ZCLK and (fOUT/2), please refer to the OCCS chapter in
the 56F8300 Peripheral User Manual.
3. This is the minimum time required after the PLL set up is changed to ensure reliable operation.
56F8367 Technical Data, Rev. 3.0
146
Freescale Semiconductor
Preliminary
Crystal Oscillator Timing
10.7 Crystal Oscillator Timing
Table 10-15 Crystal Oscillator Parameters
Characteristic
Crystal Start-up time
Symbol
TCS
Min
4
Typ
5
Max
10
Unit
ms
ms
ohms
ps
Resonator Start-up time
TRS
0.1
—
0.18
—
1
Crystal ESR
RESR
TD
120
250
1.5
300
300
290
110
1
Crystal Peak-to-Peak Jitter
Crystal Min-Max Period Variation
Resonator Peak-to-Peak Jitter
Resonator Min-Max Period Variation
Bias Current, high-drive mode
Bias Current, low-drive mode
Quiescent Current, power-down mode
70
0.12
—
—
TPV
—
ns
TRJ
—
ps
TRP
—
—
ps
IBIASH
IBIASL
IPD
—
250
80
0
µA
—
µA
—
µA
10.8 External Memory Interface Timing
The External Memory Interface is designed to access static memory and peripheral devices. Figure 10-4
shows sample timing and parameters that are detailed in Table 10-16.
The timing of each parameter consists of both a fixed delay portion and a clock related portion, as well as
user controlled wait states. The equation:
t = D + P * (M + W)
should be used to determine the actual time of each parameter. The terms in this equation are defined as:
t
= Parameter delay time
D
P
= Fixed portion of the delay, due to on-chip path delays
= Period of the system clock, which determines the execution rate of the part
(i.e., when the device is operating at 60MHz, P = 16.67 ns)
M
W
= Fixed portion of a clock period inherent in the design; this number is adjusted to account
for possible derating of clock duty cycle
= Sum of the applicable wait state controls. The “Wait State Controls” column of
Table 10-16 shows the applicable controls for each parameter and the EMI chapter of
the 56F8300 Peripheral User Manual details what each wait state field controls.
When using the XTAL clock input directly as the chip clock without prescaling (ZSRC selects prescaler
clock and prescaler set to 1), the EMI quadrature clock is generated using both edges of the EXTAL clock
÷
input. In this situation only, parameter values must be adjusted for the duty cycle at XTAL. DCAOE and
DCAEO are used to make this duty cycle adjustment where needed.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
147
DCAOE and DCAEO are calculated as follows:
DCAOE = 0.5 - MAX XTAL duty cycle, if ZSRC selects prescaler clock and the prescaler is set to
= 0.0 all other cases
÷
÷
1
1
DCAEO = MIN XTAL duty cycle - 0.5, if ZSRC selects prescaler clock and the prescaler is set to
= 0.0 all other cases
Example of DCAOE and DCAEO calculation:
Assuming prescaler is set for
÷ 1 and prescaler clock is selected by ZSRC, if XTAL duty cycle
ranges between 45% and 60% high;
DCAOE = .50 - .60 = - 0.1
DCAEO = .45 - .50 = - 0.05
The timing of write cycles is different when WWS = 0 than when WWS > 0. Therefore, some parameters
contain two sets of numbers to account for this difference. Use the “Wait States Configuration” column
of Table 10-16 to make the appropriate selection.
A0-Axx,CS
tRD
tARDD
tRDA
tRDRD
tARDA
RD
tWAC
tWRRD
tAWR
tWRWR
tWR
tRDWR
WR
tDWR
tDOH
tRDD
tDOS
Data Out
tAD
tDRD
Data In
D0-D15
Note: During read-modify-write instructions and internal instructions, the address lines do not change state.
Figure 10-4 External Memory Interface Timing
Note:
When multiple lines are given for the same wait state configuration, calculate each and then select the
smallest or most negative.
56F8367 Technical Data, Rev. 3.0
148
Freescale Semiconductor
Preliminary
External Memory Interface Timing
Table 10-16 External Memory Interface Timing
Wait States
Configuration
Wait States
Unit
Symbol
tAWR
D
M
Characteristic
Controls
WWS=0
WWS>0
WWS=0
WWS>0
WWS=0
WWS=0
WWS>0
WWS>0
-2.076
0.50
Address Valid to WR Asserted
WWSS
WWS
ns
ns
-1.795 0.75 + DCAOE
-0.094 0.25 + DCAOE
WR Width Asserted to WR
Deasserted
tWR
-0.012
0
-9.321 0.25 + DCAEO
Data Out Valid to WR Asserted
-1.160
-8.631
0.00
0.50
tDWR
WWSS
ns
-0.879 0.25 + DCAOE
-2.086 0.25 + DCAEO
-0.563 0.25 + DCAOE
Valid Data Out Hold Time after WR
Deasserted
tDOH
WWSH
ns
ns
Valid Data Out Set-Up Time to WR
Deasserted
tDOS
WWS,WWSS
-8.315
0.50
tWAC
tRDA
-3.432 0.25 + DCAEO
WWSH
RWSH
ns
ns
ns
Valid Address after WR Deasserted
RD Deasserted to Address Invalid
Address Valid to RD Deasserted
-1.780
-2.120
0.00
1.00
tARDD
RWSS,RWS
Valid Input Data Hold after RD
Deasserted
N/A1
tDRD
tRD
0.00
—
RWS
ns
ns
ns
ns
ns
ns
ns
0.279
1.00
1.00
RD Assertion Width
-15.723
Address Valid to Input Data Valid
tAD
RWSS,RWS
RWSS
-20.642 1.25 + DCAOE
tARDA
tRDD
tWRRD
tRDRD
-2.603
0.00
1.00
Address Valid to RD Asserted
-13.120
RD Asserted to Input Data Valid
RWSS,RWS
-18.039 1.25 + DCAOE
-2.135 0.25 + DCAEO
WWSH,RWSS
WR Deasserted to RD Asserted
RD Deasserted to RD Asserted
RWSS,RWSH
MDAR3, 4
-0.4832
0.00
WWS=0
WWS>0
WWS=0
WWS>0
-1.608 0.75 + DCAEO
WR Deasserted to WR Asserted
RD Deasserted to WR Asserted
tWRWR
WWSS, WWSH
ns
ns
-0.918
-0.096
1.00
0.50
RWSH, WWSS,
MDAR3
tRDWR
0.084 0.75 + DCAOE
1. N/A since device captures data before it deasserts RD
2. If RWSS = RWSH = 0, and the chip select does not change, then RD does not deassert during back-to-back reads.
3. Substitute BMDAR for MDAR if there is no chip select
4. MDAR is active in this calculation only when the chip select changes.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
149
10.9 Reset, Stop, Wait, Mode Select, and Interrupt Timing
1,2
Table 10-17 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Typical
Min
Typical
Max
Characteristic
Symbol
Unit
See Figure
10-5
RESET Assertion to Address, Data and Control
Signals High Impedance
tRAZ
—
21
ns
Minimum RESET Assertion Duration
tRA
16T
63T
—
ns
ns
10-5
10-5
RESET Deassertion to First External Address
Output3
tRDA
64T
Edge-sensitive Interrupt Request Width
tIRW
tIDM
1.5T
18T
14T
18T
14T
22T
18T
22T
18T
1.5T
—
—
—
—
—
—
—
—
—
—
ns
ns
10-6
10-7
IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction
execution in the interrupt service routine
tIDM - FAST
tIG
IRQA, IRQB Assertion to General Purpose
Output Valid, caused by first instruction
execution in the interrupt service routine
ns
ns
ns
ns
10-7
10-8
10-9
10-9
tIG - FAST
tIRI
Delay from IRQA Assertion (exiting Wait) to
External Data Memory Access4
tIRI -FAST
tIF
Delay from IRQA Assertion to External Data
Memory Access (exiting Stop)
tIF - FAST
tIW
IRQA Width Assertion to Recover from Stop
State5
1. In the formulas, T = clock cycle. For an operating frequency of 60MHz, T = 16.67ns. At 8MHz (used during Reset and
Stop modes), T = 125ns.
2. Parameters listed are guaranteed by design.
3. During Power-On Reset, it is possible to use the device’s internal reset stretching circuitry to extend this period to 221T.
4. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This
is not the minimum required so that the IRQA interrupt is accepted.
5. The interrupt instruction fetch is visible on the pins only in Mode 3.
56F8367 Technical Data, Rev. 3.0
150
Freescale Semiconductor
Preliminary
Reset, Stop, Wait, Mode Select, and Interrupt Timing
RESET
tRA
tRAZ
tRDA
A0–A15,
D0–D15
First Fetch
PS, DS,
RD, WR
First Fetch
Figure 10-5 Asynchronous Reset Timing
IRQA,
IRQB
tIRW
Figure 10-6 External Interrupt Timing (Negative Edge-Sensitive)
A0–A15,
PS
RD
,
,
DS
WR
,
First Interrupt Instruction Execution
tIDM
IRQA
,
IRQB
a) First Interrupt Instruction Execution
General
Purpose
I/O Pin
tIG
IRQA
,
IRQB
b) General Purpose I/O
Figure 10-7 External Level-Sensitive Interrupt Timing
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
151
IRQA,
IRQB
tIRI
A0–A15,
PS, DS,
RD, WR
First Interrupt Vector
Instruction Fetch
Figure 10-8 Interrupt from Wait State Timing
tIW
IRQA
tIF
A0–A15,
PS, DS,
RD, WR
First Instruction Fetch
Not IRQA Interrupt Vector
Figure 10-9 Recovery from Stop State Using Asynchronous Interrupt Timing
10.10 Serial Peripheral Interface (SPI) Timing
1
Table 10-18 SPI Timing
Characteristic
Symbol
Min
Max
Unit
See Figure
Cycle time
Master
Slave
tC
10-10, 10-11,
10-12, 10-13
50
50
—
—
ns
ns
Enable lead time
Master
Slave
tELD
tELG
tCH
10-13
10-13
—
25
—
—
ns
ns
Enable lag time
Master
Slave
—
100
—
—
ns
ns
Clock (SCK) high time
Master
Slave
10-10, 10-11,
10-12, 10-13
17.6
25
—
—
ns
ns
Clock (SCK) low time
Master
Slave
tCL
10-13
24.1
25
—
—
ns
ns
56F8367 Technical Data, Rev. 3.0
152
Freescale Semiconductor
Preliminary
Serial Peripheral Interface (SPI) Timing
1
Table 10-18 SPI Timing (Continued)
Characteristic
Symbol
Min
Max
Unit
See Figure
Data set-up time required for inputs
Master
Slave
tDS
10-10, 10-11,
10-12, 10-13
20
0
—
—
ns
ns
Data hold time required for inputs
Master
Slave
tDH
10-10, 10-11,
10-12, 10-13
0
2
—
—
ns
ns
Access time (time to data active from
high-impedance state)
Slave
tA
10-13
10-13
4.8
3.7
15
ns
ns
Disable time (hold time to high-impedance state)
Slave
tD
15.2
Data Valid for outputs
Master
Slave (after enable edge)
tDV
10-10, 10-11,
10-12, 10-13
—
—
4.5
20.4
ns
ns
Data invalid
Master
Slave
tDI
tR
tF
10-10, 10-11,
0
0
—
—
ns
ns
10-12
Rise time
Master
Slave
10-10, 10-11,
10-12, 10-13
—
—
11.5
10.0
ns
ns
Fall time
Master
Slave
10-10, 10-11,
10-12, 10-13
—
—
9.7
9.0
ns
ns
1. Parameters listed are guaranteed by design.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
153
SS
(Input)
SS is held High on master
tC
tR
tF
tCL
SCLK (CPOL = 0)
(Output)
tCH
tF
tR
tCL
SCLK (CPOL = 1)
(Output)
tDH
tCH
tDS
MISO
MSB in
tDI
Bits 14–1
tDV
Bits 14–1
LSB in
tDI(ref)
(Input)
MOSI
(Output)
Master MSB out
tF
Master LSB out
tR
Figure 10-10 SPI Master Timing (CPHA = 0)
SS
(Input)
SS is held High on master
tC
tF
tR
tCL
SCLK (CPOL = 0)
(Output)
tCH
tF
tCL
SCLK (CPOL = 1)
(Output)
tCH
tDS
tR
tDH
MISO
MSB in
tDI
Bits 14–1
LSB in
tDI(ref)
(Input)
tDV(ref)
tDV
Bits 14– 1
MOSI
(Output)
Master MSB out
tF
Master LSB out
tR
Figure 10-11 SPI Master Timing (CPHA = 1)
56F8367 Technical Data, Rev. 3.0
154
Freescale Semiconductor
Preliminary
Serial Peripheral Interface (SPI) Timing
SS
(Input)
tC
tF
tELG
tCL
tR
SCLK (CPOL = 0)
(Input)
tCH
tELD
tCL
SCLK (CPOL = 1)
(Input)
tCH
tF
tA
tR
tD
MISO
(Output)
Slave MSB out
Bits 14–1
tDV
Slave LSB out
tDI
tDS
tDI
tDH
MOSI
(Input)
MSB in
Bits 14–1
LSB in
Figure 10-12 SPI Slave Timing (CPHA = 0)
SS
(Input)
tF
tC
tR
tCL
SCLK (CPOL = 0)
(Input)
tCH
tELG
tELD
tCL
SCLK (CPOL = 1)
(Input)
tDV
tCH
tR
tD
Slave LSB out
tDI
tA
tF
MISO
(Output)
Slave MSB out
Bits 14–1
tDV
tDS
tDH
MOSI
(Input)
MSB in
Bits 14–1
LSB in
Figure 10-13 SPI Slave Timing (CPHA = 1)
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
155
10.11 Quad Timer Timing
1, 2
Table 10-19 Timer Timing
Characteristic
Timer input period
Symbol
PIN
Min
Max
—
Unit
ns
See Figure
10-14
2T + 6
1T + 3
1T - 3
Timer input high / low period
Timer output period
PINHL
POUT
—
ns
10-14
—
ns
10-14
Timer output high / low period
POUTHL
0.5T - 3
—
ns
10-14
1. In the formulas listed, T = the clock cycle. For 60MHz operation, T = 16.67ns.
2. Parameters listed are guaranteed by design.
Timer Inputs
PINHL
PINHL
PIN
Timer Outputs
POUTHL
POUTHL
POUT
Figure 10-14 Timer Timing
10.12 Quadrature Decoder Timing
1, 2
Table 10-20 Quadrature Decoder Timing
Characteristic
Symbol
PIN
Min
Max
—
Unit
See Figure
10-15
Quadrature input period
4T + 12
2T + 6
1T + 3
ns
ns
ns
Quadrature input high / low period
Quadrature phase period
PHL
—
10-15
PPH
—
10-15
1. In the formulas listed, T = the clock cycle. For 60MHz operation, T=16.67ns.
2. Parameters listed are guaranteed by design.
56F8367 Technical Data, Rev. 3.0
156
Freescale Semiconductor
Preliminary
Serial Communication Interface (SCI) Timing
PPH PPH PPH PPH
Phase A
(Input)
PHL
PIN
PHL
Phase B
(Input)
PHL
PIN
PHL
Figure 10-15 Quadrature Decoder Timing
10.13 Serial Communication Interface (SCI) Timing
1
Table 10-21 SCI Timing
Characteristic
Baud Rate2
Symbol
BR
Min
Max
Unit
Mbps
ns
See Figure
(fMAX/16)
1.04/BR
1.04/BR
—
—
RXD3 Pulse Width
TXD4 Pulse Width
RXDPW
TXDPW
0.965/BR
0.965/BR
10-16
10-17
ns
1. Parameters listed are guaranteed by design.
2. fMAX is the frequency of operation of the system clock, ZCLK, in MHz, which is 60MHz for the 56F8367 device , and
40MHz for the 56F8167 device.
3. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.
4. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.
RXD
SCI receive
data pin
RXDPW
(Input)
Figure 10-16 RXD Pulse Width
TXD
SCI receive
data pin
TXDPW
(Input)
Figure 10-17 TXD Pulse Width
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
157
10.14 Controller Area Network (CAN) Timing
Note: CAN is not available in the 56F8167 device.
1
Table 10-22 CAN Timing
Characteristic
Baud Rate
Bus Wake Up detection
Symbol
BRCAN
Min
Max
1
Unit
Mbps
µs
See Figure
—
5
—
T WAKEUP
10-18
—
1. Parameters listed are guaranteed by design
CAN_RX
CAN receive
data pin
T WAKEUP
(Input)
Figure 10-18 Bus Wakeup Detection
10.15 JTAG Timing
Table 10-23 JTAG Timing
Characteristic
Symbol
fOP
Min
DC
DC
50
5
Max
Unit
See Figure
10-19
TCK frequency of operation using EOnCE1
SYS_CLK/8
MHz
MHz
ns
TCK frequency of operation not using EOnCE1
TCK clock pulse width
fOP
SYS_CLK/4
10-19
tPW
—
—
—
30
30
—
10-19
TMS, TDI data set-up time
TMS, TDI data hold time
TCK low to TDO data valid
TCK low to TDO tri-state
TRST assertion time
tDS
ns
10-20
tDH
5
ns
10-20
tDV
—
ns
10-20
tTS
—
ns
10-20
2T2
tTRST
ns
10-21
1. TCK frequency of operation must be less than 1/8 the processor rate.
2. T = processor clock period (nominally 1/60MHz)
56F8367 Technical Data, Rev. 3.0
158
Freescale Semiconductor
Preliminary
JTAG Timing
1/fOP
tPW
tPW
VIH
VM
VM
TCK
(Input)
VIL
VM = VIL + (VIH – VIL)/2
Figure 10-19 Test Clock Input Timing Diagram
TCK
(Input)
tDS
tDH
TDI
TMS
Input Data Valid
(Input)
tDV
TDO
(Output)
Output Data Valid
tTS
TDO
(Output
)
tDV
TDO
(Output)
Output Data Valid
Figure 10-20 Test Access Port Timing Diagram
TRST
(Input)
tTRST
Figure 10-21 TRST Timing Diagram
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
159
10.16 Analog-to-Digital Converter (ADC) Parameters
Table 10-24 ADC Parameters
Characteristic
Input voltages
Symbol
VADIN
RES
Min
VREFL
12
Typ
—
Max
VREFH
12
Unit
V
Resolution
—
Bits
Integral Non-Linearity1
LSB2
LSB2
INL
—
+/- 2.4
+/- 0.7
+/- 3.2
< +1
Differential Non-Linearity
DNL
—
Monotonicity
GUARANTEED
—
ADC internal clock
fADIC
RAD
0.5
VREFL
5
5
MHz
V
Conversion range
—
6
VREFH
16
tAIC cycles3
ms
ADC channel power-up time
tADPU
ADC reference circuit power-up time4
Conversion time
tVREF
tADC
—
—
—
6
25
—
tAIC cycles3
tAIC cycles3
Sample time
tADS
—
1
—
Input capacitance
CADI
IADI
—
—
—
—
—
—
—
—
—
—
—
5
—
3
pF
mA
mA
mA
mA
Input injection current5, per pin
Input injection current, total
—
IADIT
—
20
VREFH current
IVREFH
IADCA
IADCB
IADCQ
EGAIN
VOFFSET
AECAL
CF1
1.2
3
ADC A current
25
—
ADC B current
25
0
—
mA
µA
Quiescent current
10
Uncalibrated Gain Error (ideal = 1)
Uncalibrated Offset Voltage
.+/- .004
+/- 27
+/- .01
+/- 40
—
—
mV
LSBs
—
Calibrated Absolute Error6
See Figure 10-22
0.002289
Calibration Factor 17
—
Calibration Factor 2
CF2
—
—
—
—
-25.6
-60
—
—
—
—
dB
V
Crosstalk between channels
Common Mode Voltage
Vcommon
(VREFH - VREFLO) / 2
Signal-to-noise ratio
SNR
—
64.6
—
db
56F8367 Technical Data, Rev. 3.0
160
Freescale Semiconductor
Preliminary
Analog-to-Digital Converter (ADC) Parameters
Table 10-24 ADC Parameters (Continued)
Characteristic
Symbol
Min
Typ
Max
Unit
Signal-to-noise plus distortion ratio
Total Harmonic Distortion
SINAD
THD
—
—
—
—
59.1
60.6
61.1
9.6
—
—
—
—
db
db
Spurious Free Dynamic Range
SFDR
ENOB
db
Effective Number Of Bits8
Bits
1. INL measured from Vin = .1VREFH to Vin = .9VREFH
10% to 90% Input Signal Range
2. LSB = Least Significant Bit
3. ADC clock cycles
4. Assumes each voltage reference pin is bypassed with 0.1µF ceramic capacitors to ground
5. The current that can be injected or sourced from an unselected ADC signal input without impacting the performance of
the ADC. This allows the ADC to operate in noisy industrial environments where inductive flyback is possible.
6. Absolute error includes the effects of both gain error and offset error.
7. Please see the 56F8300Peripheral User’s Manual for additional information on ADC calibration.
8. ENOB = (SINAD - 1.76)/6.02
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
161
Figure 10-22 ADC Absolute Error Over Processing and Temperature Extremes Before
and After Calibration for VDC = 0.60V and 2.70V
in
Note: The absolute error data shown in the graphs above reflects the effects of both gain error and offset
error. The data was taken on 25 parts: three each from four processing corner lots as well as five from one
nominally processed lot, each at three temperatures: -40°C, 27°C, and 150°C (giving the 75 data points
shown above), for two input DC voltages: 0.60V and 2.70V. The data indicates that for the given
population of parts, calibration significantly reduced (by as much as 24%) the collective variation (spread)
of the absolute error of the population. It also significantly reduced (by as much as 38%) the mean
(average) of the absolute error and thereby brought it significantly closer to the ideal value of zero.
Although not guaranteed, it is believed that calibration will produce results similar to those shown above
for any population of parts including those which represent processing and temperature extremes.
56F8367 Technical Data, Rev. 3.0
162
Freescale Semiconductor
Preliminary
Equivalent Circuit for ADC Inputs
10.17 Equivalent Circuit for ADC Inputs
Figure 10-23 illustrates the ADC input circuit during sample & hold. S1 and S2 are always open/closed
at the same time that S3 is closed/open. When S1/S2 are closed & S3 is open, one input of the sample and
hold circuit moves to V
- V
/ 2, while the other charges to the analog input voltage. When the
REFH
REFH
switches are flipped, the charge on C1 and C2 are averaged via S3, with the result that a single-ended
analog input is switched to a differential voltage centered about V - V / 2. The switches switch
REFH
REFH
on every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). Note that there
are additional capacitances associated with the analog input pad, routing, etc., but these do not filter into
the S/H output voltage, as S1 provides isolation during the charge-sharing phase.
One aspect of this circuit is that there is an on-going input current, which is a function of the analog input
voltage, V
and the ADC clock frequency.
REF
3
Analog Input
4
S1
C1
C2
S/H
S3
VREFH - VREFH / 2
S2
2
1
C1 = C2 = 1pF
1. Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pf
2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pf
3. Equivalent resistance for the ESD isolation resistor and the channel select mux; 500 ohms
4. Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only
connected to it at sampling time; 1pf
Figure 10-23 Equivalent Circuit for A/D Loading
10.18 Power Consumption
This section provides additional detail which can be used to optimize power consumption for a given
application.
Power consumption is given by the following equation:
Total power =
A: internal [static component]
+B: internal [state-dependent component]
+C: internal [dynamic component]
+D: external [dynamic component]
+E: external [static]
A, the internal [static component], is comprised of the DC bias currents for the oscillator, leakage current,
PLL, and voltage references. These sources operate independently of processor state or operating
frequency.
B, the internal [state-dependent component], reflects the supply current required by certain on-chip
resources only when those resources are in use. These include RAM, Flash memory and the ADCs.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
163
2
C, the internal [dynamic component], is classic C*V *F CMOS power dissipation corresponding to the
56800E core and standard cell logic.
D, the external [dynamic component], reflects power dissipated on-chip as a result of capacitive loading
2
on the external pins of the chip. This is also commonly described as C*V *F, although simulations on two
of the IO cell types used on the device reveal that the power-versus-load curve does have a non-zero
Y-intercept.
Table 10-25 I/O Loading Coefficients at 10MHz
Intercept
Slope
PDU08DGZ_ME
PDU04DGZ_ME
1.3
0.11mW / pF
0.11mW / pF
1.15mW
Power due to capacitive loading on output pins is (first order) a function of the capacitive load and
frequency at which the outputs change. Table 10-20 provides coefficients for calculating power dissipated
in the IO cells as a function of capacitive load. In these cases:
TotalPower = Σ((Intercept +Slope*Cload)*frequency/10MHz)
where:
•
•
•
Summation is performed over all output pins with capacitive loads
TotalPower is expressed in mW
Cload is expressed in pF
Because of the low duty cycle on most device pins, power dissipation due to capacitive loads was found
to be fairly low when averaged over a period of time. The one possible exception to this is if the chip is
using the external address and data buses at a rate approaching the maximum system rate. In this case,
power from these buses can be significant.
E, the external [static component], reflects the effects of placing resistive loads on the outputs of the
2
device. Sum the total of all V /R or IV to arrive at the resistive load contribution to power. Assume V =
0.5 for the purposes of these rough calculations. For instance, if there is a total of 8 PWM outputs driving
10mA into LEDs, then P = 8*.5*.01 = 40mW.
In previous discussions, power consumption due to parasitics associated with pure input pins is ignored,
as it is assumed to be negligible.
56F8367 Technical Data, Rev. 3.0
164
Freescale Semiconductor
Preliminary
56F8367 Package and Pin-Out Information
Part 11 Packaging
Note: The 160 Map Ball Grid Array is not available in the 56F8167 device.
11.1 56F8367 Package and Pin-Out Information
This section contains package and pin-out information for the 56F8367. This device comes in a 160-pin
Low-profile Quad Flat Pack (LQFP) and 160 Map Ball Grid Array. Figure 11-1 shows the package
lay-out for the 160-pin LQFP, and Figure 11-2 for the160 Map Ball Grid Array. Figure 11-5 shows the
mechanical parameters for the LQFP package and Figure 11-3 for the MAPBGA, Table 11-1 lists the
pin-out for the 160-pin LQFP and Table 11-2 lists the pin-out for the 160 MAPBGA.
Orientation Mark
V
ANB4
DD_IO
V
2
ANB3
ANB2
ANB1
ANB0
PP
CLKO
TXD0
RXD0
121
Pin 1
PHASEA1
V
SSA_ADC
PHASEB1
INDEX1
V
V
DDA_ADC
REFH
HOME1
A1
V
V
V
V
REFP
REFMID
REFN
A2
A3
A4
A5
REFLO
TEMP_SENSE
ANA7
V
4
ANA6
CAP
V
ANA5
DD_IO
A6
ANA4
A7
A8
ANA3
ANA2
A9
ANA1
A10
A11
A12
A13
ANA0
CLKMODE
RESET
RSTO
V
V
A14
A15
DD_IO
3
CAP
V
EXTAL
SS
D7
D8
D9
XTAL
VDDA_OSC_PLL
OCR_DIS
D6
V
DD_IO
D10
D5
GPIOB0
GPIOB1
GPIOB2
GPIOB3
GPIOB4
D4
FAULTA3
D3
FAULTA2
FAULTA1
PWMB0
PWMB1
PWMB2
D2
81
41
FAULTA0
PWMA5
* When the on-chip regulator is disabled, these four pins become 2.5V VDD_CORE
.
Figure 11-1 Top View, 56F8367 160-Pin LQFP Package
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
165
Table 11-1 56F8367 160-Pin LQFP Package Identification by Pin Number
Signal
Name
Pin No.
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
1
2
VDD_IO
41
42
VSS
81
82
PWMA5
121
122
ANB5
ANB6
VPP
2
VDD_IO
FAULTA0
3
4
5
CLKO
TXD0
RXD0
43
44
45
PWMB3
PWMB4
PWMB5
83
84
85
D2
123
124
125
ANB7
EXTBOOT
VSS
FAULTA1
FAULTA2
6
7
PHASEA1
PHASEB1
INDEX1
HOME1
A1
46
47
48
49
50
51
52
GPIOB5
GPIOB6
GPIOB7
TXD1
RXD1
WR
86
87
88
89
90
91
92
D3
FAULTA3
D4
126
127
128
129
130
131
132
ISA0
ISA1
ISA2
TD0
TD1
TD2
TD3
8
9
D5
10
11
12
D6
A2
OCR_DIS
VDDA_OSC_PLL
A3
RD
13
14
A4
A5
53
54
PS
DS
93
94
XTAL
133
134
TC0
EXTAL
VDD_IO
15
16
VCAP4*
VDD_IO
55
56
GPIOD0
GPIOD1
95
96
VCAP3*
VDD_IO
135
136
TC1
TRST
17
18
19
20
21
A6
A7
57
58
59
60
61
GPIOD2
GPIOD3
GPIOD4
GPIOD5
ISB0
97
98
RSTO
RESET
CLKMODE
ANA0
137
138
139
140
141
TCK
TMS
TDI
A8
99
A9
100
101
TDO
A10
ANA1
VPP1
22
A11
62
VCAP1*
102
ANA2
142
CAN_TX
23
24
A12
A13
63
64
ISB1
ISB2
103
104
ANA3
ANA4
143
144
CAN_RX
VCAP2*
25
A14
65
IRQA
105
ANA5
145
SS0
* When the on-chip regulator is disabled, these four pins become 2.5V VDD_CORE
.
56F8367 Technical Data, Rev. 3.0
166
Freescale Semiconductor
Preliminary
56F8367 Package and Pin-Out Information
Table 11-1 56F8367 160-Pin LQFP Package Identification by Pin Number (Continued)
Signal
Name
Pin No.
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
26
27
A15
VSS
66
67
IRQB
106
107
ANA6
ANA7
146
147
SCLK0
MISO0
FAULTB0
28
29
D7
D8
68
69
FAULTB1
FAULTB2
108
109
TEMP_SENSE
VREFLO
148
149
MOSI0
D11
30
31
32
33
34
35
D9
70
71
72
73
74
75
D0
D1
110
111
112
113
114
115
VREFN
VREFMID
VREFP
150
151
152
153
154
155
D12
D13
VDD_IO
D10
FAULTB3
PWMA0
VSS
D14
GPIOB0
GPIOB1
GPIOB2
VREFH
D15
VDDA_ADC
VSSA_ADC
A0
PWMA1
PHASEA0
36
37
GPIOB3
GPIOB4
76
77
PWMA2
VDD_IO
116
117
ANB0
ANB1
156
157
PHASEB0
INDEX0
38
39
40
PWMB0
PWMB1
PWMB2
78
79
80
PWMA3
PWMA4
VSS
118
119
120
ANB2
ANB3
ANB4
158
159
160
HOME0
EMI_MODE
VSS
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
167
1
2
3
4
5
6
7
8
9
10
11 12 13 14
A
ISA0
INDEX0
TXD0
D15
VPP
1
TC0
TC1
ANB4
D12
TD1
TD0
ANB7
PHASEA0
D11
D13
ANB5
ANB3
SCLK0
MOSI0
TMS
TDI
B
C
D
E
F
EMI_
MODE
PHASEB0
HOME0
CAN_RX
EXTBOOT
ISA1
ANB1
ANB6
ANB2
VDDA_ADC
VPP
2
A0
D14
PHASEA1
PHASEB1
ANB0
VREFP
VREFH
ISA2 VSSA_ADC
RXD0
MISO0
TD2
TD3
CAN_TX TDO
TCK
HOME1
SS0
TRST
TEMP_
SENSE
VCAP
2
VREFLO
VREFMID
HOME1 INDEX1
A1
A2
VDD_IO
VSS
VSS
VDD_IO
ANA7
VREFN
ANA6
A3
A8
VDD_IO
VDD_IO
A4
A6
ANA4
ANA2
A5
A7
ANA3
ANA0
ANA1
G
H
VCAP
A11
4
VSS
CLKO
MODE
V
CAP3
A12
A15
ANA5
A9
A10
A14
J
K
L
EXTAL
RESET
A13
RSTO
VDDA_
VSS
D10
VSS
OSC_PLL OCR_DIS
V
CAP1
D7
D9
D8
VDD_IO GPIOD2 VDD_IO
IRQA
VDD_IO
VSS
D6
XTAL
D5
FAULTB2
GPIOB0 GPIOB2 GPIOB1
ISB1 FAULTB1
D4
D3
GPIOD1
WR
DS
GPIOD5
M
GPIOB3 GPIOB4
PWMB5
GPIOB7
GPIOB5
TXD1
PWMA0
FAULTA2 FAULTA3
FAULTA0 FAULTA1
PWMA3
PWMA5
N
P
PWMB0
PWMB2
D1
D0
PWMB3
RXD1
RD
PWMA2
PS
ISB0 FAULTB0
GPIOD3
GPIOD4
GPIOD0
PWMB1 PWMB4 GPIOB6
ISB2
IRQB
PWMA1 PWMA4
D2
FAULTB3
Figure 11-2 Top View, 56F8367 160-Pin MAPBGA Package
56F8367 Technical Data, Rev. 3.0
168
Freescale Semiconductor
Preliminary
56F8367 Package and Pin-Out Information
Table 11-2 56F8367 -160 MAPBGA Package Identification by Pin Number
Ball
No.
Ball
No.
Ball
No.
Ball
No.
Signal Name
Signal Name
Signal Name
Signal Name
F4
VDD_IO
K11
K7
VSS
N12
N13
PWMA5
A13
B12
ANB5
ANB6
C2
VPP
2
VDD_IO
FAULTA0
D3
B1
D2
CLKO
TXD0
RXD0
N3
P2
M3
PWMB3
PWMB4
PWMB5
P14
N14
M13
D2
A12
B11
J11
ANB7
FAULTA1
FAULTA2
EXTBOOT
VSS
C1
D1
E2
D3
E3
E4
F2
PHASEA1
PHASEB1
INDEX1
HOME1
A1
N4
P3
M4
P4
N5
L4
GPIOB5
GPIOB6
GPIOB7
TXD1
RXD1
WR
L13
M14
L14
L12
L11
K14
K13
D3
A11
C11
D11
B10
A10
D10
E10
ISA0
ISA1
ISA2
TD0
TD1
TD2
TD3
FAULTA3
D4
D5
D6
A2
OCR_DIS
VDDA_OSC_PLL
A3
P5
RD
F1
F3
A4
A5
N6
L5
PS
DS
K12
J12
XTAL
A9
TC0
EXTAL
F11
VDD_IO
G4
K5
VCAP4*
VDD_IO
P6
L6
GPIOD0
GPIOD1
H11
K10
VCAP3*
VDD_IO
B9
D9
TC1
TRST
G1
G3
G2
H1
H2
A6
A7
A8
A9
A10
K6
N7
P7
L7
GPIOD2
GPIOD3
GPIOD4
GPIOD5
ISB0
J13
J14
H12
G13
H13
RSTO
D8
A8
B8
D7
A7
TCK
TMS
TDI
RESET
CLKMODE
ANA0
TDO
N8
ANA1
VPP1
H4
A11
K8
VCAP1*
G12
ANA2
D6
CAN_TX
H3
J1
A12
A13
L8
ISB1
ISB2
F13
F12
ANA3
ANA4
B7
E8
CAN_RX
VCAP2*
P8
J2
A14
K9
IRQA
H14
ANA5
D5
SS0
* When the on-chip regulator is disabled, these four pins become 2.5V VDD_CORE
.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
169
Table 11-2 56F8367 -160 MAPBGA Package Identification by Pin Number (Continued)
Ball
No.
Ball
No.
Ball
No.
Ball
No.
Signal Name
Signal Name
Signal Name
Signal Name
J3
A15
VSS
P9
N9
IRQB
G14
E13
ANA6
ANA7
A6
SCLK0
MISO0
J4
FAULTB0
D4
K1
K3
D7
D8
L9
FAULTB1
FAULTB2
E11
E12
TEMP_SENSE
VREFLO
B6
A5
MOSI0
D11
L10
K2
E5
K4
L1
L3
L2
D9
P10
N10
P11
M11
G11
P12
D0
F14
E14
D13
D14
C14
D12
VREFN
A4
B5
C4
A3
C3
A2
D12
VDD_IO
D10
D1
VREFMID
VREFP
D13
FAULTB3
PWMA0
VSS
D14
GPIOB0
GPIOB1
GPIOB2
VREFH
D15
VDDA_ADC
VSSA_ADC
A0
PWMA1
PHASEA0
M1
M2
GPIOB3
GPIOB4
N11
E9
PWMA2
VDD_IO
C13
B14
ANB0
ANB1
B4
A1
PHASEB0
INDEX0
N1
P1
N2
PWMB0
PWMB1
PWMB2
M12
P13
E7
PWMA3
PWMA4
VSS
C12
B13
A14
ANB2
ANB3
ANB4
B3
B2
E6
HOME0
EMI_MODE
VSS
56F8367 Technical Data, Rev. 3.0
170
Freescale Semiconductor
Preliminary
56F8367 Package and Pin-Out Information
D
X
LASER MARK FOR PIN 1
IDENTIFICATION IN
THIS AREA
Y
M
K
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND
TOLERANCES PER ASME Y14.5M, 1994.
3. DIMENSION b IS MEASURED AT THE
MAXIMUM SOLDER BALL DIAMETER,
PARALLEL TO DATUM PLANE Z.
4. DATUM Z (SEATING PLANE) IS DEFINED BY
THE SPHERICAL CROWNS OF THE SOLDER
BALLS.
E
5. PARALLELISM MEASUREMENT SHALL
EXCLUDE ANY EFFECT OF MARK ON TOP
SURFACE OF PACKAGE.
MILLIMETERS
DIM MIN MAX
0.20
A
A1
A2
b
1.32
0.27
1.18 REF
1.75
0.47
0.35
0.65
13X
e
D
E
e
15.00 BSC
15.00 BSC
1.00 BSC
0.50 BSC
S
METALIZED MARK FOR
PIN 1 IDENTIFICATION
IN THIS AREA
S
14 13 12 11 10
9
6
5
4
3
2
1
A
B
C
D
E
F
5
S
0.30 Z
A2
13X
e
A
G
H
J
160X
A1
0.15 Z
4
Z
K
L
M
DETAIL K
ROTATED 90 CLOCKWISE
°
N
P
3
160X
b
0.30 Z X Y
0.10 Z
VIEW M-M
CASE 1268-01
ISSUE O
DATE 04/06/98
Please see http://www.freescale.com for the most current mechanical drawing.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
171
Figure 11-3 160 MAPBGA Mechanical Information
11.2 56F8167 Package and Pin-Out Information
This section contains package and pin-out information for the 56F8167. This device comes in a 160-pin
Low-profile Quad Flat Pack (LQFP). Figure 11-4 shows the package outline for the 160-pin LQFP,
Figure 11-5 shows the mechanical parameters for this package, and Table 11-3 lists the pin-out for the
160-pin LQFP.
Orientation Mark
V
ANB4
DD_IO
V
2
ANB3
ANB2
ANB1
ANB0
PP
CLKO
TXD0
RXD0
121
Pin 1
SCLK1
MOSI1
MISO1
V
V
V
SSA_ADC
DDA_ADC
REFH
SS1
A1
V
V
V
V
REFP
REFMID
REFN
A2
A3
REFLO
A4
A5
NC
ANA7
V
V
4*
ANA6
ANA5
CAP
DD_IO
A6
ANA4
A7
A8
ANA3
ANA2
A9
ANA1
A10
A11
A12
A13
ANA0
CLKMODE
RESET
RSTO
A14
A15
V
V
DD_IO
3*
CAP
V
EXTAL
SS
D7
D8
D9
XTAL
VDDA_OSC_PLL
OCR_DIS
D6
D5
V
DD_IO
D10
GPIOB0
GPIOB1
GPIOB2
GPIOB3
GPIOB4
D4
NC
D3
NC
NC
PWMB0
PWMB1
PWMB2
81
D2
NC
NC
41
* When the on-chip regulator is disabled, these four pins become 2.5V VDD_CORE
.
Figure 11-4 Top View, 56F8167 160-Pin LQFP Package
56F8367 Technical Data, Rev. 3.0
172
Freescale Semiconductor
Preliminary
56F8167 Package and Pin-Out Information
Table 11-3 56F8167 160-Pin LQFP Package Identification by Pin Number
Signal
Name
Pin No.
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
1
2
VDD_IO
41
42
VSS
81
82
NC
NC
121
122
ANB5
ANB6
VPP
2
VDD_IO
3
4
5
CLKO
TXD0
RXD0
43
44
45
PWMB3
PWMB4
PWMB5
83
84
85
D2
NC
NC
123
124
125
ANB7
EXTBOOT
VSS
6
7
SCLK1
MOSI1
MISO1
SS1
46
47
48
49
50
51
52
GPIOB5
GPIOB6
GPIOB7
TXD1
RXD1
WR
86
87
88
89
90
91
92
D3
126
127
128
129
130
131
132
GPIOC8
GPIOC9
NC
D4
8
GPIOC10
GPIOE10
GPIOE11
GPIOE12
GPIOE13
9
D5
10
11
12
A1
D6
A2
OCR_DIS
VDDA_OSC_PLL
A3
RD
13
14
A4
A5
53
54
PS
DS
93
94
XTAL
133
134
TC0
EXTAL
VDD_IO
15
16
VCAP4*
VDD_IO
55
56
GPIOD0
GPIOD1
95
96
VCAP3*
VDD_IO
135
136
TC1
TRST
17
18
19
20
21
A6
A7
57
58
59
60
61
GPIOD2
GPIOD3
GPIOD4
GPIOD5
ISB0
97
98
RSTO
RESET
CLKMODE
ANA0
137
138
139
140
141
TCK
TMS
TDI
A8
99
A9
100
101
TDO
A10
ANA1
VPP1
22
A11
62
VCAP1*
102
ANA2
142
NC
23
24
A12
A13
63
64
ISB1
ISB2
103
104
ANA3
ANA4
143
144
NC
VCAP2*
25
A14
65
IRQA
105
ANA5
145
SS0
* When the on-chip regulator is disabled, these four pins become 2.5V VDD_CORE
Please see http://www.freescale.com for the most current mechanical drawing.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
173
Table 11-3 56F8167 160-Pin LQFP Package Identification by Pin Number (Continued)
Signal
Name
Pin No.
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
26
27
A15
VSS
66
67
IRQB
106
107
ANA6
ANA7
146
147
SCLK0
MISO0
FAULTB0
28
29
D7
D8
68
69
FAULTB1
FAULTB2
108
109
NC
148
149
MOSI0
D11
VREFLO
30
31
32
33
34
35
D9
70
71
72
73
74
75
D0
D1
110
111
112
113
114
115
VREFN
VREFMID
VREFP
150
151
152
153
154
155
D12
D13
VDD_IO
D10
FAULTB3
NC
D14
GPIOB0
GPIOB1
GPIOB2
VREFH
D15
VSS
VDDA_ADC
VSSA_ADC
A0
NC
PHASEA0
36
37
GPIOB3
GPIOB4
76
77
NC
116
117
ANB0
ANB1
156
157
PHASEB0
INDEX0
VDD_IO
38
39
40
PWMB0
PWMB1
PWMB2
78
79
80
NC
NC
118
119
120
ANB2
ANB3
ANB4
158
159
160
HOME0
EMI_MODE
VSS
VSS
56F8367 Technical Data, Rev. 3.0
174
Freescale Semiconductor
Preliminary
56F8167 Package and Pin-Out Information
160X
0.20 C A-B D
D
b
GG
D
2
6
D
(b)
SECTION G-G
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DATUMS A, B, AND D TO BE DETERMINED
WHERE THELEADS EXIT THE PLASTIC BODY
AT DATUM PLANE H.
4. DIMENSIONS D1 AND E1 DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25mm PER SIDE.
DIMENSIONS D1 AND E1 ARE MAXIMUM
PLASTIC BODY SIZE DIMENSIONS
INCLUDING MOLD MISMATCH.
D1
2
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL NOT CAUSE THE LEAD
WIDTH TO EXCEED THE MAXIMUM b
DIMENSION BY MORE THAN 0.08mm.
DAMBAR CAN NOT BE LOCATED ON THE
LOWER RADIUS OR THE FOOT. MINIMUM
SPACE BETWEEN A PROTRUSION AND AN
ADJACENT LEAD IS 0.07mm.
D1
4X
0.20 H A-B D
DETAIL F
6. EXACT SHAPE OF CORNERS MAY VARY.
0.08 C
156X
e
C
MILLIMETERS
DIM MIN MAX
4X e/2
SEATING
PLANE
160X
e
A
A1
A2
b
b1
c
c1
D
D1
e
---
0.05
1.35
0.17
0.17
0.09
0.09
1.60
0.15
1.45
0.27
0.23
0.20
0.16
M
0.08
C A-B D
θ2
θ1
H
26.00 BSC
24.00 BSC
0.50 BSC
R1
R2
E
E1
L
26.00 BSC
24.00 BSC
0.45
0.75
L1
R1
R2
S
1.00 REF
θ3
0.25
0.08
0.08
0.20
---
0.20
---
θ
GAGE
PLANE
S
L
(L1)
θ
0
0
11
11
7
---
13
13
°
°
°
°
°
θ 1
θ 2
θ 3
°
°
DETAIL F
Figure 11-5 160-pin LQFP Mechanical Information
Please see http://www.freescale.com for the most current mechanical drawing.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
175
Part 12 Design Considerations
12.1 Thermal Design Considerations
An estimation of the chip junction temperature, T , can be obtained from the equation:
J
T = T + (R
PD)
θJΑ x
J
A
where:
o
T
R
= Ambient temperature for the package ( C)
A
o
= Junction-to-ambient thermal resistance ( C/W)
θJΑ
P
= Power dissipation in the package (W)
D
The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy
estimation of thermal performance. Unfortunately, there are two values in common usage: the value
determined on a single-layer board and the value obtained on a board with two planes. For packages such
as the PBGA, these values can be different by a factor of two. Which value is closer to the application
depends on the power dissipated by other components on the board. The value obtained on a single-layer
board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the
internal planes is usually appropriate if the board has low-power dissipation and the components are well
separated.
When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal
resistance and a case-to-ambient thermal resistance:
R
R
R
θJΑ = θJC + θCΑ
where:
R
R
R
= Package junction-to-ambient thermal resistance °C/W
= Package junction-to-case thermal resistance °C/W
= Package case-to-ambient thermal resistance °C/W
θJA
θJC
θCA
R
θJC is device-related and cannot be influenced by the user. The user controls the thermal environment to
change the case-to-ambient thermal resistance, R θCA . For instance, the user can change the size of the heat
sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit
board, or change the thermal dissipation on the printed circuit board surrounding the device.
To determine the junction temperature of the device in the application when heat sinks are not used, the
Thermal Characterization Parameter (Ψ ) can be used to determine the junction temperature with a
JT
measurement of the temperature at the top center of the package case using the following equation:
T = T + (Ψ x P )
J
T
JT
D
where:
o
T
Ψ
= Thermocouple temperature on top of package ( C)
= Thermal characterization parameter ( C)/W
T
o
JT
P
= Power dissipation in package (W)
D
56F8367 Technical Data, Rev. 3.0
176
Freescale Semiconductor
Preliminary
Electrical Design Considerations
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so
that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire
is placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimizing the size of the clearance is important to minimize the change in
thermal performance caused by removing part of the thermal interface to the heat sink. Because of the
experimental difficulties with this technique, many engineers measure the heat sink temperature and then
back-calculate the case temperature using a separate measurement of the thermal resistance of the
interface. From this case temperature, the junction temperature is determined from the junction-to-case
thermal resistance.
12.2 Electrical Design Considerations
CAUTION
This device contains protective circuitry to guard
against damage due to high static voltage or electrical
fields. However, normal precautions are advised to
avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit.
Reliability of operation is enhanced if unused inputs are
tied to an appropriate voltage level.
Use the following list of considerations to assure correct operation:
•
Provide a low-impedance path from the board power supply to each V pin on the hybrid controller, and
DD
from the board ground to each V (GND) pin
SS
•
The minimum bypass requirement is to place six 0.01–0.1µF capacitors positioned as close as possible to
the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each
of the V /V pairs, including V
/V
Ceramic and tantalum capacitors tend to provide better
DD SS
DDA SSA.
performance tolerances.
•
Ensure that capacitor leads and associated printed circuit traces that connect to the chip V and V (GND)
DD SS
pins are less than 0.5 inch per capacitor lead
•
•
Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for V and V
DD
SS
Bypass the V and V layers of the PCB with approximately 100µF, preferably with a high-grade
DD
SS
capacitor such as a tantalum capacitor
•
Because the device’s output signals have fast rise and fall times, PCB trace lengths should be minimal
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
177
•
Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.
This is especially critical in systems with higher capacitive loads that could create higher transient currents
in the V and V circuits.
DD
SS
•
•
Take special care to minimize noise levels on the V , V
and V
pins
SSA
REF DDA
Designs that utilize the TRST pin for JTAG port or EOnCE module functionality (such as development or
debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means
to assert TRST independently of RESET. Designs that do not require debugging functionality, such as
consumer products, should tie these pins together.
•
Because the Flash memory is programmed through the JTAG/EOnCE port, the designer should provide an
interface to this port to allow in-circuit Flash programming
12.3 Power Distribution and I/O Ring Implementation
Figure 12-1 illustrates the general power control incorporated in the 56F8367/56F8167. This chip
contains two internal power regulators. One of them is powered from the V
pin and cannot
DDA_OSC_PLL
be turned off. This regulator controls power to the internal clock generation circuitry. The other regulator
is powered from the V pins and provides power to all of the internal digital logic of the core, all
DD_IO
peripherals and the internal memories. This regulator can be turned off, if an external V
voltage
DD_CORE
is externally applied to the V
pins.
CAP
In summary, the entire chip can be supplied from a single 3.3 volt supply if the large core regulator is
enabled. If the regulator is not enabled, a dual supply 3.3V/2.5V configuration can also be used.
Notes:
•
•
Flash, RAM and internal logic are powered from the core regulator output
V 1 and V 2 are not connected in the customer system
PP
PP
•
All circuitry, analog and digital, shares a common V bus
SS
VDDA_OSC_PLL
VDD
VDDA_ADC
VREFH
VREFP
VREFMID
VREFN
VREFLO
VCAP
REG
REG
I/O
ADC
CORE
OSC
VSS
VSSA_ADC
Figure 12-1 Power Management
56F8367 Technical Data, Rev. 3.0
178
Freescale Semiconductor
Preliminary
Power Distribution and I/O Ring Implementation
Part 13 Ordering Information
Table 13-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor
sales office or authorized distributor to determine availability and to order parts.
Table 13-1 Ordering Information
Ambient
Temperature
Range
Supply
Voltage
Pin
Count
Frequency
(MHz)
Part
Package Type
Order Number
MC56F8367
MC56F8167
3.0–3.6 V
3.0–3.6 V
160
160
60
40
-40° to + 105° C
-40° to + 105° C
MC56F8367VPY60
MC56F8167VPY
Low-Profile Quad Flat Pack (LQFP)
Low-Profile Quad Flat Pack (LQFP)
MC56F8367
MC56F8367
3.0–3.6 V
3.0–3.6 V
160
160
60
60
-40° to + 105° C
-40° to + 125° C
MC56F8367VPYE*
MC56F8367MPYE*
Low-Profile Quad Flat Pack (LQFP)
Low-Profile Quad Flat Pack (LQFP)
Low-Profile Quad Flat Pack (LQFP)
MC56F8167
MC56F8367
3.0–3.6 V
3.0–3.6 V
160
160
40
60
-40° to + 105° C
-40° to + 105° C
MC56F8167VPYE*
MC56F8367VVF*
Mold Array Process Ball Grid Array
(MAPBGA)
*This package is RoHS compliant.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
179
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This product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc. 2005. All rights reserved.
MC56F8367
Rev. 3.0
09/2005
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