MC68HLC908LJ12_1 [FREESCALE]
Addendum to MC68HC908LJ12 Technical Data; 增编MC68HC908LJ12技术参数
| 型号： | MC68HLC908LJ12_1 |
| 厂家： | 
Freescale |
| 描述： | Addendum to MC68HC908LJ12 Technical Data |
| 文件： | 总16页 (文件大小：633K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
Addendum
HC908LJ12AD/D
Rev. 0, 6/2003
Addendum to
MC68HC908LJ12
Technical Data
This addendum provides information to the following MCU devices:
•
•
MC68HLC908LJ12 (see page 1)
MC68HC08LJ12 (see page 9)
The entire MC68HC908LJ12 Technical Data, Rev. 2 (Motorola document
number MC68HC908LJ12/D) applies to the these two devices, with exceptions
outlined in this addendum.
Amendments to MC68HC908LJ12/D, Rev. 2, are documented on page 13.
MC68HLC908LJ12
The MC68HLC908LJ12 is a low-voltage version of the MC68HC908LJ12, with
an operating voltage range of 2.4 to 3.3V.
FLASH Memory
The FLASH memory can be read at operating voltages from 2.4 to 3.3V.
Program or erase operations require a minimum operating voltage of 2.7V.
Low-Voltage Inhibit
(LVI)
The LVI module is not designed for the MC68HLC908LJ12. After an MCU
reset, the LVI module is disabled (LVIPWRD = 1 in CONFIG1). The LVIPWRD
bit should be left as logic 1 (the default setting).
Electrical
Specifications
Electrical specifications for the MC68HLC908LJ12 device are given in the
following tables.
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HC908LJ12AD/D
Functional Operating
Range
Table 1. Operating Range
Characteristic
Symbol
TA
Value
Unit
°C
Operating temperature range
Operating voltage range
– 40 to +85
VDD
2.4 to 2.7
2.7 to 3.3
4
V
Maximum internal operating
frequency
fOP
2
MHz
V
Operating voltage for FLASH
memory program and erase
operations
VDD
2.7 to 3.3
DC Electrical
Characteristics
Table 2. DC Electrical Characteristics (2.4 to 2.7V)
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
Output high voltage (ILOAD = –1.0 mA)
All ports
VOH
VDD–0.4
—
—
V
Output low voltage
(ILOAD = 0.8mA) All ports
VOL
—
—
0.4
V
(ILOAD = 4.0 mA) PTB2–PTB5
(ILOAD = 10.0 mA) PTB0/TxD–PTB1
Input high voltage
All ports, RST, IRQ, OSC1
VIH
VIL
0.7 × VDD
VDD
—
—
V
V
Input low voltage
All ports, RST, IRQ, OSC1
VSS
0.3 × VDD
VDD supply current
Run(3), fOP = 2 MHz
with all modules on
with ADC on
with ADC off
Wait(4), fOP = 2 MHz (all modules off)
—
—
—
—
—
—
mA
mA
mA
5.2
3.8
2.8
2.3
—
—
mA
IDD
Stop, fOP = 8 kHz(5)
25°C (with OSC, RTC, LCD(6), LVI on)
200
—
—
µA
25°C (with OSC, RTC, LCD(6) on)
25°C (with OSC, RTC on)
25°C (all modules off)
27
15
1
—
—
—
—
—
—
µA
µA
µA
Digital I/O ports Hi-Z leakage current
All ports, RST
IIL
—
—
± 10
µA
Addendum to MC68HC908LJ12 Technical Data
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HC908LJ12AD/D
MC68HLC908LJ12
Table 2. DC Electrical Characteristics (2.4 to 2.7V) (Continued)
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
Input current
IRQ
IIN
—
—
± 1
µA
COUT
CIN
Capacitance
Ports (as input or output)
—
—
—
—
12
8
pF
POR re-arm voltage(7)
VPOR
RPOR
VHI
0
—
—
—
100
—
mV
V/ms
V
POR rise-time ramp rate(8)
0.02
1.5 × VDD
2 × VDD
Monitor mode entry voltage (at IRQ pin)
Pullup resistors(9)
PTA0–PTA3, PTD4–PTD7 configured as KBI0–KBI7
RST, IRQ
RPU1
RPU2
—
—
25
27
—
—
kΩ
kΩ
1. VDD = 2.4 to 2.7 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) IDD measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than
100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD
4. Wait IDD measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than 100 pF on
all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait IDD
.
.
5. The 8kHz clock is from a 32kHz clock input at OSC1, for the driving the RTC.
6. LCD driver configured for low current mode.
7. Maximum is highest voltage that POR is guaranteed.
8. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum
VDD is reached.
9. RPU1 and RPU2 are measured at VDD = 2.6V.
Table 3. DC Electrical Characteristics (2.7 to 3.3V)
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
Output high voltage (ILOAD = –1.0 mA)
All ports
VOH
VDD–0.4
—
—
V
Output low voltage
(ILOAD = 0.8mA) All ports
(ILOAD = 4.0 mA) PTB2–PTB5
VOL
—
—
0.4
V
(ILOAD = 10.0 mA) PTB0/TxD–PTB1
Input high voltage
All ports, RST, IRQ, OSC1
VIH
VIL
0.7 × VDD
VDD
—
—
V
V
Input low voltage
All ports, RST, IRQ, OSC1
VSS
0.3 × VDD
Addendum to MC68HC908LJ12 Technical Data
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HC908LJ12AD/D
Table 3. DC Electrical Characteristics (2.7 to 3.3V) (Continued)
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
VDD supply current
Run(3), fOP = 4 MHz
with all modules on
with ADC on
with ADC off
—
—
—
—
—
—
8
6
5
mA
mA
mA
Wait(4), fOP = 4 MHz (all modules off)
—
—
3.5
mA
IDD
Stop, fOP = 8 kHz(5)
25°C (with OSC, RTC, LCD(6), LVI on)
—
—
280
µA
25°C (with OSC, RTC, LCD(6) on)
25°C (with OSC, RTC on)
25°C (all modules off)
—
—
—
—
—
—
38
15
1
µA
µA
µA
Digital I/O ports Hi-Z leakage current
All ports, RST
IIL
—
—
—
—
± 10
± 1
µA
µA
Input current
IRQ
IIN
COUT
CIN
Capacitance
Ports (as input or output)
—
—
—
—
12
8
pF
POR re-arm voltage(7)
VPOR
RPOR
VHI
0
—
—
—
100
—
mV
V/ms
V
POR rise-time ramp rate(8)
0.02
1.5 × VDD
2 × VDD
Monitor mode entry voltage (at IRQ pin)
Pullup resistors(9)
PTA0–PTA3, PTD4–PTD7 configured as KBI0–KBI7
RST, IRQ
RPU1
RPU2
—
—
25
27
—
—
kΩ
kΩ
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) IDD measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than
100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD
4. Wait IDD measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than 100 pF on
all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait IDD
.
.
5. The 8kHz clock is from a 32kHz clock input at OSC1, for the driving the RTC.
6. LCD driver configured for low current mode.
7. Maximum is highest voltage that POR is guaranteed.
8. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum
VDD is reached.
9. RPU1 and RPU2 are measured at VDD = 3V.
Addendum to MC68HC908LJ12 Technical Data
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MC68HLC908LJ12
Oscillator
Characteristics
Table 4. Oscillator Specifications (2.4 to 2.7V)
Characteristic
Symbol
Min
Typ
Max
Unit
fICLK
Internal oscillator clock frequency
External reference clock to OSC1(1)
Crystal reference frequency(2)
—
See Figure 1.
—
Hz
fOSC
dc
—
8M
Hz
Hz
fXCLK
CL
32.768k
—
4.9152M
Crystal load capacitance(3)
Crystal fixed capacitance
Crystal tuning capacitance
Feedback bias resistor
—
—
—
—
—
—
—
—
—
—
C1
2 × CL (25p)
2 × CL (25p)
10M
F
F
C2
RB
Ω
Ω
Series resistor(4)
RS
100k
1. No more than 10% duty cycle deviation from 50%.
2. Fundamental mode crystals only.
3. Consult crystal manufacturer’s data.
4. Not Required for high frequency crystals.
Table 5. Oscillator Specifications (2.7 to 3.3V)
Characteristic
Symbol
Min
Typ
Max
Unit
fICLK
Internal oscillator clock frequency
—
See Figure 1.
—
Hz
External reference clock to OSC1(1)
Crystal reference frequency(2)
fOSC
dc
—
16M
Hz
Hz
fXCLK
CL
32.768k
—
4.9152M
Crystal load capacitance(3)
Crystal fixed capacitance
Crystal tuning capacitance
Feedback bias resistor
—
—
—
—
—
—
—
—
—
—
C1
2 × CL (25p)
2 × CL (25p)
10M
F
F
C2
RB
Ω
Ω
Series resistor(4)
RS
100k
1. No more than 10% duty cycle deviation from 50%.
2. Fundamental mode crystals only.
3. Consult crystal manufacturer’s data.
4. Not Required for high frequency crystals.
Addendum to MC68HC908LJ12 Technical Data
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HC908LJ12AD/D
70
–40
°
C
)
60
z
(
K
50
40
30
20
10
0
+25
+85
°
°
C
C
L
CI
f
,
c
u ne
f
C
O
a
n
et r
2
3
4
5
6
Supply Voltage, V (V)
DD
Figure 1. Typical Internal Oscillator Frequency
ADC Electrical
Characteristics
Table 6. ADC Electrical Characteristics (2.4 to 3.3V)
Characteristic
Supply voltage
Input range
Symbol
Min
2.4
0
Max
3.3
Unit
V
Notes
VDDA
VADIN
BAD
VDDA
V
ADIN ≤ VDDA
V
Resolution
10
10
bits
1,024 counts
Includes quantization.
±1 ADC count = ±0.5 LSB
AAD
Absolute accuracy
See Figure 2 and Figure 3.
fADIC
RAD
tADIC = 1/fADIC
ADC internal clock
Conversion range
32 k
2 M
Hz
V
VREFL
VREFH
ADC voltage
reference high
VREFH
VREFL
tADC
VDDA + 0.1
—
V
V
ADC voltage
reference low
VSSA – 0.1
VSSA is tied to VSS internally.
—
17
—
tADIC
cycles
tADIC
Conversion time
Sample time
16
5
tADS
cycles
MAD
ZADI
FADI
Monotonically
Guaranteed
V
ADIN = VREFL
Zero input reading
Full-scale reading
Input capacitance
Input impedance
VREFH/VREFL
000
3FC
—
001
3FF
20
HEX
HEX
pF
VADIN = VREFH
Not tested.
CADI
RADI
IVREF
20M
—
—
Ω
Measured at 5V
Not tested.
1.6
mA
Addendum to MC68HC908LJ12 Technical Data
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HC908LJ12AD/D
MC68HLC908LJ12
35
30
25
20
15
10
5
35
30
25
r
o
20
15
10
5
E
A
A
0
0
-5
-5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
ADC Input Voltage
ADC Input Voltage
(a) VDD = 2.4V at –40°C
(d) VDD = 2.7V at –40°C
35
30
25
20
15
10
5
35
30
25
20
15
10
5
0
0
-5
-5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
ADC Input Voltage
ADC Input Voltage
(b) VDD = 2.4V at 25°C
(e) VDD = 2.7V at 25°C
35
30
25
20
15
10
5
35
30
25
20
15
10
5
0
0
-5
-5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
ADC Input Voltage
ADC Input Voltage
(c) VDD = 2.4V at 85°C
(f) VDD = 2.7V at 85°C
Note: ADC performance increases with increase in operating voltage and temperature.
Figure 2. Typical ADC Accuracy (2.4V and 2.7V)
Addendum to MC68HC908LJ12 Technical Data
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35
30
25
or
20
15
10
5
E
DCCo u nt
A
0
-5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
ADC Input Voltage
VDD = 3.0 to 3.3V, at –40 to 85°C
Figure 3. Typical ADC Accuracy (3V and 3.3V)
Memory
Characteristics
At an operating voltage of less than 2.7 V, the FLASH memory can only be
read. Program and erase are achieved at an operating voltage of 2.7 to 3.3V.
The program and erase parameters in the MC68HC908LJ12 Technical Data
are for V = 2.7 to 3.3V only.
DD
MC68HLC908LJ12
Order Numbers
Table 7 shows the ordering numbers for the MC68HLC908LJ12.
Table 7. MC68HLC908LJ12 Order Numbers
Operating
MC Order Number (1)
Package
Temperature Range
–40 °C to +85 °C
–40 °C to +85 °C
–40 °C to +85 °C
MC68HLC98LJ12CFB
MC68HLC98LJ12CPB
MC68HLC98LJ12CFU
52-pin LQFP
64-pin LQFP
64-pin QFP
1. The missing “0” in “908” is intentional.
Addendum to MC68HC908LJ12 Technical Data
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HC908LJ12AD/D
MC68HC08LJ12
MC68HC08LJ12
The MC68HC08LJ12 is the ROM part equivalent to the MC68HC908LJ12.
Table 8. Summary of MC68HC08LJ12 and MC68HC908LJ12 Differences
MC68HC08LJ12
MC68HC908LJ12
—
3.3V ± 10%
5.0V ± 10%
Operating voltages
5.0V ± 10%
Memory ($C000–$EFFF)
12,288 bytes ROM
12,288 bytes FLASH
48 bytes FLASH
User vectors ($FFD0–$FFFF)
48 bytes ROM
FLASH related registers.
$FE08 — FLCR
$FF09 — FLBPR
Not used;
locations are reserved.
Registers at $FE08 and $FF09
Monitor ROM
($FC00–$FDFF and $FE10–$FFCF)
Used for testing and FLASH
programming/erasing.
Used for testing purposes only.
52-pin LQFP
64-pin LQFP
64-pin QFP
52-pin LQFP
64-pin LQFP
64-pin QFP
Available packages
MCU Block Diagram
Memory Map
Figure 4 shows the block diagram of the MC68HC08LJ12.
The MC68HC08LJ128 has 12,288 bytes of user ROM from $C000 to $EFFF,
and 48 bytes of user ROM vectors from $FFD0 to $FFFF. On the
MC68HC908LJ12 these memory locations are FLASH memory.
Figure 5 shows the memory map of the MC68HC08LJ12.
Reserved Registers
Monitor ROM
The two registers at $FE08 and $FE09 are reserved locations on the
MC68HC08LJ12.
On the MC68HC908LJ12, these two locations are the FLASH control register
and the FLASH block protect register respectively.
The monitor program (monitor ROM: $FE10–$FFCF and $FC00–$FDFF) on
the MC68HC08LJ12 is for device testing only.
Addendum to MC68HC908LJ12 Technical Data
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HC908LJ12AD/D
INTERNAL BUS
M68HC08 CPU
PTA7/ADC3
PTA6/ADC2
PTA5/ADC1
PTA4/ADC0
PTA3/KBI3**
PTA2/KBI2**
PTA1/KBI1**
PTA0/KBI0**
CPU
REGISTERS
ARITHMETIC/LOGIC
UNIT (ALU)
KEYBOARD INTERRUPT
MODULE
A
R
D
O
CONTROL AND STATUS REGISTERS — 96 BYTES
USER ROM — 12,288 BYTES
10-BIT ANALOG-TO-DIGITAL
CONVERTER MODULE
2-CHANNEL TIMER INTERFACE
MODULE 1
USER RAM — 512 BYTES
PTB7/ADC5
PTB6/ADC4
#
‡
PTB5/T2CH1
MONITOR ROM — 960 BYTES
B
‡
PTB4/T2CH0
2-CHANNEL TIMER INTERFACE
MODULE 2
‡
PTB3/T1CH1
USER ROM VECTOR — 48 BYTES
‡
PTB2/T1CH0
†
PTB1/RxD
CLOCK GENERATOR MODULE
OSC1
†
SERIAL COMMUNICATIONS
INTERFACE MODULE
(WITH INFRARED
PTB0/TxD
32.768-kHz OSCILLATOR
OSC2
PTC7/FP26
PTC6/FP25
PTC5/FP24
PTC4/FP23
PTC3/FP22
PTC2/FP21
PTC1/FP20
PTC0/FP19
ENCODER/DECODER)
PHASE-LOCKED LOOP
CGMXFC
REAL TIME CLOCK
MODULE
SYSTEM INTEGRATION
MODULE
* RST
* IRQ
EXTERNAL INTERRUPT
MODULE
LIQUID CRYSTAL DISPLAY
DRIVER MODULE
FP1–FP18
BP0–BP2
FP0/BP3
COMPUTER OPERATING
PROPERLY MODULE
PTD7/KBI7**
PTD6/KBI6**
PTD5/KBI5**
PTD4/KBI4**
PTD3/SPSCK
PTD2/MOSI
PTD1/MISO
PTD0/SS
SERIAL PERIPHERAL
INTERFACE MODULE
POWER-ON RESET
MODULE
#
LOW-VOLTAGE INHIBIT
MODULE
VDDA
VDD
VSS
POWER
* Pin contains integrated pullup device.
** Pin contains integrated pullup device if configured as KBI.
†
VREFH
VREFL
High current sink pin, 15mA.
High current sink pin, 8mA.
ADC REFERENCE
‡
# Pins available on 64-pin packages only.
Shaded blocks indicate differences to MC68HC908LJ12
Figure 4. MC68HC08LJ12 Block Diagram
Addendum to MC68HC908LJ12 Technical Data
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HC908LJ12AD/D
MC68HC08LJ12
$0000
I/O Registers
↓
96 Bytes
$005F
$0060
RAM
↓
512 Bytes
$025F
$0260
Unimplemented
↓
48,544 Bytes
$BFFF
$C000
ROM
↓
12,288 Bytes
$EFFF
$F000
Unimplemented
↓
3,072 Bytes
$FBFF
$FC00
Monitor ROM 1
↓
512 Bytes
$FDFF
$FE00
$FE01
$FE02
$FE03
$FE04
$FE05
$FE06
$FE07
$FE08
$FE09
$FE0A
$FE0B
$FE0C
$FE0D
$FE0E
$FE0F
SIM Break Status Register (SBSR)
SIM Reset Status Register (SRSR)
Reserved
SIM Break Flag Control Register (SBFCR)
Interrupt Status Register 1 (INT1)
Interrupt Status Register 2 (INT2)
Interrupt Status Register 3 (INT3)
Reserved
Reserved
Reserved
Reserved
Reserved
Break Address Register High (BRKH)
Break Address Register Low (BRKL)
Break Status and Control Register (BRKSCR)
LVI Status Register (LVISR)
$FE10
↓
$FFCF
Monitor ROM 2
448 Bytes
$FFD0
↓
$FFFF
ROM Vectors
48 Bytes
Figure 5. MC68HC08LJ12 Memory Map
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HC908LJ12AD/D
Electrical
Specifications
Electrical specifications for the MC68HC908LJ12 apply to the MC68HC08LJ12
except for the parameters indicated below.
Functional Operating
Range
Table 9. Operating Range
Characteristic
Symbol
TA
Value
Unit
°C
Operating temperature range
Operating voltage range
– 40 to +85
5.0V ± 10%
VDD
V
RAM Memory
Characteristics
Table 10. Memory Characteristics
Characteristic
Symbol
Min.
Max.
Unit
RAM data retention voltage
Notes:
VRDR
1.3
—
V
Since MC68HC08LJ12 is a ROM device, FLASH memory electrical characteristics do not apply.
MC68HC08LJ12
Order Numbers
These part numbers are generic numbers only. To place an order, ROM code
must be submitted to the ROM Processing Center (RPC).
Table 11. MC68HC08LJ12 Order Numbers
Operating
MC Order Number
Package
Temperature Range
–40 °C to +85 °C
–40 °C to +85 °C
–40 °C to +85 °C
MC68HC08LJ12CFB
MC68HC08LJ12CPB
MC68HC08LJ12CFU
52-pin LQFP
64-pin LQFP
64-pin QFP
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AMENDMENTS TO MC68HC908LJ12/D, REV. 2
AMENDMENTS TO MC68HC908LJ12/D, REV. 2
5.0V DC Electrical
Characteristics
Pages 394 and 395, Table 23-4 5.0V DC Electrical Characteristics —
Delete LVI typical values and correct note 6.
From:
Characteristic
Symbol
Min
4.00
4.00
Typ
4.32
4.32
Max
4.70
4.70
Unit
V
VTRIPF
Low-voltage inhibit, trip falling voltage
Low-voltage inhibit, trip rising voltage
VTRIPR
V
Notes:
6. LCD driver configured for high current mode.
To:
Characteristic
Symbol
Min
4.00
4.00
Typ
—
Max
4.70
4.70
Unit
V
VTRIPF
Low-voltage inhibit, trip falling voltage
Low-voltage inhibit, trip rising voltage
VTRIPR
—
V
Notes:
6. LCD driver configured for low current mode.
3.3V DC Electrical
Characteristics
Pages 396 and 397, Table 23-5 3.3V DC Electrical Characteristics —
Delete LVI typical values and correct note 6.
From:
Characteristic
Symbol
Min
2.40
2.46
Typ
2.57
2.63
Max
2.88
2.97
Unit
V
VTRIPF
Low-voltage inhibit, trip falling voltage
Low-voltage inhibit, trip rising voltage
VTRIPR
V
Notes:
6. LCD driver configured for high current mode.
To:
Characteristic
Symbol
Min
2.40
2.46
Typ
—
Max
2.88
2.97
Unit
V
VTRIPF
Low-voltage inhibit, trip falling voltage
Low-voltage inhibit, trip rising voltage
VTRIPR
—
V
Notes:
6. LCD driver configured for low current mode.
Addendum to MC68HC908LJ12 Technical Data
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Oscillator
Characteristics
Page 398, Table 23-8 5.0V Oscillator Specifications and Table 23-9 3.3V
Oscillator Specifications — Replace Internal oscillator clock frequency
values.
From:
Characteristic
Symbol
Min
Typ
Max
Unit
fICLK
Internal oscillator clock frequency
46k
47k
48k
Hz
Characteristic
Symbol
Min
Typ
Max
Unit
fICLK
Internal oscillator clock frequency
42.8k
43.4k
44k
Hz
To:
See Figure 1 . Typical Internal Oscillator Frequency on page 6 of this
document.
— END —
Addendum to MC68HC908LJ12 Technical Data
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— END —
Addendum to MC68HC908LJ12 Technical Data
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