MC912D60CVPV8_技术文档

MC68HC912D60A

MC68HC912D60C

MC68HC912D60P

Technical Data — Rev. 3.1

Freescale reserves the right to make changes without further notice to any products

herein. Freescale makes no warranty, representation or guarantee regarding the

suitability of its products for any particular purpose, nor does Freescale assume any

liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation consequential or incidental

damages. "Typical" parameters which may be provided in Freescale data sheets

and/or specifications can and do vary in different applications and actual performance

may vary over time. All operating parameters, including "Typicals" must be validated

for each customer application by customer's technical experts. Freescale does not

convey any license under its patent rights nor the rights of others. Freescale products

are not designed, intended, or authorized for use as components in systems intended

for surgical implant into the body, or other applications intended to support or sustain

life, or for any other application in which the failure of the Freescale product could

create a situation where personal injury or death may occur. Should Buyer purchase or

use Freescale products for any such unintended or unauthorized application, Buyer

shall indemnify and hold Freescale and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and

reasonable attorney fees arising out of, directly or indirectly, any claim of personal

injury or death associated with such unintended or unauthorized use, even if such claim

alleges that Freescale was negligent regarding the design or manufacture of the part.

Freescale, Inc. is an Equal Opportunity/Affirmative Action Employer.

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

3

Technical Data

4

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data — MC68HC912D60A

List of Paragraphs

List of Paragraphs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

List of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Section 1. General Description . . . . . . . . . . . . . . . . . . . .23

Section 2. Central Processing Unit . . . . . . . . . . . . . . . . .31

Section 3. Pinout and Signal Descriptions. . . . . . . . . . .37

Section 4. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Section 5. Operating Modes and Resource Mapping . .71

Section 6. Bus Control and Input/Output . . . . . . . . . . . .85

Section 7. Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . .97

Section 8. EEPROM Memory . . . . . . . . . . . . . . . . . . . . .105

Section 9. Resets and Interrupts . . . . . . . . . . . . . . . . . .119

Section 10. I/O Ports with Key Wake-up . . . . . . . . . . . .129

Section 11. Clock Functions . . . . . . . . . . . . . . . . . . . . .137

Section 12. Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . .175

Section 13. Pulse Width Modulator . . . . . . . . . . . . . . . .207

Section 14. Enhanced Capture Timer . . . . . . . . . . . . . .223

Section 15. Multiple Serial Interface . . . . . . . . . . . . . . .263

Section 16. Freescale Interconnect Bus . . . . . . . . . . . .289

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

5

List of Paragraphs

Section 17. MSCAN Controller. . . . . . . . . . . . . . . . . . . .303

Section 18. Analog-to-Digital Converter . . . . . . . . . . . .349

Section 19. Development Support. . . . . . . . . . . . . . . . .377

Section 20. Electrical Specifications. . . . . . . . . . . . . . .405

Section 21. Appendix: CGM Practical Aspects . . . . . .427

Section 22. Appendix: Changes from MC68HC912D60437

Section 23. Appendix: Information on MC68HC912D60A

Mask Set Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .443

Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .447

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .457

Technical Data

6

MC68HC912D60A — Rev. 3.1

List of Paragraphs

Freescale Semiconductor

Technical Data — MC68HC912D60A

Table of Contents

Technical Data — List of Paragraphs

Technical Data — Table of Contents

Technical Data — List of Figures

Technical Data — List of Tables

Section 1. General Description

1.1

1.2

1.3

1.4

1.5

1.6

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Devices Covered in this Document. . . . . . . . . . . . . . . . . . . . . .24

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Section 2. Central Processing Unit

2.1

2.2

2.3

2.4

2.5

2.6

2.7

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Indexed Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Opcodes and Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

Table of Contents

7

Table of Contents

Section 3. Pinout and Signal Descriptions

3.1

3.2

3.3

3.4

3.5

3.6

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

MC68HC912D60A Pin Assignments in 112-pin QFP. . . . . . . .38

MC68HC912D60A Pin Assignments in 80-pin QFP. . . . . . . . .40

Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Section 4. Registers

4.1

4.2

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Register Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Section 5. Operating Modes and Resource Mapping

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Background Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Internal Resource Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Memory Maps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

5.1

5.2

5.3

5.4

5.5

5.6

Section 6. Bus Control and Input/Output

6.1

6.2

6.3

6.4

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Detecting Access Type from External Signals . . . . . . . . . . . . .85

Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Section 7. Flash Memory

7.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

Technical Data

8

MC68HC912D60A — Rev. 3.1

Table of Contents

Freescale Semiconductor

Table of Contents

7.2

7.3

7.4

7.5

7.6

7.7

7.8

7.9

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

Flash EEPROM Control Block . . . . . . . . . . . . . . . . . . . . . . . . .98

Flash EEPROM Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

Flash EEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

Programming the Flash EEPROM . . . . . . . . . . . . . . . . . . . . .101

Erasing the Flash EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . .103

7.10 Stop or Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

7.11 Flash protection bit FPOPEN . . . . . . . . . . . . . . . . . . . . . . . . .104

Section 8. EEPROM Memory

8.1

8.2

8.3

8.4

8.5

8.6

8.7

8.8

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

EEPROM Selective Write More Zeros . . . . . . . . . . . . . . . . . .106

EEPROM Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . .107

EEPROM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . .108

Program/Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .115

Shadow Word Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

Programming EEDIVH and EEDIVL Registers. . . . . . . . . . . .116

Section 9. Resets and Interrupts

9.1

9.2

9.3

9.4

9.5

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

Maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120

Latching of Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

Interrupt Control and Priority Registers . . . . . . . . . . . . . . . . .123

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

Table of Contents

9

Table of Contents

9.6

9.7

9.8

9.9

Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124

Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

Register Stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

Customer Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

Section 10. I/O Ports with Key Wake-up

10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

10.3 Key Wake-up and Port Registers . . . . . . . . . . . . . . . . . . . . . .130

10.4 Key Wake-Up Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

Section 11. Clock Functions

11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

11.3 Clock Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138

11.4 Phase-Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . .139

11.5 Acquisition and Tracking Modes. . . . . . . . . . . . . . . . . . . . . . .141

11.6 Limp-Home and Fast STOP Recovery modes . . . . . . . . . . . .143

11.7 System Clock Frequency formulas. . . . . . . . . . . . . . . . . . . . .162

11.8 Clock Divider Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162

11.9 Computer Operating Properly (COP) . . . . . . . . . . . . . . . . . . .166

11.10 Real-Time Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167

11.11 Clock Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167

11.12 Clock Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .168

Section 12. Oscillator

12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

Technical Data

10

MC68HC912D60A — Rev. 3.1

Table of Contents

Freescale Semiconductor

Table of Contents

12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

12.3 MC68HC912D60A Oscillator Specification. . . . . . . . . . . . . . .176

12.4 MC68HC912D60C Colpitts Oscillator Specification . . . . . . . .179

12.5 MC68HC912D60P Pierce Oscillator Specification . . . . . . . . .194

Section 13. Pulse Width Modulator

13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

13.3 PWM Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . .210

13.4 PWM Boundary Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222

Section 14. Enhanced Capture Timer

14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223

14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223

14.3 Enhanced Capture Timer Modes of Operation. . . . . . . . . . . .230

14.4 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233

14.5 Timer and Modulus Counter Operation in Different Modes . .261

Section 15. Multiple Serial Interface

15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263

15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263

15.3 Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264

15.4 Serial Communication Interface (SCI) . . . . . . . . . . . . . . . . . .264

15.5 Serial Peripheral Interface (SPI). . . . . . . . . . . . . . . . . . . . . . .276

15.6 Port S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285

Section 16. Freescale Interconnect Bus

16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

11

Table of Contents

16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289

16.3 Push-pull sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290

16.4 Biphase coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291

16.5 Message validation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292

16.6 Interfacing to MI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294

16.7 MI Bus clock rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296

16.8 SCI0/MI Bus registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296

Section 17. MSCAN Controller

17.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303

17.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303

17.3 External Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304

17.4 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305

17.5 Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . .310

17.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314

17.7 Protocol Violation Protection. . . . . . . . . . . . . . . . . . . . . . . . . .316

17.8 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316

17.9 Timer Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320

17.10 Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321

17.11 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .324

17.12 Programmer’s Model of Message Storage . . . . . . . . . . . . . . .325

17.13 Programmer’s Model of Control Registers . . . . . . . . . . . . . . .330

Section 18. Analog-to-Digital Converter

18.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349

18.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349

18.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351

Technical Data

12

MC68HC912D60A — Rev. 3.1

Table of Contents

Freescale Semiconductor

Table of Contents

18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352

18.5 ATD Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354

18.6 ATD Operation In Different MCU Modes . . . . . . . . . . . . . . . .355

18.7 General Purpose Digital Input Port Operation . . . . . . . . . . . .357

18.8 Application Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . .358

18.9 ATD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358

Section 19. Development Support

19.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377

19.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377

19.3 Instruction Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377

19.4 Background Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .379

19.5 Breakpoints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395

19.6 Instruction Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .402

Section 20. Electrical Specifications

20.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405

20.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405

20.3 Tables of Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .406

Section 21. Appendix: CGM Practical Aspects

21.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .427

21.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .427

21.3 Practical Aspects For The PLL Usage . . . . . . . . . . . . . . . . . .427

21.4 Printed Circuit Board Guidelines. . . . . . . . . . . . . . . . . . . . . . .433

Section 22. Appendix: Changes from MC68HC912D60

22.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .437

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

13

Table of Contents

22.2 Significant changes from the MC68HC912D60

(non-suffix device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .437

Section 23. Appendix: Information on MC68HC912D60A

Mask Set Changes

23.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .443

23.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .443

23.3 Flash Protection Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . .443

23.4 Clock Circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .444

23.5 Pseudo Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .444

23.6 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .444

23.7 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .445

Technical Data — Glossary

Technical Data — Revision History

23.8 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .457

23.9 Changes from Rev 2.0 to Rev 3.0 . . . . . . . . . . . . . . . . . . . . .457

23.10 Major Changes From Rev 1.0 to Rev 2.0 . . . . . . . . . . . . . . . .457

23.11 Major Changes From Rev 0.0 to Rev 1.0 . . . . . . . . . . . . . . . .458

Technical Data

14

MC68HC912D60A — Rev. 3.1

Table of Contents

Freescale Semiconductor

Technical Data — MC68HC912D60A

List of Figures

Figure

Title

Page

1-1

1-2

2-1

3-1

3-2

3-3

3-4

3-5

3-6

5-1

6-1

MC68HC912D60A 112-pin QFP Block Diagram . . . . . . . . . . .29

MC68HC912D60A 80-pin QFP Block Diagram . . . . . . . . . . . .30

Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Pin Assignments in 112-pin TQFP for MC68HC912D60A . . . .38

112-pin TQFP Mechanical Dimensions (case no987) . . . . . . .39

Pin Assignments in 80-pin QFP for MC68HC912D60A . . . . . .40

80-pin QFP Mechanical Dimensions (case no841B) . . . . . . . .41

PLL Loop FIlter Connections . . . . . . . . . . . . . . . . . . . . . . . . . .43

External Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . .45

MC68HC912D60A Memory Map . . . . . . . . . . . . . . . . . . . . . . .83

Access Type vsBus Control Pins . . . . . . . . . . . . . . . . . . . . . . .86

10-1 STOP Key Wake-up Filter (falling edge trigger) timing. . . . . .135

11-1 Internal Clock Relationships . . . . . . . . . . . . . . . . . . . . . . . . . .139

11-2 PLL Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140

11-3 Clock Loss during Normal Operation . . . . . . . . . . . . . . . . . . .144

11-4 No Clock at Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . .146

11-5 STOP Exit and Fast STOP Recovery. . . . . . . . . . . . . . . . . . .149

11-6 Clock Generation Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163

11-7 Clock Chain for SCI0, SCI1, RTI, COP. . . . . . . . . . . . . . . . . .164

11-8 Clock Chain for ECT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165

11-9 Clock Chain for MSCAN, SPI, ATD0, ATD1 and BDM. . . . . .166

12-1 MC68HC912D60A Colpitts Oscillator Architecture. . . . . . . . .177

12-2 MC68HC912D60C Colpitts Oscillator Architecture. . . . . . . . .180

12-3 MC68HC912D60C Crystal with DC Blocking Capacitor. . . . .192

12-4 MC68HC912D60P Pierce Oscillator Architecture. . . . . . . . . .195

13-1 Block Diagram of PWM Left-Aligned Output Channel . . . . . .208

13-2 Block Diagram of PWM Center-Aligned Output Channel . . . .209

13-3 PWM Clock Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210

14-1 Timer Block Diagram in Latch Mode. . . . . . . . . . . . . . . . . . . .225

14-2 Timer Block Diagram in Queue Mode. . . . . . . . . . . . . . . . . . .226

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

15

List of Figures

14-3 8-Bit Pulse Accumulators Block Diagram . . . . . . . . . . . . . . . .227

14-4 16-Bit Pulse Accumulators Block Diagram . . . . . . . . . . . . . . .228

14-5 Block Diagram for Port7 with Output compare /

Pulse Accumulator A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229

14-6 C3F-C0F Interrupt Flag Setting . . . . . . . . . . . . . . . . . . . . . . .229

15-1 Multiple Serial Interface Block Diagram . . . . . . . . . . . . . . . . .264

15-2 Serial Communications Interface Block Diagram . . . . . . . . . .265

15-3 Serial Peripheral Interface Block Diagram . . . . . . . . . . . . . . .277

15-4 SPI Clock Format 0 (CPHA = 0). . . . . . . . . . . . . . . . . . . . . . .278

15-5 SPI Clock Format 1 (CPHA = 1). . . . . . . . . . . . . . . . . . . . . . .279

15-6 Normal Mode and Bidirectional Mode. . . . . . . . . . . . . . . . . . .280

16-1 MI Bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290

16-2 Biphase coding and error detection . . . . . . . . . . . . . . . . . . . .292

16-3 MI BUS Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293

16-4 A typical MI Bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .295

17-1 The CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305

17-2 User Model for Message Buffer Organization. . . . . . . . . . . . .308

17-3 32-bit Maskable Identifier Acceptance Filters. . . . . . . . . . . . .312

17-4 16-bit Maskable Acceptance Filters . . . . . . . . . . . . . . . . . . . .312

17-5 8-bit Maskable Acceptance Filters . . . . . . . . . . . . . . . . . . . . .313

17-6 SLEEP Request / Acknowledge Cycle . . . . . . . . . . . . . . . . . .319

17-7 Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321

17-8 Segments within the Bit Time . . . . . . . . . . . . . . . . . . . . . . . . .323

17-9 msCAN12 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . .324

17-10 Message Buffer Organization . . . . . . . . . . . . . . . . . . . . . . . . .325

17-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326

17-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327

18-1 Analog-to-Digital Converter Block Diagram . . . . . . . . . . . . . .350

19-1 BDM Host to Target Serial Bit Timing. . . . . . . . . . . . . . . . . . .381

19-2 BDM Target to Host Serial Bit Timing (Logic 1) . . . . . . . . . . .381

19-3 BDM Target to Host Serial Bit Timing (Logic 0) . . . . . . . . . . .382

20-1 Timer Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .414

20-2 POR and External Reset Timing Diagram . . . . . . . . . . . . . . .415

20-3 STOP Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . .416

20-4 WAIT Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . .417

20-5 Interrupt Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .418

20-6 Port Read Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .419

20-7 Port Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .419

Technical Data

16

MC68HC912D60A — Rev. 3.1

List of Figures

Freescale Semiconductor

List of Figures

20-8 Multiplexed Expansion Bus Timing Diagram . . . . . . . . . . . . .421

20-9 SPI Timing Diagram (1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . .423

20-10 SPI Timing Diagram (2 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . .424

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

17

List of Figures

Technical Data

18

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

List of Figures

Technical Data — MC68HC912D60A

List of Tables

Table

Title

Page

1-1

1-2

2-1

2-2

3-1

3-2

3-3

3-4

4-1

5-1

5-2

5-3

5-4

8-1

8-2

8-3

8-4

9-1

9-2

Device Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . .27

Development Tools Ordering Information. . . . . . . . . . . . . . . . .28

M68HC12 Addressing Mode Summary . . . . . . . . . . . . . . . . . .34

Summary of Indexed Operations . . . . . . . . . . . . . . . . . . . . . . .35

MC68HC912D60A Power and Ground Connection Summary .44

MC68HC912D60A Signal Description Summary . . . . . . . . . . .50

MC68HC912D60A Port Description Summary. . . . . . . . . . . . .59

Port Pull-Up, Pull-Down and Reduced Drive Summary . . . . . .60

MC68HC912D60A Register Map . . . . . . . . . . . . . . . . . . . . . . .62

Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Mapping Precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

RFSTR Stretch Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . .82

EXSTR Stretch Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . .82

EEDIV Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

1K byte EEPROM Block Protection . . . . . . . . . . . . . . . . . . . .112

Erase Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

Shadow word mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

Interrupt Vector Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122

Stacking Order on Entry to Interrupts . . . . . . . . . . . . . . . . . . .128

11-1 Summary of STOP Mode Exit Conditions. . . . . . . . . . . . . . . .155

11-2 Summary of Pseudo STOP Mode Exit Conditions . . . . . . . . .155

11-3 Clock Monitor Time-Outs . . . . . . . . . . . . . . . . . . . . . . . . . . . .167

11-4 Real Time Interrupt Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . .169

11-5 COP Watchdog Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172

13-1 Clock A and Clock B Prescaler. . . . . . . . . . . . . . . . . . . . . . . .212

13-2 PWM Left-Aligned Boundary Conditions . . . . . . . . . . . . . . . .222

13-3 PWM Center-Aligned Boundary Conditions . . . . . . . . . . . . . .222

14-1 Compare Result Output Action. . . . . . . . . . . . . . . . . . . . . . . .238

14-2 Edge Detector Circuit Configuration . . . . . . . . . . . . . . . . . . . .238

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

19

List of Tables

14-3 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240

15-1 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266

15-2 Loop Mode Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269

15-3 SS Output Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279

15-4 SPI Clock Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . .283

16-1 MI Bus Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301

17-1 msCAN12 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . .315

17-2 msCAN12 vsCPU operating modes . . . . . . . . . . . . . . . . . . . .317

17-3 CAN Standard Compliant Bit Time Segment Settings . . . . . .323

17-4 Data length codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .328

17-5 Synchronization jump width . . . . . . . . . . . . . . . . . . . . . . . . . .333

17-6 Baud rate prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333

17-7 Time segment syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334

17-8 Time segment values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335

17-9 Identifier Acceptance Mode Settings . . . . . . . . . . . . . . . . . . .341

17-10 Identifier Acceptance Hit Indication . . . . . . . . . . . . . . . . . . . .342

18-1 Result Data Formats Available . . . . . . . . . . . . . . . . . . . . . . . .361

18-2 Left Justified ATD Output Codes . . . . . . . . . . . . . . . . . . . . . .362

18-3 ATD Response to Background Debug Enable . . . . . . . . . . . .364

18-4 Final Sample Time Selection . . . . . . . . . . . . . . . . . . . . . . . . .365

18-5 Clock Prescaler Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .366

18-6 Conversion Sequence Length Coding . . . . . . . . . . . . . . . . . .367

18-7 Result Register Assignment for Different Conversion

Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .367

18-8 Special Channel Conversion Select Coding. . . . . . . . . . . . . .368

18-9 Analog Input Channel Select Coding . . . . . . . . . . . . . . . . . . .369

18-10 Multichannel Mode Result Register Assignment (MULT=1). .370

19-1 IPIPE Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .378

19-2 Hardware Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .384

19-3 BDM Firmware Commands . . . . . . . . . . . . . . . . . . . . . . . . . .385

19-4 BDM registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387

19-5 TTAGO Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .392

19-6 TTAGO Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .392

19-7 Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .392

19-8 REGN Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .392

19-9 Breakpoint Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . .398

19-10 Breakpoint Address Range Control . . . . . . . . . . . . . . . . . . . .399

19-11 Breakpoint Read/Write Control. . . . . . . . . . . . . . . . . . . . . . . .401

Technical Data

20

MC68HC912D60A — Rev. 3.1

List of Tables

Freescale Semiconductor

List of Tables

19-12 Tag Pin Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .403

20-1 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .406

20-2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .407

20-3 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .408

20-4 Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .409

20-5 ATD DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . .409

20-6 Analog Converter Characteristics (Operating) . . . . . . . . . . . .410

20-7 ATD AC Characteristics (Operating). . . . . . . . . . . . . . . . . . . .410

20-8 ATD Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .411

20-9 EEPROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .411

20-10 Flash EEPROM Characteristics . . . . . . . . . . . . . . . . . . . . . . .412

20-11 Pulse Width Modulator Characteristics. . . . . . . . . . . . . . . . . .412

20-12 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .413

20-13 Peripheral Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .419

20-14 Multiplexed Expansion Bus Timing. . . . . . . . . . . . . . . . . . . . .420

20-15 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .422

20-16 CGM Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .425

20-17 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .425

20-18 Key Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .426

20-19 msCAN12 Wake-up Time from Sleep Mode. . . . . . . . . . . . . .426

21-1 Suggested 8MHz Synthesis PLL Filter Elements

(Tracking Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .431

21-2 Suggested 8MHz Synthesis PLL Filter Elements

(Acquisition Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .432

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

21

List of Tables

Technical Data

22

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

List of Tables

Technical Data — MC68HC912D60A

Section 1. General Description

1.1 Contents

1.2

1.3

1.4

1.5

1.6

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Devices Covered in this Document. . . . . . . . . . . . . . . . . . . . . .24

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

1.2 Introduction

The MC68HC912D60A microcontroller unit (MCU) is a 16-bit device

available in two package options, 80-pin QFP and 112-pin TQFP. On-

chip peripherals include a 16-bit central processing unit (CPU12), 60K

bytes of flash EEPROM, 2K bytes of RAM, 1K bytes of EEPROM, two

asynchronous serial communication interfaces (SCI), a serial peripheral

interface (SPI), an enhanced capture timer (ECT), two (one on 80QFP)

8-channel,10-bit analog-to-digital converters (ATD), a four-channel

pulse-width modulator (PWM), and a CAN 2.0 A, B software compatible

module (MSCAN12). System resource mapping, clock generation,

interrupt control and bus interfacing are managed by the lite integration

module (LIM). The MC68HC912D60A has full 16-bit data paths

throughout, however, the external bus can operate in an 8-bit narrow

mode so single 8-bit wide memory can be interfaced for lower cost

systems. The inclusion of a PLL circuit allows power consumption and

performance to be adjusted to suit operational requirements. In addition

to the I/O ports available in each module, 16 (2 on 80QFP) I/O port pins

are available with Key-Wake-Up capability from STOP or WAIT mode.

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

23

General Description

1.3 Devices Covered in this Document

The MC68HC912D60C and MC68HC912D60P are devices similar to

the MC68HC912D60A, but with different oscillator configurations. Refer

to Section 12. Oscillator for more details.

The generic term MC68HC912D60A is used throughout this document

to mean all derivatives mentioned above, except in Section 12.

Oscillator, where it refers only to the MC68HC912D60A device.

1.4 Features

• 16-bit CPU12

– Upward compatible with M68HC11 instruction set

– Interrupt stacking and programmer’s model identical to

M68HC11

– 20-bit ALU

– Instruction queue

– Enhanced indexed addressing

• Multiplexed bus

– Single chip or expanded

– 16 address/16 data wide or 16 address/8 data narrow mode

• Two 8-bit ports with key wake-up interrupt (2 pins only are

2

available on 80QFP) and one I C start bit detector (112TQFP

only)

• Memory

– 60K byte flash EEPROM, made of a 28K module and a 32K

module with 8K bytes protected BOOT section in each module

(MC68HC912D60A)

– 1K byte EEPROM

– 2K byte RAM

Technical Data

24

MC68HC912D60A — Rev. 3.1

General Description

Freescale Semiconductor

General Description

Features

• Analog-to-digital converters

– 2 x 8-channels, 10-bit resolution in 112TQFP

– 1 x 8-channels, 8-bit resolution in 80QFP

• 1M bit per second, CAN 2.0 A, B software compatible module

– Two receive and three transmit buffers

– Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or

8 x 8 bit

– Four separate interrupt channels for Rx, Tx, error and wake-up

– Low-pass filter wake-up function

– In 80QFP, only TxCAN and RxCAN pins are available

– Loop-back for self test operation

– Programmable link to a timer input capture channel, for time-

stamping and network synchronization.

• Enhanced capture timer (ECT)

– 16-bit main counter with 7-bit prescaler

– 8 programmable input capture or output compare channels; 4

of the 8 input captures with buffer

– Input capture filters and buffers, three successive captures on

four channels, or two captures on four channels with a

capture/compare selectable on the remaining four

– Four 8-bit or two 16-bit pulse accumulators

– 16-bit modulus down-counter with 4-bit prescaler

– Four user-selectable delay counters for signal filtering

• 4 PWM channels with programmable period and duty cycle

– 8-bit 4-channel or 16-bit 2-channel

– Separate control for each pulse width and duty cycle

– Center- or left-aligned outputs

– Programmable clock select logic with a wide range of

frequencies

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

General Description

25

General Description

• Serial interfaces

– Two asynchronous serial communications interfaces (SCI)

– MI-Bus implemented on final devices

– Synchronous serial peripheral interface (SPI)

• LIM (light integration module)

– WCR (windowed COP watchdog, real time interrupt, clock

monitor)

– ROC (reset and clocks)

– MEBI (multiplexed external bus interface)

– MBI (internal bus interface and map)

– INT (interrupt control)

• Clock generation

– Phase-locked loop clock frequency multiplier

– Limp home mode in absence of external clock

– Slow mode divider

– Low power 0.5 to 16 MHz crystal oscillator reference clock

– Option of a Pierce or Colpitts oscillator

• 112-Pin TQFP package or 80-pin QFP package

– Up to 68 general-purpose I/O lines, plus up to 18 input-only

lines in 112TQFP

or

Up to 48 general-purpose I/O lines, plus up to 10 input-only

lines in 80QFP

• 8MHz operation at 5V

• Development support

– Single-wire background debug™ mode (BDM)

– On-chip hardware breakpoints

Technical Data

26

MC68HC912D60A — Rev. 3.1

General Description

Freescale Semiconductor

General Description

Ordering Information

1.5 Ordering Information

Table 1-1. Device Ordering Information

Ambient Temperature

Package

Order Number

Range

Designator

–40 to +85°C

–40 to +105°C

–40 to +125°C

–40 to +85°C

–40 to +105°C

–40 to +125°C

–40 to +85°C

–40 to +105°C

–40 to +125°C

–40 to +85°C

–40 to +105°C

–40 to +125°C

–40 to +85°C

–40 to +105°C

–40 to +125°C

–40 to +85°C

–40 to +105°C

–40 to +125°C

C

V

MC912D60ACPV8

MC912D60AVPV8

MC912D60AMPV8

MC912D60ACFU8

MC912D60AVFU8

MC912D60AMFU8

MC912D60CCPV8

MC912D60CVPV8

MC912D60CMPV8

MC912D60CCFU8

MC912D60CVFU8

MC912D60CMFU8

MC912D60PCPV8

MC912D60PVPV8

MC912D60PMPV8

MC912D60PCFU8

MC912D60PVFU8

MC912D60PMFU8

112-Pin TQFP

Single Tray

60 Pcs

M*

C

80-Pin TQFP

Single Tray

84 Pcs

V

M*

C

112-Pin TQFP

Single Tray

60 Pcs

V

M*

C

80-Pin TQFP

Single Tray

84 Pcs

V

M*

C

112-Pin TQFP

Single Tray

60 Pcs

V

M*

C

80-Pin TQFP

Single Tray

84 Pcs

V

M*

* Important: M temperature operation is available only for single chip

modes

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

27

General Description

Table 1-2. Development Tools Ordering Information

Description

Name

Order Number

Free from World Wide Web

MCUez

M68SDIL (3–5V), M68DIL12 (SDIL + MCUez +

SDBUG12)

Serial Debug Interface

Evaluation board

SDI

M68EVB912D60 (EVB only)

M68KIT912D60 (EVB + SDIL12)

EVB

NOTE: SDBUG12 is a P & E Micro Product. It can be obtained from P & E from

their web site (http://www.pemicro.com) for approximately $100.

Third party tools: http://www.mcu.motsps.com/dev_tools/3rd/index.html

Technical Data

28

MC68HC912D60A — Rev. 3.1

General Description

Freescale Semiconductor

General Description

Block Diagrams

1.6 Block Diagrams

VRH0

VRL0

VDDAD

VSSAD

VRH0

VRL0

VRH1

VRL1

VDDAD

VSSAD

VRH1

ATD0

ATD1

VRL1

60K byte flash EEPROM

VDDAD

VSSAD

2K byte RAM

AN00

AN01

AN02

AN03

AN04

AN05

AN06

AN07

PAD00 AN10

PAD01 AN11

PAD02 AN12

PAD03 AN13

PAD04 AN14

PAD05 AN15

PAD06 AN16

PAD07 AN17

PAD10

PAD11

PAD12

PAD13

PAD14

PAD15

PAD16

PAD17

1K byte EEPROM

CPU12

Periodic interrupt

Single-wire

background

debug module

IOC0

PT0

COP watchdog

Clock monitor

Breakpoints

BKGD

IOC1

IOC2

IOC3

IOC4

IOC5

IOC6

IOC7

PT1

PT2

PT3

PT4

PT5

PT6

PT7

Enhanced

capture

timer

XFC

VDDPLL

VSSPLL

PLL

RxD0

TxD0

RxD1

TxD1

PS0

PS1

PS2

PS3

SCI0 (MI BUS)

SCI1

Lite

integration

module

(LIM)

EXTAL

XTAL

RESET

SISO/MISO

MOMI/MOSI

SCK

PS4

PS5

PS6

PS7

SPI

SS

PE0

PE1

PE2

PE3

PE4

PE5

PE6

PE7

XIRQ

IRQ

R/W

PW0

PW1

PW2

PW3

PP0

PP1

PP2

PP3

LSTRB/TAGLO

ECLK

PWM

MODA/IPIPE0

MODB/IPIPE1/CGMTST

DBE/CAL/ECLK

PP4

PP5

PP6

PP7

I/O

PCAN7

PCAN6

PCAN5

PCAN4

PCAN3

PCAN2

Multiplexed Address/Data Bus

I/O

DDRA

DDRB

TxCAN PCAN1

RxCANPCAN0

PORT A

PORT B

CAN

PG7

KWG6

KWG5

KWG4

KWG3

KWG2

KWG1

KWG0

PGUPD

PG7

PG6

PG5

PG4

PG3

PG2

PG1

PG0

PGUPD

VDD ×2

VSS ×2

Power for internal circuitry

Wide

bus

KWH7

KWH6

KWH5

KWH4

KWH3

KWH2

KWH1

KWH0

PHUPD

PH7

PH6

PH5

PH4

PH3

PH2

PH1

PH0

PHUPD

VDDX ×2

VSSX ×2

Power for I/O drivers

Narrow bus

Figure 1-1. MC68HC912D60A 112-pin QFP Block Diagram

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

29

General Description

VRH1

VRL1

VDDAD

VSSAD

VRH0

VRL0

VDDAD

VSSAD

VRH0

ATD1

ATD0

VRL0

60K byte flash EEPROM

VDDAD

VSSAD

2K byte RAM

AN10

AN11

AN12

AN13

AN14

AN15

AN16

AN17

AN00

AN01

AN02

AN03

AN04

AN05

AN06

AN07

PAD00

PAD01

PAD02

PAD03

PAD04

PAD05

PAD06

PAD07

1K byte EEPROM

CPU12

Periodic interrupt

Single-wire

background

debug module

IOC0

PT0

PT1

PT2

PT3

PT4

PT5

PT6

PT7

COP watchdog

Clock monitor

Breakpoints

BKGD

IOC1

IOC2

IOC3

IOC4

IOC5

IOC6

IOC7

Enhanced

capture

timer

XFC

VDDPLL

VSSPLL

PLL

RxD0

TxD0

RxD1

TxD1

PS0

PS1

PS2

PS3

SCI0 (MI BUS)

SCI1

Lite

EXTAL

XTAL

integration

module

(LIM)

RESET

SISO/MISO

MOMI/MOSI

SCK

PS4

PS5

PS6

PS7

SPI

SS

PE0

PE1

PE2

PE3

PE4

PE5

PE6

PE7

XIRQ

IRQ

R/W

PW0

PW1

PW2

PW3

PP0

PP1

PP2

PP3

LSTRB/TAGLO

ECLK

PWM

MODA/IPIPE0

MODB/IPIPE1/CGMTST

DBE/CAL/ECLK

PP4

PP5

PP6

PP7

I/O

PCAN7

PCAN6

PCAN5

PCAN4

PCAN3

PCAN2

Multiplexed Address/Data Bus

DDRA

DDRB

TxCAN PCAN1

RxCANPCAN0

PORT A

PORT B

CAN

PG7

KWG6

KWG5

KWG4

PG4

PH4

KWG3

VDD ×2

VSS ×2

KWG2

KWG1

KWG0

PGUPD(VDD)

Wide

bus

Power for internal circuitry

KWH7

KWH6

VDDX ×2

VSSX ×2

KWH5

KWH4

KWH3

KWH2

Power for I/O drivers

Narrow bus

KWH1

KWH0

PHUPD(VSS)

Note:

Several I/O on ports G, H and CAN are unavailable externally on the 80-pin QFP package. These in-

ternal pins should either be defined as outputs or have their pull-ups/downs enabled.

Figure 1-2. MC68HC912D60A 80-pin QFP Block Diagram

Technical Data

30

MC68HC912D60A — Rev. 3.1

General Description

Freescale Semiconductor

Technical Data — MC68HC912D60A

Section 2. Central Processing Unit

2.1 Contents

2.2

2.3

2.4

2.5

2.6

2.7

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Indexed Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Opcodes and Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

2.2 Introduction

The CPU12 is a high-speed, 16-bit processing unit. It has full 16-bit data

paths and wider internal registers (up to 20 bits) for high-speed extended

math instructions. The instruction set is a proper superset of the

M68HC11instruction set. The CPU12 allows instructions with odd byte

counts, including many single-byte instructions. This provides efficient

use of ROM space. An instruction queue buffers program information so

the CPU always has immediate access to at least three bytes of machine

code at the start of every instruction. The CPU12 also offers an

extensive set of indexed addressing capabilities.

2.3 Programming Model

CPU12 registers are an integral part of the CPU and are not addressed

as if they were memory locations.

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

31

Central Processing Unit

A

B

7

0 7

0

8-BIT ACCUMULATORS A & B

OR

16-BIT DOUBLE ACCUMULATOR D

15

D

15

IX

IY

0

INDEX REGISTER X

INDEX REGISTER Y

STACK POINTER

SP

PC

PROGRAM COUNTER

CONDITION CODE REGISTER

S X H

I N Z V C

Figure 2-1. Programming Model

Accumulators A and B are general-purpose 8-bit accumulators used to

hold operands and results of arithmetic calculations or data

manipulations. Some instructions treat the combination of these two 8-

bit accumulators as a 16-bit double accumulator (accumulator D).

Index registers X and Y are used for indexed addressing mode. In the

indexed addressing mode, the contents of a 16-bit index register are

added to 5-bit, 9-bit, or 16-bit constants or the content of an accumulator

to form the effective address of the operand to be used in the instruction.

Stack pointer (SP) points to the last stack location used. The CPU12

supports an automatic program stack that is used to save system

context during subroutine calls and interrupts, and can also be used for

temporary storage of data. The stack pointer can also be used in all

indexed addressing modes.

Program counter is a 16-bit register that holds the address of the next

instruction to be executed. The program counter can be used in all

indexed addressing modes except autoincrement/decrement.

Technical Data

32

MC68HC912D60A — Rev. 3.1

Central Processing Unit

Freescale Semiconductor

Central Processing Unit

Data Types

Condition Code Register (CCR) contains five status indicators, two

interrupt masking bits, and a STOP disable bit. The five flags are half

carry (H), negative (N), zero (Z), overflow (V), and carry/borrow (C). The

half-carry flag is used only for BCD arithmetic operations. The N, Z, V,

and C status bits allow for branching based on the results of a previous

operation.

After a reset, the CPU fetches a vector from the appropriate address and

begins executing instructions. The X and I interrupt mask bits are set to

mask any interrupt requests. The S bit is also set to inhibit the STOP

instruction.

2.4 Data Types

The CPU12 supports the following data types:

• Bit data

• 8-bit and 16-bit signed and unsigned integers

• 16-bit unsigned fractions

• 16-bit addresses

A byte is eight bits wide and can be accessed at any byte location. A

word is composed of two consecutive bytes with the most significant

byte at the lower value address. There are no special requirements for

alignment of instructions or operands.

2.5 Addressing Modes

Addressing modes determine how the CPU accesses memory locations

to be operated upon. The CPU12 includes all of the addressing modes

of the M68HC11 CPU as well as several new forms of indexed

addressing. Table 2-1 is a summary of the available addressing modes.

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

33

Central Processing Unit

Table 2-1. M68HC12 Addressing Mode Summary

Addressing Mode

Source Format

Abbreviation

Description

INST

Inherent

(no externally

INH

Operands (if any) are in CPU registers

supplied operands)

INST #opr8i

or

INST #opr16i

Operand is included in instruction stream

8- or 16-bit size implied by context

Immediate

IMM

Operand is the lower 8-bits of an address in

the range $0000 – $00FF

Direct

INST opr8a

DIR

Extended

INST opr16a

EXT

Operand is a 16-bit address

INST rel8

or

INST rel16

An 8-bit or 16-bit relative offset from the

current pc is supplied in the instruction

Relative

REL

Indexed

(5-bit offset)

5-bit signed constant offset from x, y, sp, or

pc

INST oprx5,xysp

INST oprx3,–xys

INST oprx3,+xys

INST oprx3,xys–

INST oprx3,xys+

INST abd,xysp

IDX

Indexed

(auto pre-decrement)

Auto pre-decrement x, y, or sp by 1 ~ 8

Auto pre-increment x, y, or sp by 1 ~ 8

Auto post-decrement x, y, or sp by 1 ~ 8

Auto post-increment x, y, or sp by 1 ~ 8

Indexed

(auto pre-increment)

Indexed

(auto post-decrement)

Indexed

(auto post-increment)

Indexed

(accumulator offset)

Indexed with 8-bit (A or B) or 16-bit (D)

accumulator offset from x, y, sp, or pc

9-bit signed constant offset from x, y, sp, or

Indexed

(9-bit offset)

INST oprx9,xysp

INST oprx16,xysp

INST [oprx16,xysp]

INST [D,xysp]

IDX1

IDX2

pc

(lower 8-bits of offset in one extension byte)

Indexed

(16-bit offset)

16-bit constant offset from x, y, sp, or pc

(16-bit offset in two extension bytes)

Pointer to operand is found at...

16-bit constant offset from x, y, sp, or pc

(16-bit offset in two extension bytes)

Indexed-Indirect

(16-bit offset)

[IDX2]

[D,IDX]

Indexed-Indirect

(D accumulator offset)

Pointer to operand is found at...

x, y, sp, or pc plus the value in D

Technical Data

34

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Central Processing Unit

Indexed Addressing Modes

2.6 Indexed Addressing Modes

The CPU12 indexed modes reduce execution time and eliminate code

size penalties for using the Y index register. CPU12 indexed addressing

uses a postbyte plus zero, one, or two extension bytes after the

instruction opcode. The postbyte and extensions do the following tasks:

• Specify which index register is used.

• Determine whether a value in an accumulator is used as an offset.

• Enable automatic pre- or post-increment or decrement

• Specify use of 5-bit, 9-bit, or 16-bit signed offsets.

Table 2-2. Summary of Indexed Operations

Source

Code

Syntax

Postbyte

Code (xb)

Comments

,r

5-bit constant offset n = –16 to +15

rr can specify X, Y, SP, or PC

rr0nnnnn

111rr0zs

n,r

–n,r

Constant offset (9- or 16-bit signed)

z-0 = 9-bit with sign in LSB of postbyte(s)

1 = 16-bit

if z = s = 1, 16-bit offset indexed-indirect (see below)

rr can specify X, Y, SP, or PC

n,r

–n,r

16-bit offset indexed-indirect

rr can specify X, Y, SP, or PC

111rr011

rr1pnnnn

[n,r]

Auto pre-decrement/increment or Auto post-

decrement/increment;

p = pre-(0) or post-(1), n = –8 to –1, +1 to +8

rr can specify X, Y, or SP (PC not a valid choice)

n,–r n,+r

n,r– n,r+

Accumulator offset (unsigned 8-bit or 16-bit)

aa-00 = A

01 = B

10 = D (16-bit)

11 = see accumulator D offset indexed-indirect

rr can specify X, Y, SP, or PC

A,r

B,r

D,r

111rr1aa

111rr111

Accumulator D offset indexed-indirect

rr can specify X, Y, SP, or PC

[D,r]

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

35

Central Processing Unit

2.7 Opcodes and Operands

The CPU12 uses 8-bit opcodes. Each opcode identifies a particular

instruction and associated addressing mode to the CPU. Several

opcodes are required to provide each instruction with a range of

addressing capabilities.

Only 256 opcodes would be available if the range of values were

restricted to the number that can be represented by 8-bit binary

numbers. To expand the number of opcodes, a second page is added to

the opcode map. Opcodes on the second page are preceded by an

additional byte with the value $18.

To provide additional addressing flexibility, opcodes can also be

followed by a postbyte or extension bytes. Postbytes implement certain

forms of indexed addressing, transfers, exchanges, and loop primitives.

Extension bytes contain additional program information such as

addresses, offsets, and immediate data.

Technical Data

36

MC68HC912D60A — Rev. 3.1

Central Processing Unit

Freescale Semiconductor

Technical Data — MC68HC912D60A

Section 3. Pinout and Signal Descriptions

3.1 Contents

3.2

3.3

3.4

3.5

3.6

MC68HC912D60A Pin Assignments in 112-pin QFP. . . . . . . .38

MC68HC912D60A Pin Assignments in 80-pin QFP. . . . . . . . .40

Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

Pinout and Signal Descriptions

37

Pinout and Signal Descriptions

3.2 MC68HC912D60A Pin Assignments in 112-pin QFP

PAD17/AN17

PW2/PP2

PW1/PP1

1

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

PAD07/AN07

2

PAD16/AN16

PW0/PP0

3

IOC0/PT0

4

PAD06/AN06

IOC1/PT1

5

PAD15/AN15

IOC2/PT2

PAD05/AN05

6

IOC3/PT3

PAD14/AN14

7

PG7

PAD04/AN04

8

KWG6/PG6

KWG5/PG5

KWG4/PG4

V_DD

PAD13/AN13

9

PAD03/AN03

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

PAD12/AN12

PAD02/AN02

PGUPD

PAD11/AN11

V_SS

MC68HC912D60A

PAD01/AN01

IOC4/PT4

112TQFP

PAD10/AN10

IOC5/PT5

PAD00/AN00

IOC6/PT6

V_RL0

IOC7/PT7

V_RH0

KWG3/PG3

KWG2/PG2

KWG1/PG1

KWG0/PG0

SMODN/TAGHI/BKGD

ADDR0/DATA0/PB0

ADDR1/DATA1/PB1

ADDR2/DATA2/PB2

ADDR3/DATA3/PB3

ADDR4/DATA4/PB4

V_SS

V_DD

PA7/ADDR15/DATA15/DATA7

PA6/ADDR14/DATA14/DATA6

PA5/ADDR13/DATA13/DATA5

PA4/ADDR12/DATA12/DATA4

PA3/ADDR11/DATA11/DATA3

PA2/ADDR10/DATA10/DATA2

PA1/ADDR9/DATA9/DATA1

PA0/ADDR8/DATA8/DATA0

Note: TEST =

This pin is used for factory test purposes. It is recommended that this pin is not connected in the

application, but it may be bonded to 5.5 V max without issue.

Never apply voltage higher than 5.5 V to this pin.

Figure 3-1. Pin Assignments in 112-pin TQFP for MC68HC912D60A

Technical Data

38

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Pinout and Signal Descriptions

MC68HC912D60A Pin Assignments in 112-pin QFP

4X

0.20 T L-M N

4X 28 TIPS

0.20 T L-M N

4X

P

J1

PIN 1

IDENT

112

85

C

1

84

L

VIEW Y

X

108X

G

X=L, M OR N

VIEW Y

V

B

L

M

AA

J

B1

V1

28

57

BASE

METAL

F

D

29

56

M

0.13

T L-M N

N

SECTION J1-J1

A1

S1

ROTATED 90 COUNTERCLOCKWISE

°

NOTES:

A

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

S

2. DIMENSIONS IN MILLIMETERS.

3. DATUMS L, M AND N TO BE DETERMINED AT

SEATING PLANE, DATUM T.

4. DIMENSIONS S AND V TO BE DETERMINED AT

SEATING PLANE, DATUM T.

5. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION. ALLOWABLE

PROTRUSION IS 0.25 PER SIDE. DIMENSIONS

A AND B INCLUDE MOLD MISMATCH.

6. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL NOT CAUSE THE D

DIMENSION TO EXCEED 0.46.

C2

VIEW AB

0.10

θ2

C

0.050

112X

T

SEATING

PLANE

θ3

MILLIMETERS

T

DIM MIN

MAX

A

A1

B

B1

C

20.000 BSC

10.000 BSC

20.000 BSC

10.000 BSC

---

1.600

θ

C1 0.050

C2 1.350

0.150

1.450

0.370

0.750

0.330

D

E

F

G

J

K

P

0.270

0.450

0.270

0.650 BSC

0.090

^RR2

0.170

0.500 REF

0.325 BSC

0.25

R R1

R1 0.100

R2 0.100

0.200

GAGE PLANE

S

S1

V

V1

Y

Z

22.000 BSC

11.000 BSC

22.000 BSC

11.000 BSC

0.250 REF

1.000 REF

(K)

C1

θ1

E

(Y)

(Z)

AA 0.090

0.160

8 °

0 °

3 °

θ

θ1

θ2

θ 3

7 °

VIEW AB

13 °

11 °

Figure 3-2. 112-pin TQFP Mechanical Dimensions (case no. 987)

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

39

Pinout and Signal Descriptions

3.3 MC68HC912D60A Pin Assignments in 80-pin QFP

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

PAD07/AN07

PAD06/AN06

PAD05/AN05

PAD04/AN04

PAD03/AN03

PAD02/AN02

PAD01/AN01

PAD00/AN00

V_RL0

V_RH0

V_SS

V_DD

PA7/ADDR15/DATA15/DATA7

PA6/ADDR14/DATA14/DATA6

PA5/ADDR13/DATA13/DATA5

PA4/ADDR12/DATA12/DATA4

PA3/ADDR11/DATA11/DATA3

PA2/ADDR10/DATA10/DATA2

PA1/ADDR9/DATA9/DATA1

PA0/ADDR8/DATA8/DATA0

1

2

3

4

5

6

7

8

PW2/PP2

PW1/PP1

PW0/PP0

IOC0/PT0

IOC1/PT1

IOC2/PT2

IOC3/PT3

KWG4/PG4

V_DD

V_SS

IOC4/PT4

IOC5/PT5

IOC6/PT6

IOC7/PT7

9

MC68HC912D60A

10

11

12

13

14

15

16

17

18

19

20

80 QFP

SMODN/TAGHI/BKGD

ADDR0/DATA0/PB0

ADDR1/DATA1/PB1

ADDR2/DATA2/PB2

ADDR3/DATA3/PB3

ADDR4/DATA4/PB4

Note: TEST =

This pin is used for factory test purposes. It is recommended that this pin is not connected in the

application, but it may be bonded to 5.5 V max without issue.

Never apply voltage higher than 5.5 V to this pin.

Figure 3-3. Pin Assignments in 80-pin QFP for MC68HC912D60A

Technical Data

40

MC68HC912D60A — Rev. 3.1

Pinout and Signal Descriptions

Freescale Semiconductor

Pinout and Signal Descriptions

MC68HC912D60A Pin Assignments in 80-pin QFP

L

60

41

61

40

B

P

B

-A-

-B-

L

V

B

-A-,-B-,-D-

DETAIL A

21

80

F

1

20

-D-

A

M

S

0.20

H

A-B

D

0.05 A-B

J

N

S

M

S

0.20

C A-B

D

M

E

DETAIL C

M

S

0.20

C

A-B

D

SECTION B-B

C

DATUM

PLANE

VIEW ROTATED 90

-H-

°

-C-

0.10

H

SEATING

PLANE

M

G

NOTES:

MILLIMETERS

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

DIM MIN

MAX

14.10

2.45

A

B

C

D

E

F

G

H

J

K

L

M

N

P

Q

R

S

T

U

V

W

X

13.90

2.15

0.22

2.00

0.22

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF

LEAD AND IS COINCIDENT WITH THE

LEAD WHERE THE LEAD EXITS THE PLASTIC

BODY AT THE BOTTOM OF THE PARTING LINE.

4. DATUMS -A-, -B- AND -D- TO BE

U

0.38

2.40

0.33

0.65 BSC

T

DATUM

PLANE

---

0.13

0.65

0.25

0.23

0.95

-H-

DETERMINED AT DATUM PLANE -H-.

R

5. DIMENSIONS S AND V TO BE DETERMINED

AT SEATING PLANE -C-.

6. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION. ALLOWABLE

PROTRUSION IS 0.25 PER SIDE. DIMENSIONS

A AND B DO INCLUDE MOLD MISMATCH

AND ARE DETERMINED AT DATUM PLANE -H-.

7. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.08 TOTAL IN

12.35 REF

10

5

°

0.13

0.17

0.325 BSC

K

0

7

°

Q

°

W

0.13

16.95

0.13

0

0.30

17.45

---

X

DETAIL C

---

°

16.95

0.35

17.45

0.45

1.6 REF

Figure 3-4. 80-pin QFP Mechanical Dimensions (case no. 841B)

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

41

Pinout and Signal Descriptions

3.4 Power Supply Pins

MC68HC912D60A power and ground pins are described below and

summarized in Table 3-1.

All power supply pins must be connected to appropriate supplies.

On no account must any pins be left floating.

3.4.1 Internal Power (V ) and Ground (V )

DD

SS

Power is supplied to the MCU through V and V . Because fast signal

DD

SS

transitions place high, short-duration current demands on the power

supply, use bypass capacitors with high-frequency characteristics and

place them as close to the MCU as possible. Bypass requirements

depend on how heavily the MCU pins are loaded.

3.4.2 External Power (V

) and Ground (V

)

DDX

SSX

External power and ground for I/O drivers. Because fast signal

transitions place high, short-duration current demands on the power

supply, use bypass capacitors with high-frequency characteristics and

place them as close to the MCU as possible. Bypass requirements

depend on how heavily the MCU pins are loaded.

3.4.3 V

, V

SSA

DDA

Provides operating voltage and ground for the analog-to-digital

converter. This allows the supply voltage to the ATD to be bypassed

independently. Connecting V

to V if the ATD modules are not

DD

DDA

used will not result in an increase of power consumption.

3.4.4 Analog to Digital Reference Voltages (V , V )

RH

RL

V

, V : reference voltage high and low for ATD converter 0.

RL0

RH0

RH1

, V : reference voltage high and low for ATD converter 1.

RL1

If the ATD modules are not used, leaving V connected to V will not

RH

DD

result in an increase of power consumption.

Technical Data

42

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Pinout and Signal Descriptions

Power Supply Pins

3.4.5 V

, V

SSPLL

DDPLL

Provides operating voltage and ground for the Phased-Locked Loop.

This allows the supply voltage to the PLL to be bypassed independently.

NOTE: The VSSPLL pin should always be grounded even if the PLL is not used.

The VDDPLL pin should not be left floating. It is recommended to

connect the VDDPLL pin to ground if the PLL is not used.

3.4.6 XFC

PLL loop filter. Please see Appendix: CGM Practical Aspects for

information on how to calculate PLL loop filter elements. Any current

leakage on this pin must be avoided.

VDDPLL

C

0

MCU

C

a

R

0

XFC

Figure 3-5. PLL Loop FIlter Connections

If VDDPLL is connected to VSS (this is normal case), then the XFC pin

should either be left floating or connected to VSS (never to VDD). If

VDDPLL is tied to VDD but the PLL is switched off (PLLON bit cleared),

then the XFC pin should be connected preferably to VDDPLL (i.e. ready

for VCO minimum frequency).

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

43

Pinout and Signal Descriptions

Table 3-1. MC68HC912D60A Power and Ground Connection Summary

Pin Number

Mnemonic

Description

80-pin

112-pin

QFP

9, 49

10, 50

30, 75

29, 74

61

V

12, 65

14, 66

42, 107

40, 106

85

DD

Internal power and ground.

V

SS

V

DDX

External power and ground, supply to pin drivers.

V

SSX

V

Operating voltage and ground for the analog-to-digital

converter, allows the supply voltage to the A/D to be

bypassed independently.

DDA

V

62

88

SSA

V

—

86

RH1

Reference voltages for the analog-to-digital converter 1

Reference voltages for the analog-to-digital converter 0.

V

—

87

RL1

V

51

67

RH0

V

52

68

RL0

V

Provides operating voltage and ground for the Phased-Locked

Loop. This allows the supply voltage to the PLL to be

bypassed independently.

31

43

DDPLL

V

33

45

SSPLL

3.5 Signal Descriptions

3.5.1 Crystal Driver and External Clock Input (XTAL, EXTAL)

These pins provide the interface for either a crystal or a CMOS

compatible clock to control the internal clock generator circuitry. Out of

reset the frequency applied to EXTAL is twice the desired E–clock rate.

All the device clocks are derived from the EXTAL input frequency.

3.5.1.1 Crystal Connections

Refer to Section 12. Oscillator for details of crystal connections.

Technical Data

44

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Pinout and Signal Descriptions

Signal Descriptions

NOTE: When selecting a crystal, it is recommended to use one with the lowest

possible frequency in order to minimise EMC emissions.

3.5.1.2 External Oscillator Connections

XTAL is the crystal output. The XTAL pin must be left unterminated when

an external CMOS compatible clock input is connected to the EXTAL

pin. The XTAL output is normally intended to drive only a crystal. The

XTAL output can be buffered with a high-impedance buffer to drive the

EXTAL input of another device.

2xE

EXTAL

CMOS-COMPATIBLE

EXTERNALOSCILLATOR

MCU

XTAL

NC

Figure 3-6. External Oscillator Connections

3.5.2 E-Clock Output (ECLK)

ECLK is the output connection for the internal bus clock and is used to

demultiplex the address and data and is used as a timing reference.

ECLK frequency is equal to 1/2 the crystal frequency out of reset. The

ECLK output is turned off in single chip user mode to reduce the effects

of RFI. It can be turned on if necessary. In single-chip special mode, the

ECLK is turned ON at reset and can be turned OFF. In special peripheral

mode the ECLK is an input to the MCU. All clocks, including the ECLK,

are halted when the MCU is in STOP mode. It is possible to configure

the MCU to interface to slow external memory. ECLK can be stretched

for such accesses.

3.5.3 Reset (RESET)

An active low bidirectional control signal, RESET, acts as an input to

initialize the MCU to a known start-up state. It also acts as an open-drain

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

45

Pinout and Signal Descriptions

output to indicate that an internal failure has been detected in either the

clock monitor or COP watchdog circuit. The MCU goes into reset

asynchronously and comes out of reset synchronously. This allows the

part to reach a proper reset state even if the clocks have failed, while

allowing synchronized operation when starting out of reset.

It is important to use an external low-voltage reset circuit (such as

MC34064 or MC34164) to prevent corruption of RAM or EEPROM due

to power transitions.

The reset sequence is initiated by any of the following events:

• Power-on-reset (POR)

• COP watchdog enabled and watchdog timer times out

• Clock monitor enabled and Clock monitor detects slow or stopped

clock

• User applies a low level to the reset pin

External circuitry connected to the reset pin should not include a large

capacitance that would interfere with the ability of this signal to rise to a

valid logic one within nine bus cycles after the low drive is released.

Upon detection of any reset, an internal circuit drives the reset pin low

and a clocked reset sequence controls when the MCU can begin normal

processing. In the case of POR or a clock monitor error, a 4096 cycle

oscillator startup delay is imposed before the reset recovery sequence

starts (reset is driven low throughout this 4096 cycle delay). The internal

reset recovery sequence then drives reset low for 16 to 17 cycles and

releases the drive to allow reset to rise. Nine cycles later this circuit

samples the reset pin to see if it has risen to a logic one level. If reset is

low at this point, the reset is assumed to be coming from an external

request and the internally latched states of the COP timeout and clock

monitor failure are cleared so the normal reset vector ($FFFE:FFFF) is

taken when reset is finally released. If reset is high after this nine cycle

delay, the reset source is tentatively assumed to be either a COP failure

or a clock monitor fail. If the internally latched state of the clock monitor

fail circuit is true, processing begins by fetching the clock monitor vector

($FFFC:FFFD). If no clock monitor failure is indicated, and the latched

state of the COP timeout is true, processing begins by fetching the COP

Technical Data

46

MC68HC912D60A — Rev. 3.1

Pinout and Signal Descriptions

Freescale Semiconductor

Pinout and Signal Descriptions

Signal Descriptions

vector ($FFFA:FFFB). If neither clock monitor fail nor COP timeout are

pending, processing begins by fetching the normal reset vector

($FFFE:FFFF).

3.5.4 Maskable Interrupt Request (IRQ)

The IRQ input provides a means of applying asynchronous interrupt

requests to the MCU. Either falling edge-sensitive triggering or level-

sensitive triggering is program selectable (INTCR register). IRQ is

always enabled and configured to level-sensitive triggering at reset. It

can be disabled by clearing the IRQEN bit (INTCR register). When the

MCU is reset the IRQ function is masked in the condition code register.

This pin is always an input and can always be read. There is an active

pull-up on this pin while in reset and immediately out of reset. The pull-

up can be turned off by clearing PUPE in the PUCR register.

3.5.5 Nonmaskable Interrupt (XIRQ)

The XIRQ input provides a means of requesting a nonmaskable interrupt

after reset initialization. During reset, the X bit in the condition code

register (CCR) is set and any interrupt is masked until MCU software

enables it. Because the XIRQ input is level sensitive, it can be connected

to a multiple-source wired-OR network. This pin is always an input and

can always be read. There is an active pull-up on this pin while in reset

and immediately out of reset. The pull-up can be turned off by clearing

PUPE in the PUCR register. XIRQ is often used as a power loss detect

interrupt.

Whenever XIRQ or IRQ are used with multiple interrupt sources (IRQ

must be configured for level-sensitive operation if there is more than one

source of IRQ interrupt), each source must drive the interrupt input with

an open-drain type of driver to avoid contention between outputs. There

must also be an interlock mechanism at each interrupt source so that the

source holds the interrupt line low until the MCU recognizes and

acknowledges the interrupt request. If the interrupt line is held low, the

MCU will recognize another interrupt as soon as the interrupt mask bit in

the MCU is cleared (normally upon return from an interrupt).

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

47

Pinout and Signal Descriptions

3.5.6 Mode Select (SMODN, MODA, and MODB)

The state of these pins during reset determine the MCU operating mode.

After reset, MODA and MODB can be configured as instruction queue

tracking signals IPIPE0 and IPIPE1. MODA and MODB have active pull-

downs during reset.

The SMODN pin has an active pull-up when configured as input. This pin

can be used as BKGD or TAGHI after reset.

3.5.7 Single-Wire Background Mode Pin (BKGD)

The BKGD pin receives and transmits serial background debugging

commands. A special self-timing protocol is used. The BKGD pin has an

active pull-up when configured as input; BKGD has no pull-up control.

Refer to Development Support.

3.5.8 External Address and Data Buses (ADDR[15:0] and DATA[15:0])

External bus pins share function with general-purpose I/O ports A and B.

In single-chip operating modes, the pins can be used for I/O; in

expanded modes, the pins are used for the external buses.

In expanded wide mode, ports A and B are used for multiplexed 16-bit

data and address buses. PA[7:0] correspond to

ADDR[15:8]/DATA[15:8]; PB[7:0] correspond to ADDR[7:0]/DATA[7:0].

In expanded narrow mode, ports A and B are used for the16-bit address

bus, and an 8-bit data bus is multiplexed with the most significant half of

the address bus on port A. In this mode, 16-bit data is handled as two

back-to-back bus cycles, one for the high byte followed by one for the

low byte. PA[7:0] correspond to ADDR[15:8] and to DATA[15:8] or

DATA[7:0], depending on the bus cycle. The state of the address pin

should be latched at the rising edge of E. To allow for maximum address

setup time at external devices, a transparent latch should be used.

Technical Data

48

MC68HC912D60A — Rev. 3.1

Pinout and Signal Descriptions

Freescale Semiconductor

Pinout and Signal Descriptions

Signal Descriptions

3.5.9 Read/Write (R/W)

In all modes this pin can be used as general-purpose I/O and is an input

with an active pull-up out of reset. If the read/write function is required it

should be enabled by setting the RDWE bit in the PEAR register.

External writes will not be possible until enabled.

3.5.10 Low-Byte Strobe (LSTRB)

In all modes this pin can be used as general-purpose I/O and is an input

with an active pull-up out of reset. If the strobe function is required, it

should be enabled by setting the LSTRE bit in the PEAR register. This

signal is used in write operations and so external low byte writes will not

be possible until this function is enabled. This pin is also used as TAGLO

in Special Expanded modes and is multiplexed with the LSTRB function.

3.5.11 Instruction Queue Tracking Signals (IPIPE1 and IPIPE0)

These signals are used to track the state of the internal instruction

execution queue. Execution state is time-multiplexed on the two signals.

Refer to Development Support.

3.5.12 Data Bus Enable (DBE)

The DBE pin (PE7) is an active low signal that will be asserted low during

ECLK high time. DBE provides separation between output of a

multiplexed address and the input of data. When an external address is

stretched, DBE is asserted during what would be the last quarter cycle

of the last ECLK cycle of stretch. In expanded modes this pin is used to

enable the drive control of external buses during external reads. Use of

the DBE is controlled by the NDBE bit in the PEAR register.DBE is

enabled out of reset in expanded modes. This pin has an active pull-up

during and after reset in single chip modes.

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

49

Pinout and Signal Descriptions

3.5.13 Inverted ECLK (ECLK)

The ECLK pin (PE7) can be used to latch the address for de-

multiplexing. It has the same behavior as the ECLK, except is inverted.

In expanded modes this pin is used to enable the drive control of external

buses during external reads. Use of the ECLK is controlled by the NDBE

and DBENE bits in the PEAR register.

3.5.14 Calibration reference (CAL)

The CAL pin (PE7) is the output of the Slow Mode programmable clock

divider, SLWCLK, and is used as a calibration reference. The SLWCLK

frequency is equal to the crystal frequency out of reset and always has

a 50% duty. If the DBE function is enabled it will override the enabled

CAL output. The CAL pin output is disabled by clearing CALE bit in the

PEAR register.

3.5.15 Clock generation module test (CGMTST)

The CGMTST pin (PE6) is the output of the clocks tested when CGMTE

bit is set in PEAR register. The PIPOE bit must be cleared for the clocks

to be tested.

3.5.16 TEST

This pin is used for factory test purposes. It is recommended that this

pin is not connected in the application, but it may be bonded to 5.5 V max

without issue. Never apply voltage higher than 5.5 V to this pin.

Table 3-2. MC68HC912D60A Signal Description Summary

Pin Number

Description

Pin Name

80-pin

112-pin

EXTAL

XTAL

35

36

47

Crystal driver and external clock input pins.

48

An active low bidirectional control signal, RESET acts as an input to

initialize the MCU to a known start-up state, and an output when COP or

clock monitor causes a reset.

RESET

34

46

Technical Data

50

MC68HC912D60A — Rev. 3.1

Pinout and Signal Descriptions

Freescale Semiconductor

Pinout and Signal Descriptions

Signal Descriptions

Table 3-2. MC68HC912D60A Signal Description Summary

Pin Number

Pin Name

Description

80-pin

112-pin

ADDR[7:0]

DATA[7:0]

23–16

48–41

31–24

External bus pins share function with general-purpose I/O ports A and B.

In single chip modes, the pins can be used for I/O. In expanded modes,

the pins are used for the external buses.

ADDR[15:8]

DATA[15:8]

64–57

Data bus control and, in expanded mode, enables the drive control of

external buses during external reads.

DBE

25

36

ECLK

Inverted ECLK used to latch the address.

CAL is the output of the Slow Mode programmable clock divider, SLWCLK,

and is used as a calibration reference for functions such as time of day. It

is overridden when DBE function is enabled. It always has a 50% duty

cycle.

CAL

25

26

36

37

CGMTST

Clock generation module test output.

MODB/

IPIPE1,

MODA/

IPIPE0

State of mode select pins during reset determine the initial operating mode

of the MCU. After reset, MODB and MODA can be configured as

instruction queue tracking signals IPIPE1 and IPIPE0 or as general-

purpose I/O pins.

26, 27

37, 38

E Clock is the output connection for the external bus clock. ECLK is used

as a timing reference and for address demultiplexing.

ECLK

28

37

38

39

40

15

39

53

54

55

56

23

Low byte strobe (0 = low byte valid), in all modes this pin can be used as

I/O. The low strobe function is the exclusive-NOR of A0 and the internal

SZ8 signal. (The SZ8 internal signal indicates the size 16/8 access.) Pin

function TAGLO used in instruction tagging. See Development Support.

LSTRB/

TAGLO

Indicates direction of data on expansion bus. Shares function with general-

purpose I/O. Read/write in expanded modes.

R/W

IRQ

Maskable interrupt request input provides a means of applying

asynchronous interrupt requests to the MCU. Either falling edge-

sensitive triggering or level-sensitive triggering is program selectable

(INTCR register).

Provides a means of requesting asynchronous nonmaskable interrupt

requests after reset initialization

XIRQ

Single-wire background interface pin is dedicated to the background

debug function. During reset, this pin determines special or normal

operating mode. Pin function TAGHI used in instruction tagging. See

Development Support.

SMODN/BK

GD/TAGHI

PW[3:0]

SS

80, 1–3

70

112, 1–3 Pulse Width Modulator channel outputs.

Slave select output for SPI master mode, input for slave mode or master

96

mode.

SCK

69

95

Serial clock for SPI system.

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

51

Pinout and Signal Descriptions

Table 3-2. MC68HC912D60A Signal Description Summary

Pin Number

80-pin 112-pin

Pin Name

Description

SDO/MOSI

SDI/MISO

TxD1

68

67

66

65

64

63

94

93

92

91

90

89

Master out/slave in pin for serial peripheral interface

Master in/slave out pin for serial peripheral interface

SCI1 transmit pin

RxD1

SCI1 receive pin

TxD0

SCI0 transmit pin

RxD0

SCI0 receive pin

14–11,

7–4

Pins used for input capture and output compare in the timer and pulse

accumulator subsystem.

IOC[7:0]

AN1[7:0]

AN0[7:0]

18–15, 7–4

84/82/80/78/

76/74/72/70

N/A

Analog inputs for the analog-to-digital conversion module 1

Analog inputs for the analog-to-digital conversion module 0

83/81/79/77/

75/73/71/69

60–53

Used for factory test purposes. Do not connect in the application; may be

bonded to 5.5 V max.

TEST

TxCAN

RxCAN

71

72

73

97

104

105

MSCAN transmit pin. Leave unconnected if MSCAN is not used.

MSCAN receive pin. Pin has internal pull-up; where msCAN module is not

used, do not tie to VSS.

Key wake-up and general purpose I/O; can cause an interrupt when an

9–11, 19–22 input transitions from high to low. On 80-pin QFP all 8 I/O should be

initialised.

8 (KWG4

only)

KWG[6:0]

PGUPD

(1)

13

Defines if I/O port resistive load is a pull-up or a pull-down, when enabled.

Key wake-up and general purpose I/O; can cause an interrupt when an

input transitions from high to low. On 80-pin QFP all 8 I/O should be

initialised.

24(KWH4

only)

32–35,

49–52

KWH[7:0]

PHUPD

(2)

41

Defines if I/O port resistive load is a pull-up or a pull-down, when enabled.

1. In the 80-pin version PGUPD is connected internally to VDD

2. In the 80-pin version PHUPD is connected internally to VSS

3.6 Port Signals

The MC68HC912D60A incorporates eight ports which are used to

control and access the various device subsystems. When not used for

these purposes, port pins may be used for general-purpose I/O. In

addition to the pins described below, each port consists of a data register

Technical Data

52

MC68HC912D60A — Rev. 3.1

Pinout and Signal Descriptions

Freescale Semiconductor

Pinout and Signal Descriptions

Port Signals

which can be read and written at any time, and, with the exception of port

AD0, port AD1 (available only in 112TQFP), PE[1:0], RxCAN and

TxCAN, a data direction register which controls the direction of each pin.

After reset all general purpose I/O pins are configured as input.

3.6.1 Port A

Port A pins are used for address and data in expanded modes. In single

chip modes, the pins can be used as I/O. The port data register is not in

the address map during expanded and peripheral mode operation.

When it is in the map, port A can be read or written at anytime.

Register DDRA determines whether each port A pin is an input or output.

DDRA is not in the address map during expanded and peripheral mode

operation. Setting a bit in DDRA makes the corresponding bit in port A

an output; clearing a bit in DDRA makes the corresponding bit in port A

an input. The default reset state of DDRA is all zeros.

When the PUPA bit in the PUCR register is set, all port A input pins are

pulled-up internally by an active pull-up device. This bit has no effect if

the port is being used in expanded modes as the pull-ups are inactive.

Setting the RDPA bit in register RDRIV causes all port A outputs to have

reduced drive level. RDRIV can be written once after reset. RDRIV is not

in the address map in peripheral mode. Refer to Bus Control and

Input/Output.

3.6.2 Port B

Port B pins are used for address and data in expanded modes. In single

chip modes, the pins can be used as I/O. The port data register is not in

the address map during expanded and peripheral mode operation.

When it is in the map, port B can be read or written at anytime.

Register DDRB determines whether each port B pin is an input or output.

DDRB is not in the address map during expanded and peripheral mode

operation. Setting a bit in DDRB makes the corresponding bit in port B

an output; clearing a bit in DDRB makes the corresponding bit in port B

an input. The default reset state of DDRB is all zeros.

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

53

Pinout and Signal Descriptions

When the PUPB bit in the PUCR register is set, all port B input pins are

pulled-up internally by an active pull-up device. This bit has no effect if

the port is being used in expanded modes as the pull-ups are inactive.

Setting the RDPB bit in register RDRIV causes all port B outputs to have

reduced drive level. RDRIV can be written once after reset. RDRIV is not

in the address map in peripheral mode. Refer to Bus Control and

Input/Output.

3.6.3 Port E

Port E pins operate differently from port A and B pins. Port E pins are

used for bus control signals and interrupt service request signals. When

a pin is not used for one of these specific functions, it can be used as

general-purpose I/O. However, two of the pins (PE[1:0]) can only be

used for input, and the states of these pins can be read in the port data

register even when they are used for IRQ and XIRQ.

The PEAR register determines pin function, and register DDRE

determines whether each pin is an input or output when it is used for

general-purpose I/O. PEAR settings override DDRE settings. Because

PE[1:0] are input-only pins, only DDRE[7:2] have effect. Setting a bit in

the DDRE register makes the corresponding bit in port E an output;

clearing a bit in the DDRE register makes the corresponding bit in port E

an input. The default reset state of DDRE is all zeros.

When the PUPE bit in the PUCR register is set, PE7 and PE[3:0] are

pulled up by active devices.

Neither port E nor DDRE is in the map in peripheral mode; neither is in

the internal map in expanded modes with EME set.

Setting the RDPE bit in register RDRIV causes all port E outputs to have

reduced drive level. RDRIV can be written once after reset. RDRIV is not

in the address map in peripheral mode. Refer to Bus Control and

Input/Output.

Technical Data

54

MC68HC912D60A — Rev. 3.1

Pinout and Signal Descriptions

Freescale Semiconductor

Pinout and Signal Descriptions

Port Signals

3.6.4 Port G

Port G pins are used for key wake-ups that can be used with the pins

configured as inputs or outputs. The key wake-ups are triggered with a

falling edge signal (KWPG). An interrupt is generated if the

corresponding bit is enabled (KWIEG). If any of the interrupts is not

enabled, the corresponding pin can be used as a general purpose I/O

pin. Refer to I/O Ports with Key Wake-up.

Register DDRG determines pin direction of port G when used for

general-purpose I/O. When DDRG bits are set, the corresponding pin is

configured for output. On reset the DDRG bits are cleared and the

corresponding pin is configured for input.

Port PGUPD determines what type of resistive load is used for port G

input pins when PUPG bit is set in the PUCR register. When PGUPD pin

is low, it loads a pull-down in all port G input pins. When PGUPD pin is

high, it loads a pull-up in all port G input pins.

In 80-pin version, the PGUPD is connected internally to VDD. The PG4

will have a pull-up. All port G pins should either be defined as outputs or

have their pull-ups enabled.

Setting the RDPG bit in register RDRIV causes all port G outputs to have

reduced drive level. RDRIV can be written once after reset. RDRIV is not

in the address map in peripheral mode. Refer to Bus Control and

Input/Output.

3.6.5 Port H

Port H pins are used for key wake-ups that can be used with the pins

configured as inputs or outputs. The key wake-ups are triggered with a

falling edge signal (KWPH). An interrupt is generated if the

corresponding bit is enabled (KWIEH). If any of the interrupts is not

enabled, the corresponding pin can be used as a general purpose I/O

pin. Refer to I/O Ports with Key Wake-up.

Register DDRH determines pin direction of Port H when used for

general-purpose I/O. When DDRH bits are set, the corresponding pin is

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

55

Pinout and Signal Descriptions

configured for output. On reset the DDRH bits are cleared and the

corresponding pin is configured for input.

Port PHUPD determines what type of resistive load is used for Port H

input pins when PUPH bit is set in the PUCR register. When PHUPD pin

is low, it loads a pull-down in all Port H input pins. When PHUPD pin is

high, it loads a pull-up in all Port H input pins.

In 80-pin version, the PHUPD is connected internally to VSS. The PH4

will have a pull-down. All port H pins should either be defined as outputs

or have their pull-downs enabled.

Setting the RDPH bit in register RDRIV causes all Port H outputs to have

reduced drive level. RDRIV can be written once after reset. RDRIV is not

in the address map in peripheral mode. Refer to Bus Control and

Input/Output.

3.6.6 Port CAN

The MSCAN12 uses two external pins, one input (RxCAN) and one

output (TxCAN). The TxCAN output pin represents the logic level on the

CAN: ‘0’ is for a dominant state, and ‘1’ is for a recessive state. If the

MSCAN is not used, TxCAN should be left unconnected and, due to an

internal pull-up, the RxCAN pin should not be tied to VSS.

RxCAN is on bit 0 of Port CAN, TxCAN is on bit 1. The remaining six pins

of Port CAN, available only in the 112-pin package, are controlled by

registers in the MSCAN12 address space.

In 80QFP all PortCAN[2:7] pins should either be defined as outputs or

have their pull-ups enabled.

3.6.7 Port AD1

Input to the analog-to-digital subsystem and general-purpose input.

When analog-to-digital functions are not enabled, the port has eight

general-purpose input pins, PAD1[7:0]. The ADPU bit in the ATD1CTL2

register enables the A/D function.

Technical Data

56

MC68HC912D60A — Rev. 3.1

Pinout and Signal Descriptions

Freescale Semiconductor

Pinout and Signal Descriptions

Port Signals

Port AD1 pins are inputs; no data direction register is associated with this

port. The port has no resistive input loads and no reduced drive controls.

Refer to Analog-to-Digital Converter.

Port AD1 is not available in the 80-pin package.

3.6.8 Port AD0

Input to the analog-to-digital subsystem and general-purpose input.

When analog-to-digital functions are not enabled, the port has eight

general-purpose input pins, PAD0[7:0]. The ADPU bit in the ATD0CTL2

register enables the A/D function.

Port AD0 pins are inputs; no data direction register is associated with this

port. The port has no resistive input loads and no reduced drive controls.

Refer to Analog-to-Digital Converter.

3.6.9 Port P

The four pulse-width modulation channel outputs share general-purpose

port P pins. The PWM function is enabled with the PWEN register.

Enabling PWM pins takes precedence over the general-purpose port.

When pulse-width modulation is not in use, the port pins may be used for

general-purpose I/O.

Register DDRP determines pin direction of port P when used for

general-purpose I/O. When DDRP bits are set, the corresponding pin is

configured for output. On reset the DDRP bits are cleared and the

corresponding pin is configured for input.

When the PUPP bit in the PWCTL register is set, all input pins are pulled

up internally by an active pull-up device. Pull-ups are disabled after

reset.

Setting the RDPP bit in the PWCTL register configures all port P outputs

to have reduced drive levels. Levels are at normal drive capability after

reset. The PWCTL register can be read or written anytime after reset.

Refer to Pulse Width Modulator.

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

57

Pinout and Signal Descriptions

3.6.10 Port S

Port S is the 8-bit interface to the standard serial interface consisting of

the two serial communications interfaces (SCI1 and SCI0) and the serial

peripheral interface (SPI) subsystems. Port S pins are available for

general-purpose parallel I/O when standard serial functions are not

enabled.

Port S pins serve several functions depending on the various internal

control registers. If WOMS bit in the SC0CR1register is set, the P-

channel drivers of the output buffers are disabled for bits 0 through 1 for

the SCSI1 (2 through 3 for the SCI0). If SWOM bit in the SP0CR1

register is set, the P-channel drivers of the output buffers are disabled

for bits 4 through 7 (wire-ORed mode). The open drain control effects to

both the serial and the general-purpose outputs. If the RDPSx bits in the

PURDS register are set, the appropriate Port S pin drive capabilities are

reduced. If PUPSx bits in the PURDS register are set, the appropriate

pull-up device is connected to each port S pin which is programmed as

a general-purpose input. If the pin is programmed as a general-purpose

output, the pull-up is disconnected from the pin regardless of the state of

the individual PUPSx bits. See Multiple Serial Interface.

3.6.11 Port T

This port provides eight general-purpose I/O pins when not enabled for

input capture and output compare in the timer and pulse accumulator

subsystem. The TEN bit in the TSCR register enables the timer function.

The pulse accumulator subsystem is enabled with the PAEN bit in the

PACTL register.

Register DDRT determines pin direction of port T when used for general-

purpose I/O. When DDRT bits are set, the corresponding pin is

configured for output. On reset the DDRT bits are cleared and the

corresponding pin is configured for input.

When the PUPT bit in the TMSK2 register is set, all input pins are pulled

up internally by an active pull-up device. Pull-ups are disabled after

reset.

Technical Data

58

MC68HC912D60A — Rev. 3.1

Pinout and Signal Descriptions

Freescale Semiconductor

Pinout and Signal Descriptions

Port Signals

Setting the RDPT bit in the TMSK2 register configures all port T outputs

to have reduced drive levels. Levels are at normal drive capability after

reset. The TMSK2 register can be read or written anytime after reset

Refer to Enhanced Capture Timer.

Table 3-3. MC68HC912D60A Port Description Summary

Pin Numbers

Data Direction

Register

Port Name

Description

80-pin 112-pin

(Address)

Port A

PA[7:0]

In/Out

DDRA ($0002)

Port A and port B pins are used for address and data in

expanded modes. The port data registers are not in the

address map during expanded and peripheral mode

operation. When in the map, port A and port B can be

read or written any time.

48–41

23–16

64–57

31–24

In/Out

DDRB ($0003)

Port B

PB[7:0]

DDRA and DDRB are not in the address map in expanded

or peripheral modes.

84/82/80

/78/76/7

4/72/70

Port AD1

PAD1[7:0]

N/A

In

Analog-to-digital converter 1 and general-purpose I/O.

Analog-to-digital converter 0 and general-purpose I/O.

83/81/79

60–53 /77/75/7

3/71/69

Port AD0

PAD0[7:0]

In

Port CAN

PCAN[7:0]

General purpose I/O. PCAN[1:0] are used with the

MSCAN12 module and cannot be used as I/O.

(1)

98–105

In/Out

72, 73

PE[1:0] In

PE[7:2] In/Out

DDRE ($0009)

Port E

PE[7:0]

25–28, 36–39,

Mode selection, bus control signals and interrupt service

request signals; or general-purpose I/O.

37–40

53–56

108–112

Port P

PP[7:0]

76–80,

1–3

In/Out

DDRP ($0057)

General-purpose I/O. PP[3:0] are used with the pulse-width

modulator when enabled.

,

1–3

Port S

PS[7:0]

In/Out

DDRS ($00D7)

Serial communications interfaces 1 and 0 and serial

peripheral interface subsystems and general-purpose I/O.

70–63

96–89

General-purpose I/O when not enabled for input capture

and output compare in the timer and pulse accumulator

subsystem.

Port T

PT[7:0]

14–11, 18–15,

7–4 7–4

In/Out

DDRT ($00AF)

1. In 80-pin QFP package only TxCAN and RxCAN are available. PortCAN[2:7] pins should either be defined as outputs or

have their pull-ups enabled.

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

59

Pinout and Signal Descriptions

3.6.12 Port Pull-Up Pull-Down and Reduced Drive

MCU ports can be configured for internal pull-up. To reduce power

consumption and RFI, the pin output drivers can be configured to

operate at a reduced drive level. Reduced drive causes a slight increase

in transition time depending on loading and should be used only for ports

which have a light loading. Table 3-4 summarizes the port pull-up/pull-

down default status and controls.

Table 3-4. Port Pull-Up, Pull-Down and Reduced Drive Summary

Enable Bit

Reduced Drive Control Bit

Port

Name

Resistive

Input Loads

Register

(Address)

Reset

State

Register

(Address)

Reset

Bit Name

State

Full drive

Port A

Pull-up

PUCR ($000C)

PUPA

PUPB

Disabled RDRIV ($000D)

RDPA

RDPB

Port B

Port E:

PE7,

PE[3:2]

Pull-up

PUCR ($000C)

PUPE

Enabled RDRIV ($000D)

RDPE

Full drive

PE[1:0]

PE[6:4]

Pull-up

None

PUCR ($000C)

—

Enabled

—

RDRIV ($000D)

RDPE

RDPG

Full drive

Pull-up or

Pull-

Port G

Port H

PUCR ($000C)

PUPG

PUPH

Enabled RDRIV ($000D)

(1)

down

Pull-up or

Pull-

RDPH

Full drive

(2)

down

Port P

Pull-up

PWCONT ($0054) PUPP

PURDS ($00D9) PUPS0

PURDS ($00D9) PUPS1

PURDS ($00D9) PUPS2

Disabled PWCONT ($0054) RDPP

Full drive

PS[1:0]

PS[3:2]

PS[7:4]

Port T

Disabled PURDS ($00DB)

Disabled TMSK2 ($008D)

RDPS0

RDPS1

RDPS2

TDRB

TMSK2 ($008D)

PUPT

PortCAN[1]:

TxCAN

None

—

PortCAN[0]:

RxCAN

Pull-up

Always enabled

Port

CAN[7:2]

PCTLCAN

($013D)

PUPCAN Disabled PCTLCAN ($013D) RDPCAN Full drive

Port AD0

Port AD1

None

—

1. Pull-Up when PGUPD input pin is high, Pull-down when PGUPD input pin is low.

In the 80-pin version, PGUPD is internally tied to VDD, hence PG4 is pulled up.

2. Pull-Up when PHUPD input pin is high, Pull-down when PHUPD input pin is low.

In the 80-pin version, PHUPD is internally tied to VSS, hence PH4 is pulled down.

Technical Data

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

60

Pinout and Signal Descriptions

Technical Data — MC68HC912D60A

Section 4. Registers

4.1 Contents

4.2

Register Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

4.2 Register Block

The register block can be mapped to any 2K byte boundary within the

standard 64K byte address space by manipulating bits REG[15:11] in

the INITRG register. INITRG establishes the upper five bits of the

register block’s 16-bit address. The register block occupies the first 512

bytes of the 2K byte block. Default addressing (after reset) is indicated

in Table 4-1. For additional information refer to Operating Modes and

Resource Mapping.

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

61

Registers

Address

$0000

$0001

$0002

$0003

$0004

$0005

$0006

$0007

$0008

$0009

$000A

$000B

$000C

$000D

$000E

Bit 7

6

PA6

PB6

DDA6

DDB6

0

5

PA5

PB5

DDA5

DDB5

0

4

PA4

PB4

DDA4

DDB4

0

3

PA3

PB3

DDA3

DDB3

0

2

1

PA1

PB1

DDA1

DDB1

0

Bit 0

PA0

PB0

DDA0

DDB0

0

Name

(1)

PA7

PB7

DDA7

DDB7

0

PA2

PORTA

PORTB

(1)

PB2

DDA2

DDRA

DDRB

(1)

DDB2

(3)

0

Reserved

0

PE2

DDE2

RDWE

EBSWAI

0

(2)

PE7

DDE7

NDBE

SMODN

PUPH

0

PE6

DDE6

CGMTE

MODB

PUPG

RDPH

0

PE5

DDE5

PIPOE

MODA

0

PE4

DDE4

NECLK

ESTR

PUPE

0

PE3

DDE3

LSTRE

IVIS

0

PE1

0

PE0

0

PORTE

(2)

DDRE

(3)

CALE

0

DBENE

EME

PUPA

RDPA

0

PEAR

(3)

MODE

(3)

PUPB

RDPB

0

PUCR

RDPG

0

RDPE

0

RDRIV

(3)

0

Reserved

$000F

$0010

$0011

$0012

0

RAM15

REG15

EE15

RAM14

REG14

EE14

RAM13

REG13

EE13

RAM12

REG12

EE12

RAM11

REG11

0

INITRM

INITRG

MMSWAI

EEON

INITEE

$0013 MAPROM NDRF

RFSTR1 RFSTR0 EXSTR1 EXSTR0 ROMON28ROMON32

MISC

$0014

$0015

$0016

$0017

$0018

$0019

$001A

$001B

$001C

$001D

$001E

$001F

$0020

RTIE

RSWAI

0

RSBCK Reserved RTBYP

RTR2

RTR1

RTR0

RTICTL

RTIFLG

COPCTL

COPRST

Reserved

INTCR

RTIF

0

CR0

Bit 0

0

CME

FCME FCMCOP WCOP

DISR

CR2

CR1

Bit 7

6

5

4

3

2

1

0

IRQE

1

IRQEN

1

DLY

PSEL5

BKPM

0

PSEL4

0

PSEL1

0

PSEL3

PSEL2

0

HPRIO

BKEN1

BKEN0

BK1ALE BK0ALE

0

BRKCT0

= Reserved or unimplemented bits.

Table 4-1. MC68HC912D60A Register Map (Sheet 1 of 9)

Technical Data

62

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Registers

Register Block

Address

$0021

$0022

$0023

$0024

$0025

$0026

$0027

$0028

$0029

$002A

$002B

$002C

Bit 7

0

6

BKDBE

14

5

BKMBH

13

4

3

2

1

Bit 0

Name

BRKCT1

BRKAH

BRKAL

BRKDH

BRKDL

reserved

PORTG

PORTH

DDRG

BKMBL BK1RWE BK1RW BK0RWE BK0RW

Bit 15

Bit 7

Bit 15

Bit 7

0

12

4

11

3

10

2

9

1

Bit 8

Bit 0

Bit 8

Bit 0

0

6

5

14

13

12

11

10

9

6

5

4

3

2

1

0

PG7

PH7

DDG7

DDH7

PG6

PH6

DDG6

DDH6

PG5

PH5

DDG5

DDH5

PG4

PH4

DDG4

DDH4

PG3

PH3

DDG3

DDH3

PG2

PH2

DDG2

DDH2

PG1

PH1

DDG1

DDH1

PG0

PH0

DDG0

DDH0

DDRH

WI2CE KWIEG6 KWIEG5 KWIEG4 KWIEG3 KWIEG2 KWIEG1 KWIEG0

KWIEG

KWIEH

KWIFG

KWIFH

$002D KWIEH7 KWIEH6 KWIEH5 KWIEH4 KWIEH3 KWIEH2 KWIEH1 KWIEH0

$002E

$002F

0

KWIFG6 KWIFG5 KWIFG4 KWIFG3 KWIFG2 KWIFG1 KWIFG0

KWIFH7 KWIFH6 KWIFH5 KWIFH4 KWIFH3 KWIFH2 KWIFH1 KWIFH0

$0030–$

0037

(4)

Reserved

Unimplemented

$0038

$0039

$003A

$003B

$003C

$003D

$003E

$003F

$0040

$0041

$0042

$0043

$0044

$0045

$0046

$0047

$0048

$0049

$004A

0

SYN5

SYN4

SYN3

SYN2

SYN1

SYN0

SYNR

REFDV

0

REFDV2 REFDV1 REFDV0

0

Reserved

PLLFLG

PLLCR

LOCKIF

LOCKIE

0

LOCK

0

LHIF

LHIE

0

LHOME

NOLHM

0

PLLON

AUTO

ACQ

0

PSTP

MCS

SLDV2

0

BCSP

BCSS

0

CLKSEL

SLOW

0

SLDV5

SLDV4

SLDV3

0

SLDV1

0

SLDV0

0

Reserved

PWCLK

CON23

PCLK3

0

CON01

PCKA2

PCKA1

PCKA0

PPOL3

PCKB2

PPOL2

PCKB1

PPOL1

PCKB0

PPOL0

PCLK2

PCLK1

PCLK0

PWPOL

0

Bit 6

6

0

5

0

4

PWEN3 PWEN2 PWEN1 PWEN0

PWEN

0

3

2

1

Bit 0

PWPRES

PWSCAL0

PWSCNT0

PWSCAL1

PWSCNT1

PWCNT0

PWCNT1

PWCNT2

Bit 7

6

= Reserved or unimplemented bits.

Table 4-1. MC68HC912D60A Register Map (Sheet 2 of 9)

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

63

Registers

Address

$004B

$004C

$004D

$004E

$004F

$0050

$0051

$0052

$0053

$0054

$0055

$0056

$0057

$0058

$0059

$005A

$005B

$005C

$005D

$005E

$005F

$0060

$0061

$0062

$0063

$0064

$0065

$0066

$0067

$0068

$0069

Bit 7

6

5

4

3

2

1

Bit 0

PSBCK

0

Name

PWCNT3

PWPER0

PWPER1

PWPER2

PWPER3

PWDTY0

PWDTY1

PWDTY2

PWDTY3

PWCTL

Bit 7

0

6

5

4

3

2

1

6

5

4

3

2

1

6

5

4

3

2

1

6

5

4

3

2

1

6

5

4

3

2

1

6

5

4

3

2

1

6

5

4

3

2

1

6

5

4

3

2

1

6

5

4

3

2

1

0

PSWAI

CENTR

RDPP

PUPP

DISCR

PP7

DDP7

0

DISCP

DISCAL

0

PWTST

PP6

PP5

PP4

PP3

PP2

PP1

PP0

DDP0

0

PORTP

DDP6

DDP5

DDP4

DDP3

DDP2

DDP1

DDRP

0

Reserved

ATD0CTL0

ATD0CTL1

ATD0CTL2

ATD0CTL3

ATD0CTL4

ATD0CTL5

ATD0STAT0

ATD0STAT1

0

Reserved

ADPU

0

AFFC

0

ASWAI

0

DJM

0

R

ASCIE

FRZ1

PRS1

CB

ASCIF

FRZ0

PRS0

CA

S1C

PRS3

SC

FIFO

PRS2

CC

RES10

0

SMP1

S8C

0

SMP0

SCAN

0

PRS4

MULT

0

SCF

CCF7

SAR9

SAR1

0

CC2

CC1

CC0

CCF6

SAR8

SAR0

CCF5

SAR7

RST

CCF4

SAR6

TSTOUT

CCF3

SAR5

TST3

CCF2

SAR4

TST2

CCF1

SAR3

TST1

CCF0

SAR2 ATD0TESTH

TST0

ATD0TESTL

$006A–$

006E

0

Reserved

$006F

$0070

$0071

PAD07

Bit 15

Bit 7

PAD06

14

PAD05

PAD04

PAD03

PAD02

PAD01

PAD00

Bit 8

0

PORTAD0

ADR00H

ADR00L

13

0

12

0

11

0

10

0

9

0

Bit 6

= Reserved or unimplemented bits.

Table 4-1. MC68HC912D60A Register Map (Sheet 3 of 9)

Technical Data

64

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Registers

Register Block

Address

$0072

$0073

$0074

$0075

$0076

$0077

$0078

$0079

$007A

$007B

$007C

$007D

$007E

$007F

$0080

$0081

$0082

$0083

$0084

$0085

$0086

$0087

$0088

$0089

$008A

$008B

$008C

$008D

$008E

$008F

$0090

$0091

$0092

$0093

$0094

$0095

Bit 7

Bit 15

Bit 7

6

14

5

4

3

2

1

Bit 0

Bit 8

0

Name

ADR01H

ADR01L

ADR02H

ADR02L

ADR03H

ADR03L

ADR04H

ADR04L

ADR05H

ADR05L

ADR06H

ADR06L

ADR07H

ADR07L

TIOS

13

12

11

10

9

Bit 6

14

0

Bit 15

Bit 7

13

12

11

10

9

Bit 8

0

Bit 6

14

0

Bit 15

Bit 7

13

12

11

10

9

Bit 8

0

Bit 6

14

0

Bit 15

Bit 7

13

12

11

10

9

Bit 8

0

Bit 6

14

0

13

0

12

0

Bit 15

Bit 7

11

10

9

Bit 8

0

Bit 6

14

0

11

0

10

0

Bit 15

Bit 7

13

12

9

Bit 8

0

Bit 6

14

0

Bit 15

Bit 7

13

12

11

10

9

0

Bit 8

0

Bit 6

IOS6

FOC6

OC7M6

OC7D6

14

0

IOS7

FOC7

OC7M7

OC7D7

Bit 15

Bit 7

IOS5

FOC5

OC7M5

OC7D5

13

IOS4

FOC4

OC7M4

OC7D4

12

IOS3

FOC3

OC7M3

OC7D3

11

IOS2

FOC2

OC7M2

OC7D2

10

IOS1

FOC1

OC7M1

OC7D1

9

IOS0

FOC0

OC7M0

OC7D0

Bit 8

Bit 0

CFORC

OC7M

OC7D

TCNT

6

5

4

3

2

1

TCNT

TEN

TSWAI

TSBCK

TFFCA

Reserved

TSCR

Reserved

TQCR

OM7

OM3

EDG7B

EDG3B

C7I

OL7

OM6

OM2

EDG6B

EDG2B

C5I

PUPT

C5F

0

OL6

OL2

EDG6A

EDG2A

C4I

RDPT

C4F

0

OM5

OM1

EDG5B

EDG1B

C3I

TCRE

C3F

0

OL5

OL1

EDG5A

EDG1A

C2I

PR2

C2F

0

OM4

OL4

OL0

TCTL1

TCTL2

TCTL3

TCTL4

TMSK1

TMSK2

TFLG1

TFLG2

TC0

OL3

OM0

EDG7A

EDG4B

EDG4A

EDG0A

C0I

EDG3A

EDG0B

C6I

0

C1I

PR1

C1F

0

TOI

PR0

C0F

C7F

C6F

0

TOF

0

Bit 15

Bit 7

14

6

13

12

11

10

9

Bit 8

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

5

4

3

2

1

TC0

Bit 15

Bit 7

14

6

13

12

11

10

9

TC1

5

4

3

2

1

TC1

Bit 15

Bit 7

14

6

13

12

11

10

9

TC2

5

4

3

2

1

TC2

= Reserved or unimplemented bits.

Table 4-1. MC68HC912D60A Register Map (Sheet 4 of 9)

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

65

Registers

Address

$0096

$0097

$0098

$0099

$009A

$009B

$009C

$009D

$009E

$009F

$00A0

$00A1

$00A2

$00A3

$00A4

$00A5

$00A6

$00A7

$00A8

$00A9

$00AA

$00AB

$00AC

$00AD

$00AE

$00AF

$00B0

$00B1

$00B2

$00B3

$00B4

$00B5

$00B6

$00B7

$00B8

$00B9

Bit 7

6

14

6

5

13

5

4

12

4

3

2

1

Bit 0

Bit 8

Name

TC3

Bit 15

Bit 7

Bit 15

Bit 7

Bit 15

Bit 7

Bit 15

Bit 7

Bit 15

Bit 7

0

11

10

9

3

2

1

Bit 0

TC3

14

6

13

5

12

4

11

10

9

Bit 8

TC4

3

2

1

Bit 0

TC4

14

6

13

5

12

4

11

10

9

Bit 8

TC5

3

2

1

Bit 0

TC5

14

6

13

5

12

4

11

10

9

Bit 8

TC6

3

2

1

Bit 0

TC6

14

6

13

5

12

4

11

10

9

1

Bit 8

TC7

3

2

Bit 0

TC7

PAEN

0

PAMOD PEDGE

CLK1

CLK0

PAOVI

PAOVF

1

PAI

PACTL

PAFLG

PACN3

PACN2

PACN1

PACN0

MCCTL

MCFLG

ICPACR

DLYCT

ICOVW

ICSYS

Reserved

TIMTST

PORTT

DDRT

PBCTL

PBFLG

PA3H

0

5

0

PAIF

Bit 0

Bit 7

MCZI

MCZF

0

6

4

3

2

6

4

3

2

1

Bit 0

6

4

1

Bit 0

6

4

3

2

1

Bit 0

MODMC RDMCL

ICLAT

FLMC

POLF3

PA3EN

0

MCEN

POLF2

PA2EN

0

MCPR1

POLF1

PA1EN

DLY1

MCPR0

POLF0

PA0EN

DLY0

0

NOVW7 NOVW6 NOVW5 NOVW4 NOVW3 NOVW2 NOVW1 NOVW0

SH37

0

SH26

SH15

SH04

TFMOD

PACMX

BUFEN

LATQ

0

PT5

DDT5

0

PT4

DDT4

0

PT3

DDT3

0

TCBYP

0

PT7

DDT7

0

PT6

PT2

PT1

PT0

DDT0

0

DDT6

DDT2

DDT1

PBEN

0

PBOVI

0

6

0

PBOVF

0

Bit 7

Bit 15

Bit 7

Bit 15

Bit 7

5

4

3

2

1

9

1

9

1

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

6

5

4

3

2

PA2H

6

5

4

3

2

PA1H

6

5

4

3

2

PA0H

14

6

13

5

12

4

11

3

10

2

MCCNTH

MCCNTL

TC0H

14

6

13

5

12

4

11

3

10

2

= Reserved or unimplemented bits.

Table 4-1. MC68HC912D60A Register Map (Sheet 5 of 9)

Technical Data

66

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Registers

Register Block

Address

$00BA

$00BB

$00BC

$00BD

$00BE

$00BF

$00C0

$00C1

$00C2

$00C3

$00C4

Bit 7

Bit 15

Bit 7

6

14

5

13

4

12

3

2

10

1

9

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

SBR8

SBR0

PT

Name

TC1H

11

6

5

4

3

2

1

TC1H

Bit 15

Bit 7

14

13

12

11

10

9

TC2H

6

5

4

3

11

2

1

TC2H

Bit 15

Bit 7

14

13

12

10

9

TC3H

6

5

4

3

2

1

TC3H

BTST

SBR7

LOOPS

TIE

BSPL

SBR6

WOMS

TCIE

TC

BRLD

SBR5

RSRC

RIE

RDRF

MDL1

0

SBR12

SBR4

M

SBR11

SBR3

WAKE

TE

SBR10

SBR2

ILT

SBR9

SBR1

PE

SC0BDH

SC0BDL

SC0CR1

SC0CR2

SC0SR1

SC0SR2

SC0DRH

SC0DRL

SC1BDH

SC1BDL

SC1CR1

SC1CR2

SC1SR1

SC1SR2

SC1DRH

SC1DRL

SP0CR1

SP0CR2

SP0BR

SP0SR

Reserved

SP0DR

PORTS

DDRS

ILIE

IDLE

MDL0

0

RE

NF

RWU

FE

SBK

PF

TDRE

OR

0

$00C5 SCSWAI

MIE

T8

0

RAF

0

$00C6

$00C7

$00C8

$00C9

$00CA

$00CB

$00CC

R8

R7/T7

BTST

SBR7

LOOPS

TIE

0

R6/T6

BSPL

SBR6

WOMS

TCIE

TC

R5/T5

BRLD

SBR5

RSRC

RIE

RDRF

0

R4/T4

SBR12

SBR4

M

R3/T3

SBR11

SBR3

WAKE

TE

R2/T2

SBR10

SBR2

ILT

R1/T1

SBR9

SBR1

PE

R0/T0

SBR8

SBR0

PT

ILIE

IDLE

0

RE

NF

RWU

FE

SBK

PF

TDRE

OR

0

$00CD SCSWAI

0

RAF

0

$00CE

$00CF

$00D0

$00D1

$00D2

$00D3

$00D4

$00D5

$00D6

$00D7

$00D8

$00D9

R8

R7/T7

SPIE

0

T8

0

R6/T6

SPE

0

R5/T5

SWOM

0

R4/T4

MSTR

0

R3/T3

CPOL

0

R2/T2

CPHA

0

R1/T1

SSOE

SPSWAI

SPR1

0

R0/T0

LSBF

SPC0

SPR0

0

SPR2

0

SPIF

0

WCOL

0

MODF

0

Bit 7

PS7

DDS7

0

6

5

4

3

2

1

Bit 0

PS0

DDS0

0

PS6

DDS6

0

PS5

DDS5

0

PS4

DDS4

0

PS3

DDS3

0

PS2

DDS2

0

PS1

DDS1

0

Reserved

PURDS

0

RDPS2

RDPS1

RDPS0

0

PUPS2

PUPS1

PUPS0

$00DA–

$00DF

0

Reserved

$00E0–

$00ED

(4)

Reserved

EEDIVH

Unimplemented

$00EE

0

EEDIV9 EEDIV8

= Reserved or unimplemented bits.

Table 4-1. MC68HC912D60A Register Map (Sheet 6 of 9)

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

67

Registers

Address

$00EF

Bit 7

6

5

4

3

2

1

Bit 0

Name

EEDIVL

EEDIV7 EEDIV6 EEDIV5 EEDIV4 EEDIV3 EEDIV2 EEDIV1 EEDIV0

FPOPEN⁽⁵⁾

$00F0 NOBDML NOSHB Reserved

1

EESWAI PROTLCK

DMY

EEMCR

$00F1 SHPROT

1

0

1

BPROT4 BPROT3 BPROT2 BPROT1 BPROT0

EEPROT

Reserved

EEPROG

FEE32LCK

$00F2

$00F3

$00F4

$00F5

$00F6

$00F7

$00F8

$00F9

$00FA

$00FB

0

BULKP

AUTO

BYTE

ROW

ERASE

EELAT

EEPGM

LOCK

0

BOOTP FEE32MCR

0

Reserved

FEE32CTL

FEE28LCK

FEESWAI HVEN

ERAS

PGM

LOCK

0

BOOTP FEE28MCR

0

Reserved

FEESWAI HVEN

ERAS

PGM

FEE28CTL

$00FC–

$00FF

(4)

Reserved

Unimplemented

$0100

$0101

$0102

$0103

$0104

$0105

$0106

$0107

$0108

0

CSWAI

0

SYNCH TLNKEN SLPAK

SLPRQ SFTRES

WUPM CLKSRC

CMCR0

CMCR1

CBTR0

CBTR1

CRFLG

CRIER

CTFLG

CTCR

0

LOOPB

BRP2

SJW1

SAMP

SJW0

BRP5

BRP4

BRP3

BRP1

BRP0

TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10

WUPIF RWRNIF TWRNIF RERRIF TERRIF BOFFIF

WUPIE RWRNIE TWRNIE RERRIE TERRIE BOFFIE

OVRIF

OVRIE

TXE1

RXF

RXFIE

TXE0

0

ABTAK2 ABTAK1 ABTAK0

ABTRQ2 ABTRQ1 ABTRQ0

0

TXE2

TXEIE2

IDHIT2

TXEIE1

IDHIT1

TXEIE0

IDHIT0

0

IDAM1

IDAM0

CIDAC

$0109–

$010D

(4)

Reserved

Unimplemented

$010E RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 CRXERR

$010F TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0

CTXERR

CIDAR0

CIDAR1

CIDAR2

CIDAR3

CIDMR0

CIDMR1

CIDMR2

CIDMR3

CIDAR4

$0110

$0111

$0112

$0113

$0114

$0115

$0116

$0117

$0118

AC7

AM7

AC7

AC6

AM6

AC6

AC5

AM5

AC5

AC4

AM4

AC4

AC3

AM3

AC3

AC2

AM2

AC2

AC1

AM1

AC1

AC0

AM0

AC0

= Reserved or unimplemented bits.

Table 4-1. MC68HC912D60A Register Map (Sheet 7 of 9)

Technical Data

68

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Registers

Register Block

Address

$0119

$011A

$011B

$011C

$011D

$011E

$011F

Bit 7

AC7

AM7

6

5

4

3

2

1

Bit 0

AC0

AM0

Name

AC6

AM6

AC5

AM5

AC4

AM4

AC3

AM3

AC2

AM2

AC1

AM1

CIDAR5

CIDAR6

CIDAR7

CIDMR4

CIDMR5

CIDMR6

CIDMR7

$0120–

$013C

(4)

Reserved

Unimplemented

$013D

$013E

0

PUPCAN RDPCAN PCTLCAN

PCAN7

PCAN6

PCAN5

PCAN4

PCAN3

PCAN2

TxCAN

0

RxCAN PORTCAN

$013F DDCAN7 DDCAN6 DDCAN5 DDCAN4 DDCAN3 DDCAN2

0

DDRCAN

$0140–

RECEIVE BUFFER

$014F

RxFG

$0150–

TRANSMIT BUFFER 0

$015F

Tx0

Tx1

$0160–

TRANSMIT BUFFER 1

$016F

$0170–

TRANSMIT BUFFER 2

$017F

Tx2

$0180–

(4)

Reserved

Unimplemented

$01DF

$01E0

$01E1

$01E2

$01E3

$01E4

$01E5

$01E6

$01E7

$01E8

$01E9

Reserved

ATD1CTL0

ATD1CTL1

ATD1CTL2

ATD1CTL3

ATD1CTL4

ATD1CTL5

ATD1STAT0

ATD1STAT1

ADPU

0

AFFC

0

ASWAI

0

DJM

R

ASCIE

FRZ1

PRS1

CB

ASCIF

FRZ0

PRS0

CA

0

PRS4

MULT

0

S1C

PRS3

SC

FIFO

PRS2

CC

RES10

0

SMP1

S8C

0

SMP0

SCAN

0

SCF

CCF7

SAR9

SAR1

0

CC2

CC1

CC0

CCF6

SAR8

SAR0

CCF5

SAR7

RST

CCF4

SAR6

TSTOUT

CCF3

SAR5

TST3

CCF2

SAR4

TST2

CCF1

SAR3

TST1

CCF0

SAR2 ATD1TESTH

TST0

ATD1TESTL

$01EA–$

01EE

0

Reserved

$01EF

PAD17

PAD16

PAD15

PAD14

PAD13

PAD12

PAD11

PAD10

PORTAD1

= Reserved or unimplemented bits.

Table 4-1. MC68HC912D60A Register Map (Sheet 8 of 9)

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

69

Registers

Address

$01F0

$01F1

$01F2

$01F3

$01F4

$01F5

$01F6

$01F7

$01F8

$01F9

$01FA

$01FB

$01FC

$01FD

$01FE

$01FF

Bit 7

6

5

13

0

4

12

0

3

11

0

2

10

0

1

9

0

9

0

9

0

9

0

9

0

9

0

9

0

9

0

Bit 0

Bit 8

0

Name

Bit 15

Bit 7

14

ADR10H

ADR10L

ADR11H

ADR11L

ADR12H

ADR12L

ADR13H

ADR13L

ADR14H

ADR14L

ADR15H

ADR15L

ADR16H

ADR16L

ADR17H

ADR17L

Bit 6

14

Bit 15

Bit 7

13

0

12

0

11

0

10

0

Bit 8

0

Bit 6

14

Bit 15

Bit 7

13

0

12

0

11

0

10

0

Bit 8

0

Bit 6

14

Bit 15

Bit 7

13

0

12

0

11

0

10

0

Bit 8

0

Bit 6

14

Bit 15

Bit 7

13

0

12

0

11

0

10

0

Bit 8

0

Bit 6

14

Bit 15

Bit 7

13

0

12

0

11

0

10

0

Bit 8

0

Bit 6

14

Bit 15

Bit 7

13

0

12

0

11

0

10

0

Bit 8

0

Bit 6

14

Bit 15

Bit 7

13

0

12

0

11

0

10

0

Bit 8

0

Bit 6

= Reserved or unimplemented bits.

Table 4-1. MC68HC912D60A Register Map (Sheet 9 of 9)

1. Port A, port B and data direction registers DDRA, DDRB are not in map in expanded and peripheral modes.

2. Port E and DDRE not in map in peripheral mode; also not in map in expanded modes with EME set.

3. Registers also not in map in peripheral mode.

4. Data read at these locations is undefined.

5. The FPOPEN bit is available only on the 1L02H and later mask sets. For previous masks, this bit is reserved.

Technical Data

70

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Registers

Technical Data — MC68HC912D60A

Section 5. Operating Modes and Resource Mapping

5.1 Contents

5.2

5.3

5.4

5.5

5.6

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Background Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Internal Resource Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Memory Maps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

5.2 Introduction

Eight possible operating modes determine the operating configuration of

the MC68HC912D60A. Each mode has an associated default memory

map and external bus configuration. After reset, most system resources

can be mapped to other addresses by writing to the appropriate control

registers.

5.3 Operating Modes

The operating mode out of reset is determined by the states of the

BKGD, MODB, and MODA pins during reset.

The SMODN, MODB, and MODA bits in the MODE register show current

operating mode and provide limited mode switching during operation.

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

71

Operating Modes and Resource Mapping

The states of the BKGD, MODB, and MODA pins are latched into these

bits on the rising edge of the reset signal.

Table 5-1. Mode Selection

BKGD MODB MODA

Mode

Port A

G.P. I/O

Port B

G.P. I/O

ADDR

1

0

1

Normal Single Chip

Normal Expanded Narrow

ADDR/DATA

Reserved (Forced to

Peripheral)

1

0

—

1

0

1

0

1

0

1

0

1

Normal Expanded Wide

Special Single Chip

ADDR/DATA

G.P. I/O

ADDR/DATA

G.P. I/O

Special Expanded Narrow

Special Peripheral

ADDR/DATA

ADDR

ADDR/DATA

Special Expanded Wide

There are two basic types of operating modes:

Normal modes — some registers and bits are protected

against accidental changes.

Special modes — allow greater access to protected control

registers and bits for special purposes such as testing and

emulation.

For operation above 105°C, the MC68HC912D60A (M temperature

range product only) is limited to single chip modes of operation.

A system development and debug feature, background debug mode

(BDM), is available in all modes. In special single-chip mode, BDM is

active immediately after reset.

5.3.1 Normal Operating Modes

These modes provide three operating configurations. Background

debugging is available in all three modes, but must first be enabled for

some operations by means of a BDM background command, then

activated.

Technical Data

72

MC68HC912D60A — Rev. 3.1

Operating Modes and Resource Mapping

Freescale Semiconductor

Operating Modes and Resource Mapping

Operating Modes

Normal Single-Chip Mode — There are no external address

and data buses in this mode. The MCU operates as a stand-

alone device and all program and data resources are on-chip.

External port pins normally associated with address and data

buses can be used for general-purpose I/O.

Normal Expanded Wide Mode — This is a normal mode of

operation in which the expanded bus is present with a 16-bit

data bus. Ports A and B are used for the 16-bit multiplexed

address/data bus.

Normal Expanded Narrow Mode — This is a normal mode of

operation in which the expanded bus is present with an 8-bit

data bus. Ports A and B are used for the16-bit address bus.

Port A is used as the data bus, multiplexed with addresses. In

this mode, 16-bit data is presented one byte at a time, the high

byte followed by the low byte. The address is automatically

incremented on the second cycle.

5.3.2 Special Operating Modes

There are three special operating modes that correspond to normal

operating modes. These operating modes are commonly used in factory

testing and system development. In addition, there is a special

peripheral mode, in which an external master, such as an I.C. tester, can

control the on-chip peripherals.

Special Single-Chip Mode — This mode can be used to force

the MCU to active BDM mode to allow system debug through

the BKGD pin. There are no external address and data buses

in this mode. The MCU operates as a stand-alone device and

all program and data space are on-chip. External port pins can

be used for general-purpose I/O.

Special Expanded Wide Mode — This mode can be used for

emulation of normal expanded wide mode and emulation of

normal single-chip mode. Ports A and B are used for the 16-bit

multiplexed address/data bus.

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

73

Operating Modes and Resource Mapping

Special Expanded Narrow Mode — This mode can be used

for emulation of normal expanded narrow mode. Ports A and B

are used for the16-bit address bus. Port A is used as the data

bus, multiplexed with addresses. In this mode, 16-bit data is

presented one byte at a time, the high byte followed by the low

byte. The address is automatically incremented on the second

cycle.

Special Peripheral Mode — The CPU is not active in this

mode. An external master can control on-chip peripherals for

testing purposes. It is not possible to change to or from this

mode without going through reset. Background debugging

should not be used while the MCU is in special peripheral

mode as internal bus conflicts between BDM and the external

master can cause improper operation of both modes.

5.4 Background Debug Mode

Background debug mode (BDM) is an auxiliary operating mode that is

used for system development. BDM is implemented in on-chip hardware

and provides a full set of debug operations. Some BDM commands can

be executed while the CPU is operating normally. Other BDM

commands are firmware based, and require the BDM firmware to be

enabled and active for execution.

In special single-chip mode, BDM is enabled and active immediately out

of reset. BDM is available in all other operating modes, but must be

enabled before it can be activated. BDM should not be used in special

peripheral mode because of potential bus conflicts.

Once enabled, background mode can be made active by a serial

command sent via the BKGD pin or execution of a CPU12 BGND

instruction. While background mode is active, the CPU can interpret

special debugging commands, and read and write CPU registers,

peripheral registers, and locations in memory.

While BDM is active, the CPU executes code located in a small on-chip

ROM mapped to addresses $FF20 to $FFFF, and BDM control registers

are accessible at addresses $FF00 to $FF06. The BDM ROM replaces

Technical Data

74

MC68HC912D60A — Rev. 3.1

Operating Modes and Resource Mapping

Freescale Semiconductor

Operating Modes and Resource Mapping

Background Debug Mode

the regular system vectors while BDM is active. While BDM is active, the

user memory from $FF00 to $FFFF is not in the map except through

serial BDM commands.

Bit 7

6

5

4

3

IVIS

1

2

1

0

Bit 0

SMODN

MODB

MODA

ESTR

EBSWAI

EME

RESET:

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Special Single Chip

Special Exp Nar

Peripheral

1

Special Exp Wide

Normal Single Chip

Normal Exp Nar

Normal Exp Wide

$000B

0

MODE — Mode Register

MODE controls the MCU operating mode and various configuration

options. This register is not in the map in peripheral mode

SMODN, MODB, MODA — Mode Select Special, B and A

These bits show the current operating mode and reflect the status of

the BKGD, MODB and MODA input pins at the rising edge of reset.

SMODN is Read anytime. May only be written in special modes

(SMODN = 0). The first write is ignored;

MODB, MODA may be written once in Normal modes (SMODN = 1).

Write anytime in special modes (first write is ignored) – special

peripheral and reserved modes cannot be selected.

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

75

Operating Modes and Resource Mapping

ESTR — E Clock Stretch Enable

Determines if the E Clock behaves as a simple free-running clock or

as a bus control signal that is active only for external bus cycles.

ESTR is always 1 in expanded modes since it is required for address

and data bus de-multiplexing and must follow stretched cycles.

0 = E never stretches (always free running).

1 = E stretches high during external access cycles and low during

non-visible internal accesses (IVIS=0).

Normal modes: write once; Special modes: write anytime. Read

anytime.

IVIS — Internal Visibility

This bit determines whether internal ADDR, DATA, R/W and LSTRB

signals can be seen on the external bus during accesses to internal

locations. In Special Narrow Mode if this bit is set and an internal

access occurs the data will appear wide on Ports A and B. This serves

the same function as the EMD bit of the non-multiplexed versions of

the HC12 and allows for emulation. Visibility is not available when the

part is operating in a single-chip mode.

0 = No visibility of internal bus operations on external bus.

1 = Internal bus operations are visible on external bus.

Normal modes: write once; Special modes: write anytime EXCEPT

the first time. Read anytime.

EBSWAI — External Bus Module Stop in Wait Control

This bit controls access to the external bus interface when in wait

mode. The module will delay before shutting down in wait mode to

allow for final bus activity to complete.

0 = External bus and registers continue functioning during wait mode.

1 = External bus is shut down during wait mode.

Normal modes: write anytime; Special modes: write never. Read

anytime.

Technical Data

76

MC68HC912D60A — Rev. 3.1

Operating Modes and Resource Mapping

Freescale Semiconductor

Operating Modes and Resource Mapping

Internal Resource Mapping

EME — Emulate Port E

In single-chip mode PORTE and DDRE are always in the map

regardless of the state of this bit.

0 = PORTE and DDRE are in the memory map.

1 = If in an expanded mode, PORTE and DDRE are removed from the

internal memory map. Removing the registers from the map allows

the user to emulate the function of these registers externally.

Normal modes: write once; special modes: write anytime EXCEPT

the first time. Read anytime.

5.5 Internal Resource Mapping

The internal register block, RAM, and EEPROM have default locations

within the 64K byte standard address space but may be reassigned to

other locations during program execution by setting bits in mapping

registers INITRG, INITRM, and INITEE. During normal operating modes

these registers can be written once. It is advisable to explicitly establish

these resource locations during the initialization phase of program

execution, even if default values are chosen, in order to protect the

registers from inadvertent modification later.

Writes to the mapping registers go into effect between the cycle that

follows the write and the cycle after that. To assure that there are no

unintended operations, a write to one of these registers should be

followed with a NOP instruction.

If conflicts occur when mapping resources, the register block will take

precedence over the other resources; RAM or EEPROM addresses

occupied by the register block will not be available for storage. When

active, BDM ROM takes precedence over other resources, although a

conflict between BDM ROM and register space is not possible. The

following table shows resource mapping precedence.

In expanded modes, all address space not used by internal resources is

by default external memory.

The MC68HC912D60A contains 60K bytes of Flash EEPROM

nonvolatile memory which can be used to store program code or static

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

77

Operating Modes and Resource Mapping

data. It is made of the 28K byte FEE28 array mapped from $1000 to

$7FFF at reset and of the 32 K byte FEE32 array mapped from $8000 to

$FFFF at reset. MAPROM bit in the MISC register allows the swapping

of the two flash arrays.

Table 5-2. Mapping Precedence

Precedence

Resource

BDM ROM (if active)

Register Space

1

2

3

4

5

6

RAM

EEPROM

On-Chip Flash EEPROM (MC68HC912D60A)

External Memory

5.5.1 Register Block Mapping

After reset the 512 byte register block resides at location $0000 but can

be reassigned to any 2K byte boundary within the standard 64K byte

address space. Mapping of internal registers is controlled by five bits in

the INITRG register. The register block occupies the first 512 bytes of the

2K byte block.

Bit 7

REG15

0

6

REG14

0

5

REG13

0

4

REG12

0

3

REG11

0

2

0

1

0

Bit 0

MMSWAI

0

RESET:

INITRG — Initialization of Internal Register Position Register

$0011

REG[15:11] — Internal register map position

These bits specify the upper five bits of the 16-bit registers address.

Normal modes: write once; special modes: write anytime. Read

anytime.

Technical Data

78

MC68HC912D60A — Rev. 3.1

Operating Modes and Resource Mapping

Freescale Semiconductor

Operating Modes and Resource Mapping

Internal Resource Mapping

MMSWAI — Memory Mapping Interface Stop in Wait Control

This bit controls access to the memory mapping interface when in

Wait mode.

Normal modes: write anytime; special modes: write never. Read

anytime.

0 = Memory mapping interface continues to function during Wait

mode.

1 = Memory mapping interface access is shut down during Wait

mode.

5.5.2 RAM Mapping

The MC68HC912D60A has 2K byte of fully static RAM that is used for

storing instructions, variables, and temporary data during program

execution. After reset, RAM addressing begins at location $0000 but can

be assigned to any 2K byte boundary within the standard 64K byte

address space. Mapping of internal RAM is controlled by five bits in the

INITRM register.

After reset, the first 512 bytes of RAM have their access inhibited by the

presence of the register address space. After initial MCU configuration,

it is recommended to map the register space at location $0800.

Bit 7

6

5

RAM13

0

4

RAM12

0

3

RAM11

0

2

0

1

0

Bit 0

RAM15

0

RAM14

0

RESET:

INITRM — Initialization of Internal RAM Position Register

$0010

RAM[15:11] — Internal RAM map position

These bits specify the upper five bits of the 16-bit RAM address.

Normal modes: write once; special modes: write anytime. Read

anytime.

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

79

Operating Modes and Resource Mapping

5.5.3 EEPROM Mapping

The MC68HC912D60A has 1K bytes of EEPROM which is activated by

the EEON bit in the INITEE register. Mapping of internal EEPROM is

controlled by four bits in the INITEE register. After reset EEPROM

address space begins at location $0C00 but can be mapped to any 4K

byte boundary within the standard 64K byte address space.

Bit 7

EE15

0

6

EE14

0

5

EE13

0

4

EE12

0

3

0

2

0

1

0

Bit 0

EEON

1

RESET:

INITEE— Initialization of Internal EEPROM Position Register

$0012

EE[15:12] — Internal EEPROM map position

These bits specify the upper four bits of the 16-bit EEPROM address.

Normal modes: write once; special modes: write anytime. Read

anytime.

EEON — internal EEPROM On (Enabled)

This bit is forced to one in single-chip modes.

Read or write anytime.

0 = Removes the EEPROM from the map.

1 = Places the on-chip EEPROM in the memory map at the address

selected by EE[15:12].

Technical Data

80

MC68HC912D60A — Rev. 3.1

Operating Modes and Resource Mapping

Freescale Semiconductor

Operating Modes and Resource Mapping

Internal Resource Mapping

5.5.4 Miscellaneous System Control Register

Additional mapping and external resource controls are available. To use

external resources the part must be operated in one of the expanded

modes.

Bit 7

6

5

4

3

2

1

Bit 0

MAPROM

NDRF

RFSTR1 RFSTR0 EXSTR1 EXSTR0 ROMON28 ROMON32

RESET:

0

1

0

1

0

1

Exp Modes

SC Modes

MISC — Miscellaneous Mapping Control Register

$0013

Normal modes: write once; Special modes: write anytime. Read

anytime.

MAPROM — Map Location of ROM

This bit is used to swap the location of the on-chip Flash EEPROM.

0 = 28K byte array is mapped from $1000 to $7FFF, 32K byte array

is mapped from $8000 to $FFFF.

1 = 28K byte is mapped from $9000 to $FFFF, 32K byte array is

mapped from $0000 to $7FFF.

NDRF — Narrow Data Bus for Register-Following Map Space

This bit enables a narrow bus feature for the 512 byte Register-

Following Map. This is useful for accessing 8-bit peripherals and

allows 8-bit and 16-bit external memory devices to be mixed in a

system. In Expanded Narrow (eight bit) modes, Single Chip Modes,

and Peripheral mode, this bit has no effect.

0 = Makes Register-Following MAP space act as a full 16 bit data bus.

1 = Makes the Register-Following MAP space act the same as an 8

bit only external data bus (data only goes through port A externally).

The Register-Following space is mapped from $0200 to $03FF after

reset, which is next to the register map. If the registers are moved this

space follows.

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

81

Operating Modes and Resource Mapping

RFSTR1, RFSTR0 — Register Following Stretch

This two bit field determines the amount of clock stretch on accesses

to the 512 byte Register Following Map. It is valid regardless of the

state of the NDRF bit. In Single Chip and Peripheral Modes this bit

has no meaning or effect.

Table 5-3. RFSTR Stretch Bit Definition

Number of E Clocks

RFSTR1

RFSTR0

Stretched

0

1

0

1

0

1

0

1

2

3

EXSTR1, EXSTR0 — External Access Stretch

This two bit field determines the amount of clock stretch on accesses

to the External Address Space. In Single Chip and Peripheral Modes

this bit has no meaning or effect.

Table 5-4. EXSTR Stretch Bit Definition

Number of E Clocks

EXSTR1

EXSTR0

Stretched

0

1

0

1

0

1

0

1

2

3

ROMON28, ROMON32 — Enable bits for ROM

These bits are used to enable the Flash EEPROM arrays FEE28 and

FEE32 respectively.

0 = Corresponding Flash EEPROM array disabled from the memory

map.

1 = Corresponding Flash EEPROM array enabled in the memory

map.

Technical Data

82

MC68HC912D60A — Rev. 3.1

Operating Modes and Resource Mapping

Freescale Semiconductor

Operating Modes and Resource Mapping

Memory Maps

5.6 Memory Maps

The following diagrams illustrate the memory map for each mode of

operation immediately after reset.

$0000

$01FF

REGISTERS

(MAPPABLE TO ANY 2K SPACE)

$0000

$0200

$0800

$0C00

$1000

$0000

$07FF

2K bytes RAM

(MAPPABLE TO ANY 2K SPACE)

$0C00

$0FFF

1K bytes EEPROM

(MAPPABLE TO ANY 4K SPACE)

$1000

28K Flash EEPROM (FEE28)

$6000 - $7FFF Protected BOOT

$8000

EXT

$7FFF

$8000

32K Flash EEPROM (FEE32)

$E000 –$FFFF Protected BOOT

$FFFF

$FF00

$FFFF

BDM

(if active)

$FF00

VECTORS

$FFFF

VECTORS

NORMAL

SINGLE CHIP

EXPANDED

SPECIAL

SINGLE CHIP

Figure 5-1. MC68HC912D60A Memory Map

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

83

Operating Modes and Resource Mapping

Technical Data

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

84

Operating Modes and Resource Mapping

Technical Data — MC68HC912D60A

Section 6. Bus Control and Input/Output

6.1 Contents

6.2

6.3

6.4

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Detecting Access Type from External Signals . . . . . . . . . . . . .85

Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

6.2 Introduction

Internally the MC68HC912D60A has full 16-bit data paths, but

depending upon the operating mode and control registers, the external

multiplexed bus may be 8 or 16 bits. There are cases where 8-bit and

16-bit accesses can appear on adjacent cycles using the LSTRB signal

to indicate 8- or 16-bit data.

It is possible to have a mix of 8 and 16 bit peripherals attached to the

external multiplexed bus, using the NDRF bit in the MISC register while

in expanded wide modes.

6.3 Detecting Access Type from External Signals

The external signals LSTRB, R/W, and A0 can be used to determine the

type of bus access that is taking place. Accesses to the internal RAM

module are the only type of access that produce LSTRB = A0 = 1,

because the internal RAM is specifically designed to allow misaligned

16-bit accesses in a single cycle. In these cases the data for the address

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

85

Bus Control and Input/Output

that was accessed is on the low half of the data bus and the data for

address + 1 is on the high half of the data bus.

Figure 6-1. Access Type vs. Bus Control Pins

LSTRB

A0

0

R/W

Type of Access

1

0

1

0

1

0

1

8-bit read of an even address

8-bit read of an odd address

8-bit write of an even address

8-bit write of an odd address

16-bit read of an even address

1

0

1

0

16-bit read of an odd address

(low/high data swapped)

1

0

1

0

1

0

16-bit write to an even address

(low/high data swapped)

6.4 Registers

Not all registers are visible in the MC68HC912D60A memory map under

certain conditions. In special peripheral mode the first 16 registers

associated with bus expansion are removed from the memory map.

In expanded modes, some or all of port A, port B, and port E are used

for expansion buses and control signals. In order to allow emulation of

the single-chip functions of these ports, some of these registers must be

rebuilt in an external port replacement unit. In any expanded mode, port

A, and port B, are used for address and data lines so registers for these

ports, as well as the data direction registers for these ports, are removed

from the on-chip memory map and become external accesses.

In any expanded mode, port E pins may be needed for bus control (e.g.,

ECLK, R/W). To regain the single-chip functions of port E, the emulate

port E (EME) control bit in the MODE register may be set. In this special

case of expanded mode and EME set, PORTE and DDRE registers are

removed from the on-chip memory map and become external accesses

so port E may be rebuilt externally.

Technical Data

86

MC68HC912D60A — Rev. 3.1

Bus Control and Input/Output

Freescale Semiconductor

Bus Control and Input/Output

Registers

Bit 7

PA7

—

6

5

4

3

2

1

Bit 0

PA0

—

Single Chip

RESET:

PA6

—

PA5

—

PA4

—

PA3

—

PA2

—

PA1

—

Expanded ADDR15/ ADDR14/ ADDR13/ ADDR12/ ADDR11/ ADDR10/

& Periph: DATA15 DATA14 DATA13 DATA12 DATA11 DATA10

ADDR9/

DATA9

ADDR8/

DATA8

Expanded ADDR15/ ADDR14/ ADDR13/ ADDR12/ ADDR11/ ADDR10/

narrow DATA15/ DATA14/ DATA13/ DATA12/ DATA11/ DATA10/

DATA7 DATA6 DATA5 DATA4 DATA3 DATA2

ADDR9/

DATA9/

DATA1

ADDR8/

DATA8/

DATA0

PORTA — Port A Register

$0000

Bits PA[7:0] are associated respectively with addresses ADDR[15:8],

DATA[15:8] and DATA[7:0], in narrow mode. When this port is not used

for external addresses such as in single-chip mode, these pins can be

used as general-purpose I/O. DDRA determines the primary direction of

each pin. This register is not in the on-chip map in expanded and

peripheral modes. Read and write anytime.

Bit 7

6

5

DDA5

0

4

DDA4

0

3

DDA3

0

2

DDA2

0

1

DDA1

0

Bit 0

DDA0

0

DDA7

0

DDA6

0

RESET:

DDRA — Port A Data Direction Register

$0002

This register determines the primary direction for each port A pin when

functioning as a general-purpose I/O port. DDRA is not in the on-chip

map in expanded and peripheral modes. Read and write anytime.

0 = Associated pin is a high-impedance input

1 = Associated pin is an output

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

87

Bus Control and Input/Output

Bit 7

PB7

—

6

5

4

3

2

1

Bit 0

PB0

—

Single Chip

RESET:

PB6

—

PB5

—

PB4

—

PB3

—

PB2

—

PB1

—

Expanded

& Periph:

ADDR7/

DATA7

ADDR6/

DATA6

ADDR5/

DATA5

ADDR4/

DATA4

ADDR3/

DATA3

ADDR2/

DATA2

ADDR1/

DATA1

ADDR0/

DATA0

Expanded

narrow

ADDR7

ADDR6

ADDR5

ADDR4

ADDR3

ADDR2

ADDR1

ADDR0

PORTB — Port B Register

$0001

Bits PB[7:0] are associated with addresses ADDR[7:0] and DATA[7:0]

(except in narrow mode) respectively. When this port is not used for

external addresses such as in single-chip mode, these pins can be used

as general-purpose I/O. DDRB determines the primary direction of each

pin. This register is not in the on-chip map in expanded and peripheral

modes. Read and write anytime.

Bit 7

6

5

DDB5

0

4

DDB4

0

3

DDB3

0

2

DDB2

0

1

DDB1

0

Bit 0

DDB0

0

DDB7

0

DDB6

0

RESET:

DDRB — Port B Data Direction Register

$0003

This register determines the primary direction for each port B pin when

functioning as a general-purpose I/O port. DDRB is not in the on-chip

map in expanded and peripheral modes. Read and write anytime.

0 = Associated pin is a high-impedance input

1 = Associated pin is an output

Technical Data

88

MC68HC912D60A — Rev. 3.1

Bus Control and Input/Output

Freescale Semiconductor

Bus Control and Input/Output

Registers

BIT 7

PE7

—

6

5

4

3

2

1

BIT 0

PE0

—

PE6

—

PE5

—

PE4

—

PE3

—

PE2

—

PE1

—

RESET:

DBE or

ECLK or

CAL

MODB or

IPIPE1 or

CGMTST

LSTRB or

BDTAGL or

TAGLO

Alt. Pin

Function

MODA or

IPIPE0

ECLK

R/W

IRQ

XIRQ

PORTE — Port E Register

$0008

This register is associated with external bus control signals and interrupt

inputs, including data bus enable (DBE), mode select (MODB/IPIPE1,

MODA/IPIPE0), ECLK, size (LSTRB), read/write (R/W), IRQ, and XIRQ.

When the associated pin is not used for one of these specific functions,

the pin can be used as general-purpose I/O. The port E assignment

register (PEAR) selects the function of each pin. DDRE determines the

primary direction of each port E pin when configured to be general-

purpose I/O.

Some of these pins have software selectable pull-ups (DBE, LSTRB,

R/W, IRQ, and XIRQ). A single control bit enables the pull-ups for all

these pins which are configured as inputs.

This register is not in the map in peripheral mode or expanded modes

when the EME bit is set.

Read and write anytime.

Bit 7

6

5

DDE5

0

4

DDE4

0

3

DDE3

0

2

DDE2

0

1

0

Bit 0

DDE7

0

DDE6

0

RESET:

DDRE — Port E Data Direction Register

$0009

This register determines the primary direction for each port E pin

configured as general-purpose I/O.

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

89

Bus Control and Input/Output

0 = Associated pin is a high-impedance input

1 = Associated pin is an output

PE[1:0] are associated with XIRQ and IRQ and cannot be configured as

outputs. These pins can be read regardless of whether the alternate

interrupt functions are enabled.

This register is not in the map in peripheral mode and expanded modes

while the EME control bit is set.

Read and write anytime.

BIT 7

6

5

4

3

2

1

BIT 0

NDBE

CGMTE

PIPOE

NECLK

LSTRE

RDWE

CALE

DBENE

Normal

Expanded

RESET:

0

Special

Expanded

RESET:

0

1

0

1

0

1

0

1

0

1

0

Peripheral

Normal

single chip

Special

single chip

RESET:

0

1

0

1

0

PEAR — Port E Assignment Register

$000A

The PEAR register is used to choose between the general-purpose I/O

functions and the alternate bus control functions of port E. When an

alternate control function is selected, the associated DDRE bits are

overridden.

The reset condition of this register depends on the mode of operation

because bus-control signals are needed immediately after reset in some

modes.

In normal single-chip mode, no external bus control signals are needed

so all of port E is configured for general-purpose I/O.

Technical Data

90

MC68HC912D60A — Rev. 3.1

Bus Control and Input/Output

Freescale Semiconductor

Bus Control and Input/Output

Registers

In normal expanded modes, the reset vector is located in external

memory. The DBE and ECLK are required for de-multiplexing address

and data, but LSTRB and R/W are only needed by the system when

there are external writable resources. Therefore in normal expanded

modes, only the DBE and ECLK are configured for their alternate bus

control functions and the other bits of port E are configured for general-

purpose I/O. If the normal expanded system needs any other bus-control

signals, PEAR would need to be written before any access that needed

the additional signals.

In special expanded modes, DBE, IPIPE1, IPIPE0, E, LSTRB, and R/W

are configured as bus-control signals.

In peripheral mode, the PEAR register is not accessible for reads or

writes. However, the CGMTE control bit is reset to one to configure PE6

as a test output from the PLL module.

NDBE — No Data Bus Enable

Normal: write once; Special: write anytime EXCEPT the first. Read

anytime.

0 = PE7 is used for DBE, external control of data enable on

memories, or inverted ECLK.

1 = PE7 is the CAL function if CALE bit is set in PEAR register or

general-purpose I/O.

NDBE controls the use of the DBE pin of Port E. The NDBE bit has no

effect in Single Chip or Peripheral Modes. The associated pin will

default to the CAL function if the CALE bit is set in PEAR register or

otherwise to an I/O.

CGMTE — Clock Generator Module Testing Enable

Normal: write never; Special: write anytime EXCEPT the first. Read

anytime.

0 = PE6 is general-purpose I/O or pipe output.

1 = PE6 is a test signal output from the CGM module (no effect in

single chip or normal expanded modes). PIPOE = 1 overrides

this function and forces PE6 to be a pipe status output signal.

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

91

Bus Control and Input/Output

PIPOE — Pipe Status Signal Output Enable

Normal: write once; Special: write anytime EXCEPT the first time.

Read anytime.

0 = PE[6:5] are general-purpose I/O (if CGMTE = 1, PE6 is a test

output signal from the CGM module).

1 = PE[6:5] are outputs and indicate the state of the instruction

queue (only effective in expanded modes).

NECLK — No External E Clock

Normal single chip: write once; special single chip: write anytime; all

other modes: write never. Read anytime. In peripheral mode, E is an

input and in all other modes, E is an output.

0 = PE4 is the external ECLK pin subject to the following limitation:

In single-chip modes, to get an ECLK output signal, it is

necessary to have ESTR = 0 in addition to NECLK = 0.

1 = PE4 is a general-purpose I/O pin.

LSTRE — Low Strobe (LSTRB) Enable

Normal: write once; Special: write anytime EXCEPT the first time.

Read anytime. This bit has no effect in single-chip modes or normal

expanded narrow mode.

0 = PE3 is a general-purpose I/O pin.

1 = PE3 is configured as the LSTRB bus-control output, provided

the MCU is not in single chip or normal expanded narrow

modes.

LSTRB is used during external writes. After reset in normal expanded

mode, LSTRB is disabled. If needed, it should be enabled before

external writes. External reads do not normally need LSTRB because

all 16 data bits can be driven even if the MCU only needs 8 bits of

data.

In normal expanded narrow mode this pin is reset to an output driving

high allowing the pin to be an output while in and immediately after

reset.

TAGLO is a shared function of the PE3/LSTRB pin. In special

expanded modes with LSTRE set and the BDM tagging on, a zero at

the falling edge of E tags the instruction word low byte being read into

the instruction queue.

Technical Data

92

MC68HC912D60A — Rev. 3.1

Bus Control and Input/Output

Freescale Semiconductor

Bus Control and Input/Output

Registers

RDWE — Read/Write Enable

Normal: write once; Special: write anytime EXCEPT the first time.

Read anytime. This bit has no effect in single-chip modes.

0 = PE2 is a general-purpose I/O pin.

1 = PE2 is configured as the R/W pin. In single chip modes, RDWE

has no effect and PE2 is a general-purpose I/O pin.

R/W is used for external writes. After reset in normal expanded mode,

it is disabled. If needed it should be enabled before any external

writes.

CALE — Calibration Reference Enable

Read and write anytime.

0 = Calibration reference is disabled and PE7 is general-purpose

I/O in single chip or peripheral modes or if the NDBE bit is set.

1 = Calibration reference is enabled on PE7 in single chip and

peripheral modes or if the NDBE bit is set.

DBENE — DBE or Inverted E Clock on Port E[7]

Normal modes: write once. Special modes: write anytime EXCEPT

the first; read anytime.

DBENE controls which signal is output on PE7 when NDBE control bit

is cleared. The inverted ECLK output can be used to latch the address

for demultiplexing. It has the same behaviour as the ECLK, except it

is inverted. Please note that in the case of idle expansion bus, the ‘not

ECLK’ signal could stay high for many cycles.

The DBNE bit has no effect in single chip or peripheral modes and

PE7 is defaulted to the CAL function if the CALE bit is set in the PEAR

register or to an I/O otherwise.

0 = PE7 pin used for DBE external control of data enable on

memories in expanded modes when NDBE = 0

1 = PE7 pin used for inverted ECLK output in expanded modes

when NDBE = 0

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

93

Bus Control and Input/Output

Bit 7

PUPH

1

6

PUPG

1

5

0

4

PUPE

1

3

0

2

0

1

PUPB

0

Bit 0

PUPA

0

RESET:

PUCR — Pull-Up Control Register

$000C

These bits select pull-up resistors for any pin in the corresponding port

that is currently configured as an input. This register is not in the map in

peripheral mode.

Read and write anytime.

PUPH — Pull-Up or Pull-Down Port H Enable

0 = Port H pull-ups are disabled.

1 = Enable pull-up/down devices for all port H input pins.

PUPG — Pull-Up or Pull-Down Port G Enable

0 = Port G pull-ups are disabled.

1 = Enable pull-up/down devices for all port G input pins.

PUPE — Pull-Up Port E Enable

0 = Port E pull-ups on PE7 and PE[3:0] are disabled.

1 = Enable pull-up devices for port E input pins PE7 and PE[3:0].

PUPB — Pull-Up Port B Enable

0 = Port B pull-ups are disabled.

1 = Enable pull-up devices for all port B input pins.

This bit has no effect if port B is being used as part of the address/data

bus (the pull-ups are inactive).

PUPA — Pull-Up Port A Enable

0 = Port A pull-ups are disabled.

1 = Enable pull-up devices for all port A input pins.

This bit has no effect if port A is being used as part of the address/data

bus (the pull-ups are inactive).

Technical Data

94

MC68HC912D60A — Rev. 3.1

Bus Control and Input/Output

Freescale Semiconductor

Bus Control and Input/Output

Registers

Bit 7

6

RDPH

0

5

RDPG

0

4

0

3

RDPE

0

2

0

1

RDPB

0

Bit 0

RDPA

0

RESET:

RDRIV — Reduced Drive of I/O Lines

$000D

These bits select reduced drive for the associated port pins. This gives

reduced power consumption and reduced RFI with a slight increase in

transition time (depending on loading). The reduced drive function is

independent of which function is being used on a particular port.

This register is not in the map in peripheral mode.

Normal: write once; Special: write anytime EXCEPT the first time. Read

anytime.

RDPH — Reduced Drive of Port H

0 = All port H output pins have full drive enabled.

1 = All port H output pins have reduced drive capability.

RDPG — Reduced Drive of Port G

0 = All port G output pins have full drive enabled.

1 = All port G output pins have reduced drive capability.

RDPE — Reduced Drive of Port E

0 = All port E output pins have full drive enabled.

1 = All port E output pins have reduced drive capability.

RDPB — Reduced Drive of Port B

0 = All port B output pins have full drive enabled.

1 = All port B output pins have reduced drive capability.

RDPA — Reduced Drive of Port A

0 = All port A output pins have full drive enabled.

1 = All port A output pins have reduced drive capability.

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

Technical Data

95

Bus Control and Input/Output

Technical Data

MC68HC912D60A — Rev. 3.1

Freescale Semiconductor

96

Bus Control and Input/Output

Technical Data — MC68HC912D60A

Section 7. Flash Memory

7.1 Contents