MC9S08MP12E2VLC [FREESCALE]
8-Bit HCS08 Central Processor Unit (CPU); 8位HCS08中央处理单元(CPU)的型号: | MC9S08MP12E2VLC |
厂家: | Freescale |
描述: | 8-Bit HCS08 Central Processor Unit (CPU) |
文件: | 总36页 (文件大小:763K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MC9S08MP16
Rev. 1, 10/2009
48-LQFP
Case 932-03
32-LQFP
Case 873A-03
MC9S08MP16 Series Data
Sheet
28-SOIC
Case 751F-05
Features
•
8-Bit HCS08 Central Processor Unit (CPU)
– Up to 51.34 MHz CPU at 2.7V to 5.5V across temperature
range of –40°C to 105°C
– PGA — Differential programmable gain amplifier with
programmable gain (x1, x2, x4, x8, x16, or x32)
– HSCMP — Three fast analog comparators with positive and
negative inputs; separately selectable interrupt on rising and
falling comparator output; filtering; windowing; HSCMP1 and
HSCMP2 outputs can be optionally routed to FTM1 module;
runs in stop3
– Up to 40 MHz CPU at 2.7V to 5.5V across temperature range
of –40°C to 125°C
– HC08 instruction set with added BGND instruction and
additional addressing modes for LDHX and STHX
– Support for up to 48 interrupt/reset sources
On-Chip Memory
•
– Up to 16 KB flash memory; read/program/erase over full
operating voltage and temperature
– DAC — Three 5-bit digital to analog convertor used as a
32-tap voltage reference for each comparator
– Up to 1 KB random-access memory (RAM)
– Security circuitry to prevent unauthorized access to RAM and
flash memory contents
– PDB — Two programmable delay blocks: PDB1 synchronizes
PWM with samples of ADC; PDB2 synchronizes PWM with
comparing window of analog comparators
– SCI — Full duplex non-return to zero (NRZ); LIN master
extended break generation; LIN slave extended break
detection; wake up on active edge
– SPI — Full-duplex or single-wire bidirectional;
Double-buffered transmit and receive; Master or Slave mode;
MSB-first or LSB-first shifting
– IIC/SMBus — Up to 400 kbps; Multi-master operation;
Programmable slave address; Interrupt driven byte-by-byte
data transfer; supports broadcast mode and 10-bit addressing;
SMBus compatible
– FTM — Two Flextimers with total of 8 channels; One
2-channel (FTM1) and one 6-channel (FTM2); supports
operation up to 2x bus clock; selectable input capture, output
compare, edge- or center-aligned PWM; dead time insertion;
fault inputs
– MTIM — 8-bit modulo counter with 8-bit prescaler
– RTC — (Real-time counter) 8-bit modulus counter with
binary or decimal based prescaler; External clock source for
precise time base, time-of-day, calendar or task scheduling;
Free running on-chip low power oscillator (1 kHz) for cyclic
wake-up without external components, runs in all MCU modes
– CRC — Cyclic redundancy check generator
– KBI — Three 8 channel keyboard interrupt module with
software selectable polarity on edge or edge/level modes
Input/Output
•
•
Power-Saving Modes
– Two low power stop modes; reduced power wait mode
– Peripheral clock gating can disable clocks to unused modules
Clock Source Options
– Oscillator (XOSC) — Loop-control Pierce oscillator; Crystal
or ceramic resonator range of 31.25–38.4 kHz or 1–16 MHz
– Internal Clock Source (ICS) — Containing a
frequency-locked-loop (FLL) controlled by internal or
external reference; precision trimming of internal reference
allows 0.2% resolutions and 2% deviation over temperature
and voltage; supports CPU frequencies up to 51.34 MHz
System Protection
– Watchdog computer operating properly (COP) reset running
from dedicated 1-kHz internal clock source or bus clock
– Low-voltage detection with reset or interrupt; selectable trip
points
•
•
– Illegal opcode and illegal address detection with reset
– Flash memory block protection
Development Support
– Single-wire background debug interface
– Breakpoint capability to allow single breakpoint setting during
in-circuit debugging (plus three more breakpoints in on-chip
debug module)
– On-chip in-circuit emulator (ICE) debug module containing
three comparators and nine trigger modes. Eight deep FIFO for
storing change-of-flow addresses and event-only data. Debug
module supports both tag and force breakpoints
Peripherals
– IPC — Interrupt Priority Controller with 4 programmable
interrupt priority levels
– ADC — 13-channel, 12-bit resolution; 2.5 μs conversion time;
automatic compare function; 1.7 mV/°C temperature sensor;
internal bandgap reference channel; operation in stop3
•
•
– 40 GPIOs, 2 output-only pins.
– Hysteresis and configurable pull up device on input pins;
Configurable slew rate and drive strength on output pins;
Sink/Source current up to 20mA
Package Options
– 48-LQFP, 32-LQFP, 28-SOIC
•
– 48-LQFP qualified for automotive usage
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale Semiconductor, Inc., 2009. All rights reserved.
Table of Contents
1
2
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2.13 Programmable Gain Amplifier (PGA) Characteristics . 26
2.14 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.14.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.14.2 FTM Module Timing . . . . . . . . . . . . . . . . . . . . . 28
2.14.3 MTIM Module Timing . . . . . . . . . . . . . . . . . . . . 29
2.14.4 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.15 Flash Memory Specifications. . . . . . . . . . . . . . . . . . . . 33
2.16 EMC Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.16.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . . 33
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.1 Device Numbering Scheme. . . . . . . . . . . . . . . . . . . . . 35
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Related Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.2 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . .9
2.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . .9
2.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .10
2.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . .11
2.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .15
2.8 External Oscillator (XOSC) Characteristics . . . . . . . . .20
2.9 Internal Clock Source (ICS) Characteristics . . . . . . . . .21
2.10 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.11 Digital to Analog (DAC) Characteristics . . . . . . . . . . . .26
2.12 High Speed Comparator (HSCMP) Characteristics . . .26
3
4
5
6
MC9S08MP16 Series Data Sheet, Rev. 1
2
Freescale Semiconductor
ON-CHIP ICE
DEBUG MODULE (DBG)
Interrupt Priority Controller
(IPC)
CYCLIC REDUNDANCY
HCS08 CORE
CHECK (CRC)
CPU
INT
KBI1P[7:0]
KBI2P[7:0]
KBI3P[7:0]
8-BIT KEYBOARD
PTA7/SPSCK
PTA6/MOSI
INTERRUPT (KBI1)
BKGD
BKP
PTA5/SCL/MISO
PTA4/TCLK/SDA/SS
PTA3/SCL/FTM1CH1
PTA2/SDA/FTM1CH0
PTA1/SCL/RxD
8-BIT KEYBOARD
HCS08 SYSTEM CONTROL
INTERRUPT (KBI2)
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
BKGD/MS
RESET
8-BIT KEYBOARD
INTERRUPT (KBI3)
PTA0/SDA/TxD
COP
LVD
SCL
SDA
IIC MODULE (IIC)
PTB7/KBI1P7/ADP7/C3IN4
(Only on MC9S08MP16)
PTB6/KBI1P6/CMP3OUT/ADP6/C3IN3
PTB5/KBI1P5/CMP2OUT/ADP5/C2IN4
PTB4/KBI1P4/ADP4/C2IN3
PTB3/KBI1P3/ADP3/C3IN2/PGA-
PTB2/KBI1P2/ADP2/C1IN2/PGA+
PTB1/KBI1P1/ADP1/C2IN2
FTM1CH[1:0]
2-CHANNEL FLEXTIMER
USER FLASH
TCLK
FTM1FAULT
(FTM1)
(MC9S08MP16 = 16384 BYTES)
(MC9S08MP12 = 12288 BYTES)
FTM2CH[5:0]
PTB0/KBI1P0/ADP0/CIN1
6-CHANNEL FLEXTIMER
TCLK
FTM2FAULT
USER RAM
(FTM2)
PTC7/KBI2P7/TCLK
PTC6/KBI2P6/FTM2FAULT
PTC5/KBI2P5/FTM2CH5
PTC4/KBI2P4/FTM2CH4
PTC3/KBI2P3/FTM2CH3
PTC2/KBI2P2/FTM2CH2
PTC1/KBI2P1/FTM2CH1
PTC0/KBI2P0/FTM2CH0
(MC9S08MP16 = 1024 BYTES)
(MC9S08MP12 = 512 BYTES)
8-BIT MODULO TIMER
TCLK
(MTIM)
50.33 MHz INTERNAL CLOCK
TxD
RxD
SERIAL COMMUNICATIONS
SOURCE (ICS)
INTERFACE (SCI)
XTAL
LOW-POWER OSCILLATOR
31.25 kHz to 38.4 kHz
1 MHz to 16 MHz
SS
PTD7/KBI3P7/CMP3OUT
PTD6/KBI3P6/CMP2OUT
PTD5/KBI3P5/CMP1OUT
PTD4/KBI3P4/PDB2OUT
PTD3/KBI3P3/FTM1FAULT
PTD2/KBI3P2/PDB1OUT
PTD1/KBI3P1/SCL
EXTAL
SPSCK
MISO
MOSI
SERIAL PERIPHERAL
(XOSC)
INTERFACE (SPI)
REAL TIME
PROGRAMMABLE DELAY
PDB1OUT
PDB2OUT
COUNTER (RTC)
BLOCK (PDB1)
PROGRAMMABLE DELAY
PTD0/KBI3P0/SDA
BLOCK (PDB2)
VREFH
VREFL
PTE6/EXTAL
PTE5/XTAL
PTE4/ADP12/C1IN4
PTE3/ADP11/C1IN3
PTE2/ADP10
12-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC)
ADP12–ADP0
VDDA/VREFH
VSSA/VREFL
VDD1
PGA+
PGA–
VOLTAGE
VSS1
VDD2
VSS2
PTE1/ADP9
PTE0/ADP8
PROGRAMMABLE
GAIN AMPLIFIER (PGA
REGULATOR
)
(Only on MC9S08MP16)
CIN1
C1IN2
PTF2
PTF1/RESET
PTF0/BKGD/MS
DIGITAL-TO-ANALOG
HIGH SPEED ANALOG
C1IN3
C1IN4
CMP1OUT
CONVERTER (DAC1)
COMPARATOR (HSCMP1
)
)
)
C2IN2
C2IN3
C2IN4
DIGITAL-TO-ANALOG
HIGH SPEED ANALOG
CONVERTER (DAC2)
pins not available on 28-pin packages
pins not available on 32-pin or 28-pin packages
COMPARATOR (HSCMP2
CMP2OUT
C3IN2
C3IN3
C3IN4
DIGITAL-TO-ANALOG
HIGH SPEED ANALOG
CONVERTER (DAC3)
COMPARATOR (HSCMP3
CMP3OUT
Notes: When PTF1 is configured as RESET, pin becomes bi-directional with output being open-drain drive containing an internal pull-up device.
When PTF0 is configured as BKGD, pin becomes bi-directional.
VDD2 pad is tied internally on 32-pin and 28-pin packages,
VSS2 pad is tied internally on 28-pin packages
Figure 1. MC9S08MP16 Series Block Diagram
MC9S08MP16 Series Data Sheet, Rev. 1
Freescale Semiconductor
3
Pin Assignments
1
Pin Assignments
This section shows the pin assignments for the MC9S08MP16 Series devices.
1
36
35
34
33
32
31
30
29
28
27
26
25
PTC4/KBI2P4/FTM2CH4
PTC5/KBI2P5/FTM2CH5
PTC6/KBI2P6/FTM2FAULT
PTC7/KBI2P7/TCLK
PTD0/KBI3P0/SDA
PTD1/KBI3P1/SCL
PTD2/KBI3P2/PDB1OUT
PTD3/KBI3P3/FTM1FAULT
VSS1
PTB4/KBI1P4/ADP4/C2IN3
PTE4/ADP12/C1IN4
2
3
PTE3/ADP11/C1IN3
4
V
SSA/VREFL
5
VDDA/VREFH
6
PTB3/KBI1P3/ADP3/C3IN2/PGA–
PTB2/KBI1P2/ADP2/C1IN2/PGA+
PTB1/KBI1P1/ADP1/C2IN2
PTB0/KBI1P0/ADP0/CIN1
PTE2/ADP10
7
8
9
VDD1
10
11
12
PTA0/SDA/TxD
PTE1/ADP9
PTE0/ADP8
PTA1/SCL/RxD
Note: Pins in bold are lost in the next
lower pin count package.
Figure 2. MC9S08MP16 Series in 48-LQFP
MC9S08MP16 Series Data Sheet, Rev. 1
4
Freescale Semiconductor
Pin Assignments
32 31 30 29 28 27 26 25
PTC2/KBI2P2/FTM2CH2
PTC3/KBI2P3/FTM2CH3
PTC4/KBI2P4/FTM2CH4
PTB5/KBI1P5/CMP2OUT/ADP5/C2IN4
PTB4/KBI1P4/ADP4/C2IN3
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VSSA/VREFL
VDDA/VREFH
PTC5/KBI2P5/FTM2CH5
PTC6/KBI2P6/FTM2FAULT
VSS1
PTB3/KBI1P3/ADP3/C3IN2/PGA–
PTB2/KBI1P2/ADP2/C1IN2/PGA+
PTB1/KBI1P1/ADP1/C2IN2
PTB0/KBI1P0/ADP0/CIN1
VDD1
PTA0/SDA/TxD
9
10 11 12 13 14 15 16
Note: Pins in bold are lost in the next
lower pin count package.
Figure 3. MC9S08MP16 Series in 32-Pin LQFP Package
MC9S08MP16 Series Data Sheet, Rev. 1
Freescale Semiconductor
5
Pin Assignments
PTC0/KBI2P0/FTM2CH0
PTC1/KBI2P1/FTM2CH1
PTC2/KBI2P2/FTM2CH2
PTC3/KBI2P3/FTM2CH3
PTC4/KBI2P4/FTM2CH4
PTC5/KBI2P5/FTM2CH5
PTC6/KBI2P6/FTM2FAULT
VSS1
PTF0/BKGD/MS
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PTB6/KBI1P6/CMP3OUT/ADP6/C3IN3
PTB5/KBI1P5/CMP2OUT/ADP5/C2IN4
PTB4/KBI1P4/ADP4/C2IN3
2
3
4
V
SSA/VREFL
5
VDDA/VREFH
6
PTB3/KBI1P3/ADP3/C3IN2/PGA–
PTB2/KBI1P2/ADP2/C1IN2/PGA+
PTB1/KBI1P1/ADP1/C2IN2
PTB0/KBI1P0/ADP0/CIN1
PTA7/SPSCK
7
8
VDD1
9
PTA0/SDA/TxD
10
11
12
13
14
PTA1/SCL/RxD
PTA2/SDA/FTM1CH0
PTA3/SCL/FTM1CH1
PTA6/MOSI
PTA5/SCL/MISO
PTA4/TCLK/SDA/SS
PTF1/RESET
Figure 4. MC9S08MP16 Series in 28-Pin SOIC Package
MC9S08MP16 Series Data Sheet, Rev. 1
6
Freescale Semiconductor
Pin Assignments
Table 1. Pin Availability by Package Pin-Count
Pin Number <-- Lowest Priority --> Highest
32
LQFP
48
28
Port Pin
Alt 1
Alt 2
Alt3
Alt4
1
2
3
5
PTC4
KBI2P4
FTM2CH4
FTM2CH5
FTM2FAULT
TCLK1
4
6
PTC5
PTC6
PTC7
PTD0
PTD1
PTD2
PTD3
KBI2P5
KBI2P6
KBI2P7
KBI3P0
KBI3P1
KBI3P2
KBI3P3
3
5
7
4
—
—
—
—
—
6
—
—
—
—
—
8
5
SDA5
6
SCL5
7
PDB1OUT
FTM1FAULT
8
9
VSS1
10
11
12
13
14
15
16
17
18
7
9
VDD1
8
10
11
12
13
—
—
—
—
14
PTA0
PTA1
PTA2
PTA3
PTD4
PTD5
PTD6
PTD7
PTF1
PTF2
PTA4
PTA5
PTA6
PTA7
PTE0
PTE1
PTE2
PTB0
PTB1
PTB2
PTB3
SDA5
TxD
9
SCL5
RxD
10
11
—
—
—
—
12
SDA5
FTM1CH0
FTM1CH1
PDB2OUT
CMP1OUT
CMP2OUT2
CMP3OUT3
SCL5
KBI3P4
KBI3P5
KBI3P6
KBI3P7
4
19
20
21
22
23
24
25
26
RESET
—
13
14
15
16
—
—
—
17
18
19
20
21
22
—
—
15
16
17
18
—
—
—
19
20
21
22
23
24
—
TCLK1
SDA5
SCL5
SS
MISO
MOSI
SPSCK
ADP8
ADP9
ADP10
ADP06
ADP16
ADP26
ADP36
27
28
29
30
31
32
33
34
KBI1P0
KBI1P1
KBI1P2
KBI1P3
CIN16
C2IN26
C1IN26
C3IN26
PGA+6
PGA–6
VDDA/VREFH
VSSA/VREFL
PTE3
ADP116
C1IN36
MC9S08MP16 Series Data Sheet, Rev. 1
Freescale Semiconductor
7
Electrical Characteristics
Table 1. Pin Availability by Package Pin-Count (continued)
Pin Number <-- Lowest Priority --> Highest
32
LQFP
48
28
Port Pin
Alt 1
Alt 2
Alt3
Alt4
35
36
37
38
39
40
41
42
43
44
45
46
47
PTE4
ADP126
C1IN46
ADP46
—
23
24
25
26
27
28
29
—
25
26
27
—
—
—
—
—
28
1
PTB4
PTB5
PTB6
PTB7
PTE5
PTE6
KBI1P4
C2IN36
KBI1P5
KBI1P6
KBI1P7
XTAL
CMP2OUT2 ADP56
CMP3OUT3 ADP66
ADP76
C2IN46
C3IN36
C3IN46
EXTAL
VSS2
VDD2
—
30
31
32
1
PTF0
PTC0
PTC1
PTC2
PTC3
BKGD
MS
KBI2P0
KBI2P1
KBI2P2
KBI2P3
FTM2CH0
FTM2CH1
FTM2CH2
FTM2CH3
2
3
48
1
2
4
TCLK pin can be repositioned using TCLKPS in SOPT2. Default reset location is PTC7.
2
3
4
HSCMP2 output CMP2OUT can be repositioned using the CMP2OPS in the SOPT2 register.
Default reset location is PTD6.
HSCMP3 output CMP3OUT can be repositioned using the CMP3OPS in the SOPT2 register.
Default reset location is PTD7.
Pin is open drain with an internal pullup that is always enabled. Pin does not contain a clamp
diode to VDD and should not be driven above VDD. The voltage measured on the internally
pulled up RESET will not be pulled to VDD. The internal gates connected to this pin are pulled
to VDD
.
5
6
IIC pins SDA and SCL can be repositioned using IICPS in SOPT2. Default reset locations are
PTD0 and PTD1.
If ADC, HSCMP, or PGA is enabling a shared analog input pin, each has access to the pin.
2
Electrical Characteristics
2.1
Introduction
This section contains electrical and timing specifications for the MC9S08MP16 Series of microcontrollers available at the time
of publication.
MC9S08MP16 Series Data Sheet, Rev. 1
8
Freescale Semiconductor
Electrical Characteristics
2.2
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:
Table 2. Parameter Classifications
P
C
Those parameters that are guaranteed during production testing on each individual device.
Those parameters that are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
Those parameters that are achieved by design characterization on a small sample size from typical
devices under typical conditions unless otherwise noted. All values shown in the typical column are within
this category.
T
D
Those parameters that are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
2.3
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the
limits specified in Table 3 may affect device reliability or cause permanent damage to the device. For functional operating
conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised
that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for
instance, either V or V ) or the programmable pull-up resistor associated with the pin is enabled.
SS
DD
Table 3. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Supply voltage
VDD
IDD
VIn
ID
–0.3 to +5.8
120
V
mA
V
Maximum current into VDD
Digital input voltage
–0.3 to VDD + 0.3
± 25
Instantaneous maximum current
mA
Single pin limit (applies to all port pins)1, 2, 3
Storage temperature range
Tstg
–55 to 150
°C
1
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2
3
All functional non-supply pins, except for PTF1/RESET are internally clamped to VSS and VDD
.
Power supply must maintain regulation within operating VDD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
I
DD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).
MC9S08MP16 Series Data Sheet, Rev. 1
Freescale Semiconductor
9
Electrical Characteristics
2.4
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power
dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and
it is user-determined rather than being controlled by the MCU design. To take P into account in power calculations, determine
I/O
the difference between actual pin voltage and V or V and multiply by the pin current for each I/O pin. Except in cases of
SS
DD
unusually high pin current (heavy loads), the difference between pin voltage and V or V will be very small.
SS
DD
Table 4. Thermal Characteristics
Consumer &
Industrial
Num
C
Rating
Symbol
Automotive
Unit
1
2
3
—
D
Operating temperature range (packaged)
Maximum junction temperature
Thermal resistance 1,2
single-layer board
TA
TJ
–40 to 105
115
–40 to 125
135
°C
°C
D
48-pin LQFP
32-pin LQFP
28-pin SOIC
80
85
71
80
—
—
θJA
°C/W
4
D
Thermal resistance 1,2
four-layer board
48-pin LQFP
32-pin LQFP
28-pin SOIC
56
57
48
56
—
—
θJA
°C/W
1
2
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
Junction-to-ambient natural convection
The average chip-junction temperature (T ) in °C can be obtained from:
J
T = T + (P × θ )
JA
Eqn. 1
J
A
D
where:
T = Ambient temperature, °C
A
θ
= Package thermal resistance, junction-to-ambient, °C/W
JA
P = P + P
D
int
I/O
P
P
= I × V , Watts — chip internal power
= Power dissipation on input and output pins — user determined
int
I/O
DD DD
For most applications, P << P and can be neglected. An approximate relationship between P and T (if P is neglected)
I/O
int
D
J
I/O
is:
P = K ÷ (T + 273°C)
Eqn. 2
Eqn. 3
D
J
Solving Equation 1 and Equation 2 for K gives:
K = P × (T + 273°C) + θ × (P )
2
D
A
JA
D
MC9S08MP16 Series Data Sheet, Rev. 1
10
Freescale Semiconductor
Electrical Characteristics
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring P (at equilibrium)
D
for a known T . Using this value of K, the values of P and T can be obtained by solving Equation 1 and Equation 2 iteratively
A
D
J
for any value of T .
A
2.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions should be taken to avoid exposure to static discharge. Qualification tests are performed to ensure
that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During
the device qualification, ESD stresses were performed for the human body model (HBM) and the charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless instructed otherwise in the device specification.
Table 5. ESD and Latch-up Test Conditions
Model
Description
Series resistance
Symbol
Value
Unit
Human
Body
R1
C
1500
100
3
Ω
Storage capacitance
pF
Number of pulses per pin
—
Latch-up Minimum input voltage limit
Maximum input voltage limit
– 2.5
7.5
V
V
Table 6. ESD and Latch-Up Protection Characteristics
No.
Rating1
Symbol
Min
Max
Unit
1
2
3
Human body model (HBM)
Charge device model (CDM)
Latch-up current at TA = 105°C
VHBM
VCDM
ILAT
± 2000
± 500
± 100
—
—
—
V
V
mA
1
Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
2.6
DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics.
Table 7. DC Characteristics
Num C
Characteristic
Symbol
Condition
Min
Typ1
Max
Unit
1
2
3
— Operating Voltage
VDD
2.7
—
—
0
5.5
V
(2)
(2)
— Analog Supply voltage delta to VDD (VDD – VDDA
)
ΔVDDA
ΔVSSA
±100
±100
mV
mV
— Analog Ground voltage delta to VSS (VSS – VSSA
)
—
0
MC9S08MP16 Series Data Sheet, Rev. 1
Freescale Semiconductor
11
Electrical Characteristics
Table 7. DC Characteristics (continued)
Num C
Characteristic
Symbol
Condition
Min
Typ1
Max
Unit
C
All I/O pins (except PTF1/RESET)
low-drive strength
5 V, ILoad = –4 mA VDD – 1.5
5 V, ILoad = –2 mA VDD – 0.8
3 V, ILoad = –1 mA VDD – 0.8
5 V, ILoad = –20 mA VDD – 1.5
5 V, ILoad = –10 mA VDD – 0.8
3 V, ILoad = –5 mA VDD – 0.8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
P
C Output high
VOH
—
V
4
5
6
C voltage
—
P
high-drive strength
—
C
—
D Output high current
Max total IOH for all ports IOHT
All I/O pins
VOUT < VDD
5 V, ILoad = 4 mA
5 V, ILoad = 2 mA
3 V, ILoad = 1 mA
5 V, ILoad = 20 mA
5 V, ILoad = 10 mA
3 V, ILoad = 5 mA
5 V, ILoad = 3.2 mA
5 V, ILoad = 1.6 mA
3 V, ILoad = 0.8 mA
VOUT > VSS
0
–100
1.5
mA
V
C
—
P
(except PTF1/RESET)
—
0.8
C
low-drive strength
All I/O pins
VOL
—
0.8
C
—
1.5
P Output low
(Except PTF1/RESET)
high-drive strength
PTF1/RESET
—
0.8
C voltage
—
0.8
7
8
9
C
P
C
—
1.5
—
0.8
—
0.8
10 D Output low current
Max total IOL for all ports
IOLT
VIH
0
0.65 x VDD
0.7 x VDD
—
100
—
mA
V
P Input high voltage; all digital inputs
5V
11
12
C
3V
—
P Input low voltage; all digital inputs
C
VIL
5V
0.35 x VDD
0.35 x VDD
V
3V
—
13 C Input hysteresis
Vhys
0.06 x VDD
—
V
14 P Input leakage current (per pin)
|IIn|
VIn = VDD or VSS
—
1
μA
P
Hi-Z (off-state) leakage current (per pin)
input/output port pins |IOZ|
VIn = VDD or VSS
VIn = VDD or VSS
—
—
—
—
1
2
μA
μA
15
16
PTF1/RESET,
PTE5/XTAL pins
Pullup or Pulldown3 resistors; when enabled
P
I/O pins RPU,RPD
PTF1/RESET4
RPU
17
17
37
37
52
52
kΩ
kΩ
C
D DC injection current 5, 6, 7, 8
Single pin limit
VIN > VDD
VIN < VSS
0
0
0
0
—
—
—
—
2
–0.2
25
mA
mA
mA
mA
17
IIC
Total MCU limit, includes
sum of all stressed pins
VIN > VDD
VIN < VSS
–5
MC9S08MP16 Series Data Sheet, Rev. 1
12
Freescale Semiconductor
Electrical Characteristics
Table 7. DC Characteristics (continued)
Num C
Characteristic
Symbol
Condition
Min
Typ1
Max
Unit
13 C Input Capacitance, all pins
14 C RAM retention voltage
15 C POR re-arm voltage9
16 D POR re-arm time
CIn
—
—
—
0.6
1.4
—
8
pF
V
VRAM
VPOR
tPOR
1.0
2.0
—
0.9
10
V
μs
P Low-voltage detection threshold —
high range
VLVD1
VLVD0
VLVW3
VLVW2
VLVW1
17
VDD falling
VDD rising
3.9
4.0
4.0
4.1
4.1
4.2
V
V
V
V
V
P Low-voltage detection threshold —
low range
18
VDD falling
VDD rising
2.48
2.54
2.56
2.62
2.64
2.70
P Low-voltage warning threshold —
high range 1
19
VDD falling
VDD rising
4.5
4.6
4.6
4.7
4.7
4.8
P Low-voltage warning threshold —
high range 0
20
VDD falling
4.2
4.3
4.3
4.4
4.4
4.5
VDD rising
P Low-voltage warning threshold
low range 1
21
VDD falling
VDD rising
2.84
2.90
2.92
2.98
3.00
3.06
P Low-voltage warning threshold —
low range 0
VLVW0
22
VDD falling
VDD rising
2.66
2.72
2.74
2.80
2.82
2.88
V
T
Low-voltage inhibit reset/recover hysteresis
Vhys
5 V
3 V
—
—
100
60
—
—
23
mV
24 P Bandgap voltage reference at 25°C10
1.18
1.17
1.202
—
1.21
1.22
V
V
VBG
Bandgap voltage reference across temperature
range10
25
P
1
2
3
4
Typical values are measured at 25°C. Characterized, not tested
DC potential difference.
When keyboard interrupt is configured to detect rising edges, pulldown resistors are used in place of pullup resistors.
The specified resistor value is the actual value internal to the device. The pullup value may measure higher when measured externally
on the pin.
5
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If
positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply
going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk
when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce
overall power consumption).
6
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance
values for positive and negative clamp voltages, then use the larger of the two values.
MC9S08MP16 Series Data Sheet, Rev. 1
Freescale Semiconductor
13
Electrical Characteristics
All functional non-supply pins except PTF1/RESET are internally clamped to VSS and VDD
7
8
9
.
The PTF1/RESET pin does not have a clamp diode to VDD. Do not drive this pin above VDD
.
Maximum is highest voltage that POR is guaranteed.
10 Factory trimmed at VDD = 5.0 V
2
1.0
0.8
0.6
0.4
0.2
0
125°C
25°C
125°C
25°C
–40°C
Max 0.8V@5mA
Max 1.5V@20mA
–40°C
1.5
1
0.5
0
0
5
10
I
15
(mA)
20
25
0
2
4
6
8
10
I
(mA)
OL
OL
a) V = 5V, High Drive
b) V = 3V, High Drive
DD
DD
Figure 5. Typical V vs I , High Drive Strength (except PTF1/RESET)
OL
OL
2
1.5
1
1.0
0.8
0.6
0.4
0.2
0
125°C
25°C
125°C
25°C
–40°C
Max 0.8V@1mA
Max 1.5V@4mA
–40°C
0.5
0
0
1
2
I
3
4
5
0
0.4
0.8
1.2
(mA)
1.6
2.0
(mA)
I
OL
OL
a) V = 5V, Low Drive
b) V = 3V, Low Drive
DD
DD
Figure 6. Typical V vs I , Low Drive Strength (except PTF1/RESET)
OL
OL
MC9S08MP16 Series Data Sheet, Rev. 1
14
Freescale Semiconductor
Electrical Characteristics
2
1.5
1
1.0
0.8
0.6
0.4
0.2
0
125°C
25°C
125°C
25°C
Max 0.8V@ –5mA
Max 1.5V@ –20mA
–40°C
–40°C
0.5
0
0
–5
–10
–15
(mA)
–20
–25
0
–2
–4
–6
(mA)
–8
–10
I
I
OH
OH
a) V = 5V, High Drive
b) V = 3V, High Drive
DD
DD
Figure 7. Typical V – V vs I , High Drive Strength
DD
OH
OH
2
1.5
1
1.0
125°C
25°C
125°C
25°C
Max 0.8V@ –1mA
Max 1.5V@ –4mA
–40°C
–40°C
0.8
0.6
0.4
0.2
0
0.5
0
0
–1
–2
–3
(mA)
–4
–5
0
–0.4
–0.8
–1.2
(mA)
–1.6
–2.0
I
I
OH
OH
a) V = 5V, Low Drive
b) V = 3V, Low Drive
DD
DD
Figure 8. Typical V – V vs I , Low Drive Strength
DD
OH
OH
2.7
Supply Current Characteristics
This section includes information about power supply current in various operating modes.
Table 8. Supply Current Characteristics
VDD
(V)
Num
C
Parameter
Symbol
RIDD
Typ1
Max2
Unit
C
C
P
C
Run supply current3 measured at
(CPU clock = 4 MHz, fBus = 2 MHz)
5
3
5
3
2.16
1.8
3
1
2
mA
mA
2.5
7.5
7
Run supply current3 measured at
5.26
4.92
RIDD
(CPU clock = 16 MHz, fBus = 8 MHz)
MC9S08MP16 Series Data Sheet, Rev. 1
Freescale Semiconductor
15
Electrical Characteristics
Table 8. Supply Current Characteristics (continued)
VDD
Num
C
Parameter
Symbol
Typ1
Max2
Unit
mA
mA
mA
(V)
C
C
P
Run supply current4 measured at
5
3
5
3
5
3
9.4
9
10
10
30
20
30
—
3
4
5
RIDD
(CPU clock = 32 MHz, fBus = 16 MHz)
Run supply current5 measured at
14.3
13.9
16
RIDD
(CPU clock = 51.34 MHz, fBus = 25.67 MHz)
C
P
Run supply current measured at
RIDD
(CPU clock = 40 MHz, fBus = 20 MHz)
—
—
Wait mode supply current measured at
(CPU clock = 8 MHz, fBus = 4 MHz)
(FEI mode, all modules off)
6
C
WIDD
5
2.7
—
mA
Stop3 mode supply current
C
P
C
–40°C
0.96
1.3
7.5
37
—
—
25°C
85°C
25
90
150
—
5
μA
P6
P
105°C
7
125°C
–40°C
25°C
65
S3IDD
C
P
0.85
1.2
6.5
32.7
58
—
C
85°C
20
80
130
3
μA
P6
P
105°C
125°C
Stop2 mode supply current
C
P
C
–40°C
25°C
0.94
1.25
7
—
—
85°C
25
5
3
μA
μA
P6
P
105°C
30
65
8
125°C
–40°C
25°C
64
120
—
S2IDD
C
P
0.83
1.1
6.3
25
—
C
85°C
20
P6
P
105°C
55
125°C
57
100
500
500
C
RTC adder to stop2 or stop37
S23IDDRTC
5
3
300
300
nA
nA
9
MC9S08MP16 Series Data Sheet, Rev. 1
16
Freescale Semiconductor
Electrical Characteristics
Table 8. Supply Current Characteristics (continued)
VDD
Num
C
Parameter
Symbol
Typ1
Max2
Unit
(V)
C
LVD adder to stop3 (LVDE = LVDSE = 1)
S3IDDLVD
5
3
110
90
180
160
μA
μA
10
11
C
Adder to stop3 for oscillator enabled8
(EREFSTEN =1)
S3IDDOSC
5,3
5
8
μA
1
Typical values are based on characterization data at 25°C. See Figure 9 through Figure 14 for typical curves across
temperature and voltage.
2
3
4
5
6
Max values in this column apply for the full operating temperature range of the device unless otherwise noted.
All modules except ADC active, ICS configured for FBELP, and does not include any dc loads on port pins
All modules except ADC active, ICS configured for FEI, and does not include any dc loads on port pins
All modules except ADC active, ICS configured for FEI, and does not include any dc loads on port pins
Stop currents are tested in production for 25°C on all parts. Tests at other temperatures depend upon the part
number suffix and maturity of the product. Freescale may eliminate a test insertion at a particular temperature from
the production test flow once sufficient data has been collected and is approved.
7
8
Most customers are expected to find that auto-wakeup from stop2 or stop3 can be used instead of the higher
current wait mode.
Values given under the following conditions: low range operation (RANGE = 0) with a 32.768kHz crystal and low
power mode (HGO = 0).
16
FBE
FEI
14
12
10
8
6
4
2
0
2
8
16
20
25
fbus (MHz)
Figure 9. Typical Run I vs. Bus Frequency (V = 5V)
DD
DD
MC9S08MP16 Series Data Sheet, Rev. 1
Freescale Semiconductor
17
Electrical Characteristics
6
FBE
FEI
5
4
3
2
1
-40
0
25
85
105
125
Temperature (C)
Figure 10. Typical Run I vs. Temperature (V = 5V, f = 8MHz)
bus
DD
DD
16
14
12
10
8
FBE
FEI
6
4
2
0
2
8
16
20
25
fbus (MHz)
Figure 11. Typical Run I vs. Bus Frequency (V = 3V)
DD
DD
MC9S08MP16 Series Data Sheet, Rev. 1
18
Freescale Semiconductor
Electrical Characteristics
6
5
4
3
2
1
FBE
FEI
-40
0
25
85
105
125
Temperature (C)
Figure 12. Typical Run I vs. Temperature (V = 3V, f = 8MHz)
bus
DD
DD
70
60
50
40
30
20
10
0
STOP2
STOP3
-40
25
85
105
125
Temperature (C)
Figure 13. Typical Stop I vs. Temperature (V = 5V)
DD
DD
MC9S08MP16 Series Data Sheet, Rev. 1
Freescale Semiconductor
19
Electrical Characteristics
70
STOP2
60
STOP3
50
40
30
20
10
0
-40
25
85
105
125
Temperature (C)
Figure 14. Typical Stop I vs. Temperature (V = 3V)
DD
DD
2.8
External Oscillator (XOSC) Characteristics
Table 9. Oscillator Electrical Specifications (Temperature Range = –40 to 105°C Ambient)
Num
C
Rating
Symbol
Min
Typ1
Max
Unit
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)
Low range (RANGE = 0)
flo
fhi
32
1
—
—
—
—
38.4
16
16
8
kHz
MHz
MHz
MHz
High range (RANGE = 1) FEE2 or FBE3 mode
High range (RANGE = 1, HGO = 1) FBELP mode
High range (RANGE = 1, HGO = 0) FBELP mode
Load capacitors
1
C
fhi-hgo
fhi-lp
1
1
See crystal or resonator
manufacturer’s recommendation.
C1, C2
2
3
—
—
Feedback resistor
RF
Low range (32 kHz to 100 kHz)
High range (1 MHz to 16 MHz)
Series resistor
—
—
10
1
—
—
MΩ
Low range, low gain (RANGE = 0, HGO = 0)
Low range, high gain (RANGE = 0, HGO = 1)
High range, low gain (RANGE = 1, HGO = 0)
High range, high gain (RANGE = 1, HGO = 1)
≥ 8 MHz
—
—
—
0
100
0
—
—
—
RS
4
—
kΩ
—
—
—
0
0
0
0
4 MHz
10
20
1 MHz
MC9S08MP16 Series Data Sheet, Rev. 1
20
Freescale Semiconductor
Electrical Characteristics
Table 9. Oscillator Electrical Specifications (Temperature Range = –40 to 105°C Ambient) (continued)
Num
C
Rating
Symbol
Min
Typ1
Max
Unit
Crystal start-up time 4
t
Low range, low gain (RANGE = 0, HGO = 0)
Low range, high gain (RANGE = 0, HGO = 1)
High range, low gain (RANGE = 1, HGO = 0)5
High range, high gain (RANGE = 1, HGO = 1)4
—
—
—
—
200
400
5
—
—
—
—
CSTL-LP
t
5
T
ms
CSTL-HGO
t
CSTH-LP
t
20
CSTH-HGO
Square wave input clock frequency (EREFS = 0, ERCLKEN = 1)
FEE mode 2
FBE mode 3
FBELP mode
0.03125
—
—
—
51.34
51.34
51.34
MHz
MHz
MHz
fextal
6
T
0
0
1
2
3
4
Typical data was characterized at 5.0 V, 25°C or is recommended value.
The input clock source must be divided using RDIV to within the range of 31.25 kHz to 39.0625 kHz.
The input clock source must be divided using RDIV to less than or equal to 39.0625 kHz.
This parameter is characterized and not tested on each device. Proper PC board layout procedures must be followed to achieve
specifications.
5
4 MHz crystal
MCU
EXTAL
XTAL
RS
RF
C1
Crystal or Resonator
C2
2.9
Internal Clock Source (ICS) Characteristics
Table 10. ICS Frequency Specifications (Temperature Range = –40 to 105°C Ambient)
Num
C
Characteristic
Symbol
Min
Typ1
Max
Unit
Average internal reference frequency — factory trimmed
(consumer- and industrial-qualified devices)
at VDD = 5 V and temperature = 25°C
fint_t
1a
P
—
32.768
—
kHz
Average internal reference frequency — factory trimmed
(automotive-qualified devices)
fint_t
1b
P
—
31.25
—
kHz
at VDD = 5 V and temperature = 25°C
Internal reference frequency — user trimmed
Internal reference start-up time
fint_t
2
3
P
T
31.25
—
—
39.06
100
kHz
tirefst
60
μs
MC9S08MP16 Series Data Sheet, Rev. 1
Freescale Semiconductor
21
Electrical Characteristics
Table 10. ICS Frequency Specifications (Temperature Range = –40 to 105°C Ambient) (continued)
Num
C
Characteristic
Low range (DRS=00)
Symbol
Min
Typ1
Max
Unit
P
C
P
P
P
P
16
32
48
—
—
—
—
—
20
40
60
—
—
—
DCO output frequency range —
trimmed 2
fdco_t
4
Mid range (DRS=01)
High range (DRS=10)
Low range (DRS=00)
Mid range (DRS=01)
High range (DRS=10)
MHz
—
19.92
39.85
59.77
DCO output frequency 2
Reference = 32768 Hz and
DMX32 = 1
fdco_DMX32
5
MHz
Resolution of trimmed DCO output frequency at fixed voltage and
temperature (using FTRIM)
Δfdco_res_t
Δfdco_res_t
Δfdco_t
%fdco
%fdco
%fdco
%fdco
6
7
8
9
C
C
C
C
—
—
—
—
± 0.1
± 0.2
± 0.8
± 0.5
± 0.2
± 0.4
± 2
Resolution of trimmed DCO output frequency at fixed voltage and
temperature (not using FTRIM)
Total deviation of trimmed DCO output frequency over voltage and
temperature
Total deviation of trimmed DCO output frequency over fixed voltage
and temperature range of 0°C to 70 °C
Δfdco_t
± 1
FLL acquisition time 3
tAcquire
CJitter
10
11
C
C
—
—
—
1
ms
Long term jitter of DCO output clock (averaged over 2-ms interval) 4
%fdco
0.02
0.2
1
2
3
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing
from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference,
this specification assumes it is already running.
4
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected
into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given
interval.
MC9S08MP16 Series Data Sheet, Rev. 1
22
Freescale Semiconductor
Electrical Characteristics
3%
2%
1%
0%
-1%
-2%
-3%
-40
-20
0
20
40
60
80
100
120
Temperature (C)
1
Figure 15. Typical Frequency Deviation vs Temperature (ICS Trimmed to 25 MHz bus@25°C, 5V, FEI)
2.10 ADC Characteristics
Table 11. 12-bit ADC Operating Conditions
Characteristic
Conditions
Symbol
Min
Typ1
Max
Unit
Comment
Supply voltage
Input Voltage
Absolute
VDDA
VADIN
CADIN
RADIN
RAS
2.7
VREFL
—
—
—
4.5
3
5.5
VREFH
5.5
V
V
Input Capacitance
Input Resistance
pF
kΩ
kΩ
—
5
Analog Source
Resistance
12 bit mode
fADCK > 4MHz
fADCK < 4MHz
External to MCU
—
—
—
—
2
5
10 bit mode
ADCK > 4MHz
f
—
—
—
—
5
10
fADCK < 4MHz
8 bit mode (all valid fADCK
High Speed (ADLPC=0)
Low Power (ADLPC=1)
)
—
—
—
—
10
8.0
4.0
ADC Conversion
Clock Freq.
fADCK
0.4
0.4
MHz
1
Typical values assume VDDAD = 5.0V, Temp = 25°C, fADCK=1.0MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
1. Based on the average of several hundred units from a typical characterization lot.
MC9S08MP16 Series Data Sheet, Rev. 1
Freescale Semiconductor
23
Electrical Characteristics
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
ZAS
leakage
due to
input
ADC SAR
ENGINE
RAS
RADIN
protection
+
VADIN
–
CAS
VAS
+
–
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 16. ADC Input Impedance Equivalency Diagram
Table 12. 12-bit ADC Characteristics (V = V , V = V )
SSAD
REFH
DDAD REFL
C
Characteristic
Conditions
Symb
Min
Typ1
Max
Unit
Comment
T
Supply Current
ADLPC=1
ADLSMP=1
ADCO=1
IDDA
—
—
—
—
2
133
—
μA
T
T
T
P
Supply Current
ADLPC=1
ADLSMP=0
ADCO=1
IDDA
218
327
—
—
—
μA
μA
Supply Current
ADLPC=0
ADLSMP=1
ADCO=1
IDDA
Supply Current
ADLPC=0
ADLSMP=0
ADCO=1
IDDA
0.582
mA
ADC Asynchronous High Speed (ADLPC=0)
Clock Source
fADACK
3.3
2
5
MHz
tADACK
=
1/fADACK
Low Power (ADLPC=1)
1.25
3.3
MC9S08MP16 Series Data Sheet, Rev. 1
24
Freescale Semiconductor
Electrical Characteristics
) (continued)
Table 12. 12-bit ADC Characteristics (V
= V
, V
= V
REFH
DDAD REFL SSAD
C
Characteristic
Conditions
Symb
tADC
Min
Typ1
Max
Unit
Comment
D
Conversion Time
(Including sample
time)
Short Sample (ADLSMP=0)
Long Sample (ADLSMP=1)
—
—
20
40
—
—
ADCK
cycles
See ADC
chapter in the
Reference
Manual for
conversion time
variances
D
T
T
Sample Time
Short Sample (ADLSMP=0)
Long Sample (ADLSMP=1)
-40°C to 25°C
tADS
—
—
—
—
—
3.5
—
—
—
—
—
ADCK
cycles
23.5
Temp Sensor
Slope
m
3.266
3.638
1.396
mV/°C
25°C to 125°C
Temp Sensor
Voltage
25°C
VTEMP25
ETUE
mV
T
P
T
T
P
T
T
P
T
T
Total Unadjusted
Error
12 bit mode
10 bit mode
8 bit mode
—
—
—
—
—
—
—
—
—
—
±3.0
±1
±6.5
±2.5
±1.0
±3.5
±1.0
±0.5
±4.5
±1.0
±0.5
LSB2
Includes
quantization
±0.5
±1.75
±0.5
±0.3
±1.5
±0.5
±0.3
±1.5
Differential
Non-Linearity
12 bit mode
10 bit mode3
8 bit mode3
12 bit mode
10 bit mode
8 bit mode
DNL
INL
LSB2
LSB2
LSB2
Integral
Non-Linearity
Zero-Scale Error
Full-Scale Error
12 bit mode
EZS
0.0/
-3.0
VADIN = VSSAD
P
T
T
10 bit mode
8 bit mode
12 bit mode
—
—
—
±0.5
±0.5
±1.0
±1.5
±0.5
EFS
+1.75/
LSB2
VADIN = VDDAD
−1.25
T
T
D
10 bit mode
8 bit mode
—
—
—
—
—
—
—
—
±0.5
±0.5
-1 to 0
—
±1
±0.5
—
Quantization Error 12 bit mode
10 bit mode
EQ
LSB2
LSB2
±0.5
±0.5
—
8 bit mode
—
D
Input Leakage Error 12 bit mode
10 bit mode
EIL
±1
Pad leakage4 *
RAS
±0.2
±0.1
±2.5
±1
8 bit mode
1
Typical values assume VDDAD = 5.0V, Temp = 25°C, fADCK=1.0MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2
3
4
1 LSB = (VREFH - VREFL)/2N
Monotonicity and No-Missing-Codes guaranteed in 10 bit and 8 bit modes
Based on input pad leakage current. Refer to pad electricals.
MC9S08MP16 Series Data Sheet, Rev. 1
Freescale Semiconductor
25
Electrical Characteristics
2.11 Digital to Analog (DAC) Characteristics
•
•
•
The accuracy at worst case: +/- 1.5% maximum
The settling time must be less than 100 ns
When changing the output voltage level, the voltage glitch cannot be completely eliminated
Table 13. 5-bit DAC Characteristics
Num
C
Characteristic
Symbol
Min
Typical
Max
Unit
2
3
5
6
D
D
D
D
Supply current adder (enabled)
DAC reference inputs
DAC step size
IDDAC
Vin
—
—
—
20
μA
V
VSSA
VDDA
Vstep
Vdacout
0.75 × Vin/32 Vin/32 1.25 × Vin/32
Vin/32 Vin
V
DAC voltage range
—
V
2.12 High Speed Comparator (HSCMP) Characteristics
Table 14. High Speed Comparator Electrical Specifications
Num
C
Characteristic1
Symbol
Min
Typical
Max
Unit
1
D
Supply current, High Speed Mode
(EN=1, PMODE=1)
IDDAHS
—
200
μA
2
D
Supply current, Low Speed Mode
(EN=1, PMODE=0)
IDDALS
—
10
μA
3
4
5
6
—
P
Analog input voltage
VAIN
VAIO
VH
VSSA
—
—
5
VDDA
40
V
Analog input offset voltage
Analog Comparator hysteresis
mV
mV
ns
C
T
3.0
—
9
20.0
120
2
Propagation Delay, High Speed Mode
(EN=1, PMODE=1)
tDHS
70
2
7
T
Propagation Delay, Low Speed Mode
(EN=1, PMODE=0)
tDLS
—
—
400
400
600
—
ns
ns
8
D
Analog comparator initialization delay
tAINIT
1
2
All timing assumes slew rate control disabled and high drive strength enabled.
Delay from analog input to the CMPxOUT output pin. Measured with an input waveform that switches 30 mV above and
below the reference.
2.13 Programmable Gain Amplifier (PGA) Characteristics
Table 15. Programmable Gain Amplifier Electrical Specifications
Num
C
Parameter
Symbol
Min
Typical
Max
Unit
1
T
Supply current adder
IDDON
uA
• normal mode (LP=0)
• low power mode (LP=1)
—
—
450
250
550
300
2
3
T
T
Supply current adder (stand-by)
Absolute analog input level
IDDAOFF
VIL
—
1
10
nA
V
VSSA
VDDA/2
VDDA
MC9S08MP16 Series Data Sheet, Rev. 1
26
Freescale Semiconductor
Electrical Characteristics
Table 15. Programmable Gain Amplifier Electrical Specifications (continued)
Num
C
Parameter
Symbol
Min
Typical
Max
Unit
4
D
Differential input voltage
VDIFFMAX
0
V
V
– 1.4
DDA
V
– 1.4
-----------------------------
DDA
2 × Gain
-----------------------------
–
(
)
2 × Gain
5
T
Linearity (@ voltage gain)1
LV
V/V
• 1x
• 2x
• 4x
• 8x
• 16x
• 32x
1 – 1/2 LSB
2 – 1/2 LSB
4 – 1 LSB
8 – 1 LSB
16 – 4 LSB
32 – 4 LSB
1
2
4
8
16
32
1 + 1/2 LSB
2 + 1/2 LSB
4 + 1 LSB
8 + 1 LSB
16 + 4 LSB
32 + 4 LSB
6
T
Max gain error
EG
—
1
2
%
7a
D
PGA clock
• normal mode (LP=0)
• low power mode (LP=1)
fPGA
MHz
—
—
82
4
82
4
7b
D
PGA sampling frequency3
fSAMPL
—
—
Samples
per second
1
----------------------------------------------------------------------------------------------------
12 + 18 × NUM_CLK_GS
43
5
⎛
⎝
⎞
⎠
------------------------------------------------------------------
+ ------------- + ------------
f
f
f
PGA
ADC
BUS
8
9
D
D
Input signal bandwidth
BW
0
fSAMPL ÷ 8
fPGA ÷ 4
fSAMPL ÷ 2
Hz
Hz
Charge pump clock frequency
fcpclk
100
—
1
2
3
LSB in 12-bit resolution
8 MHz is required for PGA achieving 1 μs sampling time.
ADC in 12-bit mode, long sampling time, fADC = fPGA
2.14 AC Characteristics
This section describes timing characteristics for each peripheral system.
2.14.1 Control Timing
Table 16. Control Timing
Num
C
Rating
Symbol
Min
Typ1
Max
Unit
–40 to 105 °C
–40 to 125 °C
fBus
fBus
DC
DC
—
—
—
—
—
—
25.67
20
MHz
MHz
μs
Bus frequency
(tcyc = 1/fBus
1
D
)
2
3
4
5
P
D
D
D
Internal low power oscillator period
External reset pulse width2
Reset low drive
tLPO
700
1300
—
textrst
trstdrv
tMSSU
100
ns
34 x tcyc
500
—
ns
BKGD/MS setup time after issuing background debug force
reset to enter user or BDM modes
—
ns
6
D
BKGD/MS hold time after issuing background debug force
reset to enter user or BDM modes 3
tMSH
100
—
—
μs
MC9S08MP16 Series Data Sheet, Rev. 1
Freescale Semiconductor
27
Electrical Characteristics
Table 16. Control Timing (continued)
Rating Symbol
Num
C
Min
Typ1
Max
Unit
7
D
Keyboard interrupt pulse width
Asynchronous path4
ns
tILIH, IHIL
t
100
1.5 x tcyc
—
—
—
—
Synchronous path5
8
C
Port rise and fall time —
t
Rise, tFall
ns
ns
Low output drive (PTxDS = 0) (load = 50 pF)6
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
—
—
40
75
—
—
Port rise and fall time —
tRise, tFall
High output drive (PTxDS = 1) (load = 50 pF)6
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
—
—
11
35
—
—
1
2
3
Typical values are based on characterization data at VDD = 5.0V, 25°C unless otherwise stated.
This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD rises
above VLVD
.
4
5
This is the minimum pulse width that is guaranteed to be recognized as a keyboard interrupt request in stop mode.
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not
be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
6
Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40°C to 125°C.
textrst
RESET PIN
Figure 17. Reset Timing
tIHIL
KBIxPn
KBIxPn
tILIH
Figure 18. KBIxPn Timing
2.14.2 FTM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the
optional external source to the FTM timer counter. These synchronizers operate from the current ICSOUT clock. The ICSOUT
clock period = 0.5 × t = 1/(f × 2).
cyc
Bus
Table 17. FTM Input Timing
No.
C
Function
Symbol
Min
Max
Unit
1
2
3
D
D
D
External clock frequency
External clock period
fTCLK
tTCLK
tclkh
0
2
fICSOUT/41
Hz
tcyc
tcyc
—
—
External clock high time
0.75
MC9S08MP16 Series Data Sheet, Rev. 1
28
Freescale Semiconductor
Electrical Characteristics
Table 17. FTM Input Timing (continued)
No.
C
Function
Symbol
Min
Max
Unit
4
5
D
D
External clock low time
Input capture pulse width
tclkl
0.75
0.75
—
—
tcyc
tcyc
tICPW
1
The maximum external clock frequency is limited to 10MHz due to input filter characteristics.
tTCLK
tclkh
TCLK
tclkl
Figure 19. FTM External Clock
tICPW
FTMxCHn
FTMxCHn
tICPW
Figure 20. FTM Input Capture Pulse
2.14.3 MTIM Module Timing
Synchronizer circuits determine the fastest clock that can be used as the optional external clock source to the MTIM timer
counter. These synchronizers operate from the current bus rate clock.
Table 18. MTIM Input Timing
No.
C
Function
Symbol
Min
Max
Unit
1
2
3
4
D
D
D
D
External clock frequency
External clock period
fTCLK
tTCLK
tclkh
0
fBus/4
—
Hz
tcyc
tcyc
tcyc
4
External clock high time
External clock low time
1.5
1.5
—
tclkl
—
tTCLK
tclkh
TCLK
tclkl
Figure 21. MTIM Timer External Clock
MC9S08MP16 Series Data Sheet, Rev. 1
Freescale Semiconductor
29
Electrical Characteristics
2.14.4 SPI
Table 19 and Figure 22 through Figure 25 describe the timing requirements for the SPI system.
Table 19. SPI Electrical Characteristics
Num1
C
Rating2
Symbol
Min
Max
Unit
Cycle time
Master
Slave
2
4
4096
—
tcyc
tcyc
1
D
tSCK
tSCK
Enable lead time
Master
Slave
—
1/2
2
3
D
D
1/2
—
t
t
t
t
Lead
Lead
SCK
SCK
Enable lag time
Master
Slave
—
1/2
1/2
—
t
t
t
t
Lag
Lag
SCK
SCK
Clock (SPSCK) high time
Master and Slave
4
5
D
D
1/2 tSCK – 25
1/2 tSCK – 25
—
—
ns
ns
t
SCKH
Clock (SPSCK) low time
Master and Slave
t
SCKL
Data setup time (inputs)
Master
Slave
30
30
—
—
ns
ns
6
7
D
D
t
t
SI(M)
SI(S)
Data hold time (inputs)
Master
Slave
30
30
—
—
ns
ns
t
HI(M)
t
HI(S)
Access time, slave3
0
40
40
ns
ns
8
9
D
D
t
A
Disable time, slave4
Data setup time (outputs)
—
t
dis
Master
Slave
—
—
25
25
ns
ns
10
11
D
D
t
t
SO
SO
Data hold time (outputs)
Operating frequency
Master
Slave
–10
–10
—
—
ns
ns
t
t
HO
HO
f
op
5
Master (SPIFE=0)
Slave (SPIFE=0)
Master (SPIFE=1)
Slave (SPIFE=1)
MHz
f
f
/4096
8
Bus
dc
/4096
f
/4
12
D
Bus
5
5
6
MHz
MHz
Bus
6
dc
1
2
Refer to Figure 22 through Figure 25.
All timing is shown with respect to 20% V
timing assumes slew rate control disabled and high drive strength enabled for SPI output pins.
and 70% V , unless noted; 100 pF load on all SPI pins. All
DD
DD
3
4
5
6
Time to data active from high-impedance state.
Hold time to high-impedance state.
Maximum baud rate must be limited to 8 MHz.
Maximum baud rate must be limited to 5 MHz due to input filter characteristics.
MC9S08MP16 Series Data Sheet, Rev. 1
30
Freescale Semiconductor
Electrical Characteristics
SS1
(OUTPUT)
1
2
3
SCK
(CPOL = 0)
(OUTPUT)
5
4
4
5
SCK
(CPOL = 1)
(OUTPUT)
6
7
MISO
(INPUT)
MSB IN2
10
BIT 6 . . . 1
LSB IN
10
11
MOSI
(OUTPUT)
MSB OUT2
BIT 6 . . . 1
LSB OUT
NOTES:
1. SS output mode (MODFEN = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 22. SPI Master Timing (CPHA = 0)
SS(1)
(OUTPUT)
1
2
3
SCK
(CPOL = 0)
(OUTPUT)
5
4
SCK
(CPOL = 1)
5
4
(OUTPUT)
6
7
MISO
(INPUT)
MSB IN(2)
BIT 6 . . . 1
11
BIT 6 . . . 1
LSB IN
10
MOSI
(OUTPUT)
MSB OUT(2)
LSB OUT
NOTES:
1. SS output mode (MODFEN = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 23. SPI Master Timing (CPHA = 1)
MC9S08MP16 Series Data Sheet, Rev. 1
Freescale Semiconductor
31
Electrical Characteristics
SS
(INPUT)
3
1
SCK
5
4
(CPOL = 0)
4
5
(INPUT)
2
SCK
(CPOL = 1)
(INPUT)
9
8
11
10
MISO
(OUTPUT)
SEE
NOTE
BIT 6 . . . 1
BIT 6 . . . 1
SLAVE LSB OUT
MSB OUT
7
SLAVE
6
MOSI
(INPUT)
MSB IN
LSB IN
NOTE:
1. Not defined but normally MSB of character just received
Figure 24. SPI Slave Timing (CPHA = 0)
SS
(INPUT)
1
3
2
SCK
(CPOL = 0)
(INPUT)
5
4
4
5
SCK
(CPOL = 1)
(INPUT)
10
SLAVE MSB OUT
11
9
MISO
(OUTPUT)
SEE
BIT 6 . . . 1
SLAVE LSB OUT
LSB IN
NOTE
6
7
8
MOSI
(INPUT)
MSB IN
BIT 6 . . . 1
NOTE:
1. Not defined but normally LSB of character just received
Figure 25. SPI Slave Timing (CPHA = 1)
MC9S08MP16 Series Data Sheet, Rev. 1
32
Freescale Semiconductor
Electrical Characteristics
2.15 Flash Memory Specifications
This section provides details about program/erase times and program-erase endurance for the flash memory.
Program and erase operations do not require any special power sources other than the normal V supply. For more detailed
DD
information about program/erase operations, see the Memory section.
Table 20. Flash Memory Characteristics
Num
C
Characteristic
Symbol
Min
Typical
Max
Unit
—
Supply voltage for program/erase
-40°C to 125°C
1
2.7
5.5
Vprog/erase
VRead
fFCLK
V
2
3
—
—
—
C
Supply voltage for read operation
Internal FCLK frequency1
Internal FCLK period (1/FCLK)
Byte program time (random location)2
Byte program time (burst mode)2
Page erase time2
2.7
150
5
5.5
200
6.67
V
kHz
μs
4
tFcyc
5
tprog
9
tFcyc
tFcyc
tFcyc
tFcyc
mA
mA
6
—
D
tBurst
4
4000
20,000
4
7
tPage
8
D
Mass erase time2
tMass
9
C
Byte program current3
RIDDBP
RIDDPE
—
—
—
—
10
C
Page erase current3
6
Program/erase endurance4
TL to TH = –40°C to + 125°C
T = 25°C
11
12
C
C
10,000
15
—
100,000
—
—
cycles
years
Data retention5
tD_ret
100
—
1
2
The frequency of this clock is controlled by a software setting.
These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for
calculating approximate time to program and erase.
3
4
5
The program and erase currents are additional to the standard run IDD. These values are measured at room temperatures with
VDD = 5.0 V, bus frequency = 4.0 MHz.
Typical endurance for Flash is based upon the intrinsic bit cell performance. For additional information on how Freescale defines
typical endurance, please refer to Engineering Bulletin EB619/D, Typical Endurance for Nonvolatile Memory.
Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to
25°C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to
Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory.
2.16 EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board
design and layout, circuit topology choices, location and characteristics of external components as well as MCU software
operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such
as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC
performance.
2.16.1 Radiated Emissions
Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance
with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a
MC9S08MP16 Series Data Sheet, Rev. 1
Freescale Semiconductor
33
Ordering Information
custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller
are measured in a TEM cell in two package orientations (North and East).
The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal to the reported
emissions levels.
Table 21. Radiated Emissions, Electric Field
Level1
Parameter
Symbol
Conditions
Frequency
fOSC/fBUS
Unit
(Max)
0.15 – 50 MHz
50 – 150 MHz
150 – 500 MHz
500 – 1000 MHz
IEC Level2
3
8
dBμV
VDD = 5V
TA = +25°C
package type
48 LQFP
–4
–8
N
Radiated emissions,
electric field
4 MHz crystal
2 MHz bus
VRE_TEM
—
—
SAE Level3
1
1
Data based on qualification test results. The reported emission level is the value of the maximum emission, rounded up to the
next whole number, from among the measured orientations in each frequency range.
2
3
IEC level maximums: N ≤ 12 dBμV, L ≤ 24 dBμV, I ≤ 36 dBμV
SAE level maximums: 1 ≤ 10 dBμV, 2 ≤ 20 dBμV, 3 ≤ 30 dBμV, 4 ≤ 40 dBμV
3
Ordering Information
This section contains ordering information for MC9S08MP16 and MC9S08MP12 devices.
Table 22. Device and Package Options
Memory
Available Packages2
Temp
Range
Device Number1
Flash
RAM
48-Pin
32-Pin
28-Pin
Consumer and Industrial Qualification
MC9S08MP16
MC9S08MP12
V
V
16K
12K
1024
512
48 LQFP
—
32 LQFP
—
28 SOIC
28 SOIC
Automotive Qualification
1024 48 LQFP
S9S08MP16
C, V, M
16K
—
—
1
2
See the MC9S08MP16RM Reference Manual (MC9S08MP16RM) for a complete description of modules included on each
device.
See Table 23 for package information.
MC9S08MP16 Series Data Sheet, Rev. 1
34
Freescale Semiconductor
Package Information
3.1
Device Numbering Scheme
Example of the device numbering system:
xx 9 S08 MP nn E2 y zz
Package designator (see Table 23)
Status
MC = Consumer &
Industrial
Temperature range
V = –40°C to 105°C
M = –40°C to 125°C
S = Automotive Qualified
Memory
9 = Flash-based
Core
Wafer fab site and mask revision
(this field appears only in automotive-qualified
part numbers)
Family
Flash size
16 KBytes
12 KBytes
4
Package Information
The latest package outline drawings are available on the product summary pages on our web site:
http://www.freescale.com/8bit. The following table lists the document numbers per package. Use these numbers in the web
page’s keyword search engine to find the latest package outline drawings.
NOTE
The 32 LQFP and 28 SOIC are not qualified to meet automotive requirements.
Table 23. Package Descriptions
Pin Count
Package Type
Abbreviation
Designator
Case No.
Document No.
48
32
28
Low Quad Flat Pack
Low Quad Flat Pack
LQFP
LQFP
SOIC
LF
LC
WL
932-03
873A-03
751F-05
98ASH00962A
98ASH70029A
98ASB42345B
Small Outline Integrated Circuit
5
Related Documentation
Find the most current versions of all documents at http://www.freescale.com.
Reference Manual (MC9S08MP16RM)
Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module
information.
6
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web are the most current. Your
printed copy may be an earlier revision. To verify you have the latest information available, refer to:
http://www.freescale.com
MC9S08MP16 Series Data Sheet, Rev. 1
Freescale Semiconductor
35
Table 24 summarizes changes contained in this document.
Table 24. Revision History
Rev
Date
Description of Changes
1
10/6/2009
Initial public revision
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Document Number: MC9S08MP16
Rev. 1
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