MC9S08QA4_09_技术文档

Freescale Semiconductor

Data Sheet: Technical Data

Document Number: MC9S08QA4

Rev. 3, 1/2009

MC9S08QA4

8-Pin DFN

Case 1452-02

8-Pin NB-SOIC

Case 751-07

MC9S08QA4 Series

8-Pin PDIP

Case 626-06

Covers: MC9S08QA4

MC9S08QA2

Features:

– Breakpoint capability to allow single breakpoint setting

during in-circuit debugging

• Peripherals

• 8-bit HCS08 Central Processor Unit (CPU)

– Up to 20 MHz CPU at 3.6 V to 1.8 V across temperature

range of –40°C to 85°C

– HC08 instruction set with added BGND instruction

– Support for up to 32 interrupt/reset sources

• On-Chip Memory

– ADC — 4-channel, 10-bit resolution; 1.7 mV/°C

temperature sensor; automatic compare function;

internal bandgap reference channel; operation in stop3;

fully functional from 3.6 V to 1.8 V

– ACMP — Analog comparator with selectable interrupt

on rising, falling, or either edge of comparator output;

compare option to fixed internal bandgap reference

voltage; output can be tied internally to TPM input

capture

– Flash read/program/erase over full operating voltage

and temperature

– Random-access memory (RAM)

– Security circuitry to prevent unauthorized access to

RAM and flash contents

– TPM — One 1-channel timer/pulse-width modulator

(TPM) module; selectable input capture, output

compare, or buffered edge- or center-aligned PWM on

each channel; ACMP output can be tied internally to

input capture

• Power-Saving Modes

– Two very low power stop modes

– Peripheral clock enable register can disable clocks to

unused modules, thereby reducing currents

– Very low power real time counter for use in run, wait,

and stop modes with internal clock sources

• Clock Source Options

– MTIM — 8-bit modulo timer module with 8-bit

prescaler

– KBI — 4-pin keyboard interrupt module with software

selectable polarity on edge or edge/level modes

• Input/Output

– Internal Clock Source (ICS) — Internal clock source

module containing a frequency-locked-loop (FLL)

controlled by internal reference; precision trimming of

internal reference allows 0.2% resolution and 2%

deviation over temperature and voltage; supports bus

frequencies from 1 MHz to 10 MHz

• System Protection

– Four GPIOs, one input-only pin and one output-only

pin.

– Hysteresis and configurable pullup device on all input

pins; configurable slew rate and drive strength on all

output pins except PTA5

– Watchdog computer operating properly (COP) reset

with option to run from dedicated 1 kHz internal clock

source or bus clock

• Package Options

– 8-pin SOIC, PDIP, and DFN

– Low-voltage detection with reset or interrupt

– Selectable trip points

– Illegal opcode detection with reset

– Illegal address detection with reset

– Flash block protection

• Development Support

– Single-wire background debug interface

This document contains information on a product under development. Freescale reserves the

right to change or discontinue this product without notice.

Table of Contents

1

2

3

MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

3.8 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.8.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.8.2 TPM/MTIM Module Timing. . . . . . . . . . . . . . . . 14

3.9 Analog Comparator (ACMP) Electricals . . . . . . . . . . . 15

3.10 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.11 Flash Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

3.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . .5

3.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .5

3.4 ESD Protection and Latch-Up Immunity . . . . . . . . . . . . .6

3.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

3.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .10

3.7 Internal Clock Source (ICS) Characteristics . . . . . . . . .11

4

5

Revision History

To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current.

Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:

http://freescale.com/

The following revision history table summarizes changes contained in this document.

Revision

Date

1/2008

Description of Changes

1

2

3

Initial public release

2/2008

1/2009

Changed the designator of the device in Table 15.

Changed the condition of Run supply current measured to f_Bus= 1 MHz in Table 7.

Fixed the error of inconsistent table number.

Related Documentation

Find the most current versions of all documents at: http://www.freescale.com

Reference Manual (MC9S08QA4RM)

Contains extensive product information including modes of operation, memory,

resets and interrupts, register definition, port pins, CPU, and all module

information.

MC9S08QA4 Series MCU Data Sheet, Rev. 3

2

Freescale Semiconductor

MCU Block Diagram

1

MCU Block Diagram

The block diagram, Figure 1, shows the structure of the MC9S08QA4 MCU.

BKGD/MS

IRQ

HCS08 CORE

DEBUG MODULE (DBG)

BDC

CPU

TCLK

PTA5//IRQ/TCLK/RESET

8-BIT MODULO TIMER

MODULE (MTIM)

HCS08 SYSTEM CONTROL

PTA4/ACMPO/BKGD/MS

RESETS AND INTERRUPTS

MODES OF OPERATION

POWER MANAGEMENT

PTA3/KBIP3/ADP3

PTA2/KBIP2/ADP2

4

RTI

COP

LVD

8-BIT KEYBOARD

INTERRUPT MODULE (KBI)

IRQ

ACMPO

ACMP–

ACMP+

PTA1/KBIP1/ADP1/ACMP–

PTA0/KBIP0/TPMCH0/ADP0/ACMP+

ANALOG COMPARATOR

(ACMP)

USER FLASH

(MC9S08QA4 = 4096 BYTES)

(MC9S08QA2 = 2048 BYTES)

4

10-BIT

ANALOG-TO-DIGITAL

CONVERTER (ADC)

USER RAM

(MC9S08QA4 = 256 BYTES)

(MC9S08QA2 = 160BYTES)

TPMCH0

16-BIT TIMER/PWM

MODULE (TPM)

16 MHz INTERNAL CLOCK

SOURCE (ICS)

V

SS

VOLTAGE REGULATOR

DD

V

DDA

SSA

V

REFH

REFL

NOTES:

1

Port pins are software configurable with pullup device if input port.

Port pins are software configurable for output drive strength.

Port pins are software configurable for output slew rate control.

2

3

4

5

6

7

IRQ contains a software configurable (IRQPDD) pullup device if PTA5 enabled as IRQ pin function (IRQPE = 1).

RESET contains integrated pullup device if PTA5 enabled as reset pin function (RSTPE = 1).

PTA4 contains integrated pullup device if BKGD enabled (BKGDPE = 1).

When pin functions as KBI (KBIPEn = 1) and associated pin is configured to enable the pullup device, KBEDGn can

be used to reconfigure the pullup as a pulldown device.

Figure 1. MC9S08QA4 Series Block Diagram

2

Pin Assignments

This section shows the pin assignments in the packages available for the MC9S08QA4 series.

MC9S08QA4 Series MCU Data Sheet, Rev. 3

Freescale Semiconductor

3

Pin Assignments

Table 1. Pin Sharing Priority

Priority

Lowest

Highest

8-Pin

Port Pin

Alt 1

Alt 2

Alt 3

Alt 4

1

2

3

4

5

6

7

8

PTA5¹

PTA4

IRQ

TCLK

RESET

MS

ACMPO

BKGD

V

DD

V

SS

PTA3

PTA2

PTA1

PTA0

KBIP3

KBIP2

KBIP1

KBIP0

ADP3

ADP2

ADP1²

ADP0²

ACMP–²

ACMP+²

TPMCH0

1

2

Pin does not contain a clamp diode to V_DDand must not be driven

above V_DD. The voltage measured on the internally pulled-up RESET

pin will not be pulled to V_DD. The internal gates connected to this pin

are pulled to V_DD

.

If ACMP and ADC are both enabled, both will have access to the pin.

PTA5/IRQ/TCLK/RESET

1

2

3

4

8

7

6

5

PTA0/KBIP0/TPMCH0/ADP0/ACMP+

PTA1/KBIP1/ADP1/ACMP–

PTA2/KBIP2/ADP2

PTA4/ACMPO/BKGD/MS

V_DD

V_SS

PTA3/KBIP3/ADP3

8-Pin PDIP/SOIC

PTA5/IRQ/TCLK/RESET

1

8

PTA0/KBIP0/TPMCH0/ADP0/ACMP+

PTA1/KBIP1/ADP1/ACMP–

PTA2/KBIP2/ADP2

PTA4/ACMPO/BKGD/MS

2

3

7

6

V_DD

V_SS

4

5

PTA3/KBIP3/ADP3

8-Pin DFN

Figure 2. MC9S08QA4 Series in 8-Pin Packages

MC9S08QA4 Series MCU Data Sheet, Rev. 3

4

Freescale Semiconductor

Electrical Characteristics

3

Electrical Characteristics

3.1

Introduction

This chapter contains electrical and timing specifications for the MC9S08QA4 series of microcontrollers available at the time

of publication.

3.2

Absolute Maximum Ratings

Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the

limits specified in Table 2 may affect device reliability or cause permanent damage to the device. For functional operating

conditions, refer to the remaining tables in this section.

This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised

that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this

high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for

instance, either V or V ) or the programmable pullup resistor associated with the pin is enabled.

SS

DD

Table 2. Absolute Maximum Ratings

Rating

Symbol

Value

Unit

Supply voltage

V_DD

I_DD

V_In

I_D

–0.3 to 3.8

120

V

Maximum current into V_DD

Digital input voltage

mA

V

–0.3 to V_DD+ 0.3

Instantaneous maximum current

mA

±25

Single pin limit (applies to all port pins)^{1, 2, 3}

Storage temperature range

T_stg

–55 to 150

°C

1

Input must be current limited to the value specified. To determine the value of the required

current-limiting resistor, calculate resistance values for positive (V_DD) and negative (V_SS) clamp

voltages, then use the larger of the two resistance values.

2

3

All functional non-supply pins are internally clamped to V_SSand V_DD

.

Power supply must maintain regulation within operating V_DDrange during instantaneous and

operating maximum current conditions. If positive injection current (V_In> V_DD) is greater than

I_DD, the injection current may flow out of V_DDand could result in external power supply going

out of regulation. Ensure external V_DDload will shunt current greater than maximum injection

current. This will be the greatest risk when the MCU is not consuming power. Examples are: if

no system clock is present, or if the clock rate is very low (which would reduce overall power

consumption).

3.3

Thermal Characteristics

This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power

dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and

it is user-determined rather than being controlled by the MCU design. To take P into account in power calculations, determine

I/O

the difference between actual pin voltage and V or V and multiply by the pin current for each I/O pin. Except in cases of

SS

DD

unusually high pin current (heavy loads), the difference between pin voltage and V or V will be very small.

SS

DD

MC9S08QA4 Series MCU Data Sheet, Rev. 3

Freescale Semiconductor

5

Electrical Characteristics

Table 3. Thermal Characteristics

Symbol

Rating

Value

Unit

Operating temperature range

(packaged)

T_Lto T_H

–40 to 85

T_A

°C

Thermal resistance

Single-layer board

8-pin PDIP

113

150

179

8-pin NB SOIC

8-pin DFN

θ_JA

°C/W

Thermal resistance

Four-layer board

8-pin PDIP

72

87

41

8-pin NB SOIC

8-pin DFN

θ_JA

The average chip-junction temperature (T ) in °C can be obtained from:

J

T = T + (P × θ )

JA

Eqn. 1

J

A

D

where:

— T = Ambient temperature, °C

A

— θ = Package thermal resistance, junction-to-ambient, °C/W

JA

— P = P + P

I/O

D

int

— P = I × V , Watts — chip internal power

int

DD

— P = Power dissipation on input and output pins — user-determined

I/O

For most applications, P << P and can be neglected. An approximate relationship between P and T (if P is neglected)

I/O

int

D

J

I/O

is:

P = K ÷ (T + 273°C)

Eqn. 2

D

J

Solving Equation 1 and Equation 2 for K gives:

K = P × (T + 273°C) + θ × (P )

2

Eqn. 3

D

A

JA

D

where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring P (at equilibrium)

D

for a known T . Using this value of K, the values of P and T can be obtained by solving Equation 1 and Equation 2 iteratively

A

D

J

for any value of T .

A

3.4

ESD Protection and Latch-Up Immunity

Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,

normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure

that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.

All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During

the device qualification ESD stresses were performed for the human body model (HBM), the machine model (MM) and the

charge device model (CDM).

MC9S08QA4 Series MCU Data Sheet, Rev. 3

6

Freescale Semiconductor

Electrical Characteristics

A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete

DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot

temperature, unless specified otherwise in the device specification.

Table 4. ESD and Latch-up Test Conditions

Model

Description

Series resistance

Symbol

Value

Unit

R1

C

1500

100

3

Ω

Human

Body

Storage capacitance

Number of pulses per pin

Series resistance

pF

R1

C

0

Ω

Machine Storage capacitance

Number of pulses per pin

200

3

pF

Minimum input voltage limit

Latch-up

–2.5

7.5

V

Maximum input voltage limit

Table 5. ESD and Latch-Up Protection Characteristics

No.

Rating¹

Symbol

Min

Max

Unit

1

2

3

4

Human body model (HBM)

Machine model (MM)

V_HBM

V_MM

V_CDM

I_LAT

±2000

±200

±500

±100

—

V

Charge device model (CDM)

Latch-up current at T_A= 85°C

V

mA

1

Parameter is achieved by design characterization on a small sample size from typical devices

under typical conditions unless otherwise noted.

3.5

DC Characteristics

This section includes information about power supply requirements and I/O pin characteristics.

Table 6. DC Characteristics (Temperature Range = –40 to 85°C Ambient)

Parameter

Symbol

Min

Typical

Max

Unit

Supply voltage (run, wait, and stop modes)

(V_DDfalling)

(V_DDrising)

V_DD

1.8

—

3.6

—

V

V_LVDL

(rising)

1,2

Minimum RAM retention supply voltage applied to V_DD

Low-voltage detection threshold

V_RAM

V_por

V

(V_DDfalling)

V_LVD

1.80

1.88

1.82

1.90

1.91

1.99

(V_DDrising)

Low-voltage warning threshold

Freescale Semiconductor

V_LVW

(V_DDfalling)

2.08

2.1

2.2

MC9S08QA4 Series MCU Data Sheet, Rev. 3

7

Electrical Characteristics

Table 6. DC Characteristics (Temperature Range = –40 to 85°C Ambient) (continued)

Parameter

Symbol

Min

Typical

Max

Unit

(V_DDrising)

2.16

—

2.19

1.4

1.20

—

2.27

Power on reset (POR) re-arm voltage

Bandgap voltage reference

V_por

V_BG

—

1.21

V

1.18

Input high voltage (V_DD> 2.3 V) (all digital inputs)

0.70 × V_DD

0.85 × V_DD

—

V_IH

V_IL

V

Input high voltage (1.8 V ≤ V_DD≤ 2.3 V) (all digital inputs)

Input low voltage (V_DD> 2.3 V) (all digital inputs)

Input low voltage (1.8 V ≤ V_DD≤ 2.3 V) (all digital inputs)

Input hysteresis (all digital inputs)

—

0.35 × V_DD

0.30 × V_DD

—

V_hys

|I_In|

0.06 × V_DD

—

V

Input leakage current (per pin)

—

0.025

1.0

μA

V_In= V_DDor V_SS, all input-only pins

High impedance (off-state) leakage current (per pin)

|I_OZ

|

μA

V_In= V_DDor V_SS, all input/output

Internal pullup resistors^3,4

R_PU

R_PD

17.5

—

52.5

kΩ

Internal pulldown resistor (KBI)

Output high voltage — low drive (PTxDSn = 0)

V_DD– 0.5

—

I

= –2 mA (V_DD≥ 1.8 V)

OH

V_OH

Output high voltage — high drive (PTxDSn = 1)

V

I

= –10 mA (V_DD≥ 2.7 V)

= –6 mA (V_DD≥ 2.3 V)

—

OH

V_DD– 0.5

= –3 mA (V ≥ 1.8 V)

DD

Maximum total I_OHfor all port pins

|I_OHT

|

—

60

mA

V

Output low voltage — low drive (PTxDSn = 0)

I

= 2.0 mA (V_DD≥ 1.8 V)

—

0.5

OL

Output low voltage — high drive (PTxDSn = 1)

V_OL

I

= 10.0 mA (V_DD≥ 2.7 V)

= 6 mA (V_DD≥ 2.3 V)

= 3 mA (V_DD≥ 1.8 V)

—

0.5

OL

I

OL

Maximum total I_OLfor all port pins

I_OLT

—

60

mA

DC injection current ^{2, 5, 6, 7}

V_In< V_SS, V_In> V_DD

Single pin limit

I_IC

–0.2

–5

—

0.2

5

mA

Total MCU limit, includes sum of all stressed pins

Input capacitance (all non-supply pins)

C_In

—

7

pF

1

2

3

4

RAM will retain data down to POR voltage. RAM data not guaranteed to be valid following a POR.

This parameter is characterized and not tested on each device.

Measurement condition for pull resistors: V_In= V_SSfor pullup and V_In= V_DDfor pulldown.

PTA5/IRQ/TCLK/RESET pullup resistor may not pull up to the specified minimum V_IH. However, all ports are functionally tested

to guarantee that a logic 1 will be read on any port input when the pullup is enabled and no DC load is present on the pin.

5

All functional non-supply pins are internally clamped to V_SSand V_DD

.

MC9S08QA4 Series MCU Data Sheet, Rev. 3

8

Freescale Semiconductor

Electrical Characteristics

6

7

Input must be current-limited to the value specified. To determine the value of the required current-limiting resistor, calculate

resistance values for positive and negative clamp voltages, then use the larger of the two values.

Power supply must maintain regulation within operating V_DDrange during instantaneous and operating maximum current

conditions. If positive injection current (V_In> V_DD) is greater than I_DD, the injection current may flow out of V_DDand could result

in external power supply going out of regulation. Ensure external V_DDload will shunt current greater than maximum injection

current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if

clock rate is very low (which would reduce overall power consumption).

PULLUP RESISTOR TYPICALS

40

35

30

25

20

PULLDOWN RESISTOR TYPICALS

85°C

40

35

30

25

20

85°C

25°C

–40°C

1.8

2

2.2 2.4 2.6 2.8

3

3.2 3.4 3.6

1.8

2.3

2.8

V_DD(V)

3.3

3.6

V_DD(V)

Figure 3. Pullup and Pulldown Typical Resistor Values (V = 3.0 V)

DD

TYPICAL V_OLVS I_OLAT V_DD= 3.0 V

TYPICAL V_OLVS V_DD

0.2

0.15

0.1

1.2

85°C

25°C

1

–40°C

0.8

0.6

0.4

0.2

0

85

25

–40

°

C, I_OL= 2 mA

0.05

0

1

2

3

4

0

5

10

_OL(mA)

15

20

V_DD(V)

I

Figure 4. Typical Low-Side Driver (Sink) Characteristics — Low Drive (PTxDSn = 0)

TYPICAL V_OLVS V_DD

TYPICAL V_OLVS I_OLAT V_DD= 3.0 V

1

0.4

0.3

0.2

0.1

85°C

25°C

–40°C

25°C

0.8

0.6

0.4

0.2

–40°C

I_OL= 10 mA

I_OL= 6 mA

I_OL= 3 mA

0

10

20

30

1

2

3

4

V_DD(V)

I_OL(mA)

Figure 5. Typical Low-Side Driver (Sink) Characteristics — High Drive (PTxDSn = 1)

MC9S08QA4 Series MCU Data Sheet, Rev. 3

Freescale Semiconductor

9

Electrical Characteristics

TYPICAL V_DD– V_OHVS I_OHAT V_DD= 3.0 V

TYPICAL V_DD– V_OHVS V_DDAT SPEC I_OH

85 C, I_OH= 2 mA

1.2

1

0.25

0.2

85°C

°

25°C

25°

C, I_OH= 2 mA

–40°C

–40°

C, I_OH= 2 mA

0.8

0.6

0.4

0.2

0

0.15

0.1

0.05

0

–5

–10

I_OH(mA))

–15

–20

1

2

3

4

V_DD(V)

Figure 6. Typical High-Side (Source) Characteristics — Low Drive (PTxDSn = 0)

TYPICAL V_DD– V_OHVS V_DDAT SPEC I_OH

0.4

85°C

25°C

–40°C

TYPICAL V – V VS I AT V = 3.0 V

DD

OH

DD

0.3

0.2

0.1

0.8

0.6

0.4

0.2

0

85°C

25°C

I_OH= –10 mA

–40°C

I_OH= –6 mA

I

_OH= –3 mA

0

–5

–10

–15

–20

–25

–30

1

2

3

4

I

(mA)

OH

V_DD(V)

Figure 7. Typical High-Side (Source) Characteristics — High Drive (PTxDSn = 1)

3.6

Supply Current Characteristics

This section includes information about power supply current in various operating modes.

Table 7. Supply Current Characteristics

Parameter

Symbol

V_DD(V)¹

Typical²

Max

T (°C)

Run supply current³measured in FBE mode at

f_Bus= 8 MHz

3

2

3

2

3

2

3

2

3

2

3

2

3

2

3.5 mA

2.6 mA

490 μA

370 μA

1 mA

5 mA

—

85

RI_DD

Run supply current³measured in FBE mode at

1 mA

—

RI_DD

WI_DD

S1I_DD

f_Bus= 1 MHz

Wait mode supply current⁴measured in FBE at 8 MHz

Stop1 mode supply current

1.5 mA

1.2 μA

—

475 nA

470 nA

600 nA

550 nA

750 nA

680 nA

300 nA

70 μA

Stop2 mode supply current

2 μA

—

S2I_DD

S3I_DD

—

Stop3 mode supply current

6 μA

—

RTI adder to stop1, stop2, or stop3⁴

LVD adder to stop3 (LVDE = LVDSE = 1)⁴

—

60 μA

—

MC9S08QA4 Series MCU Data Sheet, Rev. 3

10

Freescale Semiconductor

Electrical Characteristics

1

2

3

4

3 V values are 100% tested; 2 V values are characterized but not tested.

Typicals are measured at 25 °C.

Does not include any DC loads on port pins.

Most customers are expected to find that auto-wakeup from a stop mode can be used instead of the higher current wait mode.

3.7

Internal Clock Source (ICS) Characteristics

Table 8. ICS Specifications (Temperature Range = –40 to 85°C Ambient)

Characteristic

Symbol

t_IRST

Min

—

Typical¹

60

Max

100

Unit

μs

Internal reference start-up time

f_{int_ut}

f_{int_t}

f_{dco_ut}

f_{dco_t}

Average internal reference frequency — untrimmed

Average internal reference frequency — trimmed

DCO output frequency range — untrimmed

DCO output frequency range — trimmed

25

32.7

—

41.66

39.06

21.33

20

kHz

MHz

31.25

12.8

16

16.8

—

Resolution of trimmed DCO output frequency at fixed voltage and

temperature²

Δf_{dco_res_t}

%f_dco

—

±0.1

±0.2

Total deviation of DCO output from trimmed frequency²

At 8 MHz over full voltage and temperature range

At 8 MHz and 3.6 V from 0 to 70 °C

Δf_{dco_t}

–1.0 to 0.5

±2

±1

±0.5

FLL acquisition time ^2,3

t_Acquire

C_Jitter

—

1.5

0.2

ms

%f_dco

0.02

Long term jitter of DCO output clock (averaged over 2 ms interval)

1

2

3

Data in Typical column was characterized at 3.0 V, 25 °C, or is typical recommended value.

This parameter is characterized and not tested on each device.

This specification applies to any time the FLL reference source or reference divider is changed, trim value changed.

MC9S08QA4 Series MCU Data Sheet, Rev. 3

Freescale Semiconductor

11

Electrical Characteristics

0.250%

0.200%

0.150%

0.100%

DEVIATION

0.050%

0.000%

–0.050%

1.6

2.1

2.6

3.1

3.6

V_DD

Figure 8. Deviation of DCO Output from Trimmed Frequency (8 MHz, 25 °C)

3.8

AC Characteristics

This section describes timing characteristics for each peripheral system.

MC9S08QA4 Series MCU Data Sheet, Rev. 3

12

Freescale Semiconductor

Electrical Characteristics

3.8.1

Control Timing

Table 9. Control Timing

Parameter

Symbol

Min

0

Typical¹

Max

10

Unit

MHz

μs

Bus frequency (t_cyc= 1/f_Bus

)

f_Bus

—

t_RTI

1000

Real-time interrupt internal oscillator period (see Table 9)

External reset pulse width²

700

100

1300

—

t_extrst

—

ns

IRQ pulse width

Asynchronous path²

Synchronous path³

t_ILIH

100

1.5 t_cyc

—

ns

KBIPx pulse width

Asynchronous path²

Synchronous path³

t_{ILIH, IHIL}

t

100

—

1.5 t_cyc

Port rise and fall time (load = 50 pF)⁴

Slew rate control disabled (PTxSE = 0)

Slew rate control enabled (PTxSE = 1)

t_Rise, t_Fall

t_MSSU

—

3

30

—

ns

BKGD/MS setup time after issuing background debug force

reset to enter user or BDM modes

500

—

BKGD/MS hold time after issuing background debug force

reset to enter user or BDM modes⁵

t_MSH

100

—

μs

1

2

3

Data in Typical column was characterized at 3.0 V, 25°C.

This is the shortest pulse that is guaranteed to be recognized.

This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or

may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.

4

5

Timing is shown with respect to 20% V_DDand 80% V_DDlevels. Temperature range –40°C to 85°C.

To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t_MSHafter V_DD

rises above V_LVD

.

1600

1400

1200

1000

800

= +3 σ

= Mean

= –3 σ

Period (μs)

600

400

200

0

–40

0

20

Temperature (°C)

Figure 9. Typical RTI Clock Period vs. Temperature

40

60

80

100

MC9S08QA4 Series MCU Data Sheet, Rev. 3

Freescale Semiconductor

13

Electrical Characteristics

t_extrst

RESET PIN

Figure 10. Reset Timing

t_IHIL

KBIPx

IRQ/KBIPx

t_ILIH

Figure 11. IRQ/KBIPx Timing

3.8.2

TPM/MTIM Module Timing

Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the

optional external source to the timer counter. These synchronizers operate from the current bus rate clock.

Table 10. TPM/MTIM Input Timing

Function

Symbol

Min

Max

Unit

External clock frequency

External clock period

f_TCLK

t_TCLK

t_clkh

0

f_Bus/4

—

Hz

t_cyc

4

External clock high time

External clock low time

Input capture pulse width

1.5

—

t_clkl

—

t_ICPW

—

t_TCLK

t_clkh

TCLK

t_clkl

Figure 12. Timer External Clock

MC9S08QA4 Series MCU Data Sheet, Rev. 3

14

Freescale Semiconductor

Electrical Characteristics

t_ICPW

TPMCHn

t_ICPW

Figure 13. Timer Input Capture Pulse

3.9

Analog Comparator (ACMP) Electricals

Table 11. Analog Comparator Electrical Specifications

Characteristic

Symbol

V_DD

Min

Typical

Max

Unit

Supply voltage

1.80

—

3.60

V

I_DDAC

Supply current (active)

—

V_SS– 0.3

—

20

—

V_DD

40

μA

V

Analog input voltage

V_AIN

V_AIO

V_H

Analog input offset voltage

Analog comparator hysteresis

20

9.0

mV

3.0

15.0

I_ALKG

t_AINIT

Analog input leakage current

—

1.0

μA

μs

Analog comparator initialization delay

3.10 ADC Characteristics

Table 12. 3 V 10-Bit ADC Operating Conditions

Characteristic

Conditions

Absolute

Symbol

Min

Typical¹

Max

Unit

Comment

Supply voltage

Input voltage

V_DD

1.8

V_SS

—

4.5

5

3.6

V_DD

5.5

7

V

V_ADIN

C_ADIN

R_ADIN

Input capacitance

Input resistance

pF

kΩ

—

Analog source

resistance

10 bit mode

_ADCK> 4 MHz

f_ADCK< 4 MHz

f

—

5

10

External to

MCU

R_AS

kΩ

8 bit mode (all valid f_ADCK

High Speed (ADLPC=0)

Low Power (ADLPC=1)

)

—

10

8.0

4.0

ADC conversion

clock frequency

0.4

f_ADCK

MHz

1

Typical values assume V_DD= 3.0 V, Temp = 25°C, f_ADCK=1.0 MHz unless otherwise stated. Typical values are for reference

only and are not tested in production.

MC9S08QA4 Series MCU Data Sheet, Rev. 3

Freescale Semiconductor

15

Electrical Characteristics

SIMPLIFIED

INPUT PIN EQUIVALENT

CIRCUIT

Z_ADIN

SIMPLIFIED

CHANNEL SELECT

CIRCUIT

Pad

Z_AS

leakage

due to

input

ADC SAR

ENGINE

R_AS

R_ADIN

protection

+

V_ADIN

–

C_AS

V_AS

+

–

R_ADIN

INPUT PIN

C_ADIN

Figure 14. ADC Input Impedance Equivalency Diagram

Table 13. 3 V 10-Bit ADC Characteristics

Characteristic

Conditions

Symbol

Min

Typical¹

Max

Unit

Comment

Supply current

ADLPC = 1

ADLSMP = 1

ADCO = 1

I_DDAD

—

120

—

μA

Supply current

ADLPC = 1

ADLSMP = 0

ADCO = 1

I_DDAD

—

202

288

532

—

Supply current

ADLPC = 0

ADLSMP = 1

ADCO = 1

I_DDAD

Supply current

ADLPC = 0

ADLSMP = 0

ADCO = 1

I_DDAD

646

μA

ADC asynchronous

clock source

High speed (ADLPC=0)

Low power (ADLPC=1)

2

3.3

2

5

t_ADACK

1/f_ADACK

=

f_ADACK

MHz

1.25

3.3

MC9S08QA4 Series MCU Data Sheet, Rev. 3

16

Freescale Semiconductor

Electrical Characteristics

Table 13. 3 V 10-Bit ADC Characteristics (continued)

Characteristic

Conditions

Symbol

Min

—

Typical¹

20

Max

—

Unit

Comment

Conversion time

(including sample

time)

Short sample (ADLSMP=0)

Long sample (ADLSMP=1)

Short sample (ADLSMP=0)

See

MC9S08QA4

Series

Reference

Manual for

conversion

time variances

ADCK

cycles

t_ADC

—

40

—

3.5

—

ADCK

cycles

Sample time

t_ADS

Long sample (ADLSMP=1)

—

23.5

—

10-bit mode

8-bit mode

10-bit mode

—

±1.5

±0.7

±0.5

±3.5

±1.5

±1.0

Includes

quantization

Total unadjusted error

E_TUE

LSB²

Monotonicity

and no

missing codes

guaranteed

Differential

non-linearity

DNL

8-bit mode

—

±0.3

±0.5

10-bit mode

8-bit mode

10-bit mode

8-bit mode

10-bit mode

8-bit mode

10-bit mode

8-bit mode

10-bit mode

8-bit mode

–40°C – 25°C

25°C – 85°C

—

0

±0.5

±0.3

±1.5

±0.5

±1.0

±0.5

—

±1.0

±0.5

±2.1

±0.7

±1.5

±0.5

±4

Integral non-linearity

Zero-scale error

INL

E_ZS

E_FS

E_Q

LSB²

V_ADIN= V_SS

Full-scale error

V_ADIN= V_DD

0

—

0

Quantization error

Input leakage error

—

±0.2

±0.1

1.646

1.769

Padleakage³*

R_AS

E_IL

0

±1.2

—

Temp sensor

slope

m

mV/°C

—

Temp sensor

voltage

25°C

V_TEMP25

—

701.2

—

mV

1

Typical values assume V_DD= 3.0 V, Temp = 25°C, f_ADCK= 1.0 MHz unless otherwise stated. Typical values are for reference

only and are not tested in production.

2

3

1 LSB = (V_REFH– V_REFL)/2^N

Based on input pad leakage current. Refer to pad electricals.

3.11 Flash Specifications

This section provides details about program/erase times and program-erase endurance for the flash memory.

MC9S08QA4 Series MCU Data Sheet, Rev. 3

Freescale Semiconductor

17

Electrical Characteristics

Program and erase operations do not require any special power sources other than the normal V supply. For more detailed

DD

information about program/erase operations, see MC9S08QA4 Series Reference Manual.

Table 14. Flash Characteristics

Characteristic

Symbol

Min

Typical

Max

Unit

Supply voltage for program/erase

–40°C to 85°C

V_prog/erase

V_Read

f_FCLK

t_Fcyc

1.8

150

5

—

3.6

V

Supply voltage for read operation

Internal FCLK frequency¹

Internal FCLK period (1/FCLK)

Byte program time (random location)²

Byte program time (burst mode)²

Page erase time²

V

—

200

6.67

kHz

μs

—

t_prog

9

t_Fcyc

t_Burst

4

t_Page

4000

20,000

Mass erase time²

t_Mass

Program/erase endurance³

T_Lto T_H= –40°C to + 85°C

T = 25°C

10,000

15

—

100,000

—

cycles

years

Data retention⁴

t_{D_ret}

100

—

1

2

The frequency of this clock is controlled by a software setting.

These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for

calculating approximate time to program and erase.

3

4

Typical endurance for flash was evaluated for this product family on the 9S12Dx64. For additional information on how

Motorola defines typical endurance, please refer to Engineering Bulletin EB619/D, Typical Endurance for Nonvolatile Memory.

Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated

to 25°C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer

to Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory.

MC9S08QA4 Series MCU Data Sheet, Rev. 3

18

Freescale Semiconductor

Ordering Information

4

Ordering Information

This section contains ordering numbers for MC9S08QA4 series devices. See below for an example of the device numbering

system.

Table 15. Device Numbering System

Memory

Package

Device Number

Flash

4 KB

2 KB

RAM

Type

Designator

Document No.

8 DFN

8 PDIP

8 NB SOIC

FQ

PA

DN

98ARL10557D

98ASB42420B

98ASB42564B

MC9S08QA4

MC9S08QA2

256 bytes

160 bytes

9

QA 4

XX E

C

MC S08

RoHS compliance indicator (E = yes)

Package designator (see Table 15)

Status

(MC = Fully qualified)

Memory

(9 = Flash-based)

Temperature range

(C = –40°C to 85°C)

Core

Family

Memory size (in KB)

5

Mechanical Drawings

The following pages contain mechanical specifications for MC9S08QA4 series package options.

•

8-pin DFN (plastic dual in-line pin)

8-pin NB SOIC (narrow body small outline integrated circuit)

8-pin PDIP (plastic dual in-line pin)

MC9S08QA4 Series MCU Data Sheet, Rev. 3

Freescale Semiconductor

19

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implementers to use Freescale Semiconductor products. There are no express or

implied copyright licenses granted hereunder to design or fabricate any integrated

circuits or integrated circuits based on the information in this document.

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Document Number: MC9S08QA4

Rev. 3

1/2009


型号：	MC9S08QA4_09
厂家：	Freescale
描述：	Technical Data 技术参数
文件：	总32页 (文件大小：2369K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC9S08QA4_09 [FREESCALE]

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