MC9S08QE32CWL [FREESCALE]
8-Bit HCS08 Central Processor Unit (CPU); 8位HCS08中央处理单元（CPU）的
| 型号： | MC9S08QE32CWL |
| 厂家： | 
Freescale |
| 描述： | 8-Bit HCS08 Central Processor Unit (CPU) |
| 文件： | 总44页 (文件大小：1209K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MC9S08QE32
Rev. 1, 6/2008
MC9S08QE32 Series
Covers: MC9S08QE32 and
MC9S08QE16
MC9S08QE32
48-QFN
Case 1314
7 mm2
44-LQFP
Case 824D
Features
32-LQFP
Case 873A
7 mm2
28-SOIC
Case 751F
•
•
•
8-Bit HCS08 Central Processor Unit (CPU)
– Up to 50.33 MHz HCS08 CPU at 3.6 V to 2.4 V, 40 MHz CPU
at 2.4 V to 2.1 V and 20 MHz CPU at 2.1 V to 1.8 V across
temperature range of –40°C to 85°C
– HC08 instruction set with added BGND instruction
– Support for up to 32 interrupt/reset sources
On-Chip Memory
– Flash read/program/erase over full operating voltage and
temperature
– Random-access memory (RAM)
– Breakpoint capability to allow single breakpoint setting during
in-circuit debugging (plus three breakpoints in on-chip debug
module)
– On-chip in-circuit emulator (ICE) debug module containing
three comparators and nine trigger modes. Eight deep FIFO for
storing change-of-flow addresses and event-only data. Debug
module supports both tag and force breakpoints
– Security circuitry to prevent unauthorized access to RAM and
flash contents
Power-Saving Modes
•
Peripherals
– ADC — 10-channel, 12-bit resolution; 2.5 μs conversion time;
automatic compare function; 1.7 mV/°C temperature sensor;
internal bandgap reference channel; operation in stop3; fully
functional from 3.6V to 1.8V
– Two very low power stop modes
– Reduced power wait mode
– Peripheral clock enable register can disable clocks to unused
modules, thereby reducing currents; allows clocks to remain
enabled to specific peripherals in stop3 mode.
– Very low power external oscillator that can be used in run, wait,
and stop modes to provide accurate clock source to real time
counter.
– ACMPx — Two analog comparators with selectable interrupt
on rising, falling, or either edge of comparator output; compare
option to fixed internal bandgap reference voltage; outputs can
be optionally routed to TPM module; operation in stop3
– SCIx — Two serial communications interface modules with
optional 13-bit break. Full duplex non-return to zero (NRZ);
LIN master extended break generation; LIN slave extended
break detection; wake up on active edge.
– 6 μs typical wake up time from stop3 mode
Clock Source Options
•
– Oscillator (XOSCVLP) — Loop-control Pierce oscillator;
crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or
1 MHz to 16 MHz
– Internal clock source (ICS) — Internal clock source module
containing a frequency-locked-loop (FLL) controlled by
internal or external reference; precision trimming of internal
reference allows 0.2% resolution and 2% deviation over
temperature and voltage; supports CPU frequencies from
4kHz to 50.33 MHz.
– SPI— One serial peripheral interface; full-duplex or
single-wire bidirectional; double-buffered transmit and
receive; master or slave mode; MSB-first or LSB-first shifting
– IIC — One IIC; up to 100 kbps with maximum bus loading;
multi-master operation; programmable slave address; interrupt
driven byte-by-byte data transfer; supports broadcast mode and
10-bit addressing
– TPMx — One 6-channel (TPM3) and two 3-channel (TPM1
and TPM2); selectable input capture, output compare, or
buffered edge- or center-aligned PWM on each channel;
– RTC — (Real-time counter) 8-bit modulus counter with binary
or decimal based prescaler; external clock source for precise
time base, time-of-day, calendar or task scheduling functions;
free running on-chip low power oscillator (1 kHz) for cyclic
wake-up without external components; runs in all MCU modes
Input/Output
•
System Protection
– Watchdog computer operating properly (COP) reset with option
to run from dedicated 1 kHz internal clock source or bus clock.
– Low-voltage warning with interrupt.
– Low-voltage detection with reset or interrupt
– Selectable trip points.
– Illegal opcode detection with reset
– Illegal address detection with reset
– Flash block protection
Development Support
•
•
– 40 GPIOs, including 1 output-only pin and 1 input-only pin
– 16 KBI interrupts with selectable polarity
– Hysteresis and configurable pull up device on all input pins;
Configurable slew rate and drive strength on all output pins.
Package Options
•
– Single-wire background debug interface
– 48-pin QFN, 44-pin LQFP, 32-pin LQFP, 28-pin SOIC
This document contains information on a product under development. Freescale reserves
the right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2008. All rights reserved.
Table of Contents
1
2
3
MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . 9
3.3 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 9
3.4 Thermal Characteristics. . . . . . . . . . . . . . . . . . . 10
3.5 ESD Protection and Latch-Up Immunity . . . . . . 11
3.6 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . 12
3.7 Supply Current Characteristics . . . . . . . . . . . . . 15
3.8 External Oscillator (XOSCVLP) Characteristics 16
3.9 Internal Clock Source (ICS) Characteristics . . . 18
3.10 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . 19
3.10.1Control Timing. . . . . . . . . . . . . . . . . . . . . 20
3.10.2TPM Module Timing . . . . . . . . . . . . . . . . 21
3.10.3SPI Timing . . . . . . . . . . . . . . . . . . . . . . . .21
3.11 Analog Comparator (ACMP) Electricals . . . . . . .25
3.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . .25
3.13 Flash Specifications . . . . . . . . . . . . . . . . . . . . . .28
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . .29
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . .29
5.1 Mechanical Drawings . . . . . . . . . . . . . . . . . . . . .29
4
5
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current.
Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Revision
Date
Description of Changes
1
6/4/2008
Initial public released.
Related Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual (MC9S08QE32RM)
Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module
information.
MC9S08QE32 MCU Series Data Sheet, Rev. 1
2
Freescale Semiconductor
MCU Block Diagram
1
MCU Block Diagram
The block diagram, Figure 1, shows the structure of the MC9S08QE32 MCU.
BKGD/MS
PTA7/TPM2CH2/ADP9
PTA6/TPM1CH2/ADP8
HCS08 CORE
DEBUG MODULE (DBG)
PTA5/IRQ/TPM1CLK/RESET
PTA4/ACMP1O/BKGD/MS
BDC
CPU
PTA3/KBI1P3/SCL/ADP3
REAL-TIME COUNTER
(RTC)
PTA2/KBI1P2/SDA/ADP2
PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1–
PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+
SCL
SDA
HCS08 SYSTEM CONTROL
IIC MODULE (IIC)
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
PTB7/SCL/EXTAL
RxD1
TxD1
IRQ
SERIAL COMMUNICATIONS
INTERFACE MODULE(SCI1)
PTB6/SDA/XTAL
COP
IRQ
LVD
PTB5/TPM1CH1/SS
RxD2
TxD2
PTB4/TPM2CH1/MISO
PTB3/KBI1P7/MOSI/ADP7
PTB2/KBI1P6/SPSCK/ADP6
PTB1/KBI1P5/TxD1/ADP5
PTB0/KBI1P4/RxD1/ADP4
SERIAL COMMUNICATIONS
INTERFACE MODULE(SCI2)
USER FLASH
(MC9S08QE32 = 32768 BYTES)
(MC9S08QE16 = 16384 BYTES)
SS
MISO
MOSI
SPSCK
SERIAL PERIPHERAL
INTERFACE MODULE(SPI)
USER RAM
(MC9S08QE32 = 2048 BYTES)
(MC9S08QE16 = 1024 BYTES)
TPM1CLK
PTC7/TxD2/ACMP2-
PTC6/RxD2/ACMP2+
PTC5/TPM3CH5/ACMP2O
PTC4/TPM3CH4
3-CHANNEL TIMER/PWM
MODULE (TPM1)
TPM1CH2-TPM1CH0
TPM2CLK
3-CHANNEL TIMER/PWM
MODULE (TPM2)
50.33 MHz INTERNAL CLOCK
SOURCE (ICS)
TPM2CH2-TPM2CH0
PTC3/TPM3CH3
PTC2/TPM3CH2
EXTAL
XTAL
TPM3CLK
PTC1/TPM3CH1
LOW-POWER OSCILLATOR
31.25 kHz to 38.4 kHz
1 MHz to 16 MHz
6-CHANNEL TIMER/PWM
MODULE (TPM3)
TPM3CH5-TPM3CH0
PTC0/TPM3CH0
(XOSCVLP)
ACMP1O
ACMP1–
ACMP1+
PTD7/KBI2P7
PTD6/KBI2P6
PTD5/KBI2P5
PTD4/KBI2P4
PTD3/KBI2P3
PTD2/KBI2P2
PTD1/KBI2P1
PTD0/KBI2P0
VSSAD
ANALOG COMPARATOR
(ACMP1)
VSS
VDD
V
DDAD
VOLTAGE REGULATOR
ACMP2O
ACMP2–
ACMP2+
VSSAD
VDDAD
ANALOG COMPARATOR
(ACMP2)
VSSAD/VREFL
VDDAD/VREFH
10-CHANNEL, 12-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC12)
ADP9-ADP0
VREFL
VREFH
PTE7/TPM3CLK
PTE6
KBI1P7-KBI1P0
KBI2P7-KBI2P0
KEYBOARD INTERRUPT
MODULE (KBI1)
PTE5
PTE4
PTE3/SS
KEYBOARD INTERRUPT
MODULE (KBI2)
PTE2/MISO
PTE1/MOSI
PTE0/TPM2CLK/SPSCK
pins not available on 28-pin packages
pins not available on 28-pin or 32-pin packages
pins not available on 28-pin, 32-pin, or 44-pin packages
Notes: When PTA5 is configured as RESET, pin becomes bi-directional with output being open-drain drive containing an internal pull-up device.
When PTA4 is configured as BKGD, pin becomes bi-directional.
For the 28-pin packages: VSSAD/VREFL and VDDAD/VREFH are double bonded to VSS and VDD respectively.
The 48-pin package is the only package with the option of having the SPI pins (SS, MISO, MOSI, and SPSCK) available on PTE3-0 pins.
Figure 1. MC9S08QE32 Series Block Diagram
MC9S08QE32 MCU Series Data Sheet, Rev. 1
Freescale Semiconductor
3
Pin Assignments
2
Pin Assignments
This section shows the pin assignments for the MC9S08QE32 Series devices.
PTA2/KBI1P2/SDA/ADP2
36
35
34
33
32
31
30
29
28
27
26
25
PTD1/KBI2P1
PTD0/KBI2P0
1
PTA3/KBI1P3/SCL/ADP3
PTD2/KBI2P2
2
PTE7/TPM3CLK
3
PTD3/KBI2P3
4
VDD
PTD4/KBI2P4
VDDAD
5
VREFH
VSS
6
VREFL
7
VDD
VSSAD
PTE4
8
VSS
9
PTA6/TPM1CH2/ADP8
PTA7/TPM2CH2/ADP9
PTB0/KBI1P4/RxD1/ADP4
PTB1/KBI1P5/TxD1/ADP5
PTB7/SCL/EXTAL
10
11
12
PTB6/SDA/XTAL
PTE6
Pins in bold are lost in the next lower pin count package.
Figure 2-2. 48-Pin QFN
MC9S08QE32 MCU Series Data Sheet, Rev. 1
4
Freescale Semiconductor
Pin Assignments
PTD1/KBI2P1
PTD0/KBI2P0
PTA2/KBI1P2/SDA/ADP2
1
33
32
31
30
29
28
27
26
25
24
23
PTA3/KBI1P3/SCL/ADP3
PTD2/KBI2P2
2
PTE7/TPM3CLK
3
PTD3/KBI2P3
VDD
4
VDDAD
PTD4/KBI2P4
5
VREFH
VREFL
VSS
6
VDD
7
PTA6/TPM1CH2/ADP8
PTA7/TPM2CH2/ADP9
VSSAD
8
VSS
9
PTB0/KBI1P4/RxD1/ADP4
PTB1/KBI1P5/TxD1/ADP5
PTB7/SCL/EXTAL
10
PTB6/SDA/XTAL 11
Pins in bold are lost in the next lower pin count package.
Figure 2-3. 44-pin LQFP
MC9S08QE32 MCU Series Data Sheet, Rev. 1
Freescale Semiconductor
5
Pin Assignments
31 30 29 28 27 26 25
32
PTD1/KBI2P1
1
2
3
4
5
6
7
8
24
23
PTA2/KBI1P2/SDA/ADP2
PTA3/KBI1P3/SCL/ADP3
PTD0/KBI2P0
VDD
22
21
20
19
18
17
PTD2/KBI2P2
PTD3/KBI2P3
VDDAD/VREFH
VSSAD/VREFL
VSS
PTA6/TPM1CH2/ADP8
PTA7/TPM2CH2/ADP9
PTB7/SCL/EXTAL
PTB0/KBIP4/RxD1/ADP4
PTB1/KBIP5/TxD1/ADP5
PTB6/SDA/XTAL
15 16
10 11 12 13 14
9
Pins in bold are lost in the next lower pin count package.
Figure 2-4. 32-LQFP
MC9S08QE32 MCU Series Data Sheet, Rev. 1
6
Freescale Semiconductor
Pin Assignments
PTC6/RxD2/ACMP2+
PTC7/TxD2/ACMP2-
PTC5/TPM3CH5/ACMP2O
PTC4/TPM3CH4
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
2
PTA5/IRQ/TPM1CLK/RESET
PTA4/ACMP1O/BKGD/MS
VDD
PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+
PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1-
PTA2/KBI1P2/SDA/ADP2
3
4
5
VDDAD/VREFH
VSSAD/VREFL
VSS
PTA3/KBI1P3/SCL/ADP3
PTA6/TPM1CH2/ADP8
6
7
PTA7/TPM2CH2/ADP9
8
PTB7/SCL/EXTAL
PTB6/SDA/XTAL
PTB5/TPM1CH1/SS
PTB0/KBI1P4/RxD1/ADP4
9
10
11
12
13
14
PTB1/KBI1P5/TxD1/ADP5
PTB2/KBI1P6/SPSCK/ADP6
PTB3/KBI1P7/MOSI/ADP7
PTC0/TPM3CH0
PTB4/TPM2CH1/MISO
PTC3/TPM3CH3
PTC2/TPM3CH2
PTC1/TPM3CH1
Figure 2-5. 28-pin SOIC
Table 2-1. MC9S08QE32 Series Pin Assignment by Package and Pin Sharing Priority
Pin Number <-- Lowest Priority --> Highest
48
44
32
28
Port Pin
Alt 1
Alt 2
Alt 3
Alt 4
1
2
1
2
1
2
—
—
—
5
PTD1
PTD0
PTE7
KBI2P1
KBI2P0
3
3
—
3
TPM3CLK
4
4
VDD
5
5
4
6
VDDAD
VREFH
VREFL
VSSAD
VSS
6
6
7
7
5
7
8
8
9
9
6
7
8
9
10
11
12
13
14
15
16
17
18
10
11
—
—
12
13
14
15
16
PTB7
SCL1
SDA1
EXTAL
XTAL
8
10 PTB6
—
—
9
—
—
PTE6
PTE5
11 PTB5
12 PTB4
13 PTC3
14 PTC2
TPM1CH1 SS2
TPM2CH1 MISO2
TPM3CH3
10
11
12
—
TPM3CH2
—
PTD7
KBI2P7
MC9S08QE32 MCU Series Data Sheet, Rev. 1
Freescale Semiconductor
7
Electrical Characteristics
Table 2-1. MC9S08QE32 Series Pin Assignment by Package and Pin Sharing Priority (continued)
Pin Number
<-- Lowest Priority --> Highest
48
44
32
28
Port Pin
Alt 1
Alt 2
Alt 3
Alt 4
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
17
18
19
20
21
22
23
24
25
26
—
—
—
13
14
15
16
17
18
19
20
—
—
—
—
21
22
23
24
25
26
27
28
—
—
—
—
29
30
31
32
—
—
PTD6
PTD5
KBI2P6
KBI2P5
15 PTC1
16 PTC0
17 PTB3
18 PTB2
19 PTB1
20 PTB0
21 PTA7
22 PTA6
TPM3CH1
TPM3CH0
KBI1P7
MOSI2
SPSCK2
ADP7
KBI1P6
ADP6
ADP5
ADP4
ADP9
ADP8
KBI1P5
TxD1
KBI1P4
RxD1
TPM2CH2
TPM1CH2
—
—
—
—
—
—
PTE4
27
28
29
30
31
32
33
34
35
36
37
—
VDD
VSS
PTD4
PTD3
PTD2
KBI2P4
KBI2P3
KBI2P2
KBI1P3
KBI1P2
KBI1P1
KBI1P0
TxD2
23 PTA3
24 PTA2
25 PTA1
26 PTA0
27 PTC7
28 PTC6
SCL1
SDA1
TPM2CH0 ADP13
TPM1CH0 ADP03
ADP3
ADP2
ACMP1-3
ACMP1+3
ACMP2-
ACMP2+
RxD2
SS2
MISO2
MOSI2
TPM2CLK SPSCK2
—
—
—
—
1
PTE3
PTE2
PTE1
PTE0
PTC5
PTC4
PTA5
PTA4
38
39
40
41
42
43
44
TPM3CH5
ACMP2O
2
TPM3CH4
3
IRQ
TPM1CLK RESET
4
ACMP1O BKGD
MS
1
2
3
IIC pins, SCL and SDA can be repositioned using IICPS in SOPT2; default reset
locations are PTA3 and PTA2.
SPI pins (SS, MISO, MOSI, and SPSCK) can be repositioned using SPIPS in SOPT2.
Default locations are PTB5, PTB4,PTB3, and PTB2.
If ADC and ACMP1 are enabled, both modules will have access to the pin.
3
Electrical Characteristics
3.1
Introduction
This section contains electrical and timing specifications for the MC9S08QE32 Series of microcontrollers available at the time
of publication.
MC9S08QE32 MCU Series Data Sheet, Rev. 1
8
Freescale Semiconductor
Electrical Characteristics
3.2
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:
Table 2. Parameter Classifications
Those parameters are guaranteed during production testing on each individual device.
P
C
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
T
Those parameters are derived mainly from simulations.
D
NOTE
The classification is shown in the column labeled “C” in the parameter
tables where appropriate.
3.3
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the
limits specified in Table 3 may affect device reliability or cause permanent damage to the device. For functional operating
conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised
that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for
instance, either V or V ) or the programmable pull-up resistor associated with the pin is enabled.
SS
DD
Table 3. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Supply voltage
VDD
IDD
VIn
ID
–0.3 to +3.8
120
V
mA
V
Maximum current into VDD
Digital input voltage
–0.3 to VDD + 0.3
± 25
Instantaneous maximum current
mA
Single pin limit (applies to all port pins)1, 2, 3
Storage temperature range
Tstg
–55 to 150
°C
1
2
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
All functional non-supply pins, except for PTA5 are internally clamped to VSS and VDD
.
MC9S08QE32 MCU Series Data Sheet, Rev. 1
Freescale Semiconductor
9
Electrical Characteristics
3
Power supply must maintain regulation within operating VDD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
IDD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).
3.4
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power
dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and
it is user-determined rather than being controlled by the MCU design. To take P into account in power calculations, determine
I/O
the difference between actual pin voltage and V or V and multiply by the pin current for each I/O pin. Except in cases of
SS
DD
unusually high pin current (heavy loads), the difference between pin voltage and V or V will be very small.
SS
DD
Table 4. Thermal Characteristics
Symbol
Rating
Value
Unit
Operating temperature range
(packaged)
TL to TH
–40 to 85
TA
°C
°C
Maximum junction temperature
TJM
95
Thermal resistance
Single-layer board
48-pin QFN
44-pin LQFP
32-pin LQFP
28-pin SOIC
81
68
66
57
θJA
°C/W
°C/W
Thermal resistance
Four-layer board
48-pin QFN
44-pin LQFP
32-pin LQFP
28-pin SOIC
26
46
54
42
θJA
The average chip-junction temperature (T ) in °C can be obtained from:
J
T = T + (P × θ )
JA
Eqn. 1
J
A
D
where:
T = Ambient temperature, °C
A
θ
= Package thermal resistance, junction-to-ambient, °C/W
JA
P = P + P
D
int
I/O
P
P
= I × V , Watts — chip internal power
= Power dissipation on input and output pins — user determined
int
I/O
DD DD
For most applications, P << P and can be neglected. An approximate relationship between P and T (if P is neglected)
I/O
int
D
J
I/O
is:
MC9S08QE32 MCU Series Data Sheet, Rev. 1
10
Freescale Semiconductor
Electrical Characteristics
P = K ÷ (T + 273°C)
Eqn. 2
D
J
Solving Equation 1 and Equation 2 for K gives:
K = P × (T + 273°C) + θ × (P )
2
Eqn. 3
D
A
JA
D
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring P (at equilibrium)
D
for a known T . Using this value of K, the values of P and T can be obtained by solving Equation 1 and Equation 2 iteratively
A
D
J
for any value of T .
A
3.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions must be used to avoid exposure to static discharge. Qualification tests are performed to ensure that
these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During
the device qualification ESD stresses were performed for the human body model (HBM), the machine model (MM) and the
charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
Table 5. ESD and Latch-up Test Conditions
Model
Description
Series resistance
Symbol
Value
Unit
Ω
Human
Body
R1
1500
Storage capacitance
C
100
3
pF
Number of pulses per pin
—
Machine
Series resistance
R1
0
Ω
Storage capacitance
C
200
3
pF
Number of pulses per pin
—
Latch-up Minimum input voltage limit
Maximum input voltage limit
–2.5
7.5
V
V
Table 6. ESD and Latch-Up Protection Characteristics
1
No.
1
Symbol
VHBM
VMM
Min
±2000
±200
±500
±100
Max
—
Unit
V
Rating
Human body model (HBM)
Machine model (MM)
2
—
V
VCDM
ILAT
3
Charge device model (CDM)
Latch-up current at TA = 85°C
—
V
4
—
mA
1
Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
MC9S08QE32 MCU Series Data Sheet, Rev. 1
Freescale Semiconductor
11
Electrical Characteristics
3.6
DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics.
Table 7. DC Characteristics
Num C
Characteristic
Operating Voltage
Symbol
Condition
Min
Typical1
Max
Unit
1
1.8
3.6
V
Output high
voltage2
All I/O pins,
low-drive strength
C
1.8 V, ILoad = –2 mA VDD – 0.5
—
—
P
T
2.7 V, ILoad = –10 mA VDD – 0.5
2.3 V, ILoad = –6 mA VDD – 0.5
1.8V, ILoad = –3 mA VDD – 0.5
—
—
—
—
—
—
2
VOH
V
mA
V
All I/O pins,
high-drive strength
C
Output high
current
D
C
Max total IOH for all ports IOHT
—
—
—
100
0.5
3
4
All I/O pins,
low-drive strength
1.8 V, ILoad = 2 mA
—
Output low
voltage
P
T
2.7 V, ILoad = 10 mA
2.3 V, ILoad = 6 mA
1.8 V, ILoad = 3 mA
—
—
—
—
—
—
0.5
0.5
0.5
VOL
All I/O pins,
high-drive strength
C
Output low
current
5
6
D
Max total IOL for all ports
all digital inputs
IOLT
VIH
—
—
100
mA
V
P
C
P
C
VDD > 2.3 V
VDD ≤ 1.8 V
VDD > 2.7 V
VDD ≤ 1.8 V
0.70 x VDD
—
—
—
—
—
Input high
voltage
0.85 x VDD
—
—
—
0.35 x VDD
0.30 x VDD
Input low
voltage
7
8
all digital inputs
VIL
Input
hysteresis
C
all digital inputs Vhys
0.06 x VDD
—
—
mV
nA
Input
P leakage
current
all input only pins
|IIn|
9
VIn = VDD or VSS
—
5
1000
(Per pin)
Hi-Z
(off-state)
leakage
current
all input/output
10
P
|IOZ
|
VIn = VDD or VSS
—
5
1000
52.5
nA
(per pin)
Pullup,
11 P Pulldown
resistors
all digital inputs, when RPU,
17.5
—
kΩ
enabled
RPD
Single pin limit
–0.2
–5
—
—
0.2
5
mA
mA
DCinjection
12 D current 3, 4,
IIC
VIN < VSS, VIN > VDD
Total MCU limit, includes
sum of all stressed pins
5
13 C Input Capacitance, all pins
14 C RAM retention voltage
15 C POR re-arm voltage6
16 D POR re-arm time
CIn
—
—
—
0.6
1.4
—
8
pF
V
VRAM
VPOR
tPOR
1.0
2.0
—
0.9
10
V
μs
Low-voltage detection threshold—
high range
VDD falling
VDD rising
2.11
2.16
2.16
2.21
2.22
2.27
17
P
VLVDH
V
MC9S08QE32 MCU Series Data Sheet, Rev. 1
12
Freescale Semiconductor
Electrical Characteristics
Table 7. DC Characteristics (continued)
Num C
Characteristic
Symbol
Condition
Min
Typical1
Max
Unit
Low-voltage detection threshold—
low range
VDD falling
VDD rising
1.80
1.88
1.82
1.90
1.91
1.99
18
19
20
21
P
P
P
C
VLVDL
V
Low-voltage warning threshold—
high range
VDD falling
VDD rising
2.36
2.36
2.46
2.46
2.56
2.56
VLVWH
VLVWL
V
V
Low-voltage warning threshold—
low range
VDD falling
2.11
2.16
2.16
2.21
2.22
2.27
VDD rising
Low-voltage inhibit reset/recover
hysteresis
22 P Bandgap Voltage Reference7
Vhys
VBG
—
80
—
mV
V
1.15
1.17
1.18
1
2
3
4
Typical values are measured at 25°C. Characterized, not tested
As the supply voltage rises, the LVD circuit will hold the MCU in reset until the supply has risen above VLVDL
All functional non-supply pins, except for PTA5 are internally clamped to VSS and VDD
.
.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
5
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result
in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or
if clock rate is very low (which would reduce overall power consumption).
6
7
Maximum is highest voltage that POR is guaranteed.
Factory trimmed at VDD = 3.0 V, Temp = 25°C
PULLDOWN RESISTOR TYPICALS
PULLUP RESISTOR TYPICALS
40
35
30
25
20
40
35
30
25
20
85°C
85°C
25°C
25°C
–40°C
–40°C
1.8
2.3
2.8
VDD (V)
3.3
3.6
1.8
2
2.2 2.4 2.6 2.8
3
3.2 3.4 3.6
VDD (V)
Figure 6. Pullup and Pulldown Typical Resistor Values (V = 3.0 V)
DD
MC9S08QE32 MCU Series Data Sheet, Rev. 1
Freescale Semiconductor
13
Electrical Characteristics
TYPICAL VOL VS IOL AT VDD = 3.0 V
TYPICAL VOL VS VDD
0.2
0.15
0.1
1.2
1
85°C
25°C
–40°C
0.8
0.6
0.4
0.2
0
85
25
–40
°
C, IOL = 2 mA
0.05
0
°
C, IOL = 2 mA
°
C, IOL = 2 mA
1
2
3
4
0
5
10
OL (mA)
15
20
VDD (V)
I
Figure 7. Typical Low-Side Driver (Sink) Characteristics — Low Drive (PTxDSn = 0)
TYPICAL VOL VS VDD
TYPICAL VOL VS IOL AT VDD = 3.0 V
1
0.4
0.3
0.2
0.1
85°C
85°C
25°C
–40°C
25°C
0.8
0.6
0.4
0.2
–40°C
IOL = 10 mA
IOL = 6 mA
IOL = 3 mA
0
0
0
10
20
30
1
2
3
4
VDD (V)
IOL (mA)
Figure 8. Typical Low-Side Driver (Sink) Characteristics — High Drive (PTxDSn = 1)
TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V
TYPICAL VDD – VOH VS VDD AT SPEC IOH
1.2
1
0.25
0.2
85°C
85
°
C, IOH = 2 mA
C, IOH = 2 mA
C, IOH = 2 mA
25°C
25
°
–40°C
–40
°
0.8
0.6
0.4
0.2
0
0.15
0.1
0.05
0
0
–5
–10
IOH (mA))
–15
–20
1
2
3
4
VDD (V)
Figure 9. Typical High-Side (Source) Characteristics — Low Drive (PTxDSn = 0)
MC9S08QE32 MCU Series Data Sheet, Rev. 1
14
Freescale Semiconductor
Electrical Characteristics
TYPICAL VDD – VOH VS VDD AT SPEC IOH
0.4
0.3
0.2
0.1
85°C
25°C
–40°C
TYPICAL V – V VS I AT V = 3.0 V
DD
OH
OH
DD
0.8
0.6
0.4
0.2
0
85°C
25°C
–40°C
IOH = –10 mA
IOH = –6 mA
I
OH = –3 mA
0
0
–5
–10
–15
–20
–25
–30
1
2
3
4
I
(mA)
OH
VDD (V)
Figure 10. Typical High-Side (Source) Characteristics — High Drive (PTxDSn = 1)
3.7
Supply Current Characteristics
This section includes information about power supply current in various operating modes.
Table 8. Supply Current Characteristics
Parameter
Run supply current
VDD
(V)
Bus
Temp
Typical1
Num
C
Symbol
Max
Unit
Freq
(°C)
P
T
T
T
C
T
T
T
T
T
25.165 MHz
20 MHz
17.3
13.75
5.59
1.03
11.5
9.5
20
—
FEI mode, all modules on
1
RIDD
3
mA
–40 to 85
8 MHz
—
1 MHz
—
Run supply current
FEI mode, all modules off
25.165 MHz
20 MHz
12.3
—
2
3
RIDD
3
3
mA
–40 to 85
–40 to 85
8 MHz
4.6
—
1 MHz
1.0
—
Run supply current
LPRS=0, all modules off
16 kHz FBILP
16 kHz FBELP
152
115
21.9
—
RIDD
μA
—
Run supply current
T
T
LPRS=1, all modules off,
running from Flash
—
—
4
5
RIDD 16 kHz FBELP
25.165 MHz
3
3
μA
μA
–40 to 85
–-40 to 85
Run supply current
LPRS=1, all modules off,
running from RAM
7.3
C
T
T
T
P
C
P
C
Wait mode supply current
FEI mode, all modules off
5740
4570
2000
730
6000
—
20 MHz
WIDD
8 MHz
—
1 MHz
—
Stop2 mode supply current
n/a
3
2
3
2
0.35
0.25
0.45
0.35
7.5
6.5
15
–40 to 85
–40 to 85
–40 to 85
–40 to 85
6
7
S2IDD
n/a
μA
μA
Stop3 mode supply current
No clocks active
n/a
S3IDD
n/a
13.2
MC9S08QE32 MCU Series Data Sheet, Rev. 1
Freescale Semiconductor
15
Electrical Characteristics
Table 8. Supply Current Characteristics (continued)
Parameter
VDD
(V)
Bus
Freq
Temp
(°C)
Typical1
Num
C
Symbol
Max
Unit
8
T
T
T
T
T
EREFSTEN=1
32 kHz
32 kHz
100 Hz
300 bps
1 kHz
500
70
—
—
—
—
—
nA
μA
μA
μA
nA
9
IREFSTEN=1
TPM PWM
10
11
12
12
SCI, SPI, or IIC
RTC using LPO
15
Low power
mode adders:
3
–40 to 85
200
RTC using
ICSERCLK
13
T
32 kHz
—
μA
1
LVD
14
15
T
T
n/a
n/a
—
—
μA
μA
100
20
ACMP
1
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
3.8
External Oscillator (XOSCVLP) Characteristics
Reference Figure 11 and Figure 12 for crystal or resonator circuits.
MC9S08QE32 MCU Series Data Sheet, Rev. 1
16
Freescale Semiconductor
Electrical Characteristics
Table 9. XOSC and ICS Specifications (Temperature Range = –40 to 85°C Ambient)
Num
C
Characteristic
Symbol
Min
Typical1
Max
Unit
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)
Low range (RANGE = 0)
High range (RANGE = 1), high gain (HGO = 1)
High range (RANGE = 1), low power (HGO = 0)
flo
fhi
fhi
32
1
1
—
—
—
38.4
16
8
kHz
MHz
MHz
1
C
Load capacitors
Low range (RANGE=0), low power (HGO=0)
Other oscillator settings
See Note 2
See Note 3
C1,C2
2
3
D
D
Feedback resistor
Low range, low power (RANGE=0, HGO=0)2
Low range, High Gain (RANGE=0, HGO=1)
High range (RANGE=1, HGO=X)
—
—
—
—
10
1
—
—
—
RF
MΩ
kΩ
Series resistor —
Low range, low power (RANGE = 0, HGO = 0)2
—
—
—
—
100
0
—
—
—
Low range, high gain (RANGE = 0, HGO = 1)
High range, low power (RANGE = 1, HGO = 0)
High range, high gain (RANGE = 1, HGO = 1)
RS
4
D
≥ 8 MHz
4 MHz
1 MHz
—
—
—
0
0
0
0
10
20
Crystal start-up time 4
Low range, low power
Low range, high power
High range, low power
High range, high power
t
—
—
—
—
200
400
5
—
—
—
—
CSTL
5
6
C
D
ms
t
CSTH
15
Square wave input clock frequency (EREFS = 0, ERCLKEN = 1)
FEE mode
fextal
0.03125
0
—
—
40
40
MHz
MHz
FBE or FBELP mode
1
2
3
4
Data in Typical column is characterized at 3.0 V, 25°C or is typical recommended value.
Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE=HGO=0.
See crystal or resonator manufacturer’s recommendation.
Proper PC board layout procedures must be followed to achieve specifications.
MC9S08QE32 MCU Series Data Sheet, Rev. 1
Freescale Semiconductor
17
Electrical Characteristics
XOSCVLP
EXTAL
XTAL
RS
RF
Crystal or Resonator
C1
C2
Figure 11. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain
XOSCVLP
EXTAL
XTAL
Crystal or Resonator
Figure 12. Typical Crystal or Resonator Circuit: Low Range/Low Power
3.9
Internal Clock Source (ICS) Characteristics
Table 10. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient)
Num
C
C
P
Characteristic
Average internal reference frequency - untrimmed
Average internal reference frequency - trimmed
Internal reference start-up time
Symbol
fint_ut
fint_t
Min
—
Typical1 Max
Unit
kHz
kHz
μs
1
2
3
32.768
—
—
31.25
39.06
tIRST
T
P
P
P
P
P
P
—
16
32
48
—
—
—
60
—
100
20
40
60
—
Low range (DFR=00)
DCO output frequency
Mid range (DFR=01)
trimmed2
fdco_u
4
5
—
MHz
MHz
High range (DFR=10)
—
DCO output frequency2
Low range (DFR=00)
19.92
39.85
59.77
Reference = 32768 Hz
and
High range (DFR=10)
DMX32 = 1
Mid range (DFR=01)
fdco_DMX32
—
—
Resolution of trimmed DCO output frequency at fixed voltage
and temperature (using FTRIM)
Δfdco_res_t
Δfdco_res_t
%fdco
%fdco
6
7
C
C
—
—
±0.1
±0.2
±0.2
±0.4
Resolution of trimmed DCO output frequency at fixed voltage
and temperature (not using FTRIM)
MC9S08QE32 MCU Series Data Sheet, Rev. 1
18
Freescale Semiconductor
Electrical Characteristics
Table 10. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient) (continued)
Num
C
Characteristic
Symbol
Min
Typical1 Max
Unit
Total deviation of trimmed DCO output frequency over voltage
and temperature
+ 0.5
±2
Δfdco_t
%fdco
8
C
—
–1.0
Total deviation of trimmed DCO output frequency over fixed
voltage and temperature range of 0°C to 70 °C
Δfdco_t
tAcquire
CJitter
%fdco
ms
9
C
C
C
—
—
—
± 0.5
—
±1
1
FLL acquisition time 3
10
11
Long term jitter of DCO output clock (averaged over 2-ms
interval) 4
%fdco
0.02
0.2
1
2
3
Data in Typical column is characterized at 3.0 V, 25°C or is typical recommended value.
The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or
changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as
the reference, this specification assumes it is already running.
4
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage
for a given interval.
3.10 AC Characteristics
This section describes timing characteristics for each peripheral system.
0.40%
0.20%
0.00%
–0.20%
DEVIATION
–0.40%
–0.60%
–0.80%
–60
–40
–20
0
20
40
60
80
100
120
140
TEMPERATURE
MC9S08QE32 MCU Series Data Sheet, Rev. 1
Freescale Semiconductor
19
Electrical Characteristics
3.10.1 Control Timing
Table 11. Control Timing
Symbol
Num
C
Rating
Bus frequency (tcyc = 1/fBus
Min
Typical1
Max
Unit
)
10
20
25.165
VDD ≤ 2.1V
2.1<VDD ≤ 2.4V
VDD > 2.4Vs
fBus
1
D
DC
—
—
MHz
tLPO
textrst
trstdrv
2
3
4
D
D
D
Internal low power oscillator period
700
100
—
—
—
1300
—
μs
ns
ns
External reset pulse width2
Reset low drive
34 x tcyc
—
BKGD/MS setup time after issuing background debug
force reset to enter user or BDM modes
tMSSU
tMSH
5
6
D
D
500
100
—
—
—
—
ns
BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes 3
μs
IRQ pulse width
Asynchronous path2
Synchronous path4
tILIH, IHIL
t
100
1.5 x tcyc
—
—
—
—
ns
ns
7
D
8
D
Keyboard interrupt pulse width
Asynchronous path2
tILIH, IHIL
t
100
1.5 x tcyc
—
—
—
—
Synchronous path5
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)5
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
t
Rise, tFall
ns
—
—
8
31
—
—
9
C
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
ns
—
—
7
24
—
—
Voltage regulator recovery time
tVRR
10
C
—
4
—
μs
1
2
Typical values are based on characterization data at VDD = 3.0V, 25°C unless otherwise stated.
This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources.
3
4
5
To enter BDM mode following a POR, BKGD/MS must be held low during the power-up and for a hold time of tMSH after VDD
rises above VLVD
.
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40°C to 85°C.
textrst
RESET PIN
Figure 13. Reset Timing
MC9S08QE32 MCU Series Data Sheet, Rev. 1
20
Freescale Semiconductor
Electrical Characteristics
tIHIL
KBIPx
IRQ/KBIPx
tILIH
Figure 14. IRQ/KBIPx Timing
3.10.2 TPM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the
optional external source to the timer counter. These synchronizers operate from the current bus rate clock.
Table 12. TPM Input Timing
No.
C
Function
Symbol
Min
Max
Unit
1
2
3
4
5
D
D
D
D
D
External clock frequency
External clock period
fTCLK
tTCLK
tclkh
0
fBus/4
—
Hz
tcyc
tcyc
tcyc
tcyc
4
External clock high time
External clock low time
Input capture pulse width
1.5
1.5
1.5
—
tclkl
—
tICPW
—
tTCLK
tclkh
TCLK
tclkl
Figure 15. Timer External Clock
tICPW
TPMCHn
TPMCHn
tICPW
Figure 16. Timer Input Capture Pulse
3.10.3 SPI Timing
Table 13 and Figure 17 through Figure 20 describe the timing requirements for the SPI system.
MC9S08QE32 MCU Series Data Sheet, Rev. 1
Freescale Semiconductor
21
Electrical Characteristics
Table 13. SPI Timing
Symbol
No.
C
Function
Operating frequency
Master
Slave
Min
Max
Unit
—
D
fop
tSPSCK
tLead
tLag
fBus/2048
0
fBus/21
fBus/4
Hz
SPSCK period
Master
Slave
1
2
3
4
5
6
D
D
D
D
D
D
2
4
2048
—
tcyc
tcyc
Enable lead time
Master
Slave
1/2
1
—
—
tSPSCK
tcyc
Enable lag time
Master
Slave
1/2
1
—
—
tSPSCK
tcyc
Clock (SPSCK) high or low time
Master
Slave
tWSPSCK
tcyc – 30
tcyc – 30
1024 tcyc
—
ns
ns
Data setup time (inputs)
Master
Slave
tSU
15
15
—
—
ns
ns
Data hold time (inputs)
Master
Slave
tHI
0
25
—
—
ns
ns
7
8
D
D
Slave access time
ta
—
—
1
1
tcyc
tcyc
Slave MISO disable time
tdis
Data valid (after SPSCK edge)
9
D
D
D
D
Master
Slave
tv
—
—
25
25
ns
ns
Data hold time (outputs)
Master
Slave
10
11
12
tHO
0
0
—
—
ns
ns
Rise time
Input
Output
tRI
tRO
—
—
tcyc – 25
25
ns
ns
Fall time
Input
Output
tFI
tFO
—
—
tcyc – 25
25
ns
ns
1
Max operating frequency limited to 8MHz when input filter disabled and high output drive strength enabled. Max
operating frequency limited to 5MHz when input filter enabled and high output drive strength disabled.
MC9S08QE32 MCU Series Data Sheet, Rev. 1
22
Freescale Semiconductor
Electrical Characteristics
SS1
(OUTPUT)
1
2
11
12
3
SPSCK
(CPOL = 0)
(OUTPUT)
4
4
SPSCK
(CPOL = 1)
(OUTPUT)
5
6
MISO
(INPUT)
MSB IN2
LSB IN
BIT 6 . . . 1
9
9
10
MOSI
(OUTPUT)
MSB OUT2
BIT 6 . . . 1
LSB OUT
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 17. SPI Master Timing (CPHA = 0)
SS(1)
(OUTPUT)
1
2
11
12
3
12
11
SPSCK
(CPOL = 0)
(OUTPUT)
4
4
SPSCK
(CPOL = 1)
(OUTPUT)
5
6
MISO
(INPUT)
MSB IN(2)
BIT 6 . . . 1
10
BIT 6 . . . 1
LSB IN
9
MOSI
(OUTPUT)
MASTER MSB OUT(2)
PORT DATA
MASTER LSB OUT
PORT DATA
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 18. SPI Master Timing (CPHA =1)
MC9S08QE32 MCU Series Data Sheet, Rev. 1
Freescale Semiconductor
23
Electrical Characteristics
SS
(INPUT)
11
12
3
1
12
11
SPSCK
(CPOL = 0)
(INPUT)
2
4
4
SPSCK
(CPOL = 1)
(INPUT)
8
7
10
9
10
MISO
(OUTPUT)
SEE
NOTE
BIT 6 . . . 1
SLAVE LSB OUT
MSB OUT
6
SLAVE
5
MOSI
(INPUT)
BIT 6 . . . 1
MSB IN
LSB IN
NOTE:
1. Not defined but normally MSB of character just received
Figure 19. SPI Slave Timing (CPHA = 0)
SS
(INPUT)
1
3
12
2
11
SPSCK
(CPOL = 0)
(INPUT)
4
4
11
12
SPSCK
(CPOL = 1)
(INPUT)
9
10
8
MISO
(OUTPUT)
SEE
BIT 6 . . . 1
SLAVE LSB OUT
LSB IN
SLAVE MSB OUT
NOTE
5
6
7
MOSI
(INPUT)
MSB IN
BIT 6 . . . 1
NOTE:
1. Not defined but normally LSB of character just received
Figure 20. SPI Slave Timing (CPHA = 1)
MC9S08QE32 MCU Series Data Sheet, Rev. 1
24
Freescale Semiconductor
Electrical Characteristics
3.11 Analog Comparator (ACMP) Electricals
Table 14. Analog Comparator Electrical Specifications
C
Characteristic
Symbol
VDD
Min
Typical
Max
Unit
D
Supply voltage
1.8
—
—
3.6
V
IDDAC
P
D
P
C
Supply current (active)
20
—
35
VDD
40
μA
V
Analog input voltage
VAIN
VAIO
VH
VSS – 0.3
Analog input offset voltage
Analog comparator hysteresis
20
9.0
mV
mV
3.0
—
15.0
IALKG
tAINIT
P
C
Analog input leakage current
—
—
1.0
1.0
μA
μs
Analog comparator initialization delay
—
3.12 ADC Characteristics
Table 15. 12-bit ADC Operating Conditions
C
Characteristic
Conditions
Symbol
Min
Typical1
Max
Unit
Comment
D
Supply voltage
Absolute
Delta to VDD (VDD-VDDAD
VDDAD
ΔVDDAD
ΔVSSAD
1.8
—
0
3.6
100
100
V
2
)
–100
–100
mV
mV
2
D
D
Ground voltage
Delta to VSS (VSS-VSSAD
)
0
Ref Voltage
High
VREFH
VADIN
CADIN
1.8
VREFL
—
VDDAD
—
VDDAD
VREFH
5.5
V
V
D
C
Input Voltage
Input
Capacitance
4.5
pF
C
C
Input
Resistance
RADIN
—
5
7
kΩ
kΩ
Analog Source
Resistance
12 bit mode
fADCK > 4 MHz
fADCK < 4 MHz
—
—
—
—
2
5
External to
MCU
10 bit mode
RAS
fADCK > 4 MHz
fADCK < 4 MHz
—
—
—
—
5
10
8 bit mode (all valid fADCK
High Speed (ADLPC=0)
Low Power (ADLPC=1)
)
—
—
—
—
10
8.0
4.0
D
ADC
Conversion
Clock Freq.
0.4
0.4
fADCK
MHz
1
2
Typical values assume VDDAD = 3.0 V, Temp = 25 °C, fADCK=1.0 MHz unless otherwise state. Typical values are for reference
only and are not tested in production.
DC potential difference.
MC9S08QE32 MCU Series Data Sheet, Rev. 1
Freescale Semiconductor
25
Electrical Characteristics
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
ZAS
leakage
due to
input
ADC SAR
ENGINE
RAS
RADIN
protection
+
VADIN
–
CAS
VAS
+
–
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 21. ADC Input Impedance Equivalency Diagram
Table 16. 12-bit ADC Characteristics (V
= V
, V
= V
)
SSAD
REFH
DDAD REFL
C
Characteristic
Conditions
Symbol
Min
Typical1
Max
Unit
Comment
Supply Current
ADLPC=1
ADLSMP=1
ADCO=1
T
IDDAD
—
—
—
—
120
—
—
—
1
μA
Supply Current
ADLPC=1
ADLSMP=0
ADCO=1
T
T
P
IDDAD
202
288
μA
μA
Supply Current
ADLPC=0
ADLSMP=1
ADCO=1
IDDAD
Supply Current
ADLPC=0
ADLSMP=0
ADCO=1
IDDAD
0.532
mA
P
P
ADC
Asynchronous
Clock Source
High Speed (ADLPC=0)
Low Power (ADLPC=1)
2
3.3
2
5
tADACK
1/fADACK
=
fADACK
MHz
1.25
3.3
MC9S08QE32 MCU Series Data Sheet, Rev. 1
26
Freescale Semiconductor
Electrical Characteristics
Table 16. 12-bit ADC Characteristics (V
= V
, V
= V
)
SSAD
REFH
Min
—
DDAD REFL
C
P
C
P
Characteristic
Conditions
Symbol
Typical1
20
Max
Unit
Comment
Conversion
Time(Including
sample time)
Short Sample (ADLSMP=0)
Long Sample (ADLSMP=1)
Short Sample (ADLSMP=0)
—
—
—
See ADC
chapter in the
QE32 Series
MCU
Reference
Manual for
conversion
time variances
ADCK
cycles
tADC
—
40
—
3.5
ADCK
cycles
Sample Time
tADS
ETUE
DNL
INL
C
Long Sample (ADLSMP=1)
—
23.5
—
T
P
T
T
P
T
T
T
T
T
P
T
T
P
T
12 bit mode
10 bit mode
8 bit mode
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
±3.0
±1
—
±2.5
±1.0
—
Total
Unadjusted
Error
Includes
quantization
LSB2
LSB2
LSB2
LSB2
LSB2
LSB2
LSB2
±0.5
±1.75
±0.5
±0.3
±1.5
±0.5
±0.3
±1.5
±0.5
±0.5
±1.0
±0.5
±0.5
–1 to 0
—
12 bit mode
10 bit mode3
8 bit mode3
12 bit mode
10 bit mode
8 bit mode
Differential
Non-Linearity
±1.0
±0.5
—
Integral
Non-Linearity
±1.0
±0.5
—
12 bit mode
10 bit mode
8 bit mode
Zero-Scale
Error
EZS
EFS
EQ
±1.5
±0.5
—
VADIN = VSSAD
12 bit mode
10 bit mode
8 bit mode
Full-Scale
Error
±1
VADIN = VDDAD
±0.5
—
12 bit mode
10 bit mode
8 bit mode
Quantization
Error
D
D
±0.5
±0.5
—
—
12 bit mode
10 bit mode
8 bit mode
±2
Input Leakage
Error
Padleakage4 *
RAS
EIL
±0.2
±0.1
1.646
1.769
±4
±1.2
—
-40°C to 25°C
25°C to 85°C
Temp Sensor
Slope
D
D
m
mV/°C
—
Temp Sensor
Voltage
25°C
VTEMP25
—
701.2
—
mV
1
Typical values assume VDDAD = 3.0 V, Temp = 25 °C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
MC9S08QE32 MCU Series Data Sheet, Rev. 1
Freescale Semiconductor
27
Electrical Characteristics
2
1 LSB = (VREFH – VREFL)/2N
3
4
Monotonicity and No-Missing-Codes guaranteed in 10 bit and 8 bit modes
Based on input pad leakage current. Refer to pad electricals.
3.13 Flash Specifications
This section provides details about program/erase times and program-erase endurance for flash memory.
Program and erase operations do not require any special power sources other than the normal V supply. For more detailed
DD
information about program/erase operations, see MC9S08QE32 Series Reference Manual Chapter 4 Memory.
Table 17. Flash Characteristics
C
Characteristic
Symbol
Min
Typical
Max
Unit
Supply voltage for program/erase
–40°C to 85°C
D
Vprog/erase
1.8
—
3.6
V
D
D
D
P
P
P
P
Supply voltage for read operation
Internal FCLK frequency1
Internal FCLK period (1/FCLK)
Byte program time (random location)(2)
Byte program time (burst mode)(2)
Page erase time2
Mass erase time(2)
Byte program current3
Page erase current3
VRead
fFCLK
tFcyc
1.8
150
5
—
3.6
200
6.67
V
—
kHz
μs
—
tprog
9
tFcyc
tFcyc
tFcyc
tFcyc
mA
tBurst
4
4000
20,000
4
tPage
tMass
RIDDBP
RIDDPE
—
—
—
—
6
mA
Program/erase endurance4
TL to TH = –40°C to 85°C
T = 25°C
C
C
10,000
15
—
100,000
—
—
cycles
years
Data retention5
tD_ret
100
—
1
2
The frequency of this clock is controlled by software setting.
These values are hardware state machine controlled. User code does not need to count cycles. This information is
supplied for calculating approximate time to program and erase.
3
4
The program and erase currents are additional to the standard run IDD. These values are measured at room temperatures
with VDD = 3.0 V, bus frequency = 4.0 MHz.
Typical endurance for flash was evaluated for this product family on the 9S12Dx64. For additional information on how
Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile
Memory.
5
Typical data retention values are based on intrinsic capability of the technology measured at high temperature and
de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale defines typical data retention,
please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.
MC9S08QE32 MCU Series Data Sheet, Rev. 1
28
Freescale Semiconductor
Ordering Information
4
Ordering Information
This section contains ordering information for Device Numbering System
Example of the device numbering system:
32
C
XX
MC 9 S08 QE
Status
(MC = Fully Qualified)
Package designator (see Table 18)
Temperature range
(C = –40°C to 85°C)
Memory
(9 = Flash-based)
Core
Approximate flash size in kbytes
Family
5
Package Information
Table 18. Package Descriptions
Pin Count
Package Type
Quad Flat No-Leads
Abbreviation
Designator
Case No.
Document No.
48
44
32
28
QFN
LQFP
LQFP
SOIC
FT
LD
LC
WL
1314
824D
873A
751F
98ARH99048A
98ASS23225W
98ASH70029A
98ASB42345B
Low Quad Flat Package
Low Quad Flat Package
Small Outline Integrated Circuit
5.1
Mechanical Drawings
The following pages are mechanical drawings for the packages described in Table 18. For the latest available drawings please
visit our web site (http://www.freescale.com) and enter the package’s document number into the keyword search box.
MC9S08QE32 MCU Series Data Sheet, Rev. 1
Freescale Semiconductor
29
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Document Number: MC9S08QE32
Rev. 1
6/2008
相关型号：
MC9S08QE64CLC
8-BIT, FLASH, 50.33MHz, MICROCONTROLLER, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LQFP-32
NXP
MC9S08QE64CLH
8-BIT, FLASH, 50.33MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, MS-026BCD, LQFP-64
NXP
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