MC9S08QE64CLD [NXP]
S08QE 8-bit MCU, S08 core, 64KB Flash, 50MHz, QFP 44;
| 型号： | MC9S08QE64CLD |
| 厂家： | 
NXP |
| 描述： | S08QE 8-bit MCU, S08 core, 64KB Flash, 50MHz, QFP 44 时钟 PC CD 微控制器 外围集成电路 |
| 文件： | 总52页 (文件大小：926K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: QFN_Addendum
Rev. 0, 07/2014
Freescale Semiconductor
Addendum
Addendum for New QFN
Package Migration
This addendum provides the changes to the 98A case outline numbers for products covered in this book.
Case outlines were changed because of the migration from gold wire to copper wire in some packages. See
the table below for the old (gold wire) package versus the new (copper wire) package.
To view the new drawing, go to Freescale.com and search on the new 98A package number for your
device.
For more information about QFN package use, see EB806: Electrical Connection Recommendations for
the Exposed Pad on QFN and DFN Packages.
© Freescale Semiconductor, Inc., 2014. All rights reserved.
Original (gold wire)
package document number package document number
Current (copper wire)
Part Number
Package Description
48 QFN
MC68HC908JW32
MC9S08AC16
MC9S908AC60
MC9S08AC128
MC9S08AW60
MC9S08GB60A
MC9S08GT16A
MC9S08JM16
MC9S08JM60
MC9S08LL16
MC9S08QE128
MC9S08QE32
MC9S08RG60
MCF51CN128
MC9RS08LA8
MC9S08GT16A
MC9S908QE32
MC9S908QE8
MC9S08JS16
MC9S08QB8
98ARH99048A
98ASA00466D
48 QFN
32 QFN
32 QFN
32 QFN
24 QFN
98ARL10606D
98ARH99035A
98ARE10566D
98ASA00071D
98ARL10608D
98ASA00466D
98ASA00473D
98ASA00473D
98ASA00736D
98ASA00734D
MC9S08QG8
MC9S08SH8
24 QFN
24 QFN
24 QFN
16 QFN
8 DFN
98ARL10605D
98ARE10714D
98ASA00087D
98ARE10614D
98ARL10557D
98ASA00474D
98ASA00474D
98ASA00602D
98ASA00671D
98ASA00672D
MC9RS08KB12
MC9S08QG8
MC9RS08KB12
MC9S08QG8
MC9RS08KA2
6 DFN
98ARL10602D
98ASA00735D
Addendum for New QFN Package Migration, Rev. 0
2
Freescale Semiconductor
Freescale Semiconductor
Data Sheet: Technical Data
An Energy Efficient Solution by Freescale
Document Number: MC9S08QE128
Rev. 7, 10/2008
MC9S08QE128
MC9S08QE128 Series
80-LQFP
Case 917A
14 mm2
64-LQFP
Case 840F
10 mm2
Covers: MC9S08QE128, MC9S08QE96, MC9S08QE64
• 8-Bit HCS08 Central Processor Unit (CPU)
– Up to 50.33-MHz HCS08 CPU above 2.4V, 40-MHz
CPU above 2.1V, and 20-MHz CPU above 1.8V, across
temperature range
– HC08 instruction set with added BGND instruction
– Support for up to 32 interrupt/reset sources
• On-Chip Memory
44-LQFP
Case 824D
10 mm2
48-QFN
Case 1314
7 mm2
32-LQFP
Case 873A
7 mm2
Eight deep FIFO for storing change-of-flow addresses
and event-only data. Debug module supports both tag
and force breakpoints.
– Flash read/program/erase over full operating voltage
and temperature
– Random-access memory (RAM)
– Security circuitry to prevent unauthorized access to
RAM and flash contents
• ADC — 24-channel, 12-bit resolution; 2.5 μs conversion
time; automatic compare function; 1.7 mV/°C temperature
sensor; internal bandgap reference channel; operation in
stop3; fully functional from 3.6V to 1.8V
• Power-Saving Modes
– Two low power stop modes; reduced power wait mode
– Peripheral clock enable register can disable clocks to
unused modules, reducing currents; allows clocks to
remain enabled to specific peripherals in stop3 mode
– Very low power external oscillator can be used in stop3
mode to provide accurate clock to active peripherals
– Very low power real time counter for use in run, wait,
and stop modes with internal and external clock sources
– 6 μs typical wake up time from stop modes
• Clock Source Options
• ACMPx — Two analog comparators with selectable
interrupt on rising, falling, or either edge of comparator
output; compare option to fixed internal bandgap reference
voltage; outputs can be optionally routed to TPM module;
operation in stop3
• SCIx — Two SCIs with full duplex non-return to zero
(NRZ); LIN master extended break generation; LIN slave
extended break detection; wake up on active edge
• SPIx— Two serial peripheral interfaces with Full-duplex or
single-wire bidirectional; Double-buffered transmit and
receive; MSB-first or LSB-first shifting
• IICx — Two IICs with; Up to 100 kbps with maximum bus
loading; Multi-master operation; Programmable slave
address; Interrupt driven byte-by-byte data transfer;
supports broadcast mode and 10 bit addressing
• TPMx — One 6-channel and two 3-channel; Selectable
input capture, output compare, or buffered edge- or
center-aligned PWMs on each channel
• RTC — 8-bit modulus counter with binary or decimal
based prescaler; External clock source for precise time
base, time-of-day, calendar or task scheduling functions;
Free running on-chip low power oscillator (1 kHz) for
cyclic wake-up without external components
– Oscillator (XOSC) — Loop-control Pierce oscillator;
Crystal or ceramic resonator range of 31.25 kHz to
38.4 kHz or 1 MHz to 16 MHz
– Internal Clock Source (ICS) — FLL controlled by
internal or external reference; precision trimming of
internal reference allows 0.2% resolution and 2%
deviation; supports CPU freq. from 2 to 50.33 MHz
• System Protection
– Watchdog computer operating properly (COP) reset
with option to run from dedicated 1-kHz internal clock
source or bus clock
– Low-voltage detection with reset or interrupt; selectable
trip points
– Illegal opcode detection with reset
– Flash block protection
• Input/Output
– 70 GPIOs and 1 input-only and 1 output-only pin
– 16 KBI interrupts with selectable polarity
– Hysteresis and configurable pull-up device on all input
pins; Configurable slew rate and drive strength on all
output pins.
• Development Support
– Single-wire background debug interface
– Breakpoint capability to allow single breakpoint setting
during in-circuit debugging (plus two more breakpoints)
– On-chip in-circuit emulator (ICE) debug module
containing two comparators and nine trigger modes.
– SET/CLR registers on 16 pins (PTC and PTE)
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale Semiconductor, Inc., 2008. All rights reserved.
Table of Contents
1
2
3
MC9S08QE128 Series Comparison. . . . . . . . . . . . . . . . . . . . .4
3.10.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.10.2 TPM Module Timing. . . . . . . . . . . . . . . . . . . . . 26
3.10.3 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.11 Analog Comparator (ACMP) Electricals . . . . . . . . . . . 30
3.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.13 Flash Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.1 Device Numbering System . . . . . . . . . . . . . . . . . . . . . 34
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1 Mechanical Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . 35
Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .12
3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .12
3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .13
3.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . .14
3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .18
3.8 External Oscillator (XOSC) Characteristics . . . . . . . . .21
3.9 Internal Clock Source (ICS) Characteristics . . . . . . . . .22
3.10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4
5
6
7
MC9S08QE128 Series Data Sheet, Rev. 7
2
Freescale Semiconductor
PTA7/TPM2CH2/ADP9
TPM1CH2-0
TPM1CLK
PTA6/TPM1CH2/ADP8
HCS08 CORE
3-CHANNEL TIMER/PWM
MODULE (TPM1)
PTA5/IRQ/TPM1CLK/RESET
PTA4/ACMP1O/BKGD/MS
PTA3/KBI1P3/SCL1/ADP3
CPU
ACMP1O
ACMP1+
ACMP1-
PTA2/KBI1P2/SDA1/ADP2
ANALOG COMPARATOR
(ACMP1)
PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1-
PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+
BDC
BKP
EXTAL
XTAL
INTERNAL CLOCK
SOURCE (ICS)
PTB7/SCL1/EXTAL
PTB6/SDA1/XTAL
HCS08 SYSTEM CONTROL
OSCILLATOR (XOSC)
PTB5/TPM1CH1/SS1
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
3
PTB4/TPM2CH1/MISO1
PTB3/KBI1P7/MOSI1/ADP7
PTB2/KBI1P6/SPSCK1/ADP6
PTB1/KBI1P5/TxD1/ADP5
PTB0/KBI1P4/RxD1/ADP4
TPM2CH2-0
TPM2CLK
3-CHANNEL TIMER/PWM
MODULE (TPM2)
COP
INT
LVD
IRQ
SCL1
SDA1
ACMP2+
IIC MODULE (IIC1)
PTC7/TxD2/ACMP2-
PTC6/RxD2/ACMP2+
PTC5/TPM3CH5/ACMP2O
PTC4/TPM3CH4/RSTO
PTC3/TPM3CH3
ACMP2O
ACMP2-
ANALOG COMPARATOR
(ACMP2)
USER FLASH
128K / 96K / 64K
TPM3CH5-0
PTC2/TPM3CH2
6
6-CHANNEL TIMER/PWM
MODULE (TPM3)
PTC1/TPM3CH1
TPM3CLK
10
PTC0/TPM3CH0
USER RAM
8K / 6K / 4K
PTD7/KBI2P7
PTD6/KBI2P6
TxD1
RxD1
SERIAL COMMUNICATIONS
INTERFACE (SCI1)
PTD5/KBI2P5
PTD4/KBI2P4
DEBUG MODULE (DBG)
SS2
PTD3/KBI2P3/SS2
PTD2/KBI2P2/MISO2
PTD1/KBI2P1/MOSI2
PTD0/KBI2P0/SPSCK2
MISO2
MOSI2
SPSCK2
SERIAL PERIPHERAL
INTERFACE MODULE (SPI2)
REAL TIME COUNTER (RTC)
VDD
VDD
PTE7/TPM3CLK
PTE6
TxD2
RxD2
VOLTAGE
SERIAL COMMUNICATIONS
INTERFACE (SCI2)
VSS
VSS
REGULATOR
PTE5
PTE4
SS1
PTE3/SS1
PTJ7
PTJ6
PTJ5
PTJ4
PTJ3
PTJ2
PTJ1
PTJ0
MISO1
MOSI1
SPSCK1
PTE2/MISO1
PTE1/MOSI1
PTE0/TPM2CLK/SPSCK1
SERIAL PERIPHERAL
INTERFACE MODULE (SPI1)
PTF7/ADP17
PTF6/ADP16
PTF5/ADP15
PTF4/ADP14
PTF3/ADP13
PTF2/ADP12
PTF1/ADP11
PTF0/ADP10
24-CHANNEL,12-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC)
VREFH
VREFL
VDDA
VSSA
SDA2
SCL2
PTH7/SDA2
PTH6/SCL2
PTH5
IIC MODULE (IIC2)
PTG7/ADP23
PTG6/ADP22
PTG5/ADP21
PTG4/ADP20
PTG3/ADP19
PTG2/ADP18
PTG1
PTH4
PTH3
PTH2
PTH1
- V
/V
internally connected to V
/V
in 48-pin and 32-pin packages
REFH REFL
DDA SSA
PTH0
- V and V pins are each internally connected to two pads in 32-pin package
DD
SS
PTG0
Figure 1. MC9S08QE128 Series Block Diagram
MC9S08QE128 Series Data Sheet, Rev. 7
Freescale Semiconductor
3
MC9S08QE128 Series Comparison
1
MC9S08QE128 Series Comparison
The following table compares the various device derivatives available within the MC9S08QE128 series.
Table 1. MC9S08QE128 Series Features by MCU and Package
Feature
MC9S08QE128
MC9S08QE96
MC9S08QE64
Flash size (bytes)
RAM size (bytes)
Pin quantity
ACMP1
ACMP2
ADC channels
DBG
131072
8064
98304
6016
65536
4096
80 64 48 44 80 64 48 44 64 48 44 32
yes
yes
24 22 10 10 24 22 10 10 22 10 10 10
yes
ICS
yes
IIC1
yes
IIC2
yes yes no no yes yes no no yes no no no
IRQ
yes
KBI
16 16 16 16 16 16 16 16 16 16 16 12
Port I/O1
70 54 38 34 70 54 38 34 54 38 34 26
RTC
yes
yes
yes
yes
yes
3
SCI1
SCI2
SPI1
SPI2
TPM1 channels
TPM2 channels
TPM3 channels
XOSC
3
6
yes
1
Port I/O count does not include the input only PTA5/IRQ/TPM1CLK/RESET or the output
only PTA4/ACMP1O/BKGD/MS.
MC9S08QE128 Series Data Sheet, Rev. 7
4
Freescale Semiconductor
Pin Assignments
2
Pin Assignments
This section describes the pin assignments for the available packages. See Table 2 for pin availability by package pin-count.
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
PTD1/KBI2P1/MOSI2
PTD0/KBI2P0/SPSCK2
PTH7/SDA2
PTA2/KBI1P2/SDA1/ADP2
PTA3/KBI1P3/SCL1/ADP3
PTD2/KBI2P2/MISO2
PTD3/KBI2P3/SS2
PTD4/KBI2P4
PTH6/SCL2
PTH5
PTH4
PTE7/TPM3CLK
PTJ0
PTJ1
PTF0/ADP10
V
DD
V
DDAD
PTF1/ADP11
9
V
REFH
10
11
12
13
14
15
16
17
18
19
20
V
V
SS
V
REFL
DD
V
SSAD
PTE4
V
SS
PTA6/TPM1CH2/ADP8
PTA7/TPM2CH2/ADP9
PTF2/ADP12
PTB7/SCL1/EXTAL
PTB6/SDA1/XTAL
PTH3
PTF3/ADP13
PTJ2
PTH2
PTH1
PTH0
PTJ3
PTB0/KBI1P4/RxD1/ADP4
PTB1/KBI1P5/TxD1/ADP5
PTE6
Pins in bold are added from the next smaller package.
Figure 2. Pin Assignments in 80-Pin LQFP
MC9S08QE128 Series Data Sheet, Rev. 7
Freescale Semiconductor
5
Pin Assignments
PTD1/KBI2P1/MOSI2
PTD0/KBI2P0/SPSCK2
PTH7/SDA2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
PTA2/KBI1P2/SDA11/ADP2
PTA3/KBI1P3/SCL1/ADP3
PTD2/KBI2P2/MISO2
PTD3/KBI2P3/SS2
PTD4/KBI2P4
PTH6/SCL2
PTE7/TPM3CLK
V
PTF0/ADP10
DD
V
PTF1/ADP11
DDAD
V
V
REFH
SS
V
V
REFL
9
DD
V
PTE4
SSAD
10
11
12
13
14
15
16
V
PTA6/TPM1CH2/ADP8
PTA7/TPM2CH2/ADP9
PTF2/ADP12
SS
PTB7/SCL1/EXTAL
PTB6/SDA1/XTAL
PTF3/ADP13
PTH1
PTH0
PTE6
PTB0/KBI1P4/RxD1/ADP4
PTB1/KBI1P5/TxD1/ADP5
Pins in bold are added from the next smaller package.
Figure 3. Pin Assignments in 64-Pin LQFP Package
MC9S08QE128 Series Data Sheet, Rev. 7
6
Freescale Semiconductor
Pin Assignments
PTA2/KBI1P2/SDA1/ADP2
36
35
34
33
32
31
30
29
28
27
26
25
PTD1/KBI2P1/MOSI2
PTD0/KBI2P0/SPSCK2
1
2
PTA3/KBI1P3/SCL1/ADP3
PTD2/KBI2P2/MISO2
PTD3/KBI2P3/SS2
PTD4/KBI2P4
PTE7/TPM3CLK 3
4
VDD
VDDAD
5
VREFH
V
6
SS
VREFL
7
V
DD
VSSAD
PTE4
8
VSS
9
PTA6/TPM1CH2/ADP8
PTA7/TPM2CH2/ADP9
PTB0/KBI1P4/RxD1/ADP4
PTB1/KBI1P5/TxD1/ADP5
PTB7/SCL1/EXTAL
10
11
12
PTB6/SDA11/XTAL
PTE6
Figure 4. Pin Assignments in 48-Pin QFN Package
MC9S08QE128 Series Data Sheet, Rev. 7
Freescale Semiconductor
7
Pin Assignments
PTD1/KBI2P1/MOSI2
PTA2/KBI1P2/SDA1/ADP2
1
33
32
31
30
29
28
27
26
25
24
23
PTD0/KBI2P0/SPSCK2
PTA3/KBI1P3/SCL1/ADP3
PTD2/KBI2P2/MISO2
PTD3/KBI2P3/SS2
PTD4/KBI2P4
2
PTE7/TPM3CLK
3
VDD
4
VDDAD
5
VREFH
VREFL
VSS
6
VDD
7
PTA6/TPM1CH2/ADP8
PTA7/TPM2CH2/ADP9
VSSAD
8
VSS
9
PTB0/KBI1P4/RxD1/ADP4
PTB1/KBI1P5/TxD1/ADP5
PTB7/SCL1/EXTAL
10
PTB6/SDA1/XTAL 11
Figure 5. Pin Assignments in 44-Pin LQFP Package
MC9S08QE128 Series Data Sheet, Rev. 7
8
Freescale Semiconductor
Pin Assignments
31 30 29 28 27 26 25
32
PTD1/KBI2P1/MOSI2
PTD0/KBI2P0/SPSCK2
1
PTA2/KBIP2/SDA1/ADP2
24
23
22
21
20
19
18
17
PTA3/KBIP3/SCL1/ADP3
2
3
4
5
6
7
8
VDD
PTD2/KBI2P2/MISO2
PTD3/KBI2P3/SS2
VREFH/VDDAD
PTA6/TPM1CH2/ADP8
PTA7/TPM2CH2/ADP9
VREFL/VSSAD
VSS
PTB0/KBI1P4/RxD1/ADP4
PTB1/KBI1P5/TxD1/ADP5
PTB7/SCL1/EXTAL
PTB6/SDA1/XTAL
9
15 16
10 11 12 13 14
Figure 6. Pin Assignments 32-Pin LQFP Package
MC9S08QE128 Series Data Sheet, Rev. 7
Freescale Semiconductor
9
Pin Assignments
Table 2. MC9S08QE128 Series Pin Assignment by Package and Pin Count
Pin Number
Lowest
←⎯
Priority
⎯→
Highest
80
64
48
44
32
Port Pin
Alt 1
Alt 2
Alt 3
Alt 4
1
1
1
1
1
2
PTD1
PTD0
PTH7
PTH6
PTH5
PTH4
PTE7
KBI2P1
KBI2P0
SDA2
MOSI2
2
2
2
2
SPSCK2
3
3
—
—
—
—
3
—
—
—
—
3
—
—
—
—
—
3
4
4
SCL2
5
—
—
5
6
7
TPM3CLK
8
6
4
4
VDD
9
7
5
5
4
VDDA
VREFH
VREFL
VSSA
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
8
6
6
—
—
5
9
7
7
10
11
12
13
—
—
14
15
16
17
18
19
20
21
22
23
24
—
—
—
—
25
26
27
28
29
30
31
32
8
8
9
9
6
10
11
—
—
—
—
12
13
14
15
16
17
18
19
20
—
—
—
—
21
22
—
—
—
—
23
24
10
11
—
—
—
—
—
—
12
13
14
15
16
17
18
—
—
—
—
19
20
—
—
—
—
21
22
7
PTB7
PTB6
PTH3
PTH2
PTH1
PTH0
PTE6
PTE5
PTB5
SCL1
SDA1
EXTAL
XTAL
8
—
—
—
—
—
—
9
TPM1CH1 SS1
TPM2CH1 MISO1
TPM3CH3
TPM3CH2
KBI2P7
10 PTB4
11 PTC3
12 PTC2
—
—
—
—
—
—
—
PTD7
PTD6
PTD5
PTJ7
PTJ6
PTJ5
PTJ4
KBI2P6
KBI2P5
13 PTC1
14 PTC0
TPM3CH1
TPM3CH0
—
—
—
—
PTF7
PTF6
PTF5
PTF4
ADP17
ADP16
ADP15
ADP14
ADP7
15 PTB3
16 PTB2
KBI1P7
KBI1P6
MOSI1
SPSCK1
ADP6
MC9S08QE128 Series Data Sheet, Rev. 7
10
Freescale Semiconductor
Pin Assignments
Table 2. MC9S08QE128 Series Pin Assignment by Package and Pin Count (continued)
Pin Number
Lowest
←⎯
Priority
⎯→
Highest
80
64
48
44
32
Port Pin
Alt 1
Alt 2
Alt 3
Alt 4
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
33
34
—
—
35
36
37
38
39
40
41
42
43
—
—
44
45
46
47
48
49
50
51
52
—
—
—
—
53
54
55
56
57
58
59
60
61
62
63
64
25
26
—
—
—
—
27
28
29
30
31
—
—
—
—
32
33
34
35
36
37
38
39
40
—
—
—
—
41
42
—
—
—
—
43
44
45
46
47
48
23
24
—
—
—
—
25
26
—
27
28
—
—
—
—
29
30
31
32
33
34
35
36
37
—
—
—
—
—
38
—
—
—
—
39
40
41
42
43
44
17 PTB1
18 PTB0
KBI1P5
KBI1P4
TxD1
ADP5
RxD1
ADP4
—
—
—
—
PTJ3
PTJ2
PTF3
PTF2
ADP13
ADP12
ADP9
19 PTA7
20 PTA6
TPM2CH2
TPM1CH2
ADP8
—
—
—
—
—
—
—
—
PTE4
VDD
VSS
PTF1
PTF0
PTJ1
PTJ0
PTD4
ADP11
ADP10
KBI2P4
KBI2P3
KBI2P2
KBI1P3
KBI1P2
KBI1P1
KBI1P0
TxD2
21 PTD3
22 PTD2
23 PTA3
24 PTA2
25 PTA1
26 PTA0
27 PTC7
28 PTC6
SS2
MISO2
SCL1
SDA1
ADP3
ADP2
TPM2CH0 ADP1
TPM1CH0 ADP0
ACMP1-
ACMP1+
ACMP2-
ACMP2+
ADP23
ADP22
ADP21
ADP20
RxD2
—
—
—
—
—
—
—
—
—
—
—
—
PTG7
PTG6
PTG5
PTG4
PTE3
PTE2
PTG3
PTG2
PTG1
PTG0
PTE1
PTE0
SS1
MISO1
ADP19
ADP18
MOSI1
TPM2CLK SPSCK1
TPM3CH5
29 PTC5
30 PTC4
31 PTA5
32 PTA4
ACMP2O
TPM3CH4 RSTO
IRQ
TPM1CLK RESET
ACMP1O BKGD
MS
MC9S08QE128 Series Data Sheet, Rev. 7
Freescale Semiconductor
11
Electrical Characteristics
3
Electrical Characteristics
3.1
Introduction
This section contains electrical and timing specifications for the MC9S08QE128 series of microcontrollers available at the time
of publication.
3.2
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:
Table 3. Parameter Classifications
Those parameters are guaranteed during production testing on each individual device.
P
C
Those parameters are achieved by the design characterization by measuring a statistically relevant sample
size across process variations.
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
T
Those parameters are derived mainly from simulations.
D
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
3.3
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the
limits specified in Table 4 may affect device reliability or cause permanent damage to the device. For functional operating
conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised
that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for
instance, either V or V ) or the programmable pull-up resistor associated with the pin is enabled.
SS
DD
Table 4. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Supply voltage
VDD
IDD
VIn
ID
–0.3 to +3.8
120
V
mA
V
Maximum current into VDD
Digital input voltage
–0.3 to VDD + 0.3
± 25
Instantaneous maximum current
mA
Single pin limit (applies to all port pins)1, 2, 3
Storage temperature range
Tstg
–55 to 150
°C
1
2
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
All functional non-supply pins are internally clamped to VSS and VDD
.
MC9S08QE128 Series Data Sheet, Rev. 7
12
Freescale Semiconductor
Electrical Characteristics
Power supply must maintain regulation within operating VDD range during instantaneous and
3
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
IDD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).
3.4
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power
dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and
it is user-determined rather than being controlled by the MCU design. To take P into account in power calculations, determine
I/O
the difference between actual pin voltage and V or V and multiply by the pin current for each I/O pin. Except in cases of
SS
DD
unusually high pin current (heavy loads), the difference between pin voltage and V or V will be very small.
SS
DD
Table 5. Thermal Characteristics
Rating
Symbol
Value
Unit
Operating temperature range (packaged)
Maximum junction temperature
TA
–40 to 85
95
°C
°C
TJM
Thermal resistance
Single-layer board
32-pin LQFP
44-pin LQFP
48-pin QFN
64-pin LQFP
80-pin LQFP
82
68
81
69
60
θJA
°C/W
°C/W
θJA
Thermal resistance
Four-layer board
32-pin LQFP
44-pin LQFP
48-pin QFN
64-pin LQFP
80-pin LQFP
54
46
26
50
47
θJA
°C/W
°C/W
θJA
The average chip-junction temperature (T ) in °C can be obtained from:
J
T = T + (P × θ )
JA
Eqn. 1
J
A
D
where:
T = Ambient temperature, °C
A
θ
= Package thermal resistance, junction-to-ambient, °C/W
JA
P = P + P
D
int
I/O
P
P
= I × V , Watts — chip internal power
= Power dissipation on input and output pins — user determined
int
I/O
DD DD
MC9S08QE128 Series Data Sheet, Rev. 7
Freescale Semiconductor
13
Electrical Characteristics
For most applications, P << P and can be neglected. An approximate relationship between P and T (if P is neglected)
I/O
int
D
J
I/O
is:
P = K ÷ (T + 273°C)
Eqn. 2
D
J
Solving Equation 1 and Equation 2 for K gives:
K = P × (T + 273°C) + θ × (P )
2
Eqn. 3
D
A
JA
D
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring P (at equilibrium)
D
for a known T . Using this value of K, the values of P and T can be obtained by solving Equation 1 and Equation 2 iteratively
A
D
J
for any value of T .
A
3.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure
that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During
the device qualification ESD stresses were performed for the human body model (HBM), the machine model (MM) and the
charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
Table 6. ESD and Latch-up Test Conditions
Model
Description
Series resistance
Symbol
Value
Unit
R1
C
1500
100
3
Ω
Human
Body
Storage capacitance
Number of pulses per pin
Series resistance
pF
—
R1
C
0
Ω
Machine Storage capacitance
Number of pulses per pin
200
3
pF
—
Minimum input voltage limit
Latch-up
– 2.5
7.5
V
V
Maximum input voltage limit
Table 7. ESD and Latch-Up Protection Characteristics
No.
Rating1
Symbol
Min
Max
Unit
1
2
3
4
Human body model (HBM)
Machine model (MM)
VHBM
VMM
VCDM
ILAT
± 2000
± 200
± 500
± 100
—
—
—
—
V
V
Charge device model (CDM)
Latch-up current at TA = 85°C
V
mA
1
Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
MC9S08QE128 Series Data Sheet, Rev. 7
14
Freescale Semiconductor
Electrical Characteristics
3.6
DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics.
Table 8. DC Characteristics
Num C
Characteristic
Operating Voltage
Symbol
Condition
Min
Typ1
Max
Unit
1
1.82
3.6
V
Output high
voltage
All I/O pins,
low-drive strength
C
1.8 V, ILoad = –2 mA VDD – 0.5
—
—
P
2
All I/O pins,
high-drive strength
2.7 V, ILoad = –10 mA VDD – 0.5
2.3 V, ILoad = –6 mA VDD – 0.5
1.8V, ILoad = –3 mA VDD – 0.5
—
—
—
—
—
—
VOH
IOHT
VOL
V
mA
V
T
C
Output high
current
Max total IOH for all
ports
3
4
D
C
—
—
—
100
0.5
Output low
voltage
All I/O pins,
low-drive strength
1.8 V, ILoad = 2 mA
—
P
T
All I/O pins,
high-drive strength
2.7 V, ILoad = 10 mA
2.3 V, ILoad = 6 mA
1.8 V, ILoad = 3 mA
—
—
—
—
—
—
0.5
0.5
0.5
C
Output low
current
Max total IOL for all
ports
5
6
D
IOLT
—
—
100
mA
V
P
C
P
C
Input high
voltage
all digital inputs
VDD > 2.7 V
VDD > 1.8 V
VDD > 2.7 V
VDD >1.8 V
0.70 x VDD
0.85 x VDD
—
—
—
—
—
—
—
—
VIH
Input low voltage
all digital inputs
0.35 x VDD
0.30 x VDD
—
7
VIL
—
8
9
C Input hysteresis
all digital inputs Vhys
0.06 x VDD
mV
Input leakage
current
all input only pins
|IIn|
P
VIn = VDD or VSS
VIn = VDD or VSS
—
—
—
—
1
1
μA
(Per pin)
Hi-Z (off-state)
P
all input/output
|IOZ|
10
11
μA
kΩ
leakage current
(per pin)
Pull-up resistors
P
all digital inputs, when
RPU
17.5
—
52.5
enabled
DC injection
Single pin limit
–0.2
–5
—
—
0.2
5
mA
mA
current 3, 4, 5
12
D
IIC
VIN < VSS, VIN > VDD
Total MCU limit, includes
sum of all stressed pins
13 C Input Capacitance, all pins
14 C RAM retention voltage
15 C POR re-arm voltage6
16 D POR re-arm time
CIn
—
—
—
0.6
1.4
—
8
pF
V
VRAM
VPOR
tPOR
1.0
1.79
—
0.9
10
V
μs
Low-voltage detection threshold —
VDD falling
VDD rising
2.11
2.16
2.16
2.21
2.22
2.27
8
17
P
VLVDH
V
high range7
MC9S08QE128 Series Data Sheet, Rev. 7
Freescale Semiconductor
15
Electrical Characteristics
Table 8. DC Characteristics (continued)
Num C
Characteristic
Symbol
Condition
Min
Typ1
Max
Unit
Low-voltage detection threshold —
low range7
VDD falling
VDD rising
1.80
1.86
1.82
1.90
1.91
1.99
18
19
20
P
P
P
VLVDL
V
Low-voltage warning threshold —
high range7
VDD falling
2.36
2.36
2.46
2.46
2.56
2.56
VLVWH
VLVWL
V
V
VDD rising
Low-voltage warning threshold —
low range7
VDD falling
VDD rising
2.11
2.16
2.16
2.21
2.22
2.27
Low-voltage inhibit reset/recover
hysteresis7
21
22
C
P
Vhys
VBG
—
50
—
mV
V
Bandgap Voltage Reference9
1.15
1.17
1.18
1
2
3
4
Typical values are measured at 25°C. Characterized, not tested
As the supply voltage rises, the LVD circuit will hold the MCU in reset until the supply has risen above VLVDL
All functional non-supply pins are internally clamped to VSS and VDD
.
.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
5
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result
in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if
clock rate is very low (which would reduce overall power consumption).
6
7
8
9
Maximum is highest voltage that POR is guaranteed.
Low voltage detection and warning limits measured at 1 MHz bus frequency.
Run at 1 MHz bus frequency
Factory trimmed at VDD = 3.0 V, Temp = 25°C
PULL-UP RESISTOR TYPICALS
40
35
30
25
20
PULL-DOWN RESISTOR TYPICALS
85°C
40
35
30
25
20
85°C
25°C
25°C
–40°C
–40°C
1.8
2
2.2 2.4 2.6 2.8
3
3.2 3.4 3.6
1.8
2.3
2.8
VDD (V)
3.3
3.6
VDD (V)
Figure 7. Pull-up and Pull-down Typical Resistor Values
MC9S08QE128 Series Data Sheet, Rev. 7
16
Freescale Semiconductor
Electrical Characteristics
TYPICAL VOL VS IOL AT VDD = 3.0 V
TYPICAL VOL VS VDD
0.2
0.15
0.1
1.2
1
85°C
25°C
–40°C
0.8
0.6
0.4
0.2
0
85
25
–40
°
C, IOL = 2 mA
0.05
0
°
C, IOL = 2 mA
°
C, IOL = 2 mA
1
2
3
4
0
5
10
15
20
VDD (V)
I
OL (mA)
Figure 8. Typical Low-Side Driver (Sink) Characteristics — Low Drive (PTxDSn = 0)
TYPICAL VOL VS VDD
TYPICAL VOL VS IOL AT VDD = 3.0 V
1
0.4
0.3
0.2
0.1
85°C
85°C
25°C
–40°C
25°C
0.8
0.6
0.4
0.2
–40°C
IOL = 10 mA
IOL = 6 mA
I
OL = 3 mA
0
0
0
10
20
30
1
2
3
4
VDD (V)
IOL (mA)
Figure 9. Typical Low-Side Driver (Sink) Characteristics — High Drive (PTxDSn = 1)
TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V
TYPICAL VDD – VOH VS VDD AT SPEC IOH
1.2
1
0.25
0.2
0.15
0.1
0.05
0
85°C
85
25
–40
°
C, IOH = 2 mA
C, IOH = 2 mA
C, IOH = 2 mA
25°C
°
–40°C
°
0.8
0.6
0.4
0.2
0
0
–5
–10
IOH (mA))
–15
–20
1
2
3
4
VDD (V)
Figure 10. Typical High-Side (Source) Characteristics — Low Drive (PTxDSn = 0)
MC9S08QE128 Series Data Sheet, Rev. 7
Freescale Semiconductor
17
Electrical Characteristics
TYPICAL VDD – VOH VS VDD AT SPEC IOH
0.4
0.3
0.2
0.1
85°C
25°C
–40°C
TYPICAL V – V VS I AT V = 3.0 V
DD
OH
OH
DD
0.8
85°C
25°C
0.6
0.4
0.2
0
–40°C
IOH = –10 mA
IOH = –6 mA
I
OH = –3 mA
0
0
–5
–10
–15
–20
–25
–30
1
2
3
4
I
(mA)
OH
VDD (V)
Figure 11. Typical High-Side (Source) Characteristics — High Drive (PTxDSn = 1)
3.7
Supply Current Characteristics
This section includes information about power supply current in various operating modes.
Table 9. Supply Current Characteristics
Bus
Freq
VDD
(V)
Temp
(°C)
Num
C
Parameter
Run supply current
Symbol
Typ1
Max
Unit
P
P
T
T
T
C
T
T
T
16
16
18
20
—
–40 to 25
85
25.165 MHz
FEI mode, all modules on
1
RIDD
20 MHz
8 MHz
3
14.4
6.5
1.4
11.5
9.5
4.6
1.0
mA
—
–40 to 85
1 MHz
—
Run supply current
FEI mode, all modules off
25.165 MHz
20 MHz
8 MHz
12.3
—
2
3
RIDD
3
3
mA
–40 to 85
—
1 MHz
—
Run supply current
LPS=0, all modules off
16 kHz
FBILP
T
T
152
115
—
—
RIDD
μA
–40 to 85
16 kHz
FBELP
Run supply current
LPS=1, all modules off, running from
Flash
—
—
0 to 70
–40 to 85
0 to 70
T
T
21.9
7.3
16 kHz
FBELP
4
5
RIDD
3
3
μA
Run supply current
LPS=1, all modules off, running from
RAM
—
—
–40 to 85
C
T
T
T
Wait mode supply current
FEI mode, all modules off
25.165 MHz
20 MHz
8 MHz
5.74
4.57
2
6
—
—
—
WIDD
mA
–-40 to 85
1 MHz
0.73
MC9S08QE128 Series Data Sheet, Rev. 7
18
Freescale Semiconductor
Electrical Characteristics
Temp
Table 9. Supply Current Characteristics (continued)
Bus
VDD
(V)
Num
C
Parameter
Symbol
Typ1
Max
Unit
Freq
(°C)
P
C
P
C
C
C
P
C
P
C
C
C
Stop2 mode supply current
0.35
0.98
2.5
0.6
2.0
7.5
0.5
1.9
6.5
1.0
4.2
15.0
0.7
3.9
13.2
-40 to 25
3
2
3
2
70
85
6
S2IDD
n/a
μA
0.25
1.4
-40 to 25
70
1.91
0.45
1.99
5.0
85
Stop3 mode supply current
No clocks active
-40 to 25
70
85
7
S3IDD
n/a
μA
0.35
2.9
-40 to 25
70
3.77
85
1
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
Table 10. Stop Mode Adders
Temperature (°C)
Num
C
Parameter
Condition
Units
-40
25
70
85
1
2
3
4
5
6
7
T
T
T
T
T
T
T
LPO
50
1000
63
75
1000
70
100
1100
77
150
1500
81
nA
nA
uA
nA
uA
uA
uA
ERREFSTEN
IREFSTEN1
RTC
RANGE = HGO = 0
does not include clock source current
LVDSE = 1
50
75
100
110
22
150
115
23
LVD1
90
100
20
ACMP1
ADC1
not using the bandgap (BGBE = 0)
18
ADLPC = ADLSMP = 1 not using the
bandgap (BGBE = 0)
95
106
114
120
1
Not available in stop2 mode.
MC9S08QE128 Series Data Sheet, Rev. 7
Freescale Semiconductor
19
Electrical Characteristics
18.00
16.00
14.00
12.00
10.00
8.00
FEI: 24 MHz
FBELP: 24 MHz
FEI: 8 MHz
FBELP: 8 MHz
FEI: 1 MHz
FBELP: 1 MHz
6.00
4.00
2.00
0.00
1.8
2
2.2
2.4
2.6
2.8
3
VDD (V)
Figure 12. Typical Run I for FBE and FEI, I vs. V
DD
DD
DD
(ADC off, All Other Modules Enabled)
MC9S08QE128 Series Data Sheet, Rev. 7
20
Freescale Semiconductor
Electrical Characteristics
3.8
External Oscillator (XOSC) Characteristics
Reference Figure 13 and Figure 14 for crystal or resonator circuits.
Table 11. XOSC and ICS Specifications (Temperature Range = –40 to 85°C Ambient)
Num
C
Characteristic
Symbol
Min
Typ1
Max
Unit
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)
Low range (RANGE = 0)
flo
fhi
fhi
32
1
1
—
—
—
38.4
16
8
kHz
MHz
MHz
1
C
High range (RANGE = 1), high gain (HGO = 1)
High range (RANGE = 1), low power (HGO = 0)
Load capacitors
See Note2
See Note3
C1,C2
2
3
D
D
Low range (RANGE=0), low power (HGO=0)
Other oscillator settings
Feedback resistor
Low range, low power (RANGE=0, HGO=0)2
Low range, High Gain (RANGE=0, HGO=1)
High range (RANGE=1, HGO=X)
—
—
—
—
10
1
—
—
—
RF
MΩ
kΩ
Series resistor —
Low range, low power (RANGE = 0, HGO = 0)2
—
—
—
—
0
100
—
—
—
Low range, high gain (RANGE = 0, HGO = 1)
High range, low power (RANGE = 1, HGO = 0)
High range, high gain (RANGE = 1, HGO = 1)
RS
4
D
≥ 8 MHz
4 MHz
1 MHz
—
—
—
0
0
0
0
10
20
Crystal start-up time 4
Low range, low power
Low range, high power
High range, low power
High range, high power
t
—
—
—
—
200
400
5
—
—
—
—
CSTL
5
6
C
D
ms
t
CSTH
15
Square wave input clock frequency (EREFS = 0, ERCLKEN = 1)
fextal
FEE or FBE mode
FBELP mode
0.03125
0
—
—
40.0
50.33
MHz
MHz
1
2
3
4
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE=HGO=0.
See crystal or resonator manufacturer’s recommendation.
Proper PC board layout procedures must be followed to achieve specifications.
MC9S08QE128 Series Data Sheet, Rev. 7
Freescale Semiconductor
21
Electrical Characteristics
XOSC
EXTAL
XTAL
RS
RF
Crystal or Resonator
C1
C2
Figure 13. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain
XOSC
EXTAL
XTAL
Crystal or Resonator
Figure 14. Typical Crystal or Resonator Circuit: Low Range/Low Gain
3.9
Internal Clock Source (ICS) Characteristics
Table 12. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient)
Num
C
P
P
Characteristic
Symbol
Min
—
Typ1
32.768
—
Max
—
Unit
Average internal reference frequency — factory trimmed
fint_ft
1
kHz
at VDD = 3.6 V and temperature = 25°C
Internal reference frequency — user trimmed
Internal reference start-up time
Low range (DRS=00)
DCO output frequency range —
Mid range (DRS=01)
trimmed 2
fint_ut
tIRST
2
3
31.25
39.06
kHz
T
P
P
P
P
P
P
—
16
32
48
—
—
—
60
—
100
20
40
60
—
μs
fdco_u
4
5
—
MHz
MHz
High range (DRS=10)
—
DCO output frequency 2
Low range (DRS=00)
19.92
39.85
59.77
Reference = 32768 Hz
and
DMX32 = 1
Mid range (DRS=01)
fdco_DMX32
—
High range (DRS=10)
—
Resolution of trimmed DCO output frequency at fixed voltage and
temperature (using FTRIM)
Δfdco_res_t
Δfdco_res_t
%fdco
%fdco
6
7
C
C
—
—
± 0.1
± 0.2
± 0.2
± 0.4
Resolution of trimmed DCO output frequency at fixed voltage and
temperature (not using FTRIM)
MC9S08QE128 Series Data Sheet, Rev. 7
22
Freescale Semiconductor
Electrical Characteristics
Table 12. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient) (continued)
Num
C
Characteristic
Symbol
Min
Typ1
Max
Unit
Total deviation of trimmed DCO output frequency over voltage
and temperature
+ 0.5
-1.0
Δfdco_t
%fdco
8
C
—
± 2
Total deviation of trimmed DCO output frequency over fixed
voltage and temperature range of 0°C to 70 °C
Δfdco_t
tAcquire
CJitter
%fdco
ms
9
C
C
C
—
—
—
± 0.5
—
± 1
1
FLL acquisition time 3
10
11
Long term jitter of DCO output clock (averaged over 2-ms
interval) 4
%fdco
0.02
0.2
1
2
3
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing
from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference,
this specification assumes it is already running.
4
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a
given interval.
0.60%
0.40%
0.20%
0.00%
-40
-20
0
20
40
60
80
100
120
-0.20%
-0.40%
-0.60%
-0.80%
-1.00%
VDD
Figure 15. Deviation of DCO Output Across Temperature at V = 3.0 V
DD
MC9S08QE128 Series Data Sheet, Rev. 7
Freescale Semiconductor
23
Electrical Characteristics
0.50%
0.40%
0.30%
0.20%
0.10%
0.00%
2.1V
2.4V
2.7V
3.0V
3.3V
3.6V
-0.10%
-0.20%
-0.30%
-0.40%
-0.50%
VDD
Figure 16. Deviation of DCO Output Across V at 25°C
DD
3.10 AC Characteristics
This section describes timing characteristics for each peripheral system.
3.10.1 Control Timing
Table 13. Control Timing
Num
C
Rating
Bus frequency (tcyc = 1/fBus
Symbol
Min
Typ1
Max
Unit
)
VDD ≥ 1.8V
VDD > 2.1V
VDD > 2.4V
—
—
—
10
20
25.165
1
D
fBus
dc
MHz
2
3
4
D
D
D
Internal low power oscillator period
External reset pulse width2
Reset low drive
tLPO
textrst
trstdrv
700
100
—
—
—
1300
—
μs
ns
ns
34 x tcyc
—
BKGD/MS setup time after issuing background debug
force reset to enter user or BDM modes
5
6
D
D
tMSSU
tMSH
500
100
—
—
—
—
ns
BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes 3
μs
MC9S08QE128 Series Data Sheet, Rev. 7
24
Freescale Semiconductor
Electrical Characteristics
Table 13. Control Timing (continued)
Rating Symbol
Num
C
Min
Typ1
Max
Unit
IRQ pulse width
7
D
Asynchronous path2
Synchronous path4
tILIH, IHIL
t
100
1.5 x tcyc
—
—
—
—
ns
Keyboard interrupt pulse width
Asynchronous path2
8
D
C
tILIH, IHIL
t
100
1.5 x tcyc
—
—
—
—
ns
ns
Synchronous path4
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)5
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
—
—
8
31
—
—
9
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
ns
—
—
7
24
—
—
10
Voltage regulator recovery time
tVRR
—
4
—
μs
1
2
Typical values are based on characterization data at VDD = 3.0V, 25°C unless otherwise stated.
This is the shortest pulse that is guaranteed to be recognized as a reset or interrupt pin request. Shorter pulses are not
guaranteed to override reset requests from internal sources.
3
4
5
To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD
rises above VLVD
.
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40°C to 85°C.
textrst
RESET PIN
Figure 17. Reset Timing
tIHIL
KBIPx
IRQ/KBIPx
tILIH
Figure 18. IRQ/KBIPx Timing
MC9S08QE128 Series Data Sheet, Rev. 7
Freescale Semiconductor
25
Electrical Characteristics
3.10.2 TPM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the
optional external source to the timer counter. These synchronizers operate from the current bus rate clock.
Table 14. TPM Input Timing
No.
C
Function
Symbol
Min
Max
Unit
1
2
3
4
5
D
D
D
D
D
External clock frequency
External clock period
fTCLK
tTCLK
tclkh
0
fBus/4
—
Hz
tcyc
tcyc
tcyc
tcyc
4
External clock high time
External clock low time
Input capture pulse width
1.5
1.5
1.5
—
tclkl
—
tICPW
—
tTCLK
tclkh
TCLK
tclkl
Figure 19. Timer External Clock
tICPW
TPMCHn
TPMCHn
tICPW
Figure 20. Timer Input Capture Pulse
MC9S08QE128 Series Data Sheet, Rev. 7
26
Freescale Semiconductor
Electrical Characteristics
3.10.3 SPI Timing
Table 15 and Figure 21 through Figure 24 describe the timing requirements for the SPI system.
Table 15. SPI Timing
No.
C
Function
Operating frequency
Symbol
Min
Max
Unit
fop
—
D
Master
Slave
fBus/2048
0
fBus/2
fBus/4
Hz
Hz
SPSCK period
Master
Slave
tSPSCK
tLead
tLag
1
2
3
4
5
6
D
D
D
D
D
D
2
4
2048
—
tcyc
tcyc
Enable lead time
Master
Slave
1/2
1
—
—
tSPSCK
tcyc
Enable lag time
Master
Slave
1/2
1
—
—
tSPSCK
tcyc
Clock (SPSCK) high or low time
Master
Slave
tWSPSCK
tcyc – 30
tcyc – 30
1024 tcyc
—
ns
ns
Data setup time (inputs)
Master
Slave
tSU
15
15
—
—
ns
ns
Data hold time (inputs)
Master
Slave
tHI
0
25
—
—
ns
ns
7
8
D
D
Slave access time
ta
tdis
tv
—
—
1
1
tcyc
tcyc
Slave MISO disable time
Data valid (after SPSCK edge)
9
D
D
D
D
Master
Slave
—
—
25
25
ns
ns
Data hold time (outputs)
Master
Slave
tHO
10
11
12
0
0
—
—
ns
ns
Rise time
Input
Output
tRI
tRO
—
—
tcyc – 25
25
ns
ns
Fall time
Input
Output
tFI
tFO
—
—
tcyc – 25
25
ns
ns
MC9S08QE128 Series Data Sheet, Rev. 7
Freescale Semiconductor
27
Electrical Characteristics
SS1
(OUTPUT)
11
12
2
1
3
SPSCK
(CPOL = 0)
(OUTPUT)
4
4
SPSCK
(CPOL = 1)
(OUTPUT)
5
6
MISO
(INPUT)
MSB IN2
LSB IN
BIT 6 . . . 1
10
9
9
MOSI
(OUTPUT)
MSB OUT2
BIT 6 . . . 1
LSB OUT
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 21. SPI Master Timing (CPHA = 0)
SS(1)
(OUTPUT)
1
11
2
3
12
SPSCK
(CPOL = 0)
(OUTPUT)
4
4
11
12
SPSCK
(CPOL = 1)
(OUTPUT)
5
6
MISO
(INPUT)
MSB IN(2)
BIT 6 . . . 1
LSB IN
9
10
MOSI
(OUTPUT)
MASTER MSB OUT(2)
PORT DATA
BIT 6 . . . 1
MASTER LSB OUT
PORT DATA
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 22. SPI Master Timing (CPHA =1)
MC9S08QE128 Series Data Sheet, Rev. 7
28
Freescale Semiconductor
Electrical Characteristics
SS
(INPUT)
11
12
3
12
11
1
SPSCK
(CPOL = 0)
(INPUT)
2
4
4
SPSCK
(CPOL = 1)
(INPUT)
8
10
10
7
9
MISO
(OUTPUT)
SEE
NOTE
BIT 6 . . . 1
SLAVE LSB OUT
MSB OUT
6
SLAVE
5
MOSI
(INPUT)
BIT 6 . . . 1
MSB IN
LSB IN
NOTE:
1. Not defined but normally MSB of character just received
Figure 23. SPI Slave Timing (CPHA = 0)
SS
(INPUT)
1
3
12
11
2
11
SPSCK
(CPOL = 0)
(INPUT)
4
4
12
SPSCK
(CPOL = 1)
(INPUT)
9
10
8
MISO
(OUTPUT)
SEE
BIT 6 . . . 1
SLAVE LSB OUT
LSB IN
SLAVE MSB OUT
NOTE
5
6
7
MOSI
(INPUT)
MSB IN
BIT 6 . . . 1
NOTE:
1. Not defined but normally LSB of character just received
Figure 24. SPI Slave Timing (CPHA = 1)
MC9S08QE128 Series Data Sheet, Rev. 7
Freescale Semiconductor
29
Electrical Characteristics
3.11 Analog Comparator (ACMP) Electricals
Table 16. Analog Comparator Electrical Specifications
C
D
C
Characteristic
Symbol
VDD
Min
1.80
Typical
—
Max
3.6
35
Unit
V
Supply voltage
Supply current (active)
IDDAC
—
20
μA
D
C
C
Analog input voltage
VAIN
VAIO
VH
VSS – 0.3
—
20
VDD
40
V
Analog input offset voltage
Analog comparator hysteresis
mV
mV
3.0
9.0
15.0
P
C
Analog input leakage current
IALKG
tAINIT
—
—
—
—
1.0
1.0
μA
μs
Analog comparator initialization delay
3.12 ADC Characteristics
Table 17. 12-bit ADC Operating Conditions
C
Characteristic
Conditions
Symb
Min
Typ1
Max
Unit
Comment
Supply voltage Absolute
VDDAD
ΔVDDAD
ΔVSSAD
VREFH
VREFL
1.8
-100
-100
1.8
—
0
3.6
V
mV
mV
V
D
2
Delta to VDD (VDD-VDDAD
)
+100
+100
VDDAD
VSSAD
VREFH
5.5
2
D
D
D
D
Ground voltage
Ref Voltage High
Ref Voltage Low
Input Voltage
Delta to VSS (VSS-VSSAD
)
0
VDDAD
VSSAD
—
VSSAD
VREFL
—
V
VADIN
V
Input
Capacitance
CADIN
4.5
C
C
pF
Input Resistance
RADIN
RAS
—
5
7
kΩ
Analog Source 12 bit mode
Resistance fADCK > 4MHz
fADCK < 4MHz
External to MCU
—
—
—
—
2
5
C
D
10 bit mode
ADCK > 4MHz
kΩ
f
—
—
—
—
5
10
fADCK < 4MHz
8 bit mode (all valid fADCK
)
—
—
—
—
10
8.0
4.0
ADCConversion High Speed (ADLPC=0)
fADCK
0.4
0.4
MHz
Clock Freq.
Low Power (ADLPC=1)
1
2
Typical values assume VDDAD = 3.0V, Temp = 25°C, fADCK=1.0MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
DC potential difference.
MC9S08QE128 Series Data Sheet, Rev. 7
30
Freescale Semiconductor
Electrical Characteristics
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
Z
ADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
Z
AS
leakage
due to
input
ADC SAR
ENGINE
R
R
AS
ADIN
protection
+
V
ADIN
–
C
AS
V
+
AS
–
R
R
R
ADIN
ADIN
ADIN
INPUT PIN
INPUT PIN
INPUT PIN
C
ADIN
Figure 25. ADC Input Impedance Equivalency Diagram
Table 18. 12-bit ADC Characteristics (V
= V
, V
= V
)
REFH
DDAD
REFL
Max
—
SSAD
Characteristic
Conditions
C
Symb
Min
Typ1
Unit
Comment
Supply Current
ADLPC=1
ADLSMP=1
ADCO=1
T
IDDAD
—
—
—
—
120
202
μA
μA
μA
mA
Supply Current
ADLPC=1
ADLSMP=0
ADCO=1
T
T
D
IDDAD
IDDAD
IDDAD
—
—
1
Supply Current
ADLPC=0
ADLSMP=1
ADCO=1
288
Supply Current
ADLPC=0
ADLSMP=0
ADCO=1
0.532
Supply Current Stop, Reset, Module Off
P
P
P
IDDAD
—
2
0.007
3.3
2
0.8
5
μA
ADC
High Speed (ADLPC=0)
Low Power (ADLPC=1)
fADACK
tADACK = 1/fADACK
Asynchronous
Clock Source
MHz
1.25
3.3
MC9S08QE128 Series Data Sheet, Rev. 7
Freescale Semiconductor
31
Electrical Characteristics
Table 18. 12-bit ADC Characteristics (V
= V
Min
, V
= V
) (continued)
SSAD
REFH
DDAD
REFL
Characteristic
Conditions
C
Symb
Typ1
Max
Unit
Comment
Conversion Time Short Sample (ADLSMP=0)
P
C
tADC
—
—
20
40
—
—
ADCK
cycles
See the ADC
chapter in the
MC9S08QE128
Reference Manual
for conversion time
variances
(Including
Long Sample (ADLSMP=1)
sample time)
Sample Time
Short Sample (ADLSMP=0)
Long Sample (ADLSMP=1)
P
C
T
P
T
T
P
T
T
T
T
T
P
T
T
P
T
D
tADS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3.5
23.5
±3.0
±1
—
—
ADCK
cycles
Total Unadjusted 12 bit mode
ETUE
—
LSB2
LSB2
LSB2
LSB2
LSB2
LSB2
Includes
Quantization
Error
10 bit mode
±2.5
±1.0
—
8 bit mode
±0.5
Differential
Non-Linearity
12 bit mode
10 bit mode3
8 bit mode3
12 bit mode
10 bit mode
8 bit mode
DNL
INL
EZS
EFS
EQ
±1.75
±0.5
±0.3
±1.5
±0.5
±0.3
±1.5
±0.5
±0.5
±1.0
±0.5
±0.5
-1 to 0
—
±1.0
±0.5
—
Integral
Non-Linearity
±1.0
±0.5
—
Zero-Scale Error 12 bit mode
10 bit mode
VADIN = VSSAD
±1.5
±0.5
—
8 bit mode
Full-Scale Error 12 bit mode
10 bit mode
VADIN = VDDAD
±1
8 bit mode
±0.5
—
Quantization
Error
12 bit mode
10 bit mode
8 bit mode
12 bit mode
10 bit mode
8 bit mode
-40°C to 25°C
25°C to 85°C
25°C
±0.5
±0.5
—
—
Input Leakage
Error
D
EIL
±2
LSB2 Pad leakage4 * RAS
±0.2
±0.1
1.646
1.769
701.2
±4
±1.2
—
Temp Sensor
Slope
D
D
m
mV/°C
—
Temp Sensor
Voltage
VTEMP25
—
mV
1
Typical values assume VDDAD = 3.0V, Temp = 25°C, fADCK=1.0MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
1 LSB = (VREFH - VREFL)/2N
2
3
4
Monotonicity and No-Missing-Codes guaranteed in 10 bit and 8 bit modes
Based on input pad leakage current. Refer to pad electricals.
MC9S08QE128 Series Data Sheet, Rev. 7
32
Freescale Semiconductor
Electrical Characteristics
3.13 Flash Specifications
This section provides details about program/erase times and program-erase endurance for the flash memory.
Program and erase operations do not require any special power sources other than the normal V supply. For more detailed
DD
information about program/erase operations, see the Memory section of the MC9S08QE128 Reference Manual.
Table 19. Flash Characteristics
C
Characteristic
Symbol
Min
Typical
Max
Unit
Supply voltage for program/erase
-40°C to 85°C
D
Vprog/erase
VRead
fFCLK
1.8
1.8
150
5
3.6
3.6
V
D
D
D
P
P
P
P
Supply voltage for read operation
Internal FCLK frequency1
Internal FCLK period (1/FCLK)
Byte program time (random location)(2)
Byte program time (burst mode)(2)
Page erase time2
V
200
6.67
kHz
μs
tFcyc
tprog
9
tFcyc
tFcyc
tFcyc
tFcyc
mA
mA
tBurst
4
4000
20,000
4
tPage
Mass erase time(2)
tMass
Byte program current3
RIDDBP
RIDDPE
—
—
—
—
Page erase current3
6
Program/erase endurance4
TL to TH = –40°C to + 85°C
T = 25°C
C
C
10,000
—
—
100,000
—
—
cycles
years
Data retention5
tD_ret
15
100
—
1
2
The frequency of this clock is controlled by a software setting.
These values are hardware state machine controlled. User code does not need to count cycles. This information supplied
for calculating approximate time to program and erase.
3
4
The program and erase currents are additional to the standard run IDD. These values are measured at room temperatures
with VDD = 3.0 V, bus frequency = 4.0 MHz.
Typical endurance for flash was evaluated for this product family on the HC9S12Dx64. For additional information on
how Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile
Memory.
5
Typical data retention values are based on intrinsic capability of the technology measured at high temperature and
de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale defines typical data retention,
please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.
MC9S08QE128 Series Data Sheet, Rev. 7
Freescale Semiconductor
33
Ordering Information
4
Ordering Information
This section contains ordering information for MC9S08QE128, MC9S08QE96, and MC9S08QE64 devices.
Table 20. Ordering Information
Memory
Freescale Part Number1
Temperature range (°C)
Package2
Flash
RAM
MC9S08QE128CLK
MC9S08QE128CLH
MC9S08QE128CFT
MC9S08QE128CLD
MC9S08QE96CLK
MC9S08QE96CLH
MC9S08QE96CFT
MC9S08QE96CLD
MC9S08QE64CLH
MC9S08QE64CFT
MC9S08QE64CLD
MC9S08QE64CLC
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
80 LQFP
64 LQFP
48 QFN
44 LQFP
80 LQFP
64 LQFP
48 QFN
44 QFP
64 LQFP
48 QFN
44 QFP
32 LQFP
128K
8K
96K
64K
6K
4K
1
2
See the reference manual, MC9S08QE128RM, for a complete description of modules included on each device.
See Table 21 for package information.
4.1
Device Numbering System
Example of the device numbering system:
128 C
9
XX
MC S08 QE
Status
(MC = Fully Qualified)
Package designator (see Table 21)
Temperature range
(C = –40°C to 85°C)
Memory
(9 = Flash-based)
Core
Approximate flash size in Kbytes
Family
5
Package Information
The below table details the various packages available.
Table 21. Package Descriptions
Pin Count
Package Type
Abbreviation
Designator
Case No.
Document No.
80
64
48
44
32
Low Quad Flat Package
Low Quad Flat Package
Quad Flat No-Leads
LQFP
LQFP
QFN
LK
LH
FT
LD
LC
917A
840F
1314
824D
873A
98ASS23237W
98ASS23234W
98ARH99048A
98ASS23225W
98ASH70029A
Low Quad Flat Package
Low Quad Flat Package
LQFP
LQFP
MC9S08QE128 Series Data Sheet, Rev. 7
34
Freescale Semiconductor
Package Information
5.1
Mechanical Drawings
The following pages are mechanical drawings for the packages described in Table 21. For the latest available drawings please
visit our web site (http://www.freescale.com) and enter the package’s document number into the keyword search box.
MC9S08QE128 Series Data Sheet, Rev. 7
Freescale Semiconductor
35
Package Information
–X–
X= L, M, N
4X
4X 20 TIPS
0.20 (0.008)
0.20 (0.008)
H
L–M
N
T
L–M
N
P
80
61
C
L
1
60
AB
AB
G
–M–
B1
VIEW Y
B
V
PLATING
F
–L–
3X VIEW Y
BASE
METAL
J
V1
41
20
D
U
21
40
–N–
M
S
S
0.13 (0.005)
T
L–M
N
A1
S1
SECTION AB–AB
ROTATED 90 CLOCKWISE
A
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –L–, –M– AND –N– TO BE DETERMINED
AT DATUM PLANE –H–.
C
8X
2
0.10 (0.004)
T
–H–
–T–
SEATING
PLANE
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –T–.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –H–.
VIEW AA
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE LEAD WIDTH TO EXCEED 0.460
(0.018). MINIMUM SPACE BETWEEN
PROTRUSION AND ADJACENT LEAD OR
PROTRUSION 0.07 (0.003).
(W)
C2
S
0.05 (0.002)
MILLIMETERS
MIN MAX
14.00 BSC
7.00 BSC
14.00 BSC
7.00 BSC
INCHES
MIN MAX
0.551 BSC
0.276 BSC
0.551 BSC
0.276 BSC
1
DIM
A
A1
B
B1
C
C1
C2
D
E
F
G
J
K
P
R1
S
S1
U
0.25 (0.010)
2X R R1
GAGE
PLANE
–––
0.04
1.30
0.22
0.40
0.17
1.60
–––
0.002
0.051
0.009
0.016
0.007
0.063
0.24
1.50
0.38
0.75
0.33
0.009
0.059
0.015
0.030
0.013
(K)
C1
E
(Z)
0.65 BSC
0.026 BSC
VIEW AA
0.09
0.27
0.004
0.011
0.50 REF
0.325 BSC
0.020 REF
0.013 REF
0.004 0.008
0.630 BSC
0.315 BSC
0.10
0.20
16.00 BSC
8.00 BSC
0.09
0.16
0.004
0.006
V
16.00 BSC
0.630 BSC
0.315 BSC
0.008 REF
0.039 REF
V1
W
Z
8.00 BSC
0.20 REF
1.00 REF
DATE 09/21/95
CASE 917A-02
ISSUE C
0
01
02
0
0
9
10
–––
14
0
0
9
10
–––
14
Figure 26. 80-pin LQFP Package Drawing (Case 917A, Doc #98ASS23237W)
MC9S08QE128 Series Data Sheet, Rev. 7
36
Freescale Semiconductor
Package Information
Figure 27. 64-pin LQFP Package Drawing (Case 840F, Doc #98ASS23234W), Sheet 1 of 3
MC9S08QE128 Series Data Sheet, Rev. 7
Freescale Semiconductor
37
Package Information
Figure 28. 64-pin LQFP Package Drawing (Case 840F, Doc #98ASS23234W), Sheet 2 of 3
MC9S08QE128 Series Data Sheet, Rev. 7
38
Freescale Semiconductor
Package Information
Figure 29. 64-pin LQFP Package Drawing (Case 840F, Doc #98ASS23234W), Sheet 3 of 3
MC9S08QE128 Series Data Sheet, Rev. 7
Freescale Semiconductor
39
Package Information
Figure 30. 48-pin QFN Package Drawing (Case 1314, Doc #98ARH99048A), Sheet 1 of 3
MC9S08QE128 Series Data Sheet, Rev. 7
40
Freescale Semiconductor
Package Information
Figure 31. 48-pin QFN Package Drawing (Case 1314, Doc #98ARH99048A), Sheet 2 of 3
MC9S08QE128 Series Data Sheet, Rev. 7
Freescale Semiconductor
41
Package Information
Figure 32. 48-pin QFN Package Drawing (Case 1314, Doc #98ARH99048A), Sheet 3 of 3
MC9S08QE128 Series Data Sheet, Rev. 7
42
Freescale Semiconductor
Package Information
Figure 33. 44-pin LQFP Package Drawing (Case 824D, Doc #98ASS23225W), Sheet 1 of 3
MC9S08QE128 Series Data Sheet, Rev. 7
Freescale Semiconductor
43
Package Information
Figure 34. 44-pin LQFP Package Drawing (Case 824D, Doc #98ASS23225W), Sheet 2 of 3
MC9S08QE128 Series Data Sheet, Rev. 7
44
Freescale Semiconductor
Package Information
Figure 35. 44-pin LQFP Package Drawing (Case 824D, Doc #98ASS23225W), Sheet 3 of 3
MC9S08QE128 Series Data Sheet, Rev. 7
Freescale Semiconductor
45
Package Information
Figure 36. 32-pin LQFP Package Drawing (Case 873A, Doc #98ASH70029A), Sheet 1 of 3
MC9S08QE128 Series Data Sheet, Rev. 7
46
Freescale Semiconductor
Package Information
Figure 37. 32-pin LQFP Package Drawing (Case 873A, Doc #98ASH70029A), Sheet 2 of 3
MC9S08QE128 Series Data Sheet, Rev. 7
Freescale Semiconductor
47
Package Information
Figure 38. 32-pin LQFP Package Drawing (Case 873A, Doc #98ASH70029A), Sheet 3 of 3
MC9S08QE128 Series Data Sheet, Rev. 7
48
Freescale Semiconductor
Product Documentation
6
Product Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual (MC9S08QE128RM)
Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module
information.
7
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web are the most current. Your
printed copy may be an earlier revision. To verify you have the latest information available, refer to:
http://www.freescale.com
The following revision history table summarizes changes contained in this document.
Table 22. Revision History
Revision
Date
Description of Changes
Replaced 44 QFP package with 44 LQFP package.
4
9 Nov 2007
Changed ACMP electricals, VAIO specification’s test category from P to C.
Updated the tables Thermal Characteristics, DC Characteristics, Supply Current
Characteristics, XOSC and ICS Specifications (Temperature Range = –40 to 85°C
Ambient), ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient),
Control Timing, and Analog Comparator Electrical Specifications, 12-bit ADC
Characteristics (VREFH = VDDAD, VREFL = VSSAD)
5
28 May 2008
Updated the figures Typical Run IDD for FBE and FEI, IDD vs. VDD (ACMP and ADC off,
All Other Modules Enabled), Deviation of DCO Output from Trimmed Frequency (50.33
MHz, 3.0 V), and Deviation of DCO Output from Trimmed Frequency (50.33 MHz, 25°C)
Updated the table Thermal Characteristics
Updated the row corresponding to Num 18 in the table DC Characteristics
Updated the tables MC9S08QE128 Series Features by MCU and Package, DC
Characteristics, Supply Current Characteristics, Thermal Characteristics, Control
Timing, and Ordering Information
Updated the figures Typical Run IDD for FBE and FEI, IDD vs. VDD
(ADC off, All Other Modules Enabled), Deviation of DCO Output Across Temperature at
VDD = 3.0 V, and Deviation of DCO Output Across VDD at 25×C
6
7
24 Jun 2008
2 Oct 2008
Updated the Stop2 and Stop3 mode supply current in the Supply Current Characteristics table.
Replaced the stop mode adders section from the Supply Current Characteristics with its own
Stop Mode Adders table with new specifications.
MC9S08QE128 Series Data Sheet, Rev. 7
Freescale Semiconductor
49
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Document Number: MC9S08QE128
Rev. 7
10/2008
相关型号：
MC9S08QE64CLH
8-BIT, FLASH, 50.33MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, MS-026BCD, LQFP-64
NXP
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