MCF51CN128CLH [FREESCALE]
MCF51CN128 ColdFire Microcontroller; MCF51CN128的ColdFire微控制器
| 型号： | MCF51CN128CLH |
| 厂家： | 
Freescale |
| 描述： | MCF51CN128 ColdFire Microcontroller |
| 文件： | 总48页 (文件大小：2707K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MCF51CN128
Rev. 4, 5/2009
MCF51CN128
80 LQFP
14 mm × 14 mm
64 LQFP
10 mm × 10 mm
MCF51CN128 ColdFire
Microcontroller
Cover: MCF51CN128
48 QFN
7 mm × 7 mm
The MCF51CN128 device is a low-cost, low-power,
high-performance 32-bit ColdFire V1 microcontroller (MCU)
featuring 10/100 BASE-T/TX fast ethernet controller (FEC),
media independent interface (MII) to connect an external
physical transceiver (PHY), and multi-function external bus
interface.
– MII—media independent interface to connect ethernet
controller to external PHY; includes output clock for
external PHY
• External Bus
– Mini-FlexBus—Multi-function external bus interface;
supports up to 1 MB memories, gate-array logic, simple
slave device or glueless interfaces to standard
chip-selected asynchronous memories
MCF51CN128 also has multiple communication interfaces
for various ethernet gateway applications. MCF51CN128 is
the first ColdFire V1 device to incorporate ethernet and
external bus interface along with new features to minimize
power consumption and increase functionality in low-power
modes.
– Programmable options: access time per chip select, burst
and burst-inhibited transfers per chip select, transfer
direction, and address setup and hold times
• Power-Saving Modes
– Two low-power stop modes, one of which allows limited
use of some peripherals (ADC, KBI, RTC)
– Reduced-power wait mode shuts off CPU and allows
full use of all peripherals; FEC can remain active and
conduct DMA transfers to RAM and assert an interrupt
to wake up the CPU upon completion
The MCF51CN128 features the following functional units:
• 32-bit ColdFire V1 Central Processing Unit (CPU)
– Up to 50.33 MHz ColdFire CPU from 3.6 V to 3.0 V, up
to 40 MHz CPU from 3.0 V to 2.1 V, and up to 20 MHz
CPU from 2.1 V to 1.8 V across temperature range of
–40 °C to 85 °C
– Low-power run and wait modes allow peripherals to run
while the voltage regulator is in standby
– Provides 0.94 Dhrystone 2.1 MIPS per MHz
performance when running from internal RAM
(0.76 DMIPS/MHz from flash)
– ColdFire Instruction Set Revision C (ISA_C)
– Support for up to 45 peripheral interrupt requests and 7
software interrupts
– Peripheral clock enable register can disable clocks to
unused modules, thereby reducing currents
– Low-power external oscillator that can be used in stop3
mode to provide accurate clock source to active
peripherals
• On-Chip Memory
– Low-power real-time counter for use in run, wait, and
stop modes with internal and external clock sources
– 6 μs typical wake-up time from stop3 mode
– Pins and clocks to peripherals not available in smaller
packages are automatically disabled for reduced current
consumption; no user interaction is needed
• Clock Source Options
– 128 KB Flash, 24 KB RAM
– Flash read/program/erase over full operating voltage
and temperature
– On-chip memory aliased to create a contiguous memory
space with off-chip memory
– Security circuitry to prevent unauthorized access to
Peripherals, RAM, and flash contents
– Oscillator (XOSC) — Loop-control pierce oscillator;
crystal or ceramic resonator range of 31.25 kHz to
38.4 kHz or 1 MHz to 25 MHz
– Multi-Purpose Clock Generator (MCG) — Flexible
clock source module with either frequency-locked-loop
(FLL) or phase-lock loop (PLL) clock options. FLL can
be controlled by internal or external reference and
• Ethernet
– FEC—10/100 BASE-T/TX, bus-mastering fast ethernet
controller with direct memory access (DMA); supports
half or full duplex; operation is limited to 3.0 V to 3.6 V
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale Semiconductor, Inc., 2009. All rights reserved.
includes precision trimming of internal reference, allowing 0.2% resolution and 2% deviation over temperature and
voltage. PLL derives a higher accuracy clock source derived by an external reference
• System Protection
– Watchdog computer operating properly (COP) reset with option to run from dedicated 1-kHz internal clock source or bus
clock
– Low-voltage detection with reset or interrupt; selectable trip points
– Illegal opcode and illegal address detection with programmable reset or exception response
– Flash block protection
• Development Support
– Single-wire background debug module (BDM) interface; supports same electrical interface used by the S08, 9S12, and
9S12x families debug modules
– 4 PC plus 2 address (optional data) breakpoint registers with programmable 1- or 2-level trigger response
– 64-entry processor status and debug data trace buffer with programmable start/stop conditions
• Peripherals
– ADC—Up to 12 channel, 12-bit resolution; 2.5 μs conversion time; automatic compare function; 1.7 mV/°C temperature
sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6 V to 1.8 V
– SCI—Three modules with optional 13-bit break
– SPI—Two interfaces with full-duplex or single-wire bi-directional; double-buffered transmit and receive; master or slave
mode; MSB-first or LSB-first shifting
– IIC—Two IICs with up to 100 kbps with maxmimum bus loading; multi-master operation; programmable slave address;
interrupt-driven byte-by-byte data transfer; supports broadcast mode and 11-bit addressing
– TPM—Two 3-channel, 16-bit resolution modules; selectable input capture, output compare, or buffered edge- or
center-aligned PWM on each channel
– RTC—8-bit modulus counter with binary- or decimal-based prescaler; external clock source for precise time base,
time-of-day, calendar- or task-scheduling functions; free-running on-chip low-power oscillator (1 kHz) for cyclic wake-up
without external components; runs in all MCU modes
– MTIM—Two 8-bit resolution modulo timers with 8-bit prescaler
• Input/Output
– Up to 70 general-purpose input/output (GPIO) pins, all with pin mux controls to select alternate functions
– 16 keyboard interrupt (KBI) pins with selectable polarity
– Hysteresis and configurable pull-up device or input filtering on all input pins; configurable slew rate and drive strength on
all output pins
– 16 Rapid GPIO pins connected to the CPU’s high-speed local bus with set, clear, and toggle functionality (PTD and PTF)
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
2
Freescale Semiconductor
Table of Contents
MCF51CN128 Series Comparison. . . . . . . . . . . . . . . . . . . . . .4
1
Table 13..Receive Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 14..Transmit Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 15..MII Transmit Signal Timing . . . . . . . . . . . . . . . . . . . . . 25
Table 16..MII Serial Management Channel Signal Timing . . . . . 26
Table 17..Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 18..TPM Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 19..SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 20..12-bit ADC Operating Conditions . . . . . . . . . . . . . . . . 32
Table 21..12-bit ADC Characteristics (VREFH = VDDAD, VREFL
1.1 Device Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .12
3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .12
3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .13
3.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . .14
3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .18
3.8 External Oscillator (XOSC) Characteristics . . . . . . . . .20
3.9 Multipurpose Clock Generator (MCG) Specifications . .21
3.10 Mini-FlexBus Timing Specifications . . . . . . . . . . . . . . .23
3.11 Fast Ethernet Timing Specifications . . . . . . . . . . . . . . .24
3.11.1 Receive Signal Timing Specifications . . . . . . . .24
3.11.2 Transmit Signal Timing Specifications . . . . . . . .25
3.11.3 Asynchronous Input Signal Timing Specifications25
3.11.4 MII Serial Management Timing Specifications .26
3.12 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
3.12.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . .26
3.12.2 TPM Module Timing . . . . . . . . . . . . . . . . . . . . .28
3.12.3 SPI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.12.4 ADC Characteristics . . . . . . . . . . . . . . . . . . . . .32
3.12.5 Flash Specifications. . . . . . . . . . . . . . . . . . . . . .35
3.13 EMC Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
3.13.1 Radiated Emissions. . . . . . . . . . . . . . . . . . . . . .36
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Mechanical Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . .36
6.1 80-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
6.2 64-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
6.3 48-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
2
3
=
V
SSAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 22..Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 23..Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 24..Package Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 25..Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
List of Figures
Figure 1..MCF51CN128 Series Block Diagram . . . . . . . . . . . . . . 5
Figure 2..Pin Assignments in 80-Pin LQFP Package. . . . . . . . . . 6
Figure 3..Pin Assignments in 64-Pin LQFP Package. . . . . . . . . . 7
Figure 4..Pin Assignments in 48-Pin QFN Package. . . . . . . . . . . 8
Figure 5..Pull-up and Pull-down Typical Resistor Values . . . . . . 16
Figure 6..Typical Low-Side Driver (Sink) Characteristics — Low Drive
(PTxDSn = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7..Typical Low-Side Driver (Sink) Characteristics — High
Drive (PTxDSn = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8..Typical High-Side (Source) Characteristics — Low Drive
(PTxDSn = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9..Typical High-Side (Source) Characteristics — High Drive
(PTxDSn = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4
5
6
Figure 10..Typical Run IDD for FBE and FEI, IDD vs. VDD
(ADC off, All Other Modules Enabled). . . . . . . . . . . . . 19
Figure 11..Typical Crystal or Resonator Circuit: High Range and Low
Range/High Gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12..Typical Crystal or Resonator Circuit: Low Range/Low
Gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7
Figure 13..Mini-FlexBus Read Timing . . . . . . . . . . . . . . . . . . . . 23
Figure 14..Mini-FlexBus Write Timing . . . . . . . . . . . . . . . . . . . . 24
Figure 15..MII Receive Signal Timing Diagram . . . . . . . . . . . . . 25
Figure 16..MII Transmit Signal Timing Diagram . . . . . . . . . . . . . 25
Figure 17..MII Async Inputs Timing Diagram. . . . . . . . . . . . . . . 25
Figure 18..MII Serial Management Channel TIming Diagram . . 26
Figure 19..Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 20..IRQ/KBIPx Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 21..Timer External Clock. . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 22..Timer Input Capture Pulse . . . . . . . . . . . . . . . . . . . . 28
Figure 23..SPI Master Timing (CPHA = 0). . . . . . . . . . . . . . . . . 30
Figure 24..SPI Master Timing (CPHA =1) . . . . . . . . . . . . . . . . . 30
Figure 25..SPI Slave Timing (CPHA = 0). . . . . . . . . . . . . . . . . . 31
Figure 26..SPI Slave Timing (CPHA = 1). . . . . . . . . . . . . . . . . . 31
Figure 27..ADC Input Impedance Equivalency Diagram . . . . . . 33
List of Tables
Table 1.. MCF51CN128 Series Device Comparison . . . . . . . . . . .4
Table 2.. Package Pin Assignments . . . . . . . . . . . . . . . . . . . . . . .8
Table 3.. Parameter Classifications . . . . . . . . . . . . . . . . . . . . . . .12
Table 4.. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .12
Table 5.. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .13
Table 6.. ESD and Latch-up Test Conditions. . . . . . . . . . . . . . . .14
Table 7.. ESD and Latch-Up Protection Characteristics . . . . . . .14
Table 8.. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 9.. Supply Current Characteristics . . . . . . . . . . . . . . . . . . .18
Table 10..XOSC and ICS Specifications (Temperature Range = –40
to 85 °C Ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 11..MCG Frequency Specifications (Temperature Range = –40
to 125 °C Ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 12..Mini-FlexBus AC Timing Specifications . . . . . . . . . . . .23
MCF51CN128 ColdFire Microcontroller Advance Information Data Sheet, Rev. 4
Freescale Semiconductor
3
MCF51CN128 Series Comparison
1
MCF51CN128 Series Comparison
1.1
Device Comparison
The following table compares the various device derivatives available within the MCF51CN128 series.
Table 1. MCF51CN128 Series Device Comparison
MCF51CN128
Feature
80-pin
64-pin
48-pin
Flash memory size (KB)
RAM size (KB)
128
24
V1 ColdFire core equiped with BDM (background debug
module) and 2X3 Crossbar switch
Yes
ADC (analog-to-digital converter) channels (12-bit)
FEC (Fast Ethernet Controller with MII Interface)
COP (computer operating properly)
IIC1 (inter-integrated circuit)
IIC2
12
Yes
Yes
Yes
Yes
Yes
12
IRQ (interrupt request input)
KBI (keyboard interrupts)
16
6
LVD (low-voltage detector)
MCG (multipurpose clock generator)
Port I/O1
Yes
Yes
54
70
16
38
8
RGPIO (rapid general-purpose I/O)
RTC (real-time counter)
16
Yes
Yes
Yes
3
SCI1, SCI2 & SCI3 (serial communications interface)
SPI1 & SPI2 (serial peripheral interface)
TPM1 (Timer/PWM Module) channels
TPM2 channels
3
3
3
3
3
MTIM1 & MTIM2
Yes2
1
External Timer Clocks
2
1
0
Mini-FlexBus
Yes
0
XOSC (crystal oscillator)
Yes
1
All GPIO are muxed with other functions
2
TMRCLK2 is not available on the 48 pin package, although MTIM2 can be used as an
internal timebase using on-chip clock sources.
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
4
Freescale Semiconductor
MCF51CN128 Series Comparison
1.2
Block Diagram
The following figure shows the connections between the MCF51CN128 series pins and modules.
PTA7/MII_RX_DV/MOSI2
PTA6/MII_RXD0/MISO2
PTA5/MII_RXD1/SPSCK2
PTA4/MII_RXD2/RXD3
PTA3/MII_RXD3/TXD3
PTA2/MII_MDC/SCL2
PTA1/MII_MDIO/SDA2
PTA0/PHYCLK
PTB7/MII_TXD2/TPM2CH1
PTB6/MII_TXD1/TPM2CH0
PTB5/MII_TXD0/SPSCK1
PTB4/MII_TX_EN/MISO1
PTB3/MII_TX_CLK/MOSI1
PTB2/MII_TX_ER/SS1
VDDA/
VDDA
VREFH
VSSA
Port C:
ADP3-
ADP0
Port D:
ADP8-
ADP4
Port E:
ADP11-
ADP9
Port C/G:
SDA1
VREFH
IIC1
IIC2
VSSA/
VREFL
SCL1
VREFL
ADC
Port C/G:
SDA2
DBG
INTC
SCL2
BDM
Port D:
Port E:
KBI2P7
KBI2P6
KBI2P5
KBI2P4
KBI2P3
KBI2P2
BKGD/MS
BKGD/MS/PTD6/RGPIO6
Port E:
TPM1CH2
TPM1CH1
TPM1CH0
TPM1
PTB1/MII_RX_ER/TMRCLK1
PTB0/MII_RX_CLK/SS2
KBI2P1
KBI2P0
ColdFire V1 core
Port B, F or H* : TPM1CLK
PTC7/SDA2/SPSCK1/ADP8
PTC6/SCL2/MISO1/ADP9
PTC5/MOSI1/ADP10
PTC4/IRQ/SS1/ADP11
PTC2/MII_CRS/SDA1
Port G/I:
KBI1P7
KBI1P6
KBI1P5
KBI1P4
KBI1P3
KBI1P2
KBI1P1
KBI1P0
KBI
Port F/H:
TPM2CH2
TPM2CH1
TPM2CH0
RESET/PTC3
TPM2
PTC1/MII_COL/SCL1
PTC0/MII_TXD3/TPM2CH2
Port B, F or H* : TPM2CLK
SIM
PTD7/RGPIO7/SPSCK2/ADP3
BKGD/MS/PTD6/RGPIO6
PTD5/RGPIO5/XTAL
Port F:
RGPIO15
RGPIO14
RGPIO13
RGPIO12
RGPIO11
RGPIO10
RGPIO9
PTD4/RGPIO4/EXTAL
LVD
COP
PTD3/RGPIO3/RXD2/ADP4
PTD2/RGPIO2/TXD2/ADP5
PTD1/RGPIO1/RXD1/ADP6
PTD0/RGPIO0/TXD1/ADP7
Port D:
EXTAL
XTAL
Port A:
CLKOUT
MCG
XOSC
RTC
FLASH
128 KB
PTE7/KBI2P7/FB_CS0/RXD3
PTE6/KBI2P6/FB_D0/TXD3
PTE5/KBI2P5/IRQ/TPM1CH2
PTE4/KBI2P4/CLKOUT/TPM1CH1
PTE3/KBI2P3/TPM1CH0
PTE2/KBI2P2/SS2/ADP0
PTE1/KBI2P1/MOSI2/ADP1
PTE0/KBI2P0/MISO2/ADP2
PTF7/RGPIO15/FB_A13/FB_AD13/TPM2CH2
PTF6/RGPIO14/FB_A14/FB_AD14/TPM2CH1
PTF5/RGPIO13/FB_D4/TPM2CH0
PTF4/RGPIO12/FB_D5/TMRCLK2
PTF3/RGPIO11/FB_A16/FB_AD16
PTF2/RGPIO10/FB_A17/FB_AD17
PTF1/RGPIO9/FB_A18/FB_AD18
RGPIO8
RAM
24 KB
RGPIO
Port D:
RGPIO7
RGPIO6
RGPIO5
RGPIO4
RGPIO3
RGPIO2
RGPIO1
RGPIO0
Port A:
Port B, F or H* :
MII_TX_CLK
MII_RX_CLK
MII_TX_EN
MII_TXD0
MTIM1
MTIM2
MTIM1CLK
Port B, F or H* :
MII_TXD1
MTIM2CLK
MII_TXD2
MII_TXD3
Port B:
MII_TX_ER
MII_RX_DV
MII_RXD0
MII_RXD1
MII_RXD2
MII_RXD3
MII_RX_ER
MII_CRS
Port C:
MII_COL
MII_MDC
MII_MDIO
MII
PTF0/RGPIO8/FB_A19/FB_AD19
Port D:
RXD1
TXD1
Port F:
FB_D7-FB_D0
SCI1
PTG7/KBI1P7/FB_D1
PTG6/KBI1P6/FB_D2
PTG5/KBI1P5/FB_D3
PTG4/KBI1P4/FB_RW
PTG3/KBI1P3/FB_A5/FB_AD5/SDA1
PTG2/KBI1P2/FB_A6/FB_AD6/SCL1
PTG1/KBI1P1/FB_A7/FB_AD7/SDA2
PTG0/KBI1P0/FB_A8/FB_AD8/SCL2
Port H:
FB_A19-FB_A16
FB_A11-FB_A8
Port D:
RXD2
TXD2
SCI2
Port G:
FB_CS1
FB_CS0
OE
FB_RW
Port E:
RXD3
TXD3
Mini-FlexBus
PTH7/FB_A9/FB_AD9/TPM2CH2
PTH6/FB_A10/FB_AD10/TPM2CH1
PTH5/FB_A11/FB_AD11
PTH4/FB_A12/FB_AD12
PTH3/FB_D6/TPM2CH0
PTH2/FB_D7/TMRCLK1
PTH1/FB_OE
SCI3
FB_A5-FB_A2
FEC
Port I:
FB_A15-FB_A12
FB_A7-FB_A6
Port E:
FB_A1-FB_A0
Port C:
SS1
SPSCK1
MOSI1
MISO1
SPI1
VDD1
VSS1
VDD2
VSS2
VDD3
VSS3
VDD4
VSS4
PTH0/FB_A15/FB_AD15
PTJ5/FB_A0/FB_AD0
PTJ4/FB_A1/FB_AD1
PTJ3/FB_A2/FB_AD2
PTJ2/FB_A3/FB_AD3
PTJ1/FB_A4/FB_AD4
PTJ0/FB_ALE/FB_CS1
VREG
Port D/E:
SS2
SPSCK2
MOSI2
MISO2
Port C:
IRQ
SPI2
External Interrupt
* TPMx and MTIMx external clocks each have the choice of being assigned to either TMRCLK1 or TMRCLK2.
Figure 1. MCF51CN128 Series Block Diagram
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
5
Pin Assignments
2
Pin Assignments
This section describes the pin assignments for the available packages. See for pin availability by package pin-count.
VDD1
VSS1
PTA0/PHYCLK
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PTG7/KBI1P7/FB_D1
PTG6/KBI1P6/FB_D2
PTG5/KBI1P5/FB_D3
PTG4/KBI1P4/FB_RW
PTG3/KBI1P3/FB_A5/FB_AD5/SDA1
PTG2/KBI1P2/FB_A6/FB_AD6/SCL1
PTG1/KBI1P1/FB_A7/FB_AD7/SDA2
PTG0/KBI1P0/FB_A8/FB_AD8/SCL2
PTD3/RGPIO3/RXD2/ADP4
PTD2/RGPIO2/TXD2/ADP5
PTD1/RGPIO1/RXD1/ADP6
PTD0/RGPIO0/TXD1/ADP7
PTC7/SDA2/SPSCK1/ADP8
PTC6/SCL2/MISO1/ADP9
PTC5/MOSI1/ADP10
2
3
4
PTA1/MII_MDIO/SDA2
PTA2/MII_MDC/SCL2
5
6
PTA3/MII_RXD3/TXD3
PTA4/MII_RXD2/RXD3
PTA5/MII_RXD1/SPSCK2
PTA6/MII_RXD0/MISO2
PTA7/MII_RX_DV/MOSI2
PTB0/MII_RX_CLK/SS2
PTB1/MII_RX_ER/TMRCLK1
PTF0/RGPIO8/FB_A19/FB_AD19
PTF1/RGPIO9/FB_A18/FB_AD18
PTF2/RGPIO10/FB_A17/FB_AD17
PTF3/RGPIO11/FB_A16/FB_AD16
PTH0/FB_A15/FB_AD15
PTH1/FB_OE
7
8
9
80-Pin LQFP
10
11
12
13
14
15
16
17
18
19
20
PTC4/IRQ/SS1/ADP11
VSSA
VDDA
VSS3
PTH2/FB_D7/TMRCLK1
PTH3/FB_D6/TPM2CH0
VDD3
Figure 2. Pin Assignments in 80-Pin LQFP Package
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
6
Freescale Semiconductor
Pin Assignments
VDD1
VSS1
PTA0/PHYCLK
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PTG3/KBI1P3/FB_A5/FB_AD5/SDA1
PTG2/KBI1P2/FB_A6/FB_AD6/SCL1
PTG1/KBI1P1/FB_A7/FB_AD7/SDA2
PTG0/KBI1P0/FB_A8/FB_AD8/SCL2
PTD3/RGPIO3/RXD2/ADP4
PTD2/RGPIO2/TXD2/ADP5
PTD1/RGPIO1/RXD1/ADP6
PTD0/RGPIO0/TXD1/ADP7
PTC7/SDA2/SPSCK1/ADP8
PTC6/SCL2/MISO1/ADP9
PTC5/MOSI1/ADP10
PTC4/IRQ/SS1/ADP11
VSSA
PTA1/MII_MDIO/SDA2
PTA2/MII_MDC/SCL2
PTA3/MII_RXD3/TXD3
PTA4/MII_RXD2/RXD3
PTA5/MII_RXD1/SPSCK2
PTA6/MII_RXD0/MISO2
PTA7/MII_RX_DV/MOSI2
PTB0/MII_RX_CLK/SS2
PTB1/MII_RX_ER/TMRCLK1
PTF0/RGPIO8/FB_A19/FB_AD19
PTF1/RGPIO9/FB_A18/FB_AD18
PTF2/RGPIO10/FB_A17/FB_AD17
PTF3/RGPIO11/FB_A16/FB_AD16
64-Pin LQFP
9
10
11
12
13
14
15
16
VDDA
VSS3
VDD3
Figure 3. Pin Assignments in 64-Pin LQFP Package
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
7
Pin Assignments
PTD3/RGPIO3/RXD2/ADP4
PTD2/RGPIO2/TXD2/ADP5
PTD1/RGPIO1/RXD1/ADP6
PTD0/RGPIO0/TXD1/ADP7
PTC7/SDA2/SPSCK1/ADP8
PTC6/SCL2/MISO1/ADP9
PTC5/MOSI1/ADP10
PTC4/IRQ/SS1/ADP11
VSSA
36
35
34
33
32
31
30
29
28
27
26
25
VDD1
VSS1
1
2
PTA0/PHYCLK
3
PTA1/MII_MDIO/SDA2
PTA2/MII_MDC/SCL2
4
5
PTA3/MII_RXD3/TXD3
6
48-Pin QFN
PTA4/MII_RXD2/RXD3
PTA5/MII_RXD1/SPSCK2
PTA6/MII_RXD0/MISO2
PTA7/MII_RX_DV/MOSI2
PTB0/MII_RX_CLK/SS2
PTB1/MII_RX_ER/TMRCLK1
7
8
9
10
11
12
VDDA
VSS3
VDD3
Figure 4. Pin Assignments in 48-Pin QFN Package
NOTE
There is no electrical connection to the flag for 48-pin QFN packages.
Table 2. Package Pin Assignments
80-Pin 64-Pin 48-Pin Default Function
Alt 1
Alt 2
Alt 3
Comment
1
2
3
1
2
3
1
2
3
VDD1
VSS1
PTA0
—
—
—
—
—
—
—
—
—
—
—
PHYCLK
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
8
Freescale Semiconductor
Pin Assignments
Comment
Table 2. Package Pin Assignments (continued)
80-Pin 64-Pin 48-Pin Default Function
Alt 1
Alt 2
Alt 3
4
4
4
PTA1
PTA2
MII_MDIO
MII_MDC
MII_RXD3
MII_RXD2
MII_RXD1
MII_RXD0
MII_RX_DV
MII_RX_CLK
MII_RX_ER
—
—
SDA2
—
—
—
—
—
—
—
—
—
5
5
5
—
SCL2
6
6
6
PTA3
TXD3
—
7
7
7
PTA4
RXD3
—
8
8
8
PTA5
SPSCK2
—
9
9
9
PTA6
MISO2
—
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
10
11
12
13
14
15
16
—
—
—
—
17
18
19
20
21
22
23
24
25
26
27
10
11
12
—
—
—
—
—
—
—
—
13
14
15
16
17
18
19
20
21
22
23
PTA7
MOSI2
—
PTB0
SS2
—
PTB1
—
TMRCLK1
PTF0/RGPIO8
PTF1/RGPIO9
PTF2/RGPIO10
PTF3/RGPIO11
PTH0
FB_A19/FB_AD19
—
RGPIO_ENB selects
between standard GPIO
and RGPIO
—
FB_A18/FB_AD18
—
—
FB_A17/FB_AD17
—
—
FB_A16/FB_AD16
—
—
FB_A15/FB_AD15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PTH1
—
FB_OE
FB_D7
FB_D6
—
PTH2
—
TMRCLK1
TPM2CH0
—
PTH3
—
VDD2
—
VSS2
—
—
—
PTB2
MII_TX_ER
MII_TX_CLK
MII_TX_EN
MII_TXD0
MII_TXD1
MII_TXD2
MII_TXD3
MII_COL
MII_CRS
SS1
MOSI1
MISO1
SPSCK1
—
—
PTB3
—
PTB4
—
PTB5
—
PTB6
TPM2CH0
TPM2CH1
TPM2CH2
SCL1
SDA1
PTB7
—
PTC0
—
PTC1
—
PTC2
—
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
9
Pin Assignments
Table 2. Package Pin Assignments (continued)
80-Pin 64-Pin 48-Pin Default Function
Alt 1
Alt 2
Alt 3
Comment
32
28
24
RESET
PTC3
—
—
This pin is a
bi-directional open drain
pin and has an internal
pullup. There is no
clamp diode to VDD.
DSE and SRE port
controls for this bit have
no effect.
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
29
30
31
32
—
—
—
—
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
—
—
—
—
—
—
—
—
—
—
—
25
26
27
28
29
30
31
32
33
34
35
36
—
—
—
—
—
—
—
PTF4/RGPIO12
PTF5/RGPIO13
PTF6/RGPIO14
PTF7/RGPIO15
PTH4
—
—
FB_D5
FB_D4
TMRCLK2
TPM2CH0
TPM2CH1
TPM2CH2
—
RGPIO_ENB selects
between standard GPIO
and RGPIO
—
FB_A14/FB_AD14
FB_A13/FB_AD13
FB_A12/FB_AD12
FB_A11/FB_AD11
FB_A10/FB_AD10
FB_A9/FB_AD9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PTH5
—
—
PTH6
—
TPM2CH1
TPM2CH2
—
PTH7
—
VDD3
—
VSS3
—
—
—
VDDA
—
—
—
VSSA
—
—
—
PTC4
IRQ
—
SS1
ADP11
ADP10
ADP9
ADP8
ADP7
ADP6
ADP5
ADP4
SCL2
SDA2
SCL1
SDA1
—
PTC5
MOSI1
PTC6
SCL2
SDA2
—
MISO1
PTC7
SPSCK1
PTD0/RGPIO0
PTD1/RGPIO1
PTD2/RGPIO2
PTD3/RGPIO3
PTG0
TXD1
RGPIO_ENB selects
between standard GPIO
and RGPIO
—
RXD1
—
TXD2
—
RXD2
KBI1P0
KBI1P1
KBI1P2
KBI1P3
KBI1P4
KBI1P5
KBI1P6
FB_A8/FB_AD8
FB_A7/FB_AD7
FB_A6/FB_AD6
FB_A5/FB_AD5
FB_RW
—
—
—
—
—
—
—
PTG1
PTG2
PTG3
PTG4
PTG5
FB_D3
—
PTG6
FB_D2
—
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
10
Freescale Semiconductor
Electrical Characteristics
Comment
Table 2. Package Pin Assignments (continued)
80-Pin 64-Pin 48-Pin Default Function
Alt 1
Alt 2
Alt 3
60
61
62
63
64
—
49
50
51
52
—
37
38
39
40
PTG7
VDD4
KBI1P7
—
FB_D1
—
—
—
—
—
—
VSS4
—
—
—
PTD4/RGPIO4
PTD5/RGPIO5
—
—
EXTAL
XTAL
RGPIO_ENB selects
between standard GPIO
and RGPIO
—
—
65
53
41
BKGD/MS
PTD6/RGPIO6
—
—
This pin has an internal
pullup. PTD6/RGPIO6
can only be
programmed as an
output.1
66
54
42
PTD7RGPIO7
—
SPSCK2
ADP3
RGPIO_ENB selects
between standard GPIO
and RGPIO
67
68
69
70
71
72
73
74
75
76
77
78
79
80
55
56
57
58
59
60
61
62
63
64
—
—
—
—
43
44
45
46
47
48
—
—
—
—
—
—
—
—
PTE0
PTE1
PTE2
PTE3
PTE4
PTE5
PTE6
PTE7
PTJ0
PTJ1
PTJ2
PTJ3
PTJ4
PTJ5
KBI2P0
KBI2P1
KBI2P2
KBI2P3
KBI2P4
KBI2P5
KBI2P6
KBI2P7
FB_ALE
—
MISO2
MOSI2
ADP2
ADP1
ADP0
TPM1CH0
TPM1CH1
TPM1CH2
TXD3
RXD3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SS2
—
CLKOUT
IRQ
FB_D0
FB_CS0
FB_CS1
FB_A4/FB_AD4
FB_A3/FB_AD3
FB_A2/FB_AD2
FB_A1/FB_AD1
FB_A0/FB_AD0
—
—
—
—
—
—
—
—
—
1
RGPIO_ENB selects between standard GPIO and RGPIO. When PTD6 is set as RGPIO output, and "1" is driven to PTD6 via
RGPIO function, a read of register RGPIODATA6 always returns a "0" because V1 RGPIO design looks for IO enable when the
return value of RGPIO function reads data. As PTD6 is set to RGPIO output only, it returns "0" always to RGPIODATA6, athough
PTD6 pin is driven to high.
3
Electrical Characteristics
3.1
Introduction
This section contains electrical and timing specifications for the MCF51CN128 series of microcontrollers available at the time
of publication.
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
11
Electrical Characteristics
3.2
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:
Table 3. Parameter Classifications
These parameters are guaranteed during production testing on each individual device.
P
C
These parameters are achieved by the design characterization by measuring a statistically relevant sample
size across process variations.
These parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
T
These parameters are derived mainly from simulations.
D
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
3.3
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the
limits specified in Table 4 may affect device reliability or cause permanent damage to the device. For functional operating
conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised
that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for
instance, either V or V ) or the programmable pull-up resistor associated with the pin is enabled.
SS
DD
Table 4. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Supply voltage
VDD
IDD
VIn
ID
–0.3 to +3.8
120
V
mA
V
Maximum current into VDD
Digital input voltage
–0.3 to VDD + 0.3
± 25
Instantaneous maximum current
mA
Single pin limit (applies to all port pins)1, 2, 3
Storage temperature range
Tstg
–55 to 150
°C
1
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2
3
All functional non-supply pins are internally clamped to VSS and VDD
.
Power supply must maintain regulation within operating VDD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
I
DD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
12
Freescale Semiconductor
Electrical Characteristics
3.4
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power
dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and
it is user-determined rather than being controlled by the MCU design. To take P into account in power calculations, determine
I/O
the difference between actual pin voltage and V or V and multiply by the pin current for each I/O pin. Except in cases of
SS
DD
unusually high pin current (heavy loads), the difference between pin voltage and V or V will be very small.
SS
DD
Table 5. Thermal Characteristics
Symbol
Rating
Value
Unit
Operating temperature range
(packaged)
TL to TH
TA
°C
°C
(–40 to 85 or 0 to 70)1
95
Maximum junction temperature
TJM
Thermal resistance
Single-layer board
48-pin QFN
64-pin LQFP
80-pin LQFP
81
69
60
θJA
°C/W
°C/W
Thermal resistance
Four-layer board
48-pin QFN
64-pin LQFP
26
50
47
θJA
80-pin LQFP
1
Depending on device.
The average chip-junction temperature (T ) in °C can be obtained from:
J
T = T + (P × θ )
JA
Eqn. 1
J
A
D
where:
T = Ambient temperature, °C
A
θ
= Package thermal resistance, junction-to-ambient, °C/W
JA
P = P + P
D
int
I/O
P
P
= I × V , Watts — chip internal power
= Power dissipation on input and output pins — user determined
int
I/O
DD DD
For most applications, P << P and can be neglected. An approximate relationship between P and T (if P is neglected)
I/O
int
D
J
I/O
is:
P = K ÷ (T + 273°C)
Eqn. 2
D
J
Solving Equation 1 and Equation 2 for K gives:
K = P × (T + 273°C) + θ × (P )
2
Eqn. 3
D
A
JA
D
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring P (at equilibrium)
D
for a known T . Using this value of K, the values of P and T can be obtained by solving Equation 1 and Equation 2 iteratively
A
D
J
for any value of T .
A
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
13
Electrical Characteristics
3.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure
that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During
the device qualification ESD stresses were performed for the human body model (HBM), the machine model (MM) and the
charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
Table 6. ESD and Latch-up Test Conditions
Model
Description
Series resistance
Symbol
Value
Unit
R1
C
1500
100
3
Ω
Human
Body
Storage capacitance
Number of pulses per pin
Series resistance
pF
—
R1
C
0
Ω
Machine Storage capacitance
Number of pulses per pin
200
3
pF
—
—
—
Minimum input voltage limit
Latch-up
– 2.5
7.5
V
V
Maximum input voltage limit
Table 7. ESD and Latch-Up Protection Characteristics
No.
Rating1
Symbol
Min
Max
Unit
1
2
3
4
Human body model (HBM)
Machine model (MM)
VHBM
VMM
VCDM
ILAT
± 2000
± 200
± 500
± 100
—
—
—
—
V
V
Charge device model (CDM)
Latch-up current at TA = 85°C
V
mA
1
Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
14
Freescale Semiconductor
Electrical Characteristics
3.6
DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics.
Table 8. DC Characteristics
Num
C
Characteristic
Symbol
Condition
Min
Typ1
Max
Unit
1
— Operating Voltage2
—
—
1.83
—
3.6
V
Output high
voltage
All I/O pins,
low-drive strength
C
1.8 V, ILoad = –2 mA VDD – 0.5
—
—
P
T
All I/O pins,
high-drive strength
2.7 V, ILoad = –10 mA VDD – 0.5
2.3 V, ILoad = –6 mA VDD – 0.5
1.8V, ILoad = –3 mA VDD – 0.5
—
—
—
—
—
—
2
3
4
VOH
IOHT
VOL
V
mA
V
C
Output high
current
Max total IOH for all
ports
D
—
—
—
—
—
100
0.5
Output low
voltage
All I/O pins,
low-drive strength
C
1.8 V, ILoad = 2 mA
P
T
All I/O pins,
high-drive strength
2.7 V, ILoad = 10 mA
2.3 V, ILoad = 6 mA
1.8 V, ILoad = 3 mA
—
—
—
—
—
—
0.5
0.5
0.5
C
Output low
current
Max total IOL for all
ports
5
6
D
IOLT
—
—
—
100
mA
V
P
C
P
C
Input high
voltage
all digital inputs
VDD > 2.7 V
VDD > 1.8 V
VDD > 2.7 V
VDD >1.8 V
—
0.70 x VDD
0.85 x VDD
—
—
—
—
—
—
—
—
VIH
Input low voltage
all digital inputs
0.35 x VDD
0.30 x VDD
—
7
VIL
—
8
9
C Input hysteresis
all digital inputs Vhys
0.06 x VDD
mV
Input leakage
current
all input only pins
|IIn|
P
VIn = VDD or VSS
VIn = VDD or VSS
—
—
—
0.1
0.1
1
1
μA
(Per pin)
Hi-Z (off-state)
P
all input/output
|IOZ|
10
11
μA
leakage current
(per pin)
Pull resistors
P
all digital inputs, when
RP
17.5
–0.2
–5
—
—
—
52.5
0.2
5
kΩ
mA
mA
enabled
DC injection
Single pin limit
current 4, 5, 6
12
D
IIC
VIN < VSS, VIN > VDD
Total MCU limit, includes
sum of all stressed pins
13 C Input Capacitance, all pins
14 C POR re-arm voltage7
15 D POR re-arm time
CIn
—
0.9
10
—
1.4
—
8
pF
V
VPOR
tPOR
1.79
—
μs
Low-voltage detection threshold —
VDD falling
VDD rising
2.15
2.24
2.32
2.39
2.45
2.49
9
16
P
VLVDH
V
high range8
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
15
Electrical Characteristics
Table 8. DC Characteristics (continued)
Num
C
Characteristic
Symbol
Condition
Min
Typ1
Max
Unit
Low-voltage detection threshold —
low range8
VDD falling
VDD rising
1.70
1.80
1.83
1.89
1.95
2.00
17
P
VLVDL
V
Low-voltage warning threshold —
high range8
VDD falling
2.50
2.50
2.62
2.62
2.70
2.70
18
P
VLVWH
V
V
DD rising
Low-voltage warning threshold —
low range8
VDD falling
VDD rising
2.25
2.29
2.32
2.39
2.45
2.49
19
20
P
P
VLVWL
VBG
V
V
Bandgap Voltage Reference10
—
1.15
1.17
1.18
1
2
3
4
5
Typical values are measured at 25 °C. Characterized, not tested
As an exception, the Fast Ethernet Controller (FEC) is only operational above the operating voltage of 3 V.
As the supply voltage rises, the LVD circuit will hold the MCU in reset until the supply has risen above VLVDL
.
All functional non-supply pins are internally clamped to VSS and VDD
.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
6
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result
in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if
clock rate is very low (which would reduce overall power consumption).
7
8
9
Maximum is highest voltage that POR is guaranteed.
Low voltage detection and warning limits measured at 1 MHz bus frequency.
Run at 1 MHz bus frequency
10 Factory trimmed at VDD = 3.3 V, Temp = 25 °C
PULL-UP RESISTOR TYPICALS
40
PULL-DOWN RESISTOR TYPICALS
85°C
40
35
30
25
20
85°C
25°C
25°C
–40°C
–40°C
35
30
25
20
1.8
2
2.2 2.4 2.6 2.8
DD (V)
3
3.2 3.4 3.6
1.8
2.3
2.8
VDD (V)
3.3
3.6
V
Figure 5. Pull-up and Pull-down Typical Resistor Values
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
16
Freescale Semiconductor
Electrical Characteristics
TYPICAL VOL VS IOL AT VDD = 3.3 V
TYPICAL VOL VS VDD
0.2
0.15
0.1
1.2
1
85°C
25°C
–40°C
0.8
0.6
0.4
0.2
0
85
25
–40
°
C, IOL = 2 mA
0.05
0
°
C, IOL = 2 mA
°
C, IOL = 2 mA
1
2
3
4
0
5
10
15
20
VDD (V)
I
OL (mA)
Figure 6. Typical Low-Side Driver (Sink) Characteristics — Low Drive (PTxDSn = 0)
TYPICAL VOL VS VDD
TYPICAL VOL VS IOL AT VDD = 3.3 V
1
0.4
0.3
0.2
0.1
85°C
85°C
25°C
–40°C
25°C
0.8
0.6
0.4
0.2
–40°C
I
OL = 10 mA
IOL = 6 mA
I
OL = 3 mA
0
0
0
10
20
30
1
2
3
4
VDD (V)
I
OL (mA)
Figure 7. Typical Low-Side Driver (Sink) Characteristics — High Drive (PTxDSn = 1)
TYPICAL VDD – VOH VS IOH AT VDD = 3.3 V
TYPICAL VDD – VOH VS VDD AT SPEC IOH
1.2
1
0.25
0.2
0.15
0.1
0.05
0
85°C
85
25
–40
°
C, IOH = 2 mA
C, IOH = 2 mA
C, IOH = 2 mA
25°C
°
–40°C
°
0.8
0.6
0.4
0.2
0
0
–5
–10
OH (mA))
–15
–20
1
2
3
4
VDD (V)
I
Figure 8. Typical High-Side (Source) Characteristics — Low Drive (PTxDSn = 0)
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
17
Electrical Characteristics
TYPICAL VDD – VOH VS VDD AT SPEC IOH
0.4
0.3
0.2
0.1
85°C
25°C
–40°C
TYPICAL V – V VS I AT V = 3.3 V
DD
OH
OH
DD
0.8
85°C
25°C
0.6
0.4
0.2
0
–40°C
IOH = –10 mA
I
OH = –6 mA
IOH = –3 mA
0
0
–5
–10
–15
–20
–25
–30
1
2
3
4
I
(mA)
OH
VDD (V)
Figure 9. Typical High-Side (Source) Characteristics — High Drive (PTxDSn = 1)
3.7
Supply Current Characteristics
This section includes information about power supply current in various operating modes.
Table 9. Supply Current Characteristics
Bus
Freq
VDD
(V)
Temp
(°C)
Num
C
Parameter
Run supply current
Symbol
Typ1
Max
Unit
P
T
T
T
C
T
T
T
25 MHz
20 MHz
8 MHz
1 MHz
25 MHz
20 MHz
8 MHz
1 MHz
60
49
75
—
—
—
47
—
—
—
FEI mode, all modules on
1
RIDD
3.3
3.3
mA
–40 to 85 °C
–40 to 85 °C
21
4.6
44
Run supply current
FEI mode, all modules off
36
2
RIDD
mA
15.5
3.9
Run supply current
LPRS=0, all modules off
16 kHz
FBILP
T
T
203
154
—
—
3
4
RIDD
3.3
3.3
μA
μA
–40 to 85 °C
–40 to 85 °C
16 kHz
FBELP
Run supply current
LPRS=1, all modules off, running from
Flash
16 kHz
FBELP
T
RIDD
50
—
C
T
Wait mode supply current
FEI mode, all modules off
25 MHz
20 MHz
8 MHz
1 MHz
11
4.57
2
13.7
—
5
6
WIDD
3.3
μA –-40 to 85 °C
0 to 70 °C
T
—
T
0.73
—
C
P
C
C
Stop2 mode supply current
11
3.3
1.8
0.35
0.35
45
–40 to 85 °C
μA
S2IDD
n/a
12
0 to 70 °C
16.2
–40 to 85 °C
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
18
Freescale Semiconductor
Electrical Characteristics
Temp
Table 9. Supply Current Characteristics (continued)
Bus
Freq
VDD
(V)
Num
C
Parameter
Symbol
Typ1
0.52
0.52
Max
Unit
(°C)
C
P
C
C
T
T
T
T
T
Stop3 mode supply current
No clocks active
14
55
15
32.4
—
0 to 70 °C
–40 to 85 °C
0 to 70 °C
3.3
1.8
7
S3IDD
n/a
μA
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
8
EREFSTEN=1
32 kHz
32 kHz
100 Hz
300 bps
1 kHz
500
70
nA
μA
μA
μA
nA
9
IREFSTEN=1
TPM PWM
—
10
11
12
12
—
Low power
mode adders:
SCI, SPI, or IIC
RTC using LPO
15
—
—
3.3
200
—
RTC using
ICSERCLK
13
14
T
T
32 kHz
n/a
1
—
—
μA
μA
–40 to 85 °C
–40 to 85 °C
LVD
100
1
Data in Typical column was characterized at 3.3 V, 25 °C or is typical recommended value.
Figure 10. Typical Run I for FBE and FEI, I vs. V
DD
DD
DD
(ADC off, All Other Modules Enabled)
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
19
Electrical Characteristics
3.8
External Oscillator (XOSC) Characteristics
Reference Figure 11 and Figure 12 for crystal or resonator circuits.
Table 10. XOSC and ICS Specifications (Temperature Range = –40 to 85 °C Ambient)
Num
C
Characteristic
Symbol
Min
Typ1
Max
Unit
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)
Low range (RANGE = 0)
flo
fhi
fhi
32
1
1
—
—
—
38.4
25
8
kHz
MHz
MHz
1
C
High range (RANGE = 1), high gain (HGO = 1)
High range (RANGE = 1), low power (HGO = 0)
Load capacitors
See Note2
See Note3
C1,C2
2
3
D
D
Low range (RANGE=0), low power (HGO=0)
Other oscillator settings
Feedback resistor
Low range, low power (RANGE=0, HGO=0)2
Low range, High Gain (RANGE=0, HGO=1)
High range (RANGE=1, HGO=X)
—
—
—
—
10
1
—
—
—
RF
MΩ
Series resistor —
Low range, low power (RANGE = 0, HGO = 0)2
Low range, high gain (RANGE = 0, HGO = 1)
High range, low power (RANGE = 1, HGO = 0)
High range, high gain (RANGE = 1, HGO = 1)
—
—
—
—
0
100
—
—
—
Ω
RS
4
D
≥ 8 MHz
4 MHz
1 MHz
—
—
—
0
0
0
0
10
20
ΚΩ
Crystal start-up time 4
Low range, low power
Low range, high power
High range, low power
High range, high power
t
—
—
—
—
200
400
5
—
—
—
—
CSTL
5
C
D
ms
t
CSTH
15
Square wave input clock frequency (EREFS = 0, ERCLKEN = 1)
External with FLL / PLL enabled (FEE / PEE)
fextal
6
0.03125
0
—
—
50.33
50.33
MHz
MHz
External with bypass (FBE.FBELP,PBE, PBELP)
1
2
3
4
Data in Typical column was characterized at 3.3 V, 25 °C or is typical recommended value.
Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE=HGO=0.
See crystal or resonator manufacturer’s recommendation.
Proper PC board layout procedures must be followed to achieve specifications.
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
20
Freescale Semiconductor
Electrical Characteristics
XOSC
EXTAL
XTAL
RS
RF
Crystal or Resonator
C1
C2
Figure 11. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain
XOSC
EXTAL
XTAL
Crystal or Resonator
Figure 12. Typical Crystal or Resonator Circuit: Low Range/Low Gain
3.9
Multipurpose Clock Generator (MCG) Specifications
Table 11. MCG Frequency Specifications (Temperature Range = –40 to 125 °C Ambient)
Num
C
Rating
Symbol
Min
Typical
Max
Unit
Internal reference frequency - factory
trimmed at VDD = and
fint_ft
1
P
—
32.768
—
kHz
temperature = 25 °C
Average internal reference frequency -
untrimmed 1
fint_ut
2
P
P
25
—
41.66
kHz
Average internal reference frequency -
user trimmed
fint_t
3
4
31.25
—
—
39.06
100
kHz
us
tirefst
D Internal reference startup time
60
DCO output frequency range -
untrimmed 1
value provided for reference:
fdco_ut
5
—
25.6
33.48
42.66
MHz
fdco_ut = 1024 X fint_ut
fdco_t
6
7
P DCO output frequency range - trimmed
32
—
—
40
MHz
Resolution of trimmed DCO output
C frequency at fixed voltage and
temperature (using FTRIM)
Δfdco_res_t
%fdco
± 0.1
± 0.2
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
21
Electrical Characteristics
Table 11. MCG Frequency Specifications (continued)(Temperature Range = –40 to 125 °C Ambient)
Num
C
Rating
Symbol
Min
Typical
Max
Unit
Resolution of trimmed DCO output
C frequency at fixed voltage and
temperature (not using FTRIM)
Δfdco_res_t
%fdco
8
—
± 0.2
± 0.4
Total deviation of trimmed DCO output
P frequency over voltage and
temperature
+ 0.5
-1.0
Δfdco_t
%fdco
9
—
—
± 2
± 1
Total deviation of trimmed DCO output
Δfdco_t
%fdco
frequency over fixed voltage and
10
C
± 0.5
temperature range of 0 - 70 °C
FLL acquisition time 2
PLL acquisition time 3
tfll_acquire
tpll_acquire
11
12
C
D
—
—
—
—
1
1
ms
ms
Long term Jitter of DCO output clock
(averaged over 2ms interval) 4
CJitter
%fdco
13
C
—
0.02
0.2
fvco
Dlock
Dunl
14 D VCO operating frequency
7.0
—
—
—
55.0
± 2.98
MHz
%
Lock entry frequency tolerance5
Lock exit frequency tolerance6
15
16
D
D
± 1.49
± 4.47
± 5.97
%
tfll_acquire+
tfll_lock
tpll_lock
floc_low
17 D Lock time - FLL
18 D Lock time - PLL
—
—
—
—
s
s
1075(1/fint_t
)
tpll_acquire+
1075(1/fpll_r
ef)
—
Loss of external clock minimum
19 D frequency - RANGE = 0
(3/5) x fint
—
kHz
1
2
TRIM register at default value (0x80) and FTRIM control bit at default value (0x0).
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing
from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference,
this specification assumes it is already running.
3
4
This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is
already running.
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a
given interval.
5
6
Below Dlock minimum, the MCG is guaranteed to enter lock. Above Dlock maximum, the MCG does not enter lock. But if the
MCG is already in lock, then the MCG may stay in lock.
Below Dunl minimum, the MCG does not exit lock if already in lock. Above Dunl maximum, the MCG is guaranteed to exit lock.
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
22
Freescale Semiconductor
Electrical Characteristics
3.10 Mini-FlexBus Timing Specifications
A multi-function external bus interface called Mini-FlexBus is provided with basic functionality to interface to slave-only
devices up to a maximum bus frequency of 25.1666 MHz. It can be directly connected to asynchronous or synchronous devices
such as external boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional
circuitry. For asynchronous devices a simple chip-select based interface can be used.
All processor bus timings are synchronous; that is, input setup/hold and output delay are given in respect to the rising edge of
a reference clock, MB_CLK. The MB_CLK frequency is half the internal system bus frequency.
The following timing numbers indicate when data is latched or driven onto the external bus, relative to the Mini-FlexBus output
clock (MB_CLK). All other timing relationships can be derived from these values.
Table 12. Mini-FlexBus AC Timing Specifications
Num
C
Characteristic
Frequency of Operation
Min
Max
Unit
Notes
—
—
D
P
—
39.73
—
25.1666
MHz
ns
—
MB1
MB2
MB3
MB4
MB5
Clock Period
Output Valid
Output Hold
Input Setup
Input Hold
—
20
—
—
—
—
1
ns
1
2
2
D
P
1.0
22
ns
ns
D
10
ns
1
2
Specification is valid for all MB_A[19:0], MB_D[7:0], MB_CS[1:0], MB_OE, MB_R/W, and MB_ALE.
Specification is valid for all MB_D[7:0].
S0
S1
S2
S3
S0
FB_CLK
MB1
MB3
ADDR[19:0]
FB_A[19:16]
MB2
ADDR[31:24]
MB5
8-bit Non-Mux’d Bus
16-bit Mux’d Bus
DATA[7:0]
FB_D[7:0]
MB4
ADDR[19:16]
FB_AD[19:16]
FB_AD[15:0]
ADDR[15:0]
DATA[15:0]
FB_R/W
FB_ALE
FB_CSn, FB_OE
Figure 13. Mini-FlexBus Read Timing
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
23
Electrical Characteristics
S0
S1
S2
S3
S0
FB_CLK
MB1
MB3
ADDR[19:8]
FB_AD[19:8]
MB2
8-bit Non-Mux’d Bus
ADDR[7:0]
FB_AD[7:0]
DATA[7:0]
ADDR[19:16]
FB_AD[19:16]
16-bit Mux’d Bus
ADDR[15:0]
DATA[15:0]
FB_AD[15:0]
FB_R/W
FB_ALE
FB_CSn
FB_OE
Figure 14. Mini-FlexBus Write Timing
3.11 Fast Ethernet Timing Specifications
The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing
specs/constraints for the physical interface.
3.11.1 Receive Signal Timing Specifications
The following timing specs meet the requirements for MII and 7-Wire style interfaces for a range of transceiver devices.
Table 13. Receive Signal Timing
MII Mode
Num
C
Characteristic
Unit
Min
Max
—
E1
E2
E3
E4
—
P
RXCLK frequency
—
5
25
—
MHz
ns
RXD[3:0], RXDV, RXER to RXCLK setup
RXCLK to RXD[3:0], RXDV, RXER hold
RXCLK pulse width high
D
D
D
5
—
ns
35%
35%
65%
65%
RXCLK period
RXCLK period
RXCLK pulse width low
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
24
Freescale Semiconductor
Electrical Characteristics
E4
E1
E3
E2
RXCLK (Input)
RXD[n:0]
RXDV,
Valid Data
RXER
Figure 15. MII Receive Signal Timing Diagram
3.11.2 Transmit Signal Timing Specifications
Table 14. Transmit Signal Timing
MII Mode
Min Max
Num
C
Characteristic
Unit
—
E5
E6
E7
E8
—
D
P
TXCLK frequency
—
5
25
—
MHz
ns
TXCLK to TXD[3:0], TXEN, TXER invalid
TXCLK to TXD[3:0], TXEN, TXER valid
TXCLK pulse width high
—
25
ns
D
D
35%
35%
65%
65%
tTXCLK
tTXCLK
TXCLK pulse width low
E8
TXCLK (Input)
E7
E5
E6
TXD[n:0]
TXEN,
TXER
Valid Data
Figure 16. MII Transmit Signal Timing Diagram
3.11.3 Asynchronous Input Signal Timing Specifications
Table 15. MII Transmit Signal Timing
Num
C
Characteristic
CRS, COL minimum pulse width
Min
Max
Unit
E9
D
1.5
—
TXCLK period
CRS, COL
E9
Figure 17. MII Async Inputs Timing Diagram
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
25
Electrical Characteristics
3.11.4 MII Serial Management Timing Specifications
Table 16. MII Serial Management Channel Signal Timing
Num
C
Characteristic
Symbol
Min
Max
Unit
E10
E11
E12
E13
E14
E15
D
D
D
D
D
D
MDC cycle time
MDC pulse width
tMDC
—
400
40
—
30
5
—
60
375
—
ns
% tMDC
ns
MDC to MDIO output valid
MDC to MDIO output invalid
MDIO input to MDC setup
MDIO input to MDC hold
—
—
ns
—
—
ns
—
15
—
ns
E10
E11
MDC (Output)
MDIO (Output)
MDIO (Input)
E11
E12
E13
Valid Data
E14
E15
Valid Data
Figure 18. MII Serial Management Channel TIming Diagram
3.12 AC Characteristics
This section describes timing characteristics for each peripheral system.
3.12.1 Control Timing
Table 17. Control Timing
Num
C
Rating
Bus frequency (tcyc = 1/fBus
Symbol
Min
Typ1
Max
Unit
)
VDD > 2.7 V
2.7 V > VDD > 2.1 V
2.1 V > VDD > 1.8 V
dc
dc
dc
—
—
—
50.33
40
20
1
D
fBus
MHz
2
3
4
D
D
D
Internal low power oscillator period
External reset pulse width2
Reset low drive
tLPO
textrst
trstdrv
700
100
—
—
—
1300
—
μs
ns
ns
34 x tcyc
—
BKGD/MS setup time after issuing background debug
force reset to enter user or BDM modes
5
D
tMSSU
500
—
—
ns
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
26
Freescale Semiconductor
Electrical Characteristics
Table 17. Control Timing (continued)
Num
C
Rating
Symbol
Min
Typ1
Max
Unit
BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes 3
6
D
tMSH
100
—
—
μs
IRQ pulse width
7
8
D
D
Asynchronous path2
Synchronous path4
tILIH, IHIL
t
100
2 x tcyc
—
—
—
—
ns
ns
ns
Keyboard interrupt pulse width
Asynchronous path2
tILIH, IHIL
t
100
2 x tcyc
—
—
—
—
Synchronous path4
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)5
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
—
—
16
23
—
—
9
C
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
ns
—
—
5
9
—
—
10
C
Stop3 recovery time, from interrupt event to vector fetch tSTPREC
—
6
10
μs
1
2
Typical values are based on characterization data at VDD = 3.3 V, 25 °C unless otherwise stated.
This is the shortest pulse that is guaranteed to be recognized as a reset or interrupt pin request. Shorter pulses are not
guaranteed to override reset requests from internal sources.
3
4
5
To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD
rises above VLVD
.
This is the minimum assertion time in which the interrupt may be recognized. The correct protocol is to assert the interrupt
request until it is explicitly negated by the interrupt service routine.
Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40 °C to 85 °C.
textrst
RESET PIN
Figure 19. Reset Timing
tIHIL
KBIPx
IRQ/KBIPx
tILIH
Figure 20. IRQ/KBIPx Timing
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
27
Electrical Characteristics
3.12.2 TPM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the
optional external source to the timer counter. These synchronizers operate from the current bus rate clock.
Table 18. TPM Input Timing
No.
C
Function
Symbol
Min
Max
Unit
1
2
3
4
5
D
D
D
D
D
External clock frequency
External clock period
fTCLK
tTCLK
tclkh
0
fBus/4
—
Hz
tcyc
tcyc
tcyc
tcyc
4
External clock high time
External clock low time
Input capture pulse width
1.5
1.5
1.5
—
tclkl
—
tICPW
—
tTCLK
tclkh
TCLK
tclkl
Figure 21. Timer External Clock
tICPW
TPMCHn
TPMCHn
tICPW
Figure 22. Timer Input Capture Pulse
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
28
Freescale Semiconductor
Electrical Characteristics
3.12.3 SPI Timing
Table 19 and Figure 23 through Figure 26 describe the timing requirements for the SPI system.
Table 19. SPI Timing
No.
C
Function
Operating frequency
Symbol
Min
Max
Unit
fop
—
D
Master
Slave
fBus/2048
0
fBus/2
fBus/4
Hz
Hz
SPSCK period
Master
Slave
tSPSCK
tLead
tLag
1
2
3
4
5
6
D
D
D
D
D
D
2
4
2048
—
tcyc
tcyc
Enable lead time
Master
Slave
1/2
1
—
—
tSPSCK
tcyc
Enable lag time
Master
Slave
1/2
1
—
—
tSPSCK
tcyc
Clock (SPSCK) high or low time
Master
Slave
tWSPSCK
tcyc – 30
tcyc – 30
1024 tcyc
—
ns
ns
Data setup time (inputs)
Master
Slave
tSU
15
15
—
—
ns
ns
Data hold time (inputs)
Master
Slave
tHI
0
25
—
—
ns
ns
7
8
D
D
Slave access time
ta
tdis
tv
—
—
1
1
tcyc
tcyc
Slave MISO disable time
Data valid (after SPSCK edge)
9
D
D
D
D
Master
Slave
—
—
25
25
ns
ns
Data hold time (outputs)
Master
Slave
tHO
10
11
12
0
0
—
—
ns
ns
Rise time
Input
Output
tRI
tRO
—
—
tcyc – 25
25
ns
ns
Fall time
Input
Output
tFI
tFO
—
—
tcyc – 25
25
ns
ns
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
29
Electrical Characteristics
SS1
(OUTPUT)
2
11
12
1
3
SPSCK
(CPOL = 0)
(OUTPUT)
4
4
SPSCK
(CPOL = 1)
(OUTPUT)
5
6
MISO
(INPUT)
MSB IN2
LSB IN
BIT 6 . . . 1
9
10
9
MOSI
(OUTPUT)
MSB OUT2
BIT 6 . . . 1
LSB OUT
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 23. SPI Master Timing (CPHA = 0)
SS(1)
(OUTPUT)
1
11
12
2
12
11
3
SPSCK
(CPOL = 0)
(OUTPUT)
4
4
SPSCK
(CPOL = 1)
(OUTPUT)
5
6
MISO
(INPUT)
MSB IN(2)
BIT 6 . . . 1
LSB IN
10
9
MOSI
(OUTPUT)
MASTER MSB OUT(2)
PORT DATA
BIT 6 . . . 1
MASTER LSB OUT
PORT DATA
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 24. SPI Master Timing (CPHA =1)
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
30
Freescale Semiconductor
Electrical Characteristics
SS
(INPUT)
11
12
12
11
3
1
SPSCK
(CPOL = 0)
(INPUT)
2
4
4
SPSCK
(CPOL = 1)
(INPUT)
8
10
10
7
9
MISO
(OUTPUT)
SEE
NOTE
BIT 6 . . . 1
SLAVE LSB OUT
MSB OUT
6
SLAVE
5
MOSI
(INPUT)
BIT 6 . . . 1
MSB IN
LSB IN
NOTE:
1. Not defined but normally MSB of character just received
Figure 25. SPI Slave Timing (CPHA = 0)
SS
(INPUT)
1
3
12
11
2
SPSCK
(CPOL = 0)
(INPUT)
4
4
11
12
SPSCK
(CPOL = 1)
(INPUT)
10
9
8
MISO
(OUTPUT)
SEE
BIT 6 . . . 1
SLAVE LSB OUT
LSB IN
SLAVE MSB OUT
NOTE
5
6
7
MOSI
(INPUT)
MSB IN
BIT 6 . . . 1
NOTE:
1. Not defined but normally LSB of character just received
Figure 26. SPI Slave Timing (CPHA = 1)
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
31
Electrical Characteristics
3.12.4 ADC Characteristics
Table 20. 12-bit ADC Operating Conditions
C
Characteristic
Conditions
Symb
Min
Typ1
Max
Unit
Comment
Supply voltage Absolute
VDDAD
ΔVDDAD
ΔVSSAD
VREFH
VREFL
VADIN
1.8
-100
-100
1.8
—
0
3.6
V
mV
mV
V
D
2
Delta to VDD (VDD-VDDAD
)
+100
+100
VDDAD
VSSAD
VREFH
5.5
2
D
D
D
D
Ground voltage
Ref Voltage High
Ref Voltage Low
Input Voltage
Delta to VSS (VSS-VSSAD
)
0
VDDAD
VSSAD
—
VSSAD
VREFL
—
V
V
Input
Capacitance
CADIN
4.5
C
C
pF
Input Resistance
RADIN
RAS
—
5
7
kΩ
Analog Source 12 bit mode
Resistance fADCK > 4MHz
fADCK < 4MHz
External to MCU
—
—
—
—
2
5
C
D
10 bit mode
kΩ
fADCK > 4MHz
fADCK < 4MHz
—
—
—
—
5
10
8 bit mode (all valid fADCK
)
—
—
—
—
10
8.0
4.0
ADC Conversion High Speed (ADLPC=0)
fADCK
0.4
0.4
MHz
Clock Freq.
Low Power (ADLPC=1)
1
2
Typical values assume VDDAD = 3.3 V, Temp = 25 °C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
DC potential difference.
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
32
Freescale Semiconductor
Electrical Characteristics
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
Z
ADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
Z
AS
leakage
due to
input
ADC SAR
ENGINE
R
R
AS
ADIN
protection
+
V
ADIN
–
C
AS
V
+
AS
–
R
R
R
ADIN
ADIN
ADIN
INPUT PIN
INPUT PIN
INPUT PIN
C
ADIN
Figure 27. ADC Input Impedance Equivalency Diagram
Table 21. 12-bit ADC Characteristics (V = V , V = V
)
REFH
DDAD REFL
SSAD
Characteristic
Conditions
C
Symb
Min
Typ1
120
Max
Unit
Comment
Supply Current
ADLPC=1
ADLSMP=1
ADCO=1
T
IDDAD
—
—
—
—
—
μA
μA
μA
mA
Supply Current
ADLPC=1
ADLSMP=0
ADCO=1
T
T
T
IDDAD
IDDAD
IDDAD
202
288
—
—
1
Supply Current
ADLPC=0
ADLSMP=1
ADCO=1
Supply Current
ADLPC=0
ADLSMP=0
ADCO=1
0.532
Supply Current Stop, Reset, Module Off
D
P
C
IDDAD
—
2
0.007
3.3
2
0.8
5
μA
ADC
High Speed (ADLPC=0)
Low Power (ADLPC=1)
fADACK
tADACK = 1/fADACK
Asynchronous
Clock Source
MHz
1.25
3.3
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
33
Electrical Characteristics
Table 21. 12-bit ADC Characteristics (V
= V
Min
, V
= V
) (continued)
Unit Comment
REFH
DDAD REFL
SSAD
Characteristic
Conditions
C
Symb
Typ1
Max
Conversion Time Short Sample (ADLSMP=0)
P
C
tADC
—
—
20
40
—
—
ADCK
cycles
See the ADC
chapter in the
MCF51CN128
Reference Manual
for conversion time
variances
(Including
Long Sample (ADLSMP=1)
sample time)
Sample Time
Short Sample (ADLSMP=0)
Long Sample (ADLSMP=1)
P
C
T
P
T
T
P
T
T
P
T
T
P
T
T
P
T
D
tADS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3.5
23.5
±3.0
±1
—
—
ADCK
cycles
Total Unadjusted 12 bit mode
ETUE
—
LSB2
LSB2
LSB2
LSB2
LSB2
LSB2
LSB2
Includes
Quantization
Error
10 bit mode
±2.5
1.0
—
8 bit mode
±0.5
±1.75
±0.5
±0.3
±1.5
±0.5
±0.3
±1.5
±0.5
±0.5
±1.0
±0.5
±0.5
-1 to 0
—
Differential
Non-Linearity
12 bit mode
10 bit mode3
8 bit mode3
12 bit mode
10 bit mode
8 bit mode
DNL
INL
EZS
EFS
EQ
±1.0
±0.5
—
Integral
Non-Linearity
±1.0
±0.5
—
Zero-Scale Error 12 bit mode
10 bit mode
VADIN = VSSAD
±1.5
±0.5
—
8 bit mode
Full-Scale Error 12 bit mode
10 bit mode
VADIN = VDDAD
±1
8 bit mode
±0.5
—
Quantization
Error
12 bit mode
10 bit mode
8 bit mode
12 bit mode
10 bit mode
8 bit mode
-40°C to 25°C
25°C to 85°C
25°C
±0.5
±0.5
—
—
Input Leakage
Error
D
EIL
±2
Pad leakage4 *
RAS{test=pad leakage
±0.2
±0.1
1.646
1.769
701.2
±4
test}
±1.2
—
Temp Sensor
Slope
D
D
m
mV/°C
—
Temp Sensor
Voltage
VTEMP25
—
mV
1
Typical values assume VDDAD = 3.3 V, Temp = 25 °C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2
3
4
1 LSB = (VREFH - VREFL)/2N
Monotonicity and No-Missing-Codes guaranteed in 10 bit and 8 bit modes
Based on input pad leakage current. Refer to pad electricals.
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
34
Freescale Semiconductor
Electrical Characteristics
3.12.5 Flash Specifications
This section provides details about program/erase times and program-erase endurance for the flash memory.
Program and erase operations do not require any special power sources other than the normal V supply. For more detailed
DD
information about program/erase operations, see the Memory section of the MCF51CN128 Reference Manual.
Table 22. Flash Characteristics
C
Characteristic
Symbol
Min
Typical
Max
Unit
Supply voltage for program/erase
-40 °C to 85 °C
D
Vprog/erase
VRead
fFCLK
1.8
1.8
150
5
—
—
3.6
3.6
V
D
D
D
P
P
P
P
D
D
Supply voltage for read operation
Internal FCLK frequency1
V
—
200
6.67
kHz
μs
Internal FCLK period (1/FCLK)
Longword program time (random location)(2)
Longword program time (burst mode)(2)
Page erase time2
tFcyc
—
tprog
9
tFcyc
tFcyc
tFcyc
tFcyc
mA
mA
tBurst
4
tPage
4000
20,000
9.7
7.6
Mass erase time(2)
tMass
Longword program current3
Page erase current3
RIDDBP
RIDDPE
—
—
—
—
Program/erase endurance4
TL to TH = –40°C to + 85°C
T = 25°C
C
C
10,000
—
—
100,000
—
—
cycles
years
Data retention5
tD_ret
15
100
—
1
2
The frequency of this clock is controlled by a software setting.
These values are hardware state machine controlled. User code does not need to count cycles. This information supplied
for calculating approximate time to program and erase.
3
4
The program and erase currents are additional to the standard run IDD. These values are measured at room temperatures
with VDD = 3.3 V, bus frequency = 8.0 MHz.
Typical endurance for flash was evaluated for this product family on the HC9S12Dx64. For additional information on
how Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile
Memory.
5
Typical data retention values are based on intrinsic capability of the technology measured at high temperature and
de-rated to 25 °C using the Arrhenius equation. For additional information on how Freescale defines typical data retention,
refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.
3.13 EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependent on the environment in which the MCU resides. Board
design and layout, circuit topology choices, location and characteristics of external components as well as MCU software
operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such
as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC
performance.
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
35
Ordering Information
3.13.1 Radiated Emissions
Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance
with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a
custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller
are measured in a TEM cell in two package orientations (North and East). For more detailed information concerning the
evaluation results, conditions and setup, please refer to the EMC Evaluation Report for this device.
4
Ordering Information
This section contains ordering information for MCF51CN128 devices.
Table 23. Ordering Information
Memory
Temperature Range
Freescale Part Number1
Package2
(°C)
Flash
RAM
MCF51CN128CLK
MCF51CN128CLH
MCF51CN128CGT
128K
128K
128K
24K
24K
24K
–40 to +85
–40 to +85
–40 to +85
80-pin LQFP
64-pin LQFP
48-pin QFN
1
2
See the MCF51CN128 Reference Manual (document MCF51CN128RM), for a complete description of modules included
on each device.
See Table 24 for package information.
5
Package Information
Table 24. Package Descriptions
Pin Count
Package Type
Abbreviation
Designator
Case No.
Document No.
80
64
48
Low Quad Flat Package
Low Quad Flat Package
Quad Flat No-Leads
LQFP
LQFP
QFN
LK
LH
GT
917A
840F
1314
98ASS23237W
98ASS23234W
98ARH99048A
6
Mechanical Outline Drawings
The following pages are mechanical drawings for the packages described in Table 24. For the latest available drawings, visit
freescale web site (http://www.freescale.com) and enter the package’s document number into the keyword search box.
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
36
Freescale Semiconductor
Mechanical Outline Drawings
6.1
80-pin LQFP
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
37
Mechanical Outline Drawings
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
38
Freescale Semiconductor
Mechanical Outline Drawings
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
39
Mechanical Outline Drawings
6.2
64-pin LQFP
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
40
Freescale Semiconductor
Mechanical Outline Drawings
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
41
Mechanical Outline Drawings
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
42
Freescale Semiconductor
Mechanical Outline Drawings
6.3
48-pin QFN
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
43
Mechanical Outline Drawings
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
44
Freescale Semiconductor
Mechanical Outline Drawings
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
45
Mechanical Outline Drawings
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
46
Freescale Semiconductor
Revision History
7
Revision History
This section lists the changes between versions of MCF51CN128 Data Sheet document.
Table 25. Revision History
Revision Number
Date
Description of Changes
Alpha Customer Release.
1
2
3
4
August 2008
January 2009
January 2009
May 2009
Pre-Launch Release.
Launch Release.
• Changed LVDH trip and recovery values in Table 8.
• Fixed Mini-FlexBus maximum frequency to 25.1666 MHz in
Section 3.10, “Mini-FlexBus Timing Specifications.”
• Updated FEC feature list to describe ethernet operation
between 3.0 V to 3.6 V.
• In Table 8, added a footnote to the operating voltage. It
describes an exception to the Fast Ethernet Controller (FEC),
because it is only operational above the operating voltage of
3 V.
• Corrected Freescale part numbers in Table 23.
• In Table 21, changed IDDAD classification to T.
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
47
Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
How to Reach Us:
Home Page:
www.freescale.com
E-mail:
support@freescale.com
Freescale Semiconductor reserves the right to make changes without further notice to
any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor assume any liability arising out of the application or use of any
product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters that may be
provided in Freescale Semiconductor data sheets and/or specifications can and do vary
in different applications and actual performance may vary over time. All operating
parameters, including “Typicals”, must be validated for each customer application by
customer’s technical experts. Freescale Semiconductor does not convey any license
under its patent rights nor the rights of others. Freescale Semiconductor products are
not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Freescale Semiconductor product
could create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Freescale
USA/Europe or Locations Not Listed:
Freescale Semiconductor
Technical Information Center, CH370
1300 N. Alma School Road
Chandler, Arizona 85224
+1-800-521-6274 or +1-480-768-2130
support@freescale.com
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
support@freescale.com
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
Semiconductor was negligent regarding the design or manufacture of the part.
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064
RoHS-compliant and/or Pb-free versions of Freescale products have the functionality
and electrical characteristics as their non-RoHS-compliant and/or non-Pb-free
counterparts. For further information, see http://www.freescale.com or contact your
Freescale sales representative.
Japan
0120 191014 or +81 3 5437 9125
support.japan@freescale.com
Asia/Pacific:
Freescale Semiconductor China Ltd.
Exchange Building 23F
No. 118 Jianguo Road
Chaoyang District
For information on Freescale’s Environmental Products program, go to
http://www.freescale.com/epp.
Beijing 100022
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
All other product or service names are the property of their respective owners.
China
+86 10 5879 8000
support.asia@freescale.com
© Freescale Semiconductor, Inc. 2009. All rights reserved.
For Literature Requests Only:
Freescale Semiconductor Literature Distribution Center
P.O. Box 5405
Denver, Colorado 80217
1-800-441-2447 or 303-675-2140
Fax: 303-675-2150
LDCForFreescaleSemiconductor@hibbertgroup.com
Document Number: MCF51CN128
Rev. 4
5/2009
相关型号：
MCF51CN128CLK
32-BIT, FLASH, 50.33 MHz, MICROCONTROLLER, PQFP80, 14 X 14 MM, 1.40 MM HEIGHT, 0.65 MM PITCH, LQFP-80
ROCHESTER
MCF51EM256_1
MCF51EM256-based Poly Phase Energy Meter Reference Design 110V Technical Specifications
FREESCALE
MCF51EM256_2
MCF51EM256-based Poly Phase Energy Meter Reference Design 220V Technical Specifications
FREESCALE
MCF51JE128CLK
32-BIT, FLASH, 50.33MHz, MICROCONTROLLER, PQFP80, 12 X 12 MM, ROHS COMPLIANT, LQFP-80
NXP
©2020 ICPDF网 联系我们和版权申明