MCF52233 [FREESCALE]

ColdFire㈢ Microcontroller; ColdFire㈢微控制器


型号：	MCF52233
厂家：	Freescale
描述：	ColdFire㈢ Microcontroller ColdFire㈢微控制器微控制器
文件：	总48页 (文件大小：603K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCF52235DS

Rev. 0, 04/2006

Freescale Semiconductor

Data Sheet: Advance Information

MCF52235 ColdFire®

Microcontroller Data Sheet

Supports MCF52235, MCF52234, MCF52233, MCF52231, &

MCF52230

By: Microcontroller Division

Table of Contents

The MCF52235 is a member of the ColdFire family of

reduced

instruction

set

computing

(RISC)

MCF52235 Family Configurations.......................2

microprocessors. This hardware specification provides

an overview of the 32-bit MCF52235 microcontroller,

focusing on its highly integrated and diverse feature set.

1.1 Block Diagram ...................................................3

1.2 Features.............................................................4

1.3 Part Numbers and Packaging..........................16

1.4 Package Pinouts..............................................17

1.5 Reset Signals ..................................................24

1.6 PLL and Clock Signals ....................................24

1.7 Mode Selection................................................24

1.8 External Interrupt Signals................................24

1.9 Queued Serial Peripheral Interface (QSPI) .....25

1.11 I²C I/O Signals.................................................27

1.12 UART Module Signals .....................................27

1.13 DMA Timer Signals..........................................27

1.16 Pulse Width Modulator Signals........................28

1.17 Debug Support Signals....................................28

1.18 EzPort Signal Descriptions..............................30

1.19 Power and Ground Pins...................................30

This 32-bit device is based on the Version 2 ColdFire

core operating at a frequency up to 60 MHz, offering

high performance and low power consumption. On-chip

memories connected tightly to the processor core include

256 Kbytes of Flash and 32 Kbytes of static random

access memory (SRAM). On-chip modules include:

•

V2 ColdFire core providing 56 Dhrystone 2.1

MIPS @ 60 MHz executing out of on-chip Flash

memory using enhanced multiply accumulate

(EMAC) and hardware divider.

Preliminary Electrical Characteristics................31

Mechanical Outline Drawings............................45

•

Enhanced Multiply Accumulate Unit (EMAC)

and hardware divide module

Cryptographic Acceleration Unit (CAU)

coprocessor

•

Fast Ethernet Controller (FEC)

On-chip Ethernet Transceiver (ePHY)

This document contains information on a new product. Specifications and information herein

are subject to change without notice.

• Preliminary

MCF52235 Family Configurations

•

FlexCAN controller area network (CAN) module

Three universal asynchronous/synchronous receiver/transmitters (UARTs)

Inter-integrated circuit (I²C™) bus controller

Queued serial peripheral interface (QSPI) module

Eight-channel 12-bit fast analog-to-digital converter (ADC)

Four channel direct memory access (DMA) controller

Four 32-bit input capture/output compare timers with DMA support (DTIM)

Four-channel general-purpose timer (GPT) capable of input capture/output compare, pulse width

modulation (PWM) and pulse accumulation

•

Eight/Four-channel 8/16-bit pulse width modulation timers (two adjacent 8-bit PWMs can be

concatenated to form a single 16-bit timer)

•

Two 16-bit periodic interrupt timers (PITs)

Real-time clock (RTC) module

Programmable software watchdog timer

Two interrupt controllers providing every peripheral with a unique selectable-priority interrupt

vector plus seven external interrupts with fixed levels/priorities

•

Clock module with support for crystal or external oscillator and integrated phase locked loop

(PLL)

Test access/debug port (JTAG, BDM)

1 MCF52235 Family Configurations

Table 1. MCF52235 Family Configurations

Module

52230

52231

52233

52234

52235

ColdFire Version 2 Core with MAC

(Multiply-Accumulate Unit)

System Clock

60 MHz

Performance (Dhrystone 2.1 MIPS)

Flash / Static RAM (SRAM)

128/32 Kbytes

256/32 Kbytes

Interrupt Controllers (INTC0/INTC1)

Fast Analog-to-Digital Converter (ADC)

Random Number Generator and Crypto

Acceleration Unit (CAU)

FlexCAN 2.0B Module

Fast Ethernet Controller (FEC) with

on-chip interface (ePHY)

Four-channel Direct-Memory Access

(DMA)

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Preliminary

Freescale Semiconductor

MCF52235 Family Configurations

Table 1. MCF52235 Family Configurations (continued)

Module

52230

52231

52233

52234

52235

Software Watchdog Timer (WDT)

Programmable Interrupt Timer

Four-Channel General Purpose Timer

32-bit DMA Timers

QSPI

UART(s)

I²C

Eight/Four-channel 8/16-bit PWM Timer

General Purpose I/O Module (GPIO)

Chip Configuration and Reset Controller

Module

Background Debug Mode (BDM)

JTAG - IEEE 1149.1 Test Access Port¹

Package

80-pin LQFP

80-pin LQFP 112-pin LQFP

112-pin LQFP 112-pin LQFP 112-pin LQFP 112-pin LQFP 121 MAPBGA

121 MAPBGA

^NOT^TEh^Se^:full debug/trace interface is available only on the 112- and 121-pin packages. A reduced debug

interface is bonded on the 80-pin package.

1.1 Block Diagram

The MCF52235 (or its variants) come in 80- and 112-pin low-profile quad flat pack packages (LQFP) and

a 121 MAPBGA, and operates in single-chip mode only. Figure 1 shows a top-level block diagram of the

MCF52235.

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Freescale Semiconductor

Preliminary

MCF52235 Family Configurations

EzPD

EzPCK

EzPCS

EPHY_TX

EzPort

Arbiter

EPHY_RX

EzPQ

ICOCn

QSPI_DIN,

QSPI_DOUT

Interrupt

Controller 1

Interrupt

EPHY

Controller 2

QSPI_SCK,

QSPI_PCSn

I²C_SDA

I²C_SCL

UnTXD

Fast

Ethernet

Controller

(FEC)

UART

UnRXD

I²C

QSPI

RTC

UnRTS

4 CH DMA

UnCTS

DTINn/DTOUTn

CANRX

CANTX

DTIM

To/From PADI

PWMn

JTAG_EN

MUX

V2 ColdFire CPU

CAU

IFP OEP

EMAC

PMM

CIM

JTAG

TAP

32 Kbytes

SRAM

256 Kbytes

Flash

(32Kx16)x4

RSTIN

PORTS

(GPIO)

AN[7:0]

ADC

RSTOUT

(4Kx16)x4

V_RHV_RL

PLL

CLKGEN

Edge

Port 1

PWM

PIT1

FlexCAN

Edge

Port 2

EXTAL XTAL CLKOUT

GPT

PIT0

RNGA

To/From Interrupt Controller

Figure 1. MCF52235 Block Diagram

1.2 Features

This document contains information on a new product under development. Freescale reserves the right to

change or discontinue this product without notice. Specifications and information herein are subject to

change without notice.

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Freescale Semiconductor

Preliminary

MCF52235 Family Configurations

1.2.1 Feature Overview

•

Version 2 ColdFire variable-length RISC processor core

— Static operation

— 32-bit address and data path on-chip

— Up to 60MHz processor core frequency

— Sixteen general-purpose 32-bit data and address registers

— Implements ColdFire ISA_A+ with extensions to support the user stack pointer register, and 4

new instructions for improved bit processing

— Enhanced Multiply-Accumulate (EMAC) unit with four 48-bit accumulators to support 32-bit

signal processing algorithms

— Cryptography Acceleration Unit (CAU)

– Tightly-coupled coprocessor to accelerate software-based encryption and message digest

functions

– FIPS-140 compliant random number generator

– Support for DES, 3DES, AES, MD5, and SHA-1 algorithms

— Illegal instruction decode that allows for 68K emulation support

System debug support

•

— Real time trace for determining dynamic execution path

— Background debug mode (BDM) for in-circuit debugging

— Real time debug support, with four user-visible hardware breakpoint registers (PC and address

with optional data) that can be configured into a 1- or 2-level trigger

•

On-chip memories

— 32 Kbyte dual-ported SRAM on CPU internal bus, accessible by core and non-core bus

masters (e.g., DMA) with standby power supply support

— 256 Kbytes of interleaved Flash memory supporting 2-1-1-1 accesses

Power management

— Fully static operation with processor sleep and whole chip stop modes

— Very rapid response to interrupts from the low-power sleep mode (wake-up feature)

— Software visible clock enable/disable for each peripheral

Fast Ethernet Controller (FEC)

•

— 10/100 BaseT/TX capability, half duplex or full duplex

— On-chip transmit and receive FIFOs

— Built-in dedicated DMA controller

— Memory-based flexible descriptor rings

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Freescale Semiconductor

Preliminary

MCF52235 Family Configurations

•

On-chip Ethernet Transceiver (ePHY)

— Digital adaptive equalization

— Supports auto-negotiation

— Baseline wander correction

— Full-/Half-duplex support in all modes

— Loopback modes

— Supports MDIO preamble suppression

— Jumbo packet

•

FlexCAN 2.0B Module

— Based on and includes all existing features of the Freescale TOUCAN module

— Full implementation of the CAN protocol specification version 2.0B

– Standard Data and Remote Frames (up to 109 bits long)

– Extended Data and Remote Frames (up to 127 bits long)

– 0-8 bytes data length

– Programmable bit rate up to 1 Mbit/sec

— Flexible Message Buffers (MBs), totalling up to 16 message buffers of 0–8 byte data length

each, configurable as Rx or Tx, all supporting standard and extended messages

— Unused Message Buffer space can be used as general purpose RAM space

— Listen only mode capability

— Content-related addressing

— No read/write semaphores required

— Three programmable mask registers: global (for MBs 0-13), special for MB14 and special for

MB15

— Programmable transmit-first scheme: lowest ID or lowest buffer number

— “Time stamp” based on 16-bit free-running timer

— Global network time, synchronized by a specific message

— Programmable I/O modes

— Maskable interrupts

•

Three Universal Asynchronous/synchronous Receiver Transmitters (UARTs)

— 16-bit divider for clock generation

— Interrupt control logic

— Maskable interrupts

— DMA support

— Data formats can be 5, 6, 7 or 8 bits with even, odd or no parity

— Up to 2 stop bits in 1/16 increments

— Error-detection capabilities

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Freescale Semiconductor

Preliminary

MCF52235 Family Configurations

— Modem support includes request-to-send (URTS) and clear-to-send (UCTS) lines for two

UARTs

— Transmit and receive FIFO buffers

•

I²C Module

— Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads

— Fully compatible with industry-standard I²C bus

— Master or slave modes support multiple masters

— Automatic interrupt generation with programmable level

Queued Serial Peripheral Interface (QSPI)

— Full-duplex, three-wire synchronous transfers

— Up to four chip selects available

— Master mode operation only

— Programmable master bit rates

— Up to 16 pre-programmed transfers

•

Fast Analog-to-Digital Converter (ADC)

— 8 analog input channels

— 12-bit resolution

— Minimum 2.25 µS conversion time

— Simultaneous sampling of two channels for motor control applications

— Single-scan or continuous operation

— Optional interrupts on conversion complete, zero crossing (sign change), or under/over

low/high limit

— Unused analog channels can be used as digital I/O

Four 32-bit DMA Timers

•

— 16.7-ns resolution at 60 MHz

— Programmable sources for clock input, including an external clock option

— Programmable prescaler

— Input-capture capability with programmable trigger edge on input pin

— Output-compare with programmable mode for the output pin

— Free run and restart modes

— Maskable interrupts on input capture or reference-compare

— DMA trigger capability on input capture or reference-compare

Four-channel general purpose timers

•

— 16-bit architecture

— Programmable prescaler

— Output pulse widths variable from microseconds to seconds

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Freescale Semiconductor

Preliminary

MCF52235 Family Configurations

— Single 16-bit input pulse accumulator

— Toggle-on-overflow feature for pulse-width modulator (PWM) generation

— One dual-mode pulse accumulation channel

•

Pulse-width modulation timer

— Operates as eight channels with 8-bit resolution or four channels with 16-bit resolution

— Programmable period and duty cycle

— Programmable enable/disable for each channel

— Software selectable polarity for each channel

— Period and duty cycle are double buffered. Change takes effect when the end of the current

period is reached (PWM counter reaches zero) or when the channel is disabled.

— Programmable center or left aligned outputs on individual channels

— Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies

— Emergency shutdown

•

Two Periodic Interrupt Timers (PITs)

— 16-bit counter

— Selectable as free running or count down

Real-Time Clock (RTC)

— Maintains system time-of-day clock

— Provides stopwatch and alarm interrupt functions

Software Watchdog Timer

— 32-bit counter

— Low power mode support

Clock Generation Features

— 25 MHz crystal input

— On-chip PLL can generate core frequencies up to maximum 60MHz operating frequency

— Provides clock for integrated ePHY

•

Dual Interrupt Controllers (INTC0/INTC1)

— Support for multiple interrupt sources organized as follows:

– Fully-programmable interrupt sources for each peripheral

– 7 fixed-level interrupt sources

– Seven external interrupt signals

— Unique vector number for each interrupt source

— Ability to mask any individual interrupt source or all interrupt sources (global mask-all)

— Support for hardware and software interrupt acknowledge (IACK) cycles

— Combinatorial path to provide wake-up from low power modes

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Freescale Semiconductor

Preliminary

MCF52235 Family Configurations

•

DMA Controller

— Four fully programmable channels

— Dual-address transfer support with 8-, 16- and 32-bit data capability along with support for

16-byte (4 X 32-bit) burst transfers

— Source/destination address pointers that can increment or remain constant

— 24-bit byte transfer counter per channel

— Auto-alignment transfers supported for efficient block movement

— Bursting and cycle steal support

— support for channel-to-channel linking

— Software-programmable DMA channel selections in the UARTs (3) and 32-bit timers (4)

Reset

•

— Separate reset in and reset out signals

— Seven sources of reset:

– Power-on reset (POR)

– External

– Software

– Watchdog

– Loss of clock

– Loss of lock

– Low-voltage detection (LVD)

— Status flag indication of source of last reset

Chip Integration Module (CIM)

•

— System configuration during reset

— Selects one of six clock modes

— Configures output pad drive strength

— Unique part identification number and part revision number

General Purpose I/O interface

•

— Up to 73 bits of general purpose I/O

— Bit manipulation supported via set/clear functions

— Unused peripheral pins may be used as extra GPIO

JTAG support for system level board testing

1.2.2 V2 Core Overview

The Version 2 ColdFire processor core is comprised of two separate pipelines that are decoupled by an

instruction buffer. The two-stage Instruction Fetch Pipeline (IFP) is responsible for instruction-address

generation and instruction fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that holds

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Freescale Semiconductor

Preliminary

MCF52235 Family Configurations

prefetched instructions awaiting execution in the Operand Execution Pipeline (OEP). The OEP includes

two pipeline stages. The first stage decodes instructions and selects operands (DSOC); the second stage

(AGEX) performs instruction execution and calculates operand effective addresses, if needed.

The V2 core implements the ColdFire Instruction Set Architecture Revision A+ (see the ColdFire Family

Programmer’s Reference Manual for instruction set details) which includes support for a separate user

stack pointer register and four new instructions to assist in bit processing. Additionally, the MCF52235

core includes the enhanced multiply-accumulate unit (EMAC) for improved signal processing capabilities.

The MAC implements a 4-stage arithmetic pipeline, optimized for 32 x 32 bit operations, with support for

four 48-bit accumulators. Supported operands include 16- and 32-bit signed and unsigned integers as well

as signed fractional operands and a complete set of instructions to process these data types. The EMAC

provides superb support for execution of DSP operations within the context of a single processor at a

minimal hardware cost.

1.2.3 Debug Module

The ColdFire processor core debug interface is provided to support system debugging in conjunction with

low-cost debug and emulator development tools. Through a standard debug interface users can access

debug information, and on 112- and 121-lead packages real-time tracing capability is provided. This

allows the processor and system to be debugged at full speed without the need for costly in-circuit

emulators. The debug interface is a superset of the BDM interface provided on Freescale’s 683xx family

of parts. The MCF52235 supports Revision B+ of the ColdFire debug architecture (DEBUG_B+).

The on-chip breakpoint resources include a total of nine programmable 32-bit registers: two address

registers, two data registers (one data register and one data mask register), four 32-bit PC registers and one

PC mask register. These registers can be accessed through the dedicated debug serial communication

channel or from the processor’s supervisor mode programming model. The breakpoint registers can be

configured to generate triggers by combining the address, data, and PC conditions in a variety of single-

or dual-level definitions. The trigger event can be programmed to generate a processor halt or initiate a

debug interrupt exception.

The MCF52235’s interrupt servicing options during emulator mode allow real-time critical interrupt

service routines to be serviced while processing a debug interrupt event, thereby ensuring that the system

continues to operate even during debugging.

To support program trace, the V2 debug module provides processor status (PST[3:0]) and debug data

(DDATA[3:0]) ports. These buses and the PSTCLK output provide execution status, captured operand

data, and branch target addresses defining processor activity at the CPU’s clock rate. The MCF52235

includes a new debug signal, ALLPST. This signal is the logical ‘AND’ of the processor status (PST[3:0])

signals and is useful for detecting when the processor is in a halted state (PST[3:0] = 1111).

The full debug/trace interface is available only on the 112- and 121-pin packages. However, every product

features the dedicated debug serial communication channel (DSI, DSO, DSCLK) and the ALLPST signal.

1.2.4 JTAG

The MCF52235 supports circuit board test strategies based on the Test Technology Committee of IEEE

and the Joint Test Action Group (JTAG). The test logic includes a test access port (TAP) consisting of a

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Freescale Semiconductor

Preliminary

MCF52235 Family Configurations

16-state controller, an instruction register, and three test registers (a 1-bit bypass register, a 256-bit

boundary-scan register, and a 32-bit ID register). The boundary scan register links the device’s pins into

one shift register. Test logic, implemented using static logic design, is independent of the device system

logic.

The MCF52235 implementation can do the following:

•

Perform boundary-scan operations to test circuit board electrical continuity

Sample MCF52235 system pins during operation and transparently shift out the result in the

boundary scan register

•

Bypass the MCF52235 for a given circuit board test by effectively reducing the boundary-scan

•

Disable the output drive to pins during circuit-board testing

Drive output pins to stable levels

1.2.5 On-Chip Memories

1.2.5.1 SRAM

The SRAM module provides a general-purpose 32-Kbyte memory block that the ColdFire core can access

in a single cycle. The location of the memory block can be set to any 32-Kbyte boundary within the

4-Gbyte address space. This memory is ideal for storing critical code or data structures and for use as the

system stack. Because the SRAM module is physically connected to the processor's high-speed local bus,

it can quickly service core-initiated accesses or memory-referencing commands from the debug module.

The SRAM module is also accessible by the DMA. The dual-ported nature of the SRAM makes it ideal

for implementing applications with double-buffer schemes, where the processor and a DMA device

operate in alternate regions of the SRAM to maximize system performance.

1.2.5.2 Flash

The ColdFire Flash Module (CFM) is a non-volatile memory (NVM) module that connects to the

processor’s high-speed local bus. The CFM is constructed with four banks of 32K x 16-bit Flash arrays to

generate 256 Kbytes of 32-bit Flash memory. These arrays serve as electrically erasable and

programmable, non-volatile program and data memory. The Flash memory is ideal for program and data

storage for single-chip applications, allowing for field reprogramming without requiring an external high

voltage source. The CFM interfaces to the ColdFire core through an optimized read-only memory

controller which supports address speculation and interleaved accesses from the 2-cycle Flash arrays for

improved performance. For operation at reduced core frequencies, the access time can be decreased (under

program control) to a single-cycle access. A backdoor mapping of the Flash memory is used for all

program, erase, and verify operations, as well as providing a read datapath for the DMA. Flash memory

may also be programmed via the EzPort, which is a serial Flash programming interface that allows the

Flash to be read, erased and programmed by an external controller in a format compatible with most SPI

bus Flash memory chips. This allows easy device programming via Automated Test Equipment or bulk

programming tools.

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Freescale Semiconductor

Preliminary

MCF52235 Family Configurations

1.2.6 Power Management

The MCF52235 incorporates several low power modes of operation which are entered under program

control and exited by several external trigger events. An integrated power-on reset (POR) circuit monitors

the input supply and forces an MCU reset as the supply voltage rises. The low voltage detector (LVD)

monitors the supply voltage and is configurable to force a reset or interrupt condition if it falls below the

LVD trip point.

1.2.7 Fast Ethernet Controller (FEC)

The integrated Fast Ethernet Controller (FEC) performs the full set of IEEE 802.3/Ethernet CSMA/CD

media access control and channel interface functions. The FEC connects through the on-chip transceiver

(ePHY) which provides the physical layer interface.

1.2.8 Ethernet Physical Interface (ePHY)

The ePHY is an IEEE 802.3 compliant 10/100 Ethernet physical transceiver. The ePHY can be configured

to support 10BASE-T or 100BASE-TX applications. The ePHY is configurable via internal registers.

There are five basic modes of operation for the ePHY:

•

Power down/initialization

Auto-negotiate

10BASE-T

100BASE-TX

Low-power

1.2.9 Cryptography Acceleration Unit

The MCF52235 device incorporates two hardware accelerators for cryptographic functions. First, the

CAU is a coprocessor tightly-coupled to the V2 ColdFire core that implements a set of specialized

operations to increase the throughput of software-based encryption and message digest functions,

specifically the DES, 3DES, AES, MD5 and SHA-1 algorithms. Second, a random number generator

provides FIPS-140 compliant 32-bit values to security processing routines. Both modules supply critical

acceleration to software-based cryptographic algorithms at a minimal hardware cost.

1.2.10 FlexCAN

The FlexCAN module is a communication controller implementing version 2.0 of the CAN protocol parts

A and B. The CAN protocol can be used as an industrial control serial data bus, meeting the specific

requirements of reliable operation in a harsh EMI environment with high bandwidth. This instantiation of

FlexCAN has 16 message buffers.

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Freescale Semiconductor

Preliminary

MCF52235 Family Configurations

1.2.11 UARTs

The MCF52235 has three full-duplex UARTs that function independently. The three UARTs can be

clocked by the system bus clock, eliminating the need for an external clock source. On smaller packages,

the third UART is multiplexed with other digital I/O functions.

1.2.12 I C Bus

The I²C bus is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange

and minimizes the interconnection between devices. This bus is suitable for applications requiring

occasional communications over a short distance between many devices on a circuit board.

1.2.13 QSPI

The queued serial peripheral interface (QSPI) provides a synchronous serial peripheral interface with

queued transfer capability. It allows up to 16 transfers to be queued at once, minimizing the need for CPU

intervention between transfers.

1.2.14 ADC

The Fast ADC consists of an eight-channel input select multiplexer and two independent sample and hold

(S/H) circuits feeding separate 12-bit ADCs. The two separate converters store their results in accessible

buffers for further processing.

The ADC can be configured to perform a single scan and halt, perform a scan whenever triggered, or

perform a programmed scan sequence repeatedly until manually stopped.

The ADC can be configured for either sequential or simultaneous conversion. When configured for

sequential conversions, up to eight channels can be sampled and stored in any order specified by the

channel list register. Both ADCs may be required during a scan, depending on the inputs to be sampled.

During a simultaneous conversion, both S/H circuits are used to capture two different channels at the same

time. This configuration requires that a single channel may not be sampled by both S/H circuits

simultaneously.

Optional interrupts can be generated at the end of the scan sequence if a channel is out of range (measures

below the low threshold limit or above the high threshold limit set in the limit registers) or at several

different zero crossing conditions.

1.2.15 DMA Timers (DTIM0–DTIM3)

There are four independent, DMA transfer capable 32-bit timers (DTIM0, DTIM1, DTIM2, and DTIM3)

on the MCF52235. Each module incorporates a 32-bit timer with a separate register set for configuration

and control. The timers can be configured to operate from the system clock or from an external clock

source using one of the DTINx signals. If the system clock is selected, it can be divided by 16 or 1. The

input clock is further divided by a user-programmable 8-bit prescaler which clocks the actual timer counter

mode. Timer events may optionally cause interrupt requests or DMA transfers.

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Freescale Semiconductor

Preliminary

MCF52235 Family Configurations

1.2.16 General Purpose Timer (GPT)

The general purpose timer (GPT) is a four-channel timer module consisting of a 16-bit programmable

counter driven by a 7-stage programmable prescaler. Each of the four channels can be configured for input

capture or output compare. Additionally, one of the channels, channel 3, can be configured as a pulse

accumulator.

A timer overflow function allows software to extend the timing capability of the system beyond the 16-bit

range of the counter. The input capture and output compare functions allow simultaneous input waveform

measurements and output waveform generation. The input capture function can capture the time of a

selected transition edge. The output compare function can generate output waveforms and timer software

delays. The 16-bit pulse accumulator can operate as a simple event counter or a gated time accumulator.

1.2.17 Periodic Interrupt Timers (PIT0 and PIT1)

The two periodic interrupt timers (PIT0 and PIT1) are 16-bit timers that provide interrupts at regular

intervals with minimal processor intervention. Each timer can either count down from the value written in

its PIT modulus register, or it can be a free-running down-counter.

1.2.18 Pulse Width Modulation Timers

The MCF52235 has an 8-channel, 8-bit PWM timer. Each channel has a programmable period and duty

cycle as well as a dedicated counter. Each of the modulators can create independent continuous waveforms

with software-selectable duty rates from 0% to 100%. The PWM outputs have programmable polarity, and

can be programmed as left aligned outputs or center aligned outputs. For higher period and duty cycle

resolution, each pair of adjacent channels ([7:6], [5:4], [3:2], and [1:0]) can be concatenated to form a

single 16-bit channel. The module can thus be configured to support 8/0, 6/1, 4/2, 2/3, or 0/4 8-/16-bit

channels.

1.2.19 Real-Time Clock (RTC)

The Real-Time Clock (RTC) module maintains the system (time-of-day) clock and provides stopwatch,

alarm, and interrupt functions. It includes full clock features: seconds, minutes, hours, days and supports

a host of time-of-day interrupt functions along with an alarm interrupt.

1.2.20 Software Watchdog Timer

The watchdog timer is a 16-bit timer that facilitates recovery from runaway code. The watchdog counter

is a free-running down-counter that generates a reset on underflow. To prevent a reset, software must

periodically restart the countdown.

1.2.21 Phase Locked Loop (PLL)

The clock module supports an external crystal oscillator and includes a phase-locked loop (PLL), reduced

frequency divider (RFD), low-power divider status/control registers, and control logic. In order to improve

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Freescale Semiconductor

Preliminary

MCF52235 Family Configurations

noise immunity the PLL has its’ own power supply inputs: VDDPLL and VSSPLL. All other circuits are

1.2.22 Interrupt Controller (INTC0/INTC1)

There are two interrupt controllers on the MCF52235. These interrupt controllers are organized as seven

levels with up to nine interrupt sources per level. Each interrupt source has a unique interrupt vector, and

provide each peripheral with all necessary interrupts. Each internal interrupt has a programmable level

[1-7] and priority within the level. The seven external interrupts have fixed levels/priorities.

1.2.23 DMA Controller

The Direct Memory Access (DMA) Controller Module provides an efficient way to move blocks of data

with minimal processor interaction. The DMA module provides four channels (DMA0-DMA3) that allow

byte, word, longword or 16-byte burst line transfers. These transfers are triggered by software explicitly

setting a DCRn[START] bit or by the assertion of a DMA request from any number of on-chip peripherals.

The DMA controller supports dual address transfers to on-chip devices.

1.2.24 Reset

The reset controller determines the source of reset, asserts the appropriate reset signals to the system, and

keeps track of what caused the last reset. There are six sources of reset:

•

External reset input

Power-on reset (POR)

Watchdog timer

Phase locked-loop (PLL) loss of lock

PLL loss of clock

Software

Registers provide status flags indicating the last source of reset and a control bit for software assertion of

the RSTO pin.

1.2.25 GPIO

All of the pins associated with the external bus interface may be used for several different functions. When

not used this, all of the pins may be used as general-purpose digital I/O pins. In some cases, the pin function

is set by the operating mode, and the alternate pin functions are not supported.

The digital I/O pins on the MCF52235 are grouped into 8-bit ports. Some ports do not use all eight bits.

Each port has registers that configure, monitor, and control the port pins.

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Freescale Semiconductor

Preliminary

MCF52235 Family Configurations

1.3 Part Numbers and Packaging

Table 2. Part Number Summary

Part Number

Flash / SRAM

Key Features

Package

Speed

MCF52230

128 Kbytes / 32 Kbytes 3 UARTs, I²C, QSPI, A/D, FEC ePHY, DMA,

16-/32-bit PWM Timers

80-pin TQFP

112-pin LQFP

60 MHz

MCF52231

MCF52233

MDCF52234

128 Kbytes / 32 Kbytes 3 UARTs, I²C, QSPI, A/D, FEC ePHY, DMA,

16-/32-bit PWM Timers, CAN

80-pin TQFP

112-pin LQFP

60 MHz

256 Kbytes / 32 Kbytes 3 UARTs, I²C, QSPI, A/D, FEC ePHY, DMA,

16-/32-bit PWM Timers

80-pin TQFP

112-pin LQFP

256 Kbytes / 32 Kbytes

3 UARTs, I²C, QSPI, A/D, FEC, ePHY,

DMA, 16-/32-bit PWM Timers, CAN

80-pin TQFP

112-pin LQFP

121 MAPBGA

MCF52235

256 Kbytes / 32 Kbytes 3 UARTs, I²C, QSPI, A/D, CAU, FEC, DMA,

ePHY, 16-/32-bit PWM Timers, CAN

112-pin LQFP

121 MAPBGA

60 MHz

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Preliminary

Freescale Semiconductor

MCF52235 Family Configurations

1.4 Package Pinouts

Figure 2 shows the pinout configuration for the 80-Lead TQFP.

TCLK/PSTCLK

TMS/BKPT

RCON/EZPCS

TDI/DSI

TDO/DSO

TRST/DSCLK

ALLPST

TIN0/TOUT0

TIN1/TOUT1

VDDX1

ACT_LED

LINK_LED

VDDR

SPD_LED

PHY_VSSRX

PHY_VDDRX

PHY_RXN

PHY_RXP

PHY_VSSTX

PHY_TXN

PHY_TXP

PHY_VDDTX

PHY_VDDA

PHY_VSSA

PHY_RBIAS

VDD2

80-Lead

TQFP-EP

VSSX1

JTAG_EN

TIN2/TOUT2

TIN3/TOUT3

U1_RTS

U1_CTS

U0_RTS

U0_CTS

SYNCB

VSS2

DUPLED

COLLED

IRQ11

SYNCA

Figure 2. 80-Lead TQFP Pin Assignments

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Preliminary

Freescale Semiconductor

MCF52235 Family Configurations

Figure 3 shows the pinout configuration for the 112-Lead LQFP.

ACTLED

LNKLED

VDDR

SPDLED

PST3

PST2

PST1

TCLK/PSTCLK

TMS/BKPT

RCON/EZPCS

TDI/DSI

TDO/DSO

TRST/DSCLK

ALLPST

TIN0/TOUT0

TIN1/TOUT1

IRQ8

PST0

PHY_VSSRX

PHY_VDDRX

PHY_RXN

PHY_RXP

PHY_VSSTX

PHY_TXN

PHY_TXP

PHY_VDDTX

PHY_VDDA

PHY_VSSA

PHY_RBIAS

VDD2

IRQ9

DDATA3

DDATA2

VDDX1

112-Lead LQFP

VSSX1

DDATA1

DDATA0

JTAG_EN

IRQ6

IRQ5

VSS2

TIN2/TOUT2

TIN3/TOUT3

U1_RTS

U1_CTS

U0_RTS

U0_CTS

SYNCB

U2_TXD

U2_RXD

U2_CTS

U2_RTS

DUPLED

COLLED

IRQ11

SYNCA

Figure 3. 112-Lead LQFP Pin Assignments

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Preliminary

Freescale Semiconductor

Table 3. Pin Functions by Primary and Alternate Purpose

Drive

Group

Primary

Function

Secondary

Function

Tertiary

Quaternary

Function

Wired OR

Control

Pull-up / Pin on121 Pinon112 Pin on 80

Strength/

Notes

Function

Pull-down²MAPBGA

LQFP

Control¹

ADC

AN7

AN6

—

PAN[0]

PAN[1]

PAN[2]

PAN[3]

PAN[4]

PAN[5]

PAN[6]

PAN[7]

PAS[3]

PAS[2]

—

Low

—

AN5

—

Low

—

AN4

—

Low

—

AN3

—

Low

—

AN2

—

Low

—

AN1

—

Low

—

AN0

—

Low

—

SYNCA

SYNCB

VDDA

VSSA

VRH

CANTX³

FEC_MDIO

PDSR[39]

N/A

—

CANRX³

FEC_MDC

—

N/A

—

N/A

—

N/A

VRL

—

N/A

Clock

Generation

EXTAL

XTAL

—

N/A

—

N/A

VDDPLL

VSSPLL

ALLPST

DDATA[3:0]

—

N/A

—

N/A

Debug

Data

—

High

PDD[7:4]

—

12,13,

16,17

—

PST[3:0]

—

PDD[3:0]

High

—

80,79,

78,77

—

Drive

Group

Primary

Function

Secondary

Function

Tertiary

Function

Quaternary

Function

Wired OR

Control

Pull-up / Pin on121 Pinon112 Pin on 80

Strength/

Notes

Pull-down²MAPBGA

LQFP

Control¹

Ethernet

LEDs

ACTLED

COLLED

—

PSD[0]

PSD[4]

PSD[3]

PSD[1]

PSD[2]

PSD[5]

PSD[6]

—

PDSR[32] PWOR[8]

PDSR[36] PWOR[12]

PDSR[35] PWOR[11]

PDSR[33] PWOR[9]

PDSR[34] PWOR[10]

PDSR[37] PWOR[13]

PDSR[38] PWOR[14]

—

111

112

—

DUPLED

—

LNKLED

—

SPDLED

—

RXLED

—

TXLED

—

Ethernet

PHY

PHY_RBIAS

PHY_RXN

PHY_RXP

PHY_TXN

PHY_TXP

PHY_VDDA

PHY_VDDRX

PHY_VDDTX

PHY_VSSA

PHY_VSSRX

PHY_VSSTX

SCL

—

N/A

—

I²C

CANTX³

CANRX³

TXD2

RXD2

PAS[1]

PAS[0]

PDSR[0]

pull-up⁴

SDA

—

Drive

Group

Primary

Function

Secondary

Function

Tertiary

Function

Quaternary

Function

Wired OR

Control

Pull-up / Pin on121 Pinon112 Pin on 80

Strength/

Notes

Pull-down²MAPBGA

LQFP

Control¹

Interrupts

IRQ15

IRQ14

IRQ13

IRQ12

IRQ11

IRQ10

IRQ9

—

PGP[7]

PGP[6]

PGP[5]

PGP[4]

PGP[3]

PGP[2]

PGP[1]

PGP[0]

PNQ[7]

PNQ[6]

PNQ[5]

PNQ[4]

PNQ[3]

PNQ[2]

PNQ[1]

—

PSDR[47]

PSDR[46]

PSDR[45]

PSDR[44]

PSDR[43]

PSDR[42]

PSDR[41]

PSDR[40]

Low

—

N/A

—

pull-up⁴

pull-down

pull-up⁵

—

106

105

—

IRQ8

—

IRQ7

—

IRQ6

FEC_RXER

FEC_RXD[1]

—

Low

IRQ5

—

Low

IRQ4

—

Low

IRQ3

—

FEC_RXD[2]

FEC_RXD[3]

PWM1

Low

IRQ2

—

Low

IRQ1

SYNCA

—

High

JTAG/BDM

JTAG_EN

—

N/A

TCLK/

CLKOUT

—

High

PSTCLK

TDI/DSI

—

N/A

High

N/A

pull-up⁵

—

TDO/DSO

TMS

pull-up⁵

/BKPT

TRST

/DSCLK

—

N/A

pull-up⁵

pull-up

—

Mode

Selection

RCON/

EZPCS

Drive

Group

Primary

Function

Secondary

Function

Tertiary

Function

Quaternary

Function

Wired OR

Control

Pull-up / Pin on121 Pinon112 Pin on 80

Strength/

Notes

Pull-down²MAPBGA

LQFP

Control¹

PWM

PWM7

PWM5

PWM3

PWM1

—

PTD[3]

PTD[2]

PTD[1]

PTD[0]

PQS[1]

PDSR[31]

PDSR[30]

PDSR[29]

PDSR[28]

PDSR[2]

—

104

103

100

—

QSPI

QSPI_DIN/

EZPD

CANRX³

RXD1

PWOR[4]

QSPI_DOUT/

EZPQ

CANTX³

SCL

TXD1

RTS1

PQS[0]

PQS[2]

PDSR[1]

PDSR[3]

PWOR[5]

PWOR[6]

—

QSPI_SCK/

EZPCK

pull-up⁶

QSPI_CS3

QSPI_CS2

QSPI_CS1

QSPI_CS0

RSTI

SYNCA

—

SYNCB

—

PQS[6]

PQS[5]

PQS[4]

PQS[3]

—

PDSR[7]

PDSR[6]

PDSR[5]

PDSR[4]

N/A

—

107

108

109

110

—

SDA

CTS1

—

PWOR[7]

N/A

pull-up⁶

pull-up⁷

—

Reset⁷

Test

—

RSTO

—

high

—

TEST

—

N/A

pull-down

pull-up⁸

—

Timers,

16-bit

GPT3

FEC_TXD[3]

FEC_TXD[2]

FEC_TXD[1]

FEC_TXER

TOUT3

TOUT2

TOUT1

TOUT0

PWM7

PWM5

PWM3

PWM1

PWM6

PWM4

PWM2

PWM0

PTA[3]

PTA[2]

PTA[1]

PTA[0]

PTC[3]

PTC[2]

PTC[1]

PTC[0]

PDSR[23] PWOR[23]

PDSR[22] PWOR[22]

PDSR[21] PWOR[21]

PDSR[20] PWOR[20]

PDSR[19] PWOR[19]

PDSR[18] PWOR[18]

PDSR[17] PWOR[17]

PDSR[16] PWOR[16]

GPT2

GPT1

GPT0

Timers,

32-bit

TIN3

TIN2

—

TIN1

—

TIN0

—

Drive

Group

Primary

Function

Secondary

Function

Tertiary

Function

Quaternary

Function

Wired OR

Control

Pull-up / Pin on121 Pinon112 Pin on 80

Strength/

Notes

Pull-down²MAPBGA

LQFP

Control¹

UART 0

UART 1

UART 2

FlexCAN

CTS0

RTS0

RXD0

TXD0

CTS1

RTS1

RXD1

TXD1

CTS2

RTS2

RXD2

TXD2

CANRX

CANTX

VDD

CANRX³

FEC_RXCLK

FEC_RXDV

FEC_RXD[0]

FEC_CRS

RXD2

PUA[3]

PUA[2]

PUA[1]

PUA[0]

PUB[3]

PUB[2]

PUB[1]

PUB[0]

PUC[3]

PUC[2]

PUC[1]

PUC[30]

PAS[3]

PAS[2]

—

PDSR[11]

PDSR[10]

PDSR[9]

PDSR[8]

PDSR[15]

PDSR[14]

—

CANTX³

—

PWOR[0]

PWOR[1]

—

SYNCA

SYNCB

—

TXD2

—

FEC_TXD[0]

FEC_COL

—

PDSR[13] PWOR[2]

PDSR[12] PWOR[3]

—

PDSR[27]

PDSR[26]

PDSR[25]

PDSR[24]

PDSR[39]

N/A

—

FEC_MDIO

FEC_MDC

—

See Note³

—

VDD⁹

VSS

—

N/A

14,43,65, 10,31,45,

82,102

58,74

VSS

—

N/A

—

15,42,

64,101

11,30,

44,73

NOTES:

The PDSR and PSSR registers are described in the MCF52235 Reference Manual. All programmable signals default to 2mA drive in normal (single-chip) mode.

All signals have a pull-up in GPIO mode.

The multiplexed CANTX and CANRX signals do not have dedicated pins, but are available as muxed replacements for other signals.

For primary and GPIO functions only.

Only when JTAG mode is enabled.

For secondary and GPIO functions only.

RSTI has an internal pull-up resistor, however the use of an external resistor is very strongly recommended

For GPIO function. Primary Function has pull-up control within the GPT module

This list for power and ground does not include those dedicated power/ground pins included elsewhere, e.g. in the ethernet PHY.

MCF52235 Family Configurations

1.5 Reset Signals

Table 4 describes signals that are used to either reset the chip or as a reset indication.

Table 4. Reset Signals

Signal Name

Abbreviation

Function

I/O

Reset In

RSTI

Primary reset input to the device. Asserting RSTI immediately resets

the CPU and peripherals.

Reset Out

RSTO

Driven low for 512 CPU clocks after the reset source has deasserted.

1.6 PLL and Clock Signals

Table 5 describes signals that are used to support the on-chip clock generation circuitry.

Table 5. PLL and Clock Signals

Signal Name

Abbreviation

Function

I/O

External Clock In

Crystal

EXTAL

XTAL

Crystal oscillator or external clock input.

Crystal oscillator output.

Clock Out

CLKOUT

This output signal reflects the internal system clock.

1.7 Mode Selection

Table 6 describes signals used in mode selection, Table 6 describes particular clocking modes.

Table 6. Mode Selection Signals

Signal Name

Abbreviation

Function

I/O

Reset Configuration

RCON

The Serial Flash Programming mode is entered by asserting the

RCON pin (with the TEST pin negated) as the chip comes out of

reset. During this mode, the EzPort has access to the Flash memory

which can be programmed from an external device.

Test

TEST

Reserved for factory testing only and in normal modes of operation

should be connected to VSS to prevent unintentional activation of

test functions.

1.8 External Interrupt Signals

Table 7 describes the external interrupt signals.

Table 7. External Interrupt Signals

Signal Name

Abbreviation

Function

I/O

External Interrupts

IRQ[15:1] External interrupt sources.

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Preliminary

Freescale Semiconductor

MCF52235 Family Configurations

1.9 Queued Serial Peripheral Interface (QSPI)

Table 8 describes QSPI signals.

Table 8. Queued Serial Peripheral Interface (QSPI) Signals

Signal Name

Abbreviation Function

I/O

QSPI Synchronous

Serial Output

QSPI_DOUT Provides the serial data from the QSPI and can be programmed to be

driven on the rising or falling edge of QSPI_CLK.

QSPI Synchronous

Serial Data Input

QSPI_DIN Provides the serial data to the QSPI and can be programmed to be

sampled on the rising or falling edge of QSPI_CLK.

QSPI Serial Clock

QSPI_CLK Provides the serial clock from the QSPI. The polarity and phase of

QSPI_CLK are programmable.

SynchronousPeripheral QSPI_CS[3:0] QSPI peripheral chip selects that can be programmed to be active

Chip Selects

high or low.

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Preliminary

Freescale Semiconductor

MCF52235 Family Configurations

1.10 Fast Ethernet Controller ePHY Signals

Table 9 describes the Fast Ethernet Controller (FEC) Signals.

Table 9. Fast Ethernet Controller (FEC) Signals

Signal Name

Abbreviation

Function

I/O

Twisted Pair Input +

RXP

Differential Ethernet twisted-pair input pin. This pin is high-impedance

out of reset.

Twisted Pair Input -

Twisted Pair Output +

Twisted Pair Output -

Bias Control Resistor

RXN

TXN

Differential Ethernet twisted-pair input pin. This pin is high-impedance

out of reset.

Differential Ethernet twisted-pair output pin. This pin is

high-impedance out of reset.

TXP

Differential Ethernet twisted-pair output pin. This pin is

high-impedance out of reset.

RBIAS

Connect a 12.4 kΩ (1.0%) external resistor, RBIAS, between the

PHY_RBIAS pin and analog ground.

Place this resistor as near to the chip pin as possible. Stray

capacitance must be kept to less than 10 pF

(>50 pF will cause instability). No high-speed signals can be permitted

in the region of RBIAS.

Activity LED

Link LED

ACT_LED

Indicates when the ePHY is transmitting or receiving

LINK_LED Indicates when the ePHY has a valid link

SPD_LED Indicates the speed of the ePHY connection

Speed LED

Duplex LED

Collision LED

Transmit LED

Receive LED

DUPLED

COLLED

TXLED

Indicates the duplex (full or half) of the ePHY connection

Indicates if the ePHY detects a collision

Indicates if the ePHY is transmitting

RXLED

Indicates if the ePHY is receiving

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Preliminary

Freescale Semiconductor

MCF52235 Family Configurations

1.11 I²C I/O Signals

Table 10 describes the I C serial interface module signals.

Table 10. I C I/O Signals

Signal Name

Abbreviation

Function

I/O

Serial Clock

SCL

Open-drain clock signal for the for the I²C interface. Either it is driven

by the I²C module when the bus is in master mode or it becomes the

clock input when the I²C is in slave mode.

I/O

Serial Data

SDA

Open-drain signal that serves as the data input/output for the I²C

interface.

I/O

1.12 UART Module Signals

Table 11 describes the UART module signals.

Table 11. UART Module Signals

Signal Name

Abbreviation

Function

I/O

Transmit Serial Data

Output

UTXDn

Transmitter serial data outputs for the UART modules. The output is

held high (mark condition) when the transmitter is disabled, idle, or in

the local loopback mode. Data is shifted out, LSB first, on this pin at

the falling edge of the serial clock source.

Receive Serial Data

Input

URXDn

Receiver serial data inputs for the UART modules. Data is received on

this pin LSB first. When the UART clock is stopped for power-down

mode, any transition on this pin restarts it.

Clear-to-Send

UCTSn

URTSn

Indicate to the UART modules that they can begin data transmission.

Request-to-Send

Automatic request-to-send outputs from the UART modules. This

signal can also be configured to be asserted and negated as a

function of the RxFIFO level.

1.13 DMA Timer Signals

Table 12 describes the signals of the four DMA timer modules.

Table 12. DMA Timer Signals

Signal Name

Abbreviation

Function

I/O

DMA Timer Input

DTIN

Event input to the DMA timer modules.

DMA Timer Output

DTOUT

Programmable output from the DMA timer modules.

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Preliminary

Freescale Semiconductor

MCF52235 Family Configurations

1.14 ADC Signals

Table 13 describes the signals of the Analog-to-Digital Converter.

Table 13. ADC Signals

Signal Name

Analog Inputs

Abbreviation

Function

Inputs to the A-to-D converter.

I/O

AN[7:0]

V_RH

Analog Reference

Reference voltage high and low inputs.

V_RL

Analog Supply

V_DDA

V_SSA

Isolate the ADC circuitry from power supply noise

—

1.15 General Purpose Timer Signals

Table 14 describes the General Purpose Timer Signals.

Table 14. GPT Signals

Signal Name

Abbreviation

Function

I/O

General Purpose Timer

Input/Output

GPT[3:0]

Inputs to or outputs from the general purpose timer module

I/O

1.16 Pulse Width Modulator Signals

Table 15 describes the PWM signals.

Table 15. PWM Signals

Signal Name

Abbreviation

Function

I/O

PWM Output Channels

PWM[7:0]

Pulse width modulated output for PWM channels

1.17 Debug Support Signals

These signals are used as the interface to the on-chip JTAG controller and also to interface to the BDM

logic.

Table 16. Debug Support Signals

Signal Name

Abbreviation

Function

I/O

JTAG Enable

Test Reset

JTAG_EN

TRST

Select between debug module and JTAG signals at reset

This active-low signal is used to initialize the JTAG logic

asynchronously.

Test Clock

TCLK

TMS

Used to synchronize the JTAG logic.

Test Mode Select

Used to sequence the JTAG state machine. TMS is sampled on the

rising edge of TCLK.

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Preliminary

Freescale Semiconductor

MCF52235 Family Configurations

Table 16. Debug Support Signals (continued)

Abbreviation Function

Signal Name

I/O

Test Data Input

TDI

Serial input for test instructions and data. TDI is sampled on the rising

edge of TCLK.

Test Data Output

TDO

Serial output for test instructions and data. TDO is tri-stateable and is

actively driven in the shift-IR and shift-DR controller states. TDO

changes on the falling edge of TCLK.

Development Serial

Clock

DSCLK

Development Serial Clock-Internally synchronized input. (The logic

level on DSCLK is validated if it has the same value on two

consecutive rising bus clock edges.) Clocks the serial communication

port to the debug module during packet transfers. Maximum frequency

is PSTCLK/5. At the synchronized rising edge of DSCLK, the data

input on DSI is sampled and DSO changes state.

Breakpoint

BKPT

Breakpoint - Input used to request a manual breakpoint. Assertion of

BKPT puts the processor into a halted state after the current

instruction completes. Halt status is reflected on processor status

signals () as the value 0xF.

Development Serial

Input

DSI

Development Serial Input -Internally synchronized input that provides

data input for the serial communication port to the debug module,

once the DSCLK has been seen as high (logic 1).

Development Serial

Output

DSO

Development Serial Output -Provides serial output communication for

debug module responses. DSO is registered internally. The output is

delayed from the validation of DSCLK high.

Debug Data

DDATA[3:0] Display captured processor data and breakpoint status. The CLKOUT

signal can be used by the development system to know when to

sample DDATA[3:0].

Processor Status Clock

PSTCLK

Processor Status Clock - Delayed version of the processor clock. Its

rising edge appears in the center of valid PST and DDATA output.

PSTCLK indicates when the development system should sample PST

and DDATA values.

If real-time trace is not used, setting CSR[PCD] keeps PSTCLK, and

PST and DDATA outputs from toggling without disabling triggers.

Non-quiescent operation can be reenabled by clearing CSR[PCD],

although the external development systems must resynchronize with

the PST and DDATA outputs.

PSTCLK starts clocking only when the first non-zero PST value (0xC,

0xD, or 0xF) occurs during system reset exception processing.

Processor Status

Outputs

PST[3:0]

ALLPST

Indicate core status. Debug mode timing is synchronous with the

processor clock; status is unrelated to the current bus transfer. The

CLKOUT signal can be used by the development system to know

when to sample PST[3:0].

All Processor Status

Outputs

Logical “AND” of PST[3.0]

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Preliminary

Freescale Semiconductor

MCF52235 Family Configurations

1.18 EzPort Signal Descriptions

Table 17 contains a list of EzPort external signals

Table 17. EzPort Signal Descriptions

Abbreviation Function

EZPCK Shift clock for EzPort transfers

Signal Name

I/O

EzPort Clock

EzPort Chip Select

EZPCS

EZPD

EZPQ

Chip select for signalling the start and end

of serial transfers

EzPort Serial Data In

EzPort Serial Data Out

EZPD is sampled on the rising edge of

EZPCK

EZPQ transitions on the falling edge of

EZPCK

1.19 Power and Ground Pins

The pins described in Table 18 provide system power and ground to the chip. Multiple pins are provided

for adequate current capability. All power supply pins must have adequate bypass capacitance for

high-frequency noise suppression.

Table 18. Power and Ground Pins

Signal Name

Abbreviation

Function

I/O

PLL Analog Supply

VDDPLL,

VSSPLL

Dedicated power supply signals to isolate the sensitive PLL analog

circuitry from the normal levels of noise present on the digital power

supply.

Positive Supply

Ground

VDD

VSS

These pins supply positive power to the core logic.

This pin is the negative supply (ground) to the chip.

Some of the V and V pins on the device are only to be used for noise bypass. Figure 4 shows a typical

connection diagram. Pay particular attention to those pins which show only capacitor connections. Do not

connect power supply voltage directly to these pins.

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Freescale Semiconductor

Preliminary

Preliminary Electrical Characteristics

V_DDPLL

V_SSPLL

V_DDA

V_RH

0.22µF

0.1µF

1000pF

10µF

0.1µF

10V

10µH

Tantalum

V_RL

V_SSA

V_DDR

V_SSX1

V_DDX1

V_DDX2

V_SSX2

V_DD2

0.1µF

3.3V

MCF52235

0.1µF

Pin numbering is shown

for the 80-lead TQFP

0.22µF

V_SS2

V_DD1

V_SS1

0.22µF 0.22µF 0.22µF

12.4KΩ

optional

Figure 4. Suggested connection scheme for Power and Ground

2 Preliminary Electrical Characteristics

This section contains electrical specification tables and reference timing diagrams for the MCF52235

microcontroller unit. This section contains detailed information on power considerations, DC/AC

electrical characteristics, and AC timing specifications of MCF52235.

The electrical specifications are preliminary and are from previous designs or design simulations. These

specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however

for production silicon these specifications will be met. Finalized specifications will be published after

complete characterization and device qualifications have been completed.

NOTE

The parameters specified in this appendix supersede any values found in the

module specifications.

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Freescale Semiconductor

Preliminary

Preliminary Electrical Characteristics

2.1 Maximum Ratings

1, 2

Table 19. Absolute Maximum Ratings

Rating

Symbol

Value

Unit

Supply Voltage

V_DD

V_DDPLL

V_STBY

V_IN

– 0.3 to +4.0

– 0.3 to + 4.0

0 to 3.3

Clock Synthesizer Supply Voltage

RAM Memory Standby Supply Voltage

Digital Input Voltage ³

EXTAL pin voltage

V_EXTAL

V_XTAL

XTAL pin voltage

0 to 3.3

Instantaneous Maximum Current

I_DD

Single pin limit (applies to all pins) ^{4, 5}

Operating Temperature Range (Packaged)

T_A

– 40 to 85

°C

(T_L- T_H)

Storage Temperature Range

N₁OTES:

T_stg

– 65 to 150

°C

Functional operating conditions are given in DC Electrical Specifications. Absolute Maximum

Ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress

beyond those listed may affect device reliability or cause permanent damage to the device.

This device contains circuitry protecting against damage due to high static voltage or electrical

fields; however, it is advised that normal precautions be taken to avoid application of any voltages

higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is

enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either V_SSor V_DD).

Input must be current limited to the I_DDvalue specified. To determine the value of the required

current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then

use the larger of the two values.

All functional non-supply pins are internally clamped to V_SSand V_DD

Power supply must maintain regulation within operating V_DDrange during instantaneous and

operating maximum current conditions. If positive injection current (V_in> V_DD) is greater than I_DD

the injection current may flow out of V_DDand could result in external power supply going out of

regulation. Insure external V_DDload will shunt current greater than maximum injection current. This

will be the greatest risk when the MCU is not consuming power (ex; no clock).Power supply must

maintain regulation within operating V_DDrange during instantaneous and operating maximum

current conditions.

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Freescale Semiconductor

Preliminary

Preliminary Electrical Characteristics

Table 20 lists thermal resistance values

Table 20. Thermal Characteristics

Characteristic

Symbol

Value

Unit

Junction to ambient, natural convection

Junction to ambient (@200 ft/min)

112 LQFP

Four layer board (2s2p)

θ_JMA

TBD^1,2

°C/W

112 LQFP

θ_JMA

TBD

°C/W

Four layer board (2s2p)

Junction to board

112 LQFP

θ_JB

θ_JC

Ψ_jt

T_j

TBD³

TBD⁴

TBD⁵

105

°C/W

^oC

Junction to case

112 LQFP

Junction to top of package

Maximum operating junction temperature

N₁OTES:

Natural convection

112 LQFP

_JMAand Ψ_jtparameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection.

Freescale recommends the use of θ_JmAand power dissipation specifications in the system design to prevent

device junction temperatures from exceeding the rated specification. System designers should be aware that

device junction temperatures can be significantly influenced by board layout and surrounding devices.

Conformance to the device junction temperature specification can be verified by physical measurement in the

customer’s system using the Ψ_jtparameter, the device power dissipation, and the method described in EIA/JESD

Standard 51-2.

Per JEDEC JESD51-6 with the board horizontal.

Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board

temperature is measured on the top surface of the board near the package.

Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL

SPEC-883 Method 1012.1).

Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter

is written in conformance with Psi-JT.

The average chip-junction temperature (T_J) in °C can be obtained from:

(1)

)

T_J= T_A+ (P_D× Θ_JMA

Where:

T_A

= Ambient Temperature, °C

Θ_JMA

P_D

= Package Thermal Resistance, Junction-to-Ambient, °C/W

= P_INT+ P_I/O

P_INT

P_I/O

= I_DD× V_DD, Watts - Chip Internal Power

= Power Dissipation on Input and Output Pins — User Determined

For most applications P_I/O< P_INTand can be ignored. An approximate relationship between P_Dand T_J(if P_I/Ois

neglected) is:

P_D= K ÷ (T_J+ 273°C)

(2)

Solving equations 1 and 2 for K gives:

K = P_D× (T_A+ 273 °C) + Θ_JMA× P_D

(3)

where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring P_D(at

equilibrium) for a known T_A. Using this value of K, the values of P_Dand T_Jcan be obtained by solving equations (1)

and (2) iteratively for any value of T_A.

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Freescale Semiconductor

Preliminary

Preliminary Electrical Characteristics

2.2 ESD Protection

1, 2

Table 21. ESD Protection Characteristics

Characteristics

Symbol

Value

Units

ESD Target for Human Body Model

ESD Target for Machine Model

HBM Circuit Description

HBM

2000

200

1500

100

R_series

ohms

MM Circuit Description

R_series

ohms

200

Number of pulses per pin (HBM)

positive pulses

negative pulses

—

Number of pulses per pin (MM)

positive pulses

negative pulses

—

Interval of Pulses

N₁OTES:

—

sec

All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for

Automotive Grade Integrated Circuits.

A device is defined as a failure if after exposure to ESD pulses the device no longer meets

the device specification requirements. Complete DC parametric and functional testing is

performed per applicable device specification at room temperature followed by hot

temperature, unless specified otherwise in the device specification.

2.3 DC Electrical Specifications

Table 22. DC Electrical Specifications

Characteristic

Symbol

Min

Max

Unit

Supply Voltage

V_DD

V_IH

3.0

3.6

4.0

Input High Voltage

Input Low Voltage

Input Hysteresis

0.7 x V_DD

V_SS– 0.3

0.06 x V_DD

–1.0

V_IL

0.35 x V_DD

—

V_HYS

I_in

µA

Input Leakage Current

1.0

V_in= V_DDor V_SS, Input-only pins

High Impedance (Off-State) Leakage Current

V_in= V_DDor V_SS, All input/output and output pins

I_OZ

V_OH

V_OL

–1.0

O V_DD- 0.5

1.0

µA

Output High Voltage (All input/output and all output pins)

I_OH= –2.0 mA

Output Low Voltage (All input/output and all output pins)

I_OL= 2.0mA

0.5

Weak Internal Pull Up Device Current, tested at V_ILMax.²

Input Capacitance ³

I_APU

C_in

-10

- 130

µA

All input-only pins

All input/output (three-state) pins

—

Load Capacitance⁴

Low Drive Strength

High Drive Strength

C_L

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Preliminary

Freescale Semiconductor

Preliminary Electrical Characteristics

Table 22. DC Electrical Specifications (continued)

Characteristic

Symbol

Min

Max

Unit

Operating Supply Current ⁵

I_DD

Master Mode

WAIT

DOZE

—

TBD

µA

STOP

3, 6, 7, 8

DC Injection Current

I_IC

V_NEGCLAMP=V_SS– 0.3 V, V_POSCLAMP= V_DD+ 0.3

Single Pin Limit

Total MCU Limit, Includes sum of all stressed pins

-1.0

-10

1.0

NOTES:

Refer to Table 23 for additional PLL specifications.

Refer to the MCF52235 signals chapter for pins having weak internal pull-up devices.

This parameter is characterized before qualification rather than 100% tested.

pF load ratings are based on DC loading and are provided as an indication of driver strength. High speed interfaces

require transmission line analysis to determine proper drive strength and termination.

Current measured at maximum system clock frequency, all modules active, and default drive strength with matching

load.

All functional non-supply pins are internally clamped to V_SSand their respective V_DD

Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,

calculate resistance values for positive and negative clamp voltages, then use the larger of the two values.

Power supply must maintain regulation within operating V_DDrange during instantaneous and operating maximum

current conditions. If positive injection current (V_in> V_DD) is greater than I_DD, the injection current may flow out of V_DD

and could result in external power supply going out of regulation. Insure external V_DDload will shunt current greater

than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if

no system clock is present, or if clock rate is very low which would reduce overall power consumption. Also, at

power-up, system clock is not present during the power-up sequence until the PLL has attained lock.

2.4 Phase Lock Loop Electrical Specifications

Table 23. PLL Electrical Specifications

(V_DDand V_DDPLL= 2.7 to 3.6 V, V_SS= V_SSPLL= 0 V)

Characteristic

Symbol

Min

Max

Unit

PLL Reference Frequency Range¹

Crystal reference

MHz

f_{ref_crystal}

f_{ref_ext}

10.0

External reference

System Frequency ²

External Clock Mode

On-Chip PLL Frequency

f_sys

MHz

f_ref/ 32

Loss of Reference Frequency ^{3, 5}

Self Clocked Mode Frequency ^{4, 5}

Crystal Start-up Time ^{5, 6}

f_LOR

f_SCM

t_cst

100

1000

kHz

MHz

—

EXTAL Input High Voltage

Crystal reference

External reference

V_IHEXT

V_DD- 1.0

2.0

V_DD

EXTAL Input Low Voltage

Crystal reference

External reference

V_ILEXT

V_SS

1.0

0.8

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Preliminary

Freescale Semiconductor

Preliminary Electrical Characteristics

Table 23. PLL Electrical Specifications (continued)

(V_DDand V_DDPLL= 2.7 to 3.6 V, V_SS= V_SSPLL= 0 V)

Characteristic

Symbol

Min

Max

Unit

XTAL Output High Voltage

I_OH= 1.0 mA

V_OL

V_DD- 1.0

—

XTAL Output Low Voltage

I_OL= 1.0 mA

XTAL Load Capacitance⁷

PLL Lock Time^5,9

V_OL

—

0.5

—

t_lpll

500

µs

Power-up To Lock Time ^{5, 7,8}

With Crystal Reference

Without Crystal Reference

t_lplk

—

10.5

500

µs

Duty Cycle of reference ⁵

Frequency un-LOCK Range

Frequency LOCK Range

t_dc

1.5

% f_sys

f_UL

- 1.5

- 0.75

fLCK

C_jitter

0.75

% % f_sys

CLKOUT Period Jitter ^{5, 6, 8, 9,10}, Measured at f_SYSMax

Peak-to-peak Jitter (Clock edge to clock edge)

Long Term Jitter (Averaged over 2 ms interval)

—

.01

% f_sys

N₁OTES:

Input to the PLL is limited to 10MHz max, however the PLL divider can accept up to 40MHz. The input must be

divided down to a frequency no greater than 10MHz. This is controlled by register CCHR.

All internal registers retain data at 0 Hz.

“Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self

clocked mode.

Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below

f_LORwith default MFD/RFD settings.

This parameter is characterized before qualification rather than 100% tested.

Proper PC board layout procedures must be followed to achieve specifications.

Load Capacitance determined from crystal manufacturer specifications and will include circuit board parasitics.

Assuming a reference is available at power up, lock time is measured from the time V_DDand V_DDPLLare valid to

RSTO negating. If the crystal oscillator is being used as the reference for the PLL, then the crystal start up time must

be added to the PLL lock time to determine the total start-up time.

Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum

f_sys. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock

signal. Noise injected into the PLL circuitry via V_DDPLLand V_SSPLLand variation in crystal oscillator frequency

increase the Cjitter percentage for a given interval

Based on slow system clock of 40 MHz measured at f_sysmax.

2.5 General Purpose I/O Timing

GPIO can be configured for certain pins of the QSPI, TIMERS, UARTS, FEC, Interrupts and USB

interfaces. When in GPIO mode, the timing specification for these pins is given in Table 24 and Figure 5.

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Freescale Semiconductor

Preliminary

Table 24. GPIO Timing

NUM

Characteristic

Symbol

Min

Max

Unit

CLKOUT High to GPIO Output Valid

CLKOUT High to GPIO Output Invalid

GPIO Input Valid to CLKOUT High

CLKOUT High to GPIO Input Invalid

t_CHPOV

t_CHPOI

t_PVCH

t_CHPI

1.5

CLKOUT

GPIO Outputs

GPIO Inputs

Figure 5. GPIO Timing

2.6 Reset Timing

Table 25. Reset and Configuration Override Timing

(V_DD= 2.7 to 3.6 V, V_SS= 0 V, T_A= T_Lto T_H)¹

NUM

Characteristic

Symbol

Min

Max

Unit

R1 RSTI Input valid to CLKOUT High

R2 CLKOUT High to RSTI Input invalid

R3 RSTI Input valid Time ²

t_RVCH

t_CHRI

1.5

t_RIVT

t_CYC

R4 CLKOUT High to RSTO Valid

t_CHROV

N₁OTES:

All AC timing is shown with respect to 50% O V_DDlevels unless otherwise noted.

During low power STOP, the synchronizers for the RSTI input are bypassed and RSTI is asserted asynchronously to

the system. Thus, RSTI must be held a minimum of 100 ns.

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Freescale Semiconductor

Preliminary

Preliminary Electrical Characteristics

CLKOUT

1R1

RSTI

RSTO

Figure 6. RSTI and Configuration Override Timing

2.7 I²C Input/Output Timing Specifications

Table 26 lists specifications for the I C input timing parameters shown in Figure 7.

Table 26. I C Input Timing Specifications between I2C_SCL and I2C_SDA

Num

Characteristic

Start condition hold time

Min

Max

Units

2 x t_CYC

8 x t_CYC

—

Clock low period

SCL/SDA rise time (V_IL= 0.5 V to V_IH= 2.4 V)

Data hold time

—

SCL/SDA fall time (V_IH= 2.4 V to V_IL= 0.5 V)

Clock high time

—

4 x t_CYC

—

Data setup time

Start condition setup time (for repeated start condition only)

Stop condition setup time

2 x t_CYC

Table 27 lists specifications for the I C output timing parameters shown in Figure 7.

Table 27. I C Output Timing Specifications between I2C_SCL and I2C_SDA

Num

Characteristic

Start condition hold time

Min

Max

Units

11¹

I2 ¹

I3 ²

6 x t_CYC

10 x t_CYC

—

µS

Clock low period

I2C_SCL/I2C_SDA rise time

(V_IL= 0.5 V to V_IH= 2.4 V)

I4 ¹

I5 ³

Data hold time

7 x t_CYC

—

I2C_SCL/I2C_SDA fall time

(V_IH= 2.4 V to V_IL= 0.5 V)

I6 ¹

I7 ¹

Clock high time

Data setup time

10 x t_CYC

2 x t_CYC

—

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Preliminary

Freescale Semiconductor

Preliminary Electrical Characteristics

Table 27. I C Output Timing Specifications between I2C_SCL and I2C_SDA (continued)

Num

Characteristic

Min

Max

Units

I8 ¹

Start condition setup time (for repeated start

condition only)

20 x t_CYC

—

I9 ¹

Stop condition setup time

10 x t_CYC

—

NOTES:

Note: Output numbers depend on the value programmed into the IFDR; an IFDR programmed with

the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table 27. The

I²C interface is designed to scale the actual data transition time to move it to the middle of the SCL

low period. The actual position is affected by the prescale and division values programmed into the

IFDR; however, the numbers given in Table 27 are minimum values.

Because SCL and SDA are open-collector-type outputs, which the processor can only actively drive

low, the time SCL or SDA take to reach a high level depends on external signal capacitance and

pull-up resistor values.

Specified at a nominal 50-pF load.

Figure 7 shows timing for the values in Table 26 and Table 27.

SCL

SDA

Figure 7. I C Input/Output Timings

2.8 Analog-to-Digital Converter (ADC) Parameters

Table 28 lists specifications for the analog-to-digital converter.

Table 28. ADC Parameters

Name

Characteristic

Min

Typical

Max

Unit

V_ADIN

Input voltages

Resolution

—

V_REFH

V_REFL

R_ES

INL

—

Bits

LSB³

LSB

Integral Non-Linearity (Full input signal range)²

2.5

Integral Non-Linearity (10% to 90% input signal

range)⁴

DNL

Differential Non-Linearity

Monotonicity

—

-1 < DNL < +1

<+1

LSB

GUARANTEED

f_ADIC

R_AD

ADC internal clock

Conversion Range

0.1

—

5.0

MHz

V_REFL

V_REFH

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Preliminary

Freescale Semiconductor

Preliminary Electrical Characteristics

Table 28. ADC Parameters (continued)

Name

Characteristic

ADC power-up time⁵

Min

Typical

Max

Unit

t_ADPU

t_REC

t_ADC

t_ADS

C_ADI

X_IN

—

t_AICcycles⁶

Recovery from auto standby

Conversion time

—

t_AICcycles

—

t_AICcycles

Sample time

t_AICcycles

Input capacitance

Input impedance

TBD

—

Ω

I_ADI

Input injection current⁷, per pin

—

I_VREFH

V_REFHcurrent

—

V_OFFSETOffset voltage internal reference

E_GAINGain Error (transfer path)

V_OFFSETOffset voltage external reference

—

.99

1.01

TBD

—

Bits

SNR

THD

Signal-to-Noise ratio

TBD

9.1

62 to 66

-75

Total Harmonic Distortion

Spurious Free Dynamic Range

Signal-to-Noise plus Distortion

Effective Number OF Bits

SFDR

SINAD

ENOB

10.6

NOTES:

All measurements are preliminary pending full characterization, and were made at V_DD= 3.3V, V_REFH= 3.3V, and V_REFL

ground

INL measured from V_IN= V_REFLto V_IN= V_REFH

LSB = Least Significant Bit

INL measured from V_IN= 0.1V_REFHto V_IN= 0.9V_REFH

Includes power-up of ADC and V_REF

ADC clock cycles

The current that can be injected or sourced from an unselected ADC signal input without impacting the performance of the

ADC

2.9 DMA Timers Timing Specifications

Table 29 lists timer module AC timings.

Table 29. Timer Module AC Timing Specifications

Name

Characteristic ¹

Min

Max

Unit

DTIN0 / DTIN1 / DTIN2 / DTIN3 cycle time

DTIN0 / DTIN1 / DTIN2 / DTIN3 pulse width

3 x t_CYC

1 x t_CYC

—

N₁OTES:

All timing references to CLKOUT are given to its rising edge.

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Preliminary

Freescale Semiconductor

Preliminary Electrical Characteristics

2.10 QSPI Electrical Specifications

Table 30 lists QSPI timings.

Table 30. QSPI Modules AC Timing Specifications

Characteristic

Name

Min

Max

Unit

QS1

QS2

QS3

QS4

QS5

QSPI_CS[3:0] to QSPI_CLK

—

510

—

t_CYC

QSPI_CLK high to QSPI_DOUT valid.

QSPI_CLK high to QSPI_DOUT invalid (Output hold)

QSPI_DIN to QSPI_CLK (Input setup)

QSPI_DIN to QSPI_CLK (Input hold)

—

The values in Table 30 correspond to Figure 8.

QS1

QSPI_CS[3:0]

QSPI_CLK

QS2

QSPI_DOUT

QS3

QS4

QS5

QSPI_DIN

Figure 8. QSPI Timing

2.11 JTAG and Boundary Scan Timing

Table 31. JTAG and Boundary Scan Timing

Num

Characteristics¹

TCLK Frequency of Operation

Symbol

Min

Max

Unit

f_JCYC

t_JCYC

t_JCW

1/4

f_sys/2

TCLK Cycle Period

4 x t_CYC

TCLK Clock Pulse Width

TCLK Rise and Fall Times

t_JCRF

t_BSDST

t_BSDHT

Boundary Scan Input Data Setup Time to TCLK Rise

Boundary Scan Input Data Hold Time after TCLK Rise

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Preliminary

Freescale Semiconductor

Preliminary Electrical Characteristics

Table 31. JTAG and Boundary Scan Timing (continued)

Num

Characteristics¹

Symbol

Min

Max

Unit

TCLK Low to Boundary Scan Output Data Valid

TCLK Low to Boundary Scan Output High Z

TMS, TDI Input Data Setup Time to TCLK Rise

TMS, TDI Input Data Hold Time after TCLK Rise

TCLK Low to TDO Data Valid

t_BSDV

t_BSDZ

t_TAPBST

t_TAPBHT

t_TDODV

t_TDODZ

t_TRSTAT

t_TRSTST

J10

J11

J12

J13

J14

TCLK Low to TDO High Z

TRST Assert Time

100

TRST Setup Time (Negation) to TCLK High

NOTES:

JTAG_EN is expected to be a static signal. Hence, it is not associated with any timing.

V_IH

TCLK

(input)

V_IL

Figure 9. Test Clock Input Timing

TCLK

V_IL

V_IH

Data Inputs

Input Data Valid

Data Outputs

Output Data Valid

Data Outputs

Output Data Valid

Figure 10. Boundary Scan (JTAG) Timing

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Preliminary

Freescale Semiconductor

Preliminary Electrical Characteristics

TCLK

V_IL

V_IH

Input Data Valid

J10

TDI

TMS

J11

TDO

Output Data Valid

J12

J11

TDO

Output Data Valid

Figure 11. Test Access Port Timing

TCLK

TRST

Figure 12. TRST Timing

2.12 Debug AC Timing Specifications

Table 32 lists specifications for the debug AC timing parameters shown in Figure 14.

Table 32. Debug AC Timing Specification

60 MHz

Num

Characteristic

Units

Min

Max

PSTCLK cycle time

0.5

t_CYC

PST, DDATA to CLKOUT setup

CLKOUT to PST, DDATA hold

DSI-to-DSCLK setup

1.5

1 x t_CYC

4 x t_CYC

5 x t_CYC

D4 ¹

DSCLK-to-DSO hold

DSCLK cycle time

BKPT input data setup time to CLKOUT Rise

BKPT input data hold time to CLKOUT Rise

CLKOUT high to BKPT high Z

1.5

0.0

10.0

N₁OTES:

DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input relative

to the rising edge of CLKOUT.

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Freescale Semiconductor

Preliminary

Preliminary Electrical Characteristics

Figure 13 shows real-time trace timing for the values in Table 32.

CLKOUT

PST[3:0]

DDATA[3:0]

Figure 13. Real-Time Trace AC Timing

Figure 14 shows BDM serial port AC timing for the values in Table 32.

CLKOUT

DSCLK

DSI

Current

Past

DSO

Current

Figure 14. BDM Serial Port AC Timing

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Preliminary

Freescale Semiconductor

Mechanical Outline Drawings

3 Mechanical Outline Drawings

This section describes the physical properties of the MCF52235 and its derivatives.

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Freescale Semiconductor

Preliminary

Mechanical Outline Drawings

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Preliminary

Freescale Semiconductor

Mechanical Outline Drawings

MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0

Preliminary

Freescale Semiconductor

How to Reach Us:

Home Page:

www.freescale.com

E-mail:

support@freescale.com

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Technical Information Center, CH370

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Chandler, Arizona 85224

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MCF52233 [FREESCALE]

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