MCF5275_技术文档

Document Number: MCF5275EC

Rev. 2, 08/2006

Freescale Semiconductor

Hardware Specification

MCF5275 Integrated

Microprocessor Family Hardware

Specification

by: Microcontroller Division

Contents

The MCF5275 family is a highly integrated

implementation of the ColdFire family of reduced

®

1

2

3

4

5

6

7

8

9

MCF5275 Family Configurations. . . . . . . . . . . . . . . . . . . 2

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Design Recommendations . . . . . . . . . . . . . . . . . . . . . . . 9

Mechanicals/Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Preliminary Electrical Characteristics . . . . . . . . . . . . . . 18

Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

instruction set computing (RISC) microprocessors. This

document describes pertinent features and functions

characteristics of the MCF5275 family. The MCF5275

family includes the MCF5275, MCF5275L, MCF5274

and MCF5274L microprocessors. The differences

between these parts are summarized in Table 1. This

document is written from the perspective of the

MCF5275 and unless otherwise noted, the information

applies also to the MCF5275L, MCF5274 and

MCF5274L.

10 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

The MCF5275 family delivers a new level of

performance and integration on the popular version 2

ColdFire core with up to 159 (Dhrystone 2.1) MIPS @

166MHz. These highly integrated microprocessors build

upon the widely used peripheral mix on the popular

MCF5272 ColdFire microprocessor (10/100 Mbps

Ethernet MAC and USB device) by adding a second

10/100 Mbps Ethernet MAC (MCF5274 and MCF5275)

and hardware encryption (MCF5275L and MCF5275).

• Preliminary—Subject to Change Without Notice

MCF5275 Family Configurations

In addition, the MCF5275 family features an enhanced multiply accumulate unit (EMAC), large on-chip

memory (64 Kbytes SRAM, 16 Kbytes configurable cache), and a 16-bit DDR SDRAM memory

controller.

These devices are ideal for cost-sensitive applications requiring significant control processing for file

management, connectivity, data buffering, and user interface, as well as signal processing in a variety of

key markets such as security, imaging, networking, gaming, and medical. This leading package of

integration and high performance allows fast time to market through easy code reuse and extensive third

party tool support.

To locate any published errata or updates for this document, refer to the ColdFire products website at

http://www.freescale.com/coldfire.

1

MCF5275 Family Configurations

Table 1. MCF5275 Family Configurations

Module

MCF5274L MCF5275L MCF5274

MCF5275

ColdFire Version 2 Core with EMAC (Enhanced Multiply-Accumulate Unit)

x

System Clock

up to 166 MHz

Performance (Dhrystone 2.1 MIPS)

Instruction/Data Cache

Static RAM (SRAM)

up to 159

16 Kbytes (configurable)

64 Kbytes

Interrupt Controllers (INTC)

Edge Port Module (EPORT)

External Interface Module (EIM)

4-channel Direct-Memory Access (DMA)

DDR SDRAM Controller

Fast Ethernet Controller (FEC)

Watchdog Timer Module (WDT)

4-channel Programmable Interval Timer Module (PIT)

32-bit DMA Timers

2

x

2

x

1

x

4

x

3

x

4

x

2

x

2

x

2

x

4

x

3

x

4

x

1

x

2

x

4

x

4

x

USB

QSPI

x

UART(s)

3

x

3

x

I²C

PWM

4

x

4

x

General Purpose I/O Module (GPIO)

CIM = Chip Configuration Module + Reset Controller Module

Debug BDM

x

JTAG - IEEE 1149.1 Test Access Port

Hardware Encryption

x

—

Package

196 MAPBGA 196 MAPBGA 256 MAPBGA 256 MAPBGA

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

2

Preliminary—Subject to Change Without Notice

Block Diagram

2

Block Diagram

The superset device in the MCF5275 family comes in a 256 Mold Array Plastic Ball Grid Array

(MAPBGA) package.

Figure 1 shows a top-level block diagram of the MCF5275, the superset device.

EIM

DDR

CHIP

SELECTS

(To/From SRAM backdoor)

QSPI

I2C_SDA

I2C_SCL

TXDx

EBI

INTC0 INTC1

RXDx

Arbiter

RTSx

CTSx

DTOUTx

DTINx

FAST ETHERNET

CONTROLLER

(FEC0)

(To/From PADI)

FEC0

FEC1

USB

UART

0

UART UART

I²C

QSPI

FAST ETHERNET

CONTROLLER

(FEC1)

1

2

SDRAMC

PWMx

D[31:16]

A[23:0]

DTIM

3

DTIM DTIM

DTIM

0

1

2

(To/From

PADI)

R/

W

4 CH DMA

DREQ[1:0]

CS[3:0]

TA

JTAG_EN

TRST

V2 ColdFire CPU

DACK[3:0]

JTAG

TAP

TCLK

EMAC

DIV

TMS

TDI

TDO

JTAG_EN

TSIZ[1:0]

TEA

64 Kbytes

SRAM

(8Kx16)x4

(To/From

PADI)

16 Kbytes

CACHE

(1Kx32)x4

BS[3:2]

4 CH PWM

(To/From PADI)

PORTS

(GPIO)

CIM

Watchdog

Timer

(To/From Arbiter backdoor)

PLL

CLKGEN

USB 2.0

Full Speed

PIT0

PIT1

PIT2

PIT3

Edge

Port

MDHA

RNGA

SKHA

Cryptography

Modules

(To/From INTC)

(To/From PADI)

Figure 1. MCF5275 Block Diagram

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

3

Preliminary—Subject to Change Without Notice

Features

3

Features

For a detailed feature list see the MCF5275 Reference Manual (MCF5275RM).

4

Signal Descriptions

This section describes signals that connect off chip, including a table of signal properties. For a more

detailed discussion of the MCF5275 signals, consult the MCF5275 Reference Manual (MCF5275RM).

Table 2 lists the signals for the MCF5275 in functional group order. The “Dir” column is the direction for

the primary function of the pin. Refer to Section 6, “Mechanicals/Pinouts,” for package diagrams.

NOTE

In this table and throughout this document a single signal within a group is

designated without square brackets (i.e., A24), while designations for

multiple signals within a group use brackets (i.e., A[23:21]) and is meant to

include all signals within the two bracketed numbers when these numbers

are separated by a colon.

NOTE

The primary functionality of a pin is not necessarily its default functionality.

Pins that are muxed with GPIO will default to their GPIO functionality.

Table 2. MCF5274 and MCF5275 Signal Information and Muxing

MCF5274

MCF5275

MCF5274L

MCF5275L

Signal Name

GPIO

Alternate1 Alternate2 Dir.¹

256 MAPBGA 196 MAPBGA

Reset

RESET

—

I

N15

N14

K12

L12

RSTOUT

O

Clock

EXTAL

XTAL

—

I

L16

M16

T12

M14

N14

P9

O

CLKOUT

Mode Selection

CLKMOD[1:0]

RCON

—

I

N13, P13

P8

M11, N11

M6

External Memory Interface and Ports

PADDR[7:5] CS[6:4] A11, B11, C11

A[23:21]

—

O

A8, B8, C8

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

4

Preliminary—Subject to Change Without Notice

Signal Descriptions

Table 2. MCF5274 and MCF5275 Signal Information and Muxing (continued)

MCF5274

MCF5275

MCF5274L

MCF5275L

Signal Name

GPIO

Alternate1 Alternate2 Dir.¹

256 MAPBGA 196 MAPBGA

A[20:0]

—

O

A12, B12, C12, B9, D9, C9,

A13, B13, C13, C10, B10, A11,

A14, B14, C14, C11, B11, A12,

B15, C15, B16, D11, C12, B13,

C16, D14, D15, C13, D12, E11,

E14:16, F14:16 D13, E12, F11,

D14, E13, F13

D[31:16]

—

O

M1, N1, N2, N3, J3, L1, K2, K3,

P1, P2, R1, R2, M1, L2, L3, L4,

P3, R3, T3, N4, K4, J4, M2, N1,

P4, R4, T4, N5 N2, M3, M4, N3

BS[3:2]

OE

PBS[3:2]

CAS[3:2]

—

O

I

M3, R5

K1

K1, L5

H4

PBUSCTL[7]

PBUSCTL[6]

PBUSCTL[5]

PBUSCTL[4]

PBUSCTL[3]

PBUSCTL[2]

PBUSCTL[1]

PBUSCTL[0]

TA

—

L13

T8

K14

—

TEA

R/W

TSIZ1

TSIZ0

TS

DREQ1

—

I

O

P7

L6

DACK1

DACK0

DACK2

DREQ0

D16

G16

L4

B14

E14

H2

TIP

P6

—

Chip Selects

CS[7:1]

CS0

PCS[7:1]

—

O

D10:13, E13,

F13, N7

D8, A9, A10,

D10, B12, C14,

P4

—

R6

N5

DDR SDRAM Controller

DDR_CLKOUT

SD_CS[1:0]

SD_SRAS

SD_SCAS

SD_WE

—

O

I/O

O

I

T7

T6

P6

P5

—

PSDRAM[7:6]

PSDRAM[5]

PSDRAM[4]

PSDRAM[3]

—

CS[3:2]

—

M2, T5

L2

H3, M5

H1

—

L1

G3

—

K2

G4

SD_A10

—

N6

N4

SD_DQS[3:2]

SD_CKE

PSDRAM[2:1]

PSDRAM[0]

—

M4, P5

L3

J2, P3

J1

—

SD_VREF

—

A15, T2

A13, P2

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

5

Preliminary—Subject to Change Without Notice

Signal Descriptions

Table 2. MCF5274 and MCF5275 Signal Information and Muxing (continued)

MCF5274

MCF5275

MCF5274L

MCF5275L

Signal Name

GPIO

Alternate1 Alternate2 Dir.¹

256 MAPBGA 196 MAPBGA

External Interrupts Port

IRQ[7:5]

IRQ[4]

IRQ[3:2]

IRQ1

PIRQ[7:5]

PIRQ[4]

—

DREQ2

DREQ[3:2]

—

I

G13, H16, H15 F14, G13, G14

H14

J14, J13

K13

H11

H14, H12

J13

PIRQ[3:2]

PIRQ[1]

FEC0

FEC0_MDIO

FEC0_MDC

FEC0_TXCLK

FEC0_TXEN

FEC0_TXD[0]

FEC0_COL

PFECI2C[5]

PFECI2C[4]

PFEC0H[7]

PFEC0H[6]

PFEC0H[5]

PFEC0H[4]

PFEC0H[3]

PFEC0H[2]

PFEC0H[1]

PFEC0H[0]

I2C_SDA

U2RXD

U2TXD

—

I/O

O

I

A7

A3

I2C_SCL

B7

C5

—

C3

C1

—

O

I

D4

C3

—

G4

D2

—

A6

B4

FEC0_RXCLK

FEC0_RXDV

FEC0_RXD[0]

FEC0_CRS

—

I

B6

B5

B3

C4

—

I

—

I

C6

D5

—

I

C7

A2

FEC0_TXD[3:1] PFEC0L[7:5]

FEC0_TXER PFEC0L[4]

FEC0_RXD[3:1] PFEC0L[3:1]

—

O

I

E3, F3, F4

D3

D1, E3, D3

C2

—

D5, C5, D6

C4

D4, B1, B2

E4

FEC0_RXER

PFEC0L[0]

—

I

FEC1

FEC1_MDIO

FEC1_MDC

FEC1_TXCLK

FEC1_TXEN

FEC1_TXD[0]

FEC1_COL

PFECI2C[3]

PFECI2C[2]

PFEC1H[7]

PFEC1H[6]

PFEC1H[5]

PFEC1H[4]

PFEC1H[3]

PFEC1H[2]

PFEC1H[1]

PFEC1H[0]

—

I/O

G1

G2

C1

D2

F1

A5

B4

A3

B3

A4

—

O

I

O

I

FEC1_RXCLK

FEC1_RXDV

FEC1_RXD[0]

FEC1_CRS

I

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

6

Preliminary—Subject to Change Without Notice

Signal Descriptions

Table 2. MCF5274 and MCF5275 Signal Information and Muxing (continued)

MCF5274

MCF5275

MCF5274L

MCF5275L

Signal Name

GPIO

Alternate1 Alternate2 Dir.¹

256 MAPBGA 196 MAPBGA

FEC1_TXD[3:1] PFEC1L[7:5]

FEC1_TXER PFEC1L[4]

FEC1_RXD[3:1] PFEC1L[3:1]

—

O

I

E1, E2, F2

D1

—

B1, B2, A2

C2

FEC1_RXER

PFEC1L[0]

I

I²C

I2C_SDA

I2C_SCL

PFECI2C[1]

PFECI2C[0]

U2RXD

U2TXD

—

I/O

B10

C10

B7

A7

DMA

DACK[3:0] and DREQ[3:0] do not have a dedicated bond pads.

Please refer to the following pins for muxing:

—

PCS3/PWM3 for DACK3, PCS2/PWM2 for DACK2, TSIZ1 for

DACK1, TSIZ0 for DACK0, IRQ3 for DREQ3, IRQ2 and TA for

DREQ2, TEA for DREQ1, and TIP for DREQ0.

QSPI

QSPI_CS[3:2]

QSPI_CS1

QSPI_CS0

QSPI_CLK

QSPI_DIN

PQSPI[6:5]

PQSPI[4]

PQSPI[3]

PQSPI[2]

PQSPI[1]

PQSPI[0]

PWM[3:2]

—

DACK[3:2]

O

I

R13, N12

T14

P10, N9

N10

—

P12

M9

I2C_SCL

I2C_SDA

—

T15

L11

T13

M10

L10

QSPI_DOUT

O

R12

UARTs

U2RXD

U2TXD

U2CTS

U2RTS

U1RXD

U1TXD

U1CTS

U1RTS

U0RXD

U0TXD

U0CTS

PUARTH[3]

PUARTH[2]

PUARTH[1]

PUARTH[0]

PUARTL[7]

PUARTL[6]

PUARTL[5]

PUARTL[4]

PUARTL[3]

PUARTL[2]

PUARTL[1]

—

I

O

I

T9

R9

P9

R8

A9

B9

C9

D9

A8

B8

C8

—

PWM1

PWM0

—

O

I

—

A6

D7

C7

B6

A4

A5

C6

—

O

I

—

O

I

—

O

I

—

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

7

Preliminary—Subject to Change Without Notice

Signal Descriptions

Table 2. MCF5274 and MCF5275 Signal Information and Muxing (continued)

MCF5274

MCF5275

MCF5274L

MCF5275L

Signal Name

GPIO

Alternate1 Alternate2 Dir.¹

256 MAPBGA 196 MAPBGA

U0RTS

PUARTL[0]

—

O

D7

B5

USB

USB_SPEED

USB_CLK

USB_RN

PUSBH[0]

PUSBL[7]

PUSBL[6]

PUSBL[5]

PUSBL[4]

PUSBL[3]

PUSBL[2]

PUSBL[1]

PUSBL[0]

—

I/O

I

G14

G15

J16

J15

L15

M13

K14

K15

L14

G11

F12

H13

J11

L14

N13

J14

J12

K13

I

USB_RP

I

USB_RXD

USB_SUSP

USB_TN

I

O

USB_TP

USB_TXEN

Timers (and PWMs)

DT3IN

DT3OUT

DT2IN

PTIMERH[3]

PTIMERH[2]

PTIMERH[1]

PTIMERH[0]

PTIMERL[3]

PTIMERL[2]

PTIMERL[1]

PTIMERL[0]

DT3OUT

U2RTS

U2CTS

—

I

O

I

J4

K3

J2

G2

G1

F3

F4

F1

F2

E1

E2

PWM3

DT2OUT

PWM2

DT2OUT

DT1IN

—

O

I

J3

DT1OUT

PWM1

—

H1

H2

H3

G3

DT1OUT

DT0IN

—

O

I

DT0OUT

PWM0

—

DT0OUT

—

O

BDM/JTAG²

DSCLK

PSTCLK

BKPT

—

TRST

TCLK

TMS

TDI

—

I

O

I

P14

P16

R15

R16

P15

R14

P13

P12

N12

M12

K11

P11

DSI

I

DSO

TDO

—

O

I

JTAG_EN

DDATA[3:0]

—

O

P10, N10, P11, M7, N7, P8, L9

N11

PST[3:0]

—

O

T10, R10, T11, P7, L8, M8, N8

R11

Test

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

8

Preliminary—Subject to Change Without Notice

Design Recommendations

Table 2. MCF5274 and MCF5275 Signal Information and Muxing (continued)

MCF5274

MCF5275

MCF5274L

MCF5275L

Signal Name

GPIO

Alternate1 Alternate2 Dir.¹

256 MAPBGA 196 MAPBGA

TEST

—

I

N9

N6

—

PLL_TEST

M14

Power Supplies

VDDPLL

VSSPLL

VSS

—

I

M15

K16

M13

L13

A1, A10, A16,

E5, E12, F6,

F11, G7:10,

H7:10, J1,

F7, F8, G6:9,

H6:9, J7, J8

J7:10, K7:10,

L6, L11, M5,

N16, R7, T1,

T16

OVDD

—

I

E6:8, F5, F7, F8, E5:7, F5, F6,

G5, G6, H5, H6, H10, J9, J10,

J11, J12, K11,

K12, L9, L10,

L12, M9:11

K8:10

VDD

—

I

D8, H13, K4, N8 D6, G5, G12, L7

SD_VDD

E9:11, F9, F10, E8:10, F9, F10,

F12, G11, G12, G10, H5, J5, J6,

H11, H12, J5,

J6, K5, K6, L5,

L7, L8, M6, M7,

M8

K5:7

1

2

Refers to pin’s primary function. All pins which are configurable for GPIO have a pullup enabled in GPIO

mode with the exception of PBUSCTL[7], PBUSCTL[4:0], PADDR, PBS, PSDRAM.

If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not

responsible for assigning these pins.

5

Design Recommendations

5.1

Layout

•

Use a 4-layer printed circuit board with the VDD and GND pins connected directly to the power

and ground planes for the MCF5275.

•

See application note AN1259 System Design and Layout Techniques for Noise Reduction in

MCU-Based Systems.

Match the PC layout trace width and routing to match trace length to operating frequency and board

impedance. Add termination (series or therein) to the traces to dampen reflections. Increase the

PCB impedance (if possible) keeping the trace lengths balanced and short. Then do cross-talk

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

9

Preliminary—Subject to Change Without Notice

Design Recommendations

analysis to separate traces with significant parallelism or are otherwise "noisy". Use 6 mils trace

and separation. Clocks get extra separation and more precise balancing.

5.2

Power Supply

•

33uF, 0.1 µF, and 0.01 µF across each power supply

5.2.1

Supply Voltage Sequencing and Separation Cautions

Figure 2 shows situations in sequencing the I/O V (OV ), SDRAM V (SDV ), PLL V

DD

(PLLV ), and Core V (V ).

DD

OV_DD, SDV_DD

SDV_DD(2.5V)

3.3V

2.5V

Supplies Stable

V_DD, PLLV_DD

1.5V

1

2

0

Time

Notes:

1. VDD should not exceed OVDD, SDVDD or PLLVDD by more than

0.4 V at any time, including power-up.

2. Recommended that VDD/PLLVDD should track OVDD/SDVDD up to

0.9 V, then separate for completion of ramps.

3. Input voltage must not be greater than the supply voltage (OVDD, SDVDD,

VDD, or PLLVDD) by more than 0.5 V at any time, including during power-up.

4. Use 1 ms or slower rise time for all supplies.

Figure 2. Supply Voltage Sequencing and Separation Cautions

The relationship between SDV and OV is non-critical during power-up and power-down sequences.

DD

Both SDV (2.5V or 3.3V) and OV are specified relative to V .

DD

5.2.1.1

Power Up Sequence

If OV /SDV are powered up with V at 0 V, then the sense circuits in the I/O pads will cause all pad

DD

output drivers connected to the OV /SDV to be in a high impedance state. There is no limit on how

DD

long after OV /SDV powers up before V must powered up. V should not lead the OV ,

DD

SDV or PLLV by more than 0.4 V during power ramp-up, or there will be high current in the internal

DD

ESD protection diodes. The rise times on the power supplies should be slower than 1 µs to avoid turning

on the internal ESD protection clamp diodes.

The recommended power up sequence is as follows:

1. Use 1 µs or slower rise time for all supplies.

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

10

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

Design Recommendations

2. V /PLLV and OV /SDV should track up to 0.9 V, then separate for the completion of

DD

ramps with OV /SD V going to the higher external voltages. One way to accomplish this is to

DD

use a low drop-out voltage regulator.

5.2.1.2

Power Down Sequence

If V /PLLV are powered down first, then sense circuits in the I/O pads will cause all output drivers to

DD

be in a high impedance state. There is no limit on how long after V and PLLV power down before

DD

OV or SDV must power down. V should not lag OV , SDV , or PLLV going low by more

DD

than 0.4 V during power down or there will be undesired high current in the ESD protection diodes. There

are no requirements for the fall times of the power supplies.

The recommended power down sequence is as follows:

1. Drop V /PLLV to 0 V.

DD

2. Drop OV /SDV supplies.

DD

5.3

Decoupling

•

Place the decoupling capacitors as close to the pins as possible, but they can be outside the footprint

of the package.

•

0.1 µF and 0.01 µF at each supply input

5.4

Buffering

•

Use bus buffers on all data/address lines for all off-board accesses and for all on-board accesses

when excessive loading is expected. See electricals.

5.5

Pull-up Recommendations

•

Use external pull-up resistors on unused inputs. See pin table.

5.6

Clocking Recommendations

•

Use a multi-layer board with a separate ground plane.

•

Place the crystal and all other associated components as close to the EXTAL and XTAL (oscillator

pins) as possible.

•

Do not run a high frequency trace around crystal circuit.

Ensure that the ground for the bypass capacitors is connected to a solid ground trace.

Tie the ground trace to the ground pin nearest EXTAL and XTAL. This prevents large loop currents

in the vicinity of the crystal.

•

Tie the ground pin to the most solid ground in the system.

Do not connect the trace that connects the oscillator and the ground plane to any other circuit

element. This tends to make the oscillator unstable.

•

Tie XTAL to ground when an external oscillator is clocking the device.

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

11

Preliminary—Subject to Change Without Notice

Design Recommendations

5.7

Interface Recommendations

5.7.1

DDR SDRAM Controller

5.7.1.1

SDRAM Controller Signals in Synchronous Mode

Table 3 shows the behavior of SDRAM signals in synchronous mode.

Table 3. Synchronous DRAM Signal Connections

Signal

Description

SD_SRAS

Synchronous row address strobe. Indicates a valid SDRAM row address is present and can be

latched by the SDRAM. SD_SRAS should be connected to the corresponding SDRAM

SD_SRAS. Do not confuse SD_SRAS with the DRAM controller’s SDRAM_CS[1:0], which

should not be interfaced to the SDRAM SD_SRAS signals.

SD_SCAS

Synchronous column address strobe. Indicates a valid column address is present and can be

latched by the SDRAM. SD_SCAS should be connected to the corresponding signal labeled

SD_SCAS on the SDRAM.

SD_WE

DRAM read/write. Asserted for write operations and negated for read operations.

SD_CS[1:0]

Row address strobe. Select each memory block of SDRAMs connected to the MCF5275. One

SDRAM_CS signal selects one SDRAM block and connects to the corresponding CS signals.

SD_CKE

Synchronous DRAM clock enable. Connected directly to the CKE (clock enable) signal of

SDRAMs. Enables and disables the clock internal to SDRAM. When CKE is low, memory can

enter a power-down mode where operations are suspended or they can enter self-refresh

mode. SD_CKE functionality is controlled by DCR[COC]. For designs using external

multiplexing, setting COC allows SD_CKE to provide command-bit functionality.

BS[3:2]

Column address strobe. For synchronous operation, BS[3:2] function as byte enables to the

SDRAMs. They connect to the DQM signals (or mask qualifiers) of the SDRAMs.

DDR_CLKOUT Bus clock output. Connects to the CLK input of SDRAMs.

5.7.1.2

Address Multiplexing

See the SDRAM controller module chapter in the MCF5275 Reference Manual for details on address

multiplexing.

5.7.2

Ethernet PHY Transceiver Connection

The FEC supports both an MII interface for 10/100 Mbps Ethernet and a seven-wire serial interface for 10

Mbps Ethernet. The interface mode is selected by R_CNTRL[MII_MODE]. In MII mode, the 802.3

standard defines and the FEC module supports 18 signals. These are shown in Table 4.

Table 4. MII Mode

Signal Description

Transmit clock

MCF5275 Pin

FECn_TXCLK

FECn_TXEN

FECn_TXD[3:0]

FECn_TXER

Transmit enable

Transmit data

Transmit error

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

12

Preliminary—Subject to Change Without Notice

Design Recommendations

Table 4. MII Mode (continued)

Signal Description MCF5275 Pin

Collision

FECn_COL

Carrier sense

FECn_CRS

Receive clock

FECn_RXCLK

FECn_RXDV

FECn_RXD[3:0]

FECn_RXER

FECn_MDC

FECn_MDIO

Receive enable

Receive data

Receive error

Management channel clock

Management channel serial data

The serial mode interface operates in what is generally referred to as AMD mode. The MCF5275

configuration for seven-wire serial mode connections to the external transceiver are shown in Table 5.

Table 5. Seven-Wire Mode Configuration

Signal Description

Transmit clock

MCF5275 Pin

FECn_TXCLK

FECn_TXEN

FECn_TXD[0]

FECn_COL

Transmit enable

Transmit data

Collision

Receive clock

FECn_RXCLK

FECn_RXDV

FECn_RXD[0]

FECn_RXER

FECn_CRS

Receive enable

Receive data

Unused, configure as PB14

Unused input, tie to ground

Unused, configure as PB[13:11]

Unused output, ignore

Unused, configure as PB[10:8]

Unused, configure as PB15

Input after reset, connect to ground

FECn_RXD[3:1]

FECn_TXER

FECn_TXD[3:1]

FECn_MDC

FECn_MDIO

Refer to the M5275EVBevaluation board user’s manual for an example of how to connect an external

PHY. Schematics for this board are accessible at the MCF5275 site by navigating to:

http://www.freescale.com/coldfire.

5.7.3

BDM

Use the BDM interface as shown in the M5275EVB evaluation board user’s manual. The schematics for

this board are accessible at the MCF5275 site by navigating to: http://www.freescale.com/coldfire.

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

13

Preliminary—Subject to Change Without Notice

Mechanicals/Pinouts

6

Mechanicals/Pinouts

6.1

256 MAPBGA Pinout

Figure 3 is a consolidated MCF5274/75 pinout for the 256 MAPBGA package. Table 2 lists the signals by

group and shows which signals are muxed and bonded on each of the device packages.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

FEC1_

RXD1

FEC1_

RXDV

FEC1_

CRS

FEC1_

COL

FEC0_

COL

FEC0_

MDIO

SD_

VREF

A

B

C

D

E

F

VSS

U0RXD U1RXD

U0TXD U1TXD

U0CTS U1CTS

VSS

A23

A20

A17

A14

VSS

A

B

C

D

E

F

FEC1_ FEC1_

RXD3 RXD2

FEC1_

RXD0

FEC1_

RXCLK

FEC0_

RXDV

FEC0_

RXCLK

FEC0_

MDC

I2C_

SDA

A22

A21

CS6

A19

A18

CS5

A16

A15

CS4

CS3

A13

A12

A7

A11

A10

A6

A9

A8

FEC1_ FEC1_

TXCLK RXER

FEC0_

TXCLK

FEC0_

RXER

FEC0_

RXD2

FEC0_

RXD0

FEC0_

CRS

I2C_

SCL

FEC1_ FEC1_

FEC0_

TXER

FEC0_

TXEN

FEC0_

RXD3

FEC0_

RXD1

U0RTS

OVDD

VSS

VDD

U1RTS

CS7

TSIZ1

A3

TXER

TXEN

FEC1_ FEC1_

TXD3 TXD2

FEC0_

TXD3

NC

VSS

OVDD

VSS

OVDD SD_VDD SD_VDD SD_VDD VSS

A5

A4

FEC1_ FEC1_

TXD0 TXD1

FEC0_

TXD2

FEC0_

TXD1

OVDD

OVDD SD_VDD SD_VDD VSS SD_VDD CS2

A2

A1

A0

FEC1_ FEC1_

MDIO MDC

FEC0_

TXD0

USB_

SPEED

USB_

CLK

G

H

J

DT0OUT

OVDD

VSS

VSS SD_VDD SD_VDD IRQ7

VSS SD_VDD SD_VDD VDD

TSIZ0

IRQ6

G

H

J

DT1IN DT1OUT DT0IN

NC

DT3IN

VDD

VSS

IRQ4

IRQ5

VSS

OE

DT2IN DT2OUT

SD_WE DT3OUT

SD_VDD SD_VDD

VSS

OVDD OVDD

IRQ2

IRQ3 USB_RP USB_RN

K

L

VSS

IRQ1 USB_TN USB_TP VSSPLL

K

L

SD_

SCAS

SD_

USB_

TXEN

USB_

RXD

SD_CKE

SRAS

TS

SD_VDD

VSS

SD_VDD SD_VDD OVDD OVDD

VSS

OVDD

NC

TA

EXTAL

USB_

SUSP

PLL_

TEST

M

N

P

R

T

D31 SD_CS1

BS3

D28

D23

D22

SD_DQS3

D20

SD_VDD SD_VDD SD_VDD OVDD OVDD OVDD

VDDPLL XTAL

M

N

P

R

T

QSPI_

CS2

CLK

MOD1

D30

D27

D25

D29

D26

D24

D16

SD_A10

TIP

CS1

R/W

VSS

VDD

TEST DDATA2 DDATA0

RSTOUT RESET

VSS

QSPI_

CS0

CLK

TRST/ TDO/

TCLK/

D19

SD_DQS2

BS2

RCON U2CTS DDATA3 DDATA1

MOD0 DSCLK

DSO PSTCLK

QSPI_ QSPI_ JTAG_

DOUT CS3 EN

TMS/

D18

CS0

U2RTS U2TXD PST2

PST0

TDI/DSI

BKPT

SD_

VREF

DDR_CLK DDR_CLK

OUT

QSPI_ QSPI_ QSPI_

VSS

D21

D17

SD_CS0

TEA

U2RXD PST3

10

PST1 CLKOUT

11 12

VSS

OUT

DIN

CS1

CLK

1

2

3

4

5

6

7

8

9

13

14

15

16

Figure 3. MCF5274 and MCF5275 Pinout (256 MAPBGA)

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

14

Preliminary—Subject to Change Without Notice

Mechanicals/Pinouts

6.2

Package Dimensions - 256 MAPBGA

Figure 6 shows MCF5275 256 MAPBGA package dimensions.

X

D

M

LASER MARK FOR PIN A1

IDENTIFICATION IN

THIS AREA

5

Y

E

0.30 Z

A2

K

A

A1

256X

4

0.15 Z

Z

DETAIL K

ROTATED 90 CLOCKWISE

°

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.

3. DIMENSION b IS MEASURED AT THE

MAXIMUM SOLDER BALL DIAMETER,

PARALLEL TO DATUM PLANE Z.

4. DATUM Z (SEATING PLANE) IS DEFINED BY

THE SPHERICAL CROWNS OF THE SOLDER

BALLS.

5. PARALLELISM MEASUREMENT SHALL

EXCLUDE ANY EFFECT OF MARK ON TOP

SURFACE OF PACKAGE.

M

0.20

15X e

S

METALIZED MARK FOR

PIN A1 IDENTIFICATION

IN THIS AREA

16151413121110

7 6 5 4 3 2 1

A

B

C

D

E

F

S

15X e

3

G

H

J

256X

b

MILLIMETERS

M

0.25

0.10

Z X Y

K

L

M

N

P

R

T

DIM MIN

1.25

A1 0.27

MAX

1.60

0.47

Z

A

A2

b

1.16 REF

0.40

0.60

D

E

e

17.00 BSC

1.00 BSC

0.50 BSC

VIEW M-M

S

Figure 4. 256 MAPBGA Package Dimensions

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

15

Preliminary—Subject to Change Without Notice

Mechanicals/Pinouts

6.3

196 MAPBGA Pinout

Figure 5 is a consolidated MCF5274L/75L pinout for the 196 MAPBGA package. Table 2 lists the signals

by group and shows which signals are muxed and bonded on each of the device packages.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

FEC0_

CRS

FEC0_

MDIO

SD_

VREF

A

B

C

D

E

F

NC

U0RXD

U0TXD

U1RXD

I2C_SCL

A23

CS6

CS5

A15

A12

NC

A

B

C

D

E

F

FEC0_

RXD2

FEC0_

RXD1

FEC0_

RXCLK

FEC0_

COL

U0RTS

U1RTS

U0CTS

VDD

I2C_SDA

U1CTS

U1TXD

OVDD

VSS

A22

A21

CS7

A20

A18

A19

A16

A17

CS4

A13

A14

A11

A6

CS3

A10

A9

A8

TSIZ1

CS2

FEC0_

TXCLK

FEC0_

TXER

FEC0_

TXEN

FEC0_

RXDV

FEC0_

MDC

FEC0_

TXD3

FEC0_

TXD0

FEC0_

TXD1

FEC0_

RXD3

FEC0_

RXD0

A7

A5

A2

FEC0_

TXD2

FEC0_

RXER

DT0IN

DT1IN

DT0OUT

DT1OUT

DT3IN

TS

OVDD

VSS

SD_VDD2 SD_VDD2 SD_VDD2

A4

A1

TSIZ0

IRQ7

IRQ5

IRQ3

USB_TN

TA

DT2IN

SD_CAS

SD_CS1

D31

DT2OUT

SD_WE

OE

VSS

SD_VDD2 SD_VDD2

A3

USB_CLK

VDD

A0

USB_

SPEED

G

H

J

DT3OUT

SD_SRAS

VDD

VSS

SD_VDD2

OVDD

IRQ6

USB_RN

IRQ1

G

H

J

SD_VDD1

VSS

IRQ4

IRQ2

SD_CKE SD_DQS3

D22

SD_VDD1 SD_VDD1

VSS

OVDD

DDATA0

OVDD

USB_RP USB_TP

TDO/DSO RESET

USB_

TXEN

K

L

BS3

D30

D27

D20

D29

D26

D21

D19

D28

D23

SD_VDD1 SD_VDD1 SD_VDD1

OVDD

PST2

PST1

PST0

OVDD

K

L

QSPI_

DOUT

D25

D24

BS2

SD_CS0

CS0

R/W

RCON

TEST

VDD

QSPI_CLK RSTOUT VSSPLL USB_RXD

QSPI_

CS0

M

N

P

D18

D17

DDATA3

DDATA2

QSPI_DIN CLKMOD1 TDI/DSI

VDDPLL

EXTAL

XTAL

M

N

P

QSPI_

CS2

QSPI_

USB_

SUSP

D16

SD_A10

CLKMOD0 TMS/BKPT

CS1

SD_

VREF

DDR_CLK DDR_CLK

OUT

QSPI_

CS3

TCLK/PST TRST/DSC

NC

SD_DQS2

CS1

PST3

DDATA1 CLKOUT

JTAG_EN

NC

OUT

CLK

LK

1

2

3

4

5

6

7

8

9

10

11

12

13

14

Figure 5. MCF5274L and MCF5275L Pinout (196 MAPBGA)

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

16

Preliminary—Subject to Change Without Notice

Mechanicals/Pinouts

6.4

Package Dimensions - 196 MAPBGA

Figure 6 shows MCF5275 196 MAPBGA package dimensions.

NOTES:

D

X

Y

1. Dimensions are in millimeters.

2. Interpret dimensions and tolerances

per ASME Y14.5M, 1994.

3. Dimension b is measured at the

maximum solder ball diameter,

parallel to datum plane Z.

Laser mark for pin 1

identification in

this area

M

K

4. Datum Z (seating plane) is defined

by the spherical crowns of the solder

balls.

5. Parallelism measurement shall

exclude any effect of mark on top

surface of package.

E

Millimeters

DIM

Min

Max

1.25

0.27

1.60

0.47

A

A1

A2

b

1.16 REF

M

0.45

0.55

TOL

15.00 BSC

D

13Xe

15.00 BSC

1.00 BSC

0.50 BSC

E

S

Metalized mark for

pin 1 identification

in this area

e

14 13 12 11 10

9

6

5

4

3

2

1

S

A

B

C

D

E

F

5

S

0.20 Z

13Xe

A2

A

G

H

J

A1

0.10 Z

196X

4

Z

K

L

Detail K

Rotated 90° Clockwise

M

N

P

3

196X

b

View M-M

0.15 Z X Y

0.08 Z

Figure 6. 196 MAPBGA Package Dimensions

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

17

Preliminary—Subject to Change Without Notice

Ordering Information

7

Ordering Information

Table 6. Orderable Part Numbers

Freescale Part

Number

Description

Speed

Temperature

MCF5274LVM133

MCF5274LVM166

MCF5274VM133

MCF5274VM166

MCF5275LCVM133

MCF5275LCVM166

MCF5275CVM133

MCF5275CVM166

MCF5274L RISC Microprocessor, 196 MAPBGA

MCF5274 RISC Microprocessor, 256 MAPBGA

MCF5275L RISC Microprocessor, 196 MAPBGA

MCF5275 RISC Microprocessor, 256 MAPBGA

133MHz

166MHz

133MHz

166MHz

133MHz

166MHz

133MHz

166MHz

0° to +70° C

-40° to +85° C

8

Preliminary Electrical Characteristics

This appendix contains electrical specification tables and reference timing diagrams for the MCF5275

microcontroller unit. This section contains detailed information on power considerations, DC/AC

electrical characteristics, and AC timing specifications of MCF5275.

The electrical specifications are preliminary and are from previous designs or design simulations. These

specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however

for production silicon these specifications will be met. Finalized specifications will be published after

complete characterization and device qualifications have been completed.

NOTE

The parameters specified in this appendix supersede any values found in the

module specifications.

8.1

Maximum Ratings

1, 2

Table 7. Absolute Maximum Ratings

Rating

Symbol

Value

Unit

Core Supply Voltage

V_DD

OV_DD

SDV_DD

V_DDPLL

V_IN

– 0.5 to +2.0

– 0.3 to +4.0

V

I/O Pad Supply Voltage (3.3V)

Memory Interface SSTL 2.5V Pad Supply Voltage

Memory Interface SSTL 3.3V Pad Supply Voltage

PLL Supply Voltage

– 0.3 to + 2.8

– 0.3 to +4.0

– 0.3 to + 4.0

0 to 3.3

Digital Input Voltage ³

EXTAL pin voltage

V_EXTAL

V_XTAL

XTAL pin voltage

0 to 3.3

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

18

Preliminary—Subject to Change Without Notice

Preliminary Electrical Characteristics

(continued)

1, 2

Table 7. Absolute Maximum Ratings

Rating

Symbol

Value

Unit

Instantaneous Maximum Current

I_D

25

mA

Single pin limit (applies to all pins) ^{4, 5}

Operating Temperature Range (Packaged)

T_A

– 40 to 85

°C

(T_L- T_H)

Storage Temperature Range

T_stg

– 65 to 150

°C

1

Functional operating conditions are given in DC Electrical Specifications. Absolute Maximum Ratings

are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond those

listed may affect device reliability or cause permanent damage to the device.

This device contains circuitry protecting against damage due to high static voltage or electrical fields;

however, it is advised that normal precautions be taken to avoid application of any voltages higher than

maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused

inputs are tied to an appropriate logic voltage level (e.g., either V_SSor O V_DD).

Input must be current limited to the value specified. To determine the value of the required

current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use

the larger of the two values.

2

3

4

5

All functional non-supply pins are internally clamped to V_SSand O V_DD

.

Power supply must maintain regulation within operating O V_DDrange during instantaneous and

operating maximum current conditions. If positive injection current (V_in> O V_DD) is greater than I_DD, the

injection current may flow out of O V_DDand could result in external power supply going out of

regulation. Insure external O V_DDload will shunt current greater than maximum injection current. This

will be the greatest risk when the MCU is not consuming power (ex; no clock).Power supply must

maintain regulation within operating V_DDrange during instantaneous and operating maximum current

conditions.

8.2

Thermal Characteristics

Table 8 lists thermal resistance values

Table 8. Thermal characteristics

Symbol

θ_JMA

Characteristic

256MBGA 196MBGA

Unit

Junction to ambient, natural convection

Junction to ambient (@200 ft/min)

Junction to board

Four layer board (2s2p)

26^1,2

23^1,2

15³

32^1,2

29^1,2

20³

°C/W

^oC

θ_JMA

θ_JB

θ_JC

Ψ_jt

Junction to case

10⁴

Junction to top of package

Natural convection

2^1,5

Maximum operating junction temperature

T_j

105

1

θ

_JMAand Ψ_jtparameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale

recommends the use of θ_JmAand power dissipation specifications in the system design to prevent device junction

temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures

can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature

specification can be verified by physical measurement in the customer’s system using the Ψ_jtparameter, the device power

dissipation, and the method described in EIA/JESD Standard 51-2.

Per JEDEC JESD51-6 with the board horizontal.

Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board

temperature is measured on the top surface of the board near the package.

2

3

4

Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1).

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

19

Preliminary—Subject to Change Without Notice

Preliminary Electrical Characteristics

5

Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written

in conformance with Psi-JT.

The average chip-junction temperature (T_J) in °C can be obtained from:

(1)

)

T_J= T_A+ (P_D× Θ_JMA

Where:

T_A

= Ambient Temperature, °C

Θ_JMA

P_D

= Package Thermal Resistance, Junction-to-Ambient, °C/W

= P_INT+ P_I/O

P_INT

P_I/O

= I_DD× V_DD, Watts - Chip Internal Power

= Power Dissipation on Input and Output Pins — User Determined

For most applications P_I/O< P_INTand can be ignored. An approximate relationship between P_Dand T_J(if P_I/Ois

neglected) is:

P_D= K ÷ (T_J+ 273°C)

(2)

Solving equations 1 and 2 for K gives:

K = P_D× (T_A+ 273 °C) + Θ_JMA× P_D

2

(3)

where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring P_D(at

equilibrium) for a known T_A. Using this value of K, the values of P_Dand T_Jcan be obtained by solving equations (1)

and (2) iteratively for any value of T_A.

8.3

ESD Protection

1, 2

Table 9. ESD Protection Characteristics

Characteristics

Symbol

Value

Units

ESD Target for Human Body Model

ESD Target for Machine Model

HBM Circuit Description

HBM

MM

2000

200

1500

100

0

V

R_series

C

Ω

pF

Ω

MM Circuit Description

R_series

C

200

pF

—

Number of pulses per pin (HBM)

positive pulses

negative pulses

—

1

Number of pulses per pin (MM)

positive pulses

—

3

negative pulses

Interval of Pulses

—

1

sec

1

All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive

Grade Integrated Circuits.

A device is defined as a failure if after exposure to ESD pulses the device no longer meets the

device specification requirements. Complete DC parametric and functional testing is

performed per applicable device specification at room temperature followed by hot

temperature, unless specified otherwise in the device specification.

2

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

20

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

Preliminary Electrical Characteristics

8.4

DC Electrical Specifications

1

Table 10. DC Electrical Specifications

Characteristic

Symbol

Min

Max

Unit

Core Supply Voltage

I/O Pad Supply Voltage

V_DD

OV_DD

SDV_DD

V_REF

V_IH

1.4

3.0

1.6

3.6

2.7

3.6

V

SSTL I/O Pad Supply Voltage

2.3

SSTL I/O Pad Supply Voltage

3.0

2

SSTL Memory pads reference voltage (SD V_DD= 2.5V)

SSTL Memory pads reference voltage (SD V_DD= 3.3V)

Input High Voltage 3.3V I/O Pads

0.5 SD V_DD

0.45 SD V_DD

0.7 x OV_DD

V_SS– 0.3

OV_DD- 0.5

—

2

—

3.6

0.35 x OV_DD

—

Input Low Voltage 3.3V I/O Pads

V_IL

Output High Voltage 3.3V I/O Pads

V_OH

I

_OH= –2.0 mA

Output Low Voltage 3.3V I/O Pads

I_OL= 2.0mA

V_OL

—

0.5

V

Input Hysteresis 3.3V I/O Pads

V_HYS

V_IH

0.06 x V_DD

V_REF+ 0.3

V_SS- 0.3

—

SDV_DD+ 0.3

V_REF- 0.3

—

mV

V

Input High Voltage SSTL 3.3V/2.5V³

Input Low Voltage SSTL 3.3V/2.5V³

Output High Voltage SSTL 3.3V/2.5V⁴

V_IL

V

V_OH

SDV_DD- 0.25V

V

I_OH= –5.0 mA

Output Low Voltage SSTL 3.3V/2.5V⁴

I_OL= 5.0 mA

V_OL

I_in

—

0.35

1.0

V

Input Leakage Current

-1.0

-10

µA

V_in= V_DDor V_SS, Input-only pins

High Impedance (Off-State) Leakage Current

V_in= V_DDor V_SS, All input/output and output pins

Weak Internal Pull Up Device Current, tested at V_ILMax.⁵

I_OZ

1.0

I_APU

C_in

-130

µA

Input Capacitance ⁶

pF

All input-only pins

All input/output (three-state) pins

—

7

Load Capacitance⁷

Low Drive Strength

High Drive Strength

pF

C_L

25

50

Core Operating Supply Current ⁸

I_DD

Master Mode

WAIT

DOZE

—

175

15

10

mA

µA

STOP

100

I/O Pad Operating Supply Current

Master Mode

OI_DD

—

250

mA

µA

Low Power Modes

DC Injection Current ^{3, 9, 10, 11}

I_IC

mA

V_NEGCLAMP=V_SS– 0.3 V, V_POSCLAMP= V_DD+ 0.3

Single Pin Limit

Total MCU Limit, Includes sum of all stressed pins

-1.0

-10

1.0

10

1

Refer to Table 11 for additional PLL specifications.

V_REFis specified as a nominal value only instead of a range, so no maximum value is listed.

This specification is guaranteed by design and is not 100% tested.

2

3

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

21

Preliminary—Subject to Change Without Notice

Preliminary Electrical Characteristics

4

The actual V_OHand V_OLvalues for SSTL pads are dependent on the termination and drive strength used. The specifications

numbers assume no parallel termination.

5

Refer to the MCF5274 signals chapter for pins having weak internal pull-up devices.

This parameter is characterized before qualification rather than 100% tested.

pF load ratings are based on DC loading and are provided as an indication of driver strength. High speed interfaces

6

7

require transmission line analysis to determine proper drive strength and termination.

Current measured at maximum system clock frequency, all modules active, and default drive strength with matching load.

8

9

All functional non-supply pins are internally clamped to V_SSand their respective V_DD

.

10

11

Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,

calculate resistance values for positive and negative clamp voltages, then use the larger of the two values.

Power supply must maintain regulation within operating V_DDrange during instantaneous and operating maximum current

conditions. If positive injection current (V_in> V_DD) is greater than I_DD, the injection current may flow out of V_DDand could

result in external power supply going out of regulation. Insure external V_DDload will shunt current greater than maximum

injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is

present, or if clock rate is very low which would reduce overall power consumption. Also, at power-up, system clock is not

present during the power-up sequence until the PLL has attained lock.

8.5

Oscillator and Phase Lock Loop (PLLMRFM) Electrical

Specifications

1

Table 11. PLL Electrical Specifications

Characteristic

PLL Reference Frequency Range

Symbol

Min

Max

Unit

MHz

Crystal reference

External reference

1:1 Mode (NOTE: f_sys/2= 2 × _{fref_1:1}

f_{ref_crystal}

f_{ref_ext}

f_{ref_1:1}

8

24

25

83

)

Core frequency

f_core

166

MHz

CLKOUT Frequency ²

External reference

On-Chip PLL Frequency

0

83

MHz

f_sys/2

f_LOR

f_SCM

t_cst

f_ref/ 32

Loss of Reference Frequency ^{3, 5}

Self Clocked Mode Frequency ^{4, 5}

Crystal Start-up Time ^{5, 6}

100

TBD

—

1000

TBD

10

kHz

MHz

ms

EXTAL Input High Voltage

Crystal Mode

V_IHEXT

V

TBD

All other modes (Dual Controller (1:1), Bypass, External)

EXTAL Input Low Voltage

V_ILEXT

V

Crystal Mode

TBD

All other modes (Dual Controller (1:1), Bypass, External)

XTAL Output High Voltage

I_OH= 1.0 mA

V_OH

V_OL

V

TBD

—

XTAL Output Low Voltage

I_OL= 1.0 mA

XTAL Load Capacitance⁷

PLL Lock Time ⁸

—

5

TBD

30

pF

t_lpll

—

750

µs

Power-up To Lock Time ^{6, 9}

With Crystal Reference

t_lplk

—

11

750

ms

µs

Without Crystal Reference¹⁰

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

22

Preliminary—Subject to Change Without Notice

Preliminary Electrical Characteristics

Table 11. PLL Electrical Specifications (continued)

1

Characteristic

Symbol

Min

Max

Unit

1:1 Mode Clock Skew (between CLKOUT and EXTAL) ¹¹

Duty Cycle of reference ⁵

t_skew

t_dc

-1

1

ns

40

60

4.1

2.0

% f_sys/2

Frequency un-LOCK Range

f_UL

-3.8

-1.7

Frequency LOCK Range

f_LCK

C_jitter

CLKOUT Period Jitter, ^{5, 6, 9,12, 13}Measured at f_sys/2Max

Peak-to-peak Jitter (Clock edge to clock edge)

Long Term Jitter (Averaged over 2 ms interval)

—

5

.01

% f_sys/2

MHz

15

Frequency Modulation Range Limit¹⁴

,

C_mod

f_ico

0.8

2.2

83

(f_sys/2Max must not be exceeded)

ICO Frequency. f_ico= f_{ref *}2 _*(MFD+2)¹⁶

48

1

All values given are initial design targets and subject to change.

All internal registers retain data at 0 Hz.

“Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self

clocked mode.

Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below

f_LORwith default MFD/RFD settings.

This parameter is guaranteed by characterization before qualification rather than 100% tested.

Proper PC board layout procedures must be followed to achieve specifications.

Load Capacitance determined from crystal manufacturer specifications and will include circuit board parasitics.

This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits

in the synthesizer control register (SYNCR).

2

3

4

5

6

7

8

9

Assuming a reference is available at power up, lock time is measured from the time V_DDand V_DDPLLare valid to

RSTOUT negating. If the crystal oscillator is being used as the reference for the PLL, then the crystal start up time

must be added to the PLL lock time to determine the total start-up time.

10

11

12

t_lpll= (64 _*4 _*5 + 5 x τ) x T , where T_ref= 1/F_{ref_crystal}= 1/F_{ref_ext}= 1/F_{ref_1:1}, and τ = 1.57x10^-6x 2(MFD + 2)

ref

PLL is operating in 1:1 PLL mode.

Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum

f_sys/2. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock

signal. Noise injected into the PLL circuitry via V_DDPLLand V_SSPLLand variation in crystal oscillator frequency

increase the jitter percentage for a given interval.

13

14

15

Based on slow system clock of 33MHz maximum frequency.

Modulation percentage applies over an interval of 10µs, or equivalently the modulation rate is 100KHz.

Modulation rate selected must not result in f_sys/2value greater than the f_sys/2maximum specified value. Modulation

range determined by hardware design.

16

f_sys/2= f_ico/ (2 _*2^RFD

)

8.6

External Interface Timing Characteristics

Table 12 lists processor bus input timings.

NOTE

All processor bus timings are synchronous; that is, input setup/hold and

output delay with respect to the rising edge of a reference clock. The

reference clock is the CLKOUT output.

All other timing relationships can be derived from these values.

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

23

Preliminary—Subject to Change Without Notice

Preliminary Electrical Characteristics

Table 12. Processor Bus Input Timing Specifications

Name

Characteristic¹

Symbol

Min

Max Unit

B0

CLKOUT

t_CYC

12

—

ns

Control Inputs

B1a

B1b

B2a

B2b

Control input valid to CLKOUT high²

BKPT valid to CLKOUT high³

t_CVCH

t_BKVCH

t_CHCII

9

0

—

ns

CLKOUT high to control inputs invalid²

CLKOUT high to asynchronous control input BKPT invalid³

t_BKNCH

Data Inputs

B4

B5

Data input (D[31:16]) valid to CLKOUT high

CLKOUT high to data input (D[31:16]) invalid

t_DIVCH

t_CHDII

4

0

—

ns

1

2

3

Timing specifications have been indicated taking into account the full drive strength for the pads.

TEA and TA pins are being referred to as control inputs.

Refer to figure A-19.

Timings listed in Table 12 are shown in Figure 7.

* The timings are also valid for inputs sampled on the negative clock edge.

CLKOUT (83MHz)

T_SETUP

T_HOLD

Invalid

Valid

Invalid

Input Setup And Hold

Input Rise Time

t_rise

V_h= V_IH

V_l= V_IL

t_fall

V_h= V_IH

V_l= V_IL

Input Fall Time

CLKOUT

Inputs

B4

B5

Figure 7. General Input Timing Requirements

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

24

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

Preliminary Electrical Characteristics

8.7

Processor Bus Output Timing Specifications

Table 13 lists processor bus output timings.

Table 13. External Bus Output Timing Specifications

Name

Characteristic

Symbol

Min

Max

Unit

Control Outputs

B6a

CLKOUT high to chip selects (CS[7:0]) valid ¹

CLKOUT high to byte enables (BS[3:2]) valid²

CLKOUT high to output enable (OE) valid³

CLKOUT high to control output (BS[3:2], OE) invalid

CLKOUT high to chip selects invalid

t_CHCV

t_CHBV

t_CHOV

t_CHCOI

t_CHCI

—

0.5t_CYC+ 5.5

—

ns

B6b

B6c

B7

—

0.5t_CYC+ 1.0

B7a

—

Address and Attribute Outputs

CLKOUT high to address (A[23:0]) and control (TS, t_CHAV

B8

B9

—

9

ns

TSIZ[1:0], TIP, R/W) valid

CLKOUT high to address (A[23:0]) and control (TS,

TSIZ[1:0], TIP, R/W) invalid

t_CHAI

1.0

—

Data Outputs

B11

B12

B13

CLKOUT high to data output (D[31:16]) valid

CLKOUT high to data output (D[31:16]) invalid

t_CHDOV

t_CHDOI

—

1.0

—

9

—

9

ns

CLKOUT high to data output (D[31:16]) high impedance t_CHDOZ

1

2

3

CS transitions after the falling edge of CLKOUT.

BS transitions after the falling edge of CLKOUT.

OE transitions after the falling edge of CLKOUT.

Read/write bus timings listed in Table 13 are shown in Figure 8, Figure 9, and Figure 10.

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

25

Preliminary—Subject to Change Without Notice

Preliminary Electrical Characteristics

S4

S5

S0

S1

S2

S5

S0

S1

S2

S3

S4

S3

CLKOUT

CSn

B7a

B6a

B8

B9

A[23:0]

TSIZ[1:0]

TS

B8

B9

B8

TIP

B9

B8

B0

B6c

B7

OE

B8

B9

(H)

R/W

B6b

B7

BS[3:2]

B7

B11

B12

B13

B4

D[31:16]

B5

(H)

TA

(H)

TEA

Figure 8. Read/Write (Internally Terminated) SRAM Bus Timing

Figure 9 shows a bus cycle terminated by TA showing timings listed in Table 13.

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

26

Preliminary—Subject to Change Without Notice

Preliminary Electrical Characteristics

S4

S0

S1

S2

S5

S0

S1

S3

CLKOUT

CSn

B6a

B7a

B8

B9

A[23:0]

TSIZ[1:0]

TS

B9

TIP

OE

B6c

B6b

B7

(H)

R/W

BS[3:2]

B5

B4

D[31:16]

TA

B2a

B1a

TEA

(H)

Figure 9. SRAM Read Bus Cycle Terminated by TA

Figure 10 shows an SRAM bus cycle terminated by TEA showing timings listed in Table 13.

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

27

Preliminary—Subject to Change Without Notice

Preliminary Electrical Characteristics

S4

S1

S2

S5

S0

S1

S0

S3

CLKOUT

CSn

B6a

B7a

B8

B9

A[23:0]

TSIZ[1:0]

B8

TS

B9

B8

TIP

B9

B6c

B6b

B7

OE

(H)

R/W

B7

BS[3:2]

D[31:16]

TA

(H)

B1a

TEA

B2a

Figure 10. SRAM Read Bus Cycle Terminated by TEA

8.8

DDR SDRAM AC Timing Characteristics

The DDR SDRAM controller uses SSTL2 and I/O drivers. Either Class I or Class II drive strength is

available and is user programmable. DDR Clock timing specifications are given in Table 14 and Figure 11.

1

Table 14. DDR Clock Timing Specifications

Symbol

Characteristic

Clock output mid-point voltage

Min

Max

Unit

V_MP

V_OUT

V_ID

1.05

-0.3

0.7

1.45

V

Clock output voltage level

SDV_DD+ 0.3

SDV_DD+ 0.6

1.45

Clock output differential voltage (peak to peak swing)

Clock crossing point voltage

V_IX

1.05

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

28

Preliminary—Subject to Change Without Notice

Preliminary Electrical Characteristics

1

SD V_DDis nominally 2.5V.

SDCLK

V_IX

V_ID

V_MP

V_IX

SDCLK

Figure 11. DDR Clock Timing Diagram

When using the DDR SDRAM controller the timing numbers in Table 15 must be followed to properly

latch or drive data onto the memory bus. All timing numbers are relative to the two DQS byte lanes.

Table 15. DDR Timing

NUM

Characteristic¹

Frequency of operation²

Symbol

Min

Max

Unit

TBD

12

83

TBD

MHz

ns

DD1 Clock Period (DDR_CLKOUT)

DD2 Pulse Width High³

DD3 Pulse Width Low³

t_CK

t_CKH

t_CKl

0.45

—

0.55

t_CK

ns

0.55

DD4 DDR_CLKOUT high to DDR address, SD_CKE,

SD_CS[1:0], SD_SCAS, SD_SRAS, SD_WE valid

t_CMV

0.5 x t_CK+ 1

DD5 DDR_CLKOUT high to DDR address, SD_CKE, SD_CS,

SD_SCAS, SD_SRAS, SD_WE invalid

t_CMH

2

—

ns

DD6 Write command to first SD_DQS Latching Transition

DD7 SD_DQS high to Data and DM valid (write) - setup^4,5

DD8 SD_DQS high to Data and DM invalid (write) - hold⁴

DD9 SD_DQS high to Data valid (read) - setup⁶

t_DQSS

t_QS

—

1.25

—

t_CK

ns

1.5

t_QH

1

—

ns

t_IS

—

1

ns

DD10 SD_DQS high to Data invalid (read) - hold⁷

DD11 SD_DQS falling edge to CLKOUT high - setup

DD12 SD_DQS falling edge to CLKOUT high - hold

t_IH

0.25 x t_CK+ 1

—

ns

t_DSS

t_DSH

t_RPRE

t_RPST

t_WPRE

t_WPST

0.5

—

ns

—

ns

DD13 DQS input read preamble width (t_RPRE

DD14 DQS input read postamble width (t_RPST

DD15 DQS output write preamble width (t_WPRE

DD16 DQS output write postamble width (t_WPST

)

0.9

1.1

0.6

—

t_CK

)

0.4

)

0.25

0.4

)

0.6

1

2

3

4

5

All timing specifications are based on taking into account, a 25pF load on the SDRAM output pins.

DDR_CLKOUT operates at half the frequency of the PLLMRFM output and the ColdFire core.

t_CKH+ t_CKLmust be less than or equal to t_CK

.

D[31:24] is relative to SD_DQS3 and D[23:16] is relative to SD_DQS2.

The first data beat will be valid before the first rising edge of SD_DQS and after the SD_DQS write preamble. The

remaining data beats will be valid for each subsequent SD_DQS edge

Data input skew is derived from each SD_DQS clock edge. It begins with a SD_DQS transition and ends when the last data

line becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or

other factors).

Data input hold is derived from each SD_DQS clock edge. It begins with a SD_DQS transition and ends when the first data

line becomes invalid.

6

7

Figure 13 shows a DDR SDRAM write cycle.

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

29

Preliminary—Subject to Change Without Notice

Preliminary Electrical Characteristics

DDR_CLKOUT

V_IX

V_ID

V_MP

V_IX

DDR_CLKOUT

Figure 12. DDR_CLKOUT and DDR_CLKOUT Crossover Timing

DD1

DD2

DDR_CLKOUT

DD3

DD5

SD_CSn,SD_WE,

SD_SRAS,SD_SCAS

CMD

ROW

DD4

DD6

A[13:0]

COL

DD7

DM[3:2]

SD_DQS[3:2]

D[31:16]

DD8

DD7

WD1 WD2 WD3 WD4

DD8

Figure 13. DDR Write Timing

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

30

Preliminary—Subject to Change Without Notice

Preliminary Electrical Characteristics

DD1

DD2

CLKOUT

DD3

DD5

CL=2

SD_CSn,SD_WE,

SD_SRAS,SD_SCAS

CMD

ROW

DD4

CL=2.5

A[13:0]

COL

DD9

DQS Read

Postamble

DQS Read

Preamble

SD_DQS[3:2]

D[31:16]

DD10

WD1 WD2 WD3 WD4

DQS Read

Preamble

DQS Read

Postamble

SD_DQS[3:2]

D[31:16]

WD1 WD2 WD3 WD4

Figure 14. DDR Read Timing

8.9

General Purpose I/O Timing

GPIO can be configured for certain pins of the QSPI, DDR Control, TIMERS, UARTS, FEC0, FEC1,

Interrupts and USB interfaces. When in GPIO mode the timing specification for these pins is given in

Table 16 and Figure 15.

Table 16. GPIO Timing

NUM

Characteristic

Symbol

Min

Max

Unit

G1 CLKOUT High to GPIO Output Valid

G2 CLKOUT High to GPIO Output Invalid

G3 GPIO Input Valid to CLKOUT High

G4 CLKOUT High to GPIO Input Invalid

t_CHPOV

t_CHPOI

t_PVCH

t_CHPI

—

1.0

9

10

—

ns

1.5

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

31

Preliminary—Subject to Change Without Notice

Preliminary Electrical Characteristics

CLKOUT

G2

G1

GPIO Outputs

GPIO Inputs

G3

G4

Figure 15. GPIO Timing

8.10 Reset and Configuration Override Timing

Table 17. Reset and Configuration Override Timing

1

(V = 2.7 to 3.6 V, V = 0 V, T = T to T )

DD

SS

L

H

A

NUM

Characteristic

Symbol

Min

Max

Unit

R1 RESET Input valid to CLKOUT High

R2 CLKOUT High to RESET Input invalid

R3 RESET Input valid Time ²

t_RVCH

t_CHRI

9

1.5

5

—

ns

t_RIVT

—

t_CYC

ns

R4 CLKOUT High to RSTOUT Valid

R5 RSTOUT valid to Config. Overrides valid

t_CHROV

t_ROVCV

t_COS

—

0

10

—

ns

R6 Configuration Override Setup Time to RSTOUT invalid

R7 Configuration Override Hold Time after RSTOUT invalid

R8 RSTOUT invalid to Configuration Override High Impedance

20

0

—

t_CYC

ns

t_COH

—

t_ROICZ

—

1 x t_CYC

ns

1

2

All AC timing is shown with respect to 50% OV_DDlevels unless otherwise noted.

During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted

asynchronously to the system. Thus, RESET must be held a minimum of 100 ns.

CLKOUT

R1

R2

R3

RESET

R4

RSTOUT

R8

R5

R6

R7

Configuration Overrides¹:

(RCON, Override pins])

1. Refer to the Coldfire Integration Module (CIM) section for more information.

RESET and Configuration Override Timing

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

32

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

Preliminary Electrical Characteristics

8.11 Fast Ethernet AC Timing Specifications

MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.

8.11.1 MII Receive Signal Timing (FECn_RXD[3:0], FECn_RXDV,

FECn_RXER, and FECn_RXCLK)

The receiver functions correctly up to a FECn_RXCLK maximum frequency of 25 MHz +1%. The

processor clock frequency must exceed twice the FECn_RXCLK frequency.

Table 18 lists MII receive channel timings.

Table 18. MII Receive Signal Timing

Num

Characteristic

Min

Max

Unit

M1

FECn_RXD[3:0], FECn_RXDV, FECn_RXER to

FECn_RXCLK setup

5

—

ns

M2

M3

M4

FECn_RXCLK to FECn_RXD[3:0], FECn_RXDV,

FECn_RXER hold

5

—

ns

FECn_RXCLK pulse width high

35%

65%

FECn_RXCLK

period

FECn_RXCLK pulse width low

FECn_RXCLK

period

Figure 16 shows MII receive signal timings listed in Table 18.

M4

M3

FECn_RXCLK (input)

FECn_RXD[3:0] (inputs)

FECn_RXDV

FECn_RXER

M1

M2

Figure 16. MII Receive Signal Timing Diagram

8.11.2 MII Transmit Signal Timing (FECn_TXD[3:0], FECn_TXEN,

FECn_TXER, FECn_TXCLK)

Table 19 lists MII transmit channel timings.

The transmitter functions correctly up to a FECn_TXCLK maximum frequency of 25 MHz +1%. The

processor clock frequency must exceed twice the FECn_TXCLK frequency.

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

33

Preliminary—Subject to Change Without Notice

Preliminary Electrical Characteristics

Table 19. MII Transmit Channel Timing

Num

Characteristic

Min

Max

Unit

M5

FECn_TXCLK to FECn_TXD[3:0], FECn_TXEN,

FECn_TXER invalid

5

—

ns

M6

FECn_TXCLK to FECn_TXD[3:0], FECn_TXEN,

FECn_TXER valid

—

25

ns

M7

M8

FECn_TXCLK pulse width high

FECn_TXCLK pulse width low

35%

65%

FECn_TXCLK period

Figure 17 shows MII transmit signal timings listed in Table 19.

M8

M7

FECn_TXCLK (input)

M5

FECn_TXD[3:0] (outputs)

FECn_TXEN

FECn_TXER

M6

Figure 17. MII Transmit Signal Timing Diagram

8.11.3 MII Async Inputs Signal Timing (FECn_CRS and FECn_COL)

Table 20 lists MII asynchronous inputs signal timing.

Table 20. MII Asynchronous Input Signal Timing

Num

Characteristic

Min

Max

Unit

M9

FECn_CRS, FECn_COL minimum pulse width

1.5

—

FECn_TXCLK period

Figure 18 shows MII asynchronous input timings listed in Table 20.

FECn_CRS

FECn_COL

M9

Figure 18. MII Async Inputs Timing Diagram

8.11.4 MII Serial Management Channel Timing (FECn_MDIO and

FECn_MDC)

Table 21 lists MII serial management channel timings. The FEC functions correctly with a maximum

MDC frequency of 2.5 MHz.

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

34

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

Preliminary Electrical Characteristics

Table 21. MII Serial Management Channel Timing

Num

Characteristic

Min

Max

Unit

M10 FECn_MDC falling edge to FECn_MDIO output invalid (minimum

0

—

ns

propagation delay)

M11 FECn_MDC falling edge to FECn_MDIO output valid (max prop delay)

M12 FECn_MDIO (input) to FECn_MDC rising edge setup

M13 FECn_MDIO (input) to FECn_MDC rising edge hold

M14 FECn_MDC pulse width high

—

10

25

—

ns

0

—

ns

40%

60%

MDC period

M15 FECn_MDC pulse width low

Figure 19 shows MII serial management channel timings listed in Table 21.

M14

M15

FECn_MDC (output)

M10

FECn_MDIO (output)

M11

FECn_MDIO (input)

M13

Figure 19. MII Serial Management Channel Timing Diagram

M12

8.11.5 USB Interface AC Timing Specifications

Table 22 lists USB Interface timings.

Table 22. USB Interface Timing

Num

Characteristic

USB_CLK frequency of operation

Min

Max

Units

US1

US2

US3

US4

48

—

45

48

2

MHz

ns

USB_CLK fall time (V_IH= 2.4 V to V_IL= 0.5 V)

USB_CLK rise time (V_IL= 0.5 V to V_IH= 2.4 V)

2

ns

USB_CLK duty cycle (at 0.5 x O V_DD

)

55

%

Data Inputs

USB_RP, USB_RN, USB_RXD valid to USB_CLK high

US5

6

—

ns

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

35

Preliminary—Subject to Change Without Notice

Preliminary Electrical Characteristics

Table 22. USB Interface Timing (continued)

Num

Characteristic

Min

Max

Units

US6

USB_CLK high to USB_RP, USB_RN, USB_RXD invalid

Data Outputs

6

—

ns

US7

US8

USB_CLK high to USB_TP, USB_TN, USB_SUSP valid

USB_CLK high to USB_TP, USB_TN, USB_SUSP invalid

—

3

12

—

ns

Figure 20 shows USB interface timings listed in Table 22.

US1

USB_CLK

US8

US7

USB Outputs

US5

US6

USB Inputs

t_rise

V_h= V_IH

Input Rise Time

Input Fall Time

V_l= V_IL

t_fall

V_h= V_IH

V_l= V_IL

Figure 20. USB Signals Timing Diagram

2

8.12 I C Input/Output Timing Specifications

2

Table 23 lists specifications for the I C input timing parameters shown in Figure 21.

2

Table 23. I C Input Timing Specifications between I2C_SCL and I2C_SDA

Num

Characteristic

Start condition hold time

Min

Max

Units

I1

I2

I3

I4

I5

I6

I7

2 x t_CYC

—

1

ns

ms

ns

ms

ns

Clock low period

8 x t_CYC

I2C_SCL/I2C_SDA rise time (V_IL= 0.5 V to V_IH= 2.4 V)

Data hold time

—

0

—

1

I2C_SCL/I2C_SDA fall time (V_IH= 2.4 V to V_IL= 0.5 V)

Clock high time

4 x t_CYC

0

—

Data setup time

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

36

Preliminary—Subject to Change Without Notice

Preliminary Electrical Characteristics

Table 23. I C Input Timing Specifications between I2C_SCL and I2C_SDA (continued)

2

Num

Characteristic

Min

Max

Units

I8

I9

Start condition setup time (for repeated start condition only)

Stop condition setup time

2 x t_CYC

—

ns

2

Table 24 lists specifications for the I C output timing parameters shown in Figure 21.

2

Table 24. I C Output Timing Specifications between I2C_SCL and I2C_SDA

Num

Characteristic

Start condition hold time

Min

Max

Units

I1¹

6 x t_CYC

10 x t_CYC

—

ns

µs

I2 ¹

I3 ²

Clock low period

I2C_SCL/I2C_SDA rise time

(V_IL= 0.5 V to V_IH= 2.4 V)

I4 ¹

I5 ³

Data hold time

7 x t_CYC

—

3

ns

I2C_SCL/I2C_SDA fall time

(V_IH= 2.4 V to V_IL= 0.5 V)

I6 ¹

I7 ¹

I8 ¹

Clock high time

Data setup time

10 x t_CYC

2 x t_CYC

—

ns

Start condition setup time (for repeated start

condition only)

20 x t_CYC

I9 ¹

Stop condition setup time

10 x t_CYC

—

ns

1

Note: Output numbers depend on the value programmed into the IFDR; an IFDR programmed

with the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in

Table 24. The I²C interface is designed to scale the actual data transition time to move it to the

middle of the I2C_SCL low period. The actual position is affected by the prescale and division

values programmed into the IFDR; however, the numbers given in Table 24 are minimum values.

2

3

Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only

actively drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external

signal capacitance and pull-up resistor values.

Specified at a nominal 50-pF load.

Figure 21 shows timing for the values in Table 23 and Table 24.

I2

I6

I5

SCL

SDA

I3

I1

I4

I8

I9

I7

2

Figure 21. I C Input/Output Timings

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

37

Preliminary—Subject to Change Without Notice

Preliminary Electrical Characteristics

8.13 DMA Timers Timing Specifications

Table 25. Timer Module AC Timing Specifications

Name

Characteristic ¹

Min

Max

Unit

T1

T2

T0IN / T1IN / T2IN / T3IN cycle time

T0IN / T1IN / T2IN / T3IN pulse width

3 x t_CYC

1 x t_CYC

—

ns

1

All timing references to CLKOUT are given to its rising edge.

8.14 QSPI Electrical Specifications

Table 26. QSPI Modules AC Timing Specifications

Name

Characteristic

Min

Max

Unit

QS1

QS2

QS3

QS4

QS5

QSPI_CS[3:0] to QSPI_CLK

1

—

2

510

10

—

t_CYC

ns

QSPI_CLK high to QSPI_DOUT valid.

QSPI_CLK high to QSPI_DOUT invalid (Output hold)

QSPI_DIN to QSPI_CLK (Input setup)

QSPI_DIN to QSPI_CLK (Input hold)

ns

9

—

ns

9

—

ns

QS1

QSPI_CS[3:0]

QSPI_CLK

QSPI_DOUT

QSPI_DIN

QS2

QS3

QS4

QS5

Figure 22. QSPI Timing

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

38

Preliminary—Subject to Change Without Notice

Preliminary Electrical Characteristics

8.15 JTAG and Boundary Scan Timing

Table 27. JTAG and Boundary Scan Timing

Num

Characteristics¹

TCLK Frequency of Operation

Symbol

Min

Max

Unit

J1

J2

f_JCYC

t_JCYC

DC

1/4

—

3

f_sys/2

ns

TCLK Cycle Period

4 x t_CYC

J3

TCLK Clock Pulse Width

t_JCW

26

0

J4

TCLK Rise and Fall Times

t_JCRF

J5

Boundary Scan Input Data Setup Time to TCLK Rise

Boundary Scan Input Data Hold Time after TCLK Rise

TCLK Low to Boundary Scan Output Data Valid

TCLK Low to Boundary Scan Output High Z

TMS, TDI Input Data Setup Time to TCLK Rise

TMS, TDI Input Data Hold Time after TCLK Rise

TCLK Low to TDO Data Valid

t_BSDST

t_BSDHT

t_BSDV

4

—

33

—

26

8

J6

26

0

J7

J8

t_BSDZ

0

J9

t_TAPBST

t_TAPBHT

t_TDODV

t_TDODZ

t_TRSTAT

t_TRSTST

4

J10

J11

J12

J13

J14

10

0

TCLK Low to TDO High Z

0

TRST Assert Time

100

10

—

TRST Setup Time (Negation) to TCLK High

1

JTAG_EN is expected to be a static signal. Hence, it is not associated with any timing.

J2

J3

V_IH

TCLK

(input)

V_IL

J4

Figure 23. Test Clock Input Timing

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

39

Preliminary—Subject to Change Without Notice

Preliminary Electrical Characteristics

TCLK

V_IL

V_IH

J5

Input Data Valid

J6

Data Inputs

J7

J8

Data Outputs

Output Data Valid

Data Outputs

J7

Output Data Valid

Figure 24. Boundary Scan (JTAG) Timing

TCLK

V_IL

V_IH

J9

Input Data Valid

J10

TDI

TMS

J11

TDO

Output Data Valid

J12

J11

TDO

Output Data Valid

Figure 25. Test Access Port Timing

TCLK

TRST

14

13

Figure 26. TRST Timing

8.16 Debug AC Timing Specifications

Table 28 lists specifications for the debug AC timing parameters shown in Figure 28.

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

40

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

Preliminary Electrical Characteristics

Table 28. Debug AC Timing Specification

166 MHz

Units

Num

Characteristic

Min

Max

D0

PSTCLK cycle time

—

0.5

—

t_CYC

ns

D1

D2

D3

D4 ¹

D5

D6

D7

D8

PST, DDATA to PSTCLK setup

CLKOUT to PST, DDATA hold

DSI-to-DSCLK setup

4

1.0

—

1 x t_CYC

4 x t_CYC

5 x t_CYC

4

—

DSCLK-to-DSO hold

—

DSCLK cycle time

—

BKPT input data setup time to PSTCLK Rise

BKPT input data hold time to PSTCLK Rise

PSTCLK high to BKPT high Z

—

1.5

—

0.0

10.0

1

DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input

relative to the rising edge of PSTCLK.

Figure 27 shows real-time trace timing for the values in Table 28.

PSTCLK

D1

D2

PST[3:0]

DDATA[3:0]

Figure 27. Real-Time Trace AC Timing

Figure 28 shows BDM serial port AC timing for the values in Table 28.

PSTCLK

D5

DSCLK

D3

DSI

Current

Past

DSO

Current

Figure 28. BDM Serial Port AC Timing

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

41

Preliminary—Subject to Change Without Notice

Documentation

9

Documentation

Documentation regarding the MCF5275 and their development support tools is available from a local

Freescale distributor, a Freescale semiconductor sales office, the Freescale Literature Distribution Center,

or through the Freescale web address at http://www.freescale.com/coldfire.

10 Revision History

Table 29 provides a revision history for this hardware specification.

Table 29. Document Revision History

Rev. No.

Substantive Change(s)

0

1

• Initial release.

• Added Figure 6.

1.1

• Removed duplicate information in the module description sections. The information is all in the

Signals Description Table.

1.2

• Removed Overview, Features, Signal Descriptions, Modes of Operation, and Address

Multiplexing sections. This information can be found in the MCF5275 Reference Manual.

• Removed list of documentation in Section 9, “Documentation.”. An up-to-date list is always

available on our web site.

• Changed CLKOUT -> PSTCLK in Section 8.16, “Debug AC Timing Specifications.”

• Table 10: Update V_DDspec from 1.35-1.65 to 1.4-1.6.

• Table 13: Timings B6a, B6b, B6c, B7, B7a, B9, B12 updated:

B6a, B6b, B6c maximum changed from “0.5t_CYC+ 5” to “0.5t_CYC+ 5.5”

B7, B7a minimum changed from “0.5t_CYC+ 1.5” to “0.5t_CYC+ 1.0”

B9, B11 minimum changed from “1.5” to “1.0”

1.3

2

• Added Section 5.2.1, “Supply Voltage Sequencing and Separation Cautions.”

• Added thermal characteristics for 196 MAPBGA in Table 8.

• Updated package dimensions drawing, Figure 6.

• Removed second sentence from Section 8.11.1, “MII Receive Signal Timing

(FECn_RXD[3:0], FECn_RXDV, FECn_RXER, and FECn_RXCLK),” and Section 8.11.2, “MII

Transmit Signal Timing (FECn_TXD[3:0], FECn_TXEN, FECn_TXER, FECn_TXCLK),”

regarding no minimum frequency requirement for TXCLK.

• Removed third and fourth paragraphs from Section 8.11.2, “MII Transmit Signal Timing

(FECn_TXD[3:0], FECn_TXEN, FECn_TXER, FECn_TXCLK),” as this feature is not

supported on this device.

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

42

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

Revision History

MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2

Freescale Semiconductor

43

Preliminary—Subject to Change Without Notice

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Document Number: MCF5275EC

Rev. 2

08/2006

Preliminary—Subject to Change Without Notice


型号：	MCF5275
厂家：	Freescale
描述：	Integrated Microprocessor Family Hardware Specification 集成的微处理器系列硬件规格微处理器
文件：	总44页 (文件大小：1246K)
中文：	中文翻译
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