MCF53014CMJ240J [FREESCALE]
Version 3 ColdFire? core with EMAC; 第3版的ColdFire ?核心与EMAC型号: | MCF53014CMJ240J |
厂家: | Freescale |
描述: | Version 3 ColdFire? core with EMAC |
文件: | 总62页 (文件大小:2881K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MCF53017
Rev. 5, 3/2010
MCF53017
LQFP–208
28 x 28
MAPBGA–256
17 x 17
MCF5301x Data Sheet
Features
®
• Version 3 ColdFire core with EMAC
• Up to 211 Dhrystone 2.1 MIPS @ 240 MHz
• 16 KBytes unified instruction/data cache
• 128 KBytes internal SRAM with standby power supply
support
• Crossbar switch technology (XBS) for concurrent access to
peripherals or RAM from multiple bus masters
• Enhanced Secure Digital Host Controller (eSDHC)
– Supports CE-ATA, SD Memory, miniSD Memory,
SDIO, miniSDIO, SD Combo, MMC, MMC plus, MMC
4x, and MMC RS cards
• Two ISO7816 smart card interfaces
• IC identification module
• Voice-band audio codec with integrated speaker,
microphone, headphone, and handset amplifiers
• 16- or 32-bit SDR, 16-bit DDR/mobile-DDR SDRAM
controller
• USB 2.0 On-the-Go controller
• USB host controller
• 2 10/100 Ethernet MACs
• Coprocessor for acceleration of the DES, 3DES, AES,
MD5, and SHA-1 algorithms
• Random number generator
• 16-channel DMA controller
• Synchronous serial interface
• 4 periodic interrupt timers
• 4 32-bit timers with DMA support
• Real-time clock (RTC) module with standby support
• DMA-supported serial peripheral interface (DSPI)
• 3 UARTs
2
• I C bus interface
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
© Freescale Semiconductor, Inc., 2010. All rights reserved.
Preliminary—Subject to Change Without Notice
Table of Contents
1
2
3
MCF5301x Family Comparison . . . . . . . . . . . . . . . . . . . . . . . .4
5.11 SSI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . 34
5.12 I2C Input/Output Timing Specifications . . . . . . . . . . . . 35
5.13 Fast Ethernet AC Timing Specifications . . . . . . . . . . . 37
5.13.1 Receive Signal Timing Specifications . . . . . . . 37
5.13.2 Transmit Signal Timing Specifications . . . . . . . 37
5.13.3 Asynchronous Input Signal Timing Specifications38
5.13.4 MII Serial Management Timing Specifications. 38
5.14 32-Bit Timer Module Timing Specifications . . . . . . . . . 39
5.15 DSPI Timing Specifications . . . . . . . . . . . . . . . . . . . . . 39
5.16 eSDHC Electrical Specifications . . . . . . . . . . . . . . . . . 41
5.16.1 eSDHC Timing . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.16.2 eSDHC Electrical DC Characterisics . . . . . . . . 42
5.17 SIM Electrical Specifications . . . . . . . . . . . . . . . . . . . . 43
5.17.1 General Timing Requirements . . . . . . . . . . . . . 43
5.17.2 Reset Sequence. . . . . . . . . . . . . . . . . . . . . . . . 44
5.17.3 Power Down Sequence . . . . . . . . . . . . . . . . . . 45
5.18 IIM/Fusebox Electrical Specifications . . . . . . . . . . . . . 46
5.19 Voice Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.19.1 Voice Codec ADC Specifications . . . . . . . . . . . 47
5.19.2 Voice Codec DAC Specifications . . . . . . . . . . . 51
5.20 Integrated Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.20.1 Speaker Amplifier. . . . . . . . . . . . . . . . . . . . . . . 55
5.20.2 Handset Amplifier. . . . . . . . . . . . . . . . . . . . . . . 56
5.20.3 Headphone Amplifier . . . . . . . . . . . . . . . . . . . . 57
5.20.4 Microphone Amplifier . . . . . . . . . . . . . . . . . . . . 57
5.21 JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . 58
5.22 Debug AC Timing Specifications . . . . . . . . . . . . . . . . . 60
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Hardware Design Considerations. . . . . . . . . . . . . . . . . . . . . . .5
3.1 PLL Power Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.2 USB Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
3.3 Supply Voltage Sequencing . . . . . . . . . . . . . . . . . . . . . .6
3.3.1 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . .7
3.3.2 Power Down Sequence . . . . . . . . . . . . . . . . . . . .7
3.4 Power Consumption Specifications. . . . . . . . . . . . . . . . .8
Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .9
4.1 Signal Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4.2 Pinout—208 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.3 Pinout–256 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . .18
Preliminary Electrical Characteristics . . . . . . . . . . . . . . . . . . .19
5.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .20
5.3 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
5.4 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .21
5.4.1 PLL Power Filtering . . . . . . . . . . . . . . . . . . . . . .22
5.4.2 USB Power Filtering. . . . . . . . . . . . . . . . . . . . . .22
5.4.3 Supply Voltage Sequencing and Separation
Cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
5.5 Oscillator and PLL Electrical Characteristics . . . . . . . .24
5.6 External Interface Timing Characteristics . . . . . . . . . . .25
5.6.1 FlexBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
5.7 SDRAM Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
5.7.1 SDR SDRAM AC Timing Characteristics. . . . . .27
5.7.2 DDR SDRAM AC Timing Characteristics . . . . .30
5.8 General Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . .32
5.9 Reset and Configuration Override Timing. . . . . . . . . . .33
5.10 USB On-The-Go . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
4
5
6
7
8
MCF5301x Data Sheet, Rev. 5
2
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
MCF53017
Version 3 ColdFire Core
JTAG
Oscillator
USB Host
PLL
16K
Instruction/
Data
Cache
EMAC
BDM
CAU
2 FECs
Hardware
Divide
128K
SRAM
eDMA
eSDHC
USB OTG
Crossbar Switch (XBS)
Splitter
Peripheral Bridge
Smart Card
Codec
IIM
DSPI
Interface
SDRAM
Controller
FlexBus
RTC &
Oscillator
SSI
RNG
I2C
GPIO
4 DMA
Timers
4 PITs
2 INTCs
2 EPORTs
3 UARTs
LEGEND
BDM
CAU
– Background debug module
IIM
– IC identification module
– Interrupt controller
– Cryptography acceleration unit
– DMA serial peripheral interface
– Enhanced direct memory access module
– Enhanced Secure Digital host controller
– Enchanced multiply-accumulate unit
– Edge port module
– Fast Ethernet Controller
– General purpose input/output module
– Inter-Integrated Circuit
INTC
JTAG
PCI
DSPI
eDMA
eSDHC
EMAC
EPORT
FEC
– Joint Test Action Group interface
– Peripheral Component Interconnect
– Programmable interrupt timers
– Phase locked loop module
– Random number generator
– Real time clock
PIT
PLL
RNG
RTC
SSI
GPIO
– Synchronous serial interface
I2C
USB OTG – Universal Serial Bus On-the-Go controller
MCF5301x Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
3
MCF5301x Family Comparison
1
MCF5301x Family Comparison
The following table compares the various device derivatives available within the MCF5301x family.
Table 1. MCF5301x Family Configurations
Module
Version 3 ColdFire Core with EMAC (enhanced
multiply-accumulate unit)
•
•
•
•
•
•
•
•
Core (system) clock
up to 240 MHz
up to 80 MHz
Peripheral and external bus clock
(Core clock ÷ 3)
Performance (Dhrystone/2.1 MIPS)
Unified data/instruction cache
Static RAM (SRAM)
up to 211
16 Kbytes
128 Kbytes
Voice-over-IP software
Cryptography acceleration unit (CAU)
Random number generator
Smart card interface (SIM)
Voice-band audio codec
Integrated audio amplifiers
IC identification module (IIM)
Enhanced Secure Digital host controller (eSDHC)
SDR/DDR SDRAM controller
FlexBus external interface
USB 2.0 On-the-Go
—
—
—
—
•
•
•
•
•
—
—
—
—
•
•
•
•
•
—
—
—
—
•
•
1 port
2 ports
•
•
•
•
•
•
•
•
•
•
•
•
—
—
—
—
2 Kbits
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
USB 2.0 Host
—
•
—
•
—
•
—
•
•
•
•
•
Synchronous serial interface (SSI)
Fast Ethernet controller (FEC)
UARTs
•
•
•
•
2
3
•
2
3
•
2
3
•
2
3
•
2
3
•
2
3
•
2
3
•
2
3
•
I2C
DSPI
•
•
•
•
•
•
•
•
Real-time clock
•
•
•
•
•
•
•
•
32-bit DMA timers
4
•
4
•
4
•
4
•
4
•
4
•
4
•
4
•
Watchdog timer (WDT)
Periodic interrupt timers (PIT)
Edge port module (EPORT)
Interrupt controllers (INTC)
4
•
4
•
4
•
4
•
4
•
4
•
4
•
4
•
2
2
2
2
2
2
2
2
MCF5301x Data Sheet, Rev. 5
Preliminary—Subject to Change Without Notice
4
Freescale Semiconductor
Ordering Information
Table 1. MCF5301x Family Configurations (continued)
Module
16-channel direct memory access (DMA)
General purpose I/O Module (GPIO)
JTAG - IEEE® 1149.1 Test Access Port
Package
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
208 LQFP
256 MAPBGA
2
Ordering Information
Table 2. Orderable Part Numbers
Freescale Part Number
Description
Package
Speed
Temperature
MCF53010CQT240
MCF53011CQT240
MCF53012CQT240
MCF53013CQT240
MCF53014CMJ240J
MCF53015CMJ240J
MCF53016CMJ240J
MCF53017CMJ240J
MCF53010 Microprocessor
MCF53011 Microprocessor
MCF53012 Microprocessor
MCF53013 Microprocessor
MCF53014 Microprocessor
MCF53015 Microprocessor
MCF53016 Microprocessor
MCF53017 Microprocessor
208 LQFP
240 MHz
–40° to +85° C
256 MAPBGA
The following are not available from Freescale for import or sale in the United States prior to September 2010
MCF53014CMJ240
MCF53015CMJ240
MCF53016CMJ240
MCF53017CMJ240
MCF53014 Microprocessor
MCF53015 Microprocessor
MCF53016 Microprocessor
MCF53017 Microprocessor
256 MAPBGA
240 MHz
–40° to +85° C
3
Hardware Design Considerations
3.1
PLL Power Filtering
To further enhance noise isolation, an external filter is strongly recommended for PLL analog V pins. The filter shown in
DD
Figure 1 should be connected between the board IV and the PLLV pins. The resistor and capacitors should be placed as
DD
DD
close to the dedicated PV pin as possible. The 10-ohm resistor in the given filter is required, do not implement the filter circuit
DD
using only capacitors. The PV pins draw very little current, so concerns regarding voltage loss across the 10-ohm resistor are
DD
not valid.
MCF5301x Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
5
Hardware Design Considerations
10 Ω
Board IVDD
PLL VDD Pin
10 µF
0.1 µF
GND
Figure 1. System PLL V Power Filter
DD
3.2
USB Power Filtering
To minimize noise, external filters are required for each of the USB power pins. The filter shown in Figure 2 should be
connected between the board EV and each of the USBV pins. The resistor and capacitors should be placed as close to the
DD
DD
dedicated USBV pin as possible.
DD
Board EVDD
USB VDD Pin
0 Ω
10 µF
0.1 µF
GND
Figure 2. USB V Power Filter
DD
NOTE
In addition to the above filter circuitry, a 0.01 F capacitor is also recommended in parallel
with those shown.
3.3
Supply Voltage Sequencing
Figure 3 shows situations in sequencing the I/O V (EV ), SDRAM V (SDV ), PLL V (PV ), and internal logic /
DD
DD
DD
DD
DD
DD
core V (IV ). The relationship between SDV and EV is non-critical during power-up and power-down sequences.
DD
DD
DD
DD
Both SDV (2.5V or 1.8V) and EV are specified relative to IV .
DD
DD
DD
MCF5301x Data Sheet, Rev. 5
Preliminary—Subject to Change Without Notice
6
Freescale Semiconductor
Hardware Design Considerations
EVDD, USBVDD (3.3V)
SDVDD (2.5V - DDR)
3.3V
2.5V
Supplies Stable
1.8V
1.2V
SDVDD (1.8V - DDR)
IVDD, PVDD
1
2
0
Time
Notes:
1
IVDD should not exceed EVDD, SDVDD or PVDD by more than 0.4V at any time, including power-up.
Recommended that IVDD/PVDD should track EVDD/SDVDD up to 0.9V then separate for completion of ramps
2
3
Input voltage must not be greater than the supply voltage (EVDD, SDVDD, IVDD, or PVDD) by more than 0.5V
at any time, including during power-up.
4
Use 1 microsecond or slower rise time for all supplies.
Figure 3. Supply Voltage Sequencing and Separation Cautions
3.3.1
Power Up Sequence
If EV /SDV are powered up with the IV at 0V, then the sense circuits in the I/O pads will cause all pad output drivers
DD
DD
DD
connected to the EV /SDV to be in a high impedance state. There is no limit on how long after EV /SDV powers up
DD
DD
DD
DD
before IV must power up. IV should not lead the EV , SDV or PV by more than 0.4V during power ramp up or
DD
DD
DD
DD
DD
there will be high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 1
microsecond to avoid turning on the internal ESD protection clamp diodes.
The recommended power up sequence is as follows:
1. Use 1 microsecond or slower rise time for all supplies.
2. IV /PV and EV /SDV should track up to 0.9V and then separate for the completion of ramps with
DD
DD
DD
DD
EV /SDV going to the higher external voltages. One way to accomplish this is to use a low drop-out voltage
DD
DD
regulator.
3.3.2
Power Down Sequence
If IV /PV are powered down first, then sense circuits in the I/O pads will cause all output drivers to be in a high impedance
DD
DD
state. There is no limit on how long after IV and PV power down before EV or SDV must power down. IV should
DD
DD
DD
DD
DD
not lag EV , SDV , or PV going low by more than 0.4V during power down or there will be undesired high current in
DD
DD
DD
the ESD protection diodes. There are no requirements for the fall times of the power supplies.
The recommended power down sequence is as follows:
1. Drop IV /PV to 0V.
DD
DD
2. Drop EVDD/SDVDD supplies.
MCF5301x Data Sheet, Rev. 5
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
7
Hardware Design Considerations
3.4
Power Consumption Specifications
Estimated maximum RUN mode power consumption measurements are shown in the below figure.
Estimated Power Consumption vs. Core Frequency
300
250
200
150
100
50
0
0
40
80
120
160
200
240
Core Frequency (MHz)
Figure 4. Estimated Maximum RUN Mode Power Consumption
Table 3 lists estimated maximum power and current consumption for the device in various operating modes.
Table 3. Estimated Maximum Power Consumption Specifications
Characteristic
Symbol Typical
Max
Unit
Run Mode — Total Power Dissipation
—
—
—
TBD
TBD
TBD
mW
mW
mW
Static
Dynamic
Core Operating Supply Current 1
Run Mode
IDD
EIDD
—
—
—
—
82.9
mA
Pad Operating Supply Current
Run Mode (application dependent)
Wait Mode
TBD
TBD
TBD
mA
mA
mA
Stop Mode
1
Current measured at maximum system clock frequency, all modules active, and default drive
strength with matching load.
MCF5301x Data Sheet, Rev. 5
8
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Pin Assignments and Reset States
Table 4. Current Measurementas at Different VCO vs. Core Frequencies
480VCO, 240MHz
core
240VCO, 120MHz
core
480VCO, 120MHz
core
480VCO, 48MHz
core
Limp Mode, 20HMHz
crystal
Stop Mode
Executing
Run
55.3mA
39.5mA
16.28mA
16.19mA
8.41mA
8.13mA
1.83mA
0.65mA
28.36mA
20.3mA
8.53mA
8.53mA
4.60mA
4.48mA
1.86mA
0.66mA
30.00mA
22.02mA
10.23mA
10.18mA
6.29mA
6.15mA
1.87mA
0.67mA
13.6mA
10.29mA
5.53mA
5.55mA
3.90mA
3.88mA
1.82mA
0.67mA
5.90mA
4.42mA
2.43mA
2.41mA
1.78mA
1.77mA
1.76mA
0.65mA
Wait
Doze
Stop(0)
Stop(1)
Stop(2)
Stop(3)
4
Pin Assignments and Reset States
4.1
Signal Multiplexing
The following table lists all the MCF5301x pins grouped by function. The “Dir” column is the direction for the primary function
of the pin only. Refer to Section 4.2, “Pinout—208 LQFP,” and Section 4.3, “Pinout–256 MAPBGA,” for package diagrams.
For a more detailed discussion of the MCF3xxx signals, consult the MCF5301x Reference Manual (MCF53017RM).
NOTE
In this table and throughout this document a single signal within a group is designated
without square brackets (i.e., FB_A23), while designations for multiple signals within a
group use brackets (i.e., FB_A[23:21]) and is meant to include all signals within the two
bracketed numbers when these numbers are separated by a colon.
NOTE
The primary functionality of a pin is not necessarily its default functionality. Most pins that
are muxed with GPIO will default to their GPIO functionality. See Table 5 for a list of the
exceptions.
Table 5. Special-Case Default Signal Functionality
Pin
Default Signal
FB_BE/BWE[3:0]
FB_CS[3:0]
FB_OE
FB_BE/BWE[3:0]
FB_CS[3:0]
FB_OE
FB_TA
FB_TA
FB_R/W
FB_R/W
FB_TS
FB_TS
MCF5301x Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
9
Pin Assignments and Reset States
Table 6. MCF5301x Signal Information and Muxing
MCF53010
MCF53011
MCF53012
MCF53013
MCF53014
MCF53015
MCF53016
MCF53017
Signal Name
GPIO
Alternate 1
Alternate 2
208 LQFP
256 MAPBGA
Reset
I
EVDD
EVDD
41
42
M3
N1
RESET
—
—
—
—
—
—
U
O
RSTOUT
—
Clock
I
EVDD
EVDD
49
50
T2
T3
EXTAL
XTAL
—
—
—
—
—
—
—
U3
O
Mode Selection
—
I
EVDD
55, 17
J5, G5
BOOTMOD[1:0]
—
—
—
FlexBus
O
O
O
O
O
O
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
115, 114
113–108
107, 106
105–103
100
P16, N16
R16, N14, N15, P15-13
R15, R14
FB_A[23:22]
FB_A[21:16]
FB_A[15:14]
FB_A[13:11]
FB_A10
—
—
—
—
—
—
FB_CS[3:2]
—
—
—
—
—
—
—
—
—
—
—
—
—
SD_BA[1:0]
SD_A[13:11]
—
N13, R12, R13
N12
99–97
95–89
P12, T14, T15, R11, P11,
N11, T13, R10, T11, T12
FB_A[9:0]
SD_A[9:0]
I/O SDVDD 208–198, 57–62, B3, A2, D6, C5, B4, A3,
FB_D[31:16]
FB_D[15:0]
—
—
SD_D[31:16]
FB_D[31:16]
—
—
—
—
64, 65
B5, C6, D12, C14, B14,
C13, D11, B13, A14, A13
I/O SDVDD 182–189, 177–170 B9, A9, A8, D7, B8, C8,
D8, B7, C10, A10, B10,
D10, C11, A11, B11, A12
O
O
O
O
O
O
I
SDVDD
153
D13
FB_CLK
FB_BE/BWE[3:0]
FB_CS[5:4]
FB_CS1
—
—
SD_DQM[3:0]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
U
SDVDD 197, 166, 179, 178
A4, B12, C9, D9
PBE[3:0]
PCS[5:4]
PCS1
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
—
5
B6, C7
D2
SD_CS1
FB_CS4
—
6
C2
FB_CS0
PCS0
1
D4
FB_OE
PFBCTL3
PFBCTL2
PFBCTL1
PFBCTL0
3
B2
FB_TA
—
O
O
2
C3
FB_R/W
—
—
—
4
D3
FB_TS
DACK0
SDRAM Controller
O
SDVDD
206
C4
SD_A10
—
—
—
—
MCF5301x Data Sheet, Rev. 5
Preliminary—Subject to Change Without Notice
10
Freescale Semiconductor
Pin Assignments and Reset States
Table 6. MCF5301x Signal Information and Muxing (continued)
MCF53010
MCF53014
MCF53015
MCF53016
MCF53017
MCF53011
MCF53012
MCF53013
Signal Name
GPIO
Alternate 1
Alternate 2
208 LQFP
256 MAPBGA
O
O
O
O
O
O
O
I
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
154
D15
SD_CAS
SD_CKE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
151
190
B15
A7
SD_CLK
191
A6
SD_CLK
155
A15
C12, A5
C15
D5
SD_CS0
196, 167
152
SD_DQS[1:0]
SD_RAS
207
SD_SDR_DQS
SD_WE
O
150
D14
External Interrupts Port 14,5
I
I
EVDD
EVDD
—
—
H1, H4-2
IRQ1DEBUG[7:4]
IRQ1DEBUG[3:0]
PIRQ1DEBUG
[7:4]
DDATA[3:0]
—
—
—
K14, H14, K15, J13
PIRQ1DEBUG
[3:0]
PST[3:0]
—
I
I
I
I
I
I
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
29
30
J1
J2
IRQ1FEC7
IRQ1FEC6
PIRQ1FEC7
PIRQ1FEC6
RMII1_CRS_DV
RMII1_RXER
MII0_CRS
MII0_RXCLK
MII0_TXCLK
—
—
—
—
D
31
K4
IRQ1FEC5
PIRQ1FEC5
RMII1_TXEN
32
J3
IRQ1FEC4
PIRQ1FEC4
RMII1_REF_CLK
RMII1_RXD[1:0]
RMII1_TXD[1:0]
33, 34
35, 36
J4, K1
K2, L1
IRQ1FEC[3:2]
IRQ1FEC[1:0]
PIRQ1FEC[3:2]
PIRQ1FEC[1:0]
MII0_RXD[3:2]
MII0_TXD[3:2]
—
—
External Interrupts Port 05
I
I
I
I
EVDD
EVDD
EVDD
EVDD
10
—
19
11
E4
L13
D1
F4
IRQ07
IRQ06
IRQ04
IRQ01
PIRQ07
PIRQ06
PIRQ04
PIRQ01
—
—
U
U
U
U
—
USB_CLKIN
DREQ0
DREQ1
—
—
Enhanced Secure Digital Host Controller
I/O
I/O
I/O
O
EVDD
EVDD
EVDD
EVDD
60
61–63
59
N4
R5, N6, N5
R4
SDHC_DAT3
SDHC_DAT[2:0]
SDHC_CMD
SDHC_CLK
PSDHC5
PSDHC[4:2]
PSDHC1
—
—
—
—
—
—
—
—
UD
U
U
58
R3
PSDHC0
—
MCF5301x Data Sheet, Rev. 5
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
11
Pin Assignments and Reset States
Table 6. MCF5301x Signal Information and Muxing (continued)
MCF53010
MCF53014
MCF53015
MCF53016
MCF53017
MCF53011
MCF53012
MCF53013
Signal Name
GPIO
Alternate 1
Alternate 2
208 LQFP
256 MAPBGA
Codec
I
I
85
84
86
75
67
81
79
78
82
P10
P9
N9
R7
R6
P6
P8
P7
N7
CODEC_ADCN
CODEC_ADCP
CODEC_BGRVREF
CODEC_DACN
CODEC_DACP
CODEC_REGBYP
CODEC_REFN
CODEC_REFP
CODEC_VAG
—
—
—
—
—
—
—
—
—
AMP_MICN
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AMP_MICP
I
—
O
O
I
AMP_HSN
AMP_HSP
—
—
—
—
I
I
I
Amplifiers
O
O
O
O
—
—
—
—
R9
R8
T9
T7
AMP_HPDUMMY
AMP_HPOUT
AMP_SPKRN
AMP_SPKRP
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Smart Card interface 1
I/O
O
EVDD
EVDD
EVDD
EVDD
EVDD
141
142
144
145
143
E14
D16
E13
E15
F13
SIM1_DATA
SIM1_VEN
SIM1_RST
SIM1_PD
PSIM14
PSIM13
PSIM12
PSIM11
PSIM10
SSI_TXD
SSI_RXD
SSI_FS
U1TXD
U1RXD
U1RTS
U1CTS
—
UD
UD
—
O
O
SSI_BCLK
SSI_MCLK
—
O
SIM1_CLK
—
Smart Card interface 0
I/O
O
EVDD
EVDD
EVDD
EVDD
EVDD
L3
M2
SIM0_DATA
SIM0_VEN
SIM0_RST
SIM0_PD
PSIM04
PSIM03
PSIM02
PSIM01
PSIM00
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
O
F16
L14
M16
O
O
SIM0_CLK
USB On-the-Go
O
O
USB
VDD
148
149
C16
B16
USBO_DM
USBO_DP
—
—
—
—
—
—
—
USB
VDD
—
MCF5301x Data Sheet, Rev. 5
Preliminary—Subject to Change Without Notice
12
Freescale Semiconductor
Pin Assignments and Reset States
Table 6. MCF5301x Signal Information and Muxing (continued)
MCF53010
MCF53014
MCF53015
MCF53016
MCF53017
MCF53011
MCF53012
MCF53013
Signal Name
GPIO
Alternate 1
Alternate 2
208 LQFP
256 MAPBGA
USB Host
O
O
USB
VDD
—
—
B1
C1
USBH_DM
USBH_DP
—
—
—
—
—
—
—
USB
VDD
—
FEC 1
EVDD
EVDD
22
23
E1
F1
RMII1_MDC
RMII1_MDIO
PFECI2C5
PFECI2C4
—
—
MII0_TXER
MII0_COL
—
—
FEC 0
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
131
130, 129
127
G16
H15, H16
J16
RMII0_CRS_DV
RMII0_RXD[1:0]
RMII0_RXER
RMII0_TXD[1:0]
RMII0_TXEN
RMII0_MDC
PFEC06
PFEC0[5:4]
PFEC03
—
—
—
—
—
—
—
MII0_RXDV
MII0_RXD[1:0]
MII0_RXER
MII0_TXD[1:0]
MII0_TXEN
MII0_MDC
—
—
—
—
D
125, 124
123
J15, J14
K16
PFEC0[2:1]
PFEC00
133
G14
PFECI2C3
PFECI2C2
—
—
132
G15
RMII0_MDIO
MII0_MDIO
Real Time Clock
I
EVDD
EVDD
—
—
P1
R1
RTC_EXTAL
RTC_XTAL
—
—
—
—
—
—
—
—
O
Synchronous Serial Interface
I
EVDD
EVDD
EVDD
EVDD
EVDD
—
—
—
—
—
N3
P3
R2
P4
P5
SSI_RXD
SSI_TXD
SSI_FS
PSSI4
PSSI3
PSSI2
PSSI1
PSSI0
—
—
—
—
—
U1RXD
U1TXD
UD
O
UD
—
I/O
O
U1RTS
SSI_MCLK
SSI_BCLK
SSI_CLKIN
U1CTS
—
I/O
—
I2C
I/O
I/O
EVDD
EVDD
37
38
M1
K3
I2C_SCL
I2C_SDA
PFECI2C1
PFECI2C0
U2RXD
U2TXD
RMII1_MDC
RMII1_MDIO
U
U
DSPI
I/O
I/O
EVDD
EVDD
—
—
P2
N2
DSPI_PCS3
DSPI_PCS2
PDSPI6
PDSPI5
USBH_VBUS_EN
USBH_VBUS_OC
—
—
—
—
MCF5301x Data Sheet, Rev. 5
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
13
Pin Assignments and Reset States
Table 6. MCF5301x Signal Information and Muxing (continued)
MCF53010
MCF53014
MCF53015
MCF53016
MCF53017
MCF53011
MCF53012
MCF53013
Signal Name
GPIO
Alternate 1
Alternate 2
208 LQFP
256 MAPBGA
I/O
I/O
I/O
I
EVDD
EVDD
EVDD
EVDD
EVDD
140
F14
DSPI_PCS1
DSPI_PCS0/SS
DSPI_SCK
PDSPI4
PDSPI3
PDSPI2
PDSPI1
PDSPI0
—
—
—
—
—
—
—
U
137
134
136
135
G13
H13
E16
F15
U2RTS
U2CTS
U2RXD
U2TXD
—
—
—
DSPI_SIN
O
DSPI_SOUT
UARTs
I
O
I
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
14
18
20
21
27
28
E2
F2
U2RXD
U2TXD
U0CTS
U0RTS
U0RXD
U0TXD
PUART5
PUART4
PUART3
PUART2
PUART1
PUART0
—
—
—
—
—
—
—
—
—
—
G4
G3
G2
G1
USBO_VBUS_EN
USB_PULLUP
O
I
USBO_VBUS_OC
—
—
—
—
—
O
DMA Timers
I
I
I
I
EVDD
EVDD
EVDD
EVDD
13
12
F3
E3
T3IN
T2IN
T1IN
T0IN
PTIMER3
PTIMER2
PTIMER1
PTIMER0
T3OUT
T2OUT
T1OUT
T0OUT
IRQ03
IRQ02
—
—
—
—
122
121
K13
L16
DACK1
CODEC_ALTCLK
BDM/JTAG6
O
I
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
43
64
—
M8
ALLPST
JTAG_EN
PSTCLK
DSI
PDEBUG
—
—
—
—
—
—
—
—
—
—
D
—
—
—
—
—
—
I
65
T5
TCLK
TDI
—
U
I
66
T4
O
I
120
119
118
M15
M14
L15
DSO
TDO
TMS
TRST
—
U
BKPT
I
DSCLK
U
MCF5301x Data Sheet, Rev. 5
Preliminary—Subject to Change Without Notice
14
Freescale Semiconductor
Pin Assignments and Reset States
Table 6. MCF5301x Signal Information and Muxing (continued)
MCF53010
MCF53014
MCF53015
MCF53016
MCF53017
MCF53011
MCF53012
MCF53013
Signal Name
GPIO
Alternate 1
Alternate 2
208 LQFP
256 MAPBGA
Test
I
EVDD
146
F12
TEST
—
—
—
Power Supplies
—
D
16, 44, 69, 77, 128, E9, F8, F9, H5, H6, H11,
IVDD
—
—
—
—
—
—
—
—
—
—
169, 193
H12, J6, J11, L8, L9
9, 24, 26, 40, 47,
51, 54, 57, 74, 126,
139, 195
F5, G6, G11, G12,
J12, K6, K11, K12,
L5-7, L10-12, M5-7, M12
EVDD
—
—
7, 102, 116, 156, E5, E6, E10-12, F6, F7,
163, 181, 208
SD_VDD
—
—
—
—
—
F10, F11
46
M4
VDD_OSC_A_PLL
VDD_USBO
VDD_USBH
VDD_RTC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
147
—
E7
E8
—
80
—
N8
T8
M9
L2
L4
AVDD_CODEC
AVDD_SPKR
VDD_EPM
96
—
VSTBY_SRAM
VSTBY_RTC
VSS
—
8, 15, 25, 39, 45, A1, A16, G7-10, H7-10,
48, 52, 53, 56, 68,
73, 76, 101, 117,
138, 168, 180, 192,
194
J7-10, K7-10, T1, T16
83
—
—
N10
T6
VSS_CODEC
AVSS_SPKR_HDST
AVSS_SPKR_HP
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T10
1
Pull-ups are generally only enabled on pins with their primary function, except as noted.
Refers to pin’s primary function.
2
3
4
Enabled only in oscillator bypass mode (internal crystal oscillator is disabled).
The edge port 1 signals are the primary functions on two sets of pins (IRQ1FECn and IRQ1DEBUGn). If an IRQ1 function is configured on
both pins, the IRQ1FECn pin takes priority. The corresponding IRQ1DEBUGn pin is disconnected internally from the edge port 1 module.
5
6
GPIO functionality is determined by the edge port module. The GPIO module is only responsible for assigning the alternate functions.
If JTAG_EN is asserted, these pins default to alternate 1 (JTAG) functionality. The GPIO module is not responsible for assigning these pins.
MCF5301x Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
15
Pin Assignments and Reset States
4.2
Pinout—208 LQFP
The pinout for the 208 LQFP devices is shown in Figure 5 and Figure 6.
•
1
2
3
4
5
6
7
8
FB_OE
FB_R/W
FB_TA
FB_TS
FB_CS1
FB_CS0
SDVDD
VSS
9
EVDD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
IRQ07
IRQ01
T2IN
T3IN
U2RXD
VSS
IVDD
BOOTMOD0
U2TXD
IRQ04
U0CTS
U0RTS
RMII1_MDC
RMII1_MDIO
EVDD
VSS
EVDD
U0RXD
U0TXD
IRQ17
IRQ16
IRQ15
IRQ14
IRQ13
IRQ12
IRQ11
IRQ10
I2C_SCL
I2C_SDA
VSS
EVDD
RESET
RSTOUT
ALLPST
IVDD
VSS
VDD_OSC
EVDD
VSS
EXTAL
XTAL
EVDD
VSS 52
Figure 5. MCF53010, MCF53011, MCF53012, and MCF53013 Pinout Top View, Left (208 QFP)
MCF5301x Data Sheet, Rev. 5
16
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Pin Assignments and Reset States
156 SDVDD
155 SD_CS0
154 SD_CAS
153 FB_CLK
152 SD_RAS
151 SD_CKE
150 SD_WE
149 USBO_DP
148 USBO_DM
147 VDD_USBO
146 TEST
145 SIM1_PD
144 SIM1_RST
143 SIM1_CLK
142 SIM1_VEN
141 SIM1_DATA
140 DSPI_PCS1
139 EVDD
138 VSS
137 DSPI_PCS0
136 DSPI_SIN
135 DSPI_SOUT
134 DSPI_SCK
133 RMII0_MDC
132 RMII0_MDIO
131 RMII0_CRSDV
130 RMII0_RXD1
129 RMII0_RXD0
128 IVDD
127 RMII0_RXER
126 EVDD
125 RMII0_TXD1
124 RMII0_TXD0
123 RMII0_TXEN
122 T1IN
121 T0IN
120 TDO
119 TMS
118 TRST
117 VSS
116 SDVDD
115 FB_A23
114 FB_A22
113
FB_A21
112 FB_A20
111 FB_A19
110 FB_A18
109 FB_A17
108 FB_A16
107 FB_A15
106 FB_A14
105 FB_A13
Figure 6. MCF53010, MCF53011, MCF53012, and MCF53013 Pinout Top View, Right (208 QFP)
MCF5301x Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
17
Pin Assignments and Reset States
4.3
Pinout–256 MAPBGA
The pinout for the MCF53014, MCF53015, MCF53016, and MCF53017 packages are shown below.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FB_D
30
FB_D
26
FB_BE/
BWE3
SD_
DQS1
SD_
CLK
SD_
CLK
FB_D
13
FB_D
14
FB_D
6
FB_D
2
FB_D
0
FB_D
16
FB_D
17
A
B
C
D
E
F
VSS
SD_CS
VSS
A
B
C
D
E
F
USBH_
DM
FB_D
31
FB_D
27
FB_D
25
FB_D
8
FB_D
11
FB_D
15
FB_D
5
FB_D FB_BE/
1
FB_D
18
FB_D
21
SD_
CKE
USBO_
DP
FB_TA
FB_CS5
BWE2
USBH_
DP
FB_D
28
FB_D
24
FB_D FB_BE/ FB_D
10 BWE1
FB_D
3
SD_
DQS2
FB_D
20
FB_D
22
SD_
RAS
USBO_
DM
FB_CS0 FB_R/W SD_A10
FB_CS4
7
SD_SDR FB_D
_DQS 29
FB_D
12
FB_D FB_BE/ FB_D
9
FB_D
19
FB_D
23
SD_
WE
SD_
CAS
SIM1_
VEN
IRQ04 FB_CS1 FB_TS
FB_OE
IRQ07
IRQ01
FB_CLK
BWE0
4
RMII1_
MDC
VDD_
USBO
VDD_
USBH
SIM1_
RST
SIM1_
DATA
SIM1_
PD
DSPI_
SIN
U2RXD
U2TXD
T2IN
T3IN
SDVDD SDVDD
IVDD
SDVDD SDVDD SDVDD
SDVDD SDVDD TEST
RMII1_
MDIO
SIM1_
CLK
DSPI_
PCS1
DSPI_
SOUT
SIM0_
RST
EVDD SDVDD SDVDD
IVDD
VSS
VSS
VSS
VSS
IVDD
IVDD
VSS
VSS
VSS
VSS
IVDD
BOOT
DSPI_
PCS0
RMII0_
MDC
RMII0_ RMII0_
MDIO
G
H
J
U0TXD U0RXD U0RTS U0CTS
EVDD
IVDD
VSS
VSS
VSS
VSS
VSS
VSS
EVDD
NC
EVDD
IVDD
IVDD
EVDD
EVDD
NC
EVDD
IVDD
G
H
J
MOD0
IVDD
CRSDV
IRQ1
IRQ1
IRQ1
IRQ1
DSPI_
SCK
IRQ1
DEBUG2 RXD1
RMII0_ RMII0_
RXD0
DEBUG7 DEBUG4 DEBUG5 DEBUG6
IRQ1
FEC7
IRQ1
FEC6
IRQ1
FEC4
IRQ1
FEC3
BOOT
MOD1
IRQ1
DEBUG0 TXD0
RMII0_
RMII0_ RMII0_
TXD1
IVDD
VSS
EVDD
EVDD
EVDD
EVDD
RXER
IRQ1
FEC2
IRQ1
FEC1
I2C_
SDA
IRQ1
FEC5
IRQ1
T1IN
IRQ1
RMII0_
K
L
NC
EVDD
EVDD
EVDD
VSS
K
L
DEBUG3 DEBUG1 TXEN
IRQ1
FEC0
VSTBY_ SIM0_ VSTBY_
SRAM
SIM0_
PD
EVDD
EVDD
EVDD
IRQ06
NC
TRST
TDO
T0IN
DATA
RTC
VDD_
I2C_
SCL
SIM0_
VEN
JTAG_
EN
VDD_
EPM
SIM0_
CLK
M
RESET OSC_A_ EVDD
PLL
TMS
M
N
P
R
T
CODEC
_BGR
VREF
RST
OUT
DSPI_
PCS2
SSI_
RXD
SDHC_ SDHC_ SDHC_ CODEC AVDD_
DAT3
VSS_
CODEC
N
P
FB_A4 FB_A10 FB_A13 FB_A20 FB_A19 FB_A22
FB_A5 FB_A9 FB_A16 FB_A17 FB_A18 FB_A23
DAT0
DAT1
_VAG CODEC
CODEC
_REG
BYP
RTC_
EXTAL
DSPI_
PCS3
SSI_
TXD
SSI_
MCLK
SSI_
BCLK
CODEC CODEC CODEC CODEC
_REFP _REFN _ADCP _ADCN
AMP_
HP
OUT
AMP_
HP
DUMMY
R
T
RTC_
XTAL
SDHC_ SDHC_ SDHC_ CODEC CODEC
CLK
SSI_FS
FB_A2 FB_A6 FB_A12 FB_A11 FB_A14 FB_A15 FB_A21
AVSS_
SPKR_ FB_A1 FB_A0
HP
CMD
DAT2
_DACP _DACN
AVSS_
SPKR_
HDST
AMP_ AVDD_ AMP_
SPKRP SPKR SPKRN
VSS
EXTAL
XTAL
TDI
TCLK
FB_A3
FB_A8
FB_A7
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Figure 7. MCF53014, MCF53015, MCF53016, and MCF53017 Pinout (256 MAPBGA)
MCF5301x Data Sheet, Rev. 5
18
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Preliminary Electrical Characteristics
5
Preliminary Electrical Characteristics
This document contains electrical specification tables and reference timing diagrams for the MCF5301x microprocessor. This
section contains detailed information on DC/AC electrical characteristics and AC timing specifications.
The electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not
be fully tested or guaranteed at this early stage of the product life cycle, however for production silicon these specifications will
be met. Finalized specifications will be published after complete characterization and device qualifications have been
completed.
NOTE
The parameters specified in this MCU document supersede any values found in the module
specifications.
5.1
Maximum Ratings
1, 2
Table 7. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Core Supply Voltage
IVDD
EVDD
SDVDD
PLLVDD
VIN
–0.5 to +2.0
–0.3 to +4.0
–0.3 to +4.0
–0.3 to +2.0
–0.3 to +3.6
25
V
V
CMOS Pad Supply Voltage
DDR/Memory Pad Supply Voltage
PLL Supply Voltage
V
V
Digital Input Voltage 3
V
Instantaneous Maximum Current
ID
mA
Single pin limit (applies to all pins) 3, 4, 5
Operating Temperature Range (Packaged)
TA
(TL – TH)
–40 to +85
°C
°C
Storage Temperature Range
Tstg
–55 to +150
1
2
Functional operating conditions are given in Section 5.4, “DC Electrical Specifications.”
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is
not guaranteed. Continued operation at these levels may affect device reliability or cause
permanent damage to the device.
This device contains circuitry protecting against damage due to high static voltage or
electrical fields; however, it is advised that normal precautions be taken to avoid application of
any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g.,
either VSS or EVDD).
3
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive and negative clamp voltages,
then use the larger of the two values.
4
5
All functional non-supply pins are internally clamped to VSS and EVDD
.
Power supply must maintain regulation within operating EVDD range during instantaneous
and operating maximum current conditions. If positive injection current (Vin > EVDD) is greater
than IDD, the injection current may flow out of EVDD and could result in external power supply
going out of regulation. Insure external EVDD load will shunt current greater than maximum
injection current. This will be the greatest risk when the MCU is not consuming power (ex; no
clock). Power supply must maintain regulation within operating EVDD range during
instantaneous and operating maximum current conditions.
MCF5301x Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
19
Preliminary Electrical Characteristics
5.2
Thermal Characteristics
Table 8. Thermal Characteristics
256
MAPBGA
208
LQFP
Characteristic
Symbol
Unit
Junction to ambient, natural convection
Junction to ambient (@200 ft/min)
Four layer board
(2s2p)
θJMA
361,2
381,2
°C/W
Four layer board
(2s2p)
θJMA
321,2
331,2
°C/W
Junction to board
θJB
θJC
Ψjt
Tj
253
144
21,5
105
293
114
31,5
105
°C/W
°C/W
°C/W
oC
Junction to case
Junction to top of package
Maximum operating junction temperature
1
θ
JMA and Ψjt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection.
Freescale recommends the use of θJmA and power dissipation specifications in the system design to prevent
device junction temperatures from exceeding the rated specification. System designers should be aware
that device junction temperatures can be significantly influenced by board layout and surrounding devices.
Conformance to the device junction temperature specification can be verified by physical measurement in
the customer’s system using the Ψjt parameter, the device power dissipation, and the method described in
EIA/JESD Standard 51-2.
2
3
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8.
Board temperature is measured on the top surface of the board near the package.
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL
SPEC-883 Method 1012.1).
Thermal characterization parameter indicating the temperature difference between package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal
characterization parameter is written in conformance with Psi-JT.
4
5
The average chip-junction temperature (T ) in °C can be obtained from:
J
TJ = TA + (PD × ΘJMA
)
Eqn. 1
Where:
TA
= Ambient Temperature, °C
QJMA
PD
= Package Thermal Resistance, Junction-to-Ambient, °C/W
= PINT + PI/O
PINT
PI/O
= IDD × IVDD, Watts - Chip Internal Power
= Power Dissipation on Input and Output Pins — User Determined
For most applications P < P
and can be ignored. An approximate relationship between P and T (if P is neglected) is:
D J I/O
I/O
INT
K
--------------------------------
PD
=
Eqn. 2
(TJ + 273°C)
Solving equations 1 and 2 for K gives:
K = PD × (TA × 273°C) + QJMA × P2D
Eqn. 3
MCF5301x Data Sheet, Rev. 5
20
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Preliminary Electrical Characteristics
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring P (at equilibrium)
D
for a known T . Using this value of K, the values of P and T can be obtained by solving Equation 1 and Equation 2 iteratively
A
D
J
for any value of T .
A
5.3
ESD Protection
1, 2
Table 9. ESD Protection Characteristics
Characteristics
Symbol
Value
Units
ESD Target for Human Body Model
HBM
2000
V
1
All ESD testing is in conformity with JEDEC JESD22-A114 specification.
2
A device is defined as a failure if after exposure to ESD pulses the device no longer meets
the device specification requirements. Complete DC parametric and functional testing is
performed per applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
5.4
DC Electrical Specifications
Table 10. DC Electrical Specifications
Characteristic
Symbol
Min
Max
Unit
Core Supply Voltage
IVDD
SRAMVSTBY
RTCVSTBY
PLLVDD
1.08
1.08
3.0
1.32
1.32
3.6
V
V
V
V
V
V
SRAM Standby Voltage
RTC Standby Voltage
PLL Supply Voltage
3.0
3.6
CMOS Pad Supply Voltage
EVDD
3.0
3.6
SDRAM and FlexBus Supply Voltage
SDVDD
Mobile DDR/Bus Pad Supply Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)
1.70
2.25
3.0
1.95
2.75
3.6
USB Supply Voltage
USBVDD
EVIH
3.0
3.6
EVDD + 0.3
0.42 × EVDD
—
V
V
V
V
CMOS Input High Voltage
CMOS Input Low Voltage
0.51 × EVDD
VSS – 0.3
0.8 × EVDD
EVIL
CMOS Output High Voltage
IOH = –2.0 mA
EVOH
CMOS Output Low Voltage
EVOL
—
0.2 × EVDD
V
V
IOL = 2.0 mA
SDRAM and FlexBus Input High Voltage
SDVIH
Mobile DDR/Bus Input High Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)
SDVDD × 0.7 SDVDD+0.3
Vref+0.15
SDVDD+0.3
2
SDVDD + 0.3
SDRAM and FlexBus Input Low Voltage
SDVIL
V
Mobile DDR/Bus Input High Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)
–0.3
–0.3
VSS – 0.3
SDVDD × 0.3
Vref+0.15
0.8
MCF5301x Data Sheet, Rev. 5
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
21
Preliminary Electrical Characteristics
Table 10. DC Electrical Specifications (continued)
Characteristic
Symbol
Min
Max
Unit
SDRAM and FlexBus Output High Voltage
Mobile DDR/Bus Input High Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)
IOH = –5.0 mA for all modes
SDVOH
V
SDVDD × 0.9
SDVDD – 0.35
2.9
—
—
—
SDRAM and FlexBus Output Low Voltage
Mobile DDR/Bus Input High Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)
SDVOL
V
—
—
—
SDVDD × 0.1
0.35
0.4
IOL = 5.0 mA for all modes
Input Leakage Current
Iin
–2.5
2.5
μA
Vin = VDD or VSS, Input-only pins
Weak Internal Pull-Up/Pull-down Device Current1
IAPU
IAPU
Cin
10
25
315
150
μA
μA
pF
Selectable Weak Internal Pull-Up/Pull-down Device Current2
Input Capacitance 3
All input-only pins
All input/output (three-state) pins
—
—
7
7
1
Refer to the signals section for pins having weak internal pull-up devices.
Refer to the signals section for pins having weak internal pull-up devices.
This parameter is characterized before qualification rather than 100% tested.
2
3
5.4.1
PLL Power Filtering
To further enhance noise isolation, an external filter is strongly recommended for PLL analog V pins. The filter shown in
DD
Figure 8 should be connected between the board V and the PLLV pins. The resistor and capacitors should be placed as
DD
DD
close to the dedicated PLLV pin as possible.
DD
10 Ω
Board IVDD
PLL VDD Pin
10 µF
0.1 µF
GND
Figure 8. System PLL V Power Filter
DD
5.4.2
USB Power Filtering
To minimize noise, external filters are required for each of the USB power pins. The filter shown in Figure 2 should be
connected between the board EV or IV and each of the USBV pins. The resistor and capacitors should be placed as
DD
DD
DD
close to the dedicated USBV pin as possible.
DD
MCF5301x Data Sheet, Rev. 5
22
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Preliminary Electrical Characteristics
0 Ω
Board EVDD
USB VDD Pin
10 µF
0.1 µF
GND
Figure 9. USB V Power Filter
DD
NOTE
In addition to the above filter circuitry, a 0.01 F capacitor is also recommended in parallel
with those shown.
5.4.3
Supply Voltage Sequencing and Separation Cautions
The relationship between SDV and EV is non-critical during power-up and power-down sequences. Both SDV (2.5V
DD
DD
DD
or 3.3V) and EV are specified relative to IV
.
DD
DD
5.4.3.1
Power Up Sequence
If EV /SDV are powered up with IV at 0 V, then the sense circuits in the I/O pads will cause all pad output drivers
DD
DD
DD
connected to the EV /SDV to be in a high impedance state. There is no limit on how long after EV /SDV powers up
DD
DD
DD
DD
before IV must powered up. IV should not lead the EV , SDV or PLLV by more than 0.4 V during power ramp-up,
DD
DD
DD
DD
DD
or there will be high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than
500 us to avoid turning on the internal ESD protection clamp diodes.
5.4.3.2
Power Down Sequence
If IV /PLLV are powered down first, then sense circuits in the I/O pads will cause all output drivers to be in a high
DD
DD
impedance state. There is no limit on how long after IV and PLLV power down before EV or SDV must power
DD
DD
DD
DD
down. IV should not lag EV , SDV , or PLLV going low by more than 0.4 V during power down or there will be
DD
DD
DD
DD
undesired high current in the ESD protection diodes. There are no requirements for the fall times of the power supplies.
The recommended power down sequence is as follows:
1. Drop IV /PLLV to 0 V.
DD
DD
2. Drop EV /SDV supplies.
DD
DD
MCF5301x Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
23
Preliminary Electrical Characteristics
5.5
Oscillator and PLL Electrical Characteristics
Table 11. PLL Electrical Characteristics
Min.
Value
Max.
Value
Num
Characteristic
Symbol
Unit
1
PLL Reference Frequency Range
Crystal reference
fref_crystal
fref_ext
14
14
251
481
MHz
MHz
External reference
2
Core frequency
fsys
fsys/3
488 x 10-6
163 x 10-6
240
80
MHz
MHz
CLKOUT Frequency2
3
4
Crystal Start-up Time3, 4
tcst
—
10
ms
EXTAL Input High Voltage
Crystal Mode5
All other modes (External, Limp)
VIHEXT
VIHEXT
VXTAL + 0.4
EVDD/2 + 0.4
—
—
V
V
5
EXTAL Input Low Voltage
Crystal Mode5
VILEXT
VILEXT
—
—
VXTAL – 0.4
EVDD/2 – 0.4
V
V
All other modes (External, Limp)
7
8
PLL Lock Time 3, 6
tlpll
tdc
—
40
1
750
60
us
%
Duty Cycle of reference 3
9
XTAL Current
IXTAL
3
mA
pF
pF
10
11
12
Total on-chip stray capacitance on XTAL
Total on-chip stray capacitance on EXTAL
Crystal capacitive load
CS_XTAL
CS_EXTAL
CL
—
—
—
1.5
1.5
See crystal
spec
13
14
17
Discrete load capacitance for XTAL
Discrete load capacitance for EXTAL
CL_XTAL
CL_EXTAL
Cjitter
—
—
2 × CL –
pF
pF
CS_XTAL
–
7
CPCB_XTAL
2 × CL –
CS_EXTAL
CPCB_EXTAL
–
7
CLKOUT Period Jitter, 3, 4, 7, 8, 9 Measured at fSYS Max
Peak-to-peak Jitter (Clock edge to clock edge)
Long Term Jitter
—
—
TBD
TBD
% fsys/3
% fsys/3
18
19
Frequency Modulation Range Limit 3, 10, 11
(fsysMax must not be exceeded)
Cmod
fvco
0.8
2.2
%fsys/3
VCO Frequency. fvco = (fref × PFD)/4
200
667
MHz
1
The maximum allowable input clock frequency when booting with the PLL enabled is 24MHz. For higher input clock
frequencies the processor must boot in LIMP mode to avoid violating the maximum allowable CPU frequency.
All internal registers retain data at 0 Hz.
This parameter is guaranteed by characterization before qualification rather than 100% tested.
Proper PC board layout procedures must be followed to achieve specifications.
This parameter is guaranteed by design rather than 100% tested.
This specification is the PLL lock time only and does not include oscillator start-up time..
CPCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively.
2
3
4
5
6
7
MCF5301x Data Sheet, Rev. 5
24
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Preliminary Electrical Characteristics
8
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal.
.
Noise injected into the PLL circuitry via PLL VDD, EVDD, and VSS and variation in crystal oscillator frequency increase
the Cjitter percentage for a given interval.
Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of Cjitter+Cmod.
Modulation percentage applies over an interval of 10μs, or equivalently the modulation rate is 100kHz.
Modulation range determined by hardware design.
9
10
11
5.6
External Interface Timing Characteristics
Table 12 lists processor bus input timings.
NOTE
All processor bus timings are synchronous; that is, input setup/hold and output delay with
respect to the rising edge of a reference clock. The reference clock is the FB_CLK output.
All other timing relationships can be derived from these values. Timings listed in Table 12
are shown in Figure 11 and Figure 12.
* The timings are also valid for inputs sampled on the negative clock edge.
1.5V
FB_CLK (80MHz)
TSETUP
THOLD
Invalid
1.5V Valid 1.5V
Invalid
Input Setup And Hold
Input Rise Time
Input Fall Time
t
t
rise
V
= V
IH
h
V = V
l
IL
fall
V
= V
IH
h
V = V
l
IL
FB_CLK
B4
B5
Inputs
Figure 10. General Input Timing Requirements
5.6.1
FlexBus
A multi-function external bus interface called FlexBus is provided with basic functionality to interface to slave-only devices up
to a maximum bus frequency of 80MHz. It can be directly connected to asynchronous or synchronous devices such as external
boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional circuitry. For
asynchronous devices a simple chip-select based interface can be used. The FlexBus interface has six general purpose
chip-selects (FB_CS[5:0]) which can be configured to be distributed between the FlexBus or SDRAM memory interfaces.
MCF5301x Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
25
Preliminary Electrical Characteristics
Chip-select, FB_CS0 can be dedicated to boot ROM access and can be programmed to be byte (8 bits), word (16 bits), or
longword (32 bits) wide. Control signal timing is 1‘compatible with common ROM/flash memories.
5.6.1.1
FlexBus AC Timing Characteristics
The following timing numbers indicate when data will be latched or driven onto the external bus, relative to the system clock.
Table 12. FlexBus AC Timing Specifications
Num
Characteristic
Symbol
Min
Max
Unit Notes
Frequency of Operation
FB1 Clock Period (FB_CLK)
—
12.5
—
80
—
Mhz
ns
fsys/3
tFBCK
tcyc
1
FB2 Address, Data, and Control Output Valid (A[23:0], D[31:0],
FB_CS[5:0], R/W, TS, BE/BWE[3:0] and OE)
tFBCHDCV
7.0
ns
1, 2
FB3 Address, Data, and Control Output Hold (A[23:0], D[31:0],
FB_CS[5:0], R/W, TS, BE/BWE[3:0], and OE)
tFBCHDCI
1
—
ns
FB4 Data Input Setup
tDVFBCH
tDIFBCH
tCVFBCH
tCIFBCH
3.5
0
—
—
—
—
ns
ns
ns
ns
FB5 Data Input Hold
FB6 Transfer Acknowledge (TA) Input Setup
FB7 Transfer Acknowledge (TA) Input Hold
4
0
1
2
Timing for chip selects only applies to the FB_CS[5:0] signals. Please see Section 5.7.2, “DDR SDRAM AC Timing
Characteristics” for SD_CS[3:0] timing.
The FlexBus supports programming an extension of the address hold. Please consult the MCF5301x Reference
Manual for more information.
NOTE
The processor drives the data lines during the first clock cycle of the transfer with the full
32-bit address. This may be ignored by standard connected devices using non-multiplexed
address and data buses. However, some applications may find this feature beneficial.
The address and data busses are muxed between the FlexBus and SDRAM controller. At
the end of the read and write bus cycles the address signals are indeterminate.
MCF5301x Data Sheet, Rev. 5
26
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Preliminary Electrical Characteristics
S0
S1
S2
S3
FB_CLK
FB1
FB3
ADDR[23:0]
FB_A[23:0]
FB2
FB5
FB_D[31:X]
ADDR[31:X]
DATA
FB4
FB_R/W
FB_TS
FB_CSn, FB_OE,
FB_BE/BWEn
FB6
FB7
FB_TA
Figure 11. FlexBus Read Timing
S0
S1
S2
S3
FB_CLK
FB1
FB3
ADDR[23:0]
FB_A[23:0]
FB2
ADDR[31:X]
FB_D[31:X]
DATA
FB_R/W
FB_TS
FB_CSn, FB_BE/BWEn
FB_OE
FB6
FB7
FB_TA
Figure 12. Flexbus Write Timing
5.7
SDRAM Bus
The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports either standard
SDRAM or double data rate (DDR) SDRAM, but it does not support both at the same time.
5.7.1
SDR SDRAM AC Timing Characteristics
The following timing numbers indicate when data will be latched or driven onto the external bus, relative to the memory bus
clock, when operating in SDR mode on write cycles and relative to SD_DQS on read cycles. The device’s SDRAM controller
is a DDR controller that has an SDR mode. Because it is designed to support DDR, a DQS pulse must still be supplied to the
device for each data beat of an SDR read. The processor accomplishes this by asserting a signal named SD_SDR_DQS during
MCF5301x Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
27
Preliminary Electrical Characteristics
read cycles. Care must be taken during board design to adhere to the following guidelines and specs with regard to the
SD_SDR_DQS signal and its usage.
Table 13. SDR Timing Specifications
Symbol
Characteristic
Frequency of operation
Symbol
Min
Max
Unit
Notes
1
50
12.5
0.45
0.45
—
80
20
Mhz
ns
2
3
4
SD1 Clock period
tSDCK
tSDCKH
SD2 Pulse width high
SD3 Pulse width low
0.55
0.55
SD_CLK
SD_CLK
ns
tSDCKH
SD4 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,
SD_CS[1:0] output valid
tSDCHACV
0.5 × SD_CLK
+ 1.0
SD5 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,
SD_CS[1:0] output hold
tSDCHACI
2.0
—
—
ns
5
6
SD6 SD_SDR_DQS output valid
tDQSOV
Self timed
ns
ns
SD7 SD_DQS[3:0] input setup relative to SD_CLK
tDQVSDCH
0.25 ×
0.40 × SD_CLK
SD_CLK
7
8
SD8 SD_DQS[3:2] input hold relative to SD_CLK
tDQISDCH
tDVSDCH
tDISDCH
Does not apply. 0.5×SD_CLK fixed
width.
SD9 Data (D[31:0]) input setup relative to SD_CLK (reference
only)
0.25 ×
SD_CLK
—
—
ns
SD10 Data input hold relative to SD_CLK (reference only)
1.0
—
ns
ns
SD11 Data (D[31:0]) and data mask (SD_DQM[3:0]) output valid tSDCHDMV
0.75 × SD_CLK
+ 0.5
SD12 Data (D[31:0]) and data mask (SD_DQM[3:0]) output hold tSDCHDMI
1.5
—
ns
1
The device supports same frequency of operation for both FlexBus and SDRAM clock operates as that of the internal bus clock.
Please see the PLL chapter of the MCF5301x Reference Manual for more information on setting the SDRAM clock rate.
SD_CLK is one SDRAM clock in (ns).
Pulse width high plus pulse width low cannot exceed min and max clock period.
Pulse width high plus pulse width low cannot exceed min and max clock period.
SD_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle variation
from this guideline is expected. SD_DQS will only pulse during a read cycle and one pulse will occur for each data beat.
SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle
variation from this guideline is expected. SDR_DQS will only pulse during a read cycle and one pulse will occur for each data
beat.
The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge does
not affect the memory controller.
Since a read cycle in SDR mode still uses the DQS circuit within the device, it is most critical that the data valid window be
centered 1/4 clk after the rising edge of DQS. Ensuring that this happens will result in successful SDR reads. The input setup
spec is just provided as guidance.
2
3
4
5
6
7
8
MCF5301x Data Sheet, Rev. 5
28
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Preliminary Electrical Characteristics
SD2
SD1
SD_CLK
SD3
SD5
SD_CSn
SD_RAS
SD_CAS
SD_WE
CMD
ROW
SD4
A[23:0]
SD_BA[1:0]
COL
SD11
SDDM
D[31:0]
SD12
WD1
WD2
WD3
WD4
Figure 13. SDR Write Timing
SD2
SD1
SD_CLK
SD5
SD_CSn,
SD_RAS,
SD_CAS,
SD_WE
SD3
CMD
3/4 MCLK
Reference
SD4
A[23:0],
SD_BA[1:0]
ROW
COL
tDQS
SDDM
SD6
SD_SDR_DQS (Measured at Output Pin)
SD_DQS[3:2] (Measured at Input Pin)
Board Delay
SD8
Board Delay
SD7
Delayed
SD_CLK
SD9
D[31:0]
from
WD1
WD2
WD3
WD4
Memories
NOTE: Data driven from memories relative
to delayed memory clock.
SD10
Figure 14. SDR Read Timing
MCF5301x Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
29
Preliminary Electrical Characteristics
5.7.2
DDR SDRAM AC Timing Characteristics
When the SDRAM controller is configured for DDR SDRAM, the following timing numbers must be followed to properly latch
or drive data onto the memory bus. All timing numbers are relative to the four DQS byte lanes. The following timing numbers
are subject to change at anytime, and are only provided to aid in early board design.
Table 14. DDR Timing Specifications
Num
Characteristic
Frequency of Operation
Symbol
Min
Max
Unit
Notes
1
tDDCK
tDDSK
50
12.5
0.45
0.45
—
80
20
Mhz
ns
2
3
3
4
DD1 Clock Period
DD2 Pulse Width High
DD3 Pulse Width Low
tDDCKH
tDDCKL
tSDCHACV
0.55
0.55
SD_CLK
SD_CLK
ns
DD4 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] Output Valid
0.5 × SD_CLK
+ 1.0
DD5 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] Output Hold
tSDCHACI
2.0
—
ns
DD6 Write Command to first DQS Latching Transition
tCMDVDQ
tDQDMV
—
1.25
—
SD_CLK
ns
5
6
DD7 Data and Data Mask Output Setup (DQ-->DQS)
Relative to DQS (DDR Write Mode)
1.5
7
DD8 Data and Data Mask Output Hold (DQS-->DQ)
Relative to DQS (DDR Write Mode)
tDQDMI
1.0
—
ns
8
9
DD9 Input Data Skew Relative to DQS (Input Setup)
DD10 Input Data Hold Relative to DQS.
tDVDQ
tDIDQ
—
1
ns
ns
0.25 × SD_CLK
—
+ 0.5ns
DD11 DQS falling edge from SDCLK rising (output hold time) tDQLSDCH
0.5
0.9
—
1.1
0.6
—
ns
DD12 DQS input read preamble width
DD13 DQS input read postamble width
DD14 DQS output write preamble width
DD15 DQS output write postamble width
tDQRPRE
tDQRPST
tDQWPRE
tDQWPST
SD_CLK
SD_CLK
SD_CLK
SD_CLK
0.4
0.25
0.4
0.6
1
The frequency of operation is either 2x or 4x the FB_CLK frequency of operation. FlexBus and SDRAM clock operate at the
same frequency as the internal bus clock.
2
3
4
SD_CLK is one SDRAM clock in (ns).
Pulse width high plus pulse width low cannot exceed min and max clock period.
Command output valid should be 1/2 the memory bus clock (SD_CLK) plus some minor adjustments for process, temperature,
and voltage variations.
5
This specification relates to the required input setup time of today’s DDR memories. The device’s output setup should be larger
than the input setup of the DDR memories. If it is not larger, then the input setup on the memory will be in violation.
SD_D[31:24] is relative to SD_DQS3, SD_D[23:16] is relative to SD_DQS2, SD_D[15:8] is relative to SD_DQS1, and
SD_D[7:0] is relative SD_DQS0.
6
7
The first data beat will be valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats
will be valid for each subsequent DQS edge.
This specification relates to the required hold time of today’s DDR memories. SD_D[31:24] is relative to SD_DQS3,
SD_D[23:16] is relative to SD_DQS2, SD_D[15:8] is relative to SD_DQS1, and SD_D[7:0] is relative SD_DQS0.
MCF5301x Data Sheet, Rev. 5
30
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Preliminary Electrical Characteristics
8
9
Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line
becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other
factors).
Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line becomes
invalid.
SD_CLK
VIX
VID
VMP
VIX
SD_CLK
Figure 15. SD_CLK and SD_CLK Crossover Timing
DD1
DD2
SD_CLK
DD3
SD_CLK
DD5
SD_CSn,SD_WE,
SD_RAS, SD_CAS
CMD
ROW
DD4
DD6
A[13:0]
COL
DD7
DM3/DM2
SD_DQS3/SD_DQS2
D[31:24]/D[23:16]
DD8
DD7
WD1 WD2 WD3 WD4
DD8
Figure 16. DDR Write Timing
MCF5301x Data Sheet, Rev. 5
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
31
Preliminary Electrical Characteristics
DD1
DD2
SD_CLK
DD3
SD_CLK
DD5
CL=2
SD_CSn,SD_WE,
SD_RAS, SD_CAS
CMD
ROW
DD4
CL=2.5
A[13:0]
COL
DD9
DQS Read
Postamble
DQS Read
Preamble
SD_DQS3/SD_DQS2
D[31:24]/D[23:16]
DD10
WD1 WD2 WD3 WD4
DQS Read
Preamble
DQS Read
Postamble
SD_DQS3/SD_DQS2
D[31:24]/D[23:16]
WD1 WD2 WD3 WD4
Figure 17. DDR Read Timing
5.8
General Purpose I/O Timing
1
Table 15. GPIO Timing
Num
Characteristic
Symbol
Min
Max
Unit
G1 FB_CLK High to GPIO Output Valid
G2 FB_CLK High to GPIO Output Invalid
G3 GPIO Input Valid to FB_CLK High
tCHPOV
tCHPOI
tPVCH
tCHPI
—
1.5
9
10
—
—
—
ns
ns
ns
ns
G4 FB_CLK High to GPIO Input Invalid
GPIO pins include: IRQn, PWM, UART, and Timer pins.
1.5
1
MCF5301x Data Sheet, Rev. 5
Preliminary—Subject to Change Without Notice
32
Freescale Semiconductor
Preliminary Electrical Characteristics
FB_CLK
G2
G1
GPIO Outputs
G3
G4
GPIO Inputs
Figure 18. GPIO Timing
5.9
Reset and Configuration Override Timing
Table 16. Reset and Configuration Override Timing
Num
Characteristic
Symbol
Min
Max
Unit
R1 RESET Input valid to FB_CLK High
tRVCH
tCHRI
9
1.5
5
—
—
—
10
—
—
—
1
ns
ns
R2 FB_CLK High to RESET Input invalid
R3 RESET Input valid Time 1
tRIVT
tCYC
ns
R4 FB_CLK High to RSTOUT Valid
tCHROV
tROVCV
tCOS
—
0
R5 RSTOUT valid to Config. Overrides valid
R6 Configuration Override Setup Time to RSTOUT invalid
R7 Configuration Override Hold Time after RSTOUT invalid
R8 RSTOUT invalid to Configuration Override High Impedance
ns
20
0
tCYC
ns
tCOH
tROICZ
—
tCYC
1
During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously to
the system. Thus, RESET must be held a minimum of 100 ns.
FB_CLK
R1
R2
R3
RESET
R4
R4
RSTOUT
R8
R5
R6
R7
Configuration Overrides*:
(RCON, Override pins])
Figure 19. RESET and Configuration Override Timing
NOTE
Refer to the CCM chapter of the MCF5301x Reference Manual for more information.
MCF5301x Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
33
Preliminary Electrical Characteristics
5.10 USB On-The-Go
The MCF53017 device is compliant with industry standard USB 2.0 specification.
5.11 SSI Timing Specifications
This section provides the AC timings for the SSI in master (clocks driven) and slave modes (clocks input). All timings are given
for non-inverted serial clock polarity (SSI_TCR[TSCKP] = 0, SSI_RCR[RSCKP] = 0) and a non-inverted frame sync
(SSI_TCR[TFSI] = 0, SSI_RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings
remain valid by inverting the clock signal (SSI_BCLK) and/or the frame sync (SSI_FS) shown in the figures below.
1
Table 17. SSI Timing - Master Modes
Num
Description
Symbol
Min
Max
Units
Notes
2
S1
S2
S3
S4
S5
S6
S7
S8
S9
SSI_MCLK cycle time
tMCLK 8 × tSYS
—
55%
—
ns
tMCLK
ns
SSI_MCLK pulse width high / low
SSI_BCLK cycle time
45%
3
tBCLK 8 × tSYS
SSI_BCLK pulse width
45%
—
0
55%
15
tBCLK
ns
SSI_BCLK to SSI_FS output valid
SSI_BCLK to SSI_FS output invalid
SSI_BCLK to SSI_TXD valid
—
ns
—
–2
10
0
15
ns
SSI_BCLK to SSI_TXD invalid / high impedence
SSI_RXD / SSI_FS input setup before SSI_BCLK
—
ns
—
ns
S10 SSI_RXD / SSI_FS input hold after SSI_BCLK
—
ns
1
2
3
All timings specified with a capactive load of 25pF.
SSI_MCLK can be generated from SSI_CLKIN or a divided version of the internal system clock (SYSCLK).
SSI_BCLK can be derived from SSI_CLKIN or a divided version of SYSCLK. If the SYSCLK is used, the minimum
divider is 6. If the SSI_CLKIN input is used, the programmable dividers must be set to ensure that SSI_BCLK does
not exceed 4 x fSYS
.
1
Table 18. SSI Timing — Slave Modes
Num
Description Symbol
Min
Max
Units
Notes
S11 SSI_BCLK cycle time
tBCLK 8 × tSYS
—
55%
—
ns
tBCLK
ns
S12 SSI_BCLK pulse width high / low
S13 SSI_FS input setup before SSI_BCLK
S14 SSI_FS input hold after SSI_BCLK
S15 SSI_BCLK to SSI_TXD / SSI_FS output valid
45%
10
2
—
ns
—
0
15
ns
S16 SSI_BCLK to SSI_TXD / SSI_FS output invalid / high
impedence
—
ns
S17 SSI_RXD setup before SSI_BCLK
S18 SSI_RXD hold after SSI_BCLK
10
2
—
—
ns
ns
1
All timings specified with a capactive load of 25pF.
MCF5301x Data Sheet, Rev. 5
Preliminary—Subject to Change Without Notice
34
Freescale Semiconductor
Preliminary Electrical Characteristics
S1
S2
S2
SSI_MCLK
(Output)
S3
SSI_BCLK
(Output)
S4
S4
S5
S6
SSI_FS
(Output)
S9
S10
SSI_FS
(Input)
S7
S8
S7
S8
SSI_TXD
SSI_RXD
S9
S10
Figure 20. SSI Timing — Master Modes
S11
SSI_BCLK
(Input)
S12
S12
S15
S16
SSI_FS
(Output)
S13
S14
SSI_FS
(Input)
S15
S16
S16
S15
SSI_TXD
SSI_RXD
S17
S18
Figure 21. SSI Timing — Slave Modes
2
5.12 I C Input/Output Timing Specifications
2
Table 19 lists specifications for the I C input timing parameters shown in Figure 22.
2
Table 19. I C Input Timing Specifications between SCL and SDA
Num
Characteristic
Start condition hold time
Min
Max
Units
I1
I2
I3
I4
2
8
—
—
1
tcyc
tcyc
ms
ns
Clock low period
I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
Data hold time
—
0
—
MCF5301x Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
35
Preliminary Electrical Characteristics
2
Table 19. I C Input Timing Specifications between SCL and SDA (continued)
Num
Characteristic
Min
Max
Units
I5
I6
I7
I8
I9
I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
Clock high time
—
4
1
ms
tcyc
ns
—
—
—
—
Data setup time
0
Start condition setup time (for repeated start condition only)
Stop condition setup time
2
tcyc
tcyc
2
2
Table 20 lists specifications for the I C output timing parameters shown in Figure 22.
2
Table 20. I C Output Timing Specifications between SCL and SDA
Num
I11 Start condition hold time
I2 1 Clock low period
Characteristic
Min
Max
Units
6
10
—
7
—
—
—
—
3
tcyc
tcyc
µs
I3 2 I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
I4 1 Data hold time
tcyc
ns
I5 3 I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
I6 1 Clock high time
—
10
2
—
—
—
—
tcyc
tcyc
tcyc
tcyc
I7 1 Data setup time
I8 1 Start condition setup time (for repeated start condition only)
I9 1 Stop condition setup time
20
10
1
Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum
frequency (IFDR = 0x20) results in minimum output timings as shown in Table 20. The I2C interface is
designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual
position is affected by the prescale and division values programmed into the IFDR; however, the numbers
given in Table 20 are minimum values.
Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively
drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance
and pull-up resistor values.
2
3
Specified at a nominal 50-pF load.
Figure 22 shows timing for the values in Table 20 and Table 19.
I5
I6
I2
I2C_SCL
I2C_SDA
I7
I8
I1
I9
I4
I3
2
Figure 22. I C Input/Output Timings
MCF5301x Data Sheet, Rev. 5
36
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Preliminary Electrical Characteristics
5.13 Fast Ethernet AC Timing Specifications
The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing
specs/constraints for the physical interface.
5.13.1 Receive Signal Timing Specifications
The following timing specs meet the requirements for both MII and 7-Wire style interfaces for a range of transceiver devices.
Table 21. Receive Signal Timing
MII Mode
RMII Mode
Num
Characteristic
Unit
Min
Max
Min
Max
E1
E2
E3
E4
RXD[n:0], RXDV, RXER to RXCLK setup1
RXCLK to RXD[n:0], RXDV, RXER hold1
RXCLK pulse width high
5
—
—
4
—
—
ns
5
2
ns
35%
35%
65%
65%
35%
35%
65%
65%
RXCLK period
RXCLK period
RXCLK pulse width low
1
In MII mode, n = 3; In RMII mode, n = 1
E4
E3
E2
RXCLK (Input)
E1
RXD[n:0]
RXDV,
Valid Data
RXER
Figure 23. MII Receive Signal Timing Diagram
5.13.2 Transmit Signal Timing Specifications
Table 22. Transmit Signal Timing
MII Mode
RMII Mode
Num
Characteristic
Unit
Min
Max
Min
Max
E5
E6
E7
E8
TXCLK to TXD[n:0], TXEN, TXER invalid1
TXCLK to TXD[n:0], TXEN, TXER valid1
TXCLK pulse width high
5
—
5
—
ns
—
25
—
10
ns
35%
35%
65%
65%
35%
35%
65%
65%
tTXCLK
tTXCLK
TXCLK pulse width low
1
In MII mode, n = 3; In RMII mode, n = 1
MCF5301x Data Sheet, Rev. 5
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
37
Preliminary Electrical Characteristics
E8
TXCLK (Input)
E7
E5
E6
TXD[n:0]
TXEN,
TXER
Valid Data
Figure 24. MII Transmit Signal Timing Diagram
5.13.3 Asynchronous Input Signal Timing Specifications
Table 23. MII Transmit Signal Timing
Num
Characteristic
CRS, COL minimum pulse width
Min
Max
Unit
E9
1.5
—
TXCLK period
CRS, COL
E9
Figure 25. MII Async Inputs Timing Diagram
5.13.4 MII Serial Management Timing Specifications
Table 24. MII Serial Management Channel Signal Timing
Num
Characteristic
Symbol
Min
Max
Unit
E10
E11
E12
E13
E14
E15
MDC cycle time
MDC pulse width
tMDC
400
40
—
25
10
0
—
60
375
—
ns
% tMDC
ns
MDC to MDIO output valid
MDC to MDIO output invalid
MDIO input to MDC setup
MDIO input to MDC hold
ns
—
ns
—
ns
MCF5301x Data Sheet, Rev. 5
Preliminary—Subject to Change Without Notice
38
Freescale Semiconductor
Preliminary Electrical Characteristics
E10
E11
MDC (Output)
MDIO (Output)
MDIO (Input)
E11
E12
E13
Valid Data
E14
E15
Valid Data
Figure 26. MII Serial Management Channel TIming Diagram
5.14 32-Bit Timer Module Timing Specifications
Table 25 lists timer module AC timings.
Table 25. Timer Module AC Timing Specifications
Name
Characteristic
Min
Max
Unit
T1
T2
DT0IN / DT1IN / DT2IN / DT3IN cycle time
DT0IN / DT1IN / DT2IN / DT3IN pulse width
3
1
—
—
tCYC
tCYC
5.15 DSPI Timing Specifications
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with both master and slave operations. Many
of the transfer attributes are programmable. Table 26 provides DSPI timing characteristics for classic SPI timing modes. Refer
to the DSPI chapter of the MCF5301x Reference Manual for information on the modified transfer formats used for
communicating with slower peripheral devices.
1
Table 26. DSPI Module AC Timing Specifications
Name
Characteristic
DSPI_SCK Cycle Time
DSPI_SCK Duty Cycle
Symbol
Min
Max
Unit
Notes
2
DS1
DS2
tSCK
—
4 x tSYS
—
ns
ns
3
(tsck ÷ 2) – 2.0 (tsck ÷ 2) + 2.0
Master Mode
4
5
DS3
DS4
DS5
DS6
DS7
DS8
DSPI_PCSn to DSPI_SCK delay
tCSC
tASC
—
(2 × tSYS) – 1.5
—
—
5
ns
ns
ns
ns
ns
ns
DSPI_SCK to DSPI_PCSn delay
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
(2 × tSYS) – 3.0
—
–5
9
—
—
—
—
—
—
0
Slave Mode
DS9
DSPI_SCK to DSPI_SOUT valid
—
—
4
ns
MCF5301x Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
39
Preliminary Electrical Characteristics
Table 26. DSPI Module AC Timing Specifications (continued)
1
Name
Characteristic
Symbol
Min
Max
Unit
Notes
DS10 DSPI_SCK to DSPI_SOUT invalid
DS11 DSPI_SIN to DSPI_SCK input setup
DS12 DSPI_SCK to DSPI_SIN input hold
DS13 DSPI_SS active to DSPI_SOUT driven
DS14 DSPI_SS inactive to DSPI_SOUT not driven
—
—
—
—
—
0
2
—
—
—
20
18
ns
ns
ns
ns
ns
7
—
—
1
Timings shown are for DMCR[MTFE] = 0 (classic SPI) and DCTARn[CPHA] = 0. Data is sampled on the DSPI_SIN pin
on the odd-numbered DSPI_SCK edges and driven on the DSPI_SOUT pin on even-numbered DSPI edges.
2
3
When in master mode, the baud rate is programmable in DCTARn[DBR], DCTARn[PBR], and DCTARn[BR].
This specification assumes a 50/50 duty cycle setting. The duty cycle is programmable in DCTARn[DBR],
DCTARn[CPHA], and DCTARn[PBR].
4
5
The DSPI_PCSn to DSPI_SCK delay is programmable in DCTARn[PCSSCK] and DCTARn[CSSCK].
The DSPI_SCK to DSPI_PCSn delay is programmable in DCTARn[PASC] and DCTARn[ASC].
DS3
DS4
DSPI_PCSn
DS1
DS2
DSPI_SCK
(DCTARn[CPOL] = 0)
DS2
DSPI_SCK
(DCTARn[CPOL] = 1)
DS7
DS8
DSPI_SIN
Last Data
First Data
Data
Data
DS6
DS5
DSPI_SOUT
First Data
Last Data
Figure 27. DSPI Classic SPI Timing — Master Mode
MCF5301x Data Sheet, Rev. 5
40
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Preliminary Electrical Characteristics
DSPI_SS
DS1
DSPI_SCK
DS2
(DCTARn[CPOL] = 0)
DS2
DSPI_SCK
(DCTARn[CPOL] = 1)
DS13
DS9
DS10
Data
DS14
First Data
DSPI_SOUT
DSPI_SIN
Last Data
DS11
DS12
Data
Last Data
First Data
Figure 28. DSPI Classic SPI Timing — Slave Mode
5.16 eSDHC Electrical Specifications
This section describes the electrical information of the eSDHC.
5.16.1 eSDHC Timing
Figure 29 depicts the timing of eSDHC, and Table 29 lists the eSDHC timing characteristics.
SD2
SD1
SD4
SD5
SDHC_CLK
SD3
SD6
Output from eSDHC to card
SDHC_CMD
SDHC_DAT[3:0]
SD7
SD8
Input from card to eSDHC
SDHC_CMD
SDHC_DAT[3:0]
Figure 29. eSDHC Timing
MCF5301x Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
41
Preliminary Electrical Characteristics
Table 27. eSDHC Interfacde Timing Specifications
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
1
SD1 Clock Frequency (Low Speed)
Clock Frequency (SD/SDIO Full Speed)
Clock Frequency (MMC Full Speed)
Clock Frequency (Identification Mode)
SD2 Clock Low Time
fPP
0
0
400
25
20
400
—
—
3
kHz
MHz
MHz
kHz
ns
2
fPP
3
fPP
0
4
fOD
100
7
tWL
tWH
tTLH
tTHL
SD3 Clock High Time
7
ns
SD4 Clock Rise Time
—
—
ns
SD5 Clock Fall Time
3
ns
eSDHC Output / Card Inputs SDHC_CMD, SDHC_DAT (Reference to SDHC_CLK)
SD6 eSDHC Output Delay tOD
eSDHC Input / Card Outputs SDHC_CMD, SDHC_DAT (Reference to SDHC_CLK)
–5
5
ns
SD7 eSDHC Input Setup Time
SD8 eSDHC Input Hold Time
tISU
tIH
4
0
—
—
ns
ns
1
2
3
4
In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.
In normal data transfer mode for SD/SDIO card, clock frequency can be any value from 0 to 25 MHz.
In normal data transfer mode for MMC card, clock frequency can be any value from 0 to 20 MHz.
In card identification mode, card clock must be 100 kHz – 400 kHz, voltage ranges from 2.7 to 3.6 V.
5.16.2 eSDHC Electrical DC Characterisics
Table 28 lists the eSDHC electrical DC characteristics.
Table 28. MMC/SD Interface Electrical Specifications
Design
Value
Num
Parameter
Min
Max
Unit
Condition/Remark
General
1
Peak Voltage on All Lines
Input Leakage Current
—
—
–0.3
–10
–10
2.7
VDD + 0.3
V
uA
uA
V
All Inputs
2
10
10
All Outputs
3
Output Leakage Current
—
Power Supply
4
5
Supply Voltage (HV card)
3.1
3.6
for high voltage cards, must
provide this voltage for card
initialization
Supply Voltage (LV card)
1.8
1.65
1.95
V
for low voltage cards
MCF5301x Data Sheet, Rev. 5
Preliminary—Subject to Change Without Notice
42
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 28. MMC/SD Interface Electrical Specifications (continued)
Design
Value
Num
Parameter
Min
Max
Unit
Condition/Remark
5
6
Power Up Time
Supply Current
—
—
—
250
200
ms
100
mA
Bus Signal Line Load
7
8
Pull-up Resistance
Open Drain Resistance
47
10
100
NA
kohm Internal PU
NA
NA
kohm For MMC cards only
For MMC cards only
Open Drain Signal Level
9
Output High Voltage
Output Low Voltage
—
—
V
DD – 0.2
—
V
V
IOH = –100 µA
IOL= 2 mA
10
—
0.3
Bus Signal Levels
11
12
Output HIGH Voltage
—
—
0.75 x VDD
—
—
V
V
IOH = –100 µA @VDD min
IOL = 100 µA @VDD min
Output LOW Voltage
0.125 x VDD
13
14
Input HIGH Voltage
Input LOW Voltage
—
—
0.625 x VDD
VSS – 0.3
VDD + 3
V
V
0.25 x VDD
5.17 SIM Electrical Specifications
Each SIM card interface consist of a total of 12 pins (two separate ports of six pins each. Mostly one port with 5 pins is used).
The interface is meant to be used with synchronous SIM cards. This means that the SIM module provides a clock for the SIM
card to use. The frequency of this clock is normally 372 times the data rate on the TX/RX pins, however SIM module can work
with CLK equal to 16 times the data rate on TX/RX pins.
There is no timing relationship between the clock and the data. The clock that the SIM module provides to the SIM card is used
by the SIM card to recover the clock from the data, like a standard UART. All six (or five when a bidirectional TXRX is used)
of the pins for each half of the SIM module are asynchronous to each other. There are no required timing relationships between
the signals in normal mode. However, there are some in reset and power down sequences.
5.17.1 General Timing Requirements
Figure 30 shows the timing of the SIM module, and Table 29 lists the timing parameters.
1/Sfreq
SIM_CLK
Sfall
Srise
Figure 30. SIM Clock Timing Diagram
MCF5301x Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
43
Preliminary Electrical Characteristics
Table 29. SIM Timing Specification—High Drive Strength
Num
Description
Symbol
Min
Max
Unit
1
SIM Clock Frequency (SIM_CLK)1
Sfreq
0.01
5 (Some new cards
may reach 10)
MHz
2
3
4
SIM_CLK Rise Time 2
Srise
Sfall
–
–
–
20
20
25
ns
ns
ns
SIM_CLK Fall Time 3
SIM Input Transition Time (RX, SIM_PD)
Strans
1
2
3
50% duty cycle clock
With C = 50pF
With C = 50pF
5.17.2 Reset Sequence
5.17.2.1 Cards with Internal Reset
The reset sequence for this kind of SIM card is as follows (see Figure 31):
•
•
•
After powerup, the clock signal is enabled on SIM_CLK (time T0)
After 200 clock cycles, RX must be high.
The card must send a response on RX acknowledging the reset between 400 and 40,000 clock cycles after T0.
SIM_VEN
SIM_CLK
Response
SIM_RX
1
2
1
2
< 200 clock cycles
T0
400 clock cycles <
< 40,000 clock cycles
Figure 31. Internal-Reset Card Reset Sequence
5.17.2.2 Cards with Active-Low Reset
The sequence of reset for this kind of card is as follows (see Figure 32):
1. After powerup, the clock signal is enabled on SIM_CLK (time T0)
2. After 200 clock cycles, RX must be high.
3. SIM_RST must remain low for at least 40,000 clock cycles after T0 (no response is to be received on RX during those
40,000 clock cycles)
4. SIM_RST is set high (time T1)
5. SIM_RST must remain high for at least 40,000 clock cycles after T1 and a response must be received on RX between
400 and 40,000 clock cycles after T1.
MCF5301x Data Sheet, Rev. 5
44
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Preliminary Electrical Characteristics
SIM_VEN
SIM_RST
SIM_CLK
SIM_RX
Response
2
1
3
3
T0
T1
< 200 clock cycles
1
2
3
400 clock cycles <
< 40,000 clock cycles
400,000 clock cycles <
Figure 32. Active-Low-Reset Card Reset Sequence
5.17.3 Power Down Sequence
Power down sequence for SIM interface is as follows:
1. SIM_PD port detects the removal of the SIM card
2. SIM_RST goes low
3. SIM_CLK goes low
4. SIM_TX goes low
5. SIM_VEN goes low
Each of these steps is completed in one CKIL period (usually 32 kHz). Power-down may be started in response to a
card-removal detection or launched by the processor. Figure 33 and Table 30 show the usual timing requirements for this
sequence, with Fckil = CKIL frequency value.
Table 30. Timing Requirements for Power Down Sequence
Num
Description
Symbol
Min
Max
Unit
1
2
3
4
SIM reset to SIM clock stop
Srst2clk
Srst2dat
Srst2ven
Spd2rst
0.9 ÷ fCKIL
1.8 ÷ fCKIL
2.7 ÷ fCKIL
0.9 ÷ fCKIL
0.8
1.2
1.8
25
µs
µs
µs
ns
SIM reset to SIM TX data low
SIM reset to SIM Voltage Enable Low
SIM Presence Detect to SIM reset Low
MCF5301x Data Sheet, Rev. 5
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
45
Preliminary Electrical Characteristics
Spd2rst
SIM_PD
SIM_RST
Srst2clk
SIM_CLK
SIM__TX
Srst2dat
Srst2ven
SIM_VEN
Figure 33. SmartCard Interface Power-Down AC Timing
5.18 IIM/Fusebox Electrical Specifications
Table 31. IIM/Fusebox Timing Characteristics
Num
Description
Program time for eFuse1
Symbol
Min
Max
Unit
1
tprogram
125
—
µs
1
The program length is defined by the value defined in IIM_FCR[PRG_LENGTH] of the IIM module. The value to program is
based on a 32 kHz clock source (4 ÷ 32 kHz = 125 μs)
5.19 Voice Codec
The voice codec function is analog-to-digital and digital-to-analog conversion of the voice signal. The following section
contains detailed electrical specifications for the analog and digital parts’ performance. The voice codec is powered down when
not enabled for power consumption.
MCF5301x Data Sheet, Rev. 5
46
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 32 shows the voice codec general specifications.
Table 32. Voice Codec General Specifications
Parameter
Condition
VCLK[2:0]=0
VCLK[2:0]=1,2
VCLK[2:0]=3
VCLK[2:0]=4
VCLK[2:0]=5
VCLK[2:0]=6
VCLK[2:0]=7
Min
Typ
Max
Units
CODEC Input clock CODEC_CLK
—
—
—
—
—
—
—
16.8
19.44
20.0
24.0
26.0
28.0
30.0
—
—
—
—
—
—
—
MHz
MHz
MHz
MHz
MHz
MHz
MHz
VAG input Voltage
No Load,
1.225
1.325
1.425
V
AVDD (CODEC_REGBYP) =
2.5V
Ref_Codec_p
TBD
TBD
—
1.665
0.985
0.1
TBD
TBD
—
V
V
Ref_Codec_n
VAG External Cap
μF
μF
μF
μF
mA
avoco_ref_codec_p External Cap
avoco_ref_codec_n External Cap
avoco_vagout_codec External Cap
—
0.1
—
—
0.1
—
—
0.1
—
Codec Analog Supply Current
(includes Rx and Tx paths)
AVDD (CODEC_REGBYP) =
2.5V, operational
—
5
6
Power-down mode
Operational mode
—
—
—
—
—
—
5
1
1
μA
mA
ms
Codec Digital Supply Current1
Response to input ON/OFF
(settling time at turn on)
1
More accurate estimation will be given after some progress in design.
5.19.1 Voice Codec ADC Specifications
Voice coding function includes a 50 kHz second-order, low-pass anti-aliasing filter, an analog-to-digital converter, digital filters
for decimation, band-passing, frequency ripple compensation, and DSP interface logic. The audio input A/D converter converts
the incoming signal to 13-bit two’s-compliment linear PCM words at an 8 or 8.1 kHz rate. Following the A/D converter, the
signal is digitally filtered, low-pass, and selectable high-pass. Table 33 shows the voice coding specifications.
1
Table 33. Voice Codec ADC Specifications
Parameter
Condition
20Hz to 100kHz,
with 100 mVpp noise applied to AVDD,
with an external VAG cap
Min
Typ
Max
Units
Power Supply Rejection Ratio
with respect to
50
60
—
dB
AVDD (CODEC_REGBYP)2
Peak Input
(+3dBm0)3 on an individual differential VAG–0.34
pin (ADC_P or ADC_M)
—
VAG+0.34
V
Tx AC Input Impedance
Absolute Gain
f=1.02kHz
100
—
—
—
kΩ
0dBm0@1.02kHz
–1.0
1.0
dB
MCF5301x Data Sheet, Rev. 5
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
47
Preliminary Electrical Characteristics
Table 33. Voice Codec ADC Specifications (continued)
1
Parameter
Gain vs. Signal
Condition
Min
Typ
Max
Units
Relative to –10dBm0 @1.02kHz
+3 to –40dBm0
–40 to –50dBm0
–0.25
–1.2
–1.3
—
—
—
0.25
1.2
1.3
dB
dB
dB
–50 to –55dBm0
Total Distortion
1.02kHz tone (linear)
(noise and harmonic)
(300Hz – 20kHz Noise BW in
300Hz – 4kHz measured BW
out)
+2dBm04
0dBm0
57
60
60
55
45
35
25
20
15
60
64
70
65
55
45
35
30
20
—
—
—
—
—
—
—
—
—
dB
dB
dB
dB
dB
dB
dB
dB
dB
–6dBm0
–10dBm0
–20dBm0
–30dBm0
–40dBm0
–45dBm0
–55dBm0
Idle Channel Noise5
Digital Offset6
Psophometric Weighting at the output
—
—
—
—
–72
5
dBm0p
%Full
Scale
Frequency Response
VCIHPF = logic high
Relative to 0dBm0@1.02kHz
50Hz
–8
–0.5
–1.0
—
—
—
—
—
—
—
—
—
—
–25
–23
–0.5
+0.5
+0.1
–14
–35
dB
dB
dB
dB
dB
dB
dB
60Hz7
200Hz
300 to 3000Hz
3400Hz8
4000Hz
4600Hz
—
Frequency Response
VCIHPF=logic low
Relative to 0dBm0@1.02kHz
50Hz
200Hz
300 to 3000Hz
3400Hz9
4000Hz
4600Hz
–0.5
–0.5
–0.5
–1.0
—
—
—
—
—
—
—
+0.5
+0.5
+0.5
+0.1
–14
dB
dB
dB
dB
dB
dB
—
–35
Inband Spurious
1.02kHz @ 0dBm0,
300 to 3kHz
—
—
–48
dB
Crosstalk D/A to A/D
D/A = 0 dBm0 @1.02kHz
Measured while stimulated w/ 2667Hz
@–50dBm0
—
—
–75
dB
Intermodulation Distortion
Two frequencies of amplitudes –4 to
–21 dBm0 from the range 300 to
3400Hz
—
—
–41
dB
MCF5301x Data Sheet, Rev. 5
48
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 33. Voice Codec ADC Specifications (continued)
1
Parameter
Filter Group Delay
Condition
500Hz < f < 600Hz
600Hz < f < 800Hz
800Hz < f < 1kHz
1kHz < f < 1.6kHz
1.6kHz < f < 2.6kHz
2.6kHz < f < 2.8kHz
2.8kHz < f < 3.0kHz
Min
Typ
Max
Units
—
—
—
—
—
—
—
—
—
—
—
—
—
—
260
155
57
15
95
μS
μS
μS
μS
μS
μS
μS
VCIHPF=logic high
CODEC_CLK=26MHz
(Relative to 1.6kHz)
135
190
Filter Group Delay
VCIHPF=logic low
CODEC_CLK=26MHz
(Relative to 1.6kHz)
f < 1.6kHz
–40
0
—
—
—
—
—
—
0
μS
μS
μS
μS
1.6kHz < f < 2.6kHz
2.6kHz < f < 2.8kHz
2.8kHz < f < 3.0kHz
100
150
200
Filter Absolute Group Delay
VCIHPF=logic high
f=1.6kHz
—
—
—
—
—
—
300
235
–50
μS
μS
dB
Filter Absolute Group Delay
VCIHPF=logic low
f=1.6kHz
Out of Band input fold-in
spurious
with 0dBm0 input signal from 4.6 kHz
to 8.4 kHz
1
All analog signals are referenced to VAG unless otherwise noted.
2
Power Supply Rejection Ratio is for Longjing IC only. Total PSRR from battery to output is obtained by summing the
PSRR from Neptune to the one from the Regulator in Seaweed. It is assumed that the regulators in Seaweed will
have a minimum PSRR of 45 dB.
3
4
For A/D differential input (ADC_P - ADC_M) 0dBm0 = 340mVrms
The codec output will not “foldback” or oscillate if overdriven, but clip.
.
The digital word corresponding to +3dBm0 is ‘0111111111111’b. Therefore if the audio level is set to +3dBm0, any
variation in gain could cause large distortion if the digital number exceeds ‘0111111111111’b. For this reason the
maximum recommended signal for low distortion is +3dBm0 − (Absolute Gain Error) = +2dBm0.
5
6
7
8
9
GSM Spec = –64 0dB.
This value is a preliminary target. The final number will be specified after obtaining the production statistical data.
Small frequency response deviation from straight line in the 60:200 Hz range is acceptable by spec requirements.
Small frequency response deviation from straight line in the 3400:4000 Hz range is acceptable by spec requirements.
Small frequency response deviation from straight line in the 3400:4000 Hz range is acceptable by spec requirements.
MCF5301x Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
49
Preliminary Electrical Characteristics
Figure 34 and Figure 35 show the filter frequency response for the audio signal for voice coding path. (All filter frequencies
increase by 8.1/8.0 if VCLK is selected to generate f
=8.1kHz).
SYNC
4
+0.1dB
@ 3.4kHz
+0.5dB @ 3.0kHz
0
-5
-0.5dB
@ 3.0kHz
-1.0dB
@ 3.4kHz
-14dB
@ 4.0kHz
-10
-15
dB
-20
-25
-30
-35dB
@ 4.6kHz
-35
-38
20
30 40 50
70
100
200
300 400 500 700 1000
2000
3000 4000 5000
8000
Hz
Figure 34. Voice Signal Frequency Response Requirements at the ADC Path
(VCIHPF=0, LPF Alone Without HPF)
MCF5301x Data Sheet, Rev. 5
50
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Preliminary Electrical Characteristics
4
0
+0.5dB @ 3.0kHz
+0.5dB @ 300Hz
-0.5dB
@ 200Hz
-0.5dB
@ 3.0kHz
+0.1dB
@ 3.4kHz
-0.5dB
@ 300Hz
-5
-10
-15
-20
-25
-30
-35
-1.0dB
@ 3.4kHz
-14dB
@ 4.0kHz
-8.0dB
@ 200Hz
-23dB
@ 60Hz
dB
-25dB
@ 50Hz
-35dB
@ 4.6kHz
-38
20
30 40 50
70
100
200
300 400 500 700
1000
2000 3000 40005000
8000
Hz
Figure 35. Voice Signal Frequency Response Requirements at the ADC Path
(VCIHPF=1, HPF and LPF Together)
5.19.2 Voice Codec DAC Specifications
Voice-decoding function includes frequency ripple compensation, interpolation, digital-to-analog conversion, and anti-imaging
filter. The input signal for the voice-decoding function is in linear 16-bit two’s compliment PCM words at an 8 kHz or 8.1 kHz
rate. Table 34 shows the voice decoding specifications.
1
Table 34. Voice Codec DAC Specifications
Parameter
Output Level
Condition
Min
Typ
Max
Units
+3dbm02 (clipping level) on an
individual differential output pin
(CODEC_DACP or CODEC_DACN)
VAG–0.5
—
VAG+0.5
V
Output Source Impedance
10kΩ Load
—
100
60
—
—
Ω
Output Power Supply Rejection
Ratio
20Hz to 100kHz with 100 mVrms,
noise applied to AVDD
50
dBa
(CODEC_REGBYP)
Absolute Gain
Gain vs. Signal
0dBm0@1.02kHz
–1.0
—
1.0
dB
–10dBm0@1.02kHz
+3 to –40dBm0
–40 to –50dB
–50 to –55dBm0
–0.25
–1.2
–1.3
—
—
—
0.25
1.2
1.3
dB
dB
dB
MCF5301x Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
51
Preliminary Electrical Characteristics
Table 34. Voice Codec DAC Specifications (continued)
1
Parameter
Total Distortion
Condition
Min
Typ
Max
Units
1.02 kHz tone (linear)
+2 dBm0
0 dBm0
57
60
60
55
45
35
25
20
15
60
64
70
65
55
45
35
30
20
—
—
—
—
—
—
—
—
—
dB
dB
dB
dB
dB
dB
dB
dB
dB
(4 kHz noise BW in
300 Hz – 20 kHz measured BW –6 dBm0
out)
–10 dBm0
–20 dBm0
–30 dBm0
–40 dBm0
–45 dBm0
–55 dBm0
Idle Channel Noise3
(At CODEC out)
A weighted to 20kHz
—
–78
–73
dBm0
8kHz, 30Hz BW, D/A = zero code
No spurious
Differential offset
TA = 70 ° C
TA = 25 ° C
—
—
—
—
40
30
mV
Frequency Response
VCOHPF = logic high
Relative to 0dBm0@1.02kHz
50Hz
—
—
–8
–0.5
–0.8
—
—
—
—
—
—
—
—
–25
–23
–0.5
+0.5
+0.1
–14
–35
dB
dB
dB
dB
dB
dB
dB
(Min. limit valid for
CODEC_CLK=26MHz)
60Hz4
200Hz
300–3000Hz
3400Hz5
4000Hz
4600Hz
—
Frequency Response
VCOHPF = logic low
Relative to 0dBm0@1.02kHz
50Hz
200Hz
300–3000Hz
3400Hz6
4000Hz
4600Hz
–0.5
–0.5
–0.5
–0.8
—
—
—
—
v
—
—
+0.5
+0.5
+0.5
+0.1
–14
dB
dB
dB
dB
dB
dB
(Min. limit valid for
CODEC_CLK=26MHz)
—
–35
Inband Spurious
1.02kHz @ 0dBm0, 300 to 3kHz
300 to 3400Hz @ 0dBm0 input
—
—
—
—
–48
dB
Out-of-Band Spurious
(Interpolation Image Suppression)
4600 to 7600Hz
7600 to 8400Hz
8400 to 20,000Hz
–50
–50
–50
dB
dB
dB
Crosstalk A/D to D/A
A/D = 0dBm0 @1.02kHz
—
—
—
—
–75
–41
dB
dB
Intermodulation Distortion
Two frequencies. of amplitudes –4 to
–21 dBm0 from the range 300 to
3400Hz
MCF5301x Data Sheet, Rev. 5
52
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 34. Voice Codec DAC Specifications (continued)
1
Parameter
Filter Group Delay
VCOHPF = logic high
CODEC_CLK=26 MHz
(Relative to 1.6kHz)
Condition
500Hz < f < 600Hz
600Hz < f < 800Hz
800Hz < f < 1kHz
1kHz < f < 1.6kHz
1.6kHz < f < 2.6kHz
2.6kHz < f < 2.8kHz
2.8kHz < f < 3.0kHz
Min
Typ
Max
Units
—
—
—
—
—
—
—
—
—
—
—
—
—
—
300
200
70
30
95
μs
μs
μs
μs
μs
μs
μs
135
190
Filter Group Delay
VCOHPF = logic low
CODEC_CLK=26 MHz (Relative 2.6kHz < f < 2.8kHz
to 1.6kHz)
f < 1.6kHz
1.6kHz < f < 2.6kHz
–40
0
—
—
—
—
—
—
0
μs
μs
μs
μs
100
160
200
2.8kHz < f < 3.0kHz
Filter Absolute Group Delay
VCOHPF = logic high
f=1.6kHz
—
—
350
μs
Filter Absolute Group Delay
VCOHPF = logic low
f=1.6kHz
—
—
320
μs
1
2
3
4
5
6
All analog signals are referenced to VAG unless otherwise noted. Output is 0dbm0 unless noted.
For D/A differential output (CODEC_DACP - CODEC_DACN) 0dBm0 = 500 mVrms
GSM Spec = –64.
.
Small frequency response deviation from straight line in the 60:200 Hz range is acceptable by spec requirements.
Small frequency response deviation from straight line in the 3400:4000 Hz range is acceptable by spec requirements.
Small frequency response deviation from straight line in the 3400:4000 Hz range is acceptable by spec requirements.
MCF5301x Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
53
Preliminary Electrical Characteristics
Figure 36 and Figure 37 show the filter frequency response for the audio signal for voice decoding. The requirements for the
decoding path at 3.4 kHz are slightly different from the coding path. (All filter frequencies increase by 8.1/8.0 if VCLK is
selected to generate f
= 8.1 kHz).
SYNC
4
+0.1dB
@ 3.4kHz
+0.5dB @ 3.0kHz
0
-0.5dB
@ 3.0kHz
-5
-0.8dB
@ 3.4kHz
-14dB
@ 4.0kHz
-10
-15
-20
-25
-30
dB
-35dB
@ 4.6kHz
-35
-38
20
30 40 50 70
100
200
300 400 500 700 1000
2000 300040005000 8000
Hz
Figure 36. Voice Signal Frequency Response Requirements at the DAC Path
(VCOHPF=0, LPF Alone Without HPF)
MCF5301x Data Sheet, Rev. 5
54
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Preliminary Electrical Characteristics
4
0
+0.5dB @ 3.0kHz
+0.5dB @ 300Hz
-0.5dB
@ 200Hz
-0.5dB
@ 3.0kHz
+0.1dB
@ 3.4kHz
-0.5dB
@ 300Hz
-5
-10
-15
-20
-25
-30
-35
-0.8dB
@ 3.4kHz
-14dB
@ 4.0kHz
-8.0dB
@ 200Hz
-23dB
@ 60Hz
dB
-25dB
@ 50Hz
-35dB
@ 4.6kHz
-38
20
30 40 50
70
100
200
300 400 500 700
1000
2000 3000 40005000
8000
Hz
Figure 37. Voice Signal Frequency Response Requirements at the DAC Path
(VCOHPF=1, HPF and LPF Together)
5.20 Integrated Amplifiers
5.20.1 Speaker Amplifier
The speaker amplifier boosts the power from the DAC and drives the speaker. It also provides analog volume control to optimize
the noise performance of the entire channel. Table 35 shows the specifications for the speaker amplifier.
Table 35. Speaker Amplifier Specifications
Parameter
Quiescent Current
Conditions
Min
Typ
Max
Units
—
—
—
—
—
—
—
—
—
800
TBD
2
—
—
5
μA
Shutdown Current
Input Reference Offset
Max Output Power
mV
mW
%
F
in = 1kHz, THD+N = 1%, RL = 4Ω
600
0.050
0.050
0.1
—
—
—
—
—
—
Total Harmonic Distortion (THD)
Gain = 0dB,
Full Power, 500mW
Half Power, 250mW
Full Power, 500mW
Half Power, 250mW
RL = 4Ω, Fin = 1kHz
Gain = 0dB,
RL = 4Ω, Fin = 4kHz
0.1
Integrated Output Noise
Freescale Semiconductor
Gain = 0dB, BW = 20Hz – 20kHz
15
μV
MCF5301x Data Sheet, Rev. 5
Preliminary—Subject to Change Without Notice
55
Preliminary Electrical Characteristics
Table 35. Speaker Amplifier Specifications (continued)
Parameter
Conditions
Min
Typ
Max
Units
Signal to Noise Ratio (SNR)
Gain = 0dB, VOUT = 1.4VRMS
,
—
99
—
dB
BW = 20Hz – 20kHz
Power Supply Rejection Ratio
(PSRR)
Gain = 0dB,
ripple = 200mVpp
f = 217Hz
f = 1kHz
f = 4kHz
—
—
—
—
—
—
60
60
—
—
—
—
—
—
dB
V
60
Max. Cap Load Drive
Output SC Current
Gain Error
No Sustained Oscillations
300
625
0.5
pF
mA
dB
Gain = –45,–21, –6, 0, 4, 6 dB
5.20.2 Handset Amplifier
The handset amplifier boosts the power from the DAC and drives the handset. It also provides analog volume control to
optimize the noise performance of the entire channel. Table 36 shows the specifications for handset amplifier.
Table 36. Handset Amplifier Specifications
Parameter
Quiescent Current
Conditions
Min
Typ
Max
Units
—
—
—
—
—
—
—
—
—
—
800
TBD
2
—
—
5
μA
Shutdown Current
Input Reference Offset
Max. Output Power
mV
mW
%
Fin = 1kHz, THD + N = 1%, RL = 8Ω
300
0.050
0.050
0.1
—
—
—
—
—
—
—
Total Harmonic Distortion (THD)
Gain = 0dB,
Full Power, 250mW
Half Power, 125mW
Full Power, 250mW
Half Power, 125mW
RL = 8Ω, Fin = 1kHz
Gain = 0dB,
RL = 8Ω, Fin = 4kHz
0.050
15
Integrated Output Noise
Gain = 0dB, BW = 20Hz – 20kHz
μV
Signal to Noise Ratio (SNR)
Gain = 0dB, VOUT = 1.4VRMS
BW = 20Hz – 20kHz
,
99
dB
Power Supply Rejection Ratio
(PSRR)
Gain = 0dB,
Vripple = 200mVpp
f = 217Hz
f = 1kHz
f = 4kHz
—
—
—
—
—
—
60
60
—
—
—
—
—
—
dB
60
Maximum Cap Load Drive
Output SC Current
Gain Error
No Sustained Oscillations
300
325
0.5
pF
mA
dB
Gain = –45, –21, –6, 0, 4, 6 dB
MCF5301x Data Sheet, Rev. 5
56
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Preliminary Electrical Characteristics
5.20.3 Headphone Amplifier
The headphone amplifier boosts the power from the DAC and drives the headphone. It also provides analog volume control to
optimize the noise performance of the entire channel. Table 37 shows the specifications for the microphone amplifier.
Table 37. Headphone Amplifier Specifications
Parameter
Quiescent Current
Conditions
Min
Typ
Max
Units
—
—
—
—
—
—
—
—
600
TBD
2
—
—
5
μA
Shutdown Current
Input Reference Offset
Output Power
mV
mW
%
F
in = 1kHz, THD+N = 1%, RL = 16Ω
40
—
—
—
—
—
Total Harmonic Distortion (THD)
Gain = 0dB, RL = 16Ω, Full Power, 31.25mW
0.05
0.05
15
BW = 200Hz – 4kHz
Half Power, 16.5mW
Integrated Output Noise
Gain = 0dB, BW = 20Hz – 20kHz
μV
Signal to Noise Ratio (SNR)
Gain = 0dB, VOUT = 0.7VRMS
BW = 20Hz – 20kHz
,
93
dB
Power Supply Rejection Ratio
(PSRR)
Gain = 0dB,
Vripple = 200mVpp
f = 217Hz
f = 1kHz
f = 4kHz
—
—
—
—
—
—
60
60
—
—
—
—
—
—
dB
60
Maximum Cap Load Drive
Output SC Current
Gain Error
No Sustained Oscillations
300
150
0.5
pF
mA
dB
Gain = –45, –21, –12, –6, –2, 0 dB
5.20.4 Microphone Amplifier
The microphone amplifier boosts the signal from the microphone and provides it to the ADC. The gain control present in the
microphone amplifier helps in optimizing the noise performance of the entire channel. Table 38 shows the specifications for the
microphone amplifier.
Table 38. Microphone Amplifier Specifications
Parameter
Quiescent Current
Conditions
Min
Typ
Max
Units
—
—
—
500
TBD
2
—
—
5
μA
Shutdown Current
Input Reference Offset
mV
MCF5301x Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
57
Preliminary Electrical Characteristics
Table 38. Microphone Amplifier Specifications (continued)
Parameter
Conditions
VOUT = 0.5VRMS
VOUT = 0.35VRMS
OUT = 0.5VRMS
VOUT = 0.35VRMS
OUT = 0.5VRMS
Min
Typ
Max
Units
Total Harmonic Distortion (THD)
Gain = 0dB, Fin = 1k
Gain = 20dB, Fin = 1k
Gain = 0dB, Fin = 4k
Gain = 20dB, Fin = 4k
BW = 20Hz – 20kHz
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.5
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
24.0
%
V
V
VOUT = 0.35VRMS
VOUT = 0.5VRMS
VOUT = 0.35VRMS
Integrated Output Noise
Signal to Noise Ratio (SNR)
THD plus Noise
Gain = 0dB
Gain = 20dB
Gain = 0dB
Gain = 20dB
Gain = 0dB
Gain = 20dB
f = 1kHz
μV
dB
dB
dB
dB
40
VOUT = 0.5VRMS
BW = 20Hz – 20kHz
,
92.4
81.9
80
VOUT = 0.35VRMS
BW = 20Hz – 20kHz
,
80
Power Supply Rejection Ratio
Commom Mode Rejection Ratio
Gain = 0dB,
60
Vripple = 200mVpp
f = 4kHz
60
Gain = 0dB,
f = 1kHz
50
Vripple = 100mVpp
f = 4kHz
50
Gain Error
Gain = 0, 6, 9.56, 15.56, 20, 24, 29.56, 39.9 dB
Depends on the Gain Setting
0.5
dB
Input Impedance
—
kΩ
5.21 JTAG and Boundary Scan Timing
Table 39. JTAG and Boundary Scan Timing
Num
Characteristics1
TCLK Frequency of Operation
Symbol
Min
Max
Unit
J1
J2
J3
J4
J5
J6
J7
J8
J9
fJCYC
tJCYC
DC
4
1/4
—
—
3
fsys/3
tCYC
ns
TCLK Cycle Period
TCLK Clock Pulse Width
tJCW
26
0
TCLK Rise and Fall Times
tJCRF
ns
Boundary Scan Input Data Setup Time to TCLK Rise
Boundary Scan Input Data Hold Time after TCLK Rise
TCLK Low to Boundary Scan Output Data Valid
TCLK Low to Boundary Scan Output High Z
TMS, TDI Input Data Setup Time to TCLK Rise
tBSDST
tBSDHT
tBSDV
4
—
—
33
33
—
—
ns
26
0
ns
ns
tBSDZ
0
ns
tTAPBST
tTAPBHT
4
ns
J10 TMS, TDI Input Data Hold Time after TCLK Rise
10
ns
MCF5301x Data Sheet, Rev. 5
Preliminary—Subject to Change Without Notice
58
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 39. JTAG and Boundary Scan Timing (continued)
Num
Characteristics1
Symbol
Min
Max
Unit
J11 TCLK Low to TDO Data Valid
J12 TCLK Low to TDO High Z
tTDODV
tTDODZ
tTRSTAT
tTRSTST
0
0
26
8
ns
ns
ns
ns
J13 TRST Assert Time
100
10
—
—
J14 TRST Setup Time (Negation) to TCLK High
1
JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.
J2
J3
J3
VIH
TCLK
(input)
VIL
J4
J4
Figure 38. Test Clock Input Timing
TCLK
VIL
VIH
J5
J6
Data Inputs
Input Data Valid
J7
J8
Data Outputs
Output Data Valid
Data Outputs
Data Outputs
J7
Output Data Valid
Figure 39. Boundary Scan (JTAG) Timing
MCF5301x Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
59
Preliminary Electrical Characteristics
TCLK
VIL
VIH
J9
Input Data Valid
J10
TDI
TMS
J11
TDO
Output Data Valid
J12
J11
TDO
TDO
Output Data Valid
Figure 40. Test Access Port Timing
TCLK
TRST
J14
J13
Figure 41. TRST Timing
5.22 Debug AC Timing Specifications
Table 40 lists specifications for the debug AC timing parameters shown in Figure 42.
Table 40. Debug AC Timing Specification
Num
Characteristic
PSTCLK cycle time
Min
Max
Units
D0
D1
D2
D3
D41
D5
D6
1.5
—
1.5
1
1.5
3.0
—
tSYS
ns
PSTCLK rising to PSTDDATA valid
PSTCLK rising to PSTDDATA invalid
DSI-to-DSCLK setup
ns
—
PSTCLK
PSTCLK
PSTCLK
PSTCLK
DSCLK-to-DSO hold
4
—
DSCLK cycle time
5
—
BKPT assertion time
1
—
1
DSCLK and DSI are synchronized internally. D4 is measured from the synchronized
DSCLK input relative to the rising edge of PSTCLK.
MCF5301x Data Sheet, Rev. 5
60
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Package Information
D0
PSTCLK
D2
D1
PSTDDATA[7:0]
Figure 42. Real-Time Trace AC Timing
D5
DSCLK
DSI
D3
Current
D4
Next
DSO
Past
Current
Figure 43. BDM Serial Port AC Timing
6
Package Information
The latest package outline drawings are available on the product summary pages on our web site:
http://www.freescale.com/coldfire. The following table lists the package case number per device. Use these numbers in the web
page keyword search engine to find the latest package outline drawings.
Table 41. Package Information
Device
Package Type
Case Outline Number
MCF53010
MCF53011
MCF53012
MCF53013
MCF53014
MCF53015
MCF53016
MCF53017
208 LQFP
98ASS23458W
256 MAPBGA
98ARH98219A
7
Product Documentation
Documentation is available from a local Freescale distributor, a Freescale sales office, the Freescale Literature Distribution
Center, or through the Freescale world-wide web address at http://www.freescale.com/coldfire.
MCF5301x Data Sheet, Rev. 5
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
61
8
Revision History
Table 42 summarizes revisions to this document.
Table 42. Revision History
Revision
Date
Location
Changes
3
4
12 Aug 2009
10 Feb 2010
—
Initial public revision
Table 8
Table 41
Added thermal characteristics for 208LQFP package
Added 208LQFP case outline number
5
3 Mar 2010
Table 2
Added non-J suffixed part numbers for the 256MAPBGA package
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Document Number: MCF53017
Rev. 5
3/2010
Preliminary—Subject to Change Without Notice
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