MCZ33903C5EK/R2 [FREESCALE]
SBC Gen2 with CAN High Speed and LIN Interface;
| 型号： | MCZ33903C5EK/R2 |
| 厂家： | 
Freescale |
| 描述： | SBC Gen2 with CAN High Speed and LIN Interface |
| 文件： | 总106页 (文件大小：1584K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MC33903_4_5
Rev. 9.0, 2/2012
Freescale Semiconductor
Technical Data
SBC Gen2 with CAN High Speed
and LIN Interface
33903/4/5
The 33903/4/5 is the second generation family of the System Basis
Chip (SBC). It combines several features and enhances present
module designs. The device works as an advanced power
management unit for the MCU with additional integrated circuits such
as sensors and CAN transceivers. It has a built-in enhanced high-speed
CAN interface (ISO11898-2 and -5) with local and bus failure
diagnostics, protection, and fail-safe operation modes. The SBC may
include zero, one or two LIN 2.1 interfaces with LIN output pin switches.
It includes up to four wake-up input pins that can also be configured as
output drivers for flexibility.
SYSTEM BASIS CHIP
This device implements multiple Low-power (LP) modes, with very
low-current consumption. In addition, the device is part of a family
concept where pin compatibility adds versatility to module design.
EK Suffix (Pb-free)
98ASA10506D
54-PIN SOIC
EK Suffix (Pb-free)
98ASA10556D
32-PIN SOIC
The 33903/4/5 also implements an innovative and advanced fail-safe
state machine and concept solution.
Features
• Voltage regulator for MCU, 5.0 or 3.3 V, part number selectable, with
possibility of usage external PNP to extend current capability and
share power dissipation
• Voltage, current, and temperature protection
• Extremely low quiescent current in LP modes
• Fully-protected embedded 5.0 V regulator for the CAN driver
• Multiple under-voltage detections to address various MCU
specifications and system operation modes (i.e. cranking)
• Auxiliary 5.0 or 3.3 V SPI configurable regulator, for additional ICs,
with over-current detection and under-voltage protection
• MUX output pin for device internal analog signal monitoring and
power supply monitoring
• Advanced SPI, MCU, ECU power supply, and critical pins
diagnostics and monitoring.
• Multiple wake-up sources in LP modes: CAN or LIN bus,
I/O transition, automatic timer, SPI message, and VDD over-current
detection.
• ISO11898-5 high-speed CAN interface compatibility for baud rates of
40 kb/s to 1.0 Mb/s
• Scalable product family of devices ranging from 0 to 2 LINs which are
compatible to J2602-2 and LIN 2.1
Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2010 - 2012. All rights reserved.
TABLE OF CONTENTS
TABLE OF CONTENTS
Simplified Application Diagrams ................................................................................................................. 3
Device Variations ....................................................................................................................................... 7
Internal Block Diagrams ............................................................................................................................. 9
Pin Connections ....................................................................................................................................... 11
Electrical Characteristics .......................................................................................................................... 17
Maximum Ratings .................................................................................................................................. 17
Static Electrical Characteristics ............................................................................................................. 19
Dynamic Electrical Characteristics ........................................................................................................ 27
Timing Diagrams ................................................................................................................................... 30
Functional Description .............................................................................................................................. 35
Introduction ............................................................................................................................................ 35
Functional Pin Description ..................................................................................................................... 35
Functional Device Operation .................................................................................................................... 39
Mode and State Description .................................................................................................................. 39
LP Modes .............................................................................................................................................. 40
State Diagram ........................................................................................................................................ 41
Mode Change ........................................................................................................................................ 42
Watchdog Operation .............................................................................................................................. 42
Functional Block Operation Versus Mode ............................................................................................. 44
Illustration of Device Mode Transitions. ................................................................................................. 45
Cyclic Sense Operation During LP Modes ............................................................................................ 47
Behavior at Power Up and Power Down ............................................................................................... 49
Fail-safe Operation ................................................................................................................................... 51
CAN Interface ........................................................................................................................................ 55
CAN Interface Description ..................................................................................................................... 55
CAN Bus Fault Diagnostic ..................................................................................................................... 58
LIN Block .................................................................................................................................................. 61
LIN Interface Description ....................................................................................................................... 61
LIN Operational Modes .......................................................................................................................... 61
Serial Peripheral Interface ........................................................................................................................ 63
High Level Overview .............................................................................................................................. 63
Detail Operation ..................................................................................................................................... 64
Detail of Control Bits And Register Mapping ......................................................................................... 67
Flags and Device Status ........................................................................................................................ 84
Typical Applications ................................................................................................................................. 91
Packaging ................................................................................................................................................ 99
33903/4/5
Analog Integrated Circuit Device Data
2
Freescale Semiconductor
SIMPLIFIED APPLICATION DIAGRAMS
SIMPLIFIED APPLICATION DIAGRAMS
* = Optional
33905D
VBAT
(5.0 V/3.3 V)
D1
Q2
Q1*
VSUP1
VE VB
VAUX
V
VBAUX
VCAUX
VDD
DD
VSUP2
RST
INT
SAFE
DBG
GND
MOSI
SCLK
MISO
VSENSE
SPI
MCU
I/O-0
CS
A/D
MUX-OUT
I/O-1
5V-CAN
TXD
CANH
SPLIT
RXD
TXD-L1
RXD-L1
TXD-L2
RXD-L2
CAN Bus
CANL
LIN-TERM 1
LIN Bus
LIN Bus
LIN-1
LIN-TERM 2
LIN-2
Figure 1. 33905D Simplified Application Diagram
* = Optional
33905S
VBAT
(5.0 V/3.3 V)
D1
Q2
Q1*
VCAUX VAUX
VSUP1 VE VB
VBAUX
VDD
VDD
VSUP2
RST
INT
SAFE
DBG
GND
MOSI
SCLK
MISO
VSENSE
SPI
MCU
I/O-0
CS
A/D
MUX-OUT
I/O-1
5V-CAN
TXD
CANH
SPLIT
RXD
TXD-L
RXD-L
CAN Bus
LIN Bus
CANL
LIN-T
VBAT
LIN
I/O-3
Figure 2. 33905S Simplified Application Diagram
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
SIMPLIFIED APPLICATION DIAGRAMS
33904
VBAT
* = Optional
(5.0 V/3.3 V)
Q1*
D1
Q2
VCAUX VAUX
VSUP1 VE VB
V
BAUX
SUP2
VDD
VDD
V
RST
INT
SAFE
DBG
GND
MOSI
SCLK
MISO
VSENSE
SPI
MCU
I/O-0
CS
A/D
MUX-OUT
5V-CAN
I/O-1
CANH
TXD
SPLIT
CANL
VBAT
RXD
CAN Bus
I/O-2
I/O-3
Figure 3. 33904 Simplified Application Diagram
33903
VBAT
D1
VDD
VDD
VSUP1 VSUP2
DBG
RST
INT
SAFE
GND
MOSI
SCLK
MISO
CS
SPI
MCU
I/O-0
5V-CAN
CANH
SPLIT
CANL
TXD
CAN Bus
RXD
Figure 4. 33903 Simplified Application Diagram
33903/4/5
Analog Integrated Circuit Device Data
4
Freescale Semiconductor
SIMPLIFIED APPLICATION DIAGRAMS
33903D
VBAT
D1
* = Optional
VDD
Q1*
VSUP
VE VB
VDD
RST
INT
SAFE
DBG
GND
MOSI
SCLK
MISO
VSENSE
SPI
MCU
IO-0
CS
A/D
MUX-OUT
CANH
SPLIT
5V-CAN
TXD
CANL
RXD
TXD-L1
RXD-L1
TXD-L2
RXD-L2
LIN-T1/I/O-2
CAN Bus
LIN Bus
LIN-1
LIN-T2/IO-3
LIN Bus
LIN-2
Figure 5. 33903D Simplified Application Diagram
33903S
VBAT
D1
* = Optional
VDD
Q1*
VSUP
VE VB
VDD
RST
INT
SAFE
DBG
GND
MOSI
SCLK
MISO
VSENSE
SPI
MCU
IO-0
CS
A/D
MUX-OUT
CANH
SPLIT
5V-CAN
TXD
CANL
RXD
TXD-L1
RXD-L1
LIN-T1/I/O-2
VBAT
CAN Bus
LIN Bus
LIN-1
I/O-3
Figure 6. 33903S Simplified Application Diagram
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
SIMPLIFIED APPLICATION DIAGRAMS
33903P
VBAT
D1
* = Optional
VDD
Q1*
VSUP
VE VB
VDD
RST
INT
SAFE
DBG
GND
MOSI
SCLK
MISO
VSENSE
SPI
MCU
IO-0
CS
A/D
MUX-OUT
5V-CAN
CANH
SPLIT
CANL
CAN Bus
VBAT
TXD
RXD
VBAT
I/O-2
I/O-3
Figure 7. 33903P Simplified Application Diagram
33903/4/5
Analog Integrated Circuit Device Data
6
Freescale Semiconductor
DEVICE VARIATIONS
DEVICE VARIATIONS
Table 1. MC33905 Device Variations - (All devices rated at TA = -40 TO 125 °C)
Version
(1), (2)
VDD Output
Voltage
LIN
Interface(s)
Wake-up Input / LIN Master
Termination
VAUX VSENSE
Freescale Part Number
Package
MUX
MC33905D (Dual LIN)
MCZ33905BD3EK/R2
MCZ33905CD3EK/R2
MCZ33905D5EK/R2
MCZ33905BD5EK/R2
MCZ33905CD5EK/R2
MC33905S (Single LIN)
MCZ33905BS3EK/R2
MCZ33905CS3EK/R2
MCZ33905S5EK/R2
MCZ33905BS5EK/R2
MCZ33905CS5EK/R2
Notes
B
C
3.3 V
5.0 V
2 Wake-up + 2 LIN terms
or
SOIC 54 pin
exposed pad
3 Wake-up + 1 LIN terms
or
4 Wake-up + no LIN terms
Yes
Yes
Yes
2
B
C
B
C
3.3 V
5.0 V
3 Wake-up + 1 LIN terms
Yes
Yes
Yes
1
or
4 Wake-up + no LIN terms
B
C
1. Design changes in the “B” version resolved V
slow ramp up issues, enhanced device current consumption and improved oscillator
SUP
stability. “B” version has an errata linked to the SPI operation.
2. “C” versions are recommended for new designs. Design changes in the “C” version resolve the SPI deviation of all prior versions, and
does not have the RxD short to ground detection feature.
Table 2. MC33904 Device Variations - (All devices rated at TA = -40 TO 125 °C)
Version
(3), (4)
VDD Output
Voltage
LIN
Interface(s)
Wake-up Input / LIN Master
Termination
VAUX VSENSE
Freescale Part Number
Package
MUX
MC33904
MCZ33904B3EK/R2
MCZ33904C3EK/R2
MCZ33904A5EK/R2
MCZ33904B5EK/R2
MCZ33904C5EK/R2
Notes
B
C
A
B
C
3.3 V
5.0 V
SOIC 32 pin
exposed pad
4 Wake-up
Yes
Yes
Yes
0
3. Design changes in the “B” version resolved V
slow ramp up issues, enhanced device current consumption and improved oscillator
SUP
stability. “B” version has an errata linked to the SPI operation.
4. “C” versions are recommended for new designs. Design changes in the “C” version resolve the SPI deviation of all prior versions, and
does not have the RxD short to ground detection feature.
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
DEVICE VARIATIONS
Table 3. MC33903 Device Variations - (All devices rated at TA = -40 TO 125 °C)
Version
(6), (7)
VDD Output
Voltage
LIN
Interface(s)
Wake-up Input / LIN Master
Termination
VAUX VSENSE
Freescale Part Number
Package
MUX
MC33903
MCZ33903B3EK/R2
MCZ33903C3EK/R2
MCZ33903B5EK/R2
MCZ33903C5EK/R2
MC33903D (Dual LIN)
MCZ33903BD3EK/R2
MCZ33903CD3EK/R2
MCZ33903BD5EK/R2
MCZ33903CD5EK/R2
MC33903S (Single LIN)
MCZ33903BS3EK/R2
MCZ33903CS3EK/R2
MCZ33903BS5EK/R2
MCZ33903CS5EK/R2
MC33903P
B
C
B
C
3.3 V(5)
5.0 V(5)
SOIC 32 pin
exposed pad
1 Wake-up
No
No
No
No
0
2
B
C
B
C
1 Wake-up + 2 LIN terms
3.3 V
5.0 V
or
SOIC 32 pin
exposed pad
2 Wake-up + 1 LIN terms
or
3 Wake-up + no LIN terms
Yes
Yes
B
C
B
C
3.3 V
5.0 V
2 Wake-up + 1 LIN terms
or
3 Wake-up + no LIN terms
SOIC 32 pin
exposed pad
No
No
Yes
Yes
Yes
Yes
1
0
MCZ33903CP5EK/R2
MCZ33903CP3EK/R2
Notes
5.0 V
3.3 V
SOIC 32 pin
exposed pad
3 Wake-up
C
5. VDD does not allow usage of an external PNP on the 33903. Output current limited to 100 mA.
6. Design changes in the “B” version resolved V slow ramp up issues, enhanced device current consumption and improved oscillator
SUP
stability. “B” version has an errata linked to the SPI operation.
7. “C” versions are recommended for new designs. Design changes in the “C” version resolve the SPI deviation of all prior versions, and
does not have the RxD short to ground detection feature.
33903/4/5
Analog Integrated Circuit Device Data
8
Freescale Semiconductor
INTERNAL BLOCK DIAGRAMS
INTERNAL BLOCK DIAGRAMS
VBAUX VCAUX
VSUP1
VBAUX VCAUX
VSUP1
VAUX
VE
VB
VAUX
VE
VB
5 V Auxiliary
Regulator
5 V Auxiliary
Regulator
VSUP2
SAFE
VDD
VSUP2
SAFE
VDD
VDD Regulator
VDD Regulator
V
S2-INT
V
S2-INT
RST
INT
RST
INT
Fail-safe
Fail-safe
Power Management
State Machine
Power Management
State Machine
DBG
GND
DBG
GND
MOSI
SCLK
MOSI
SCLK
Oscillator
Oscillator
SPI
SPI
MISO
CS
MISO
CS
VSENSE
VSENSE
Analog Monitoring
Analog Monitoring
Signals Condition & Analog MUX
MUX-OUT
5 V-CAN
Signals Condition & Analog MUX
MUX-OUT
5 V-CAN
V
V
S2-INT
S2-INT
I/O-0
I/O-1
I/O-3
I/O-0
I/O-1
Configurable
5 V-CAN
Input-Output
Regulator
5 V-CAN
Configurable
Regulator
Input-Output
CANH
SPLIT
CANL
CANH
SPLIT
CANL
Enhanced High Speed CAN
Physical Interface
TXD
Enhanced High Speed CAN
Physical Interface
TXD
RXD
RXD
V
V
S2-INT
S2-INT
TXD-L1
RXD-L1
TXD-L
RXD-L
LIN Term #1
LIN Term #1
LIN-T1
LIN1
LIN 2.1 Interface - #1
LIN 2.1 Interface - #2
LIN-T
LIN
LIN 2.1 Interface - #1
V
S2-INT
TXD-L2
RXD-L2
33905S
LIN Term #2
LIN-T2
LIN2
33905D
Figure 8. 33905 Internal Block Diagram
VBAUX VCAUX
VSUP1
VAUX
VE
VB
5 V Auxiliary
Regulator
VDD
VDD Regulator
VSUP2
SAFE
V
S2-INT
RST
INT
Fail-safe
Power Management
State Machine
DBG
GND
MOSI
SCLK
Oscillator
SPI
MISO
CS
VSENSE
Analog Monitoring
Signals Condition & Analog MUX
MUX-OUT
5 V-CAN
V
I/O-0
I/O-1
I/O-2
I/O-3
S2-INT
Configurable
Input-Output
5 V-CAN
Regulator
CANH
SPLIT
CANL
Enhanced High Speed CAN
Physical Interface
TXD
RXD
Figure 9. 33904 Internal Block Diagram
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
INTERNAL BLOCK DIAGRAMS
VSUP
VE
VB
VSUP1
VDD Regulator
VDD
VSUP2
SAFE
VDD
VDD Regulator
V
S-INT
V
RST
INT
S2-INT
RST
INT
SAFE
Fail-safe
Power Management
State Machine
MOSI
SCLK
Power Management
State Machine
DBG
GND
MOSI
SCLK
DBG
GND
SPI
MISO
CS
Oscillator
SPI
Oscillator
MISO
CS
V
VSENSE
S2-INT
Analog Monitoring
Signals Condition & Analog MUX
Configurable
Input-Output
5 V-CAN
5 V-CAN
I/O-0
Regulator
MUX-OUT
5 V-CAN
CANH
SPLIT
CANL
V
S-INT
Enhanced High Speed CAN
Physical Interface
TXD
I/O-0
I/O-2
5 V-CAN
Regulator
Configurable
Input-Output
RXD
I/O-3
33903
CANH
SPLIT
CANL
Enhanced High Speed CAN
Physical Interface
TXD
RXD
VSUP
VE
VB
33903P
VDD
VSUP
VE
VDD Regulator
Fail-safe
VB
V
S-INT
RST
INT
SAFE
VDD
VDD Regulator
V
S-INT
Power Management
State Machine
DBG
GND
MOSI
SCLK
RST
INT
SAFE
Oscillator
SPI
Fail-safe
MISO
CS
Power Management
State Machine
DBG
GND
VSENSE
MOSI
SCLK
Analog Monitoring
Signals Condition & Analog MUX
Oscillator
SPI
MISO
CS
MUX-OUT
5 V-CAN
VSENSE
Analog Monitoring
Signals Condition & Analog MUX
V
S-INT
Configurable
Input-Output
5 V-CAN
Regulator
IO-0
MUX-OUT
5 V-CAN
V
S-INT
CANH
SPLIT
CANL
I/O-0
I/O-3
Enhanced High-speed CAN
Physical Interface
TXD
5 V-CAN
Regulator
Configurable
Input-Output
RXD
V
S-INT
CANH
SPLIT
CANL
TXD-L1
RXD-L1
Enhanced High Speed CAN
Physical Interface
TXD
LIN Term #1
LIN Term #2
LIN-T1
LIN1
LIN 2.1 Interface - #1
LIN 2.1 Interface - #2
RXD
V
S-INT
V
S-INT
TXD-L2
RXD-L2
TXD-L
LIN-T2
LIN2
LIN Term #1
LIN-T
LIN
LIN 2.1 Interface - #1
RXD-L
33903D
33903S
Figure 10. 33903 Internal Block Diagram
33903/4/5
Analog Integrated Circuit Device Data
10
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
MC33905D
MC33905S
1
54
1
32
NC
NC
NC
NC
NC
VB
VE
VSUP1
2
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
2
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSUP2
I/O-3
LIN-T/I/O-2
3
3
RXD
TXD
VDD
MISO
NC
VB
VE
4
4
VSUP1
5
5
SAFE
5V-CAN
CANH
VSUP2
LIN-T2/I/O-3
LIN-T1/I/O-2
6
6
RXD
7
7
TXD
VDD
MISO
MOSI
SCLK
CS
MOSI
SCLK
CS
INT
RST
8
CANL
8
SAFE
5V-CAN
CANH
GROUND
9
9
GND CAN
SPLIT
V-BAUX
V-CAUX
10
11
12
13
14
15
16
17
18
19
20
21
22
10
11
12
13
14
15
16
CANL
GND CAN
SPLIT
V-BAUX
V-CAUX
I/O-1
V-AUX
MUX-OUT
I/O-0
INT
VSENSE
RXD-L
TXD-L
LIN
GROUND
RST
I/O-1
DBG
V-AUX
MUX-OUT
VSENSE
RXD-L1
TXD-L1
LIN-1
NC
38
37
GND - LEAD FRAME
32 pin exposed package
I/O-0
DBG
NC
36
35
34
NC
NC
NC
NC
33
32
31
30
29
28
NC
TXD-L2
GND
RXD-L2
LIN-2
NC
23
24
GND
25
26
27
NC
NC
NC
GND - LEAD FRAME
54 pin exposed package
MC33904
MC33903
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VB
VE
VSUP1
VSUP1
VSUP2
NC
NC
NC
RXD
TXD
VDD
MISO
2
2
VSUP2
I/O-3
I/O-2
SAFE
5V-CAN
CANH
3
3
RXD
TXD
VDD
MISO
4
4
NC
5
5
SAFE
5V-CAN
CANH
6
6
7
7
MOSI
SCLK
CS
INT
RST
MOSI
SCLK
CS
INT
RST
NC
CANL
8
CANL
8
GROUND
GROUND
9
9
GND CAN
SPLIT
V-BAUX
V-CAUX
GND CAN
SPLIT
10
11
12
13
14
15
16
10
11
12
13
14
15
16
NC
NC
NC
NC
I/O-0
DBG
I/O-1
V-AUX
MUX-OUT
I/O-0
NC
VSENSE
NC
NC
NC
NC
NC
DBG
NC
GND - LEAD FRAME
32 pin exposed package
GND - LEAD FRAME
32 pin exposed package
Note: MC33905D, MC33905S, MC33904 and MC33903 are footprint compatible,
Figure 11. 33905D, MC33905S, MC33904 and MC33903 Pin Connections
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
PIN CONNECTIONS
MC33903D
MC33903S
VE
VE
1
32
1
32
VB
VSUP
VB
VSUP
2
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
2
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
RXD
TXD
VDD
MISO
RXD
TXD
VDD
MISO
3
3
LIN-T2 / I/O-3
LIN-T1 / I/O-2
I/O-3
LIN-T / I/O-2
4
4
5
5
SAFE
5V-CAN
CANH
SAFE
5V-CAN
CANH
6
6
MOSI
SCLK
CS
INT
RST
VSENSE
RXD-L1
TXD-L1
LIN1
MOSI
SCLK
CS
INT
RST
VSENSE
RXD-L
TXD-L
LIN
7
7
CANL
8
CANL
8
GROUND
GROUND
9
9
GND CAN
SPLIT
GND CAN
SPLIT
10
11
12
13
14
15
16
10
11
12
13
14
15
16
MUX-OUT
IO-0
MUX-OUT
I/O-0
DBG
NC
DBG
TXD-L2
GND
GND
GND
GND
NC
LIN2
NC
RXD-L2
GND - LEAD FRAME
32 pin exposed package
GND - LEAD FRAME
32 pin exposed package
MC33903P
VE
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VB
VSUP
I/O-3
2
RXD
TXD
VDD
MISO
3
4
I/O-2
5
SAFE
5V-CAN
CANH
6
MOSI
SCLK
CS
INT
RST
7
CANL
8
GROUND
9
GND CAN
SPLIT
10
11
12
13
14
15
16
VSENSE
N/C
MUX-OUT
I/O-0
DBG
NC
N/C
N/C
GND
NC
GND
NC
GND - LEAD FRAME
32 pin exposed package
Note: MC33903D, MC33903S, and MC33903P are footprint compatible.
Figure 12. 33905D, MC33905S, MC33904 and MC33903 Pin Connections
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
12
PIN DEFINITIONS
PIN DEFINITIONS
Table 4. 33903/4/5 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 35.
54 Pin 32 Pin 32 Pin 32 Pin 32 Pin 32 Pin 32 Pin
33905D 33905S 33904 33903 33903D 33903S 33903P
Pin
Function
Formal
Name
Pin Name
Definition
Connect to GND.
1-3, 20-
22, 27-
30, 32-
35, 52-
54
N/A
17, 18, 3-4,11-
N/A
N/A
N/A
N/C
No
Connect
-
19
14, 17-
21, 31,
32
Do NOT connect the N/C pins to
GND. Leave these pins Open.
N/A
N/A
1
N/A
1
N/A
1
N/A
2
14, 16, 14, 16,
N/C
No
Connect
17
17, 19-
21
Supply input for the device internal
supplies, power on reset circuitry and
the VDD regulator. VSUP and VSUP1
supplies are internally connected on
part number MC33903BDEK and
MC33903BSEK
4
2
2
VSUP/1
Power
Battery
Voltage
Supply 1
Supply input for 5 V-CAN regulator,
5
6
2
3
2
3
2
N/A
N/A
N/A
VSUP2
Power
Battery
Voltage
Supply 2
V
AUX regulator, I/O and LIN pins.
VSUP1 and VSUP2 supplies are
internally connected on part number
MC33903BDEK and MC33903BSEK
33903D and 33905D - Output pin for
the LIN2 master node termination
resistor.
N/A
3
3
3
LIN-T2
or
Output
or
LIN
Termination 2
or
I/O-3
Input/
Output
or
Input/Output
3
33903P, 33903S, 33903D, 33904,
33905S and 33905D - Configurable
pin as an input or HS output, for
connection to external circuitry
(switched or small load). The input
can be used as a programmable
Wake-up input in (LP) mode. When
used as a HS, no over-temperature
protection is implemented. A basic
short to GND protection function,
based on switch drain-source over-
voltage detection, is available.
33905D - Output pin for the LIN1
master node termination resistor.
7
4
4
N/A
4
4
4
LIN-T1
or
Output
or
LIN
Termination
or
1
33903P, 33903S, 33903D, 33904,
33905S and 33905D - Configurable
pin as an input or HS output, for
connection to external circuitry
(switched or small load). The input
can be used as a programmable
Wake-up input in (LP) mode. When
used as a HS, no over-temperature
protection is implemented. A basic
short to GND protection function,
based on switch drain-source over-
voltage detection, is available.
LIN-T
Input/
Output
or
Input/Output
2
or
I/O-2
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
PIN DEFINITIONS
Table 4. 33903/4/5 Pin Definitions (continued)
A functional description of each pin can be found in the Functional Pin Description section beginning on page 35.
54 Pin 32 Pin 32 Pin 32 Pin 32 Pin 32 Pin 32 Pin
33905D 33905S 33904 33903 33903D 33903S 33903P
Pin
Function
Formal
Name
Pin Name
Definition
Output of the safe circuitry. The pin is
asserted LOW if a fault event occurs
(e.g.: software watchdog is not
triggered, VDD low, issue on the RST
pin, etc.). Open drain structure.
8
9
5
6
5
6
5
6
5
6
5
6
5
SAFE
Output
Safe Output
(Active LOW)
Output voltage for the embedded
CAN interface. A capacitor must be
connected to this pin.
6
5 V-CAN
Output
5V-CAN
CAN high output.
CAN low output.
10
11
12
7
8
9
7
8
9
7
8
9
7
8
9
7
8
9
7
8
9
CANH
CANL
Output
Output
CAN High
CAN Low
GND-CAN
Power GND of the embedded CAN
interface
GND-CAN Ground
Output pin for connection to the
middle point of the split CAN
termination
13
10
10
10
10
10
10
SPLIT
Output SPLIT Output
Output pin for external path PNP
transistor base
14
15
16
17
11
12
13
14
11
12
13
14
N/A
N/A
N/A
N/A
N/A
N/A
N/A
11
N/A
N/A
N/A
11
N/A
N/A
N/A
11
VBAUX
VCAUX
VAUX
Output
Output
Output
Output
VB Auxiliary
Output pin for external path PNP
transistor collector
VCOLLECT
OR Auxiliary
Output pin for the auxiliary voltage.
VOUT
Auxiliary
Multiplexed output to be connected to
an MCU A/D input. Selection of the
analog parameter available at MUX-
OUT is done via the SPI. A
MUX-OUT
Multiplex
Output
switchable internal pull-down resistor
is integrated for VDD current sense
measurements.
Configurable pin as an input or
output, for connection to external
circuitry (switched or small load). The
voltage level can be read by the SPI
and via the MUX output pin. The
input can be used as a
18
15
15
15
12
12
12
I/O-0
Input/
Output
Input/Output
0
programmable Wake-up input in LP
mode. In LP, when used as an
output, the High Side (HS) or Low
Side (LS) can be activated for a cyclic
sense function.
Input to activate the Debug mode. In
Debug mode, no watchdog refresh is
necessary. Outside of Debug mode,
connection of a resistor between
DBG and GND allows the selection of
Safe mode functionality.
19
23
16
16
16
13
14
13
13
DBG
Input
Input
Debug
LIN bus transmit data input. Includes
an internal pull-up resistor to VDD.
N/A
N/A
N/A
N/A
N/A
TXD-L2
LIN Transmit
Data 2
Ground of the IC.
24,31
25
N/A
N/A
N/A
N/A
N/A
N/A
15, 18 15, 18 15, 18
16 N/A N/A
GND
Ground
Output
Ground
LIN bus receive data output.
RXD-L2
LIN Receive
Data
33903/4/5
Analog Integrated Circuit Device Data
14
Freescale Semiconductor
PIN DEFINITIONS
Table 4. 33903/4/5 Pin Definitions (continued)
A functional description of each pin can be found in the Functional Pin Description section beginning on page 35.
54 Pin 32 Pin 32 Pin 32 Pin 32 Pin 32 Pin 32 Pin
33905D 33905S 33904 33903 33903D 33903S 33903P
Pin
Function
Formal
Name
Pin Name
Definition
LIN bus input output connected to the
LIN bus.
26
36
N/A
17
N/A
N/A
N/A
N/A
17
19
N/A
19
N/A
N/A
LIN2
Input/
Output
LIN bus
LIN bus
LIN bus input output connected to the
LIN bus.
33903D/5D
LIN-1
Input/
Output
33903S/5S
LIN
LIN bus transmit data input. Includes
an internal pull-up resistor to VDD.
37
38
39
40
18
19
20
21
N/A
N/A
20
N/A
N/A
N/A
N/A
20
21
20
21
N/A
N/A
22
33903D/5D
TXD-L11
33903S/5S
TXD-L
Input
Output
Input
LIN Transmit
Data
LIN bus receive data output.
33903D/5D
RXD-L1
33903S/5S
RXD-L
LIN Receive
Data
Direct battery voltage input sense. A
serial resistor is required to limit the
input current during high voltage
transients.
22
22
VSENSE
Sense input
Configurable pin as an input or
output, for connection to external
circuitry (switched or small load). The
voltage level can be read by the SPI
and the MUX output pin. The input
can be used as a programmable
Wake-up input in (LP) mode. It can
be used in association with
21
N/A
N/A
N/A
I/O-1
Input/
Output
Input Output
1
I/O-0 for a cyclic sense function in
(LP) mode.
This is the device reset output whose
main function is to reset the MCU.
This pin has an internal pull-up to
VDD. The reset input voltage is also
monitored in order to detect external
reset and safe conditions.
41
22
22
22
23
23
23
RST
Output Reset Output
(Active LOW)
This output is asserted low when an
enabled interrupt condition occurs.
This pin is an open drain structure
with an internal pull up resistor to
VDD.
42
43
23
24
23
24
23
24
24
25
24
25
24
25
INT
CS
Output
Input
Interrupt
Output
(Active LOW)
Chip select pin for the SPI. When the
CS is low, the device is selected. In
(LP) mode with VDD ON, a transition
on CS is a Wake-up condition
Chip Select
(Active LOW)
Clock input for the Serial Peripheral
Interface (SPI) of the device
44
45
46
25
26
27
25
26
27
25
26
27
26
27
28
26
27
28
26
27
28
SCLK
MOSI
MISO
Input
Input
Serial Data
Clock
SPI data received by the device
Master Out/
Slave In
SPI data sent to the MCU. When the
CS is high, MISO is high-impedance
Output
Master In/
Slave Out
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
PIN DEFINITIONS
Table 4. 33903/4/5 Pin Definitions (continued)
A functional description of each pin can be found in the Functional Pin Description section beginning on page 35.
54 Pin 32 Pin 32 Pin 32 Pin 32 Pin 32 Pin 32 Pin
33905D 33905S 33904 33903 33903D 33903S 33903P
Pin
Function
Formal
Name
Pin Name
Definition
5.0 or 3.3 V output pin of the main
regulator for the Microcontroller
supply.
47
28
28
28
29
29
29
VDD
Output
Input
Voltage
Digital Drain
CAN bus transmit data input. Internal
pull-up to VDD
48
29
29
29
30
30
30
TXD
Transmit
Data
CAN bus receive data output
49
50
30
31
30
31
30
31
32
31
32
31
32
RXD
VE
Output Receive Data
Connection to the external PNP path
transistor. This is an intermediate
current supply source for the VDD
regulator
N/A
Voltage
Emitter
Base output pin for connection to the
external PNP pass transistor
51
32
32
N/A
1
1
1
VB
Output Voltage Base
Ground
EX PAD EX PAD EX PAD EX PAD EX PAD EX PAD EX PAD
GND
Ground
Ground
33903/4/5
Analog Integrated Circuit Device Data
16
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 5. Maximum Ratings
All voltages are referenced to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent
damage to the device.
Ratings
Symbol
Value
Unit
ELECTRICAL RATINGS(8)
Supply Voltage at VSUP/1 and VSUP2
Normal Operation (DC)
V
V
-0.3 to 28
-0.3 to 40
SUP1/2
Transient Conditions (Load Dump)
V
SUP1/2TR
DC voltage on LIN/1 and LIN2
Normal Operation (DC)
V
V
V
V
VBUSLIN
-28 to 28
-28 to 40
Transient Conditions (Load Dump)
VBUSLINTR
DC voltage on CANL, CANH, SPLIT
Normal Operation (DC)
VBUS
-28 to 28
-32 to 40
Transient Conditions (Load Dump)
VBUSTR
DC Voltage at SAFE
Normal Operation (DC)
VSAFE
-0.3 to 28
-0.3 to 40
Transient Conditions (Load Dump)
VSAFETR
DC Voltage at I/O-0, I/O-1, I/O-2, I/O-3 (LIN-T Pins)
Normal Operation (DC)
VI/O
-0.3 to 28
-0.3 to 40
Transient Conditions (Load Dump)
VI/OTR
DC voltage on TXD-L, TXD-L1 TXD-L2, RXD-L, RXD-L1, RXD-L2
DC voltage on TXD, RXD(10)
DC Voltage at INT
VDIGLIN
VDIG
-0.3 to VDD +0.3
-0.3 to VDD +0.3
-0.3 to 10
V
V
VINT
V
DC Voltage at RST
VRST
VRST
VMUX
VDBG
ILH
-0.3 to VDD +0.3
-0.3 to VDD +0.3
-0.3 to VDD +0.3
-0.3 to 10
V
DC Voltage at MOSI, MSIO, SCLK and CS
DC Voltage at MUX-OUT
V
V
DC Voltage at DBG
V
Continuous current on CANH and CANL
DC voltage at VDD, 5V-CAN, VAUX, VCAUX
DC voltage at VBASE(9) and VBAUX
DC voltage at VE(10)
200
mA
V
VREG
VREG
VE
-0.3 to 5.5
-0.3 to 40
V
-0.3 to 40
V
DC voltage at VSENSE
VSENSE
-28 to 40
V
Notes
8. The voltage on non-VSUP pins should never exceed the VSUP voltage at any time or permanent damage to the device may occur.
9. If the voltage delta between VSUP/1/2 and VBASE is greater than 6.0 V, the external V
damaged.
ballast current sharing functionality may be
DD
10. Potential Electrical Over Stress (EOS) damage may occur if RXD is in contact with VE while the device is ON.
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 5. Maximum Ratings (continued)
All voltages are referenced to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent
damage to the device.
Ratings
Symbol
Value
Unit
ESD Capability
AECQ100(11)
V
Human Body Model - JESD22/A114 (C
= 100 pF, R
= 1500 )
ZAP
ZAP
V
V
8000
2000
ESD1-1
ESD1-2
CANH and CANL. LIN1 and LIN2, Pins versus all GND pins
all other Pins including CANH and CANL
Charge Device Model - JESD22/C101 (C
= 4.0 pF
ZAP
V
V
750
500
ESD2-1
ESD2-2
Corner Pins (Pins 1, 16, 17, and 32)
All other Pins (Pins 2-15, 18-31)
Tested per IEC 61000-4-2 (C
= 150 pF, R
ZAP
= 330 )
ZAP
V
V
V
15000
15000
15000
ESD3-1
ESD3-2
ESD3-3
Device unpowered, CANH and CANL pin without capacitor, versus GND
Device unpowered, LIN, LIN1 and LIN2 pin, versus GND
Device unpowered, VS1/VS2 (100 nF to GND), versus GND
Tested per specific OEM EMC requirements for CAN and LIN with
additional capacitor on VSUP/1/2 pins (See Typical Applications on page
91)
CANH, CANL without bus filter
LIN, LIN1 and LIN2 with and without bus filter
I/O with external components (22 k - 10 nF)
V
V
V
9000
12000
7000
ESD4-1
ESD4-2
ESD4-3
THERMAL RATINGS
Junction temperature
TJ
TA
150
°C
°C
°C
Ambient temperature
-40 to 125
-50 to 150
Storage temperature
TST
THERMAL RESISTANCE
Thermal resistance junction to ambient(14)
Peak package reflow temperature during reflow(12), (13)
Notes
RJA
50(14)
°C/W
°C
TPPRT
Note 13
11. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100pF, RZAP = 1500 ), the Charge Device Model
(CDM), and Robotic (CZAP = 4.0 pF).
12. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
13. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
14. This parameter was measured according to Figure 13:
PCB 100mm x 100mm
Top side, 300 sq. mm
(20mmx15mm)
Bottom view
Bottom side
20mm x 40mm
Figure 13. PCB with Top and Bottom Layer Dissipation Area (Dual Layer)
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
18
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 6. Static Electrical Characteristics
Characteristics noted under conditions 5.5 V VSUP 28 V, -40 C TA 125 C, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUT
Nominal DC Voltage Range(15)
Extended DC Low Voltage Range(16)
VSUP1/VSUP2
VSUP1/VSUP2
VS1_LOW
5.5
4.0
-
-
28
V
V
V
5.5
Under-voltage Detector Thresholds, at the VSUP/1 pin,
Low threshold (VSUP/1 ramp down)
High threshold (VSUP/1 ramp up)
Hysteresis
5.5
-
0.22
6.0
-
0.35
6.5
6.6
0.5
Note: function not active in LP mode
Under-voltage Detector Thresholds, at the VSUP2 pin:
VS2_LOW
V
V
Low threshold (VSUP2 ramp down)
High threshold (VSUP2 ramp up)
Hysteresis
5.5
-
0.22
6.0
-
0.35
6.5
6.6
0.5
Note: function not active in LP modes
VSUP Over-voltage Detector Thresholds, at the VSUP/1 pin:
Not active in LP modes
VS_HIGH
16.5
17
18.5
Battery loss detection threshold, at the VSUP/1 pin.
VSUP/1 to turn VDD ON, VSUP/1 rising
BATFAIL
VSUP-TH1
VSUP-TH1HYST
ISUP1
2.0
-
2.8
4.1
180
4.0
4.5
V
V
VSUP/1 to turn VDD ON, hysteresis (Guaranteed by design)
150
mV
mA
(18)
Supply current(17)
,
-
-
- from VSUP/1
- from VSUP2, (5V-CAN VAUX, I/O OFF)
2.0
0.05
4.0
0.85
Supply current, ISUP1 + ISUP2, Normal mode, VDD ON
ISUP1+2
mA
- 5 V-CAN OFF, VAUX OFF
- 5 V-CAN ON, CAN interface in Sleep mode, VAUX OFF
- 5 V-CAN OFF, Vaux ON
- 5 V-CAN ON, CAN interface in TXD/RXD mode, VAUX OFF, I/O-x disabled
-
-
-
-
2.8
4.5
5.0
5.5
8.0
-
-
-
LP mode VDD OFF. Wake-up from CAN, I/O-x inputs
ILPM_OFF
A
A
VSUP 18 V, -40 to 25 °C
VSUP 18 V, 125 °C
-
-
15
-
35
50
LP mode VDD ON (5.0 V) with VDD under-voltage and VDD
over-current monitoring, Wake-up from CAN, I/O-x inputs
ILPM_ON
-
-
VSUP 18 V, -40 to 25 °C, IDD = 1.0 A
VSUP 18 V, -40 to 25 °C, IDD = 100 A
VSUP 18 V, 125 °C, IDD = 100 A
20
40
-
-
65
85
LP mode, additional current for oscillator (used for: cyclic sense, forced Wake-
up, and in LP V ON mode cyclic interruption and watchdog)
IOSC
A
DD
VSUP 18 V, -40 to 125 °C
-
5.0
-
9.0
10
Debug mode DBG voltage range
VDBG
8.0
V
Notes
15. All parameters in spec (ex: VDD regulator tolerance).
16. Device functional, some parameters could be out of spec. VDD is active, device is not in Reset mode if the lowest VDD under-voltage
reset threshold is selected (approx. 3.4 V). CAN and I/Os are not operational.
17. In Run mode, CAN interface in Sleep mode, 5 V-CAN and VAUX turned OFF. IOUT at VDD < 50 mA. Ballast: turned OFF or not connected.
18. VSUP1 and VSUP2 supplies are internally connected on part number MC33903BDEK and MC33903BSEK. Therefore, I
cannot be measured individually.
and I
SUP2
SUP1
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 6. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V VSUP 28 V, -40 C TA 125 C, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
VDD VOLTAGE REGULATOR, VDD PIN
Symbol
Min
Typ
Max
Unit
Output Voltage
V
VDD 5.0 V, VSUP 5.5 to 28 V, IOUT 0 to 150 mA
VDD 3.3 V, VSUP 5.5 to 28 V, IOUT 0 to 150 mA
VOUT-5.0
VOUT-3.3
4.9
5.0
3.3
5.1
3.4
3.234
Drop voltage without external PNP pass transistor(19)
VDD 5.0 V, IOUT 100 mA
VDROP
mV
-
-
330
-
450
500
VDD 5.0 V, IOUT 150 mA
Drop voltage with external transistor(19)
VDROP-B
mV
V
IOUT 200 mA (I_BALLAST + I_INTERNAL
VSUP/1 to maintain V within V
)
-
350
500
specified voltage range
OUT-3.3
VSUP1-3.3
DD
VDD 3.3 V, IOUT 150 mA
4.0
4.0
-
-
-
-
VDD 3.3 V, IOUT 200 mA, external transistor implemented
External ballast versus internal current ratio (I_BALLAST = K x Internal current)
Output Current limitation, without external transistor
Temperature pre-warning (Guaranteed by design)
Thermal shutdown (Guaranteed by design)
K
1.5
150
-
2.0
350
140
-
2.5
550
-
ILIM
mA
°C
°C
F
V
TPW
TSD
160
4.7
-
Range of decoupling capacitor (Guaranteed by design)(20)
CEXT
VDDLP
-
100
LP mode VDD ON, IOUT 50 mA (time limited)
VDD 5.0 V, 5.6 V V
VDD 3.3 V, 5.6 V V
28 V
28 V
4.75
5.0
3.3
5.25
SUP
SUP
3.135
3.465
LP mode VDD ON, dynamic output current capability (Limited duration. Ref. to
device description).
LP-IOUTDC
LP-ITH
-
-
50
mA
mA
LP VDD ON mode:
Over-current Wake-up threshold.
Hysteresis
1.0
0.1
-
3.0
1.0
200
-
-
LP mode VDD ON, drop voltage, at IOUT 30 mA (Limited duration. Ref. to
LP-VDROP
LP-MINVS
400
mV
V
device description) (19)
LP mode VDD ON, min VSUP operation (Below this value, a VDD, under-voltage
reset may occur)
5.5
-
-
VDD when VSUP < VSUP-TH1, at I_VDD 10 A (Guaranteed by design)
VDD_OFF
-
-
-
0.3
-
V
V
VDD when VSUP VSUP-TH1, at I_VDD 40 mA (Guaranteed with parameter
VSUP-TH1
VDD_START UP
3.0
Notes
19. For 3.3 V VDD devices, the drop-out voltage test condition leads to a VSUP below the min VSUP threshold (4.0 V). As a result, the dropout
voltage parameter cannot be specified.
20. The regulator is stable without an external capacitor. Usage of an external capacitor is recommended for AC performance.
33903/4/5
Analog Integrated Circuit Device Data
20
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 6. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V VSUP 28 V, -40 C TA 125 C, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
VOLTAGE REGULATOR FOR CAN INTERFACE SUPPLY, 5.0 V-CAN PIN
Output voltage, VSUP/2 = 5.5 to 40 V
V
5V-C OUT
IOUT 0 to 160 mA
4.75
5.0
5.25
Output Current limitation (21)
5V-C ILIM
5V-C UV
5V-CTS
160
4.1
280
-
4.7
-
mA
V
Under-voltage threshold
4.5
Thermal shutdown (Guaranteed by design)
External capacitance (Guaranteed by design)
160
1.0
-
-
°C
F
CEXT-CAN
100
V AUXILIARY OUTPUT, 5.0 AND 3.3 V SELECTABLE PIN VB-AUX, VC-AUX, VAUX
VAUX output voltage
VAUX
V
V
VAUX = 5.0 V, VSUP = VSUP2 5.5 to 40 V, IOUT 0 to 150 mA
VAUX = 3.3 V, VSUP = VSUP2 5.5 to 40 V, IOUT 0 to 150 mA
4.75
5.0
3.3
5.25
3.135
3.465
VAUX under-voltage detector (VAUX configured to 5.0 V)
VAUX-UVTH
Low Threshold
4.2
4.5
-
4.70
0.12
Hysteresis
0.06
2.75
VAUX under-voltage detector (VAUX configured to 3.3 V, default value)
3.0
3.135
VAUX over-current threshold detector
VAUX set to 3.3 V
VAUX-ILIM
mA
250
230
360
330
450
430
VAUX set to 5.0 V
External capacitance (Guaranteed by design)
VAUX CAP
2.2
-
100
F
UNDER-VOLTAGE RESET AND RESET FUNCTION, RST PIN
VDD under-voltage threshold down - 90% VDD (VDD 5.0 V)(22), (24)
VDD under-voltage threshold up - 90% VDD (VDD 5.0 V)
VRST-TH1
4.5
-
4.65
-
4.85
4.90
V
VDD under-voltage threshold down - 90% VDD (VDD 3.3 V)(22), (24)
2.75
-
3.0
-
3.135
3.135
3.45
VDD under-voltage threshold up - 90% VDD (VDD 3.3 V)
VDD under-voltage reset threshold down - 70% VDD (VDD 5.0 V)(23), (24)
Hysteresis
VRST-TH2-5
VRST-HYST
2.95
3.2
V
mV
for threshold 90% VDD, 5.0 V device
for threshold 70% VDD, 5.0 V device
Hysteresis 3.3 V VDD
20
10
-
-
150
150
for threshold 90% VDD, 3.3 V device
10
-
150
VDD under-voltage reset threshold down - LP VDD ON mode
(Note: device change to Normal Request mode). VDD 5.0 V
(Note: device change to Normal Request mode). VDD 3.3 V
VRST-LP
V
4.0
4.5
3.0
4.85
2.75
3.135
Notes
21. Current limitation will be reported by setting a flag.
22. Generate a Reset or an INT. SPI programmable
23. Generate a Reset
24. In Non-LP modes
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 6. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V VSUP 28 V, -40 C TA 125 C, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
UNDER-VOLTAGE RESET AND RESET FUNCTION, RST PIN (CONTINUED)
Reset VOL @ 1.5 mA, VSUP 5.5 to 28 V
Current limitation, Reset activated, VRESET = 0.9 x VDD
Pull-up resistor (to VDD pin)
VOL
-
300
7.0
11
-
500
10
15
-
mV
mA
k
V
IRESET LOW
RPULL-UP
VSUP-RSTL
VRST-VTH
2.5
8.0
2.5
VSUP to guaranteed reset low level(25)
Reset input threshold
V
Low threshold, VDD = 5.0 V
1.5
2.5
1.9
3.0
2.2
3.5
High threshold, VDD = 5.0 V
0.99
1.65
1.17
2.0
1.32
2.31
Low threshold, VDD = 3.3 V
High threshold, VDD = 3.3 V
Reset input hysteresis
VHYST
0.5
1.0
1.5
V
I/O PINS WHEN FUNCTION SELECTED IS OUTPUT
I/O-0 HS switch drop @ I = -12 mA, VSUP = 10.5 V
I/O-2 and I/O-3 HS switch drop @ I = -20 mA, VSUP = 10.5 V
I/O-1, HS switch drop @ I = -400 A, VSUP = 10.5 V
I/O-0, I/O-1 LS switch drop @ I = 400 A, VSUP = 10.5 V
Leakage current, I/O-x VSUP
VI/O-0 HSDRP
VI/O-2-3 HSDRP
VI/O-1 HSDRP
VI/O-01 LSDRP
II/O_LEAK
-
-
-
-
-
0.5
0.5
0.4
0.4
0.1
1.4
1.4
1.4
1.4
3.0
V
V
V
V
A
I/O PINS WHEN FUNCTION SELECTED IS INPUT
Negative threshold
VI/O_NTH
VI/O_PTH
VI/O_HYST
II/O_IN
1.4
2.1
0.2
-5.0
-
2.0
3.0
1.0
1.0
100
2.9
3.8
1.4
5.0
-
V
V
Positive threshold
Hysteresis
V
Input current, I/O VSUP/2
A
k
I/O-0 and I/O-1 input resistor. I/O-0 (or I/O-1) selected in
register, 2.0 V < VI/O-X <16 V (Guaranteed by design).
RI/O-X
VSENSE INPUT
VSENSE under-voltage threshold (Not active in LP modes)
VSENSE_TH
V
Low Threshold
High threshold
Hysteresis
8.1
-
8.6
-
9.0
9.1
0.5
-
0.1
-
0.25
125
Input resistor to GND. In all modes except in LP modes. (Guaranteed by
design).
RVSENSE
k
Notes
25. Reset must be kept low
33903/4/5
Analog Integrated Circuit Device Data
22
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 6. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V VSUP 28 V, -40 C TA 125 C, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
ANALOG MUX OUTPUT
Output Voltage Range, with external resistor to GND >2.0 k
Internal pull-down resistor for regulator output current sense
External capacitor at MUX OUTPUT(26) (Guaranteed by design)
VOUT_MAX
RMI
0.0
0.8
-
-
1.9
-
VDD - 0.5
2.8
V
k
CMUX
1.0
nF
Chip temperature sensor coefficient (Guaranteed by design and device
characterization)
TEMP-COEFF
mv/°C
VDD = 5.0 V
VDD = 3.3 V
20
21
22
13.2
13.9
14.6
Chip temperature: MUX-OUT voltage
VDD = 5.0 V, TA = 125 °C
VTEMP
V
V
3.6
3.75
2.58
3.9
VDD = 3.3 V, TA = 125 °C
2.45
2.65
Chip temperature: MUX-OUT voltage (guaranteed by design and
characterization)
VTEMP(GD)
TA = -40 °C, VDD = 5.0 V
TA = 25 °C, VDD = 5.0 V
TA = -40 °C, VDD = 3.3 V
TA = 25 °C, VDD = 3.3 V
0.12
1.5
0.30
1.65
0.19
1.14
0.48
1.8
0.07
1.08
0.3
1.2
Gain for VSENSE, with external 1.0 k 1% resistor
VSENSE GAIN
VDD = 5.0 V
VDD = 3.3 V
5.42
8.1
5.48
8.2
5.54
8.3
Offset for VSENSE, with external 1.0 k 1% resistor
VSENSE
-20
-
20
mV
OFFSET
Divider ratio for VSUP/1
VDD = 5.0 V
VSUP/1 RATIO
5.335
7.95
5.5
5.665
8.45
VDD = 3.3 V
8.18
Attenuation/Gain ratio for I/O-0 and I/O-1 actual voltage:
VDD = 5.0 V, I/O = 16 V (Attenuation, MUX-OUT register bit 3 set to 1)
VDD = 5.0 V, (Gain, MUX-OUT register bit 3 set to 0)
VI/O RATIO
3.8
-
4.0
2.0
5.8
1.3
4.2
-
5.6
-
6.2
-
VDD = 3.3 V, I/O = 16 V (Attenuation, MUX-OUT register bit 3 set to 1)
VDD = 3.3 V, (Gain, MUX-OUT register bit 3 set to 0)
Internal reference voltage
VDD = 5.0 V
VREF
V
2.45
1.64
2.5
2.55
1.7
VDD = 3.3 V
1.67
Current ratio between VDD output & IOUT at MUX-OUT
IDD_RATIO
(IOUT at MUX-OUT = IDD out / IDD_RATIO
At IOUT = 50 mA
)
80
97
97
115
117
I_OUT from 25 to 150 mA
62.5
SAFE OUTPUT
SAFE low level, at I = 500 A
VOL
0.0
-
0.2
0.0
1.0
1.0
V
Safe leakage current (VDD low, or device unpowered). VSAFE 0 to 28 V.
ISAFE-IN
A
Notes
26. When C is higher than CMUX, a serial resistor must be inserted
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 6. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V VSUP 28 V, -40 C TA 125 C, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
INTERRUPT
V
Output low voltage, IOUT = 1.5 mA
Pull-up resistor
VOL
RPU
-
0.2
10
1.0
14
k
V
6.5
3.9
-
Output high level in LP V
ON mode (Guaranteed by design)
VOH-LPVDDON
VMAX
4.3
35
DD
A
mA
Leakage current INT voltage = 10 V (to allow high-voltage on MCU INT pin)
Sink current, VINT > 5.0 V, INT low state
MISO, MOSI, SCLK, CS PINS
100
10
I SINK
2.5
6.0
Output low voltage, IOUT = 1.5 mA (MISO)
Output high voltage, IOUT = -0.25 mA (MISO)
Input low voltage (MOSI, SCLK,CS)
VOL
VOH
VIL
-
VDD -0.9
-
-
1.0
V
V
-
-
0.3 x VDD
V
Input high voltage (MOSI, SCLK,CS)
Tri-state leakage current (MISO)
VIH
IHZ
0.7 x VDD
-2.0
-
-
-
V
2.0
500
A
A
Pull-up current (CS)
IPU
200
370
CAN LOGIC INPUT PINS (TXD)
High Level Input Voltage
Low Level Input Voltage
Pull-up Current, TXD, VIN = 0 V
VDD =5.0 V
VIH
VIL
0.7 x VDD
-0.3
-
-
VDD + 0.3
0.3 x VDD
V
V
IPDWN
µA
-850
-500
-650
-250
-200
-175
VDD =3.3 V
CAN DATA OUTPUT PINS (RXD)
Low Level Output Voltage
IRXD = 5.0 mA
VOUTLOW
VOUTHIGH
IOUTHIGH
IOUTLOW
V
V
0.0
0.7 x VDD
2.5
-
0.3 x VDD
High Level Output Voltage
IRX = -3.0 mA
-
VDD
High Level Output Current
mA
mA
VRXD = V
- 0.4 V
5.0
5.0
9.0
DD
Low Level Input Current
VRXD = 0.4 V
2.5
9.0
33903/4/5
Analog Integrated Circuit Device Data
24
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 6. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V VSUP 28 V, -40 C TA 125 C, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
CAN OUTPUT PINS (CANH, CANL)
Symbol
Min
Typ
Max
Unit
VCOM
Bus pins common mode voltage for full functionality
Differential input voltage threshold
Differential input hysteresis
-12
500
50
-
12
900
-
V
mV
mV
k
k
%
VCANH-VCANL
VDIFF-HYST
-
-
-
Input resistance
RIN
5.0
10
50
Differential input resistance
RIN-DIFF
RIN-MATCH
VCANH
-
100
3.0
Input resistance matching
-3.0
0.0
CANH output voltage (45 < RBUS < 65)
TXD dominant state
V
2.75
2.0
3.5
2.5
4.5
3.0
TXD recessive state
CANL output voltage (45 < RBUS < 65)
TXD dominant state
VCANL
V
V
0.5
2.0
1.5
2.5
2.25
3.0
TXD recessive state
Differential output voltage (45 < RBUS < 65)
TXD dominant state
VOH-VOL
1.5
-0.5
-
2.0
0.0
-
3.0
0.05
-30
-
TXD recessive state
CAN H output current capability - Dominant state
CAN L output current capability - Dominant state
CANL over-current detection - Error reported in register
CANH over-current detection - Error reported in register
ICANH
ICANL
mA
mA
mA
mA
k
30
-
ICANL-OC
ICANH-OC
RINSLEEP
75
120
-120
-
195
-75
50
-195
5.0
CANH, CANL input resistance to GND, device supplied, CAN in Sleep mode,
V_CANH, V_CANL from 0 to 5.0 V
CANL, CANH output voltage in LP V
OFF and LP V
ON modes
VCANLP
-0.1
-
0.0
3.0
0.1
10
V
DD
DD
CANH, CANL input current, VCANH, VCANL = 0 to 5.0 V, device unpowered
(VSUP, VDD, 5V-CAN: open).(27)
ICAN-UN_SUP1
µA
CANH, CANL input current, VCANH, VCANL = -2.0 to 7.0 V, device
unpowered (VSUP, VDD, 5V-CAN: open).(27)
ICAN-UN_SUP2
-
-
250
µA
Differential voltage for recessive bit detection in LP mode(28)
Differential voltage for dominant bit detection in LP mode(28)
CANH AND CANL DIAGNOSTIC INFORMATION
CANL to GND detection threshold
VDIFF-R-LP
VDIFF-D-LP
-
-
-
0.4
-
V
V
1.15
VLG
VHG
VLVB
VHVB
VL5
1.6
1.6
-
1.75
2.0
V
V
V
V
V
V
CANH to GND detection threshold
1.75
2.0
CANL to VBAT detection threshold, VSUP/1 and VSUP2 > 8.0 V
CANH to VBAT detection threshold, VSUP/1 and VSUP2 > 8.0 V
CANL to VDD detection threshold
VSUP -2.0
VSUP -2.0
VDD -0.43
VDD -0.43
-
-
-
-
-
4.0
4.0
CANH to VDD detection threshold
VH5
Notes
27. VSUP, VDD, 5V-CAN: shorted to GND, or connected to GND via a 47 k resistor instances are guaranteed by design and device
characterization.
28. Guaranteed by design and device characterization.
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 6. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V VSUP 28 V, -40 C TA 125 C, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SPLIT
Output voltage
VSPLIT
V
Loaded condition ISPLIT = ±500 µA
0.3 x VDD 0.5 x VDD 0.7 x VDD
Unloaded condition Rmeasure > 1.0 M
0.45 x 0.5 x VDD 0.55 x VDD
VDD
Leakage current
ILSPLIT
µA
-12 V < VSPLIT < +12 V
-22 to -12 V < VSPLIT < +12 to +35 V
-
-
0.0
-
5.0
200
LIN TERMINALS (LIN-T/1, LIN-T2)
LIN-T1, LIN-T2, HS switch drop @ I = -20 mA, V
> 10.5 V
VLT_HSDRP
-
1.0
1.4
V
SUP
LIN1 & LIN2 33903D/5D PIN - LIN 33903S/5S PIN (Parameters guaranteed for VSUP/1, VSUP2 7.0 V VSUP 18 V)
Operating Voltage Range
VBAT
VSUP
8.0
7.0
-
-
18
18
V
V
Supply Voltage Range
Current Limitation for Driver Dominant State
Driver ON, VBUS = 18 V
IBUS_LIM
mA
40
-1.0
-
90
-
200
-
Input Leakage Current at the receiver
Driver off; VBUS = 0 V; VBAT = 12 V
IBUS_PAS_DOM
IBUS_PAS_REC
IBUS_NO_GND
mA
µA
Leakage Output Current to GND
Driver Off; 8.0 V VBAT 18 V; 8.0 V VBUS 18 V; VBUS VBAT
-
20
1.0
Control unit disconnected from ground (Loss of local ground must not affect
communication in the residual network)
mA
-1.0
-
GNDDEVICE = VSUP; VBAT = 12 V; 0 < V
< 18 V (Guaranteed by design)
BUS
V
Disconnected; VSUP_DEVICE = GND; 0 < V
< 18 V (Node has to
IBUSNO_BAT
µA
BAT
BUS
sustain the current that can flow under this condition. Bus must remain
operational under this condition). (Guaranteed by design)
-
-
100
Receiver Dominant State
VBUSDOM
VBUSREC
VBUS_CNT
VSUP
VSUP
VSUP
-
-
-
0.4
-
Receiver Recessive State
0.6
Receiver Threshold Center
(VTH_DOM + VTH_REC)/2
0.475
0.5
0.525
Receiver Threshold Hysteresis
VHYS
VSUP
(VTH_REC - VTH_DOM
)
-
-
0.175
LIN Wake-up threshold from LP V
ON or LP V
OFF mode
DD
VBUSWU
RSLAVE
-
20
140
-
5.3
30
5.8
60
180
-
V
DD
LIN Pull-up Resistor to V
SUP
k
°C
°C
Over-temperature Shutdown (Guaranteed by design)
TLINSD
160
10
Over-temperature Shutdown Hysteresis (Guaranteed by design)
TLINSD_HYS
33903/4/5
Analog Integrated Circuit Device Data
26
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 7. Dynamic Electrical Characteristics
Characteristics noted under conditions 5.5 V VSUP 28 V, -40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SPI TIMING
SPI Operation Frequency (MISO cap = 50 pF)
SCLK Clock Period
FREQ
tPCLK
0.25
250
125
125
-
-
-
-
4.0
N/A
N/A
N/A
MHz
ns
SCLK Clock High Time
tWSCLKH
tWSCLKL
tLEAD
ns
SCLK Clock Low Time
ns
Falling Edge of CS to Rising Edge of SCLK
ns
“C” version
All others
30
550
-
-
N/A
N/A
Falling Edge of SCLK to Rising Edge of CS
MOSI to Falling Edge of SCLK
Falling Edge of SCLK to MOSI
MISO Rise Time (CL = 50 pF)
MISO Fall Time (CL = 50 pF)
tLAG
tSISU
tSIH
30
30
30
-
-
-
-
-
-
N/A
N/A
N/A
30
ns
ns
ns
ns
ns
ns
tRSO
tFSO
tSOEN
tSODIS
-
30
Time from Falling to MISO Low-impedance
Time from Rising to MISO High-impedance
-
-
-
-
30
30
Time from Rising Edge of SCLK to MISO Data Valid
Delay between falling and rising edge on CS
tVALID
-
-
30
ns
tCSLOW
s
“C” version
All others
1.0
5.5
-
-
N/A
N/A
CS Chip Select Low Timeout Detection
tCS-TO
2.5
-
-
ms
SUPPLY, VOLTAGE REGULATOR, RESET
tVS_LOW1/
2_DGLT
V
under-voltage detector threshold deglitcher
SUP
30
50
100
s
Rise time at turn ON. VDD from 1.0 to 4.5V. 2.2 F at the VDD pin.
Deglitcher time to set RST pin low
tRISE-ON
50
20
250
30
800
40
s
s
tRST-DGLT
RESET PULSE DURATION
VDD under-voltage (SPI selectable)
tRST-PULSE
ms
short, default at power on when BATFAIL bit set
0.9
4.0
8.5
17
1.0
5.0
10
1.4
6.0
12
medium
medium long
long
20
24
Watchdog reset
tRST-WD
0.9
19
30
1.0
30
-
1.4
41
ms
s
s
I/O INPUT
Deglitcher time (Guaranteed by design)
VSENSE INPUT
tIODT
Under-voltage deglitcher time
tBFT
100
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 7. Dynamic Electrical Characteristics
Characteristics noted under conditions 5.5 V VSUP 28 V, -40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
INTERRUPT
INT pulse duration (refer to SPI for selection. Guaranteed by design)
short (25 to 125 °C)
tINT-PULSE
s
20
25
35
short (-40 °C)
long (25 to 125 °C)
20
90
25
100
40
130
long (-40 °C)
90
100
140
STATE DIGRAM TIMINGS
Delay for SPI Timer A, Timer B or Timer C write command after entering Normal
mode
tD_NM
60
-
-
s
(No command should occur within tD_NM
.
tD_NM delay definition: from CS rising edge of “Go to Normal mode (i.e. 0x5A00)”
command to CS falling edge of “Timer write” command)
Tolerance for: watchdog period in all modes, FWU delay, Cyclic sense period
and active time, Cyclic Interrupt period, LP mode over-current (unless otherwise
noted)(32)
t
-10
-
10
%
TIMING-ACC
CAN DYNAMIC CHARACTERISTICS
TXD Dominant State Timeout
tDOUT
tDOM
300
600
600
120
70
1000
1000
210
110
µs
µs
ns
ns
ns
ns
ns
ns
ns
Bus dominant clamping detection
300
Propagation loop delay TXD to RXD, recessive to dominant (Fast slew rate)
Propagation delay TXD to CAN, recessive to dominant
Propagation delay CAN to RXD, recessive to dominant
Propagation loop delay TXD to RXD, dominant to recessive (Fast slew rate)
Propagation delay TXD to CAN, dominant to recessive
Propagation delay CAN to RXD, dominant to recessive
tLRD
60
tTRD
-
tRRD
-
45
140
200
150
140
tLDR
100
120
75
tTDR
-
-
tRDR
50
Loop time TXD to RXD, Medium Slew Rate (Selected by SPI)
Recessive to Dominant
tLOOP-MSL
-
-
200
200
-
-
Dominant to Recessive
Loop time TXD to RXD, Slow Slew Rate (Selected by SPI)
Recessive to Dominant
tLOOP-SSL
ns
-
-
300
300
-
-
Dominant to Recessive
CAN Wake-up filter time, single dominant pulse detection(29) (See Figure 35)
CAN Wake-up filter time, 3 dominant pulses detection(30)
tCAN-WU1-F
tCAN-WU3-F
tCAN-WU3-TO
0.5
300
-
2.0
5.0
-
s
ns
s
-
-
CAN Wake-up filter time, 3 dominant pulses detection timeout(31) (See
Figure 36)
120
Notes
29. No Wake-up for single pulse shorter than tCAN-WU1 min. Wake-up for single pulse longer than tCAN-WU1 max.
30. Each pulse should be greater than tCAN-WU3-F min. Guaranteed by design, and device characterization.
31. The 3 pulses should occur within tCAN-WU3-TO. Guaranteed by design, and device characterization.
32. Guaranteed by design.
33903/4/5
Analog Integrated Circuit Device Data
28
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 7. Dynamic Electrical Characteristics
Characteristics noted under conditions 5.5 V VSUP 28 V, -40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR NORMAL SLEW RATE - 20.0 KBIT/SEC ACCORDING TO LIN PHYSICAL
LAYER SPECIFICATION
BUS LOAD RBUS AND CBUS 1.0 NF / 1.0 K, 6.8 NF / 660 , 10 NF / 500 . SEE Figure 18, PAGE 32.
Duty Cycle 1:
D1
THREC(MAX) = 0.744 * VSUP
THDOM(MAX) = 0.581 * VSUP
0.396
-
-
-
D1 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 50 µs, 7.0 V VSUP18 V
Duty Cycle 2:
D2
THREC(MIN) = 0.422 * VSUP
THDOM(MIN) = 0.284 * VSUP
-
0.581
D2 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 50 µs, 7.6 V VSUP18 V
LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR SLOW SLEW RATE - 10.4 KBIT/SEC ACCORDING TO LIN PHYSICAL LAYER
SPECIFICATION
BUS LOAD RBUS AND CBUS 1.0 NF / 1.0 K, 6.8 NF / 660 , 10 NF / 500 . MEASUREMENT THRESHOLDS. SEE Figure 19, PAGE 33.
Duty Cycle 3:
D3
THREC(MAX) = 0.778 * VSUP
THDOM(MAX) = 0.616 * VSUP
0.417
-
-
D3 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 96 µs, 7.0 V VSUP18 V
Duty Cycle 4:
D4
THREC(MIN) = 0.389 * VSUP
THDOM(MIN) = 0.251 * VSUP
-
-
-
0.590
-
D4 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 96 µs, 7.6 V VSUP18 V
LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR FAST SLEW RATE
LIN Fast Slew Rate (Programming Mode)
SR
20
V/s
s
FAST
LIN PHYSICAL LAYER: CHARACTERISTICS AND WAKE-UP TIMINGS
VSUP FROM 7.0 TO 18 V, BUS LOAD RBUS AND CBUS 1.0 NF / 1.0 K, 6.8 NF / 660 , 10 NF / 500 . SEE Figure 18, PAGE 32.
Propagation Delay and Symmetry (See Figure 18, page 31 and Figure 19,
page 33)
Propagation Delay of Receiver, tREC_PD = MAX (tREC_PDR, tREC_PDF
Symmetry of Receiver Propagation Delay, tREC_PDF - tREC_PDR
)
tREC_PD
-
4.2
-
6.0
2.0
tREC_SYM
-2.0
Bus Wake-up Deglitcher (LP V OFF and LP V ON modes) (See Figure 20,
tPROPWL
42
70
95
s
s
DD
DD
page 32 for LP V
OFF mode and Figure 21, page 33 for LP mode)
DD
Bus Wake-up Event Reported
From LP V
OFF mode
tWAKE_LPVDD
-
-
1500
DD
OFF
tWAKE_LPVDD
From LP V
ON mode
1.0
-
12
DD
ON
TXD Permanent Dominant State Delay (Guaranteed by design)
tTXDDOM
0.65
1.0
1.35
s
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
t
PCLK
CS
t
WCLKH
t
LEAD
t
LAG
SCLK
t
WCLKL
t
t
SIH
SISU
MOSI
MISO
Undefined
Di 0
Don’t Care
Di n
Don’t Care
t
VALID
t
SODIS
t
SOEN
Do 0
Do n
t
CSLOW
Figure 14. SPI Timings
t
LRD
TXD
0.7 x V
DD
0.3 x V
DD
t
LDR
0.7 x V
RXD
DD
0.3 x V
DD
Figure 15. CAN Signal Propagation Loop Delay TXD to RXD
33903/4/5
Analog Integrated Circuit Device Data
30
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
t
TRD
TXD
0.7 x V
DD
0.3 x VDD
t
TDR
0.9 V
V
DIFF
0.5 V
t
RRD
t
RDR
0.7 x V
RXD
DD
0.3 x V
DD
Figure 16. CAN Signal Propagation Delays TXD to CAN and CAN to RXD
.
12 V
10 F
5 V_CAN
CANH
VSUP
TXD
22 F
100 nF
Signal generator
RBUS
CBus
60
100 pF
CANL
SPLIT
RXD
All pins are not shown
GND
15 pF
Figure 17. Test Circuit for CAN Timing Characteristics
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
31
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TXD
tBIT
tBIT
t
t
BUS_REC(MIN)
BUS_DOM(MAX)
VLIN_REC
74.4% VSUP
Thresholds of
receiving node 1
TH
REC(MAX)
DOM(MAX)
58.1% V
SUP
TH
LIN
Thresholds of
receiving node 2
42.2% V
28.4% V
SUP
SUP
TH
REC(MIN)
TH
DOM(MIN)
t
BUS_DOM(MIN)
t
BUS_REC(MAX)
RXD
Output of receiving Node 1
t
REC_PDF(1)
t
REC_PDR(1)
RXD
Output of receiving Node 2
t
REC_PDF(2)
t
REC_PDR(2)
Figure 18. LIN Timing Measurements for Normal Slew Rate
33903/4/5
Analog Integrated Circuit Device Data
32
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TXD
tBIT
tBIT
t
t
BUS_REC(MIN)
BUS_DOM(MAX)
VLIN_REC
77.8% VSUP
Thresholds of
receiving node 1
TH
REC(MAX)
DOM(MAX)
61.6% V
SUP
TH
LIN
Thresholds of
receiving node 2
38.9% V
25.1% V
SUP
SUP
TH
REC(MIN)
TH
DOM(MIN)
t
BUS_DOM(MIN)
t
BUS_REC(MAX)
RXD
Output of receiving Node 1
t
REC_PDF(1)
t
REC_PDR(1)
RXD
Output of receiving Node 2
t
REC_PDF(2)
t
REC_PDR(2)
Figure 19. LIN Timing Measurements for Slow Slew Rate
V
REC
V
BUSWU
LIN
0.4 V
SUP
Dominant level
3V
VDD
T
T
WAKE
PROPWL
Figure 20. LIN Wake-up LP VDD OFF Mode Timing
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
33
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
VLIN_REC
LIN
V
BUSWU
0.4 V
SUP
Dominant level
IRQ
T
T
PROPWL
WAKE
IRQ stays low until SPI reading command
Figure 21. LIN Wake-up LP VDD ON Mode Timing
33903/4/5
Analog Integrated Circuit Device Data
34
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The MC33903_4_5 is the second generation of System
Basis Chip, combining:
- Built in LIN interface, compliant to LIN 2.1 and J2602-2
specification, with local and bus failure diagnostic and
protection.
- Advanced power management unit for the MCU, the
integrated CAN interface and for the additional ICs such as
sensors, CAN transceiver.
- Innovative hardware configurable fail-safe state machine
solution.
- Built in enhanced high speed CAN interface (ISO11898-
2 and -5), with local and bus failure diagnostic, protection,
and fail-safe operation mode.
- Multiple LP modes, with low current consumption.
- Family concept with pin compatibility; with and without
LIN interface devices.
FUNCTIONAL PIN DESCRIPTION
(Wake-up detection, timer start for over-current duration
monitoring or watchdog refresh).
POWER SUPPLY (VSUP/1 AND VSUP2)
Note: VSUP1 and VSUP2 supplies are externally available
on all devices except the 33903D, 33903S, and 33903P,
where these are connected internally.
EXTERNAL TRANSISTOR Q1 (VE AND VB)
The device has a dedicated circuit to allow usage of an
external “P” type transistor, with the objective to share the
power dissipation between the internal transistor of the VDD
regulator and the external transistor. The recommended
bipolar PNP transistor is MJD42C or BCP52-16.
VSUP1 is the input pin for the internal supply and the VDD
regulator. VSUP2 is the input pin for the 5 V-CAN regulator,
LIN’s interfaces and I/O functions. The VSUP block includes
over and under-voltage detections which can generate
interrupt. The device includes a loss of battery detector
connected to VSUP/1.
When the external PNP is connected, the current is shared
between the internal path transistor and the external PNP,
with the following typical ratio: 1/3 in the internal transistor
and 2/3 in the external PNP. The PNP activation and control
is done by SPI.
Loss of battery is reported through a bit (called BATFAIL).
This generates a POR (Power On Reset).
VDD VOLTAGE REGULATOR (VDD)
The device is able to operate without an external
transistor. In this case, the VE and VB pins must remain
open.
The regulator has two main modes of operation (Normal
mode and LP mode). It can operate with or without an
external PNP transistor.
In Normal mode, without external PNP, the max DC
capability is 150 mA. Current limitation, temperature pre-
warning flag and over-temperature shutdown features are
included. When VDD is turned ON, rise time from 0 to 5.0 V is
controlled. Output voltage is 5.0 V. A 3.3 V option is available
via dedicated part number.
5 V-CAN VOLTAGE REGULATOR FOR CAN AND
ANALOG MUX
This regulator is supplied from the VSUP/2 pin. A capacitor
is required at 5 V-CAN pin. Analog MUX and part of the LIN
interfaces are supplied from 5 V-CAN. Consequently, the
5 V-CAN must be ON in order to have Analog MUX operating
and to have the LIN interface operating in TXD/RXD mode.
If current higher than 150 mA is required, an external PNP
transistor must be connected to VE (PNP emitter) and VB
(PNP base) pins, in order to increase total current capability
and share the power dissipation between internal VDD
transistor and the external transistor. See External Transistor
Q1 (VE and VB). The PNP can be used even if current is less
than 150 mA, depending upon ambient temperature,
The 5 V-CAN regulator is OFF by default and must be
turned ON by SPI. In Debug mode, the 5 V-CAN is ON by
default.
V AUXILIARY OUTPUT, 5.0 AND 3.3 V
SELECTABLE (VB-AUX, VC-AUX, AND VCAUX) -
Q2
maximum supply and thermal resistance. Typically, above
100-200 mA, an external ballast transistor is recommended.
The VAUX block is used to provide an auxiliary voltage
output, 5.0 or 3.3 V, selectable by the SPI. It uses an external
PNP pass transistor for flexibility and power dissipation
constraints. The external recommended bipolar transistors
are MJD42C or BCP52-16.
VDD REGULATOR IN LP MODE
When the device is set in LP VDD ON mode, the VDD
regulator is able to supply the MCU with a DC current below
typically 1.5 mA (LP-ITH). Transient current can also be
supplied up to a tenth of a mA. Current in excess of 1.5 mA
is detected, and this event is managed by the device logic
An over-current and under-voltage detectors are provided.
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
35
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
VAUX is controlled via the SPI, and can be turned ON or
OFF. VAUX low threshold detection and over-current
information will disable VAUX, and are reported in the SPI and
can generate INT.
When cyclic sense is used, I/O-0 is the HS/LS switch, I/O-
1, -2 and -3 are the wake inputs.
I/O-2 and I/O-3 pins share the LIN Master pin function.
VAUX is OFF by default and must be turned ON by the SPI.
VSENSE INPUT (VSENSE)
This pin can be connected to the battery line (before the
reverse battery protection diode), via a serial resistor and a
capacitor to GND. It incorporates a threshold detector to
sense the battery voltage and provide a battery early
warning. It also includes a resistor divider to measure the
VSENSE voltage via the MUX-OUT pin.
UNDER-VOLTAGE RESET AND RESET FUNCTION
(RST)
The RST pin is an open drain structure with an internal
pull-up resistor. The LS driver has limited current capability
when asserted low, in order to tolerate a short to 5.0 V. The
RST pin voltage is monitored in order to detect failure (e.g.
RST pin shorted to 5.0 V or GND).
MUX-OUTPUT (MUXOUT)
The RST pin reports an under-voltage condition to the
MCU at the VDD pin, as a RST failure in the watchdog refresh
operation. VDD under-voltage reset also operates in LP VDD
ON mode.
The MUX-OUT pin (Figure 22) delivers an analog voltage
to the MCU A/D input. The voltage to be delivered to MUX-
OUT is selected via the SPI, from one of the following
functions: VSUP/1, VSENSE, I/O-0, I/O-1, Internal 2.5 V
reference, die temperature sensor, VDD current copy.
Two VDD under-voltage thresholds are included. The
upper (typically 4.65 V, RST-TH1-5) can lead to a Reset or an
Interrupt. This is selected by the SPI. When “RST-TH2-5“is
selected, in Normal mode, an INT is asserted when VDD falls
below “RST-TH1-5“, then, when VDD falls below “RST-TH2-5” a
Reset will occur. This will allow the MCU to operate in a
degraded mode (i.e., with 4.0 V VDD).
Voltage divider or amplifier is inserted in the chain, as
shown in Figure 22.
For the VDD current copy, a resistor must be added to the
MUX-OUT pin, to convert current into voltage. Device
includes an internal 2.0 k resistor selectable by the SPI.
Voltage range at MUX-OUT is from GND to VDD. It is
automatically limited to VDD (max 3.3 V for 3.3 V part
numbers).
I/O PINS (I/O-0: I/O-3)
I/Os are configurable input/output pins. They can be used
for small loads or to drive external transistors. When used as
output drivers, the I/Os are either a HS or LS type. They can
also be set to high-impedance. I/Os are controlled by the SPI
and at power on, the I/Os are set as inputs. They include
over-load protection by temperature or excess of a voltage
drop.
The MUX-OUT buffer is supplied from 5 V-CAN regulator,
so the 5 V-CAN regulator must be ON in order to have:
1) MUX-OUT functionality and
2) SPI selection of the analog function.
If the 5 V-CAN is OFF, the MUX-OUT voltage is near GND
and the SPI command that selects one of the analog inputs
is ignored.
When I/O-0/-1/-2/-3 voltage is greater than VSUP/2
voltage, the leakage current (II/O_LEAK) parameter is not
applicable
Delay must be respected between SPI commands for 5 V-
CAN turned ON and SPI to select MUX-OUT function. The
delay depends mainly upon the 5 V-CAN capacitor and load
on 5 V-CAN.
• I/O-0 and I/O-1 will have current flowing into the device
through three diodes limited by an 80 kOhm resistor (in
series).
• I/O-2 and I/O-3 will have unlimited current flowing into the
device through one diode.
The delay can be estimated using the following formula:
delay = C(5 V-CAN) x U (5.0 V) / I_lim 5 V-CAN.
C = cap at 5 V-CAN regulator, U = 5.0 V,
In LP mode, the state of the I/O can be turned ON or OFF,
with extremely low power consumption (except when there is
a load). Protection is disabled in LP mode.
I_LIM 5 V-CAN = min current limit of 5 V-CAN regulator
(parameter 5 V-C ILIM).
33903/4/5
Analog Integrated Circuit Device Data
36
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
VBAT
D1
S_in
S_in
VDD-I_COPY
Multiplexer
VSUP/1
VSENSE
S_iddc
5 V-CAN
5 V-CAN
R
1.0 k
SENSE
MCU
MUX-OUT
RM(*)
buffer
S_g3.3
A/D in
S_in
I/O-0
I/O-1
RMI
S_ir
S_g5
S_I/O_att
S_in
(*)Optional
All swicthes and resistor are configured and controlled via the SPI
R : internal resistor connected when V current monitor is used
Temp
VREF: 2.5 V
M
REG
S_g3.3 and S_g5 for 5.0 V or 3.3 V VDD versions
S_iddc to select V regulator current copy
S_in1 for LP mode resistor bridge disconnection
DD
S_ir to switch on/off of the internal R resistor
S_I/O_att for I/O-0 and I/O-1 attenuation selection
MI
S_I/O_att
Figure 22. Analog Multiplexer Block Diagram
Flexibility is provided to select SAFE output operation via
DGB (DGB) AND DEBUG MODE
Primary Function
a resistor at the DBG pin or via a SPI command. The SPI
command has higher priority than the hardware selection via
Debug resistor.
It is an input used to set the device in Debug mode. This is
achieved by applying a voltage between 8.0 and 10 V at the
DEBUG pin and then, powering up the device (See State
Diagram). When the device leaves the INIT Reset mode and
enters into INIT mode, it detects the voltage at the DEBUG
pin to be between a range of 8.0 to 10 V, and activates the
Debug mode.
When the Debug mode is selected, the SAFE modes
cannot be configured via the resistor connected at DBG pin.
SAFE
Safe Output Pin
When Debug mode is detected, no Watchdog SPI refresh
commands are necessary. This allows an easy debug of the
hardware and software routines (i.e. SPI commands).
This pin is an output and is asserted low when a fault event
occurs. The objective is to drive electrical safe circuitry and
set the ECU in a known state, independent of the MCU and
SBC, once a failure has been detected.
When the device is in Debug mode it is reported by the SPI
flag. While in Debug mode, and the voltage at DBG pin falls
below the 8.0 to 10 V range, the Debug mode is left, and the
device starts the watchdog operation, and expects the proper
watchdog refresh. The Debug mode can be left by SPI. This
is recommended to avoid staying in Debug mode when an
unwanted Debug mode selection (FMEA pin) is present. The
SPI command has a higher priority than providing 8.0 to 10 V
at the DEBUG pin.
The SAFE output structure is an open drain, without a pull-
up.
INTERRUPT (INT)
The INT output pin is asserted low or generates a low
pulse when an interrupt condition occurs. The INT condition
is enabled in the INT register. The selection of low level or
pulse and pulse duration are selected by SPI.
No current will flow inside the INT structure when VDD is
low, and the device is in LP VDD OFF mode. This allows the
connection of an external pull-up resistor and connection of
an INT pin from other ICs without extra consumption in
unpowered mode.
Secondary Function
The resistor connected between the DBG pin and the GND
selects the Fail-Safe mode operation. DBG pin can also be
connected directly to GND (this prevents the usage of Debug
mode).
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
37
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
INT has an internal pull-up structure to VDD. In LP VDD ON
mode, a diode is inserted in series with the pull-up, so the
high level is slightly lower than in other modes.
The MC33903, MC33903P, and MC33904 do not have a
LIN interface. However, the MC33903S/5S (S = Single) and
MC33903D/5D (D=Dual) contain 1 and 2 LIN interfaces,
respectively.
CANH, CANL, SPLIT, RXD, TXD
LIN, LIN1 and LIN2 pins are the connection to the LIN sub
buses.
These are the pins of the high speed CAN physical
interface, between the CAN bus and the micro controller. A
detail description is provided in the document.
LIN interfaces are connected to the MCU via the TXD,
TXD-L1 and TXD-L2 and RXD, RXD-L1 and RXD-L2 pins.
The device also includes one or two HS switches to VSUP/
2 pin which can be used as a LIN master termination switch.
Pins LINT, LINT-1 and LINT-2 pins are the same as
I/O-2 and I/O-3.
LIN, LIN-T, TXDL AND RXDL
These are the pins of the LIN physical interface. Device
contains zero, one or two LIN interfaces.
33903/4/5
Analog Integrated Circuit Device Data
38
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
MODE AND STATE DESCRIPTION
FUNCTIONAL DEVICE OPERATION
MODE AND STATE DESCRIPTION
The device has several operation modes. The transitions
and conditions to enter or leave each mode are illustrated in
the state diagram.
A watchdog refresh SPI command is necessary to
transition to NORMAL mode. The duration of the Normal
request mode is 256 ms when Normal Request mode is
entered after RESET mode. Different durations can be
selected by SPI when normal request is entered from LP VDD
ON mode.
INIT RESET
This mode is automatically entered after the device is
“powered on”. In this mode, the RST pin is asserted low, for
a duration of typically 1.0 ms. Control bits and flags are “set”
to their default reset condition. The BATFAIL is set to indicate
the device is coming from an unpowered condition, and all
previous device configurations are lost and “reset” the default
value. The duration of the INIT reset is typically 1.0 ms.
If the watchdog refresh SPI command does not occur
within the 256 ms (or the shorter user defined time out), then
the device will enter into RESET mode for a duration of
typically 1.0 ms.
Note: in init reset, init, reset and normal request modes as
well as in LP modes, the VDD external PNP is disabled.
INIT reset mode is also entered from INIT mode if the
expected SPI command does not occur in due time (Ref. INIT
mode), and if the device is not in the debug mode.
NORMAL
In this mode, all device functions are available. This mode
is entered by a SPI watchdog refresh command from Normal
Request mode, or from INIT mode.
INIT
This mode is automatically entered from the INIT Reset
mode. In this mode, the device must be configured via SPI
within a time of 256 ms max.
Four registers called INIT Wdog, INIT REG, INIT LIN I/O
and INIT MISC must be, and can only be configured during
INIT mode.
During Normal mode, the device watchdog function is
operating, and a periodic watchdog refresh must occur.
When an incorrect or missing watchdog refresh command is
initiated, the device will enter into Reset mode.
While in Normal mode, the device can be set to LP modes
(LP VDD ON or LP VDD OFF) using the SPI command.
Dedicated, secured SPI commands must be used to enter
from Normal mode to Reset mode, INIT mode or Flash mode.
Other registers can be written in this and other modes.
Once the INIT register configuration is done, a SPI
Watchdog Refresh command must be sent in order to set the
device into Normal mode. If the SPI watchdog refresh does
not occur within the 256 ms period, the device will return into
INIT Reset mode for typically 1.0 ms, and then re enter into
INIT mode.
FLASH
In this mode, the software watchdog period is extended up
to typically 32 seconds. This allow programming of the MCU
flash memory while minimizing the software over head to
refresh the watchdog. The flash mode is entered by Secured
SPI command and is left by SPI command. Device will enter
into Reset mode. When an incorrect or missing watchdog
refresh command device will enter into Reset mode. An
interrupt can be generated at 50% of the watchdog period.
Register read operation is allowed in INIT mode to collect
device status or to read back the INIT register configuration.
When INIT mode is left by a SPI watchdog refresh
command, it is only possible to re-enter the INIT mode using
a secured SPI command. In INIT mode, the CAN, LIN1, LIN2,
VAUX, I/O_x and Analog MUX functions are not operating.
The 5 V-CAN is also not operating, except if the Debug mode
is detected.
CAN interface operates in Flash mode to allow flash via
CAN bus, inside the vehicle.
RESET
In this mode, the RST pin is asserted low. Reset mode is
entered from Normal mode, Normal Request mode, LP VDD
on mode and from the Flash mode when the watchdog is not
triggered, or if a VDD low condition is detected.
DEBUG
Debug is a special operation mode of the device which
allows for easy software and hardware debugging. The
debug operation is detected after power up if the DBG pin is
set to 8.0 to 10 V range.
The duration of reset is typically 1.0 ms by default. You
can define a longer Reset pulse activation only when the
Reset mode is entered following a VDD low condition. Reset
pulse is always 1.0 ms, when reset mode is entered due to
wrong watchdog refresh command.
When debug is detected, all the software watchdog
operations are disabled: 256 ms of INIT mode, watchdog
refresh of Normal mode and Flash mode, Normal Request
time out (256 ms or user defined value) are not operating and
will not lead to transition into INIT reset or Reset mode.
Reset mode can be entered via the secured SPI
command.
When the device is in Debug mode, the SPI command can
be sent without any time constraints with respect to the
watchdog operation and the MCU program can be “halted” or
“paused” to verify proper operation.
NORMAL REQUEST
This mode is automatically entered after RESET mode, or
after a Wake-up from LP VDD ON mode.
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
39
FUNCTIONAL DEVICE OPERATION
LP MODES
Debug can be left by removing 8 to 10 V from the DEBUG
pin, or by the SPI command (Ref. to MODE register).
The 5 V-CAN regulator is ON by default in Debug mode.
LP MODES
The device has two main LP modes: LP mode with VDD
OFF, and LP mode with VDD ON.
During this mode, the 5 V-CAN and VAUX regulators are
OFF. The optional external PNP at VDD will also be
automatically disabled when entering this mode.
Prior to entering into LP mode, I/O and CAN Wake-up
flags must be cleared (Ref. to mode register). If the Wake-up
flags are not cleared, the device will not enter into LP mode.
In addition, the CAN failure flags (i.e. CAN_F and CAN_UF)
must be cleared, in order to meet the LP current consumption
specification.
The same Wake-up events as in LP VDD OFF mode (CAN,
LIN, I/O, timer, cyclic sense) are available in LP VDD on
mode.
In addition, two additional Wake-up conditions are
available.
• Dedicated SPI command. When device is in LP VDD ON
mode, the Wake-up by SPI command uses a write to
“Normal Request mode”, 0x5C10.
LP - V OFF
DD
In this mode, VDD is turned OFF and the MCU connected
to VDD is unsupplied. This mode is entered using SPI. It can
also be entered by an automatic transition due to fail-safe
management. 5 V-CAN and VAUX regulators are also turned
OFF.
• Output current from VDD exceeding LP-ITH threshold.
In LP VDD ON mode, the device is able to source several
tenths of mA DC. The current source capability can be time
limited, by a selectable internal timer. Timer duration is up to
32 ms, and is triggered when the output current exceed the
output current threshold typically 1.5 mA.
When the device is in LP VDD OFF mode, it monitors
external events to Wake-up and leave the LP mode. The
Wake-up events can occur from:
This allows for instance, a periodic activation of the MCU,
while the device remains in LP VDD on mode. If the duration
exceed the selected time (ex 32 ms), the device will detect a
Wake-up.
• CAN
• LIN interface, depending upon device part number
• Expiration of an internal timer
• I/O-0, and I/O-1 inputs, and depending upon device part
number and configuration, I/O-2 and/or -3 input
• Cyclic sense of I/O-1 input, associated by I/O-0
activation, and depending upon device part number and
configuration, cyclic sense of I/O-2 and -3 input,
associated by I/O-0 activation
Wake-up events are reported to the MCU via a low level
pulse at INT pulse. The MCU will detect the INT pulse and
resume operation.
Watchdog Function in LP VDD ON Mode
It is possible to enable the watchdog function in LP VDD
ON mode. In this case, the principle is timeout.
When a Wake-up event is detected, the device enters into
Reset mode and then into Normal Request mode. The Wake-
up sources are reported to the device SPI registers. In
summary, a Wake-up event from LP VDD OFF leads to the
VDD regulator turned ON, and the MCU operation restart.
Refresh of the watchdog is done either by:
• a dedicated SPI command (different from any other SPI
command or simple CS activation which would Wake-
up - Ref. to the previous paragraph)
• or by a temporary (less than 32 ms max) VDD over
current Wake-up (IDD > 1.5 mA typically).
LP - V ON
DD
In this mode, the voltage at the VDD pin remains at 5.0 V
(or 3.3 V, depending upon device part number). The
objective is to maintain the MCU powered, with reduced
consumption. In such mode, the DC output current is
expected to be limited to 100 A or a few mA, as the ECU is
in reduced power operation mode.
As long as the watchdog refresh occurs, the device
remains in LP VDD on mode.
Mode Transitions
Mode transitions are either done automatically (i.e. after a
timeout expired or voltage conditions), or via a SPI command,
or by an external event such as a Wake-up. Some mode
changes are performed using the Secured SPI commands.
33903/4/5
Analog Integrated Circuit Device Data
40
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
STATE DIAGRAM
STATE DIAGRAM
V
rise > V
SUP/1
SUP-TH1
DD_UVTH
V
fall
INIT Reset
& V > V
SUP
DD
start T_
Debug
mode
detection
IR
POWER DOWN
(T_ = 1.0 ms)
IR
T_
expired
INIT
V
fall
SUP
or V <V
_
DD UVTH
DD
watchdog refresh
by SPI
T_ expired
IR
INIT
start T_
FLASH
INIT
start T_
WDF
(T_
= 256ms)
INIT
(config)
SPI secured (3)
SPI secured (3)
Ext reset
SPI secured
or T_ expired
SPI write (0x5A00)
WDF
(watchdog refresh)
or V <V
_
DD
DD UVTH
NORMAL (4)
RESET
watchdog refresh
by SPI
start T_
WDN
start T_
R
(1.0 ms or config)
V
<V
_
or T_
expired
WD
DD
DD UVTH
(T_
= config)
WDN
or watchdog failure (1) or SPI secured
or VDD T
Wake-up
SD
SPI write (0x5A00)
(watchdog refresh)
T_ expired
NR
T_ expired
R
& V >V
_
DD UVTH
DD
NORMAL
REQUEST
SPI
start T_
(256 ms or config)
if enable
watchdog refresh
by SPI
NR
LP
VDD ON
Wake-up (5)
start T_
(2)
T_ expired
OC
WDL
or Wake-up
I- <I
DD OC
(1.5 mA)
I- >I
(1.5 mA)
DD OC
LP VDDON
IDD > 1.5 mA
V
<V
_
DD UVTHLP
start T_ time
DD
OC
T_
expired or V <V
DD
_
DD UVTHLP
WDL
SPI
LP
VDD OFF
FAIL-SAFE DETECTED
(1) watchdog refresh in closed window or enhanced watchdog refresh failure
(2) If enable by SPI, prior to enter LP V ON mode
DD
(3) Ref. to “SPI secure” description
(4) V external PNP is disable in all mode except Normal and Flash modes.
DD
(5) Wake-up from LP V ON mode by SPI command is done by a SPI mode change: 0X5C10
DD
Figure 23. State Diagram
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
41
FUNCTIONAL DEVICE OPERATION
MODE CHANGE
MODE CHANGE
- from Normal mode to Flash mode
“SECURED SPI” DESCRIPTION:
- from Normal mode to Reset mode (reset request).
A request is done by a SPI command, the device provide
on MISO an unpredictable “random code”. Software must
perform a logical change on the code and return it to the
device with the new SPI command to perform the desired
action.
“Random code” is also used when the “advance
watchdog” is selected.
CHANGING OF DEVICE CRITICAL PARAMETERS
The “random code” is different at every exercise of the
secured procedure and can be read back at any time.
Some critical parameters are configured one time at
device power on only, while the batfail flag is set in the INIT
mode. If a change is required while device is no longer in INIT
mode, device must be set back in INIT mode using the “SPI
secure” procedure.
The secured SPI uses the Special MODE register for the
following transitions:
- from Normal mode to INT mode
WATCHDOG OPERATION
If the watchdog is triggered before 50%, or not triggered
before end of period, a reset has occurred. The device enters
into Reset mode.
IN NORMAL REQUEST MODE
In Normal Request mode, the device expects to receive a
watchdog configuration before the end of the normal request
time out period. This period is reset to a long (256 ms) after
power on and when BATFAIL is set.
Watchdog in Debug Mode
When the device is in Debug mode (entered via the DBG
pin), the watchdog continues to operate but does not affect
the device operation by asserting a reset. For the user,
operation appears without the watchdog.
The device can be configured to a different (shorter) time
out period which can be used after Wake-up from LP VDD on
mode.
After a software watchdog reset, the value is restored to
256 ms, in order to allow for a complete software initialization,
similar to a device power up.
When Debug mode is set by software (SPI mode reg), the
watchdog period starts at the end of the SPI command.
When Debug mode is set by hardware (DBG pin below 8-
10 V), the device enters into Reset mode.
In Normal Request mode the watchdog operation is
“timeout” only and can be triggered/observed any time within
the period.
Watchdog in Flash Mode
WATCHDOG TYPE SELECTION
Three types of watchdog operation can be used:
- Window watchdog (default)
- Timeout operation
During Flash mode, watchdog can be set to a long timeout
period. Watchdog is timeout only and an INT pulse can be
generated at 50% of the time window.
Advance Watchdog Operation
- Advanced
When the Advance watchdog is selected (at INIT mode),
the refresh of the watchdog must be done using a random
number and with 1, 2, or 4 SPI commands. The number for
the SPI command is selected in INIT mode.
The selection of watchdog is performed in INIT mode. This
is done after device power up and when the BATFAIL flag is
set. The Watchdog configuration is done via the SPI, then the
Watchdog mode selection content is locked and can be
changed only via a secured SPI procedure.
The software must read a random byte from the device,
and then must return the random byte inverted to clear the
watchdog. The random byte write can be performed in 1, 2,
or 4 different SPI commands.
Window Watchdog Operation
The window watchdog is available in Normal mode only.
The watchdog period selection can be kept (SPI is selectable
in INIT mode), while the device enters into LP VDD ON mode.
The watchdog period is reset to the default long period after
BATFAIL.
If one command is selected, all eight bits are written at
once.
If two commands are selected, the first write command
must include four of the eight bits of the inverted random byte.
The second command must include the next four bits. This
completes the watchdog refresh.
The period and the refresh of watchdog are done by the
SPI. A refresh must be done in the open window of the
period, which starts at 50% of the selected period and ends
at the end of the period.
If four commands are selected, the first write command
must include two of the eight bits of the inverted random byte.
The second command must include the next two bits, the 3rd
command must include the next two, and the last command,
33903/4/5
Analog Integrated Circuit Device Data
42
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
WATCHDOG OPERATION
must include the last two. This completes the watchdog
refresh.
along with the next refresh command. It must be done in an
open window, if the Window operation was selected.
When multiple writes are used, the most significant bits are
sent first. The latest SPI command needs to be done inside
the open window time frame, if window watchdog is selected.
Advance Watchdog, Refresh by two SPI Commands:
The refresh command is split in two SPI commands.
The first partial refresh command is 0x5Aw1, and the
second is 0x5Aw2. Byte w1 contains the first four inverted
bits of the RD byte plus the last four bits equal to zero. Byte
w2 contains four bits equal to zero plus the last four inverted
bits of the RD byte.
DETAIL SPI OPERATION AND SPI COMMANDS
FOR ALL WATCHDOG TYPES.
All SPI commands and examples do not use parity
functions.
During this second refresh command the device returns on
MISO a new Random Code. This new random code must be
inverted and send along with the next two refresh commands
and so on.
In INIT mode, the watchdog type (window, timeout,
advance and number of SPI commands) is selected using the
register Init watchdog, bits 1, 2 and 3. The watchdog period
is selected using the TIM_A register. The watchdog period
selection can also be done in Normal mode or in Normal
Request mode.
The second command must be done in an open window if
the Window operation was selected.
Transition from INIT mode to Normal mode or from Normal
Request mode to Normal mode is done using a single
watchdog refresh command (SPI 0x 5A00).
Advance Watchdog, Refresh by four SPI Commands
The refresh command is split into four SPI commands.
While in Normal mode, the Watchdog Refresh Command
depends upon the watchdog type selected in INIT mode.
They are detailed in the paragraph below:
The first partial refresh command is 0x5Aw1, the second is
0x5Aw2, the third is 0x5Aw3, and the last is 0x5Aw4.
Byte w1 contains the first two inverted bits of the RD byte,
plus the last six bits equal to zero.
Simple Watchdog
Byte w2 contains two bits equal to zero, plus the next two
inverted bits of the RD byte, plus four bits equal to zero.
The Refresh command is 0x5A00. It can be send any time
within the watchdog period, if the timeout watchdog operation
is selected (INIT-watchdog register, bit 1 WD N/Win = 0). It
must be send in the open window (second half of the period)
if the Window Watchdog operation was selected (INIT-
watchdog register, bit 1 WD N/Win = 1).
Byte w3 contains four bits equal to zero, plus the next two
inverted bits of the RD byte, plus two bits equal to zero.
Byte w4 contains six bits equal to zero, plus the next two
inverted bits of the RD byte.
During this fourth refresh command, the device will return,
on MISO, a new Random Code. This new Random Code
must be inverted and send along with the next four refresh
commands.
Advance Watchdog
The first time the device enters into Normal mode (entry on
Normal mode using the 0x5A00 command), Random
(RNDM) code must be read using the SPI command,
0x1B00. The device returns on MISO second byte the RNDM
code. The full 16 bits MISO is called 0x XXRD. RD is the
complement of the RD byte.
The fourth command must be done in an open window if
the Window operation was selected.
PROPER RESPONSE TO INT
During a device detect upon an INT, the software handles
the INT in a timely manner: Access of the INT register is done
within two watchdog periods. This feature must be enabled
by SPI using the INIT watchdog register bit 7.
Advance Watchdog, Refresh by 1 SPI Command
The refresh command is 0x5ARD. During each refresh
command, the device will return on MISO, a new Random
Code. This new Random Code must be inverted and send
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
43
FUNCTIONAL DEVICE OPERATION
FUNCTIONAL BLOCK OPERATION VERSUS MODE
FUNCTIONAL BLOCK OPERATION VERSUS MODE
Table 8. Device Block Operation for Each State
State
V
5 V-CAN
I/O-X
V
CAN
LIN1/2
DD
AUX
Power down
Init Reset
OFF
ON
OFF
OFF
OFF
OFF
OFF
High-impedance
High-impedance
OFF:
HS/LS off
OFF:
Wake-up disable
CAN termination 25 k to GND
internal 30 k pull-up active.
Transmitter: receiver /
Wake-up OFF.
Transmitter / receiver /Wake-up
OFF
LIN term OFF
OFF
(34)
INIT
Reset
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
WU disable
(35)(36)(37)
Keep SPI config
Keep SPI config
OFF
OFF
WU disable
(35)(36)(37)
Normal Request
Normal
WU disable
(35)(36)(37)
ON
SPI config
OFF
SPI config
WU SPI config
user defined
WU SPI config
user defined
WU SPI config
HS/LS off
SPI config
OFF
SPI config
SPI config
LP V OFF
OFF
OFF + Wake-up en/dis
OFF + Wake-up en/dis
OFF + Wake-up enable
OFF + Wake-up en/dis
OFF + Wake-up en/dis
OFF + Wake-up enable
DD
(33)
LP V ON
DD
ON
OFF
OFF
SAFE output low:
Safe case A
safe case
A:ON
A: Keep SPI
config, B: OFF
OFF
Wake-upbychange
state
safe case B:
OFF
FLASH
ON
SPI config
SPI config
OFF
SPI config
OFF
Notes
33. With limited current capability
34. 5 V-CAN is ON in Debug mode.
35. I/O-0 and I/O-1, configured as an output high-side switch and ON in Normal mode will remain ON in RESET, INIT or Normal
Request.
36. I/O-0, configured as an output low-side switch and ON in Normal mode will turn OFF when entering Reset mode, resume
operation in Normal mode.
37. I/O-1, configured as an output low-side switch and ON in Normal mode will remain ON in RESET, INIT or Normal Request.
The 5 V-CAN default is ON when the device is powered-up and set in Debug mode. It is fully controllable via the SPI command.
33903/4/5
Analog Integrated Circuit Device Data
44
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
ILLUSTRATION OF DEVICE MODE TRANSITIONS.
ILLUSTRATION OF DEVICE MODE TRANSITIONS.
Normal to LP
ON Mode
Normal to LP
OFF Mode
Power up to Normal Mode
V
DD
A
V
D
B
C
B
B
DD
V
V
V
>4.0 V
SUP
SUP
SUP
V
V
(4.5 V typically)
DD-UV
DD-UV
V
V
V
DD
DD
DD
5V-CAN
VAUX
RST
5V-CAN
VAUX
5V-CAN
VAUX
RST
RST
INT
SPI
INT
SPI
INT
SPI
NORMAL
LP VDD On
NORMAL
MODE
NORMAL
LP VDD OFF
RESET
INIT
BATFAIL
s_2: go to LP V
OFF mode
s_1: go to Normal mode
s_11: write INT registers
s_3: go to LP mode
s_13: LP Mode configuration
DD
s_12: LP Mode configuration
legend:
Series of SPI
Single SPI
Figure 24. Power Up Normal and LP Modes
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
45
FUNCTIONAL DEVICE OPERATION
ILLUSTRATION OF DEVICE MODE TRANSITIONS.
Wake-up from LP V ON Mode
DD
Wake-up from LP V OFF Mode
D
C
DD
V
V
SUP
SUP
V
(4.5 V typically)
DD-UV
V
V
DD
DD
Based on reg configuration
Based on reg configuration
Based on reg configuration
Based on reg configuration
5V-CAN
VAUX
5V-CAN
VAUX
RST
RST
INT
SPI
INT
SPI
NORMAL
REQUEST
NORMAL
REQUEST
LP V _OFF
DD
MODE
MODE
RESET
NORMAL
LP V ON
NORMAL
DD
CAN bus
LIN Bus
CAN bus
LIN Bus
CAN Wake-up
pattern
CAN Wake-up
pattern
LIN Wake-up filter
LIN Wake-up filter
I/O-x toggle
FWU timer
I/O-x toggle
FWU timer
.
Start
Stop
Start
FWU timer
FWU timer
duration (50-8192 ms)
SPI selectable
duration (50-8192 ms)
SPI selectable
I
current
SPI
I
(3.0 mA typically)
DD-OC
DD
Wake-up detected
I
deglitcher or timer (100 us typically, 3 -32 ms)
Wake-up detected
D OC
Figure 25. Wake-up from LP Modes
33903/4/5
Analog Integrated Circuit Device Data
46
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
CYCLIC SENSE OPERATION DURING LP MODES
CYCLIC SENSE OPERATION DURING LP MODES
This function can be used in both LP modes: VDD OFF and
VDD ON.
transistor can be activated. The selection is done by the state
of I/O-0 prior to entering in LP mode.
Cyclic sense is the periodic activation of I/O-0 to allow
biasing of external contact switches. The contact switch state
can be detected via I/O-1, -2, and -3, and the device can
Wake-up from either LP mode.
During the T-CSON duration, the I/O-x’s are monitored. If
one of them is high, the device will detect a Wake-up.
(Figure 26).
Cyclic sense period is selected by the SPI configuration
prior to entering LP mode. Upon entering LP mode, the I/O-0
should be activated.
Cyclic sense is optimized and designed primarily for
closed contact switch in order to minimize consumption via
the contact pull-up resistor.
The level of I/O-1 is sense during the I/O-0 active time, and
is deglitched for a duration of typically 30 s. This means that
I/O-1 should be in the expected state for a duration longer
than the deglitch time.
Principle
A dedicated timer provides an opportunity to select a cyclic
sense period from 3.0 to 512 ms (selection in timer B).
The diagram below (Figure 26) illustrates the cyclic sense
operation, with I/O-0 HS active and I/O-1 Wake-up at high
level.
At the end of the period, the I/O-0 will be activated for a
duration of T_CSON (SPI selectable in INIT register, to 200 s,
400 s, 800 s, or 1.6 ms). The I/O-0 HS transistor or LS
I/O-0 HS active in Normal mode
I/O-0 HS active during cyclic sense active time
I/O-0
Zoom
S1
S1 closed
S1 open
Cyclic sense active
time (ex 200 us)
I/O-1
I/O-0
I/O-1 high => Wake-up
I/O-1
Cyclic sense period
state of I/O-1 low => no Wake-up
I/O-1 deglitcher time
(typically 30 us)
Cyclic sense active time
Wake-up event detected
NORMAL MODE
LP MODE
RESET or NORMAL REQUEST MODE
Wake-up detected.
R
R
R
R
R
R
I/O-0
I/O-0
I/O-1
I/O-1
I/O-2
I/O-3
S1
S1
I/O-2
I/O-3
S2
S2
S3
S3
Upon entering in LP mode, all 3
contact switches are closed.
In LP mode, 1 contact switch is open.
High level is detected on I/O-x, and device wakes up.
Figure 26. Cyclic Sense Operation - Switch to GND, Wake-up by Open Switch
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
47
FUNCTIONAL DEVICE OPERATION
CYCLIC INT OPERATION DURING LP VDD ON MODE
CYCLIC INT OPERATION DURING LP VDD ON MODE
Principle
This function can be used only in LP VDD ON mode (LP
VDD ON).
When Cyclic INT is selected and device is in LP VDD ON
SPI commands to acknowledge INT: (2 commands)
- read the Random code via the watchdog register address
using the following command: MOSI 0x1B00 device report on
MISO second byte the RNDM code (MISO bit 0-7).
- write watchdog refresh command using the random code
inverted: 0x5A RNDb.
mode, the device will generate a periodic INT pulse.
Upon reception of the INT pulse, the MCU must
acknowledge the INT by sending SPI commands before the
end of the next INT period in order to keep the process going.
These commands can occur at any time within the period.
Initial entry in LP mode with Cyclic INT: after the device is
set in LP VDD ON mode, with cyclic INT enable, no SPI
command is necessary until the first INT pulse occurs. The
acknowledge process must start only after the 1st INT pulse.
When Cyclic INT is selected and operating, the device
remains in LP VDD ON mode, assuming the SPI commands
are issued properly. When no/improper SPI commands are
sent, the device will cease Cyclic INT operation and leave LP
VDD ON mode by issuing a reset. The device will then enter
into Normal Request mode.
Leave LP mode with Cyclic INT:
This is done by a SPI Wake-up command, similar to SPI
Wake-up from LP VDD ON mode: 0x5C10. The device will
enter into Normal Request mode.
VDD current capability and VDD regulator behavior is
similar as in LP VDD ON mode.
Improper SPI command while Cyclic INT operates:
When no/improper SPI commands are sent, while the
device is in LP VDD ON mode with Cyclic INT enable, the
device will cease Cyclic INT operation and leave LP VDD ON
mode by issuing a reset. The device will then enter into
Normal Request mode.
Operation
Cyclic INT period selection: register timer B
SPI command in hex 0x56xx [example; 0x560E for 512ms
cyclic Interrupt period (SPI command without parity bit)].
The figure below (Figure 27) describes the complete
Cyclic Interrupt operation.
This command must be send while the device is in Normal
mode.
Prepare LP V
with Cyclic INT
ON
Leave LP
ON Mode
DD
In LP V
DD
ON with Cyclic INT
V
DD
INT
LP V
ON mode
DD
SPI
Timer B
Cyclic INT period
1st period
Cyclic INT period
3rd period
Cyclic INT period
2nd period
Cyclic INT period
NORMAL
REQUEST
MODE
NORMAL MODE
LP V
ON MODE
DD
Legend for SPI commands
Write Timer B, select Cyclic INT period (ex: 512 ms, 0x560E)
Leave LP V
ON and Cyclic INT due to improper operation
DD
INT
Write Device mode: LP V
ON with Cyclic INT enable (example: 0x5C90)
DD
Improper or no
acknowledge SPI command
Read RNDM code
SPI
Write RNDM code inv.
SPI Wake-up: 0x5C10
RST
Cyclic INT period
RESET and
NORMAL
REQUEST
MODE
LP V
ON MODE
DD
Figure 27. Cyclic Interrupt Operation
33903/4/5
Analog Integrated Circuit Device Data
48
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
BEHAVIOR AT POWER UP AND POWER DOWN
BEHAVIOR AT POWER UP AND POWER DOWN
The figures below illustrate the device behavior during
VSUP/1 ramp up. As the Crank bit is by default set to 0, VDD is
enabled when VSUP/1 is above VSUP TH 1 parameters.
DEVICE POWER UP
This section describe the device behavior during ramp up,
and ramp down of VSUP/1, and the flexibility offered mainly by
the Crank bit and the two VDD under-voltage reset thresholds.
V
(ex 12 V)
SUP_NOMINAL
V
(ex 5.0 V)
DD NOMINAL
V
slew rate
SUP
VBAT
V
(typically 4.65 V)
DD_UV TH
D1
V
VSUP/1
VDD
SUP_TH1
3390X
V
DD_START UP
90% V
I_VDD
DD_START UP
VSUP/1
Gnd
10% V
DD_OFF
DD_START UP
VDD
RST
V
1.0 ms
Figure 28. VDD Start-up Versus VSUP/1 Tramp
(VDD < 4.6 V or VDD < 3.2 V typically, threshold selected by
the SPI). When device is in Reset, if VSUP/1 is below
“VSUP_TH1”, VDD is turned OFF.
DEVICE POWER DOWN
The figures below illustrate the device behavior during
VSUP/1 ramp down, based on Crank bit configuration, and
VDD under-voltage reset selection.
Crank Bit Set (INIT Watchdog Register, Bit 0 =1)
Crank Bit Reset (INIT Watchdog Register, Bit 0 =0)
The bit 0 is set by SPI write. During VSUP/1 ramp down,
VDD remains ON until device detects a POR and set
BATFAIL. This occurs for a VSUP/1 approx 3.0 V.
Bit 0 = 0 is the default state for this bit.
During VSUP/1 ramp down, VDD remain ON until device
enters in Reset mode due to a VDD under-voltage condition
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49
FUNCTIONAL DEVICE OPERATION
BEHAVIOR AT POWER UP AND POWER DOWN
V
V
BAT
BAT
V
V
SUP_NOMINAL
(ex 12 V)
SUP_NOMINAL
(ex 12 V)
VSUP/1
VSUP/1
V
(5.0 V)
V
(5.0 V)
DD
DD
V
(4.1 V)
SUP_TH1
V
(typically 4.65 V)
V
(typically 4.65 V)
DD_UV TH
DD_UV TH
BATFAIL (3.0 V)
VDD
VDD
RST
RST
Case 1: “VDD UV TH 4.6V”, with bit Crank = 0 (default value)
Case 2: “VDD UV 4.6V”, with bit Crank = 1
V
V
BAT
BAT
V
V
SUP_NOMINAL
(ex 12 V)
SUP_NOMINAL
(ex 12 V)
VSUP/1
VSUP/1
V
(4.1 V)
SUP_TH1
V
(5.0 V)
V
(5.0 V)
DD
DD
V
(typically 4.65 V)
V
(typically 4.65 V)
BATFAIL (3.0 V)
DD_UV TH
DD_UV TH
VDD
VDD
V
(typically 3.2 V)
V
(typically 3.2 V)
DD_UV TH2
DD_UV TH2
(2)
INT
INT
RST
RST
(1)
(1) reset then (2) V turn OFF
DD
Case 2: “VDD UV 3.2V”, with bit Crank = 1
Case 1: “VDD UV TH 3.2V”, with bit Crank = 0 (default value)
Figure 29. VDD Behavior During VSUP/1 Ramp Down
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50
FAIL-SAFE OPERATION
BEHAVIOR AT POWER UP AND POWER DOWN
FAIL-SAFE OPERATION
to properly control the device and properly refresh the
watchdog).
OVERVIEW
Fail-safe mode is entered when specific fail conditions
occur. The “Safe state” condition is defined by the resistor
connected at the DGB pin. Safe mode is entered after
additional event or conditions are met: time out for CAN
communication and state at I/O-1 pin.
Modes B1, B2 and B3
Upon SAFE activation, the system continues to monitor
external event, and disable the MCU supply (turn VDD OFF).
The external events monitored are: CAN traffic, I/O-1 low
level or both of them. 3 sub cases exist, B1, B2 and B3.
Note: no CAN traffic indicates that the ECU of the vehicle
are no longer active, thus that the car is being parked and
stopped. The I/O low level detection can also indicate that the
vehicle is being shutdown, if the I/O-1 pin is connected for
instance to a switched battery signal (ignition key on/off
signal).
The selection of the monitored events is done by
hardware, via the resistor connected at DBG pin, but can be
over written by software, via a specific SPI command.
By default, after power up the device detect the resistor
value at DBG pin (upon transition from INIT to Normal mode),
and, if no specific SPI command related to Debug resistor
change is send, operates according to the detected resistor.
The INIT MISC register allow you to verify and change the
device behavior, to either confirm or change the hardware
selected behavior. Device will then operate according to the
SAFE mode configured by the SPI.
Exiting the safe state is always possible by a Wake-up
event: in the safe state, the device can automatically be
awakened by CAN and I/O (if configured as inputs). Upon
Wake-up, the device operation is resumed: enter in Reset
mode.
FAIL-SAFE FUNCTIONALITY
Upon dedicated event or issue detected at a device pin
(i.e. RST short to VDD), the Safe mode can be entered. In
this mode, the SAFE pin is active low.
Description
Upon activation of the SAFE pin, and if the failure
condition that make the SAFE pin activated have not
recovered, the device can help to reduce ECU consumption,
assuming that the MCU is not able to set the whole ECU in LP
mode. Two main cases are available:
Mode A
Table 9 illustrates the complete options available:
Upon SAFE activation, the MCU remains powered (VDD
stays ON), until the failure condition recovers (i.e. S/W is able
Table 9. Fail-safe Options
Resistor at
SPI coding - register INIT MISC bits [2,1,0]
DBG pin
Safe mode
code
V
status
DD
(higher priority that Resistor coding)
bits [2,1,0) = [111]: verification enable: resistor at DBG pin is typically
<6.0 k
A
remains ON
0 kohm (RA) - Selection of SAFE mode A
typically 15 k bits [2,1,0) = [110]: verification enable: resistor at DBG pin is typically
15 kohm (RB1) - Selection of SAFE mode B1
B1
Turn OFF 8.0 s after CAN traffic bus idle detection.
typically 33 k bits [2,1,0) = [101]: verification enable: resistor at DBG pin is typically
33 kohm (RB2 - Selection of SAFE mode B2
B2
B3
Turn OFF when I/O-1 low level detected.
typically 68 k bits [2,1,0) = [100]: verification enable: resistor at DBG pin is typically
68 kohm (RB3) - Selection of SAFE mode B3
Turn OFF 8.0 s after CAN traffic bus idle detection
AND when I/O-1 low level detected.
Exit of Safe Mode
Wake-up, the device operation is resumed, and device enters
in Reset mode. The SAFE pin remains active, until there is a
proper read and clear of the SPI flags reporting the SAFE
conditions.
Exit of the safe state with VDD OFF is always possible by
a Wake-up event: in this safe state the device can
automatically awakened by CAN and I/O (if I/O Wake-up was
enable by the SPI prior to enter into SAFE mode). Upon
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51
FAIL-SAFE OPERATION
BEHAVIOR AT POWER UP AND POWER DOWN
.
SAFE Operation Flow Chart
Legend:
Failure events
Device state:
RESET
NR
RESET
detection of 2nd
bit 4, INIT watchdog = 1 (1)
bit 4, INIT watchdog = 0 (1)
consecutive watchdog failure
SAFE high
SAFE low
Reset: 1.0 ms pulse
Reset: 1.0 ms pulse
(6)
SAFE low
8 consecutive watchdog failure (5
- SAFE low
- V ON
- Reset: 1.0 ms
periodic pulse
DD
State A: R
watchdog failure
<6.0 k AND
DBG
SAFE pin release
(SAFE high)
a) Evaluation of
watchdog failure
State A: R <6.0 k AND
Resistor detected
at DBG pin during
power up, or SPI
DBG
- SAFE low
(V low or R s/c GND) failure
DD
ST
- V ON
DD
SPI (3)
- Reset low
V
low:
<V
DD
State B1: R
= 15 k AND
DBG
register content
V
_
Bus idle timeout expired
DD
DD UVTH
INIT,
Normal Request
Normal, FLASH
State B2:
b) ECU external signal
monitoring (7):
- Reset low
- SAFE low
- Reset low
- V OFF
DD
R
= 33 k AND I/O-1 low
DBG
- SAFE low
- bus idle time out
- I/O-1 monitoring
State B3:
- V ON
DD
R
=
DBG 47 k AND I/O-1 low
Rst s/c GND:
Rst <2.5 V, t >100 ms
AND Bus idle time out expired
Wake-up (2), V ON, SAFE pin remains low
DD
RESET
failure recovery, SAFE pin remains low
1) bit 4 of INIT Watchdog register
2) Wake-up event: CAN, LIN or I/O-1 high level (if I/O-1 Wake-up previously enabled)
3) SPI commands: 0xDD00 or 0xDD80 to release SAFE pin
4) Recovery: reset low condition released, V low condition released, correct SPI watchdog refresh
DD
5) detection of 8 consecutive watchdog failures: no correct SPI watchdog refresh command occurred for duration of 8 x 256 ms.
6) Dynamic behavior: 1.0 ms reset pulse every 256 ms, due to no watchdog refresh SPI command, and device state transition
between RESET and NORMAL REQUEST mode, or INIT RESET and INIT modes.
7) 8 second timer for bus idle timeout. I/O-1 high to low transition.
Figure 30. Safe Operation Flow Chart
Conditions to Set SAFE Pin Active Low
VDD low: VDD < RST-TH. SAFE pin is set low at the same
time as the RST pin is set low.
Watchdog refresh issue: SAFE activated at 1st reset pulse
or at the second consecutive reset pulse (selected by bit 4,
INIT watchdog register).
The RST pin is monitored to verify that reset is not
clamped to a low level preventing the MCU to operate. If this
is the case, the Safe mode is entered.
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52
Freescale Semiconductor
FAIL-SAFE OPERATION
BEHAVIOR AT POWER UP AND POWER DOWN
SAFE Mode A Illustration
Figure 31 illustrates the event and consequences when SAFE mode A is selected via the appropriate debug resistor or SPI
configuration.
Behavior Illustration for Safe State A (R < 6.0 kohm), or Selection by the SPI
DG
step 2: Consequence on
step 1: Failure illustration
V
, RST and SAFE
DD
V
DD
V
DD
failure event, i.e. watchdog
8th
2nd
1st
RST
SAFE
RST
SAFE
ON state
OFF state
8 x 256 ms delay time to enter in SAFE mode
to evaluate resistor at DBG pin
and monitor ECU external events
failure event, V low
DD
V
DD_UV TH
V
V
V
<
DD
DD_UV TH
DD
V
DD
GND
GND
RST
RST
SAFE
ON state
OFF state
SAFE
100ms
100 ms delay time to enter in SAFE mode
to evaluate resistor at DBG pin
and monitor ECU external events
failure event, Reset s/c GND
V
DD
V
DD
RST
2.5 V
RST
SAFE
ON state
OFF state
SAFE
100ms
100 ms deglitcher time to activate SAFE and
enter in SAFE mode to evaluate resistor at the DBG pin
and monitor ECU external events
Figure 31. SAFE Mode A Behavior Illustration
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53
FAIL-SAFE OPERATION
BEHAVIOR AT POWER UP AND POWER DOWN
SAFE Mode B1, B2 and B3 Illustration
Figure 32 illustrates the event, and consequences when SAFE mode B1, B2, or B3 is selected via the appropriate debug
resistor or SPI configuration.
Behavior illustration for the safe state B (RDG > 10 kohm)
CAN bus
DBG resistor => safe state B1
step 2:
CAN bus idle time
Exclusive detection of
ECU external event to
disable VDD based on
I/O-1
I/O-1 high to low transition
DBG resistor => safe state B2
RDBG resistor or
SPI configuration
CAN bus
DBG resistor => safe state B3
CAN bus idle time
I/O-1
I/O-1 high to low transition
step 1: Failure illustration
Consequences for V
step 3:
DD
VDD
VDD
failure event, i.e. watchdog
8th
2nd
1st
RST
RST
SAFE
ON state
OFF state
SAFE
8 x 256 ms delay time to enter in SAFE mode
to evaluate resistor at the DBG pin
and monitor ECU external events
failure event, VDD low
If VDD failure recovered
VDD
GND
VDD < VDD_UV TH
VDD_UV TH
VDD
GND
VDD OFF
RST
RST
SAFE
SAFE
ON state
OFF state
100 ms
100 ms delay time to enter in SAFE mode
to evaluate resistor at DBG pin
and monitor ECU external events
If Reset s/c GND recovered
VDD OFF
failure event, Reset s/c GND
VDD
VDD
2.5 V
RST
RST
SAFE
ON state
OFF state
SAFE
100 ms
100 ms deglitcher time to activate SAFE and
enter in SAFE mode to evaluate resistor at DBG pin
and monitor ECU external events
Figure 32. SAFE Modes B1, B2, or B3 Behavior Illustration
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Analog Integrated Circuit Device Data
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54
CAN INTERFACE
CAN INTERFACE DESCRIPTION
CAN INTERFACE
CAN INTERFACE DESCRIPTION
The figure below is a high level schematic of the CAN
interface. It exist in a LS driver between CANL and GND, and
a HS driver from CANH to 5 V-CAN. Two differential
receivers are connected between CANH and CANL to detect
a bus state and to Wake-up from CAN Sleep mode. An
internal 2.5 V reference provides the 2.5 V recessive levels
via the matched RIN resistors. The resistors can be switched
to GND in CAN Sleep mode. A dedicated split buffer provides
a low-impedance 2.5 V to the SPLIT pin, for recessive level
stabilization.
VSUP/2
Pattern
Detection
Wake-up
Receiver
SPI & State machine
5 V-CAN
Driver
QH
R
IN
2.5 V
CANH
CANL
Differential
Receiver
RXD
R
IN
5 V-CAN
TXD
Driver
QL
Thermal
SPI & State machine
SPI & State machine
5 V-CAN
Failure Detection
& Management
Buffer
SPLIT
Figure 33. CAN Interface Block Diagram
Can Interface Supply
The 5 V-CAN regulator must be ON. It supplies the CAN
driver and receiver.The SPLIT pin is active and a 2.5 V
biasing is provided on the SPLIT output pin.
The supply voltage for the CAN driver is the 5 V-CAN pin.
The CAN interface also has a supply pass from the battery
line through the VSUP/2 pin. This pass is used in CAN Sleep
mode to allow Wake-up detection.
Receive Only Mode
This mode is used to disable the CAN driver, but leave the
CAN receiver active. In this mode, the device is only able to
report the CAN state on the RXD pin. The TXD pin has no
effect on CAN bus lines. The 5 V-CAN regulator must be ON.
The SPLIT pin is active and a 2.5 V biasing is provided on the
SPLIT output pin.
During CAN communication (transmission and reception),
the CAN interface current is sourced from the 5 V-CAN pin.
During CAN LP mode, the current is sourced from the VSUP/
2 pin.
TXD/RXD Mode
In TXD/RXD mode, both the CAN driver and the receiver
are ON. In this mode, the CAN lines are controlled by the TXD
pin level and the CAN bus state is reported on the RXD pin.
Operation in TXD/RXD Mode
The CAN driver will be enabled as soon as the device is in
Normal mode and the TXD pin is recessive.
33903/4/5
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Freescale Semiconductor
55
CAN INTERFACE
CAN INTERFACE DESCRIPTION
When the CAN interface is in Normal mode, the driver has
two states: recessive or dominant. The driver state is
controlled by the TXD pin. The bus state is reported through
the RXD pin.
to the bus and from the bus to the RXD. The loop time is thus
affected by the slew rate selection.
Minimum Baud Rate
When TXD is high, the driver is set in the recessive state,
and CANH and CANL lines are biased to the voltage set with
5 V-CAN divided by 2, or approx. 2.5 V.
The minimum baud rate is determined by the shortest TXD
permanent dominant timing detection. The maximum number
of consecutive dominant bits in a frame is 12 (6 bits of active
error flag and its echo error flag).
When TXD is low, the bus is set into the dominant state,
and CANL and CANH drivers are active. CANL is pulled low
and CANH is pulled high.
The shortest TXD dominant detection time of 300 s lead
to a single bit time of: 300 s / 12 = 25 s.
The RXD pin reports the bus state: CANH minus the CANL
voltage is compared versus an internal threshold (a few
hundred mV).
So the minimum Baud rate is 1 / 25 s = 40 kBaud.
Sleep Mode
If “CANH minus CANL” is below the threshold, the bus is
recessive and RXD is set high.
Sleep mode is a reduced current consumption mode.
CANH and CANL drivers are disabled and CANH and CANL
lines are terminated to GND via the RIN resistor, the SPLIT
pin is high-impedance. In order to monitor bus activities, the
CAN Wake-up receiver can be enabled. It is supplied
If “CANH minus CANL” is above the threshold, the bus is
dominant and RXD is set low.
The SPLIT pin is active and provides a 2.5 V biasing to the
SPLIT output.
internally from VSUP/2
.
Wake-up events occurring on the CAN bus pin are
reporting by dedicated flags in SPI and by INT pulse, and
results in a device Wake-up if the device was in LP mode.
TXD/RXD Mode and Slew Rate Selection
The CAN signal slew rate selection is done via the SPI. By
default and if no SPI is used, the device is in the fastest slew
rate. Three slew rates are available. The slew rate controls
the recessive to dominant, and dominant to recessive
transitions. This also affects the delay time from the TXD pin
.
When the device is set back into Normal mode, CANH and
CANL are set back into the recessive level. This is illustrated
in Figure 34.
TXD
Dominant state
CANH-DOM
Recessive state
CANH
CANL
CANL/CANH-REC
CANH-CANL
2.5 V
CANL-DOM
High ohmic termination (50 kohm) to GND
High-impedance
RXD
2.5 V
SPLIT
Bus Driver
Receiver
(bus dominant set by other IC)
Go to sleep,
Normal or Listen Only mode
Sleep or Stand-by mode
Normal or Listen Only mode
Figure 34. Bus Signal in TXD/RXD and LP Mode
Wake-up
up is a pattern Wake-up. The Wake-up by the CAN is enabled
or disabled via the SPI.
When the CAN interface is in Sleep mode with Wake-up
enabled, the CAN bus traffic is detected. The CAN bus Wake-
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Analog Integrated Circuit Device Data
56
Freescale Semiconductor
CAN INTERFACE
CAN INTERFACE DESCRIPTION
CAN
bus
CANH
CANL
Dominant
Pulse # 2
Dominant
Pulse # 1
Internal differential Wake-up receiver signal
Internal Wake-up signal
Can Wake-up detected
t
CAN WU1-F
Figure 35. Single Dominant Pulse Wake-up
Pattern Wake-up
A valid dominant pulse should be longer than 500 ns. The
three pulses should occur in a time frame of 120 s, to be
considered valid. When three pulses meet these conditions,
the wake signal is detected. This is illustrated by the following
figure.
In order to Wake-up the CAN interface, the Wake-up
receiver must receive a series of three consecutive valid
dominant pulses, by default when the CANWU bit is low.
CANWU bit can be set high by SPI and the Wake-up will occur
after a single pulse duration of 2.0 s (typically).
.
CAN
bus
CANH
Dominant
Pulse # 3
Dominant
Pulse # 2
Dominant
Pulse # 4
Dominant
Pulse # 1
CANL
Internal differential Wake-up receiver signal
Internal Wake-up signal
Can Wake-up detected
t
t
t
CAN WU3-F
CAN WU3-F
CAN WU3-F
t
CAN WU3-TO
Dominant Pulse # n: duration 1 or multiple dominant bits
Figure 36. Pattern Wake-up - Multiple Dominant Detection
• SPLIT termination concept, with the mid point of the
BUS TERMINATION
differential termination connected to GND through a
capacitor and to the SPLIT pin.
• In application, the device can also be used without
termination.
• Figure 37 illustrates some of the most common
terminations.
The device supports the two main types of bus
terminations:
• Differential termination resistors between CANH and
CANL lines.
33903/4/5
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57
CAN INTERFACE
CAN BUS FAULT DIAGNOSTIC
CANH
CANH
SPLIT
CANL
No
connect
No
connect
SPLIT
120
CAN bus
CAN bus
CANL
ECU connector
ECU connector
No termination
Standard termination
CANH
SPLIT
CANL
60
60
CAN bus
ECU connector
Figure 37. Bus Termination Options
CAN BUS FAULT DIAGNOSTIC
The device includes diagnostic of bus short-circuit to GND,
VBAT, and internal ECU 5.0 V. Several comparators are
implemented on CANH and CANL lines. These comparators
monitor the bus level in the recessive and dominant states.
The information is then managed by a logic circuitry to
properly determine the failure and report it.
Vr5
H5
V
(12-14 V)
-2.0 V)
BAT
(V
Vrvb
V
Hb
DD
V
RVB SUP
Vrg
TXD
Diag
Hg
Lg
CANH
CANL
V
(5.0 V)
(V -.43 V)
DD
Logic
V
R5 DD
CANH dominant level (3.6 V)
Vrg
Lb
Recessive level (2.5 V)
Vrvb
V
(1.75 V)
RG
L5
CANL dominant level (1.4 V)
GND (0.0 V)
Vr5
Figure 38. CAN Bus Simplified Structure Truth Table for Failure Detection
The following table indicates the state of the comparators when there is a bus failure, and depending upon the driver state.
Table 10. Failure Detection Truth Table
Driver Recessive State
Driver Dominant State
Failure Description
Lg (threshold 1.75 V)
Hg (threshold 1.75 V)
Lg (threshold 1.75 V)
Hg (threshold 1.75 V)
No failure
1
1
0
0
0
1
1
0
CANL to GND
CANH to GND
0
0
0
0
Lb (threshold V
-2.0 V)
Hb (threshold V
-2.0 V)
Lb (threshold V
-2.0 V)
Hb (threshold V
-2.0 V)
SUP
SUP
SUP
SUP
No failure
0
1
1
0
1
1
0
1
0
0
1
1
CANL to VBAT
CANH to VBAT
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Analog Integrated Circuit Device Data
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Freescale Semiconductor
CAN INTERFACE
CAN BUS FAULT DIAGNOSTIC
Table 10. Failure Detection Truth Table
Driver Recessive State
Lg (threshold 1.75 V) Hg (threshold 1.75 V)
Driver Dominant State
Lg (threshold 1.75 V) Hg (threshold 1.75 V)
Failure Description
L5 (threshold V -0.43 V)
DD
H5 (threshold V -0.43 V)
DD
L5 (threshold V -0.43 V)
DD
H5 (threshold V -0.43 V)
DD
No failure
0
1
1
0
1
1
0
1
0
0
1
1
CANL to 5.0 V
CANH to 5.0 V
This condition could occur when the CANH line is shorted
DETECTION PRINCIPLE
to a high-voltage. In this case, current will flow from the high-
voltage short-circuit, through the bus termination resistors
(60 ), into the SPLIT pin (if used), and into the device CANH
and CANL input resistors, which are terminated to internal
2.5 V biasing or to GND (Sleep mode).
In the recessive state, if one of the two bus lines are
shorted to GND, VDD (5.0 V), or VBAT, the voltage at the
other line follows the shorted line, due to the bus termination
resistance. For example: if CANL is shorted to GND, the
CANL voltage is zero, the CANH voltage measured by the Hg
comparator is also close to zero.
Depending upon the high-voltage short-circuit, the number
of nodes, usage of the SPLIT pin, RIN actual resistor and
mode state (Sleep or Active) the voltage across the bus
termination can be sufficient to create a positive dominant
voltage between CANH and CANL, and the RXD pin will be
low. This would prevent start of any CAN communication and
thus, proper failure identification requires five pulses on TXD.
The bus dominant clamp circuit will help to determine such
failure situation.
In the recessive state, the failure detection to GND or
VBAT is possible. However, it is not possible with the above
implementation to distinguish which of the CANL or CANH
lines are shorted to GND or VBAT. A complete diagnostic is
possible once the driver is turned on, and in the dominant
state.
Number of Samples for Proper Failure Detection
The failure detector requires at least one cycle of the
recessive and dominant states to properly recognize the bus
failure. The error will be fully detected after five cycles of the
recessive-dominant states. As long as the failure detection
circuitry has not detected the same error for five recessive-
dominant cycles, the error is not reported.
RXD Permanent Recessive Failure (does not apply
to “C version”)
The aim of this detection is to diagnose an external
hardware failure at the RXD output pin and ensure that a
permanent failure at RXD does not disturb the network
communication. If RXD is shorted to a logic high signal, the
CAN protocol module within the MCU will not recognize any
incoming message. In addition, it will not be able to easily
distinguish the bus idle state and can start communication at
any time. In order to prevent this, RXD failure detection is
necessary. When a failure is detected, the RXD high flag is
set and CAN switches to receive only mode.
BUS CLAMPING DETECTION
If the bus is detected to be in dominant for a time longer
than (TDOM), the bus failure flag is set and the error is
reported in the SPI.
TXD
CANL&H
Diag
TXD driver
Logic
Diff output
V
/2
DD
Sampling
Sampling
V
DD
Rxsense
V
DD
RXD short to V
DD
RXD output
RXD
CANH
CANL
RXD flag latched
RXD driver Diff
60
RXD flag
Prop delay
The RXD flag is not the RXPR bit in the LPC register, and neither is the CANF in the INTR register.
Figure 39. RXD Path Simplified Schematic, RXD Short to VDD Detection
Implementation for Detection
external short to VDD at the RXD output, RXD will be tied to
a high level and can be detected at the next low to high
transition of the differential receiver.
The implementation senses the RXD output voltage at
each low to high transition of the differential receiver.
Excluding the internal propagation delay, the RXD output
should be low when the differential receiver is low. When an
As soon as the RXD permanent recessive is detected, the
RXD driver is deactivated.
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59
CAN INTERFACE
CAN BUS FAULT DIAGNOSTIC
Once the error is detected the driver is disabled and the
error is reported via SPI in CAN register.
Recovery Condition
The internal recovery is done by sampling a correct low
level at TXD as shown in the following illustration.
CANL&H
Diff output
Sampling
Sampling
RXD short to V
DD
RXD output
RXD flag
RXD no longer shorted to V
DD
RXD flag latched
The RXD flag is not the RXPR bit in the LPC register, and neither is the CANF in the INTR register.
Figure 40. RXD Path Simplified Schematic, RXD Short to VDD Detection
low and drives CANH and CANL into a dominant state. Thus
the bus is stuck in dominant. No further communication is
possible.
TXD PERMANENT DOMINANT
Principle
If the TXD is set to a permanent low level, the CAN bus is
set into dominant level, and no communication is possible.
The device has a TXD permanent timeout detector. After the
timeout (TDOUT), the bus driver is disabled and the bus is
released into a recessive state. The TXD permanent flag is
set.
Detection and Recovery
The TXD permanent dominant timeout will be activated and
release the CANL and CANH drivers. However, at the next
incoming dominant bit, the bus will then be stuck in dominant
again. The recovery condition is same as the TXD dominant
failure
Recovery
The TXD permanent dominant is used and activated when
there is a TXD short to RXD. The recovery condition for a
TXD permanent dominant (recovery means the re-activation
of the CAN drivers) is done by entering into a Normal mode
controlled by the MCU or when TXD is recessive while RXD
change from recessive to dominant.
IMPORTANT INFORMATION FOR BUS DRIVER
REACTIVATION
The driver stays disabled until the failure is/are removed
(TXD and/or RXD is no longer permanent dominant or
recessive state or shorted) and the failure flags cleared
(read). The CAN driver must be set by SPI in TXD/RXD mode
in order to re enable the CAN bus driver.
TXD TO RXD SHORT-CIRCUIT
Principle
When TXD is shorted to RXD during incoming dominant
information, RXD is set to low. Consequently, the TXD pin is
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Analog Integrated Circuit Device Data
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Freescale Semiconductor
LIN BLOCK
LIN INTERFACE DESCRIPTION
LIN BLOCK
LIN INTERFACE DESCRIPTION
The physical interface is dedicated to automotive LIN sub-
bus applications.
The LIN pin exhibits no reverse current from the LIN bus
line to VSUP/2, even in the event of a GND shift or VSUP/2
disconnection.
The interface has 20 kbps and 10 kbps baud rates, and
includes as well as a fast baud rate for test and programming
modes. It has excellent ESD robustness and immunity
against disturbance, and radiated emission performance. It
has safe behavior when a LIN bus short-to-ground, or a LIN
bus leakage during LP mode.
The transmitter has a 20 kbps, 10 kbps and fast baud rate,
which are selected by SPI.
Receiver Characteristics
The receiver thresholds are ratiometric with the device
VSUP/2 voltage.
Digital inputs are related to the device VDD pin.
If the VSUP/2 voltage goes below typically 6.1 V, the LIN
bus enters into a recessive state even if communication is
sent on TXD.
POWER SUPPLY PIN (VSUP/2)
The VSUP/2 pin is the supply pin for the LIN interface. To
avoid a false bus message, an under-voltage on VSUP/2
disables the transmission path (from TXD to LIN) when
VSUP/2 falls below 6.1 V.
If LIN driver temperature reaches the over-temperature
threshold, the transceiver and receiver are disabled. When
the temperature falls below the over-temperature threshold,
LIN driver and receiver will be automatically enabled.
GROUND PIN (GND)
When there is a ground disconnection at the module level,
the LIN interface do not have significant current consumption
on the LIN bus pin when in the recessive state.
DATA INPUT PIN (TXD-L, TXD-L1, TXD-L2)
The TXD-L,TXD-L1 and TXD-L2 input pin is the MCU
interface to control the state of the LIN output. When TXD-L
is LOW (dominant), LIN output is LOW. When TXD-L is HIGH
(recessive), the LIN output transistor is turned OFF.
LIN BUS PIN (LIN, LIN1, LIN2)
The LIN pin represents the single-wire bus transmitter and
receiver. It is suited for automotive bus systems, and is
compliant to the LIN bus specification 2.1 and SAEJ2602-2.
This pin has an internal pull-up current source to VDD to
force the recessive state if the input pin is left floating.
If the pin stays low (dominant sate) more than tTXDDOM
,
The LIN interface is only active during Normal mode.
the LIN transmitter goes automatically in recessive state. This
is reported by flag in LIN register.
Driver Characteristics
The LIN driver is a LS MOSFET with internal over-current
thermal shutdown. An internal pull-up resistor with a serial
diode structure is integrated so no external pull-up
components are required for the application in a slave node.
An additional pull-up resistor of 1.0 k must be added when
the device is used in the master node. The 1.0 kpull-up
resistor can be connected to the LIN pin or to the ECU battery
supply.
DATA OUTPUT PIN (RXD-L, RXD-L1, RXD-L2)
This output pin is the MCU interface, which reports the
state of the LIN bus voltage.
LIN HIGH (recessive) is reported by a high voltage on
RXD, LIN LOW (dominant) is reported by a low voltage on
RXD.
LIN OPERATIONAL MODES
The LIN interface have two operational modes, Transmit
receiver and LIN disable modes.
When the fast baud rate is selected, the slew rate and
timing are much faster than the above specification and allow
fast data transition. The LIN interface can be set by the SPI
command in TXD/RXD mode, only when TXD-L is at a high
level. When the SPI command is send while TXD-L is low, the
command is ignored.
TRANSMIT RECEIVE
In the TXD/RXD mode, the LIN bus can transmit and
receive information.
When the 20 kbps baud rate is selected, the slew rate and
timing are compatible with LIN protocol specification 2.1.
SLEEP MODE
This mode is selected by SPI, and the transmission path is
disabled. Supply current for LIN block from VSUP/2 is very low
(typically 3.0 A). LIN bus is monitor to detect Wake-up
When the 10 kbps baud rate is selected, the slew rate and
timing are compatible with J2602-2.
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Freescale Semiconductor
61
LIN BLOCK
LIN OPERATIONAL MODES
event. In the Sleep mode, the internal 725 kOhm pull-up
resistor is connected and the 30 kOhm disconnected.
recessive transition. This is illustrated in Figures 20 and 21.
Once the Wake-up is detected, the event is reported to the
device state machine. An INT is generated if the device is in
LP VDD ON mode, or VDD will restart if the device was in LP
VDDOFF mode.
The LIN block can be awakened from Sleep mode by
detection of LIN bus activity.
LIN Bus Activity Detection
The Wake-up can be enable or disable by the SPI.
Fail-safe Features
The LIN bus Wake-up is recognized by a recessive to
dominant transition, followed by a dominant level with a
duration greater than 70 s, followed by a dominant to
Table 11 describes the LIN block behavior when there is a
failure.
Table 11. LIN Block Failure
FAULT
FUNCTIONNAL
MODE
CONDITION
CONSEQUENCE
RECOVERY
LIN supply under-voltage
LIN supply voltage < 6.0 V (typically)
TXD pin low for more than tTXDDOM
LIN transmitter in recessive State
LIN transmitter in recessive State
Condition gone
Condition gone
TXD RXD
TXD RXD
TXD Pin Permanent
Dominant
LIN transmitter and receiver disabled
HS turned off
LIN driver temperature > 160 °C
(typically)
LIN Thermal Shutdown
Condition gone
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Freescale Semiconductor
SERIAL PERIPHERAL INTERFACE
HIGH LEVEL OVERVIEW
SERIAL PERIPHERAL INTERFACE
HIGH LEVEL OVERVIEW
The device uses a 16 bits SPI, with the following
• bit 7 to 0 (D7 to D0): control bits
arrangements:
MISO, Master In Slave Out bits:
MOSI, Master Out Slave In bits:
• bits 15 to 8 (S15 to S8) are device status bits
• bits 7 to 0 (Do7 to Do0) are either extended device
status bits, device internal control register content or
device flags.
• bits 15 and 14 (called C1 and C0) are control bits to
select the SPI operation mode (write control bit to
device register, read back of the control bits, read of
device flag).
The SPI implementation does not support daisy chain
• bit 13 to 9 (A4 to A0) to select the register address.
• bit 8 (P/N) has two functions: parity bit in write mode
(optional, = 0 if not used), Next bit ( = 1) in read mode.
capability.
Figure 41 is an overview of the SPI implementation.
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MOSI C1
C0
A4
A2
A3
A1
A0
P/N
D7
D6
D5 D4
D3
D2
D1
D0
register address
Parity (optional) or
Next bit = 1
control bits
data
MISO S15 S14
S13 S12 S11
Device Status
S9
S8
S10
Do7 Do6 Do5 Do4
Do3 Do2 Do1 Do0
Extended Device Status, Register Control bits or Device Flags
CS active low. Must rise at end of 16 clocks,
for write commands, MOSI bits [15, 14] = [0, 1]
CS
SCLK
SCLK signal is low outside of CS active
MOSI and MISO data changed at SCLK rising edge
and sampled at falling edge. Msb first.
MOSI Don’t Care
Don’t Care
Tri-state
C1
C0
D0
Do0
MISO tri-state outside of CS active
MISO
Tri-state
S14
S15
SPI Wave Form, and Signals Polarity
Figure 41. SPI Overview
33903/4/5
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63
SERIAL PERIPHERAL INTERFACE
DETAIL OPERATION
DETAIL OPERATION
SPI Operation Deviation (does not apply to “C” version)
When the previous steps are implemented, the device will
operate as follows:
In some cases, the SPI write command is not properly
interpreted by the device. This results in either a “non
received SPI command” or a “corrupted SPI command”.
Important: Due to this, the tLEAD and tCSLOW parameters
must be carefully acknowledged.
For a given SPI write command (named SPI write ‘n’):
• In case the SPI write command ‘n’ is not accepted, the
following SPI command (named SPI ‘n+1’) will finish the
write process of the SPI write ‘n’, thanks to step 2
(tLAG > 550 ns) and step 3 (which is the additional SPI
command ‘n+1’).
• By applying steps 1, 2, and 3, no SPI command is ignored.
Worst case, the SPI write ‘n’ is executed at the time the
SPI ‘n+1’ is sent. This will lead to a delay in device
operation (delay between SPI command ‘n’ and ‘n+1’).
Only SPI write commands (starting with bits 15,14 = 01)
are affected. The SPI read commands (starting with bits
15,14 = 00 or 11) are not affected.
The occurrence of this issue is extremely low and is
caused by the synchronization between internal and external
signals. In order to guarantee proper operation, the following
steps must be taken.
Note: Occurrence of an incorrect command is reduced,
thanks to step 1 (extension of tCSLOW duration to >5.5 s).
1. Ensure the duration of the Chip Select Low (tCSLOW
)
Sequence examples:
Example 1:
state is >5.5 s.
Note: In data sheet revisions prior to 7.0, this parameter is
not specified and is indirectly defined by the sum of 3
parameters, tLEAD + 16 x tPCLK + tLAG (sum = 4.06 s).
• 0x60C0 (CAN interface control) – in case this command is
missed, next write command will complete it
• 0x66C0 (LIN interface control) – in case this command is
missed, next read command will complete it
• 0x2580 (read device ID) – Additional command to
complete previous LIN command, in case it was missed
2. Ensure SPI timing parameter tLEAD is a min. of
550 ns.
Note: In data sheet revisions prior to 7.0, the tLEAD
parameter is a min of 30 ns.
Example 2:
3. Make sure to include a SPI read command after a
• 0x60C0 (CAN interface control) - in case this command is
missed, next write command will complete it
• 0x66C0 (LIN interface control) - in case this command is
missed, next read command will complete it
• 0x2100 (read CAN register content) – this command will
complete previous one, in case it was missed
• 0x2700 (read LIN register content)
SPI write command.
In case a series of SPI write commands is used, only one
additional SPI read is necessary. The recommended SPI
read command is “device ID read: 0x2580” so device
operation is not affected (ex: clear flag). Other SPI read
commands may also be used.
BITS 15, 14, AND 8 FUNCTIONS
Table 12 summarizes the various SPI operation, depending upon bit 15, 14, and 8.
Table 12. SPI Operations (bits 8, 14, & 15)
Parity/Next
MOSI[8] P/N
Control Bits MOSI[15-14], C1-C0
Type of Command
Note for Bit 8 P/N
Read back of register
content and block (CAN,
I/O, INT, LINs) real time
state. See Table 39.
Bit 8 must be set to 1, independently of the parity function
selected or not selected.
00
1
Write to register
address, to control the
device operation
If bit 8 is set to “0”: means parity not selected OR
parity is selected AND parity = 0
01
0
1
if bit 8 is set to “1”: means parity is selected AND parity = 1
Reserved
10
11
Read of device flags
Bit 8 must be set to 1, independently of the parity function
selected or not selected.
1
form a register address
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SERIAL PERIPHERAL INTERFACE
DETAIL OPERATION
Device Status on MISO
BITS 13-9 FUNCTIONS
The device contains several registers coded on five bits
(bits 13 to 9).
When a write operation is performed to store data or
control bits into the device, the MISO pin reports a 16 bit fixed
device status composed of 2 bytes: Device Fixed Status (bits
15 to 8) + extended Device Status (bits 7 to 0). In a read
operation, MISO will report the Fixed device status (bits 15 to
8) and the next eight bits will be the content of the selected
register.
Each register controls or reports part of the device’s
function. Data can be written to the register to control the
device operation or to set the default value or behavior.
Every register can also be read back in order to ensure
that it’s content (default setting or value previously written) is
correct.
REGISTER ADRESS TABLE
Table 13 is a list of device registers and addresses, coded
with bits 13 to 9.
In addition, some of the registers are used to report device
flags.
Table 13. Device Registers with Corresponding Address
Address
MOSI[13-9]
A4...A0
Quick Ref.
Name
Description
Functionality
0_0000
Analog Multiplexer
MUX
1) Write “device control bits” to register address.
2) Read back register “control bits”
0_0001
0_0010
0_0011
0_0100
0_0101
0_0110
0_0111
0_1000
0_1001
Memory byte A
Memory byte B
RAM_A
RAM_B
1) Write “data byte” to register address.
2) Read back “data byte” from register address
Memory byte C
RAM_C
Memory byte D
RAM_D
Initialization Regulators
Initialization Watchdog
Initialization LIN and I/O
Initialization Miscellaneous functions
Specific modes
Init REG
1) Write “device initialization control bits” to register address.
2) Read back “initialization control bits” from register address
Init watchdog
Init LIN I/O
Init MISC
SPE_MODE
1) Write to register to select device Specific mode, using “Inverted
Random Code”.
2) Read “Random Code”
0_1010
0_1011
0_1100
0_1101
0_1110
Timer_A: watchdog & LP MCU consumption
Timer_B: Cyclic Sense & Cyclic Interrupt
Timer_C: watchdog LP & Forced Wake-up
Watchdog Refresh
TIM_A
TIM_B
1) Write “timing values” to register address.
2) Read back register “timing values”
TIM_C
watchdog
MODE
Watchdog Refresh Commands
Mode register
1) Write to register to select LP mode, with optional “Inverted Random
code” and select Wake-up functionality
2) Read operations:
Read back device “Current mode”
Read “Random Code”,
Leave “Debug mode”
0_1111
1_0000
1_0001
1_0010
1_0011
1_0100
Regulator Control
CAN interface control
Input Output control
Interrupt Control
REG
CAN
1) Write “device control bits” to register address, to select device
operation.
I/O
2) Read back register “control bits”.
Interrupt
LIN1
3) Read device flags from each of the register addresses.
LIN1 interface control
LIN2 interface control
LIN2
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65
SERIAL PERIPHERAL INTERFACE
DETAIL OPERATION
COMPLETE SPI OPERATION
Table 14 is a compiled view of all the SPI capabilities and
options. Both MOSI and MISO information are described.
Table 14. SPI Capabilities with Options
MOSI/
MISO
Control bits
[15-14]
Address
[13-9]
Parity/Next
bits [8]
Type of Command
Bit 7
Bits [6-0]
Read back of “device control bits” (MOSI bit 7 = 0)
OR
MOSI
MISO
MOSI
MISO
MOSI
MISO
00
address
1
0
000 0000
Register control bits content
000 0000
Device Fixed Status (8 bits)
Read specific device information (MOSI bit 7 = 1)
00
address
1
1
Device Fixed Status (8 bits)
Device ID and I/Os state
Control bits
Write device control bit to address selected by bits
(13-9).
01
address
(note)
Device Fixed Status (8 bits)
Device Extended Status (8 bits)
MISO return 16 bits device status
Reserved
MOSI
MISO
MISO
10
Reserved
Reserved
Read device flags and Wake-up flags, from
register address (bit 13-9), and sub address (bit 7).
11
address
Reserved
0
Read of device flags form a register address,
and sub address LOW (bit 7)
MISO return fixed device status (bit 15-8) + flags
from the selected address and sub-address.
MOSI
MISO
Device Fixed Status (8 bits)
Flags
11
address
1
1
Read of device flags form a register address,
and sub address HIGH (bit 7)
MOSI
Device Fixed Status (8 bits)
Flags
Note: P = 0 if parity bit is not selected or parity = 0. P = 1 if parity
is selected and parity = 1.
Thus the Exact command will then be:
MOSI [bit 15-0] = 01 00 011 0 01101001
Examples 2:
PARITY BIT 8
Calculation
MOSI [bit 15-0] = 01 00 011 P 0100 0000, P should be 1,
because the command contains 4 bits with logic 1.
Thus the Exact command will then be:
The parity is used for the write-to-register command (bit
15,14 = 01). It is calculated based on the number of logic one
contained in bits 15-9,7-0 sequence (this is the entire 16 bits
of the write command except bit 8).
MOSI [bit 15-0] = 01 00 011 1 0100 0000
Parity Function Selection
Bit 8 must be set to 0 if the number of 1 is odd.
Bit 8 must be set to 1if the number of 1 is even.
All SPI commands and examples do not use parity
functions.
The parity function is optional. It is selected by bit 6 in INIT
MISC register.
If parity function is not selected (bit 6 of INIT MISC = 0),
then Parity bits in all SPI commands (bit 8) must be “0”.
Examples 1:
MOSI [bit 15-0] = 01 00 011 P 01101001, P should be 0,
because the command contains 7 bits with logic 1.
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SERIAL PERIPHERAL INTERFACE
DETAIL OF CONTROL BITS AND REGISTER MAPPING
DETAIL OF CONTROL BITS AND REGISTER MAPPING
The following tables contain register bit meaning arranged by register address, from address 0_000 to address 1_0100
MUX AND RAM REGISTERS
Table 15. MUX Register(38)
MOSI Second Byte, bits 7-0
MOSI First Byte [15-8]
[b_15 b_14] 0_0000 [P/N]
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
01 00 _ 000 P
Default state
MUX_2
0
MUX_1
0
MUX_0
0
Int 2K
0
I/O-att
0
0
0
0
0
0
0
Condition for default
POR, 5 V-CAN off, any mode different from Normal
Bits
Description
b7 b6 b5
MUX_2, MUX_1, MUX_0 - Selection of external input signal or internal signal to be measured at MUX-OUT pin
000
001
010
011
100
101
110
111
b4
All functions disable. No output voltage at MUX-OUT pin
V
regulator current recopy. Ratio is approx 1/97. Requires an external resistor or selection of Internal 2.0 K (bit 3)
Device internal voltage reference (approx 2.5 V)
DD
Device internal temperature sensor voltage
Voltage at I/O-0. Attenuation or gain is selected by bit 3.
Voltage at I/O-1. Attenuation or gain is selected by bit 3.
Voltage at VSUP/1 pin. Refer to electrical table for attenuation ratio (approx 5)
Voltage at VSENSE pin. Refer to electrical table for attenuation ratio (approx 5)
INT 2k - Select device internal 2.0 kohm resistor between AMUX and GND. This resistor allows the measurement of a voltage proportional
to the V output current.
DD
0
1
Internal 2.0 kohm resistor disable. An external resistor must be connected between AMUX and GND.
Internal 2.0 kohm resistor enable.
b3
I/O-att - When I/O-0 (or I/O-1) is selected with b7,b6,b5 = 100 (or 101), b3 selects attenuation or gain
between I/O-0 (or I/O-1) and MUX-OUT pin
0
1
Gain is approx 2 for device with V = 5.0 V (Ref. to electrical table for exact gain value)
DD
Gain is approx 1.3 for device with V = 3.3 V (Ref. to electrical table for exact gain value)
DD
Attenuation is approx 4 for device with V = 5.0 V (Ref. to electrical table for exact attenuation value)
DD
Attenuation is approx 6 for device with V = 3.3 V (Ref. to electrical table for exact attenuation value)
DD
Notes
38. The MUX register can be written and read only when the 5V-CAN regulator is ON. If the MUX register is written or read while
5V-CAN is OFF, the command is ignored, and the MXU register content is reset to default state (all control bits = 0).
33903/4/5
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SERIAL PERIPHERAL INTERFACE
DETAIL OF CONTROL BITS AND REGISTER MAPPING
Table 16. Internal Memory Registers A, B, C, and D, RAM_A, RAM_B, RAM_C, and RAM_D
MOSI Second Byte, bits 7-0
MOSI First Byte [15-8]
[b_15 b_14] 0_0xxx [P/N]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01 00 _ 001 P
Default state
Ram a7
0
Ram a6
0
Ram a5
0
Ram a4
0
Ram a3
0
Ram a2
0
Ram a1
0
Ram a0
0
Condition for default
01 00 _ 010 P
POR
POR
POR
POR
Ram b7
0
Ram b6
0
Ram b5
0
Ram b4
0
Ram b3
0
Ram b2
0
Ram b1
0
Ram b0
0
Default state
Condition for default
01 00 _ 011 P
Ram c7
0
Ram c6
0
Ram c5
0
Ram c4
0
Ram c3
0
Ram c2
0
Ram c1
0
Ram c0
0
Default state
Condition for default
01 00 _ 100 P
Ram d7
0
Ram d6
0
Ram d5
0
Ram d4
0
Ram d3
0
Ram d2
0
Ram d1
0
Ram d0
0
Default state
Condition for default
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Freescale Semiconductor
SERIAL PERIPHERAL INTERFACE
DETAIL OF CONTROL BITS AND REGISTER MAPPING
INIT REGISTERS
Note: these registers can be written only in INIT mode
Table 17. Initialization Regulator Registers, INIT REG (note: register can be written only in INIT mode)
MOSI Second Byte, bits 7-0
MOSI First Byte [15-8]
[b_15 b_14] 0_0101 [P/N]
bit 7
bit 6
rst[1]
bit 5
rst[0]
bit 4
rstD[1]
bit 3
rstD[0]
bit 2
bit 1
bit 0
01 00 _ 101 P
Default state
I/O-x sync
1
V
V
V
V
V
5/3
Cyclic on[1]
0
Cyclic on[0]
0
DDL
DDL
DD
DD
AUX
0
0
0
0
0
Condition for default
POR
Bit
b7
Description
I/O-x sync - Determine if I/O-1 is sensed during I/O-0 activation, when cyclic sense function is selected
0
1
I/O-1 sense anytime
I/O-1 sense during I/O-0 activation
b6, b5
V
[1] V
[0] - Select the V under-voltage threshold, to activate RST pin and/or INT
DDL RST
DDL RST DD
00
01
10
11
Reset at approx 0.9 V
.
DD
INT at approx 0.9 V , Reset at approx 0.7 V
DD
DD
Reset at approx 0.7 V
DD
Reset at approx 0.9 V
.
DD
b4, b3
V
D[1] V
D[0] - Select the RST pin low lev duration, after V rises above the V under-voltage threshold
DD RST
DD RST DD DD
00
01
10
11
1.0 ms
5.0 ms
10 ms
20 ms
b2
[V
5/3] - Select Vauxilary output voltage
AUX
0
1
V
V
= 3.3 V
= 5.0 V
AUX
AUX
b1, b0
Cyclic on[1] Cyclic on[0] - Determine I/O-0 activation time, when cyclic sense function is selected
00
01
10
11
200 s (typical value. Ref. to dynamic parameters for exact value)
400 s (typical value. Ref. to dynamic parameters for exact value)
800 s (typical value. Ref. to dynamic parameters for exact value)
1600 s (typical value. Ref. to dynamic parameters for exact value)
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SERIAL PERIPHERAL INTERFACE
DETAIL OF CONTROL BITS AND REGISTER MAPPING
Table 18. Initialization Watchdog Registers, INIT watchdog (note: register can be written only in INIT mode)
MOSI Second Byte, bits 7-0
MOSI First Byte [15-8]
[b_15 b_14] 0_0110 [P/N]
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
01 00 _ 110 P
Default state
WD2INT
0
MCU_OC
1
OC-TIM
0
WD Safe
WD_spi[1]
0
WD_spi[0]
0
WD N/Win
1
Crank
0
Condition for default
POR
Bit
b7
Description
WD2INT - Select the maximum time delay between INT occurrence and INT source read SPI command
0
1
Function disable. No constraint between INT occurrence and INT source read.
INT source read must occur before the remaining of the current watchdog period plus 2 complete watchdog periods.
MCU_OC, OC-TIM - In LP V ON, select watchdog refresh and V current monitoring functionality. V threshold is defined in device
DD_OC_LP
DD
DD
b6, b5
electrical parameters (approx 1.5 mA)
In LP mode, when watchdog is not selected
no watchdog
+ 00
In LP V ON mode, V over-current has no effect
DD DD
no watchdog
+ 01
In LP V ON mode, V over-current has no effect
DD DD
no watchdog
+ 10
In LP V ON mode, V current > V
threshold for a time > 100 s (typically) is a wake-up event
DD
DD
DD_OC_LP
no watchdog In LP V ON mode, V current > V
threshold for a time > I_mcu_OC is a wake-up event. I_mcu_OC time is selected in Timer register
(selection range from 3.0 to 32 ms)
DD
DD
DD_OC_LP
+ 11
In LP mode when watchdog is selected
watchdog +
00
In LP V ON mode, V current > V
threshold has no effect. watchdog refresh must occur by SPI command.
DD
DD
DD_OC_LP
In LP V ON mode, V current > V
DD DD DD_OC_LP
watchdog +
01
threshold has no effect. watchdog refresh must occur by SPI command.
watchdog +
10
In LP V ON mode, V over-current for a time > 100 s (typically) is a wake-up event.
DD DD
watchdog +
11
In LP V ON mode, V current > V
threshold for a time > I_mcu_OC is a wake-up event. I_mcu_OC time is selected in Timer register (selection range from 3.0 to 32 ms)
threshold for a time < I_mcu_OC is a watchdog refresh condition. V current > V
DD_OC_LP DD DD_OC_LP
DD
DD
b4
WD Safe - Select the activation of the SAFE pin low, at first or second consecutive RESET pulse
0
1
SAFE pin is set low at the time of the RST pin low activation
SAFE pin is set low at the second consecutive time RST pulse
b3, b2
00
WD_spi[1] WD_spi[0] - Select the Watchdog (watchdog) Operation
Simple Watchdog selection: watchdog refresh done by a 8 bits or 16 bits SPI
Enhanced 1: Refresh is done using the Random Code, and by a single 16 bits.
Enhanced 2: Refresh is done using the Random Code, and by two 16 bits command.
Enhanced 4: Refresh is done using the Random Code, and by four 16 bits command.
01
10
11
b1
0
WD N/Win - Select the Watchdog (watchdog) Window or Timeout operation
Watchdog operation is TIMEOUT, watchdog refresh can occur anytime in the period
1
Watchdog operation is WINDOW, watchdog refresh must occur in the open window (second half of period)
33903/4/5
Analog Integrated Circuit Device Data
70
Freescale Semiconductor
SERIAL PERIPHERAL INTERFACE
DETAIL OF CONTROL BITS AND REGISTER MAPPING
Bit
Description
b0
0
Crank - Select the V
threshold to disable V , while V
is falling toward GND
SUP/1
DD
SUP1
V
disable when V
is below typically 4.0 V (parameter V
), and device in Reset mode
DD
SUP/1
SUP-TH1
1
V
kept ON when V
is below typically 4.0 V (parameter V
)
SUP_TH1
DD
SUP/1
Table 19. Initialization LIN and I/O Registers, INIT LIN I/O (note: register can be written only in INIT mode)
MOSI Second Byte, bits 7-0
MOSI First Byte [15-8]
[b_15 b_14] 0_0111 [P/N]
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
01 00 _ 111 P
Default state
I/O-1 ovoff
0
LIN_T2[1]
0
LIN_T2[0]
0
LIN_T/1[1]
LIN_T/1[0]
0
I/O-1 out-en
0
I/O-0 out-en
0
Cyc_Inv
0
Condition for default
POR
Bit
b7
Description
I/O-1 ovoff - Select the deactivation of I/O-1 when V or V
over-voltage condition is detected
AUX
DD
0
1
Disable I/O-1 turn off.
Enable I/O-1 turn off, when V or V
over-voltage condition is detected.
AUX
DD
b6, b5
LIN_T2[1], LIN_T2[0] - Select pin operation as LIN Master pin switch or I/O
00
01
10
11
pin is OFF
pin operation as LIN Master pin switch
pin operation as I/O: HS switch and Wake-up input
N/A
b4, b3
LIN_T/1[1], LIN_T/1[0] - Select pin operation as LIN Master pin switch or I/O
00
01
10
11
pin is OFF
pin operation as LIN Master pin switch
pin operation as I/O: HS switch and Wake-up input
N/A
b2
0
I/O-1 out-en- Select the operation of the I/O-1 as output driver (HS, LS)
Disable HS and LS drivers of pin I/O-1. I/O-1 can only be used as input.
Enable HS and LS drivers of pin I/O-1. Pin can be used as input and output driver.
1
b1
0
I/O-0 out-en - Select the operation of the I/O-0 as output driver (HS, LS)
Disable HS and LS drivers of I/O-0 can only be used as input.
1
Enable HS and LS drivers of the I/O-0 pin. Pin can be used as input and output drivers.
b0
Cyc_Inv - Select I/O-0 operation in device LP mode, when cyclic sense is selected
0
During cyclic sense active time, I/O is set to the same state prior to entering in to LP mode. During cyclic sense off time, I/O-0 is disable (HS and
LS drivers OFF).
1
During cyclic sense active time, I/O is set to the same state prior to entering in to LP mode. During cyclic sense off time, the opposite driver of I/
O_0 is actively set. Example: If I/0_0 HS is ON during active time, then I/O_O LS is turned ON at expiration of the active time, for the duration of
the cyclic sense period.
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
71
SERIAL PERIPHERAL INTERFACE
DETAIL OF CONTROL BITS AND REGISTER MAPPING
Table 20. Initialization Miscellaneous Functions, INIT MISC (Note: Register can be written only in INIT mode)
MOSI Second Byte, bits 7-0
MOSI First Byte [15-8]
[b_15 b_14] 0_1000 [P/N]
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
01 01_ 000 P
Default state
LPM w RNDM
0
SPI parity
0
INT pulse
0
INT width
INT flash
0
Dbg Res[2]
0
Dbg Res[1]
0
Dbg Res[0]
0
Condition for default
POR
Bit
Description
b7
LPM w RNDM - This enables the usage of random bits 2, 1 and 0 of the MODE register to enter into LP VDD OFF or LP VDD ON.
0
1
Function disable: the LP mode can be entered without usage of Random Code
Function enabled: the LP mode is entered using the Random Code
b6
SPI parity - Select usage of the parity bit in SPI write operation
0
1
Function disable: the parity is not used. The parity bit must always set to logic 0.
Function enable: the parity is used, and parity must be calculated.
b5
INT pulse -Select INT pin operation: low level pulse or low level
0
1
INT pin will assert a low level pulse, duration selected by bit [b4]
INT pin assert a permanent low level (no pulse)
b4
0
INT width - Select the INT pulse duration
INT pulse duration is typically 100 s. Ref. to dynamic parameter table for exact value.
INT pulse duration is typically 25 s. Ref. to dynamic parameter table for exact value.
1
b3
INT flash - Select INT pulse generation at 50% of the Watchdog Period in Flash mode
Function disable
Function enable: an INT pulse will occur at 50% of the Watchdog Period when device in Flash mode.
b2, b1, b0 Dbg Res[2], Dbg Res[1], Dbg Res[0] - Allow verification of the external resistor connected at DBG pin. Ref. to parametric table for resistor range
(39)
value.
0xx
100
101
110
111
Function disable
100 verification enable: resistor at DBG pin is typically 68 kohm (RB3) - Selection of SAFE mode B3
101 verification enable: resistor at DBG pin is typically 33 kohm (RB2 - Selection of SAFE mode B2
110 verification enable: resistor at DBG pin is typically 15 kohm (RB1) - Selection of SAFE mode B1
111 verification enable: resistor at DBG pin is typically 0 kohm (RA) - Selection of SAFE mode A
Notes
39. Bits b2,1 and 0 allow the following operation:
First, check the resistor device has detected at the DEBUG pin. If the resistor is different, bit 5 (Debug resistor) is set in INTerrupt
register (Ref. to device flag table).
Second, over write the resistor decoded by device, to set the SAFE mode operation by SPI. Once this function is selected by bit 2 = 1,
this selection has higher priority than “hardware”, and device will behave according to b2,b1 and b0 setting
33903/4/5
Analog Integrated Circuit Device Data
72
Freescale Semiconductor
SERIAL PERIPHERAL INTERFACE
DETAIL OF CONTROL BITS AND REGISTER MAPPING
SPECIFIC MODE REGISTER
Table 21. Specific Mode Register, SPE_MODE
MOSI Second Byte, bits 7-0
MOSI First Byte [15-8]
[b_15 b_14] 01_001 [P/N]
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
01 01_ 001 P
Default state
Sel_Mod[1]
0
Sel_Mod[0]
0
Rnd_C5b
0
Rnd_C4b
Rnd_C3b
0
Rnd_C2b
0
Rnd_C1b
0
Rnd_C0b
0
Condition for default
POR
Bit
Description
b7, b6
Sel_Mod[1], Sel_Mod[0] - Mode selection: these 2 bits are used to select which mode the device will enter upon a SPI command.
00
01
10
11
RESET mode
INIT mode
FLASH mode
N/A
b5....b0
[Rnd_C4b... Rnd_C0b] - Random Code inverted, these six bits are the inverted bits obtained from the SPE MODE Register read command.
The SPE MODE Register is used for the Following
Operation
2) Write INIT mode + random code inverted
MOSI : 0101 0010 01 Ri5 Ri4 Ri3 Ri2 Ri1 Ri0 [Hex 0x 52
HH] (RIX = random code inverted)
- Set the device in RESET mode, to exercise or test the
RESET functions.
MISO : xxxx xxxx xxxx xxxx (don’t care)
- Go to INIT mode, using the Secure SPi command.
SAFE pin activation: SAFE pin can be set low, only in INIT
mode, with following commands:
- Go to FLASH mode (in this mode the watchdog timer can
be extended up to 32 s).
1) Read random code:
- Activate the SAFE pin by S/W.
MOSI : 0001 0011 0000 0000 [Hex:0x 13 00]
MISO report 16 bits, random code are bits (5-0)
This mode (called Special mode) is accessible from the
secured SPI command, which consist of 2 commands:
miso = xxxx xxxx xxR5 R4 R3 R2 R1 R0 (RXD = 6 bits
random code)
1) reading a random code and
2) then write the inverted random code plus mode
selection or SAFE pin activation:
2) Write INIT mode + random code bits 5:4 not inverted
and random code bits 3:0 inverted
Return to INIT mode is done as follow (this is done from
Normal mode only):
MOSI : 0101 0010 01 R5 R4 Ri3 Ri2 Ri1 Ri0 [Hex 0x 52
HH] (RIX = random code inverted)
1) Read random code:
MISO : xxxx xxxx xxxx xxxx (don’t care)
MOSI : 0001 0011 0000 0000 [Hex:0x 13 00]
MISO report 16 bits, random code are bits (5-0)
Return to Reset or Flash mode is done similarly to the go
to INIT mode, except that the b7 and b6 are set according to
the table above (b7, b6 = 00 - go to reset, b7, b6 = 10 - go to
Flash).
miso = xxxx xxxx xxR5 R4 R3 R2 R1 R0 (RXD = 6 bits
random code)
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
73
SERIAL PERIPHERAL INTERFACE
DETAIL OF CONTROL BITS AND REGISTER MAPPING
TIMER REGISTERS
Table 22. Timer Register A, LP VDD Over-current & Watchdog Period Normal mode, TIM_A
MOSI Second Byte, bits 7-0
MOSI First Byte [15-8]
[b_15 b_14] 01_010 [P/N]
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
01 01_ 010 P
I_mcu[2]
I_mcu[1]
I_mcu[1]
watchdog
Nor[4]
W/D_N[4]
W/D_Nor[3]
W/D_N[2]
W/D_Nor[0]
Default state
0
0
0
1
1
1
1
0
Condition for default
POR
LP VDD Over-current (ms)
b6, b5
b7
00
3 (def)
4
01
6
10
12
16
11
24
32
0
1
8
Watchdog Period in Device Normal Mode (ms)
b2, b1, b0
b4, b3
000
2.5
3
001
5
010
10
011
20
24
28
32
100
40
48
56
64
101
110
160
192
224
111
00
01
10
11
80
96
320
384
448
512
6
12
3.5
4
7
14
112
128
8
16
256 (def)
Table 23. Timer Register B, Cyclic Sense and Cyclic INT, in Device LP Mode, TIM_B
MOSI Second Byte, bits 7-0
MOSI First Byte [15-8]
[b_15 b_14] 01_011 [P/N]
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
01 01_ 011 P
Default state
Cyc-sen[3]
0
Cyc-sen[2]
0
Cyc-sen[1]
0
Cyc-sen[0]
0
Cyc-int[3]
0
Cyc-int[2]
0
Cyc-int[1]
0
Cyc-int[0]
0
Condition for default
POR
Cyclic Sense (ms)
b6, b5, b4
b7
000
001
6
010
011
24
100
101
96
110
192
256
111
384
512
0
1
3
12
16
48
64
4
8
32
128
Cyclic Interrupt (ms)
b2, b1, b0
b3
000
6 (def)
8
001
12
010
24
011
48
100
96
101
192
258
110
384
512
111
768
0
1
16
32
64
128
1024
33903/4/5
Analog Integrated Circuit Device Data
74
Freescale Semiconductor
SERIAL PERIPHERAL INTERFACE
DETAIL OF CONTROL BITS AND REGISTER MAPPING
Table 24. Timer Register C, Watchdog LP Mode or Flash Mode and Forced Wake-up Timer, TIM_C
MOSI Second Byte, bits 7-0
MOSI First Byte [15-8]
[b_15 b_14] 01_100 [P/N]
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
01 01_ 100 P
Default state
WD-LP-F[3]
0
WD-LP-F[2] WD-LP-F[1] WD-LP-F[0]
FWU[3]
0
FWU[2]
0
FWU[1]
0
FWU[0]
0
0
0
0
Condition for default
POR
Table 25. Typical Timing Values
Watchdog in LP VDD ON Mode (ms)
b6, b5, b4
b7
000
12
001
24
010
48
011
96
100
192
256
101
384
512
110
111
0
1
768
1536
2048
16
32
64
128
1024
Watchdog in Flash Mode (ms)
b6, b5, b4
b7
000
48 (def)
256
001
96
010
192
011
384
100
768
101
110
3072
16384
111
6144
32768
0
1
1536
8192
512
1024
2048
4096
Forced Wake-up (ms)
b2, b1, b0
b3
000
48 (def)
64
001
96
010
192
258
011
384
512
100
101
1536
2048
110
111
6144
8192
0
1
768
3072
4096
128
1024
WATCHDOG AND MODE REGISTERS
Table 26. Watchdog Refresh Register, watchdog(40)
MOSI Second Byte, bits 7-0
MOSI First Byte [15-8]
[b_15 b_14] 01_101 [P/N]
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
01 01_ 101 P
Default state
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Condition for default
POR
Notes
40. The Simple Watchdog Refresh command is in hexadecimal: 5A00. This command is used to refresh the watchdog and also to
transition from INIT mode to Normal mode, and from Normal Request mode to Normal mode (after a wake-up of a reset)
.
Table 27. MODE Register, MODE
MOSI Second Byte, bits 7-0
MOSI First Byte [15-8]
[b_15 b_14] 01_110 [P/N]
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
01 01_ 110 P
Default state
mode[4]
N/A
mode[3]
N/A
mode[2]
N/A
mode[1]
N/A
mode[0]
N/A
Rnd_b[2]
N/A
Rnd_b[1]
N/A
Rnd_b[0]
N/A
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
75
SERIAL PERIPHERAL INTERFACE
DETAIL OF CONTROL BITS AND REGISTER MAPPING
Table 28. LP VDD OFF Selection and FWU / Cyclic Sense Selection
b7, b6, b5, b4, b3
FWU
Cyclic Sense
0 1100
0 1101
0 1110
0 1111
OFF
OFF
ON
OFF
ON
OFF
ON
ON
Table 29. LP VDD ON Selection and Operation Mode
b7, b6, b5, b4, b3
FWU
Cyclic Sense
Cyclic INT
Watchdog
1 0000
1 0001
1 0010
1 0011
1 0100
1 0101
1 0110
1 0111
1 1000
1 1001
1 1010
1 1011
1 1100
1 1101
1 1110
1 1111
b2, b1, b0
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
ON
OFF
OFF
ON
OFF
ON
OFF
ON
ON
OFF
OFF
ON
OFF
ON
ON
ON
OFF
ON
ON
ON
OFF
OFF
OFF
OFF
ON
OFF
OFF
ON
OFF
ON
ON
ON
OFF
ON
ON
ON
ON
OFF
OFF
ON
OFF
ON
ON
ON
ON
ON
OFF
ON
ON
ON
ON
Random Code inverted, these 3bits are the inverted bits obtained from the previous SPI command.
The usage of these bits are optional and must be previously selected in the INIT MISC register [See
bit 7 (LPM w RNDM) in Table 20]
Prior to enter in LP VDD ON or LP VDD OFF, the Wake-up
flags must be cleared or read.
When the device is in LP VDD ON mode, the Wake-up by
a SPI command uses a write to “Normal Request mode”,
0x5C10.
This is done by the following SPI commands (See Table
39, Device Flag, I/O Real Time and Device Identification):
Mode Register Features
0xE100 for CAN Wake-up clear
0xE380 for I/O Wake-up clear
0xE700 for LIN1 Wake-up clear
0xE900 for LIN2 Wake-up clear
The mode register includes specific functions and a “global
SPI command” that allow the following:
- read device current mode
- read device Debug status
- read state of SAFE pin
If Wake-up flags are not cleared, the device will enter into
the selected LP mode and immediately Wake-up. In addition,
the CAN failure flags (i.e. CAN_F and CAN_UF) must be
cleared in order to meet the low power current consumption
specification. This is done by the following SPI command:
- leave Debug state
- release or turn off SAFE pin
- read a 3 bit Random Code to enter in LP mode
0xE180 (read CAN failure flags)
These global commands are built using the MODE register
address bit [13-9], along with several combinations of bit [15-
14] and bit [7]. Note, bit [8] is always set to 1.
33903/4/5
Analog Integrated Circuit Device Data
76
Freescale Semiconductor
SERIAL PERIPHERAL INTERFACE
DETAIL OF CONTROL BITS AND REGISTER MAPPING
Entering into LP Mode Using Random Code
1. in hex: 0x5C60 to enter in LP VDD OFF mode without
using the 3 random code bits.
- LP mode using Random Code must be selected in INIT
mode via bit 7 of the INIT MISC register.
2. if Random Code is selected, the commands are:
- Read Random Code: 0x1D00 or 0x1D80,
- In Normal mode, read the Random Code using 0x1D00 or
0x1D80 command. The 3 Random Code bits are available on
MISO bits 2,1 and 0.
MISO report in binary: bits 15-8, bits 7-3, Rnd_[2], Rnd_[1],
Rnd_[0].
- Write LP mode by inverting the 3 random bits.
- Write LP VDD OFF mode, using Random Code inverted:
in binary: 0101 1100 0110 0 Rnd_b[2], Rnd_b[1], Rnd_b[0].
Table 30 summarizes these commands
Example - Select LP VDD OFF without cyclic sense and
FWU:
Table 30. Device Modes
Global commands and effects
MOSI bits 15-14
00
bits 13-9
bit 8
bit 7
bits 6-0
Read device current mode, Leave debug mode.
Keep SAFE pin as is.
01 110
1
0
000 0000
MOSI in hexadecimal: 1D 00
MISO
bit 15-8
Fix Status
bit 7-3
device current mode
bit 2-0
Random code
MOSI bits 15-14
bits 13-9
bit 8
bit 7
bits 6-0
Read device current mode
Release SAFE pin (turn OFF).
MOSI in hexadecimal: 1D 80
00
01 110
1
1
000 0000
MISO
bit 15-8
Fix Status
bit 7-3
device current mode
bit 2-0
Random code
MOSI bits 15-14
bits 13-9
bit 8
bit 7
bits 6-0
Read device current mode, Leave debug mode.
Keep SAFE pin as is.
11
01 110
1
0
000 0000
MOSI in hexadecimal: DD 00
MISO reports Debug and SAFE state (bits 1,0)
MISO
bit 15-8
Fix Status
bit 7-3
device current mode
bit 2
bit 1
bit 0
X
SAFE
DEBUG
MOSI bits 15-14
bits 13-9
bit 8
bit 7
bits 6-0
Read device current mode, Keep DEBUG mode
Release SAFE pin (turn OFF).
11
01 110
1
1
000 0000
MOSI in hexadecimal: DD 80
MISO reports Debug and SAFE state (bits 1,0)
MISO
bit 15-8
Fix Status
bit 7-3
device current mode
bit 2
bit 1
bit 0
X
SAFE
DEBUG
Table 31 describes MISO bits 7-0, used to decode the
device’s current mode.
Table 32. SAFE and DEBUG status
SAFE and DEBUG bits
Table 31. MISO bits 7-3
b1
description
Device current mode, any of the above commands
0
1
SAFE pin OFF, not activated
SAFE pin ON, driver activated.
description
b7, b6, b5, b4, b3
MODE
0 0000
0 0001
0 0010
0 0011
1 XXXX
INIT
FLASH
b0
0
1
Debug mode OFF
Debug mode Active
Normal Request
Normal mode
Low Power mode (Table 29)
Table 32 describes the SAFE and DEBUG bit decoding.
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
77
SERIAL PERIPHERAL INTERFACE
DETAIL OF CONTROL BITS AND REGISTER MAPPING
REGULATOR, CAN, I/O, INT AND LIN REGISTERS
Table 33. Regulator Register
MOSI Second Byte, bits 7-0
MOSI First Byte [15-8]
[b_15 b_14] 01_111 [P/N]
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bal en
bit 1
bit 0
01 01_ 111 P
Default state
V
[1]
V
[0]
-
5V-can[1]
0
5V-can[0]
0
V
V
bal auto
N/A
V
DD
OFF en
N/A
AUX
AUX
DD
DD
0
0
N/A
N/A
Condition for default
POR
POR
Bits
b7 b6
00
Description
VAUX[1], VAUX[0] - Vauxilary regulator control
Regulator OFF
Regulator ON. Under-voltage (UV) and Over-current (OC) monitoring flags not reported. VAUX is disabled when UV or OC
detected after 1.0 ms blanking time.
01
Regulator ON. Under-voltage (UV) and over-current (OC) monitoring flags active. VAUX is disabled when UV or OC detected
after 1.0 ms blanking time.
10
11
Regulator ON. Under-voltage (UV) and over-current (OC) monitoring flags active. VAUX is disabled when UV or OC detected
after 25 s blanking time.
5 V-can[1], 5 V-can[0] - 5V-CAN regulator control
b4 b3
00
Regulator OFF
Regulator ON. Thermal protection active. Under-voltage (UV) and over-current (OC) monitoring flags not reported. 1.0 ms
blanking time for UV and OC detection. Note: by default when in Debug mode
01
Regulator ON. Thermal protection active. Under-voltage (UV) and over-current (OC) monitoring flags active. 1.0 ms blanking
time for UV and OC detection.
10
11
Regulator ON. Thermal protection active. Under-voltage (UV) and over-current (OC) monitoring flags active after 25 s blanking
time.
VDD bal en - Control bit to Enable the VDD external ballast transistor
External VDD ballast disable
b2
0
External VDD ballast Enable
1
VDD bal auto - Control bit to automatically Enable the VDD external ballast transistor, if VDD is > typically 60 mA
Disable the automatic activation of the external ballast
Enable the automatic activation of the external ballast, if VDD > typically 60 mA
VDD OFF en - Control bit to allow transition into LP VDD OFF mode (to prevent VDD turn OFF)
Disable Usage of LP VDD OFF mode
b1
0
1
b0
0
Enable Usage of LP VDD OFF mode
1
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SERIAL PERIPHERAL INTERFACE
DETAIL OF CONTROL BITS AND REGISTER MAPPING
Table 34. CAN Register(41)
MOSI Second Byte, bits 7-0
MOSI First byte [15-8]
[b_15 b_14] 10_000 [P/N]
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
01 10_ 000P
Default state
CAN mod[1] CAN mod[0]
Slew[1]
0
Slew[0]
0
Wake-up 1/3
-
-
-
-
CAN int
0
1
0
0
Condition for default
note
POR
POR
POR
Bits
Description
b7 b6
00
CAN mod[1], CAN mod[0] - CAN interface mode control, Wake-up enable / disable
CAN interface in Sleep mode, CAN Wake-up disable.
CAN interface in receive only mode, CAN driver disable.
01
CAN interface is in Sleep mode, CAN Wake-up enable. In device LP mode,
10
CAN Wake-up is reported by device Wake-up. In device Normal mode, CAN Wake-up reported by INT.
CAN interface in transmit and receive mode.
11
b5 b4
00/11
01
Slew[1] Slew[0] - CAN driver slew rate selection
FAST
MEDIUM
SLOW
10
Wake-up 1/3 - Selection of CAN Wake-up mechanism
3 dominant pulses Wake-up mechanism
b3
0
Single dominant pulse Wake-up mechanism
1
CAN INT - Select the CAN failure detection reporting
Select INT generation when a bus failure is fully identified and decoded (i.e. after 5 dominant pulses on TxCAN)
Select INT generation as soon as a bus failure is detected, event if not fully identified
b0
0
1
Notes
41. The first time the device is set to Normal mode, the CAN is in Sleep Wake-up enabled (bit7 = 1, bit 6 =0). The next time the device is
set in Normal mode, the CAN state is controlled by bits 7 and 6.
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SERIAL PERIPHERAL INTERFACE
DETAIL OF CONTROL BITS AND REGISTER MAPPING
Table 35. I/O Register
MOSI Second Byte, bits 7-0
MOSI First byte [15-8]
[b_15 b_14] 10_001 [P/N]
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
01 10_ 001P
Default state
I/O-3 [1]
0
I/O-3 [0]
0
I/O-2 [1]
0
I/O-2 [0]
0
I/O-1 [1]
0
I/O-1 [0]
0
I/O-0 [1]
0
I/O-0 [0]
0
Condition for default
POR
Bits
Description
b7 b6
00
I/O-3 [1], I/O-3 [0] - I/O-3 pin operation
I/O-3 driver disable, Wake-up capability disable
I/O-3 driver disable, Wake-up capability enable.
I/O-3 HS driver enable.
01
10
I/O-3 HS driver enable.
11
I/O-2 [1], I/O-2 [0] - I/O-2 pin operation
I/O-2 driver disable, Wake-up capability disable
I/O-2 driver disable, Wake-up capability enable.
I/O-2 HS driver enable.
b5 b4
00
01
10
I/O-2 HS driver enable.
11
I/O-1 [1], I/O-1 [0] - I/O-1 pin operation
I/O-1 driver disable, Wake-up capability disable
I/O-1 driver disable, Wake-up capability enable.
I/O-1 LS driver enable.
b3 b2
00
01
10
I/O-1 HS driver enable.
11
I/O-0 [1], I/O-0 [0] - I/O-0 pin operation
I/O-0 driver disable, Wake-up capability disable
I/O-0 driver disable, Wake-up capability enable.
I/O-0 LS driver enable.
b1 b0
00
01
10
I/O-0 HS driver enable.
11
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Freescale Semiconductor
SERIAL PERIPHERAL INTERFACE
DETAIL OF CONTROL BITS AND REGISTER MAPPING
Table 36. INT Register
MOSI Second Byte, bits 7-0
MOSI First byte [15-8]
[b_15 b_14] 10_010 [P/N]
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
01 10_ 010P
Default state
CAN failure
0
MCU req
0
LIN2 fail
0
LIN1fail
0
I/O
0
SAFE
0
-
Vmon
0
0
Condition for default
POR
Bits
Description
CAN failure - control bit for CAN failure INT (CANH/L to GND, VDD or VSUP, CAN over-current, Driver Over-temp, TXD-PD,
RXD-PR, RX2HIGH, and CANBUS Dominate clamp)
b7
INT disable
0
1
INT enable.
MCU req - Control bit to request an INT. INT will occur once when the bit is enable
b6
0
INT disable
INT enable.
1
LIN2 fail - Control bit to enable INT when of failure on LIN2 interface
b5
0
INT disable
INT enable.
1
LIN/1 fail - Control bit to enable INT when of failure on LIN1 interface
b4
0
INT disable
INT enable.
1
I/O - Bit to control I/O interruption: I/O failure
b3
0
INT disable
INT enable.
1
SAFE - Bit to enable INT when of: Vaux over-voltage, VDD over-voltage, VDD Temp pre-warning, VDD under-voltage(42)
,
b2
SAFE resistor mismatch, RST terminal short to VDD, MCU request INT.(43)
INT disable
INT enable.
0
1
VMON - enable interruption by voltage monitoring of one of the voltage regulator: VAUX, 5 V-CAN, VDD (IDD Over-current, VSUV
SOV, VSENSELOW, 5V-CAN low or thermal shutdown, VAUX low or VAUX over-current
,
b0
V
INT disable
INT enable.
0
1
Notes
42. If VDD under-voltage is set to 70% of VDD, see bits b6 and b5 in Table 15 on page 69.
43. Bit 2 is used in conjunction with bit 6. Both bit 6 and bit 2 must be set to 1 to activate the MCU INT request.
33903/4/5
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SERIAL PERIPHERAL INTERFACE
DETAIL OF CONTROL BITS AND REGISTER MAPPING
Table 37. LIN/1 Register(45)
MOSI Second Byte, bits 7-0
MOSI First byte [15-8]
[b_15 b_14] 10_010 [P/N]
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
01 10_ 011P
Default state
LIN mode[1] LIN mode[0] Slew rate[1] Slew rate[0]
-
LIN T/1 on
0
-
V
ext
SUP
0
0
0
0
0
0
0
Condition for default
POR
Bits
Description
LIN mode [1], LIN mode [0] - LIN/1 interface mode control, Wake-up enable / disable
LIN/1 disable, Wake-up capability disable
not used
b7 b6
00
01
LIN/1 disable, Wake-up capability enable
LIN/1 Transmit Receive mode(44)
10
11
Slew rate[1], Slew rate[0] LIN/1 slew rate selection
Slew rate for 20 kbit/s baud rate
Slew rate for 10 kbit/s baud rate
Slew rate for fast baud rate
b5 b4
00
01
10
Slew rate for fast baud rate
11
LIN T/1 on
b2
0
LIN/1 termination OFF
LIN/1 termination ON
1
VSUP ext
b0
0
LIN goes recessive when device VSUP/2 is below typically 6.0 V. This is to meet J2602 specification
LIN continues operation below VSUP/2 6.0 V, until 5 V-CAN is disabled.
1
Notes
44. The LIN interface can be set in TXD/RXD mode only when the TXD-L input signal is in recessive state. An attempt to set TXD/RXD
mode, while TXD-L is low, will be ignored and the LIN interface remains disabled.
45. In order to use the LIN interface, the 5V-CAN regulator must be set to ON.
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SERIAL PERIPHERAL INTERFACE
DETAIL OF CONTROL BITS AND REGISTER MAPPING
Table 38. LIN2 Register(47)
MOSI Second Byte, bits 7-0
MOSI First byte [15-8]
[b_15 b_14] 10_010 [P/N]
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
01 10_ 100P
Default state
LIN mode[1] LIN mode[0] Slew rate[1] Slew rate[0]
-
LIN T2 on
0
-
V
ext
SUP
0
0
0
0
0
0
0
Condition for default
POR
Bits
Description
b7 b6
00
LIN mode [1], LIN mode [0] - LIN 2 interface mode control, Wake-up enable / disable
LIN2 disable, Wake-up capability disable
not used
01
LIN2 disable, Wake-up capability enable
LIN2 Transmit Receive mode(46)
10
11
Slew rate[1], Slew rate[0] LIN 2slew rate selection
Slew rate for 20 kbit/s baud rate
Slew rate for 10 kbit/s baud rate
Slew rate for fast baud rate
Slew rate for fast baud rate
LIN T2 on
b5 b4
00
01
10
11
b2
0
LIN 2 termination OFF
LIN 2 termination ON
1
VSUP ext
b0
0
LIN goes recessive when device VSUP/2 is below typically 6.0 V. This is to meet J2602 specification
LIN continues operation below VSUP/2 6.0 V, until 5 V-CAN is disabled.
1
Notes
46. The LIN interface can be set in TXD/RXD mode only when the TXD-L input signal is in a recessive state. An attempt to set TXD/RXD
mode while TXD-L is low, will be ignored and the LIN interface will remain disabled.
47. In order to use the LIN interface, the 5V-CAN regulator must be set to ON.
33903/4/5
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SERIAL PERIPHERAL INTERFACE
FLAGS AND DEVICE STATUS
FLAGS AND DEVICE STATUS
• - [0 0] for I/O real time status, device identification and
DESCRIPTION
CAN LIN driver receiver real time state.
• bit 13 to 9 are the register address from which the flags is
to be read.
• bit 8 = 1 (this is not parity bit function, as this is a read
command).
The table below is a summary of the device flags, I/O real
time level, device Identification, and includes examples of
SPI commands (SPI commands do not use parity functions).
They are obtained using the following commands.
This command is composed of the following:
bits 15 and 14:
When a failure event occurs, the respective flag is set and
remains latched until it is cleared by a read command
(provided the failure event has recovered).
• [1 1] for failure flags
Table 39. Device Flag, I/O Real Time and Device Identification
Bits
15-14
13-9
8
7
6
5
4
3
2
1
0
MOSI bits 15-7
MOSI
Next 7 MOSI bits (bits 6.0) should be “000_0000”
bits [15, Address
14] [13-9]
bit
7
bit 8
MISO bits [7-0], device response on MISO pin
8 Bits Device Fixed Status
(bits 15...8)
MISO
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
REG
11
0_1111
REG
1
0
1
V
V
5V
5V
5V
V
V
I
DD-OC-
AUX_LOW
AUX_OVER-
CURRENT
-CAN_
-CAN_
UV
-CAN_
SENSE_
LOW
SUP_
NORMAL
MODE
THERMAL
OVER-
UNDER-
SHUTDOWN
CURRENT
VOLTAGE
11
-
-
-
V
R
V
I
DD-OC-LP
DD_
ST_LOW
SUP_
V
ON
DD
MODE
(<100 ms)
THERMAL
BATFAIL
SHUTDOWN
Hexa SPI commands to get Vreg Flags: MOSI 0x DF 00, and MOSI Ox DF 80
(48)
CAN
11
1_0000
CAN
1
0
1
CAN
-
CAN Over- RXD low
temp
Rxd high
TXD dom
Bus Dom
clamp
CAN Over-
current
Wake-up
CAN_UF
CAN_F
CANL
to V
CANL to V
CANL to
GND
CANH to CANH to V
V
CANH to
GND
DD
DD
BAT
BAT
Hexa SPI commands to get CAN Flags: MOSI 0x E1 00, and MOSI 0x E1 80
00
11
1_0000
CAN
1
1
1
CAN Driver CANReceiver CAN WU
State
-
-
-
-
-
State
en/dis
Hexa SPI commands to get CAN real time status: MOSI 0x 21 80
I/O
1_0001
I/O
0
1
HS3 short to HS2 short to
SPI parity
error
CSB low
>2.0 ms
V
V
I/O_O thermal watchdog
SUP/2-UV
SUP/1-OV
GND
GND
flash mode
50%
I/O_1-3
I/O_0-2
SPI Wake-up
FWU
INT service LP V OFF Reset request Hardware
DD
Wake-up
Wake-up
Timeout
Leave Debug
Hexa SPI commands to get I/O Flags and I/O Wake-up: MOSI 0x E3 00, and MOSI 0x E3 80
00
11
1_0001
I/O
1
1
1
I/O_3
state
I/O_2
state
I/O_1 state
I/O_0 state
Hexa SPI commands to get I/O real time level: MOSI 0x 23 80
SAFE
1_0010
SAFE
0
1
INT request
RST high
DBG resistor
V
temp
V
UV
V
Over-
V
-
DD
DD
DD
AUX_OVER-
VOLTAGE
Pre-warning
voltage
-
-
-
V
low
V
low RST RST low
>100 ms
multiple
Resets
watchdog
refresh
failure
DD
DD
>100 ms
Hexa SPI commands to get INT and RST Flags: MOSI 0x E5 00, and MOSI 0x E5 80
00
1_0010
SAFE
1
1
V
(5.0 Vor
3.3 V)
device
p/n 1
device
p/n 0
id4
id3
id2
id1
id0
DD
Hexa SPI commands to get device Identification: MOSI 0x 2580
example: MISO bit [7-0] = 1011 0100: MC33904, 5.0 V version, silicon Rev. C (Pass 3.3)
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SERIAL PERIPHERAL INTERFACE
FLAGS AND DEVICE STATUS
Table 39. Device Flag, I/O Real Time and Device Identification
LIN/1
11
1_0011
LIN 1
1
0
-
LIN1
LIN1 Term
short to GND
LIN 1
RXD1 low
RXD1 high
TXD1 dom
LIN1 bus
dom clamp
Wake-up
Over-temp
Hexa SPI commands to get LIN 2 Flags: MOSI 0x E7 00
00
1_0011
LIN 1
1
1
LIN1 State
LIN1 WU
en/dis
-
-
-
-
-
-
Hexa SPI commands to get LIN1 real time status: MOSI 0x 27 80
LIN2
11
00
1_0100
LIN 2
1
1
0
1
-
LIN2
LIN2 Term
short to GND
LIN 2
RXD2 low
RXD2 high
TXD2 dom
LIN2 bus
dom clamp
Wake-up
Over-temp
Hexa SPI commands to get LIN 2 Flags: MOSI 0x E9 00
1_0100
LIN 2
LIN2 State
LIN2 WU
en/dis
-
-
-
-
-
-
Hexa SPI commands to get LIN2 real time status: MOSI 0x 29 80
Notes
48. Not available on “C” versions
Table 40. Flag Descriptions
Flag
Description
REG
VAUX_LOW
Description
Reports that VAUX regulator output voltage is lower than the VAUX_UV threshold.
Set / Reset condition
Description
Set: VAUX below threshold for t >100 s typically. Reset: VAUX above threshold and flag read (SPI)
Report that current out of VAUX regulator is above VAUX_OC threshold.
VAUX_OVER-
CURRENT
Set / Reset condition
Description
Set: Current above threshold for t >100 s. Reset: Current below threshold and flag read by SPI.
Report that the 5 V-CAN regulator has reached over-temperature threshold.
5 V-CAN_
Set / Reset condition
Set: 5 V-CAN thermal sensor above threshold. Reset: thermal sensor below threshold and flag read
(SPI)
THERMAL
SHUTDOWN
5V-CAN_UV
Description
Reports that 5 V-CAN regulator output voltage is lower than the 5 V-CAN UV threshold.
Set: 5V-CAN below 5V-CAN UV for t >100 s typically. Reset: 5V-CAN > threshold and flag read (SPI)
Report that the CAN driver output current is above threshold.
Set / Reset condition
Description
5V-can_
over-current
Set / Reset condition
Set: 5V-CAN current above threshold for t>100 s. Reset: 5V-CAN current below threshold and flag
read (SPI)
VSENSE_
Description
Reports that VSENSE pin is lower than the VSENSE LOW threshold.
Set / Reset condition
Set: VSENSE below threshold for t >100 s typically. Reset: VSENSE above threshold and flag read
LOW
(SPI)
VSUP_
Description
Reports that VSUP/1 pin is lower than the VS1_LOW threshold.
Set / Reset condition
Set: VSUP/1 below threshold for t >100 s typically. Reset: VSUP/1 above threshold and flag read (SPI)
UNDER-
VOLTAGE
IDD-OC-
Description
Report that current out of VDD pin is higher that IDD-OC threshold, while device is in Normal mode.
Set: current above threshold for t>100 s typically. Reset; current below threshold and flag read (SPI)
Report that the VDD has reached over-temperature threshold, and was turned off.
NORMAL MODE
Set / Reset condition
Description
VDD_
Set / Reset condition
Set: VDD OFF due to thermal condition. Reset: VDD recover and flag read (SPI)
THERMAL
SHUTDOWN
RST_LOW
Description
Report that the RST pin has detected a low level, shorter than 100 ms
(<100 ms)
Set / Reset condition
Description
Set: after detection of reset low pulse. Reset: Reset pulse terminated and flag read (SPI)
Report that the device voltage at VSUP/1 pin was below BATFAIL threshold.
Set: VSUP/1 below BATFAIL. Reset: VSUP/1 above threshold, and flag read (SPI)
VSUP_
Set / Reset condition
Description
BATFAIL
IDD-OC-LP
Report that current out of VDD pin is higher that IDD-OC threshold LP, while device is in LP V
mode.
ON
DD
V
DDON mode
Set / Reset condition
Set: current above threshold for t>100 s typically. Reset; current below threshold and flag read (SPI)
33903/4/5
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SERIAL PERIPHERAL INTERFACE
FLAGS AND DEVICE STATUS
Table 40. Flag Descriptions
Flag
Description
CAN
CAN driver
state
Description
Report real time CAN bus driver state: 1 if Driver is enable, 0 if driver disable
Set / Reset condition
Set: CAN driver is enable. Reset: CAN driver is disable. Driver can be disable by SPI command (ex
CAN set in RXD only mode) or following a failure event (ex: TXD Dominant). Flag read SPI command
(0x2180) do not clear the flag, as it is “real time” information.
CAN receiver Description
state
Report real time CAN bus receiver state: 1 if Enable, 0 if disable
Set / Reset condition
Set: CAN bus receiver is enable. Reset: CAN bus receiver is disable. Receiver disable by SPI
command (ex: CAN set in sleep mode). Flag read SPI command (0x2180) do not clear the flag, as it
is “real time” information.
CAN WU
enable
Description
Report real time CAN bus Wake-up receiver state: 1 if WU receiver is enable, 0 if disable
Set / Reset condition
Set: CAN Wake-up receiver is enable. Reset: CAN Wake-up receiver is disable. Wake-up receiver is
controlled by SPI, and is active by default after device Power ON. SPI command (0x2180) do not
change flag state.
CAN
Description
Report that Wake-up source is CAN
Wake-up
Set / Reset condition
Description
Set: after CAN wake detected. Reset: Flag read (SPI)
CAN Over-
temp
Report that the CAN interface has reach over-temperature threshold.
Set: CAN thermal sensor above threshold. Reset: thermal sensor below threshold and flag read (SPI)
Report that RXD pin is shorted to GND.
Set / Reset condition
Description
RXD low(49)
Set / Reset condition
Description
Set: RXD low failure detected. Reset: failure recovered and flag read (SPI)
Report that RXD pin is shorted to recessive voltage.
Rxd high
Set / Reset condition
Description
Set: RXD high failure detected. Reset: failure recovered and flag read (SPI)
Report that TXD pin is shorted to GND.
TXD dom
Set / Reset condition
Description
Set: TXD low failure detected. Reset: failure recovered and flag read (SPI)
Report that the CAN bus is dominant for a time longer than tDOM
Set: Bus dominant clamp failure detected. Reset: failure recovered and flag read (SPI)
Report that the CAN current is above CAN over-current threshold.
Set: CAN current above threshold. Reset: current below threshold and flag read (SPI)
Report that the CAN failure detection has not yet identified the bus failure
Set: bus failure pre detection. Reset: CAN bus failure recovered and flag read
Report that the CAN failure detection has identified the bus failure
Set: bus failure complete detetction.Reset: CAN bus failure recovered and flag read
Report CAN L short to VBAT failure
Bus Dom
clamp
Set / Reset condition
Description
CAN Over-
current
Set / Reset condition
Description
CAN_UF
Set / Reset condition
Description
CAN_F
Set / Reset condition
Description
CANL
to VBAT
Set / Reset condition
Set: failure detected. Reset failure recovered and flag read (SPI)
Report CANL short to VDD
CANL to VDD Description
Set / Reset condition
CANL to GND Description
Set / Reset condition
Description
Set / Reset condition
Set: failure detected. Reset failure recovered and flag read (SPI)
Report CAN L short to GND failure
Set: failure detected. Reset failure recovered and flag read (SPI)
Report CAN H short to VBAT failure
CANH
to VBAT
Set: failure detected. Reset failure recovered and flag read (SPI)
Report CANH short to VDD
CANH to VDD Description
Set / Reset condition
Description
Set / Reset condition
Set: failure detected. Reset failure recovered and flag read (SPI)
Report CAN H short to GND failure
CANH to
GND
Set: failure detected. Reset failure recovered and flag read (SPI)
Notes
49. Not available on “C” versions
33903/4/5
Analog Integrated Circuit Device Data
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SERIAL PERIPHERAL INTERFACE
FLAGS AND DEVICE STATUS
Table 40. Flag Descriptions
Flag
Description
I/O
HS3 short to
GND
Description
Report I/O-3 HS switch short to GND failure
Set / Reset condition
Description
Set: failure detected. Reset failure recovered and flag read (SPI)
Report I/O-2 HS switch short to GND failure
HS2 short to
GND
Set / Reset condition
Description
Set: failure detected. Reset failure recovered and flag read (SPI)
Report SPI parity error was detected.
SPI parity
error
Set / Reset condition
Description
Set: failure detected. Reset: flag read (SPI)
CSB low
>2.0 ms
Report SPI CSB was low for a time longer than typically 2.0 ms
Set: failure detected. Reset: flag read (SPI)
Set / Reset condition
Description
Report that V
is below V
threshold.
S2_LOW
V
SUP/2
SUP/2-UV
Set / Reset condition
Description
Set V
below V
thresh. Reset V
> V thresh and flag read (SPI)
S2_LOW
SUP/2
S2_LOW
SUP/2
Report that V
is above V
threshold.
V
SUP/1
S_HIGH
SUP/1-OV
Set / Reset condition
Set V
above V
threshold. Reset V
SUP/1
< V thresh and flag read (SPI)
S_HIGH
SUP/1
S_HIGH
I/O-0 thermal Description
Set / Reset condition
Report that the I/O-0 HS switch has reach over-temperature threshold.
Set: I/O-0 HS switch thermal sensor above threshold. Reset: thermal sensor below threshold and flag
read (SPI)
watchdog
flash mode
50%
Description
Set / Reset condition
Report that the watchdog period has reach 50% of its value, while device is in Flash mode.
Set: watchdog period > 50%. Reset: flag read
I/O-1-3 Wake- Description
up
Report that Wake-up source is I/O-1 or I/O-3
Set / Reset condition
Set: after I/O-1 or I/O-3 wake detected. Reset: Flag read (SPI)
Report that Wake-up source is I/O-0 or I/O-2
I/O-0-2 Wake- Description
up
Set / Reset condition
Set: after I/O-0 or I/O-2 wake detected. Reset: Flag read (SPI)
SPI Wake-up Description
Set / Reset condition
Description
Report that Wake-up source is SPI command, in LP V
ON mode.
DD
Set: after SPI Wake-up detected. Reset: Flag read (SPI)
Report that Wake-up source is forced Wake-up
FWU
Set / Reset condition
Description
Set: after Forced Wake-up detected. Reset: Flag read (SPI)
Report that INT timeout error detected.
INT service
Timeout
Set / Reset condition
Description
Set: INT service timeout expired. Reset: flag read.
LP VDD OFF
Report that LP V OFF mode was selected, prior Wake-up occurred.
DD
Set / Reset condition
Set: LP V
OFF selected. Reset: Flag read (SPI)
DD
Reset request Description
Set / Reset condition
Description
Report that RST source is an request from a SPI command (go to RST mode).
Set: After reset occurred due to SPI request. Reset: flag read (SPI)
Hardware
Report that the device left the Debug mode due to hardware cause (voltage at DBG pin lower than
typically 8.0 V).
Leave Debug
Set / Reset condition
Set: device leave debug mode due to hardware cause. Reset: flag read.
33903/4/5
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SERIAL PERIPHERAL INTERFACE
FLAGS AND DEVICE STATUS
Table 40. Flag Descriptions
Flag
Description
INT
INT request
Description
Report that INT source is an INT request from a SPI command.
Set: INT occurred. Reset: flag read (SPI)
Set / Reset condition
Description
RST high
Report that RST pin is shorted to high voltage.
Set / Reset condition
Description
Set: RST failure detection. Reset: flag read.
DBG resistor
Report that the resistor at DBG pin is different from expected (different from SPI register content).
Set: failure detected. Reset: correct resistor and flag read (SPI).
Report that the VDD has reached over-temperature pre-warning threshold.
Set / Reset condition
VDD TEMP PRE- Description
WARNING
Set / Reset condition
Set: VDD thermal sensor above threshold. Reset: VDD thermal sensor below threshold and flag read
(SPI)
VDD UV
Description
Reports that VDD pin is lower than the VDDUV threshold.
Set / Reset condition
Description
Set: VDD below threshold for t >100 s typically. Reset: VDD above threshold and flag read (SPI)
VDD OVER-
Reports that VDD pin is higher than the typically VDD + 0.6 V threshold. I/O-1 can be turned OFF if
this function is selected in INIT register.
VOLTAGE
Set / Reset condition
Description
Set: VDD above threshold for t >100 s typically. Reset: VDD below threshold and flag read (SPI)
VAUX_OVER-
Reports that VAUX pin is higher than the typically VAUX + 0.6 V threshold. I/O-1 can be turned OFF if
this function is selected in INIT register.
VOLTAGE
Set / Reset condition
Description
Set: VAUX above threshold for t >100 s typically. Reset: VAUX below threshold and flag read (SPI)
VDD LOW
>100 ms
Reports that VDD pin is lower than the VDDUV threshold for a time longer than 100 ms
Set / Reset condition
Description
Set: VDD below threshold for t >100 ms typically. Reset: VDD above threshold and flag read (SPI)
VDD LOW
Report that VDD is below VDD under-voltage threshold.
Set / Reset condition
Set: VDD below threshold. Reset: fag read (SPI)
VDD (5.0 V or Description
3.3 V)
0: mean 3.3 V VDD version
1: mean 5.0 V VDD version
Set / Reset condition
Description
N/A
Device P/N1
and 0
Describe the device part number:
00: MC33903
01: MC33904
10: MC33905S
11: MC333905D
Set / Reset condition
N/A
Device id 4 to Description
0
Describe the silicon revision number
10010: silicon revision A (Pass 3.1)
10011: silicon revision B (Pass 3.2)
10100: silicon revision C (Pass 3.3)
Set / Reset condition
Description
N/A
RST low
>100 ms
Report that the RST pin has detected a low level, longer than 100 ms (Reset permanent low)
Set: after detection of reset low pulse. Reset: Reset pulse terminated and flag read (SPI)
Set / Reset condition
Description
Multiple
Resets
Report that the more than 8 consecutive reset pulses occurred, due to missing or wrong watchdog
refresh.
Set / Reset condition
Description
Set: after detection of multiple reset pulses. Reset: flag read (SPI)
Report that a wrong or missing watchdog failure occurred.
Set: failure detected. reset: flag read (SPI)
watchdog
refresh failure
Set / Reset condition
33903/4/5
Analog Integrated Circuit Device Data
88
Freescale Semiconductor
SERIAL PERIPHERAL INTERFACE
FLAGS AND DEVICE STATUS
Table 40. Flag Descriptions
Flag
Description
LIN/1/2
LIN/1/2 bus
dom clamp
Description
Report that the LIN/1/2 bus is dominant for a time longer than tDOM
Set / Reset condition
Set: Bus dominant clamp failure detected. Reset: failure recovered and flag read (SPI)
LIN/1/2 State Description
Report real time LIN interface TXD/RXD mode. 1 if LIN is in TXD/RXD mode. 0 is LIN is not in TXD/
RXD mode.
Set / Reset condition
Set: LIN in TXD RXD mode. Reset: LIN not in TXD/RXD mode. LIN not in TXD/RXD mode by SPI
command (ex LIN set in Sleep mode) or following a failure event (ex: TxL Dominant). Flag read SPI
command (0x2780 or 0x2980) do not clear it, as it is “real time” flag.
LIN/1/2 WU
Description
Report real time LIN Wake-up receiver state. 1 if LIN Wake-up is enable, 0 if LIN Wake-up is disable
(means LIN signal will not be detected and will not Wake-up the device).
Set / Reset condition
Set: LIN WU enable (LIN interface set in Sleep mode Wake-up enable). Reset: LIN Wake-up disable
(LIN interface set in Sleep mode Wake-up disable). Flag read SPI command (0x2780 or 0x2980) do
not clear the flag, as it is “real time” information.
LIN/1/2
Description
Report that Wake-up source is LIN/1/2
Wake-up
Set / Reset condition
Set: after LIN/1/2 wake detected. Reset: Flag read (SPI)
Report LIN/1/2 short to GND failure
LIN/1/2 Term Description
short to GND
Set / Reset condition
Set: failure detected. Reset failure recovered and flag read (SPI)
Report that the LIN/1/2 interface has reach over-temperature threshold.
Set: LIN/1/2 thermal sensor above threshold. Reset: sensor below threshold and flag read (SPI)
Report that RXD/1/2 pin is shorted to GND.
LIN/1/2
Description
Over-temp
Set / Reset condition
Description
RXD-L/1/2
low
Set / Reset condition
Description
Set: RXD low failure detected. Reset: failure recovered and flag read (SPI)
Report that RXD/1/2pin is shorted to recessive voltage.
Set: RXD high failure detected. Reset: failure recovered and flag read (SPI)
Report that TXD/1/2 pin is shorted to GND.
RXD-L/1/2
high
Set / Reset condition
Description
TXD-L/1/2
dom
Set / Reset condition
Set: TXD low failure detected. Reset: failure recovered and flag read (SPI)
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
89
SERIAL PERIPHERAL INTERFACE
FLAGS AND DEVICE STATUS
One Byte
FIX AND EXTENDED DEVICE STATUS
Fix Status: when a device read operation is performed
(MOSI bits 15-14, bits C1 C0 = 00 or 11).
For every SPI command, the device response on MISO is
fixed status information. This information is either:
Two Bytes
Fix Status + Extended Status: when a device write
command is used (MOSI bits 15-14, bits C1 C0 = 01)
Table 41. Status Bits Description
Bits
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MISO
INT
WU
RST
CAN-G LIN-G
I/O-G SAFE-G VREG-G CAN-BUS CAN-LOC LIN2 LIN1 I/O-1 I/O-0 VREG-1 VREG-0
Bits
Description
Indicates that an INT has occurred and that INT flags are pending to be read.
Indicates that a Wake-up has occurred and that Wake-up flags are pending to be read.
Indicates that a reset has occurred and that the flags that report the reset source are pending to be read.
The INT, WU, or RST source is CAN interface. CAN local or CAN bus source.
The INT, WU, or RST source is LIN2 or LIN1 interface
INT
WU
RST
CAN-G
LIN-G
The INT, WU, or RST source is I/O interfaces.
I/O-G
The INT, WU, or RST source is from a SAFE condition
SAFE-G
VREG-G
CAN-LOC
CAN-BUS
LIN2
The INT, WU, or RST source is from a Regulator event, or voltage monitoring event
The INT, WU, or RST source is CAN interface. CAN local source.
The INT, WU, or RST source is CAN interface. CAN bus source.
The INT, WU, or RST source is LIN2 interface
The INT, WU, or RST source is LIN1 interface
LIN/LIN1
I/O-0
The INT, WU, or RST source is I/O interface, flag from I/O sub adress Low (bit 7 = 0)
The INT, WU, or RST source is I/O interface, flag from I/O sub adress High (bit 7 = 1)
The INT, WU, or RST source is from a Regulator event, flag from REG register sub adress high (bit 7 = 1)
The INT, WU, or RST source is from a Regulator event, flag from REG register sub adress low (bit 7 = 0)
I/O-1
VREG-1
VREG-0
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
90
TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
* Optional
5.0 V (3.3 V)
>2.2
Q2
RF module
Switch Detection Interface
eSwitch
F
<10 k
V
BAT
Safing Micro Controller
CAN xcvr
*
Q1
V
BAUX VAUX
VCAUX
D1
VE
V
SUP
V
SUP2
SUP1
V
B
22 F
100 nF
V
(50)
V
V
DD
DD
DBG
5V-CAN
>4.7 F
>1.0 F
1.0 k
22 k
RST
RST
INT
A/D
V
BAT
INT
V
SENSE
MUX
100 nF
100 nF
4.7 k *
I/O-0
V
MOSI
SCLK
MISO
CS
SUP
MCU
SPI
I/O-1
CANH
TXD
60
60
CAN
LIN1
RXD
SPLIT
CANL
4.7 nF
TXD-L1
RXD-L1
CAN BUS
VSUP1/2
LIN TERM1
TXD-L2
RXD-L2
LIN2
1.0 k
1.0 k
LIN BUS 1
VSUP1/2
LIN1
option 2
option 1
N/C
LIN TERM2
1.0 k
1.0 k
LIN BUS 1
LIN2
option 2
option 1
GND
SAFE
V
SUP
V
SUP
Safe Circuitry
Notes
50. Tested per specific OEM EMC requirements for CAN and LIN with additional
capacitor > 10 F on VSUP1/VSUP2 pins
Figure 42. 33905D Typical Application Schematic
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
91
TYPICAL APPLICATIONS
5.0 V (3.3 V)
Q2
RF module
Switch Detection Interface
eSwitch
Safing Micro Controller
CAN xcvr
>2.2 F
<10 k
V
BAT
Q1*
VBAUX VCAUX VAUX
D1
VE
V
VSUP2
VSUP1
DBG
SUP
VB
22 F
100 nF
(51)
VDD
VDD
>4.7 F
>1.0 F
5V-CAN
RST
INT
A/D
1.0 k
RST
V
BAT
INT
VSENSE
I/O-0
22 k
100 nF
100 nF
MUX
V
SUP
4.7 k *
MOSI
SCLK
MISO
CS
MCU
I/O-1
SPI
V
SUP
TXD
CAN
LIN1
I/O-3
RXD
CANH
TXD-L1
RXD-L1
60
60
SPLIT
CANL
4.7 nF
CAN BUS
LIN TERM1
VSUP1/2
1.0 k
option 1
1.0 k
option 2
LIN BUS 1
LIN1
GND
SAFE
V
SUP
V
SUP
Safe Circuitry
Notes
51. Tested per specific OEM EMC requirements for CAN and LIN with additional
capacitor > 10 F on VSUP1/VSUP2 pins
Figure 43. 33905S Typical Application Schematic
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
92
TYPICAL APPLICATIONS
* Optional
5V (3.3 V)
Q2
RF module
Switch Detection Interface
>2.2 F
<10 k
V
eSwitch
BAT
Q1*
>4.7 F
4.7 k *
Safing Micro Controller
CAN xcvr
VBAUX VCAUX VAUX VE
D1
V
SUP
VSUP2
VSUP1
VB
22 F
100 nF
(52)
VDD
VDD
DBG
>1.0 F
1.0 k
RST
RST
INT
A/D
5V-CAN
V
BAT
INT
VSENSE
I/O-0
MUX
100nF
22 k
MCU
MOSI
SCLK
MISO
CS
V
SUP
100 nF
SPI
I/O-1
V
BAT
22 k
TXD
CAN
I/O-2
V
RXD
SUP
100 nF
I/O-3
N/C
CANH
60
60
SPLIT
CANL
4.7 nF
CAN BUS
GND
SAFE
V
V
SUP
SUP
OR
function
Safe Circuitry
Notes
52. Tested per specific OEM EMC requirements for CAN and LIN with additional
capacitor > 10 F on VSUP1/VSUP2 pins
Figure 44. 33904 Typical Application Schematic
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
93
TYPICAL APPLICATIONS
V
BAT
D1
V
SUP
VSUP1
22 F
100 nF
VSUP2
DBG
VDD
VDD
(53)
>4.7 F
>1.0 F
RST
INT
RST
INT
5V-CAN
V
BAT
MOSI
SCLK
MISO
CS
MCU
I/O-0
SPI
22 k
100 nF
CANH
TXD
60
60
CAN
SPLIT
CANL
RXD
4.7 nF
N/C
CAN BUS
GND
SAFE
V
V
SUP
SUP
OR
function
Safe Circuitry
Notes
53. Tested per specific OEM EMC requirements for CAN and LIN with additional
capacitor > 10 F on VSUP1/VSUP2 pins
Figure 45. 33903 Typical Application Schematic
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
94
TYPICAL APPLICATIONS
V
BAT
*
Q1
* = Optional
D1
V
SUP
VSUP
VB
VE
22 F
100 nF
VDD
VDD
DBG
>4.7 F
>1.0 F
5V-CAN
1.0 k
22 k
V
RST
RST
INT
A/D
BAT
INT
VSENSE
100 nF
100 nF
MUX
IO-0
4.7 k (optional)
MOSI
SCLK
MISO
CS
CANH
SPLIT
CANL
LIN-T1
LIN1
SPI
MCU
60
60
4.7 nF
TXD
CAN BUS
CAN
LIN1
RXD
TXD-L1
RXD-L1
VSUP
LIN BUS 1
1.0 k
option1
1.0 k
TXD-L2
RXD-L2
option2
LIN2
LIN-T2
LIN2
VSUP
LIN BUS 2
1.0 k
1.0 k
V
SUP
V
SUP
GND
SAFE
option1
option2
Safe Circuitry
Notes
54. Tested per specific OEM EMC requirements for CAN and LIN with additional
capacitor > 10 F on VSUP pin
Figure 46. 33903D Typical Application Schematic
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
95
TYPICAL APPLICATIONS
V
BAT
*
Q1
* = Optional
D1
V
SUP
VSUP
VE VB
VDD
22 F
100 nF
VDD
DBG
>4.7 F
>1.0 F
5V-CAN
1.0 k
22 k
V
RST
RST
INT
A/D
BAT
INT
VSENSE
IO-0
100 nF
100 nF
MUX
V
SUP
4.7 k (optional)
MOSI
SCLK
MISO
CS
IO-3
SPI
MCU
CANH
SPLIT
CANL
LIN-T
LIN
TXD
CAN
LIN
RXD
60
60
TXD-L
RXD-L
4.7 nF
CAN BUS
VSUP
LIN BUS
1.0 k
option1
N/C
1.0 k
option2
V
SUP
V
SUP
GND
SAFE
Safe Circuitry
Notes
55. Tested per specific OEM EMC requirements for CAN and LIN with additional
capacitor > 10 F on VSUP pin
56. Leave N/C pins open.
Figure 47. 33903S Typical Application Schematic
33903/4/5
Analog Integrated Circuit Device Data
96
Freescale Semiconductor
TYPICAL APPLICATIONS
V
BAT
*
Q1
* = Optional
D1
V
SUP
VSUP
VE VB
VDD
22 F
100 nF
VDD
DBG
>4.7 F
>1.0 F
5V-CAN
1.0 k
22 k
V
RST
RST
INT
A/D
BAT
INT
VSENSE
IO-0
100 nF
100 nF
MUX
4.7 k (optional)
MOSI
SCLK
MISO
CS
V
BAT
SPI
MCU
22 k
100 nF
I/O-2
IO-3
V
SUP
TXD
CAN
RXD
CANH
SPLIT
CANL
60
60
4.7 nF
N/C
CAN BUS
V
SUP
V
SUP
GND
SAFE
Safe Circuitry
Notes
57. Tested per specific OEM EMC requirements for CAN and LIN with additional
capacitor > 10 F on VSUP pin
58. Leave N/C pins open.
Figure 48. 33903P Typical Application Schematic
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
97
TYPICAL APPLICATIONS
The following figure illustrates the application case
where two reverse battery diodes can be used for
optimization of the filtering and buffering capacitor at the
VDD pin. This allows using a minimum value capacitor at
the VDD pin to guarantee reset-free operation of the MCU
during the cranking pulse and temporary (50 ms) loss of the
supply.
V
BAT
Applications without an external ballast on V and
DD
without using the VAUX regulator are illustrated as well.
Q2
Q2
VBAT
5.0 V/3.3 V
5.0 V/3.3 V
D2
VBAT
VBAUX
C2
VCAUX
VBAUX
VAUX
VCAUX VAUX
VE
D1
Q1
Q1
VSUP2
VSUP1
VSUP2
VSUP1
VE
VB
D1
C1
VB
VDD
VDD
Partial View
ex1: Single VSUP Supply
Partial View
ex2: Split V
Supply
SUP
Optimized solution for cranking pulses.
C1 is sized for MCU power supply buffer only.
Q2
5.0 V/3.3 V
VBAT
VBAT
VBAUX
VCAUXVAUX
VE
VAUX
D1
VBAUX
VCAUX
D1
VSUP2
VSUP1
VE
VSUP2
VSUP1
VB
VB
VDD
VDD
Partial View
Partial View
ex 4: No External Transistor - No VAUX
ex 3: No External Transistor, VDD ~100 mA Capability
delivered by internal path transistor.
Figure 49. Application Options
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
98
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EK SUFFIX (PB-FREE)
32-PIN SOIC WIDE BODY
EXPOSED PAD
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REVISION HISTORY
REVISION HISTORY
REVISION
DATE
DESCRIPTION OF CHANGES
•
•
Initial Release - This document supersedes document MC33904_5.
Initial release of document includes the MC33903 part number, the VDD 3.3 V version description,
and the silicon revision rev. 3.2. Change details available upon request.
9/2010
4.0
•
•
•
•
•
•
•
•
Added Cyclic INT Operation During LP VDD ON Mode 48
12/2010
5.0
Changed VSUP pin to VSUP1 and pin 2 (NC) to VSUP2 for the 33903 device
Removed Drop voltage without external PNP pass transistor(19) 20 for V =3.3 V devices
DD
Added VSUP1-3.3 to VDD Voltage regulator, VDD pin 20.
Added Pull-up Current, TXD, VIN = 0 V 24 for V =3.3 V devices
DD
Revised MUX and RAM registers 67
Revised Status Bits Description 90
Added Entering into LP Mode Using Random Code 77.
•
Removed part numbers MCZ33905S3EK/R2, MCZ33904A3EK/R2 and MCZ33905D3EK/R2, and
added part numbers MCZ33903BD3EK/R2, MCZ33903BD5EK/R2, MCZ33903BS3EK/R2 and
MCZ33903BS5EK/R2.
4/2011
6.0
•
•
•
•
Voltage Supply was improved from 27V to 28V.
Changed Classification from Advance Information to Technical Data.
Updated Notes in Tables 8.
Revised Tables 8; Attenuation/Gain ratio for I/O-0 and I/O-1 actual voltage: to reflect a Typical
value.
•
•
Corrected typographical errors throughout.
Added Chip temperature: MUX-OUT voltage (guaranteed by design and characterization)
parameter to Tables 8.
•
Updated I/O pins (I/O-0: I/O-3) on page 36.
•
•
•
•
•
Updated VOUT-3.3 maximum
Updated tLEAD parameter
Added tCSLOW parameter
Updated the Detail Operation section to reflect the importance of acknowledging tLEAD and tCSLOW
Corrected typographical error in Tables 34 CAN REGISTER for Slew Rate bits b5,b4
9/2011
1/2011
7.0
8.0
.
•
•
•
•
•
•
•
•
Added 12 PCZ devices to the ordering information
Bit label change on Table 39 from INT to SAFE
Revised notes on Table 1 to include “C” version
Split Falling Edge of CS to Rising Edge of SCLK to differentiate the “C” version
Added “C” version note to Table 39 and Table 40
Added device ID 10100 Rev C, Pass 3.3 to Device id 4 to 0
Added Debug mode DBG voltage range parameter. Already detailed in text.
Added the MC33903P device, making additions throughout the document, where applicable.
2/2012
•
Changed all PC devices to MC devices.
9.0
33903/4/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
105
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