MMA1612NKW [FREESCALE]
DSI Inertial Sensor;
| 型号： | MMA1612NKW |
| 厂家： | 
Freescale |
| 描述： | DSI Inertial Sensor |
| 文件： | 总44页 (文件大小：415K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MMA16xxNKW
Rev. 4, 03/2012
Freescale Semiconductor
Data Sheet: Technical Data
DSI Inertial Sensor
The MMA16xxNKW family, a SafeAssure solution, includes the DSI2.5
compatible overdamped Z-axis satellite accelerometers.
MMA16xxNKW
Features
• ±50g to ±312.5g Nominal Full-Scale Range
Bottom View
• Selectable 180 Hz, 2-pole, 400 Hz, 4-pole, or 800 Hz, 4-pole LPF
• DSI2.5 Compatible with full support of Mandatory Commands
• 16 μs internal sample rate, with interpolation to 1 ms
• -40°C to 125°C Operating Temperature Range
• Pb-Free 16-Pin QFN, 6 by 6 Package
• Qualified AECQ100, Revision G, Grade 1 (-40°C to +125°C)
(http://www.aecouncil.com/)
16-PIN QFN
CASE 2086-01
Typical Applications
• Airbag Front and Side Crash Detection
Top View
ORDERING INFORMATION
Device
Axis
Z
Range
50g
Package
2086-01
2086-01
2086-01
2086-01
2086-01
2086-01
2086-01
2086-01
2086-01
2086-01
Shipping
Tubes
16 15 14 13
MMA1605NKW
MMA1606NKW
MMA1612NKW
MMA1618NKW
MMA1631NKW
MMA1605NKWR2
MMA1606NKWR2
MMA1612NKWR2
MMA1618NKWR2
MMA1631NKWR2
1
2
3
4
12
11
10
9
TEST2
TEST3
V
SSA
17
Z
62.5g
125g
187g
312g
50g
Tubes
C
REGA
Z
Tubes
TEST1
TEST4
Z
Tubes
BUSRTN
C
REG
Z
Tubes
5
6
7
8
Z
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Z
62.5g
125g
187g
312g
Z
Z
PIN CONNECTIONS
Z
For user register array programming, please consult your Freescale
representative.
© 2010-2012 Freescale Semiconductor, Inc. All rights reserved.
Application Diagram
BUSIN
TEST2
TEST1
BUSIN
TEST3MMA16xxN
C1
TEST4
BUSRTN
BUSRTN
TEST5
TEST6
TEST7
CREG
BUSOUT
HCAP
CREGA
C4
C5
C3
VSSA
VSS
PCM
Figure 1. Application Diagram
External Component Recommendations
Description
Ref Des
C1
Type
Ceramic
Purpose
100 pF ≤ C1 ≤ 1000 pF 10%, 50V, X7R BUSIN Power Supply Decoupling, ESD
C3
Ceramic, Tantalum
Ceramic
1 μF ≤ C3 ≤ 100 μF, 10%, 50V, X7R Reservoir Capacitor for Keep Alive during Signaling
C4
1 μF, 10%, 10V, X7R
1 μF, 10%, 10V, X7R
Voltage Regulator Output Capacitor (CREG
)
C5
Ceramic
Voltage Regulator Output Capacitor (CREGA)
Device Orientation
x x x x x x x
x x x x x x x
xxxxxxx
xxxxxxx
Z: 0 g
Z: 0 g
Z: +1 g
Z: -1 g
Z: 0 g
Z: 0 g
EARTH GROUND
Figure 2. Device Orientation Diagram
MMA16xxNKW
Sensors
Freescale Semiconductor, Inc.
2
Internal Block Diagram
HCAP
BUSIN
HCAP
CREG
DIGITAL
VOLTAGE
REGULATOR
VREG
ANALOG
VOLTAGE
REGULATOR
VREGA
CREGA
VSSA
VDSI_REF
VREF
REFERENCE
VOLTAGE
VDSI_REF
VSSB
LOW-VOLTAGE
RESET
TEST3
TEST4
BUSRTN
VSS
CONTROL
LOGIC
SERIAL
ENCODER
TEST
OTP
FUSE
ARRAY
TEST5
TEST6
OSCILLATOR
VREG
SELF-TEST
INTERFACE
CONTROL STATUS
OUT
IN
VREGA
VREG
DSP
IIR
SINC Filter
Low-Pass Filter
3
–D
ΣΔ
CONVERTER
Compensation
PCM Encoder
PCM
1 – z
---------------------------------
–1
D × (1 – z
)
Figure 3. Block Diagram
MMA16xxNKW
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Freescale Semiconductor, Inc.
3
1
Pin Connections
16 15 14 13
17
1
2
3
4
12
11
10
9
TEST2
TEST3
V
SSA
C
REGA
TEST1
TEST4
BUSRTN
C
REG
5
6
7
8
Figure 4. Block Diagram
Table 1. Pin Description
Pin
Pin
Formal Name
Definition
Name
1
2
3
4
TEST2
Test Pin
Test Pin
Test Pin
Ground
This pin must be left unconnected in the application.
This pin must be grounded in the application.
This pin must be grounded in the application.
This pin is the common return for power and signalling.
TEST3
TEST1
BUSRTN
PCM
Output
This pin provides a 4 MHz PCM signal proportional to the acceleration data for test purposes. The output can be enabled or
disabled via OTP. If unused, this pin must be left unconnected in the application. Reference Section 3.5.3.6.
5
6
7
PCM
VSSB
BUSIN
Ground
This pin must be grounded in the application.
Supply /
Comm
This pin is connected to the DSI positive bus node and provides the power supply and communication to the system master.
An external capacitor must be connected to between this pin and the BUSRTN pin. Reference Figure 1.
This pin rectifies the supply voltage on the BUSIN pin to create the supply voltage for the device. An external capacitor must
8
HCAP
Hold Capacitor be connected between this pin and the BUSRTN pin to store energy for operation during master communication signalling.
Reference Figure 1.
Digital
Supply
This pin is connected to the power supply for the internal digital circuitry. An external capacitor must be connected between
9
C
REG
this pin and V . Reference Figure 1.
SS
10
11
TEST4
Test Pin
This pin must be grounded in the application.
Analog
Supply
This pin is connected to the power supply for the internal analog circuitry. An external capacitor must be connected between
C
REGA
this pin and V
. Reference Figure 1.
SSA
12
13
VSSA
Analog GND
Test Pin
This pin is the power supply return node for analog circuitry.
This pin enables test mode, and provides the SPI programming voltage in test mode. This pin is must be grounded in the
application.
TEST5
14
15
16
17
TEST6
TEST7
Test Pin
Test Pin
This pin must be grounded in the application.
This pin must be grounded in the application.
V
Digital GND
This pin is the power supply return node for the digital circuitry.
SS
PAD
Die Attach Pad This pin is the die attach flag, and should be connected to VSS in the application. Reference Section 5.
Corner Pads The corner pads are internally connected to V
Corner
Pads
.
SS
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2
Electrical Characteristics
2.1
Maximum Ratings
Maximum ratings are the extreme limits to which the device can be exposed without permanently damaging it. Do not apply
voltages higher than those shown in the table below.
#
Rating
Symbol
Value
Unit
1
2
Supply Voltage (continuous) (BUSIN, HCAP)
Supply Voltage (pulsed < 400 ms, repetition rate 60s) (BUSIN, HCAP)
V
V
-0.3 to +30.0
-0.3 to +34.0
V
V
(3)
(3)
CC
CC
3
C
, C
PCM, TEST1, TEST2, TEST3, TEST4, TEST5, TEST6, TEST7
REGA,
-0.3 to +3.0
V
(3)
REG
BUSIN, BUSRTN and H
Current
CAP
4
5
Maximum duration 1s
Continuous
I
I
400
75
mA
mA
(3)
(3)
IN
IN
6
7
8
Powered Shock (six sides, 0.5 ms duration)
g
2000
2000
1.2
g
g
(5)
(5)
(5)
pms
Unpowered Shock (six sides, 0.5 ms duration)
g
shock
Drop Shock (to concrete, tile or steel surface, 10 drops, any orientation)
h
m
DROP
Electrostatic Discharge (per AECQ100)
HBM (100 pF, 1.5 kΩ)
CDM (R = 0Ω)
9
10
11
V
V
V
2000
500
200
V
V
V
(5)
(5)
(5)
ESD
ESD
ESD
MM (200pF, 0Ω)
Temperature Range
Storage
12
13
T
T
-40 to +125
-40 to +150
°C
°C
(3)
(3)
stg
Junction
J
14 Thermal Resistance
θ
2.5
°C/W
(11)
JC
2.2
Operating Range
The operating ratings are the limits normally expected in the application.
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified.
#
Characteristic
Symbol
Min
Typ
Max
Units
Supply Voltage
V
V
H
L
15
V
V
V
6.3
-0.3
⎯
⎯
30
30
V
V
(1,12)
(1,12)
HCAP
HCAP
16
17
18
BUSIN
BUS
Programming Voltage
Applied to BUSIN (DSI)
V
14.0
85
⎯
⎯
30.0
V
(3)
(3)
PP
Programming Current
BUSIN
I
⎯
mA
PP
T
-40
-40
T
H
+105
+125
L
Operating Temperature Range
19
20
T
A
⎯
⎯
°C
°C
(1)
(3)
T
A
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2.3
Electrical Characteristics - Supply and I/O
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified.
#
Characteristic
Symbol
Min
Typ
Max
Units
21 Quiescent Supply Current
*
I
⎯
⎯
8.0
mA
(1)
(3)
DD
Inrush Current (excluding HCAP Capacitor charge current)
Power On until V Stable
22
I
⎯
⎯
20
mA
REG
INRUSH
Internally Regulated Voltages
23
24
V
V
V
2.425
2.425
2.50
2.50
2.575
2.575
V
V
(1)
(1)
REG
REG
V
REGA
REGA
V
Under-Voltage Detection (See Figure 5)
HCAP
25
26
27
Under-Voltage Detection Threshold
V
V
V
5.8
⎯
70
6.0
⎯
100
6.2
6.3
140
V
V
mV
(3,6)
(3,6)
(3)
PORHCAP_f
PORHCAP_r
HYST_HCAP
V
Recovery Threshold
HCAP
Hysteresis (V
- V
)
PORHCAP_f
PORHCAP_r
Internal Regulator Low Voltage Detection Threshold
28
29
V
V
Falling
V
2.15
2.15
2.25
2.25
2.40
2.40
V
V
(3.6)
(3.6)
REG
PORVREG_f
Falling
V
REGA
PORVREGA_f
Hysteresis
30
31
V
V
V
0.05
0.05
0.10
0.10
0.15
0.15
V
V
(3)
(3)
REG
HYST_VREG
V
REGA
HYST_VREGA
External Capacitor (C
Capacitance
, C
)
REGA
REG
C
R
R
, C
REGA
REG
32
33
500
⎯
1000
⎯
1500
200
nF
mΩ
(9)
(9)
,
CREGESR
ESR (including interconnect resistance)
CREGAESR
Output High Voltage (PCM)
34 I
= 100 μA
V
V - 0.1
REG
⎯
⎯
⎯
V
V
(9)
(9)
Load
OH
Output Low Voltage (PCM)
35 I = 100 μA
V
⎯
0.1
Load
OL
Temperature Monitoring
36
37
Under-Temperature Monitor Threshold
Over-Temperature Monitor Threshold
T
T
⎯
155
⎯
⎯
-55
⎯
°C
°C
(9)
(9)
UNDER
OVER
2.4
Electrical Characteristics - DSI
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified
#
Characteristic
Symbol
Min
Typ
Max
Units
HCAP Rectifier Leakage Current
= 0V, V = 9.0V
38
V
*
I
⎯
⎯
100
μA
(1)
BUSIN
HCAP
RLKG
BUSIN to HCAP Rectifier Voltage Drop (V
= 7 V)
BUSIN
39
40
I
I
= -15 mA
= -100 mA
*
*
V
V
⎯
⎯
0.75
0.9
1.0
1.2
V
V
(1)
(1)
HCAP
HCAP
RECT
RECT
BUSIN Bias Current
41
42
V
V
= 8.0V, V
= 4.5V, V
= 9.0V
*
*
I
I
-100
-100
⎯
⎯
100
100
μA
μA
(1)
(1)
BUSIN
BUSIN
HCAP
HCAP
BUSIN_BIAS
BUSIN_BIAS
= 24V, No Response Current
BUSIN Response Current
= 4.0V
43
V
I
9.9
11
12.1
mA
(1)
BUSIN
RESP
BUSIN Logic Thresholds
Signal Threshold
44
45
*
*
V
V
2.8
5.5
3.0
6.0
3.2
6.5
V
V
(1)
(1)
THS
THF
Frame Threshold
BUSIN Logic Hysteresis
46
47
Signal
Frame
*
*
V
V
30
100
⎯
⎯
90
300
mV
mV
(3)
(3)
HYSS
HYSF
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2.5
Electrical Characteristics - Signal Chain
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified.
#
Characteristic
Symbol
Min
Typ
Max
Units
Sensitivity (10-bit @ 100 Hz referenced to 0 Hz)
*
*
*
*
48
50g Range
62.5g Range
125g Range
187g Range
SENS
SENS
SENS
SENS
SENS
⎯
⎯
⎯
⎯
⎯
10.24
8.192
4.096
2.731
1.638
⎯
⎯
⎯
⎯
⎯
LSB/g
LSB/g
LSB/g
LSB/g
LSB/g
(1,14)
(1,14)
(1,14)
(1,14)
(1,14)
49
50
51
52
*
312g Range
Total Sensitivity Error (including non-linearity)
53
54
T
T
= 25°C
A
ΔSENS_25
ΔSENS
-5
-7
⎯
⎯
+5
+7
%
%
(1)
(1)
*
*
A
L
≤ T ≤ T
H
Digital Offset
55
10-bit output
*
OFF
460
512
564
LSB
(1)
10Bit
Range of Output (10-Bit Mode)
Acceleration
56
57
RANGE
RANGE
1
⎯
⎯
0
1023
⎯
LSB
LSB
(3)
(3)
ACC
ERR
Internal Error
Cross-Axis Sensitivity
X-axis to Z-axis
58
59
V
V
-5
-5
—
—
+5
+5
%
%
(3)
(3)
XZ
YZ
Y-axis to Z-axis
60 ADC Output Noise Peak (1 Hz - 1 kHZ, 10-Bit)
61 System Output Noise (10-Bit, RMS, All Ranges)
62 Non-linearity (all ranges)
n
-4
⎯
-2
—
⎯
⎯
+4
+1.2
+2
LSB
LSB
%
(3)
(3)
(3)
SD
n
RMS
NL
OUT
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2.6
Electrical Characteristics - Self-Test and Overload
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified.
#
Characteristic
Symbol
Min
Typ
Max
Units
Acceleration (without hitting internal g-cell stops)
±50g, ±62.5g, ±125g Positive
63
64
g
g
425
-1205
642
-720
980
-512
g
g
(9)
(9)
g-cell_Clip60ZP
g-cell_Clip60ZN
±50g, ±62.5g, ±125g Negative
Acceleration (without hitting internal g-cell stops)
±187g, ±312g Positive
65
66
g
g
1450
-3100
2180
-2210
2800
-1800
g
g
(9)
(9)
g-cell_Clip240ZP
g-cell_Clip240ZN
±187g, ±312g Negative
ΣΔ and Sinc Filter Clipping Limit
±50g Range Positive
67
68
g
g
160
-333
238
-274
335
-216
g
g
(9)
(9)
ADC_Clip60ZP
ADC_Clip60ZN
±50g Range Negative
ΣΔ and Sinc Filter Clipping Limit
±62.5g Range Positive
69
70
g
g
160
-333
238
-274
335
-216
g
g
(9)
(9)
ADC_Clip60ZP
ADC_Clip60ZN
±62.5g Range Negative
ΣΔ and Sinc Filter Clipping Limit
±125g Range Positive
71
72
g
g
306
-693
433
-544
577
-415
g
g
(9)
(9)
ADC_Clip120ZP
ADC_Clip120ZN
±125g Range Negative
ΣΔ and Sinc Filter Clipping Limit
±187g Range Positive
73
74
g
g
836
-1909
1178
-1566
1599
-1245
g
g
(9)
(9)
ADC_Clip240ZP
ADC_Clip240ZN
±187g Range Negative
ΣΔ and Sinc Filter Clipping Limit
±312g Range Positive
75
76
g
g
836
-1909
1178
-1566
1599
-1245
g
g
(9)
(9)
ADC_Clip480ZP
ADC_Clip480ZN
±312g Range Negative
Deflection, 10-Bit, Self-Test - Offset, 30 sample ave, T = 25°C)
A
77
78
79
80
81
±50g Range
±62.5g Range
±125g Range
±187g Range
±312g Range
*
*
*
*
*
ΔDFLCT_Z50
ΔDFLCT_Z62
ΔDFLCT_Z125
ΔDFLCT_Z187
ΔDFLCT_Z312
⎯
⎯
⎯
⎯
⎯
307
245
299
205
123
⎯
⎯
⎯
⎯
⎯
LSB
LSB
LSB
LSB
LSB
(1)
(1)
(1)
(1)
(1)
82 Self-Test deflection range, T = 25 °C
ΔDFLCT
ΔDFLCT
-10
-20
⎯
⎯
+10
+20
%
%
(1)
(1)
A
83 Self-Test deflection range, T ≤ T ≤ T
H
L
A
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2.7
Dynamic Electrical Characteristics - DSI
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified
#
Characteristic
Symbol
Min
Typ
Max
Units
Reset Recovery (See Figure 20)
84
POR negated to 1st DSI Command (Initialization Command)
POR negated to Acceleration Data Valid (Including LPF Init)
DSI Clear Command to 1st DSI Command (Initialization Command)
DSI Clear Command to Acceleration Data Valid (Including LPF Init)
t
⎯
⎯
⎯
⎯
400 / f
⎯
10000 / f
⎯
s
s
s
s
(7)
(7)
(7)
(7)
DSI_INIT
OSC
85
86
87
t
⎯
400 / f
⎯
DSP_INIT
OSC
OSC
t
DSI_INIT
OSC
t
10000 / f
DSP_INIT
HCAP Under-Voltage Reset Delay (See Figure 5)
88 V
< V
to POR assertion
t
t
⎯
⎯
⎯
880 / f
⎯
⎯
5
s
(7)
(3)
(3)
HCAP
PORHCAP_f
HCAP_POR
OSC
V
89 V
Under-Voltage Reset Delay (See Figure 6)
REG
REG
< V
to POR assertion
μs
μs
PORVREG_f
VREG_POR
V
90 V
Under-Voltage Reset Delay (See Figure 7)
< V
REGA
REGA
to POR assertion
t
⎯
5
PORVREGA_f
VREGA_POR
V
91
92
, V
Capacitor Monitor
REGA
REG
POR to first Capacitor Test Disconnect
Disconnect Time ()
Disconnect Rate ()
t
⎯
⎯
⎯
12000 / f
6 / f
⎯
⎯
⎯
s
s
s
(7)
(7)
(7)
POR_CAPTEST
OSC
t
CAPTEST_TIME
OSC
93
t
256 / f
CAPTEST_RATE
OSC
94 Communication Data Rate
D
100
2.00
0.33
⎯
200
4.00
10.0
kbps
(7)
(7)
(3)
RATE
Loss of Signal Reset Time
95
96
Maximum time below frame threshold
t
⎯
⎯
ms
TO
BUSIN Response Current Slew Rate
1.0 mA to 9.0 mA, 9.0 to 1.0 mA
t
mA/μs
ITR
BUSIN Timing to Response Current
97
98
BUSIN Negative Voltage Transition = 3.0V to I
BUSIN Negative Voltage Transition = 3.0V to I
= 7.0 mA rise
= 5.0 mA fall
t
t
⎯
⎯
⎯
⎯
2.50
2.50
μs
μs
(7)
(7)
RSP
RSP
RSP_R
RSP_F
DSI BUSIN Signal Duty Cycle
99
100
Logic ‘0’
Logic ‘1’
*
*
D
10
60
33
67
40
90
%
%
(7)
(7)
CL
D
CH
Inter-frame Separation Time (See Figure 8)
Following Read Write NVM Command
Following Initialization
101
102
103
t
t
t
2
20
20
⎯
⎯
⎯
⎯
⎯
⎯
ms
μs
μs
(7)
(7)
(7)
IFS
IFS
IFS
Following other DSI bus commands
104 DSI Data Latency
OTP Program Timing
t
4 / f
⎯
5 / f
OSC
s
(7)
LAT_DSI
OSC
105
Time to program one OTP bit
t
64
⎯
256
μs
(7)
PROG_BIT
Self-Test Response Time
t
ST_ACT_180
106
107
108
109
110
111
Self-Test Activation time (EOF
Self-Test Deactivation time (EOF
Self-Test Activation time (EOF
Self-Test Deactivation time (EOF
Self-Test Activation time (EOF
Self-Test Deactivation time (EOF
to 90% ΔDFLCT_xxx, 180 Hz LPF)
to 10% ΔDFLCT_xxx, 180 Hz LPF)
2.00
2.00
1.00
1.00
0.50
0.50
⎯
⎯
⎯
⎯
⎯
⎯
5.00
5.00
2.50
2.50
1.75
1.75
ms
ms
ms
ms
ms
ms
(7)
(7)
(7)
(7)
(7)
(7)
Slave
t
ST_DEACT_180
Slave
t
ST_ACT_400
to 90% ΔDFLCT_xxx, 400 Hz LPF)
to 10% ΔDFLCT_xxx, 400 Hz LPF)
Slave
t
t
ST_DEACT_400
Slave
t
ST_ACT_800
to 90% ΔDFLCT_xxx, 800 Hz LPF)
Slave
ST_DEACT_800
to 10% ΔDFLCT_xxx, 800 Hz LPF)
Slave
Error Detection Response Time
112
Mirror Register CRC Error to Status Flag (S) set (Factory or User Array)
t
⎯
75 / f
⎯
s
(7)
CRC_Err
OSC
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2.8
Dynamic Electrical Characteristics - Signal Chain
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified
#
Characteristic
Symbol
Min
Typ
4
Max
Units
MHz
s
113 Internal Oscillator Frequency
114 Data Interpolation Latency
DSP Low-Pass Filter
*
f
3.80
4.20
(1)
(7)
OSC
t
64 / f
⎯
65 / f
OSC
LAT_INTERP
OSC
115
116
117
118
119
120
Cutoff frequency LPF0 (referenced to 0 Hz)
Filter Order LPF0
Cutoff frequency LPF1 (referenced to 0 Hz)
Filter Order LPF1
Cutoff frequency LPF2 (referenced to 0 Hz)
Filter Order LPF2
f
O
171
⎯
180
2
400
4
800
4
189
⎯
Hz
1
Hz
1
Hz
1
(7)
(7)
(7)
(7)
(7)
(7)
C_LPF0
LPF0
f
380
⎯
420
⎯
C_LPF1
O
LPF1
f
760
⎯
840
⎯
C_LPF2
O
LPF2
Sensing Element Rolloff Frequency (-3 db)
±50g, ±62.5g, ±125g
121
122
f
f
798
1437
⎯
⎯
2211
2425
Hz
Hz
(9)
(9)
gcell_3dB_zlo
gcell_3dB_zhi
±187g, ±312g
Sensing Element Natural Frequency
±50g, ±62.5g, ±125g
123
124
f
f
7000
13600
⎯
⎯
8000
15100
Hz
Hz
(9)
(9)
gcell_zlo
±187g, ±312g
gcell_zhi
Sensing Element Damping Ratio
±50g, ±62.5g, ±125g
±187g, ±312g
125
126
ζ
1.870
2.040
⎯
⎯
4.610
7.580
⎯
⎯
(9)
(9)
gcell_zlo
ζ
gcell_zhi
Sensing Element Delay (@100 Hz)
±50g, ±62.5g, ±125g
127
128
f
f
77
47
⎯
⎯
200
160
μs
μs
(9)
(9)
gcell_delay100_zlo
gcell_delay100_zhi
±187g, ±312g
129 Package Resonance Frequency
f
100
⎯
⎯
kHz
(9)
Package
Notes:
1. Parameters tested 100% at final test at -40°C, 25°C, and 105°C.
2. Parameters tested 100% at probe.
3. Verified by characterization.
4. * Indicates critical characteristic.
5. Verified by qualification testing, not tested in production.
6. Parameters verified by pass/fail testing in production.
7. Functionality guaranteed by modeling, simulation and/or design verification. Circuit integrity assured through IDDQ and scan testing. Timing
is determined by internal system clock frequency.
8. Verified by user system level characterization, not tested in production, or at component level.
9. Verified by Simulation.
10.Measured at final test. Self-Test activation occurs under control of the test program.
11.Thermal resistance between the die junction and the exposed pad; cold plate is attached to the exposed pad.
12.Maximum voltage characterized. Minimum voltage tested 100% at final test. Maximum voltage tested 100% to 24V at final test.
13.N/A.
14.Sensitivity, and overload capability specifications will be reduced when 800 Hz filter is selected.
15.Filter cutoff frequencies are directly dependent upon the internal oscillator frequency.
16.Target values. Actual values to be determined during device characterization.
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UV: UNDER-VOLTAGE CONDITION
EXISTS
VPORHCAP_r
VPORHCAP_f
VHCAP
VHYST_HCAP
UV
UV
tHCAP_POR
POR
Figure 5. VHCAP Under-Voltage Detection
VREG
VPORVREG_r
VPORVREG_f
VHYST_VREG
tVREG_POR
POR
Figure 6. VREG Under-Voltage Detection
VREGA
VPORVREGA_r
VPORVREGA_f
VHYST_VREGA
tVREGA_POR
POR
Figure 7. VREGA Under-Voltage Detection
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tSTART_master
VTHF
VTHS
BUSIN’
tIFS_master
tIFS_slave
LOGIC ‘1’
LOGIC ‘0’
tSTART_slave
EOFslave
9mA
1mA
IRESPONSE
tITR
tRSP_F
tITR
tRSP_R
tLAT_DSI
tLAT_INTERP
DSP_OUT
Figure 8. DSI Bus Inter-frame Timing
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3
Functional Description
3.1
User Accessible Data Array
A user accessible data array allows for each device to be customized. The array consists of an OTP factory programmable
array, an OTP user programmable array, and read-only registers for device status. The OTP arrays incorporate independent CRC
circuitry for fault detection (reference Section 3.2). Portions of the factory programmable array are reserved for factory-pro-
grammed trim values. The user accessible data is shown in the table below.
Table 2. User Accessible Data
Byte
Addr
RA[3:0]
Bit Function
Bit Function
Nibble Addr
WA[3:0]
Nibble Addr
(WA[3:0])
Register
Type
7
6
5
4
3
2
1
0
$00
$01
$02
$03
$04
$05
$06
$07
$08
$09
$0A
$0B
$0C
$0D
$0E
$0F
SN0
SN1
SN[7]
SN[15]
SN[6]
SN[14]
SN[22]
SN[30]
LPF[0]
SN[5]
SN[13]
SN[21]
SN[29]
0
SN[4]
SN[12]
SN[20]
SN[28]
0
SN[3]
SN[11]
SN[19]
SN[27]
RNG[3]
SN[2]
SN[10]
SN[18]
SN[26]
RNG[2]
SN[1]
SN[9]
SN[0]
SN[8]
F
SN2
SN[23]
SN[17]
SN[25]
RNG[1]
SN[16]
SN[24]
RNG[0]
SN3
SN[31]
TYPE
DEVCFG
DEVCFG1
DEVCFG2
UD01
LPF[1]
DEVID
UNUSED UNUSED UNUSED
UNUSED CRC_U[2] CRC_U[1] CRC_U[0]
UD00[5]
LOCK_U
UD01[7]
UD02[7]
UD03[7]
UD04[7]
UD05[7]
UD06[7]
UD07[7]
UD08[7]
UD00[4]
UNUSED
UD01[6]
UD02[6]
UD03[6]
UD04[6]
UD05[6]
UD06[6]
UD07[6]
UD08[6]
UD00[3]
PCM
UD00[2]
RESERVED
UD01[4]
UD02[4]
UD03[4]
UD04[4]
UD05[4]
UD06[4]
UD07[4]
UD08[4]
UD00[1]
ADDR[3]
UD01[3]
UD02[3]
UD03[3]
UD04[3]
UD05[3]
UD06[3]
UD07[3]
UD08[3]
UD00[0] AT_OTP[1] AT_OTP[0]
ADDR[2]
UD01[2]
UD02[2]
UD03[2]
UD04[2]
UD05[2]
UD06[2]
UD07[2]
UD08[2]
ADDR[1]
UD01[1]
UD02[1]
UD03[1]
UD04[1]
UD05[1]
UD06[1]
UD07[1]
UD08[1]
ADDR[0]
UD01[0]
UD02[0]
UD03[0]
UD04[0]
UD05[0]
UD06[0]
UD07[0]
UD08[0]
UD01[5]
UD02[5]
UD03[5]
UD04[5]
UD05[5]
UD06[5]
UD07[5]
UD08[5]
UD02
Reference
Table 39
Reference
Table 39
U/F
UD03
UD04
UD05
UD06
UD07
UD08
Type codes
F:
Freescale programmed OTP locationU/F:User and/or Freescale programmed OTP location.
Read-only registerU:User Programmed OTP location.
R:
Note: Unused and Unprogrammed Spare bits always read ‘0’.
3.1.1 Device Serial Number Registers
A unique serial number is programmed into the serial number registers of each device during manufacturing. The serial num-
ber is composed of the following information:
Bit Range
SN[12:0]
Content
Serial Number
Lot Number
SN[31:13]
Serial numbers begin at 1 for all produced devices in each lot, and are sequentially assigned. Lot numbers begin at 1 and are
sequentially assigned. No lot will contain more devices than can be uniquely identified by the 13-bit serial number. Depending on
lot size and quantities, all possible lot numbers and serial numbers may not be assigned.
The serial number registers are included in the factory programmed OTP CRC verification. Reference Section 3.2.1 for details
regarding the CRC verification. Beyond this, the contents of the serial number registers have no impact on device operation or
performance, and are only used for traceability purposes.
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3.1.2 Device Type Register (TYPE)
The Device Type Register is an OTP configuration register which contains device configuration information. Bit 5 - Bit 0 are
factory programmed and are included in the factory programmed OTP CRC verification. These bits are read only to the user.
Bit 7 - Bit 6 are user programmable OTP bits and are included in the user programmable OTP CRC verification.
Table 3. Factory Configuration Register
Location
RA[3:0] Register WA[3:0]
Bit
WA[3:0]
7
LPF[1]
0
6
LPF[0]
0
5
0
0
4
0
0
3
RNG[3]
0
2
RNG[2]
0
1
RNG[1]
0
0
RNG[0]
0
$04
TYPE
Bnk0 $08
Factory Default
3.1.2.1
The Low-Pass Filter selection bit selects between one of three low-pass filter options. These bits can be factory or user pro-
grammed.
Low-Pass Filter Selection Bits (LPF[1:0]) (TYPE[7:6])
LPF[1]
LPF[0]
Low-Pass Filter Selected
0
0
1
1
0
1
0
1
400 Hz, 4-Pole
1
Not Enabled
180 Hz, 2-Pole
800 Hz, 4-Pole
This filter option is not implemented. LPF[1:0] must not be set to this value to guarantee proper operation and performance.
3.1.2.2
Range Selection Bits (RNG[3:0]) (TYPE[3:0])
The Range Selection Bits indicate the full-scale range of the device, as shown below. These bits are factory programmed.
RNG[3] RNG[2] RNG[1] RNG[0]
Full-Scale Range
g-Cell Design
N/A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
N/A
N/A
N/A
50g
Medium-g
Medium-g
Medium-g
High-g
62g
125g
187g
312g
N/A
High-g
N/A
Reserved
N/A
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3.1.3 Device Configuration Register (DEVCFG)
The Device configuration register is a user programmable OTP register which contains device configuration information. This
register is included in the user register CRC check. Refer to Section 3.2.2 for details regarding the CRC for the user programma-
ble OTP array.
Table 4. Device Control Register
Location
RA[3:0] Register WA[3:0]
Bit
WA[3:0]
7
1
1
6
0
0
5
0
0
4
0
0
3
0
0
2
1
0
$05
DEVCFG
Bnk0 $0A
Bnk0 $09
CRC_U[2] CRC_U[1] CRC_U[0]
Factory Default
0
0
0
3.1.3.1
Device ID Bit (DEVCFG[7])
The Device ID Bit is a user programmable bit which allows the user to select between 2 device IDs. The Device ID is trans-
mitted in response to the Request ID DSI command. Reference Section 4.2.1.5 for more information regarding the Request ID
DSI command. This bit can be factory or user programmed.
DEVID
Device ID
‘00110’
0
1
‘00100’
3.1.3.2
User Configuration CRC (CRC_U[2:0], DEVCFG[2:0])
The User Configuration CRC bits contain the 3-bit CRC used for verification of the user programmable OTP array. Reference
Section 3.2.2 for details regarding the CRC for the user programmable OTP array. These bits can be factory or user programmed.
3.1.4 Device Configuration Register 1 (DEVCFG1)
The Device configuration register is a user programmable OTP register which contains device configuration information. This
register is included in the user register CRC check. Refer to Section 3.2.2 for details.
Table 5. Device Control Register 1
Location
RA[3:0] Register WA[3:0]
Bit
WA[3:0]
7
UD00[5]
0
6
UD00[4]
0
5
UD00[3]
0
4
UD00[2]
0
3
UD00[1]
0
2
1
0
$06
DEVCFG1
Bnk2 $06
Bnk1 $06
UD00[0] AT_OTP[1] AT_OTP[0]
Factory Default
0
0
0
3.1.4.1
User Specific Data 00 Bits (UD00[5:0], DEVCFG1[7:2])
The User Specific Data bits have no impact on the device function or performance. The bits can be programmed with user or
assembly specific information. These bits can be factory or user programmed.
3.1.4.2
Attribute Bits (AT_OTP[1:0], DEVCFG1[1:0])
The Attribute Bits are user defined bits which are transmitted in response to the Request Status, Disable Self-Test Stimulus or
Enable Self-Test Stimulus DSI commands. The transmitted values are qualified by the LOCK_U bit as shown in the table below.
These bits can be factory or user programmed.
DEVCFG1 Values
DSI Transmitted Values
LOCK_U
AT_OTP[1]
AT_OTP[0]
AT[1]
AT[0]
0
X
0
0
1
1
X
0
1
0
1
1
0
0
1
1
0
0
1
0
1
1
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3.1.5 Device Configuration 2 Register (DEVCFG2)
Device configuration register 2 is a user programmable OTP register which contains device configuration information. This
register is included in the user register CRC check. Refer to Section 3.2.2 for details regarding the CRC for the user programma-
ble OTP array.
Table 6. Device Control Register
Location
Bit
RA[3:0]
Register WA[3:0]
7
6
5
PCM
0
4
WA[3:0]
3
2
1
0
Bnk0 $07
Bnk2 $07
Bnk3 $07
Bnk3 $0F
RESERVED
0
$07
DEVCFG2
LOCK_U UNUSED
Bnk1 $07
ADDR[3] ADDR[2] ADDR[1] ADDR[0]
Factory Default
0
0
0
0
0
0
3.1.5.1
User Configuration Lock Bit (LOCK_U, DEVCFG2[7])
The LOCK_U bit is a factory or user programmed OTP bit which inhibits writes to the user configuration array when active.
Reference Section 3.2.2 for details regarding the LOCK_U bit and CRC verification.
3.1.5.2
PCM Bit (DEVCFG2[5])
The PCM Bit enables the PCM output pin. When the PCM bit is set, the PCM output pin is active and outputs a Pulse Code
Modulated signal proportional to the acceleration response. Reference Section 3.5.3.6 for more information regarding the PCM
output. When the PCM output is cleared, the PCM output pin is actively pulled low. This bit can be factory or user programmed.
3.1.5.3
Device Address (ADDR[3:0], DEVCFG2[3:0])
The Device Address bits define the preprogrammed DSI Bus device address. If the Device Address bits are programmed to
‘0000’, there is not preprogrammed address, and the address must be assigned via the Initialization DSI command. Reference
Section 4.2.1.1 for more details regarding the Initialization DSI command. These bits can be factory or user programmed.
3.1.6 User Data Registers (UDx)
The User Data Registers are user programmable OTP register which can be programmed with user or assembly specific in-
formation. These registers have no impact on the device performance, but are included in the user register CRC check. Refer to
Section 3.2.2 for details regarding the user register CRC check. These registers can be factory or user programmed.
Location
RA[3:0] Register WA[3:0]
Bit
7
6
5
4
WA[3:0]
Bnk1 $08
Bnk1 $09
Bnk1 $0A
Bnk1 $0B
Bnk1 $0C
Bnk1 $0D
Bnk1 $0E
Bnk1 $0F
3
2
1
0
$08
$09
$0A
$0B
$0C
$0D
$0E
$0F
UD01
UD02
UD03
UD04
UD05
UD06
UD07
UD08
Bnk2 $08
Bnk2 $09
Bnk2 $0A
Bnk2 $0B
Bnk2 $0C
Bnk2 $0D
Bnk2 $0E
Bnk2 $0F
UD01[7] UD01[6] UD01[5] UD01[4]
UD02[7] UD02[6] UD02[5] UD02[4]
UD03[7] UD03[6] UD03[5] UD03[4]
UD04[7] UD04[6] UD04[5] UD04[4]
UD05[7] UD05[6] UD05[5] UD05[4]
UD06[7] UD06[6] UD06[5] UD06[4]
UD07[7] UD07[6] UD07[5] UD07[4]
UD08[7] UD08[6] UD08[5] UD08[4]
UD01[3] UD01[2] UD01[1] UD01[0]
UD02[3] UD02[2] UD02[1] UD02[0]
UD03[3] UD03[2] UD03[1] UD03[0]
UD04[3] UD04[2] UD04[1] UD04[0]
UD05[3] UD05[2] UD05[1] UD05[0]
UD06[3] UD06[2] UD06[1] UD06[0]
UD07[3] UD07[2] UD07[1] UD07[0]
UD08[3] UD08[2] UD08[1] UD08[0]
Factory Default
0
0
0
0
0
0
0
0
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3.2
OTP Array Lock and CRC Verification
3.2.1 Factory Programmed OTP Array Lock and CRC Verification
The Factory programmed OTP array is verified for errors with a 3-bit CRC. The CRC verification is enabled only when the
Factory programmed OTP array is locked and the lock is active. The lock is active only after an automatic OTP readout in which
the internal lock bit is read as ‘1’. Automatic OTP readouts occur only after POR or a DSI Clear Command is received.
Lock Bit Value in Mirror Register
After Automatic Readout
CRC Verification
Enabled?
Factory Lock Bit Value in Fuse Array
Lock Bit Active?
0
1
1
N/A
0
NO
NO
NO
NO
1
YES
YES
The Factory programmed OTP array is locked by Freescale and will always be active after POR. The CRC is continuously
calculated on the factory programmed OTP array, which includes the registers listed below:
Register Name
Serial Number Registers
Register Addresses
SN0, SN1, SN2, SN3
TYPE[5:0]
Included in Factory CRC?
Yes
Yes
Yes
No
Type Register
Factory Programmable Device Configuration Bits
Factory OTP Array CRC
Internal Register Map
CRC_F[2:0]
Factory OTP Array Lock Bit
LOCK_F
No
Bits are fed in from right to left (LSB first), and top to bottom (lower addresses first) in the register map. The CRC verification
uses a generator polynomial of g(x) = X3 + X + 1, with a seed value = ‘111’. The calculated CRC is compared against the
CRC_F[2:0] bits. If a CRC mismatch is detected, an internal data error is set and the device responds to DSI messages as spec-
ified in Section 4.3. The CRC verification is completed on the memory registers which hold a copy of the fuse array values, not
the fuse array values.
3.2.2 User Programmable OTP Array Lock and CRC Verification
The User Programmable OTP array is independently verified for errors with a 3-bit CRC. The CRC verification is enabled only
when the User Programmable OTP array is locked and the lock is active. The lock is active only after an automatic OTP readout
in which the LOCK_U bit is read as ‘1’. Automatic OTP readouts occur only after POR or a DSI Clear Command is received.
Lock Bit Value in Mirror Register
After Automatic Readout
CRC Verification
Enabled?
Factory Lock Bit Value in Fuse Array
Lock Bit Active?
0
1
1
N/A
0
NO
NO
NO
NO
1
YES
YES
Once the LOCK_U bit is active, the CRC is continuously calculated on the user programmable OTP Array, which includes the
registers listed below:
Register Name
Type Register
Register Addresses
TYPE[7:6]
Included in User CRC?
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Device ID Bit
DEVCFG[7]: 1
User Data Register 0
Attribute Bits
DEVCFG1[7:2]: UD00[5:0]
DEVCFG1[1:0]: AT_OTP[1:0]
DEVCFG2[5]: PCM
DEVCFG2[4]
PCM Bit
RESERVED Bit
Device Address
DEVCFG2[3:0]: ADDR[3:0]
UD01 - UD08
User Data Registers 1 - 8
User Programmable OTP Array CRC
User Programmable OTP Array Lock Bit
DEVCFG[2:0]: CRC_U[2:0]
DEVCFG2[7]: LOCK_U
No
Bits are fed in from right to left (LSB first), and top to bottom (lower addresses first) in the register map. The CRC verification
uses a generator polynomial of g(x) = X3 + X + 1, with a seed value = ‘111’. The calculated CRC is compared against the user
programmed CRC, CRC_U[2:0], which is also included in the user programmable array. If a CRC mismatch is detected, an in-
ternal data error is set, and the device responds to DSI messages as specified in Section 4.3. The CRC verification is completed
on the memory registers which hold a copy of the fuse array values, not the fuse array values. Writes to the User Programmable
OTP array using the Write NVM Command will update the mirror registers and result in a change to the CRC calculation regard-
less of the state of the LOCK_U bit. A CRC mismatch will only be detected if the LOCK_U bit is active.
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3.3
Voltage Regulators
The device derives its internal supply voltage from the HCAP supply voltage. The device includes separate internal voltage
regulators for the analog (VREGA) and digital circuitry (VREG). External filter capacitors are required, as shown in Figure 1.
The voltage regulator module includes voltage monitoring circuitry which holds the device in reset following power-on until the
HCAP and internal voltages have stabilized sufficiently for proper operation. The voltage monitor asserts internal reset when the
HCAP supply or internally regulated voltages fall below predetermined levels. A reference generator provides a stable voltage
which is used by the ΣΔ converter.
VBUF
VOLTAGE
REGULATOR
HCAP
VREGA = 2.50 V
OSCILLATOR
TRIM
VOLTAGE
REGULATOR
CREGA
BIAS
GENERATOR
VREF
BANDGAP
REFERENCE
TRIM
ΣΔ
CONVERTER
VREF_MOD = 1.250 V
REFERENCE
GENERATOR
VBUF
OTP
ARRAY
V
REG = 2.50 V
VREGA
VOLTAGE
REGULATOR
CREG
DIGITAL
LOGIC
DSP
Digital Delay
HCAP
COMPARATOR
t
HCAP_POR
POR
Analog Filter Delay
V
REG
COMPARATOR
COMPARATOR
t
VREG_POR
Analog Filter Delay
V
REGA
t
VREG_POR
V
REF
Figure 9. Voltage Regulation and Monitoring
3.3.1 CREG and CREGA Regulator Capacitor
The internal regulator requires an external capacitor between the CREG pin and VSS pin, and the CREGA pin and VSSA pin for
stability. Figure 1 shows the recommended types and values for each of these capacitors.
3.3.2 VHCAP Voltage Monitor
The device includes a circuit to monitor the voltage on the HCAP pin. If the voltage falls below the specified threshold in Section
2, the device will be reset within the reset delay time (tHCAP_POR) specified in Section 2.7.
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3.3.3 VREG, and VREGA Under-Voltage Monitor
The device includes a circuit to monitor the internally regulated voltages (VREG and VREGA). If either of the internal regulator
voltages fall below the specified thresholds in Section 2, the device will be reset within the reset delay time (tVREG_POR
,
t
VREGA_POR) specified in Section 2.7.
3.3.4 VREG and VREGA Capacitance Monitor
A monitor circuit is incorporated to ensure predictable operation if the connection to the external CREG or CREGA capacitor
becomes open. At a continuous rate specified in Section 2.7 (tCAPTEST_RATE), both regulators are simultaneously disabled for a
short duration (tCAPTEST_TIME). If either of the external capacitors are not present, the associated regulator voltage will fall below
the internal reset threshold, forcing a device reset.
tCAPTEST_RATE
tCAPTEST_TIME
CAP_Test
VREG
Capacitor Present
Capacitor Open
VPORVREG_f
POR
Time
Figure 10. VREG Capacitor Monitor
tCAPTEST_RATE
tCAPTEST_TIME
CAP_Test
VREGA
Capacitor Present
Capacitor Open
VPORREGA_f
POR
Time
Figure 11. VREGA Capacitor Monitor
3.4
Internal Oscillator
The device includes a factory trimmed oscillator as specified in Section 2.8.
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3.5
Acceleration Signal Path
3.5.1 Transducer
The device transducer is an overdamped mass-spring-damper system described by the following transfer function:
where:
2
n
ω
H(s) = ------------------------------------------------------
2
2
n
s + 2 ⋅ ξ ⋅ ω ⋅ s + ω
n
ζ = Damping Ratio
ωn = Natural Frequency = 2∗Π∗fn
Reference Section 2.8 for transducer parameters.
3.5.2 ΣΔ Converter
The sigma delta converter provides the interface between the g-cell and the DSP block. The output of the ΣΔ converter is a
data stream at a nominal frequency of 1 MHz.
g-cell
CTOP
1-BIT
QUANTIZER
FIRST
INTEGRATOR
SECOND
INTEGRATOR
VX
α1=
α2
CINT1
z-1
z-1
ΣΔ_OUT
1 - z-1
1 - z-1
CBOT
ADC
DAC
V = ΔC x VX / CINT1
ΔC = CTOP - CBOT
β1
β2
V = 2 × VREF
Figure 12. ΣΔ Converter Block Diagram
3.5.3 Digital Signal Processing Block
A digital signal processing (DSP) block is used to perform signal filtering and compensation operations. A diagram illustrating
the signal processing flow within the DSP block is shown in Figure 13.
ΣΔ_OUT
A
F
Low-Pass Filter
Sinc Filter
B
D
E
C
3
–D
–1
+ (n ⋅ z ) + (n ⋅ z
–2
–1
+ (n ⋅ z ) + (n ⋅ z
–2
Output
Scaling
1 – z
OUTPUT
n
)
n
)
Interpolation
Compensation
---------------------------------
11
12 13
21
22 23
----------------------------------------------------------------------------- ----------------------------------------------------------------------------
a
⋅
⋅
–1
0
D × (1 – z
)
–1
–2
–1
–2
d
+ (d ⋅ z ) + (d ⋅ z
)
d
+ (d ⋅ z ) + (d ⋅ z
)
11
12 13
21
22 23
Figure 13. Signal Chain Diagram
Table 7. Signal Chain Characteristics
Sample Time
Data Width
(Bits)
Over Range Signal Width Signal Noise Signal Margin Typical Block
Description
Reference
(μs)
(Bits
(Bits)
(Bits)
(Bits)
Latency
A
B
ΣΔ
1
1
1
Section 3.5.2
112/f
osc
SINC Filter
16
20
12
4
4
3
Section 3.5.3.1
Reference
Section 3.5.3.2
C
D
Low-pass Filter
16
16
26
26
1
4
12
10
9
9
Section 3.5.3.2
Section 3.5.3.3
Compensation
DSP Sampling
24/f
osc
E
F
16
1
10
10
4/f
Section 3.5.3.5
Section 3.5.3.5
osc
10-Bit Output Scaling
Interpolation
64/f
osc
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3.5.3.1
Decimation Sinc Filter
The serial data stream produced by the ΣΔ converters is decimated and converted to parallel values by a 3rd order 16:1 sinc
filter with a decimation factor of 16.
3
–16
1 – z
----------------------------------
H(z) =
–1
16 × (1 – z
)
Figure 14. Sinc Filter Response, tS = 16 μs
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3.5.3.2
Low-Pass Filter
Data from the Sinc filter is processed by an infinite impulse response (IIR) low-pass filter.
0
–1
–2
0
–1
–2
(n ⋅ z ) + (n ⋅ z ) + (n ⋅ z ) (n ⋅ z ) + (n ⋅ z ) + (n ⋅ z
)
11 12 13
21 22 23
-------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------
H(z) = a ⋅
⋅
0
0
–1
–2
0
–1
–2
(d ⋅ z ) + (d ⋅ z ) + (d ⋅ z ) (d ⋅ z ) + (d ⋅ z ) + (d ⋅ z
11 12 13
11 22 23
)
The device provides the option for one of three low-pass filters. The filter is selected with the LPF[1:0] bits in the TYPE register.
The filter selection options are listed in Section 3.1.2.1, Table 8. Response parameters for the low-pass filter are specified in
Section 2.8. Filter characteristics are illustrated in the figures below.
Table 8. Low-Pass Filter Coefficients
Description
Filter Coefficients
Group Delay
a
0.000534069200512
0
n
n
n
n
n
n
0.25
d
d
d
d
d
d
1
11
12
13
21
22
23
11
12
13
21
22
23
0.499999985098839
0.25
-1.959839582443237
180 Hz LPF
0.960373640060425
4608/f
3392/f
1728/f
osc
osc
osc
1
1
0
0
0
0
a
0.003135988372378
0.000999420881271
0.001998946070671
0.000999405980110
0.250004753470421
0.499986037611961
0.250009194016457
0.011904109735042
0.003841564059258
0.007683292031288
0.003841534256935
0.250001862645149
0.499994158744812
0.250003993511200
0
n
n
n
n
n
n
d
d
d
d
d
d
1.0
11
12
13
21
22
23
11
12
13
21
22
23
-1.892452478408814
0.89558845758438
1.0
400 Hz LPF
-1.919075012207031
0.923072755336761
a
0
n
n
n
n
n
n
d
d
d
d
d
d
1.0
11
12
13
21
22
23
11
12
13
21
22
23
-1.790004611015320
0.801908731460571
1.0
800 Hz LPF
-1.836849451065064
0.852215826511383
Note: Low-Pass Filter Figures do not include g-cell frequency response.
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Figure 15. Low-Pass Filter Characteristics: fC = 180 Hz, 2-Pole, tS = 16 μs
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Figure 16. Low-Pass Filter Characteristics: fC = 400 Hz, 4-Pole, tS = 16 μs
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Figure 17. Low-Pass Filter Characteristics: fC = 800 Hz, 4-Pole, tS = 16 μs
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3.5.3.3
Compensation
The device includes internal compensation circuitry to compensate for sensor offset, sensitivity and non-linearity.
3.5.3.4
Data Interpolation
The device includes 16 to 1 linear data interpolation to minimize the system sample jitter. Each result produced by the digital
signal processing chain is delayed one sample time. On reception of an acceleration data request, the transmitted data is inter-
polated from the two previous samples, resulting in a latency of one sample time, and a maximum signal jitter of ±1/16 of a sample
time. Reference Figure 8 for more information regarding interpolation and data latency.
3.5.3.5
Output Scaling
The 26 bit digital output from the DSP is clipped and scaled to a 10-bit or 8-bit word which covers the acceleration range of
the device. Figure 18 shows the method used to establish the acceleration data word from the 26-bit DSP output.
Over Range
Signal
Noise
Margin
D2 D1 D0
D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8
...
10-Bit Data Word
9-Bit Data Word
8-Bit Data Word
D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
D21 D20 D19 D18 D17 D16 D15 D14 D13
D21 D20 D19 D18 D17 D16 D15 D14
Using Truncation
Using Truncation
Using Truncation
Figure 18. Output Scaling Diagram
3.5.3.6
PCM Output Function
The device provides the option for a PCM output function. The PCM output is activated if the PCM bit is set in the DEVCFG2
register. When the PCM function is enabled, a 4 MHz Pulse Code Modulated signal proportional to the upper 9 bits of the accel-
eration response is output onto the PCM pin. The PCM output is intended for test use only. A block diagram of the PCM output
is shown in Figure 19.
Output Scaling
D_x[9:1]
A
CARRY
PCM
9
9 Bit ADDER
9
Sample updated every 16μS
B
SUM
D
FF
Q
CLK
fCLK = 4 MHz
Q
9
Figure 19. PCM Output Function Block Diagram
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3.6
Device Initialization
Following powerup, under-voltage reset or reception of a DSI Clear Command, the device proceeds through an initialization
process as described in the following tables:
Table 9. Powerup or Under-Voltage Reset Initialization Process
#
1
3
Description
Power up to a Known State
Time
S Flag ST Flag
DSI Response
No Response
No Response
0
N/A
1
N/A
0
Read Fuse Array and Copy to Memory Array (Mirror Registers)
Initialize DSI State Machine (the device is ready for DSI Messages)
Initialize the DSP (Acceleration Data is Valid)
DSI Read Acceleration Data Short response = zero.
DSI Read Acceleration Data Long response = invalid data.
4
5
t
1
0
0
0
DSI_INIT
t
Normal
DSP_INIT
Table 10. DSI Clear Command Initialization Process
#
1
3
Description
the device logic comes out of reset
Time
S Flag ST Flag
DSI Response
No Response
No Response
0
1
1
0
0
Read Fuse Array and Copy to Memory Array (Mirror Registers)
Initialize DSI State Machine (the device is ready for DSI Messages)
Initialize the DSP (Acceleration Data is Valid)
DSI Read Acceleration Data Short response = zero.
DSI Read Acceleration Data Long response = invalid data.
4
5
t
1
0
0
0
DSI_INIT
t
Normal
DSP_INIT
BUSIN’
VPORHCAP_r
VHCAP
VPORVREG_r
VREG
VPORVREGA_r
VREGA
POR
Internal Delay
tINT_INIT
DSI Ready
DSP_OUT
tDSI_INIT
tDSP_INIT
Figure 20. Initialization Timing
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3.7
Overload Response
3.7.1 Overload Performance
The device is designed to operate within a specified range. However, acceleration beyond that range (overload) impacts the
operating range output of the sensor. Acceleration beyond the range of the device can generate a DC shift at the output of the
device that is dependent upon the overload frequency and amplitude. The device g-cell is overdamped, providing the optimal
design for overload performance. However, the performance of the device during an overload condition is affected by many other
parameters, including:
• g-cell damping
• Non-linearity
• Clipping limits
• Symmetry
Figure 21 shows the g-cell, Sigma Delta, and output clipping of the device over frequency. The relevant parameters are spec-
ified in Section 2.
Acceleration (g)
g-cellRolloff
Region Clipped
LPFRolloff
by Output
Determined by g-cell
roll-off and ADC clipping
gg-cell_Clip
Determined by g-cell
roll-off and full-scale range
gADC_Clip
gRange_Norm
Region of Interest
fLPF
Region of No Signal Distortion Beyond
Specification
fg-Cell
5kHz
10kHz
Frequency (kHz)
Figure 21. Output Clipping Vs. Frequency
3.7.2 Sigma Delta Overrange Response
Overrange conditions exist when the signal level is beyond the full-scale range of the device but within the computational limits
of the DSP. The ΣΔ converter can saturate at levels above those specified in Section 2 (GADC_CLIP). The DSP operates predict-
ably under all cases of overrange, although the signal may include residual high frequency components for some time after re-
turning to the normal range of operation due to non-linear effects of the sensor.
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4
DSI Protocol Layer
4.1
Communication Interface Overview
The device is compatible with the DSI Bus Standard V2.5.
4.1.1 DSI Physical Layer
Reference DSI Bus Standard V2.5, Section 3 for information regarding the physical layer.
4.1.2 DSI Data Link Layer
Reference DSI Bus Standard,V2.5, Section 4 for information regarding the DSI data link layer. The sections below describe
the DSI data link layer features supported.
4.2
DSI Protocol
4.2.1 DSI Bus Commands
DSI Bus Commands are summarized in Table 11. The device supports only the command formats specified in Section 4.2.1.
The device will ignore commands of any other format. If a CRC error is detected, or a reserved or un-implemented command is
received, the device will not respond.
Following all messages, the device requires a minimum inter-frame separation (tIFS). As long as the minimum inter-frame sep-
aration times defined in Section 4.2.1 are met, all supported commands are guaranteed to be executed, and the device will be
ready for the next message. The device will respond as appropriate during the subsequent DSI transfer. Exactly one response
is attempted.
Table 11. DSI Bus Command Summary
Command
C3 C2 C1 C0 Hex
$0 Initialization
$1 Request Status
Command Format
Data
Description
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Standard Long Only
NV
⎯
⎯
BS
⎯
⎯
Bnk[1] Bnk[0] PA[3] PA[2] PA[1] PA[0]
Standard/Enhanced L/S
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
$2 Read Acceleration Data Standard/Enhanced L/S
$3 Not Implemented Not Implemented
$4 Request ID Information Standard/Enhanced L/S
Not Implemented
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
$5 Not Implemented
$6 Not Implemented
$7 Clear
Not Implemented
Not Implemented
Not Implemented
Not Implemented
Standard/Enhanced L/S
Not Implemented
⎯
⎯
$8 Not Implemented
$9 Read Write NVM
$A Format Control
$B Read Register Data
$C Disable Self-Test
$D Activate Self-Test
$E Not Implemented
$F Reverse Initialization
Not Implemented
Standard/Enhanced L WA[3] WA[2] WA[1] WA[0] RD[3] RD[2] RD[1] RD[0]
Standard/Enhanced L
Standard/Enhanced L
Standard/Enhanced L/S
Standard/Enhanced L/S
Not Implemented
R/W
0
FA[2] FA[1] FA[0] FD[3] FD[2] FD[1] FD[0]
0
0
0
RA[3] RA[2] RA[1] RA[0]
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Not Implemented
Not Implemented
Not Implemented
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4.2.1.1
Initialization Command
The initialization command conforms to the description provided in Section 6.1.1 of the DSI Bus Standard V2.5. The initializa-
tion command is only supported as a standard long command. No other commands are recognized by the device until a valid
standard long initialization command is received.
Table 12. Initialization Command
Data
D[4] D[3]
Address
Command
CRC
D[7]
D[6]
D[5]
D[2]
D[1]
D[0]
A[3]
A[2]
A[1]
A[0]
C[3]
C[2]
C[1]
C[0]
NV
BS
Bnk[1] Bnk[0] PA[3]
PA[2]
PA[1]
PA[0]
A[3]
A[2]
A[1]
A[0]
0
0
0
0
4 bits
Table 13. Initialization Command Bit Definitions
Bit Field
Definition
C[3:0]
Initialization Command = ‘0000’
DSI device address. This address is set to the preprogrammed device address following reset, or to ‘0000’ if no preprogrammed address
has been assigned.
A[3:0]
PA[3:0]
DSI Address to be programmed.
These bits select the bank address for the user writable data registers. Bank selection affects the Read/Write NVM command operation.
Invalid combinations of B1 and B0 result in no response from the device to the associated initialization. Refer to Section 4.2.1.10 for fur-
ther details regarding register programming and bank selection.
Bnk[1:0]
BS
No bus switch is included in the device:
1 - the device is Reset.
0 - Normal Operation
NVM Program Enable. This bit enables programming of the user-programmed OTP locations. Data to be programmed is transferred to the
device during subsequent Read Write NVM commands.
1 - Enable OTP programming
NV
0 - Disable OTP programming
If the BS bit is set in the initialization command, the device will be reset within tBSOPEN.
If the device has been preprogrammed, PA[3:0] and A[3:0] must match the preprogrammed address.
If no device address has been previously programmed into the OTP array, PA[3:0] contains the device address, and A[3:0]
must be zero. If either addressing condition is not met, the device address is not assigned, and the device will not respond to the
Initialization command. If the addressing conditions are met, the new device address is assigned to A[3:0]. Once the device ad-
dress is assigned, the new address (A[3:0]) is not protected by the User Programmable OTP Array CRC Verification. The User
Programmable OTP array CRC is calculated and verified using the OTP programmed values of A[3:0] = ‘0000’.
Once initialized, the device will no longer recognize or respond to Initialization commands.
Table 14. Initialization Command Response
Response
CRC
D[15] D[14] D[13] D[12] D[11] D[10] D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
PA[3]
PA[2]
PA[1]
PA[0]
0
0
0
BF
NV
0
Bnk[1] Bnk[0] PA[3]
PA[2]
PA[1]
PA[0]
4 bits
Table 15. Initialization Response Bit Definitions
Bit Field
Definition
DSI device address. This field contains the device address. If the device is unprogrammed when the initialization command is issued, the
device address is assigned. This field contains the programmed address. An Initialization command which attempts to assign a device
address of zero is ignored.
PA[3:0]
Bnk[1:0]
NV
These bits select the bank address for the user writable data registers. Bank selection affects the Read/Write NVM command operation.
Invalid combinations of B1 and B0 result in no response from the device to the associated initialization. Refer to Section 4.2.1.10 for fur-
ther details regarding register programming and bank selection.
NVM Program Enable. This bit indicates if programming of the user-accessible OTP is enabled.
1 - OTP programming Enabled
0 - OTP programming Disabled
This bit indicates the success or failure of the bus test performed as part of the Initialization command.
BF
1 - Bus fault detected
0 - Bus test passed
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4.2.1.2
Request Status Command
The Request Status command is supported in the following command formats:
• Standard Long Command
• Standard Short Command
• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11)
• Enhanced Short Command as configured by the Format Control Command (Reference Section 4.2.1.11)
The device ignores the Request Status command if the DSI device address is set to the DSI Global Device Address of ‘0000’.
The data bits D[7:0] in the command are only used in the CRC calculation.
Table 16. Request Status Command
Data
Address
Command
CRC
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
A[3]
A[2]
A[1]
A[0]
C[3]
C[2]
C[1]
C[0]
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
A[3]
A[2]
A[1]
A[0]
0
0
0
1
0 to 8 bits
Table 17. Request Status Command Bit Definitions
Bit Field
Definition
C[3:0]
A[3:0]
D[7:0]
Request Status Command = ‘0001’
DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the
command is ignored.
Used for CRC calculation only
Table 18. Short Response - Request Status Command
Response
CRC
D[14] D[13] D[12] D[11] D[10] D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
0
0
0
0
0
0
0
NV
U
ST
0
AT[1]
AT[0]
S
0
0 to 8 bits
Table 19. Long Response - Request Status Command
Data
CRC
D[15] D[14] D[13] D[12] D[11] D[10] D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
A[3]
A[2]
A[1]
A[0]
0
0
0
0
NV
U
ST
0
AT[1]
AT[0]
S
0
0 to 8 bits
Table 20. Request Status Response Bit Definitions
Bit Field
Definition
This bit indicates whether the device has detected an internal device error.
1 - Internal Error detected.
0 - No Internal Error detected
S
Reference Table 59 for conditions that set the S bit.
AT[1:0]
ST
Attribute bits located in Register DEVCFG1 (Reference Section 3.1.4.2)
This bit indicates whether internal self-test circuitry is active
1 - Self-Test active
0 - Self-Test disabled
U
This bit is set if the voltage at HCAP is below the threshold specified in Section 2. Refer to Section 3.3.2 for details.
NVM Program Enable. This bit indicates whether programming of the user-programmable OTP locations is enabled.
NV
1 - OTP programming Enabled
0 - OTP programming Disabled
A[3:0]
DSI device address. This field contains the device address.
Shaded bits are transmitted to meet the response message length of the received message
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4.2.1.3
Read Acceleration Data Command
The Read Acceleration Data command is supported in the following command formats:
• Standard Long Command
• Standard Short Command
• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11)
• Enhanced Short Command as configured by the Format Control Command (Reference Section 4.2.1.11)
The device ignores the Request Status command if the DSI device address is set to the DSI Global Device Address of ‘0000’.
The data bits D[7:0] in the command are only used in the CRC calculation.
Table 21. Read Acceleration Data Command
Data
Address
Command
CRC
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
A[3]
A[2]
A[1]
A[0]
C[3]
C[2]
C[1]
C[0]
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
A[3]
A[2]
A[1]
A[0]
0
0
1
0
0 to 8 bits
Table 22. Read Acceleration Data Command Bit Definitions
Bit Field
Definition
C[3:0]
A[3:0]
D[7:0]
Read Acceleration Data Command = ‘0010’
DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the
command is ignored.
Used for CRC calculation only
Table 23. Short Response - Read Acceleration Data Command
Response
Response
Length
CRC
D[14]
D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
AD[9] AD[8] AD[7] AD[6] AD[5] AD[4] AD[3] AD[2]
8
9
AD[9] AD[8] AD[7] AD[6] AD[5] AD[4] AD[3] AD[2] AD[1]
10
11
12
13
14
15
0 to 8 bits
AD[9] AD[8] AD[7] AD[6] AD[5] AD[4] AD[3] AD[2] AD[1] AD[0]
S
0
ST
AT_OTP[0]
AT_OTP[1]
Table 24. Long Response - Read Acceleration Data Command
Response
CRC
D[15] D[14] D[13] D[12] D[11] D[10] D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
A[3]
A[2]
A[1]
A[0]
0
S
AD[9]
AD[8]
AD[7]
AD[6]
AD[5]
AD[4]
AD[3]
AD[2]
AD[1]
AD[0] 0 to 8 bits
Table 25. Read Acceleration Response Bit Definitions
Bit Field
Definition
AD[9:0]
Ten-bit acceleration result produced by the device.
This bit indicates whether the device has detected an internal device error.
1 - Internal Error detected.
0 - No Internal Error detected
S
Reference Table 59 for conditions that set the S bit.
This bit indicates whether internal self-test circuitry is active
1 - Self-Test active
ST
0 - Self-Test disabled
A[3:0]
DSI device address. This field contains the device address.
AT_OTP[1:0]
Attribute bits located in Register DEVCFG1 (Reference Section 3.1.4.2)
Shaded bits are transmitted to meet the response message length of the received message
The device truncates the LSBs for Acceleration Data Responses of length less than 10. If the result of the truncation is 0, the
minimum acceleration value is transmitted as defined in Table 26.
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Table 26. Acceleration Data Values
8-Bit Data Value
Decimal Hex
9-Bit Data Value
10-Bit Data Value
Description
Decimal
Hex
Decimal
Hex
255
0xFF
511
0x1FF
1023
0x3FF
Maximum positive acceleration value
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Positive acceleration values
131
130
129
128
127
126
125
0x83
0x82
0x81
0x80
0x7F
0x7E
0x7D
259
258
257
256
127
126
125
0x103
0x102
0x101
0x100
0x0FF
0x0FE
0x0FD
515
514
513
512
511
510
509
0x203
0x202
0x201
0x200
0x1FF
0x1FE
0x1FD
Typical 0 g level
Negative acceleration values
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
0
1
0
1
0
1
0
1
0
1
0
Maximum negative acceleration value
Sensor Error
4.2.1.4
DSI Command #3
DSI Command ‘0011’ is not implemented. The device ignores all command formats with a command ID of ‘0011’.
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4.2.1.5
Request ID Information Command
The Request ID Information command is supported in the following command formats:
• Standard Long Command
• Standard Short Command
• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11)
• Enhanced Short Command as configured by the Format Control Command (Reference Section 4.2.1.11)
The device ignores the Request ID Information command if the DSI device address is set to the DSI Global Device Address
of ‘0000’. The data bits D[7:0] in the command are only used in the CRC calculation.
Table 27. Request ID Information Command
Data
Address
Command
CRC
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
A[3]
A[2]
A[1]
A[0]
C[3]
C[2]
C[1]
C[0]
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
A[3]
A[2]
A[1]
A[0]
0
1
0
0
0 to 8 bits
Table 28. Request ID Information Command Bit Definitions
Bit Field
Definition
C[3:0]
A[3:0]
D[7:0]
Request ID Information Data Command = ‘0100’
DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the
command is ignored.
Used for CRC calculation only
Table 29. Short Response - Request ID Information Command
Response
CRC
D[14] D[13] D[12] D[11] D[10] D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
0
0
0
0
0
0
0
V2
V1
V0
0
1
1
1
0
0 to 8 bits
Table 30. Long Response - Request ID Information Command
Response
CRC
D[15] D[14] D[13] D[12] D[11] D[10] D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
A[3]
A[2]
A[1]
A[0]
0
0
0
0
V[2]
V[1]
V[0]
0
DEVID
1
0
0
0 to 8 bits
Table 31. Request ID Response Bit Definitions
Bit Field
Definition
Device Identifier:‘00100’, or ‘01100’
DEVID: Bit 7 of the DEVCFG regIster
D[4:0] = {1’b0,DEVID, 3’b100}
V[2:0]
A[3:0]
Version ID. This field indicates the device / silicon revision of the device.
DSI device address. This field contains the device address.
Shaded bits are transmitted to meet the response message length of the received message
4.2.1.6
DSI Command #5
DSI Command ‘0101’ is not implemented. The device ignores all command formats with a command ID of ‘0101’.
4.2.1.7
DSI Command #6
DSI Command ‘0110’ is not implemented. The device ignores all command formats with a command ID of ‘0110’.
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4.2.1.8
Clear Command
The Clear command is supported in the following command formats:
• Standard Long Command
• Standard Short Command
• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11)
• Enhanced Short Command as configured by the Format Control Command (Reference Section 4.2.1.11)
When the device successfully decodes a Clear Command, and the address field matches either the assigned device address
(PA[3:0]) or the DSI Global address of ‘0000’ the device logic is reset. Reference Section 3.6 for the initialization sequence fol-
lowing a Clear Command. The data bits D[7:0] in the command are only used in the CRC calculation. There is no response to
the Clear Command.
Table 32. Clear Command
Data
Address
Command
CRC
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[3] A[2] A[1] A[0] C[3] C[2] C[1] C[0]
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
A[3]
A[2]
A[1]
A[0]
0
1
1
1
0 to 8 bits
Table 33. Clear Command Bit Definitions
Bit Field
Definition
Clear Command = ‘0111’.
C[3:0]
When a Clear Command is successfully decoded and the address field matches either the assigned device address or the DSI Global
Device Address of ‘0000’ the device logic is reset. Reference Section 3.6 for the initialization sequence following a Clear Command.
DSI device address. This field contains the device address. This field must match the internal programmed address field or the Global
Device Address of ‘0000’. Otherwise, the command is ignored.
A[3:0]
D[7:0]
Used for CRC calculation only
4.2.1.9
DSI Command #8
DSI Command ‘1000’ is not implemented. The device ignores all command formats with a command ID of ‘1000’.
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4.2.1.10
Write NVM Command
The Write NVM command is supported in the following command formats:
• Standard Long Command
• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11)
The device ignores the Write NVM command if the command is in any other format, or if the DSI device address is set to the
DSI Global Device Address of ‘0000’.
The Write NVM command uses the nibble address definitions in Table 2 and summarized in Table 39.
Table 34. Write NVM Command
Data
D[4] D[3]
Address
Command
CRC
D[7]
D[6]
D[5]
D[2]
D[1]
D[0]
A[3]
A[2]
A[1]
A[0]
C[3]
C[2]
C[1]
C[0]
WA[3] WA[2] WA[1] WA[0] RD[3]
RD[2]
RD[1]
RD[0]
A[3]
A[2]
A[1]
A[0]
1
0
0
1
0 to 8 bits
Table 35. Write NVM Command Bit Definitions
Bit Field
Definition
C[3:0]
Write NVM Command = ‘1001’
DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the command is
ignored.
A[3:0]
RD[3:0] RD[3:0] contains the data to be written to the OTP location addressed by WA[3:0] when the NV bit is set.
WA[3:0] WA[3:0] contains the nibble address of the OTP register to be written to when the NV bit is set.
Table 36. Long Response - Write NVM Command (NV = 1)
Data
CRC
D[15] D[14] D[13] D[12] D[11] D[10] D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
A[3]
A[2]
A[1]
A[0]
WA[3] WA[2] WA[1] WA[0]
1
1
Bnk[1] Bnk[0] RD[3]
RD[2]
RD[1]
RD[0] 0 to 8 bits
Table 37. Long Response - Write NVM Command (NV = 0)
Data
CRC
D[0]
D[15] D[14] D[13] D[12] D[11] D[10] D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
A[3]
A[2]
A[1]
A[0]
0
0
0
0
1
1
1
1
A[3]
A[2]
A[1]
A[0]
0 to 8 bits
Table 38. Write NVM Response Bit Definitions
Bit Field
Definition
Bnk[1:0] These bits provide the bank address selected in the Initialization command.
DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the command is
ignored.
A[3:0]
RD[3:0] RD[3:0] contains the contents of the registers addressed by WA[3:0] after the execution of the NVM write.
WA[3:0] WA[3:0] contains the nibble address of the OTP register to be written to when the NV bit is set.
Writes to OTP occur only if the NV bit is set. The NV bit is set by the Initialization Command (reference Section 4.2.1.1). If the
NV bit is cleared when the command is executed, the mirror registers addressed by WA[3:0] are updated with the contents of
RD[3:0] and the DSI Device Address is returned regardless of the WA[3:0] value. If the Write NVM command is a request to
change the Device Address, the new Device Address is returned.
The DSI Bus idle voltage must exceed the minimum VPP voltage when programming the OTP array. No internal verification of
the VPP voltage is completed while writing is in process. To verify proper writes, it is recommend that the registers be read back
after writes to verify proper contents. The total Execution time for the Write NVM command is tPROG_BIT times the number of bits
being programmed (1 - 4 bits). Inter-frame spacing between the Write NVM command and the subsequent DSI command must
accommodate this timing.
Writes to the User Programmable OTP array using the Write NVM Command will update the mirror registers and result in a
change to the CRC calculation regardless of the state of the NV bit and the LOCK_U bit. A CRC mismatch will only be detected
if the LOCK_U bit is active (reference Section 3.2.2).
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Table 39. OTP Register Nibble Address Assignments
Bank Address
Register Address (Nibble)
Register
Description
Bnk[1] Bnk[0] WA[3] WA[2] WA[1] WA[0]
x
x
x
x
x
x
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
x
x
x
x
x
x
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
UNUSED
No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
UNUSED
No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
UNUSED
DEVCFG2[7]
TYPE[7:6]
DEVCFG[3:0]
DEVCFG[7:4]
UNUSED
No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
Only RD[3] is written to the LOCK_U bit
Only RD[3:2] is written to LPF[1:0]
RD[3] is written to DEVCFG[3] - UNUSED, RD[2:0] is written to CRC_U[2:0]
RD[3:0] is written to DEVCFG[7:4] - UNUSED
No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
RD[3:2] is written to UD00[1:0], RD[1:0] is written to AT[1:0]
RD[3:0] is written to ADDR[3:0]
UNUSED
UNUSED
UNUSED
UNUSED
DEVCFG1[3:0]
DEVCFG2[3:0]
UD01[3:0]
UD02[3:0]
UD03[3:0]
UD04[3:0]
UD05[3:0]
UD06[3:0]
UD07[3:0]
UD08[3:0]
DEVCFG1[7:4]
DEVCFG2[5]
UD01[7:4]
UD02[7:4]
UD03[7:4]
UD04[7:4]
UD05[7:4]
UD06[7:4]
UD07[7:4]
UD08[7:4]
UNUSED
RD[3:0] is written to UD01[3:0]
RD[3:0] is written to UD02[3:0]
RD[3:0] is written to UD03[3:0]
RD[3:0] is written to UD04[3:0]
RD[3:0] is written to UD05[3:0]
RD[3:0] is written to UD06[3:0]
RD[3:0] is written to UD07[3:0]
RD[3:0] is written to UD08[3:0]
RD[3:0] is written to UD00[5:2]
Only RD[1] is written to the PCM bit
RD[3:0] is written to UD01[7:4]
RD[3:0] is written to UD02[7:4]
RD[3:0] is written to UD03[7:4]
RD[3:0] is written to UD04[7:4]
RD[3:0] is written to UD05[7:4]
RD[3:0] is written to UD06[7:4]
RD[3:0] is written to UD07[7:4]
RD[3:0] is written to UD08[7:4]
No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
Only RD[2] is written to the DEVCFG2[6] bit (UNUSED)
No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
Only RD[0] is written to DEVCFG2[4]
DEVCFG2[6]
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
DEVCFG2[4]
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4.2.1.11
Format Control Command
The Format Control command is supported in the following command formats:
• Standard Long Command
• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11)
The device ignores the Format Control command if the command is in any other format. The device supports the Format Con-
trol command with the DSI Global Address of ‘0000’, but does not provide a response.
Table 40. Format Control Command
Data
Address
Command
CRC
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
A[3]
A[2]
A[1]
A[0]
C[3]
C[2]
C[1]
C[0]
R/W
FA[2]
FA[1]
FA[0]
FD[3]
FD[2]
FD[1]
FD[0]
A[3]
A[2]
A[1]
A[0]
1
0
1
0
0 to 8 bits
Table 41. Format Control Command Bit Definitions
Bit Field
Definition
C[3:0]
Format Control Command = ‘1010’
DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the
command is ignored.
A[3:0]
FD[3:0]
FA[2:0]
Data to be written to the Format Control Register addressed by FA[2:0] if the R/W bit is set to ‘1’.
The Address of the Format Control Register to read or written.
Read/Write determines if the register at address FA[2:0] is to be read or written.
1 - Write FD[3:0] to the Format Control Register addressed by FA[2:0]
0 - Read the Format Control Register addressed by FA[2:0]
R/W
Table 42. Long Response - Format Control Command
Response
CRC
D[15] D[14] D[13] D[12] D[11] D[10] D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
A[3]
A[2]
A[1]
A[0]
0
1
1
0
R/W
FA[2]
FA[1]
FA[0]
FD[3]
FD[2]
FD[1]
FD[0]
0 to 8 bits
Table 43. Format Control Response Bit Definitions
Bit Field
Definition
FD[3:0]
FA[2:0]
The contents of the Format Control Register addressed by FA[2:0].
The Address of the Format Control Register that was read or written.
Read/Write indicates if the register at address FA[2:0] was read or written.
R/W
1 - FD[3:0] contains the data written to the Format Control Register addressed by FA[2:0]
0 - FD[3:0] contains the contents for the Format Control Register addressed by FA[2:0]
A[3:0]
DSI device address. This field contains the device address.
The format control registers defined in the DSI Bus Standard V2.5 are shown in Table 44. The reset values assigned to each
register are also indicated.
Table 44. Format Control Register Values
Register Address
Reset Values
DSI Standard Values
Format Control Register
Definition
FA[2] FA[1] FA[0] FD[3] FD[2] FD[1] FD[0] FD[3] FD[2] FD[1] FD[0]
CRC Polynomial - Low Nibble
CRC Polynomial - High Nibble
Seed - Low Nibble
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
4
CRC Polynomial = X + 1
Seed = ‘1010’
Seed - High Nibble
CRC Length (0 to 8)
CRC Length = 4
Short Word Data Length (8 to 15)
Reserved
Short Command Length = 8
N/A
N/A
Format Selection
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The following restrictions apply to format control register operations:
• Writes to the CRC Length Register of values greater than 8 are ignored. The contents of the register are
unchanged.
• Writes to the Short Word Data Length register of values less than 8 are ignored. The contents of the register are
unchanged.
The contents of the Format Selection register determine whether the standard DSI values or the values in the format control
registers are used. If the Format Selection register contains ‘1111’, the Format Control register values are active. Any write to the
Format Control registers will become active upon completion of the write. In this case, the response to a Format Control Com-
mand will maintain the format of the previous command resulting in an invalid response.
A write of ‘0000’ to the Format Selection register activates the standard DSI values.
A write to the Format Selection register of any other value is ignored.
4.2.1.12
Read Register Data Command
The Read Register Data command is supported in the following command formats:
• Standard Long Command
• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11)
The device ignores the Register Data command if the command is in any other format, or if the DSI device address is set to
the DSI Global Device Address of ‘0000’.
The read register command uses the byte address definitions shown in Table 2. Readable registers along with their Byte ad-
dresses are shown in Table 2.
Table 45. Read Register Data Command
Data
Address
Command
CRC
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
A[3]
A[2]
A[1]
A[0]
C[3]
C[2]
C[1]
C[0]
0
0
0
0
RA[3]
RA[2]
RA[1]
RA[0]
A[3]
A[2]
A[1]
A[0]
1
0
1
1
0 to 8 bits
Table 46. Read Register Data Command Bit Definitions
Bit Field
Definition
C[3:0]
Read Register Data Command = ‘1011’
DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the
command is ignored.
A[3:0]
RA[3:0]
RA[3:0] contains the byte address of the register to be read.
Table 47. Long Response - Read Register Data Command
Data
CRC
D[15] D[14] D[13] D[12] D[11] D[10] D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
A[3]
A[2]
A[1]
A[0]
RA[3]
RA[2]
RA[1]
RA[0]
RD[7]
RD[6]
RD[5]
RD[4]
RD[3]
RD[2]
RD[1]
RD[0] 0 to 8 bits
Table 48. Read Register Data Response Bit Definitions
Bit Field
Definition
RD7:0]
RA[3:0]
RD[7:0] contains the data of the register addressed by RA[3:0].
RA[3:0] contains the byte address of the register to be read.
DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the
command is ignored.
A[3:0]
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4.2.1.13
Disable Self-Test Command
The Disable Self-Test command is supported in the following command formats:
• Standard Long Command
• Standard Short Command
• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11)
• Enhanced Short Command as configured by the Format Control Command (Reference Section 4.2.1.11)
The data bits D[7:0] in the command are only used in the CRC calculation. The device supports the Disable Self-Test command
with the DSI Global Address of ‘0000’, but does not provide a response.
The Disable Self-Test Command removes the voltage from the self-test plate of the transducer which results in the acceleration
output value returning to the 0g offset value within tST_DEACT_xxx, as specified in Section 2.
Table 49. Disable Self-Test Command
Data
Address
Command
CRC
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
A[3]
A[2]
A[1]
A[0]
C[3]
C[2]
C[1]
C[0]
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
A[3]
A[2]
A[1]
A[0]
1
1
0
0
0 to 8 bits
Table 50. Disable Self-Test Command Bit Definitions
Bit Field
Definition
C[3:0]
A[3:0]
D[7:0]
Disable Self-Test Command = ‘1100’
DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the
command is ignored.
Used for CRC calculation only
Table 51. Short Response - Disable Self-Test Command
Response
CRC
D[14] D[13] D[12] D[11] D[10] D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
0
0
0
0
0
0
0
NV
U
ST
0
AT[1]
AT[0]
S
0
0 to 8 bits
Table 52. Long Response - Disable Self-Test Command
Data
D[8] D[7]
CRC
D[15] D[14] D[13] D[12] D[11] D[10] D[9]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
A[3]
A[2]
A[1]
A[0]
0
0
0
0
NV
U
ST
0
AT[1]
AT[0]
S
0
0 to 8 bits
Table 53. Disable Self-Test Response Bit Definitions
Bit Field
Definition
This bit indicates whether the device has detected an internal device error.
1 - Internal Error detected.
0 - No Internal Error detected
S
Reference Table 59 for conditions that set the S bit.
AT[1:0]
ST
Attribute bits located in Register DEVCFG1 (Reference Section 3.1.4.2)
This bit indicates whether internal self-test circuitry is active
1 - Self-Test active
0 - Self-Test disabled
U
This bit is set if the voltage at HCAP is below the threshold specified in Section 2. Refer to Section 3.3.2 for details.
NVM Program Enable. This bit indicates whether programming of the user-programmable OTP locations is enabled.
NV
1 - OTP programming Enabled
0 - OTP programming Disabled
A[3:0]
DSI device address. This field contains the device address.
A self-test lockout is activated when the device receives two consecutive Disable Self-Test commands Once self-test lockout
is activated, the internal self-test circuitry is disabled until one of the following conditions occurs:
• HCAP under-voltage
• A Clear command is received
• Internal regulator under-voltage resulting in a reset.
• A Frame Timeout resulting in a reset.
MMA16xxNKW
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40
Freescale Semiconductor, Inc.
4.2.1.14
Enable Self-Test Command
The Enable Self-Test command is supported in the following command formats:
• Standard Long Command
• Standard Short Command
• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11)
• Enhanced Short Command as configured by the Format Control Command (Reference Section 4.2.1.11)
The data bits D[7:0] in the command are only used in the CRC calculation. The device ignores the Enable Self-Test command
when it is sent to the DSI Global Address of ‘0000’.
The Enable Self-Test Command applies a voltage to the self-test plate of the transducer which results in a delta in the accel-
eration output value of ΔDFLCT_xxx within tST_ACT_xxx, as specified in Section 2. This remains present until the Disable Self-Test
command is received.
Activation of the self-test circuit is inhibited if the self-test locking has been activated. If self-test locking is activated, the internal
self-test circuitry remains disabled, and the ST bit is cleared in the response. Self-Test locking is described in Section 4.2.1.13.
Table 54. Enable Self-Test Command
Data
Address
Command
CRC
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
A[3]
A[2]
A[1]
A[0]
C[3]
C[2]
C[1]
C[0]
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
A[3]
A[2]
A[1]
A[0]
1
1
0
1
4 bits
Table 55. Enable Self-Test Command Bit Definitions
Bit Field
Definition
C[3:0]
A[3:0]
D[7:0]
Enable Self-Test Command = ‘1101’
DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the
command is ignored.
Used for CRC calculation only
Table 56. Short Response - Enable Self-Test Command
Response
CRC
D[14] D[13] D[12] D[11] D[10] D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
0
0
0
0
0
0
0
NV
U
ST
0
AT[1]
AT[0]
S
0
4 bits
Table 57. Long Response - Enable Self-Test Command
Data
D[8] D[7]
CRC
D[15] D[14] D[13] D[12] D[11] D[10] D[9]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
A[3]
A[2]
A[1]
A[0]
0
0
0
0
NV
U
ST
0
AT[1]
AT[0]
S
0
4 bits
Table 58. Enable Self-Test Response Bit Definitions
Bit Field
Definition
This bit indicates whether the device has detected an internal device error.
1 - Internal Error detected.
0 - No Internal Error detected
S
Reference Table 59 for conditions that set the S bit.
AT[1:0]
ST
Attribute bits located in Register DEVCFG1 (Reference Section 3.1.4.2)
This bit indicates whether internal self-test circuitry is active
1 - Self-Test active
0 - Self-Test disabled
U
This bit is set if the voltage at HCAP is below the threshold specified in Section 2. Refer to Section 3.3.2 for details.
NVM Program Enable. This bit indicates whether programming of the user-programmable OTP locations is enabled.
NV
1 - OTP programming Enabled
0 - OTP programming Disabled
A[3:0]
DSI device address. This field contains the device address.
MMA16xxNKW
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4.2.1.15
DSI Command #14
DSI Command ‘1110’ is not implemented. The device ignores all command formats with a command ID of ‘1110’.
4.2.1.16
Reverse Initialization Command
The Reverse Initialization Command is not implemented. The device ignores all command formats with a command ID of
‘1111’.
4.3
Exception Handling
Table 59 summarizes the exception conditions detected by the device and the response for each exception.
Table 59. Exception Handling
Condition
Description
S
ST
U
Response
Self-Test
Request
Exception
Power On
Reset
Power Applied
Clear Command
N/A
1
1
0
–
Reference Section 3.6
Device held in Reset.
–
–
–
V
REG
N/A
V
V
V
< V
No response to DSI commands.
REG
PORCREG_f
Under-Voltage
Device must be re-initialized when V
returns above V
PORCREG_r
REG
–
–
–
Device held in Reset.
No response to DSI commands.
Device must be re-initialized when V
V
REGA
N/A
< V
REGA
PORCREG_f
Under-Voltage
returns above V
REGA
PORCREGA_r
–
–
–
DSI Read Acceleration Data Short response = zero.
DSI Read Acceleration Data Long response = normal.
< V
for less
HCAP
PORCREG_f
Disabled
0
0
0
1
1
1
Device does not need to be re-initialized if
before t
V
returns above
than t
, ST Disabled
for less
PORCREG_f
HCAP
HCAP_POR
V
HCAP
V
PORHCAP_r
HCAP_POR
Under-Voltage
Transient
–
–
–
DSI Read Acceleration Data Short response = self-test data.
DSI Read Acceleration Data Long response = self-test data.
V
< V
HCAP
Enabled
N/A
Device does not need to be re-initialized if
before t
V
returns above
than t
, ST Enabled
HCAP
HCAP_POR
V
PORHCAP_r
HCAP_POR
–
Device is Reset and will continue to Reset every t
until VHCAP
HCAP_POR
returns above V
occurs.
, or an internal supply under-voltage condition
PORHCAP_r
V
V
< V
for longer
HCAP
HCAP
PORCREG_f
than t
HCAP_POR
Under-Voltage
–
–
No response to DSI commands.
Device must be re-initialized when V
returns above V
PORHCAP_r
HCAP
–
Device is Reset and will continue to be reset every t
capacitor failure is removed.
until the
POR_CAPTEST
Capacitor Test
Failure
N/A
N/A
–
–
No response to DSI commands.
Device must be re-initialized when capacitor failure is removed.
–
Device is Reset and will continue to be reset every t until the BUSIN
TO
DSI Frame
Timeout
voltage returns above V
or a supply under-voltage condition occurs.
THF
V
< V
for longer than t
THF TO
BUSIN
–
–
No response to DSI commands.
Device must be re-initialized when V
returns above V
THF
BUSIN
CRC failure detected in factory
Disabled programmed OTP array and the
LOCK_F bit is set. ST Disabled
–
–
DSI Read Acceleration Data Short response = zero.
DSI Read Acceleration Data Long response = normal.
1
1
1
1
0
1
0
1
0
0
0
0
Fuse CRC
Fault
(Factory Array)
CRC failure detected in factory
Enabled programmed OTP array and the
LOCK_F bit is set. ST Enabled
–
–
DSI Read Acceleration Data Short response = zero.
DSI Read Acceleration Data Long response = self-test data.
CRC failure detected in User pro-
Disabled grammed OTP array and the
LOCK_U bit is set. ST Disabled
–
–
DSI Read Acceleration Data Short response = zero.
DSI Read Acceleration Data Long response = normal.
Fuse CRC
Fault
(User Array)
CRC failure detected in User pro-
Enabled grammed OTP array and the
LOCK_U bit is set. ST Enabled
–
–
DSI Read Acceleration Data Short response = zero.
DSI Read Acceleration Data Long response = self-test data.
Temperature out of range, ST
–
–
DSI Read Acceleration Data Short response = zero.
DSI Read Acceleration Data Long response = normal.
Disabled
Disabled.
1
1
0
1
0
0
Temperature
Out of Range
Temperature out of range, ST
–
–
DSI Read Acceleration Data Short response = zero.
DSI Read Acceleration Data Long response = self-test data.
Enabled
Enabled.
–
–
–
Internal self-test circuitry enabled.
Self-Test
Enabled
Enabled ST Enabled
1
0
1
0
0
0
DSI Read Acceleration Data Short response = self-test data.
DSI Read Acceleration Data Long response = self-test data.
–
–
Internal self-test circuitry disabled.
Sel- Test
Lockout
2 consecutive Disable Self-Test
Disabled
Enable Self-Test DSI command does not enable Self-Test. Normal
response to Enable Self-Test DSI command except the ST bit is not set.
DSI Clear command or Reset disables lockout.
DSI commands received.
–
MMA16xxNKW
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Freescale Semiconductor, Inc.
42
5
Package
5.1
Case Outline Drawing
Reference Freescale Case Outline Drawing # 98ASA00090D
http://www.freescale.com/files/shared/doc/package_info/98ASA00090D.pdf
5.2
Recommended Footprint
Reference Freescale Application Note AN3111, latest revision:
http://www.freescale.com/files/sensors/doc/app_note/AN3111.pdf
Table 60. Revision History
Revision Revision
Description of changes
number
date
4
03/2012
• Added SafeAssure logo, changed first paragraph and disclaimer to include trademark
information.
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MMA16xxNKW
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