MPC8306SEC_技术文档

Document Number: MPC8306SEC

Rev. 1, 09/2011

Freescale Semiconductor

Technical Data

MPC8306S

PowerQUICC II Pro Integrated

Communications Processor

Family Hardware Specifications

Contents

This document provides an overview of the MPC8306S

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

PowerQUICC II Pro processor features. The MPC8306S is

a cost-effective, highly integrated communications

processor that addresses the requirements of several

networking applications, including residential gateways,

modem/routers, industrial control, and test and measurement

applications. The MPC8306S extends current PowerQUICC

offerings, adding higher CPU performance, additional

functionality, and faster interfaces, while addressing the

requirements related to time-to-market, price, power

consumption, and board real estate. This document describes

the electrical characteristics of MPC8306S.

2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 6

3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10

4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 12

6. DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

8. Ethernet and MII Management . . . . . . . . . . . . . . . . . 21

9. TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

10. HDLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

11. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

12. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

13. I²C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

14. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

15. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

16. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

17. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

18. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

19. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 44

20. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

21. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

22. System Design Information . . . . . . . . . . . . . . . . . . . 64

23. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 67

24. Document Revision History . . . . . . . . . . . . . . . . . . . 69

To locate published errata or updates for this document, refer

to the MPC8306S product summary page on our website

listed on the back cover of this document or contact your

local Freescale sales office.

Overview

1 Overview

The MPC8306S incorporates the e300c3 (MPC603e-based) core built on Power Architecture®

technology, which includes 16 Kbytes of each L1 instruction and data caches, dual integer units, and

on-chip memory management units (MMUs). The MPC8306S also includes two DMA engines and a

16-bit DDR2 memory controller.

A new communications complex based on QUICC Engine technology forms the heart of the networking

capability of the MPC8306S. The QUICC Engine block contains several peripheral controllers and a

32-bit RISC controller. Protocol support is provided by the main workhorses of the device—the unified

communication controllers (UCCs). A block diagram of the MPC8306S is shown in the following figure.

2 x DUART

e300c3 Core with Power

I2C

Management

Timers

16-KB

I-Cache

16-KB

D-Cache

GPIO

SPI

RTC

ULPI

Enhanced Local

Bus Controller

Interrupt

USB 2.0 HS

Host/Device/OTG

FPU

Controller

DDR2

DMA

Engine

QUICC Engine™ Block

Controller

16 KB Multi-User RAM

48 KB Instruction RAM

Accelerators

Baud Rate

Generators

Serial DMA

Single 32-bit RISC CP

Time Slot Assigner

Serial Interface

3 RMII/MII

2x TDM Ports

2x HDLC

Figure 1. MPC8306S Block Diagram

Each of the five UCCs can support a variety of communication protocols such as 10/100 Mbps MII/RMII

Ethernet, HDLC and TDM.

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

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Freescale Semiconductor

Overview

In summary, the MPC8306S provides users with a highly integrated, fully programmable communications

processor. This helps to ensure that a low-cost system solution can be quickly developed and offers

flexibility to accommodate new standards and evolving system requirements.

1.1

Features

The major features of the device are as follows:

•

e300c3 Power Architecture processor core

— Enhanced version of the MPC603e core

— High-performance, superscalar processor core with a four-stage pipeline and low interrupt

latency times

— Floating-point, dual integer units, load/store, system register, and branch processing units

— 16-Kbyte instruction cache and 16-Kbyte data cache with lockable capabilities

— Dynamic power management

— Enhanced hardware program debug features

— Software-compatible with Freescale processor families implementing Power Architecture

technology

— Separate PLL that is clocked by the system bus clock

— Performance monitor

•

QUICC Engine block

— 32-bit RISC controller for flexible support of the communications peripherals with the

following features:

– One clock per instruction

– Separate PLL for operating frequency that is independent of system’s bus and e300 core

frequency for power and performance optimization

– 32-bit instruction object code

– Executes code from internal IRAM

– 32-bit arithmetic logic unit (ALU) data path

– Modular architecture allowing for easy functional enhancements

– Slave bus for CPU access of registers and multiuser RAM space

– 48 Kbytes of instruction RAM

– 16 Kbytes of multiuser data RAM

– Serial DMA channel for receive and transmit on all serial channels

— Five unified communication controllers (UCCs) supporting the following protocols and

interfaces:

– 10/100 Mbps Ethernet/IEEE Std. 802.3® through MII and RMII interfaces.

– HDLC/Transparent (bit rate up to QUICC Engine operating frequency / 8)

– HDLC Bus (bit rate up to 10 Mbps)

– Asynchronous HDLC (bit rate up to 2 Mbps)

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

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3

Overview

– Two TDM interfaces supporting up to 128 QUICC multichannel controller channels, each

running at 64 kbps

For more information on QUICC Engine sub-modules, see QUICC Engine Block Reference

Manual with Protocol Interworking.

•

DDR SDRAM memory controller

— Programmable timing supporting DDR2 SDRAM

— Integrated SDRAM clock generation

— 16-bit data interface, up to 266-MHz data rate

— 14 address lines

— The following SDRAM configurations are supported:

– Up to two physical banks (chip selects), 256-Mbyte per chip select for 16 bit data interface.

– 64-Mbit to 2-Gbit devices with x8/x16 data ports (no direct x4 support)

– One 16-bit device or two 8-bit devices on a 16-bit bus,

— Support for up to 16 simultaneous open pages for DDR2

— One clock pair to support up to 4 DRAM devices

— Supports auto refresh

— On-the-fly power management using CKE

•

Enhanced local bus controller (eLBC)

— Multiplexed 26-bit address and 8-/16-bit data operating at up to 66 MHz

— Eight chip selects supporting eight external slaves

– Four chip selects dedicated

– Four chip selects offered as multiplexed option

— Supports boot from parallel NOR Flash and parallel NAND Flash

— Supports programmable clock ratio dividers

— Up to eight-beat burst transfers

— 16- and 8-bit ports, separate LWE for each 8 bit

— Three protocol engines available on a per chip select basis:

– General-purpose chip select machine (GPCM)

– Three user programmable machines (UPMs)

– NAND Flash control machine (FCM)

— Variable memory block sizes for FCM, GPCM, and UPM mode

— Default boot ROM chip select with configurable bus width (8 or 16)

— Provides two Write Enable signals to allow single byte write access to external 16-bit eLBC

slave devices

•

Integrated programmable interrupt controller (IPIC)

— Functional and programming compatibility with the MPC8260 interrupt controller

— Support for external and internal discrete interrupt sources

— Programmable highest priority request

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

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Overview

— Six groups of interrupts with programmable priority

— External and internal interrupts directed to host processor

— Unique vector number for each interrupt source

•

Universal serial bus (USB) dual-role controller

— Designed to comply with Universal Serial Bus Revision 2.0 Specification

— Supports operation as a stand-alone USB host controller

— Supports operation as a stand-alone USB device

— Supports high-speed (480-Mbps), full-speed (12-Mbps), and low-speed (1.5-Mbps) operations.

Low speed is only supported in host mode.

2

Dual I C interfaces

— Two-wire interface

— Multiple-master support

2

— Master or slave I C mode support

— On-chip digital filtering rejects spikes on the bus

2

— I C1 can be used as the boot sequencer

•

DMA Engine

— Support for the DMA engine with the following features:

– Sixteen DMA channels

– All data movement via dual-address transfers: read from source, write to destination

– Transfer control descriptor (TCD) organized to support two-deep, nested transfer operations

– Channel activation via one of two methods (for both the methods, one activation per

execution of the minor loop is required):

– Explicit software initiation

– Initiation via a channel-to-channel linking mechanism for continuous transfers

(independent channel linking at end of minor loop and/or major loop)

– Support for fixed-priority and round-robin channel arbitration

– Channel completion reported via optional interrupt requests

— Support for scatter/gather DMA processing

•

DUART

— Two 2-wire interfaces (RxD, TxD)

– The same can be configured as one 4-wire interface (RxD, TxD, RTS, CTS)

— Programming model compatible with the original 16450 UART and the PC16550D

Serial peripheral interface (SPI)

•

— Master or slave support

Power managemnt controller (PMC)

— Supports core doze/nap/sleep/ power management

— Exits low power state and returns to full-on mode when

– The core internal time base unit invokes a request to exit low power state

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

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5

Electrical Characteristics

– The power management controller detects that the system is not idle and there are

outstanding transactions on the internal bus or an external interrupt.

Parallel I/O

•

— General-purpose I/O (GPIO)

– 56 parallel I/O pins multiplexed on various chip interfaces

– Interrupt capability

System timers

— Periodic interrupt timer

— Software watchdog timer

— Eight general-purpose timers

Real time clock (RTC) module

— Maintains a one-second count, unique over a period of thousands of years

— Two possible clock sources:

– External RTC clock (RTC_PIT_CLK)

– CSB bus clock

•

IEEE Std. 1149.1™ compliant JTAG boundary scan

2 Electrical Characteristics

This section provides the AC and DC electrical specifications and thermal characteristics for the

MPC8306S. The MPC8306S is currently targeted to these specifications. Some of these specifications are

independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer

design specifications.

2.1

Overall DC Electrical Characteristics

This section covers the ratings, conditions, and other characteristics.

2.1.1

Absolute Maximum Ratings

The following table provides the absolute maximum ratings.

1

Table 1. Absolute Maximum Ratings

Characteristic

Symbol

Max Value

Unit

Notes

Core supply voltage

PLL supply voltage

V_DD

–0.3 to 1.26

V

—

AV_DD1

AV_DD2

AV_DD3

DDR2 DRAM I/O voltage

GV_DD

OV_DD

–0.3 to 1.98

–0.3 to 3.6

V

—

2

Local bus, DUART, system control and power management, I²C,

SPI, MII, RMII, MII management, USB and JTAG I/O voltage

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

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Electrical Characteristics

1

Table 1. Absolute Maximum Ratings (continued)

Characteristic

Symbol

Max Value

Unit

Notes

Input voltage

DDR2 DRAM signals

MV_IN

MV_REF

OV_IN

–0.3 to (GV_DD+ 0.3)

–0.3 to (OV_DD+ 0.3)

V

3

4

DDR2 DRAM reference

Local bus, DUART, SYS_CLK_IN,

system control and power

management, I²C, SPI, and JTAG

signals

Storage temperature range

T_STG

–55 to 150

C

—

Notes:

1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and

functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause

permanent damage to the device.

2. OVDD here refers to NVDDA, NVDDB, NVDDC, NVDDF, NVDDG, and NVDDH from the ball map.

3. Caution: MV_INmust not exceed GV_DDby more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during

power-on reset and power-down sequences.

4. Caution: OV_INmust not exceed OV_DDby more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during

power-on reset and power-down sequences.

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

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7

Electrical Characteristics

2.1.2

Power Supply Voltage Specification

The following table provides the recommended operating conditions for the MPC8306S. Note that these

values are the recommended and tested operating conditions. Proper device operation outside of these

conditions is not guaranteed.

Table 2. Recommended Operating Conditions

Recommended

Characteristic

Symbol

Unit

Note

Value

Core supply voltage

PLL supply voltage

V_DD

1.0 V ± 50 mV

V

1

AV_DD1

AV_DD2

AV_DD3

DDR2 DRAM I/O voltage

GV_DD

OV_DD

1.8 V ± 100 mV

3.3 V ± 300 mV

V

1

Local bus, DUART, system control and power management, I²C,

SPI, MII, RMII, MII management, USB and JTAG I/O voltage

1, 3

Junction temperature

T_A/T_J

0 to 105

C

2

Notes:

1. GV_DD, OV_DD, AV_DD, and V_DDmust track each other and must vary in the same direction—either in the positive or negative

direction.

2. Minimum temperature is specified with T_A(Ambient Temperature); maximum temperature is specified with T_J(Junction

Temperature).

3. OVDD here refers to NVDDA, NVDDB, NVDDC, NVDDF, NVDDG, and NVDDH from the ball map.

The following figure shows the undershoot and overshoot voltages at the interfaces of the MPC8306S

G/OV_DD+ 20%

G/OV_DD+ 5%

G/OV_DD

V_IH

GND

GND – 0.3 V

V_IL

GND – 0.7 V

Not to Exceed 10%

1

of t_interface

Note:

1. t_interfacerefers to the clock period associated with the bus clock interface.

Figure 2. Overshoot/Undershoot Voltage for GV /OV

DD

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

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Electrical Characteristics

2.1.3

Output Driver Characteristics

The following table provides information on the characteristics of the output driver strengths.

Table 3. Output Drive Capability

Output Impedance

Driver Type

Supply Voltage (V)

()

Local bus interface utilities signals

DDR2 signal

42

18

42

OV_DD= 3.3

GV_DD= 1.8

OV_DD= 3.3

DUART, system control, I2C, SPI, JTAG

GPIO signals

2.1.4

Input Capacitance Specification

The following table describes the input capacitance for the SYS_CLK_IN pin in the MPC8306S.

Table 4. Input Capacitance Specification

Parameter/Condition

Symbol

Min

Max

Unit

Note

Input capacitance for all pins except SYS_CLK_IN and

QE_CLK_IN

C_I

6

8

pF

—

Input capacitance for SYS_CLK_IN and QE_CLK_IN

C_{ICLK_IN}

10

—

pF

1

Note:

1. The external clock generator should be able to drive 10 pF.

2.2

Power Sequencing

The device does not require the core supply voltage (V ) and I/O supply voltages (GV and OV ) to

DD

be applied in any particular order. Note that during power ramp-up, before the power supplies are stable

and if the I/O voltages are supplied before the core voltage, there might be a period of time that all input

and output pins are actively driven and cause contention and excessive current. In order to avoid actively

driving the I/O pins and to eliminate excessive current draw, apply the core voltage (V ) before the I/O

DD

voltage (GV and OV ) and assert PORESET before the power supplies fully ramp up. In the case

DD

where the core voltage is applied first, the core voltage supply must rise to 90% of its nominal value before

the I/O supplies reach 0.7 V; see Figure 3. Once both the power supplies (I/O voltage and core voltage) are

stable, wait for a minimum of 32 clock cycles before negating PORESET.

NOTE

There is no specific power down sequence requirement for the device. I/O

voltage supplies (GV and OV ) do not have any ordering requirements

DD

with respect to one another.

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

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9

Power Characteristics

I/O Voltage (GV_DDand OV_DD

)

V

Core Voltage (V_DD

)

0.7 V

90%

t

0

PORESET

>= 32  t_{SYS_CLK_IN}

Figure 3. MPC8306S Power-Up Sequencing Example

3 Power Characteristics

The typical power dissipation for this family of MPC8306S devices is shown in the following table.

Table 5. MPC8306S Power Dissipation

Core

Frequency (MHz)

QUICC Engine

Frequency (MHz)

CSB

Frequency (MHz)

Typical

Maximum

Unit

Note

133

200

266

333

133

233

133

0.272

0.291

0.451

0.471

0.618

0.631

0.925

0.950

W

1, 2, 3

Notes:

1. The values do not include I/O supply power (OV_DDand GV_DD), but it does include V_DDand AV_DDpower. For I/O power

values, see Table 6.

2. Typical power is based on a nominal voltage of V_DD= 1.0 V, ambient temperature, and the core running a Dhrystone

benchmark application. The measurements were taken on the evaluation board using WC process silicon.

3. Maximum power is based on a voltage of V_DD= 1.05 V, WC process, a junction T_J= 105C, and a smoke test code.

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

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Clock Input Timing

The following table shows the estimated typical I/O power dissipation for the device.

Table 6. Typical I/O Power Dissipation

GV_DD

(1.8 V) (3.3 V)

OV_DD

Interface

Parameter

266 MHz, 1  16 bits

Unit Comments

W —

DDR I/O

65% utilization

1.8 V

R_s= 20 

R_t= 50 

1 pair of clocks

0.141

—

Local bus I/O load = 25 pF

1 pair of clocks

66 MHz, 26 bits

QUICC Engine block and other I/Os

TDM serial, HDLC/TRAN serial,

DUART, MII, RMII, Ethernet

management, USB, SPI, Timer

output,

—

0.150

W

1

Note:

1. Typical I/O power is based on a nominal voltage of V_DD= 3.3V, ambient temperature, and the core running a Dhrystone

benchmark application. The measurements were taken on the evaluation board using WC process silicon.

4 Clock Input Timing

This section provides the clock input DC and AC electrical characteristics for the MPC8306S.

NOTE

The rise/fall time on QUICC Engine input pins should not exceed 5 ns. This

should be enforced especially on clock signals. Rise time refers to signal

transitions from 10% to 90% of OV ; fall time refers to transitions from

DD

90% to 10% of OV

.

DD

4.1

DC Electrical Characteristics

The following table provides the clock input (SYS_CLK_IN) DC specifications for the MPC8306S. These

specifications are also applicable for QE_CLK_IN.

Table 7. SYS_CLK_IN DC Electrical Characteristics

Parameter

Input high voltage

Condition

Symbol

Min

Max

Unit

—

V_IH

V_IL

I_IN

2.4

–0.3

—

OV_DD+ 0.3

V

Input low voltage

0.4

±5

SYS_CLK_IN input current

0 V  V_IN OV_DD

A

0 V  V_IN 0.5 V or

I_IN

—

OV_DD– 0.5 V  V_INOV_DD

SYS_CLK_IN input current

0.5 V  V_IN OV_DD– 0.5 V

I_IN

—

±50

A

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

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11

RESET Initialization

4.2

AC Electrical Characteristics

The primary clock source for the MPC8306S is SYS_CLK_IN. The following table provides the clock

input (SYS_CLK_IN) AC timing specifications for the MPC8306S. These specifications are also

applicable for QE_CLK_IN.

Table 8. SYS_CLK_IN AC Timing Specifications

Parameter/Condition

SYS_CLK_IN frequency

Symbol

Min

Typical

Max

Unit

Note

f_{SYS_CLK_IN}

t_{SYS_CLK_IN}

t_KH, t_KL

24

15

1.1

40

—

66.67

41.6

2.8

MHz

ns

1

—

2

SYS_CLK_IN cycle time

SYS_CLK_IN rise and fall time

SYS_CLK_IN duty cycle

ns

t

_KHK/t_{SYS_CLK_}

60

%

3

IN

SYS_CLK_IN jitter

—

±150

ps

4, 5

Notes:

1. Caution: The system, core and QUICC Engine block must not exceed their respective maximum or minimum operating

frequencies.

2. Rise and fall times for SYS_CLK_IN are measured at 0.33 and 2.97 V.

3. Timing is guaranteed by design and characterization.

4. This represents the total input jitter—short term and long term—and is guaranteed by design.

5. The SYS_CLK_IN driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set low to

allow cascade-connected PLL-based devices to track SYS_CLK_IN drivers with the specified jitter.

6. Spread spectrum is allowed up to 1% down-spread @ 33kHz (max rate).

5 RESET Initialization

This section describes the AC electrical specifications for the reset initialization timing requirements of

the MPC8306S. The following table provides the reset initialization AC timing specifications for the reset

component(s).

Table 9. RESET Initialization Timing Specifications

Parameter/Condition

Min

Max

Unit

Note

Required assertion time of HRESET to activate reset flow

32

—

t_{SYS_CLK_IN}

1

Required assertion time of PORESET with stable clock applied to

SYS_CLK_IN

HRESET assertion (output)

512

4

—

t_{SYS_CLK_IN}

1

Input setup time for POR configuration signals

1, 2

(CFG_RESET_SOURCE[0:3]) with respect to negation of PORESET

Input hold time for POR config signals with respect to negation of

HRESET

0

—

ns

1, 2

Notes:

1. t_{SYS_CLK_IN}is the clock period of the input clock applied to SYS_CLK_IN. For more details, see the MPC8306S PowerQUICC

II Pro Integrated Communications Processor Family Reference Manual.

2. POR configuration signals consist of CFG_RESET_SOURCE[0:3].

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

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DDR2 SDRAM

The following table provides the PLL lock times.

Table 10. PLL Lock Times

Parameter/Condition

Min

Max

Unit

Note

PLL lock times

—

100

s

—

5.1

Reset Signals DC Electrical Characteristics

The following table provides the DC electrical characteristics for the MPC8306S reset signals mentioned

in Table 9.

Table 11. Reset Signals DC Electrical Characteristics

Characteristic

Output high voltage

Symbol

Condition

Min

Max

Unit

Note

V_OH

V_OL

I_OH= –6.0 mA

I_OL= 6.0 mA

2.4

—

0.5

V

1

Output low voltage

Input high voltage

Input low voltage

Input current

V

I

= 3.2 mA

—

0.4

V

1

OL

V_IH

V_IL

I_IN

—

2.0

–0.3

—

OV_DD+ 0.3

0.8

V

1

V

—

0 V  V_IN OV_DD

±5

A

Note:

1. This specification applies when operating from 3.3 V supply.

6 DDR2 SDRAM

This section describes the DC and AC electrical specifications for the DDR2 SDRAM interface of the

MPC8306S. Note that DDR2 SDRAM is GV (typ) = 1.8 V.

DD

6.1

DDR2 SDRAM DC Electrical Characteristics

The following table provides the recommended operating conditions for the DDR2 SDRAM component(s)

of the MPC8306S when GV (typ) = 1.8 V.

DD

Table 12. DDR2 SDRAM DC Electrical Characteristics for GV (typ) = 1.8 V

DD

Parameter/Condition

I/O supply voltage

Symbol

Min

Max

Unit

Note

GV_DD

MVREF

V_TT

1.7

0.49  GV_DD

MVREF – 0.04

MVREF+ 0.125

–0.3

1.9

V

1

2

I/O reference voltage

I/O termination voltage

Input high voltage

0.51  GV_DD

MVREF + 0.04

GV_DD+ 0.3

MVREF – 0.125

9.9

V

3

V_IH

V

—

4

Input low voltage

V_IL

V

Output leakage current

I_OZ

–9.9

A

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

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13

DDR2 SDRAM

Table 12. DDR2 SDRAM DC Electrical Characteristics for GV (typ) = 1.8 V (continued)

DD

Parameter/Condition

Symbol

Min

Max

Unit

Note

Output high current (V_OUT= 1.35 V)

Output low current (V_OUT= 0.280 V)

Notes:

I_OH

I_OL

–13.4

13.4

—

mA

—

1. GV_DDis expected to be within 50 mV of the DRAM GV_DDat all times.

2. MVREF is expected to be equal to 0.5  GV_DD, and to track GV_DDDC variations as measured at the receiver. Peak-to-peak

noise on MVREF may not exceed ±2% of the DC value.

3. V_TTis not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MVREF. This rail should track variations in the DC level of MVREF.

4. Output leakage is measured with all outputs disabled, 0 V  V_OUTGV_DD

.

The following table provides the DDR2 capacitance when GV (typ) = 1.8 V.

DD

Table 13. DDR2 SDRAM Capacitance for GV (typ) = 1.8 V

DD

Parameter/Condition

Symbol

Min

Max

Unit

Note

Input/output capacitance: DQ, DQS

Delta input/output capacitance: DQ, DQS

Note:

C_IO

6

8

pF

1

C_DIO

—

0.5

1. This parameter is sampled. GV_DD= 1.8 V ± 0.100 V, f = 1 MHz, T_A= 25 °C, V_OUT= GV_DD 2,

V_OUT(peak-to-peak) = 0.2 V.

6.2

DDR2 SDRAM AC Electrical Characteristics

This section provides the AC electrical characteristics for the DDR2 SDRAM interface.

6.2.1

DDR2 SDRAM Input AC Timing Specifications

This table provides the input AC timing specifications for the DDR2 SDRAM (GV (typ) = 1.8 V).

DD

Table 14. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface

At recommended operating conditions with GV_DDof 1.8 V± 100mV.

Parameter

AC input low voltage

AC input high voltage

Symbol

Min

Max

Unit

Note

V_IL

—

MVREF – 0.25

—

V

—

V_IH

MVREF + 0.25

The following table provides the input AC timing specifications for the DDR2 SDRAM interface.

Table 15. DDR2 SDRAM Input AC Timing Specifications

At recommended operating conditions with GV_DDof 1.8V ± 100mV.

Parameter

Symbol

Min

Max

Unit

Note

Controller skew for MDQS—MDQ/MDM

t_CISKEW

ps

1, 2

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

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Freescale Semiconductor

DDR2 SDRAM

Table 15. DDR2 SDRAM Input AC Timing Specifications (continued)

At recommended operating conditions with GV_DDof 1.8V ± 100mV.

Parameter

Symbol

Min

Max

Unit

Note

266 MHz

–750

750

Notes:

1. t_CISKEWrepresents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that

is captured with MDQS[n]. This should be subtracted from the total timing budget.

2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t_DISKEW. This can be

determined by the equation: t_DISKEW= ±(T/4 – abs(t_CISKEW)) where T is the clock period and abs(t_CISKEW) is the absolute

value of t_CISKEW

.

The following figure shows the input timing diagram for the DDR controller.

MCK[n]

t_MCK

MDQS[n]

MDQ[x]

D0

D1

t_DISKEW

Figure 4. DDR Input Timing Diagram

6.2.2

DDR2 SDRAM Output AC Timing Specifications

The following table provides the output AC timing specifications for the DDR2 SDRAM interfaces.

Table 16. DDR2 SDRAM Output AC Timing Specifications

At recommended operating conditions with GV_DDof 1.8V ± 100mV.

Parameter

Symbol¹

Min

Max

Unit

Note

MCK cycle time, (MCK/MCK crossing)

t_MCK

5.988

8

ns

2

3

ADDR/CMD output setup with respect to MCK

t_DDKHAS

266 MHz

ADDR/CMD output hold with respect to MCK

266 MHz

2.5

—

t_DDKHAX

ns

3

MCS output setup with respect to MCK

t_DDKHCS

266 MHz

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

Freescale Semiconductor

15

DDR2 SDRAM

Table 16. DDR2 SDRAM Output AC Timing Specifications (continued)

At recommended operating conditions with GV_DDof 1.8V ± 100mV.

Parameter

Symbol¹

t_DDKHCX

Min

Max

Unit

Note

MCS output hold with respect to MCK

ns

3

266 MHz

2.5

—

MCK to MDQS Skew

t_DDKHMH

t_DDKHDS,

–0.6

0.6

ns

4

5

MDQ/MDM output setup with respect to MDQS

t_DDKLDS

266 MHz

0.9

—

MDQ/MDM output hold with respect to MDQS

t_DDKHDX,

t_DDKLDX

ps

5

266 MHz

MDQS preamble start

1100

—

t_DDKHMP

t_DDKHME

0.75 x t_MCK

0.4 x t_MCK

ns

6

MDQS epilogue end

0.6 x t_MCK

Notes:

1. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. Output hold time can be read as DDR timing

(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,

t_DDKHASsymbolizes DDR timing (DD) for the time t_MCKmemory clock reference (K) goes from the high (H) state until outputs

(A) are setup (S) or output valid time. Also, t_DDKLDXsymbolizes DDR timing (DD) for the time t_MCKmemory clock reference

(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.

2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.

3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MDM/MDQS. For the ADDR/CMD

setup and hold specifications, it is assumed that the Clock Control register is set to adjust the memory clocks by 1/2 applied

cycle.

4. Note that t_DDKHMHfollows the symbol conventions described in note 1. For example, t_DDKHMHdescribes the DDR timing (DD)

from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). t_DDKHMHcan be modified through control

of the DQSS override bits in the TIMING_CFG_2 register. This is typically set to the same delay as the clock adjusts in the

CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same

adjustment value. See the MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Reference

Manual for a description and understanding of the timing modifications enabled by use of these bits.

5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), or data

mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.

6. t_DDKHMPfollows the symbol conventions described in note 1.

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

16

Freescale Semiconductor

DDR2 SDRAM

The following figure shows the DDR SDRAM output timing for the MCK to MDQS skew measurement

(t

).

DDKHMH

MCK

t_MCK

t_DDKHMH(max) = 0.6 ns

MDQS

t_DDKHMH(min) = –0.6 ns

Figure 5. Timing Diagram for t

DDKHMH

The following figure shows the DDR2 SDRAM output timing diagram.

MCK[n]

t_MCK

t_DDKHAS,t_DDKHCS

t_DDKHAX,t_DDKHCX

ADDR/CMD

MDQS[n]

Write A0

t_DDKHMP

NOOP

t_DDKHMH

t_DDKHME

t_DDKHDS

t_DDKLDS

MDQ[x]/

MECC[x]

D0

D1

t_DDKLDX

t_DDKHDX

Figure 6. DDR2 SDRAM Output Timing Diagram

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

Freescale Semiconductor

17

Local Bus

7 Local Bus

This section describes the DC and AC electrical specifications for the local bus interface of the

MPC8306S.

7.1

Local Bus DC Electrical Characteristics

The following table provides the DC electrical characteristics for the local bus interface.

Table 17. Local Bus DC Electrical Characteristics

Parameter

High-level input voltage

Symbol

Min

Max

Unit

V_IH

V_IL

2

–0.3

OV_DD+ 0.3

V

Low-level input voltage

0.8

—

High-level output voltage, I_OH= –100 A

Low-level output voltage, I_OL= 100 A

Input current

V_OH

V_OL

I_IN

OV_DD– 0.2

—

V

0.2

±5

V

—

A

7.2

Local Bus AC Electrical Specifications

The following table describes the general timing parameters of the local bus interface of the MPC8306S.

Table 18. Local Bus General Timing Parameters

Parameter

Symbol¹

Min

Max

Unit

Note

Local bus cycle time

t_LBK

15

7

—

3

ns

2

3, 4

3

Input setup to local bus clock (LCLKn)

Input hold from local bus clock (LCLKn)

Local bus clock (LCLKn) to output valid

Local bus clock (LCLKn) to output high impedance for LAD/LDP

Notes:

t_LBIVKH

t_LBIXKH

t_LBKHOV

t_LBKHOZ

1.0

—

4

5

1. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_LBIXKH1symbolizes local bus

timing (LB) for the input (I) to go invalid (X) with respect to the time the t_LBKclock reference (K) goes high (H), in this case

for clock one(1).

2. All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or rising edge of

LCLK0 (for all other inputs).

3. All signals are measured from OV_DD/2 of the rising/falling edge of LCLK0 to 0.4  OV_DDof the signal in question for 3.3-V

signaling levels.

4. Input timings are measured at the pin.

5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

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Freescale Semiconductor

Local Bus

The following figure provides the AC test load for the local bus.

OV_DD/2

Output

Z₀= 50 

R_L= 50 

Figure 7. Local Bus AC Test Load

The following figures show the local bus signals. These figures has been given indicate timing parameters

only and do not reflect actual functional operation of interface.

LCLK[n]

t_LBIXKH

t_LBIVKH

Input Signals:

LAD[0:15]

t_LBIXKH

t_LBIVKH

Input Signal:

LGTA

t_LBIXKH

t_LBKHOV

Output Signals:

LBCTL/LBCKE/LOE

t_LBKHOZ

t_LBKHOV

Output Signals:

LAD[0:15]

t_LBOTOT

LALE

Figure 8. Local Bus Signals

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

Freescale Semiconductor

19

Local Bus

LCLK

T1

T3

t_LBKHOZ

t_LBKHOV

GPCM Mode Output Signals:

LCS[0:3]/LWE

t_LBIXKH

t_LBIVKH

UPM Mode Input Signal:

LUPWAIT

t_LBIXKH

t_LBIVKH

Input Signals:

LAD[0:15]/LDP[0:3]

t_LBKHOZ

t_LBKHOV

UPM Mode Output Signals:

LCS[0:3]/LBS[0:1]/LGPL[0:5]

Figure 9. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 2

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

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Freescale Semiconductor

Ethernet and MII Management

LCLK

T1

T2

T3

T4

t_LBKHOZ

t_LBKHOV

GPCM Mode Output Signals:

LCS[0:3]/LWE

t_LBIXKH

t_LBIVKH

UPM Mode Input Signal:

LUPWAIT

t_LBIXKH

t_LBIVKH

Input Signals:

LAD[0:15]

t_LBKHOZ

t_LBKHOV

UPM Mode Output Signals:

LCS[0:3]/LBS[0:1]/LGPL[0:5]

Figure 10. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4

8 Ethernet and MII Management

This section provides the AC and DC electrical characteristics for Ethernet interfaces.

8.1

Ethernet Controller (10/100 Mbps)—MII/RMII Electrical

Characteristics

The electrical characteristics specified here apply to all MII (media independent interface) and RMII

(reduced media independent interface), except MDIO (management data input/output) and MDC

(management data clock). The MII and RMII are defined for 3.3 V. The electrical characteristics for MDIO

and MDC are specified in Section 8.3, “Ethernet Management Interface Electrical Characteristics.”

8.1.1

DC Electrical Characteristics

All MII and RMII drivers and receivers comply with the DC parametric attributes specified in The

following table.

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

Freescale Semiconductor

21

Ethernet and MII Management

Parameter

Table 19. MII and RMII DC Electrical Characteristics

Symbol

Conditions

Min

Max

Unit

Supply voltage 3.3 V

Output high voltage

Output low voltage

Input high voltage

Input low voltage

Input current

OV_DD

V_OH

V_OL

V_IH

—

3

3.6

OV_DD+ 0.3

0.50

V

I_OH= –4.0 mA OV_DD= Min

2.40

GND

2.0

I_OL= 4.0 mA

OV_DD= Min

V

—

OV_DD+ 0.3

0.90

V

V_IL

–0.3

—

V

I_IN

0 V  V_IN OV_DD

±5

A

8.2

MII and RMII AC Timing Specifications

The AC timing specifications for MII and RMII are presented in this section.

8.2.1

MII AC Timing Specifications

This section describes the MII transmit and receive AC timing specifications.

8.2.1.1 MII Transmit AC Timing Specifications

The following table provides the MII transmit AC timing specifications.

Table 20. MII Transmit AC Timing Specifications

At recommended operating conditions with OV_DDof 3.3 V ± 300mV.

Parameter/Condition

TX_CLK clock period 10 Mbps

Symbol¹

Min

Typical

Max

Unit

t_MTX

—

400

40

—

5

—

ns

%

TX_CLK clock period 100 Mbps

TX_CLK duty cycle

t

_MTXH/t_MTX

t_MTKHDX

t_MTXR

35

1

65

15

4.0

TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay

TX_CLK data clock rise V_IL(min) to V_IH(max)

TX_CLK data clock fall V_IH(max) to V_IL(min)

Note:

ns

1.0

—

t_MTXF

1. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_MTKHDXsymbolizes MII transmit

timing (MT) for the time t_MTXclock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general,

the clock reference symbol representation is based on two to three letters representing the clock of a particular functional.

For example, the subscript of t_MTXrepresents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is

used with the appropriate letter: R (rise) or F (fall).

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

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Freescale Semiconductor

Ethernet and MII Management

The following figure provides the AC test load.

OV_DD/2

Output

Z₀= 50 

R_L= 50 

Figure 11. AC Test Load

The following figure shows the MII transmit AC timing diagram.

t_MTXR

t_MTX

TX_CLK

t_MTXF

t_MTXH

TXD[3:0]

TX_EN

TX_ER

t_MTKHDX

Figure 12. MII Transmit AC Timing Diagram

8.2.1.2

MII Receive AC Timing Specifications

The following table provides the MII receive AC timing specifications.

Table 21. MII Receive AC Timing Specifications

At recommended operating conditions with OV_DDof 3.3 V ± 300mV.

Parameter/Condition

RX_CLK clock period 10 Mbps

Symbol¹

Min

Typical

Max

Unit

t_MRX

—

400

40

—

ns

%

RX_CLK clock period 100 Mbps

RX_CLK duty cycle

t

_MRXH/t_MRX

t_MRDVKH

t_MRDXKH

t_MRXR

35

65

—

RXD[3:0], RX_DV, RX_ER setup time to RX_CLK

RXD[3:0], RX_DV, RX_ER hold time to RX_CLK

RX_CLK clock rise V_IL(min) to V_IH(max)

RX_CLK clock fall time V_IH(max) to V_IL(min)

Note:

10.0

1.0

—

ns

—

4.0

t_MRXF

—

1. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_MRDVKHsymbolizes MII receive

timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t_MRXclock reference (K)

going to the high (H) state or setup time. Also, t_MRDXKLsymbolizes MII receive timing (GR) with respect to the time data input

signals (D) went invalid (X) relative to the t_MRXclock reference (K) going to the low (L) state or hold time. Note that, in general,

the clock reference symbol representation is based on three letters representing the clock of a particular functional. For

example, the subscript of t_MRXrepresents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used

with the appropriate letter: R (rise) or F (fall).

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

Freescale Semiconductor

23

Ethernet and MII Management

The following figure shows the MII receive AC timing diagram.

t_MRXR

t_MRX

RX_CLK

t_MRXH

t_MRXF

Valid Data

RXD[3:0]

RX_DV

RX_ER

t_MRDVKH

t_MRDXKH

Figure 13. MII Receive AC Timing Diagram

8.2.2

RMII AC Timing Specifications

This section describes the RMII transmit and receive AC timing specifications.

8.2.2.1 RMII Transmit AC Timing Specifications

The following table provides the RMII transmit AC timing specifications.

Table 22. RMII Transmit AC Timing Specifications

At recommended operating conditions with OV_DDof 3.3 V ± 300mV.

Parameter/Condition

Symbol¹

Min

Typical

Max

Unit

REF_CLK clock

t_RMX

_RMXH/t_RMX

t_RMTKHDX

t_RMXR

—

35

2

20

—

65

ns

%

REF_CLK duty cycle

t

REF_CLK to RMII data TXD[1:0], TX_EN delay

REF_CLK data clock rise V_IL(min) to V_IH(max)

REF_CLK data clock fall V_IH(max) to V_IL(min)

Note:

13

ns

1.0

4.0

t_RMXF

1. The symbols used for timing specifications follow the pattern of t_{(first three letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_RMTKHDXsymbolizes RMII

transmit timing (RMT) for the time t_RMXclock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in

general, the clock reference symbol representation is based on two to three letters representing the clock of a particular

functional. For example, the subscript of t_RMXrepresents the RMII(RM) reference (X) clock. For rise and fall times, the latter

convention is used with the appropriate letter: R (rise) or F (fall).

The following figure provides the AC test load.

OV_DD/2

Output

Z₀= 50 

R_L= 50 

Figure 14. AC Test Load

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

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Freescale Semiconductor

Ethernet and MII Management

The following figure shows the RMII transmit AC timing diagram.

t_RMX

t_RMXR

REF_CLK

t_RMXF

t_RMXH

TXD[1:0]

TX_EN

t_RMTKHDX

Figure 15. RMII Transmit AC Timing Diagram

8.2.2.2

RMII Receive AC Timing Specifications

The following table provides the RMII receive AC timing specifications.

Table 23. RMII Receive AC Timing Specifications

At recommended operating conditions with OV_DDof 3.3 V ± 300mV.

Parameter/Condition

REF_CLK clock period

Symbol¹

Min

Typical

Max

Unit

t_RMX

t_RMXH/t_RMX

t_RMRDVKH

t_RMRDXKH

t_RMXR

—

35

20

—

65

—

ns

%

REF_CLK duty cycle

RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK

RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK

REF_CLK clock rise V_IL(min) to V_IH(max)

REF_CLK clock fall time V_IH(max) to V_IL(min)

Note:

4.0

2.0

1.0

ns

—

4.0

t_RMXF

1. The symbols used for timing specifications follow the pattern of t_{(first three letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_RMRDVKHsymbolizes RMII

receive timing (RMR) with respect to the time data input signals (D) reach the valid state (V) relative to the t_RMXclock

reference (K) going to the high (H) state or setup time. Also, t_RMRDXKLsymbolizes RMII receive timing (RMR) with respect

to the time data input signals (D) went invalid (X) relative to the t_RMXclock reference (K) going to the low (L) state or hold

time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a

particular functional. For example, the subscript of t_RMXrepresents the RMII (RM) reference (X) clock. For rise and fall times,

the latter convention is used with the appropriate letter: R (rise) or F (fall).

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

Freescale Semiconductor

25

Ethernet and MII Management

The following figure shows the RMII receive AC timing diagram.

t_RMXR

t_RMX

REF_CLK

t_RMXH

t_RMXF

Valid Data

RXD[1:0]

CRS_DV

RX_ER

t_RMRDVKH

t_RMRDXKH

Figure 16. RMII Receive AC Timing Diagram

8.3

Ethernet Management Interface Electrical Characteristics

The electrical characteristics specified here apply to MII management interface signals MDIO

(management data input/output) and MDC (management data clock). The electrical characteristics for

MII, and RMII are specified in Section 8.1, “Ethernet Controller (10/100 Mbps)—MII/RMII Electrical

Characteristics.”

8.3.1

MII Management DC Electrical Characteristics

MDC and MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics for

MDIO and MDC are provided in the following table.

Table 24. MII Management DC Electrical Characteristics When Powered at 3.3 V

Parameter

Symbol

Conditions

Min

Max

Unit

Supply voltage (3.3 V)

Output high voltage

Output low voltage

Input high voltage

Input low voltage

Input current

OV_DD

V_OH

V_OL

V_IH

—

3

3.6

OV_DD+ 0.3

0.50

V

I_OH= –1.0 mA OV_DD= Min

2.40

GND

2.00

—

I_OL= 1.0 mA

OV_DD= Min

V

—

V

V_IL

0.80

V

I_IN

0 V  V_IN OV_DD

—

±5

A

8.3.2

MII Management AC Electrical Specifications

The following table provides the MII management AC timing specifications.

Table 25. MII Management AC Timing Specifications

At recommended operating conditions with OV_DDis 3.3 V ± 300mV.

Parameter/Condition

MDC frequency

Symbol¹

Min

Typical

Max

Unit

Note

f_MDC

t_MDC

—

32

2.5

400

—

MHz

ns

—

MDC period

MDC clock pulse width high

t_MDCH

ns

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

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Freescale Semiconductor

Ethernet and MII Management

Table 25. MII Management AC Timing Specifications (continued)

At recommended operating conditions with OV_DDis 3.3 V ± 300mV.

Parameter/Condition

MDC to MDIO delay

Symbol¹

Min

Typical

Max

Unit

Note

t_MDKHDX

t_MDDVKH

10

—

70

—

ns

—

MDIO to MDC setup time

8.5

MDIO to MDC hold time

MDC rise time

MDC fall time

Note:

t_MDDXKH

t_MDCR

0

—

10

ns

—

t_MDHF

1. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_MDKHDXsymbolizes

management data timing (MD) for the time t_MDCfrom clock reference (K) high (H) until data outputs (D) are invalid (X) or data

hold time. Also, t_MDDVKHsymbolizes management data timing (MD) with respect to the time data input signals (D) reach the

valid state (V) relative to the t_MDCclock reference (K) going to the high (H) state or setup time. For rise and fall times, the

latter convention is used with the appropriate letter: R (rise) or F (fall).

The following figure shows the MII management AC timing diagram.

t_MDC

t_MDCR

MDC

t_MDCH

t_MDCF

MDIO

(Input)

t_MDDVKH

t_MDDXKH

MDIO

(Output)

t_MDKHDX

Figure 17. MII Management Interface Timing Diagram

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

Freescale Semiconductor

27

TDM/SI

9 TDM/SI

This section describes the DC and AC electrical specifications for the time-division-multiplexed and serial

interface of the MPC8306S.

9.1

TDM/SI DC Electrical Characteristics

The following table provides the DC electrical characteristics for the MPC8306S TDM/SI.

Table 26. TDM/SI DC Electrical Characteristics

Characteristic

Output high voltage

Symbol

Condition

Min

Max

Unit

V_OH

V_OL

V_IH

V_IL

I_OH= –2.0 mA

2.4

—

0.5

V

Output low voltage

Input high voltage

Input low voltage

Input current

I_OL= 3.2 mA

—

2.0

–0.3

—

OV_DD+ 0.3

0.8

V

I_IN

0 V  V_IN OV_DD

±5

A

9.2

TDM/SI AC Timing Specifications

The following table provides the TDM/SI input and output AC timing specifications.

1

Table 27. TDM/SI AC Timing Specifications

Characteristic

TDM/SI outputs—External clock delay

Symbol²

Min

Max

Unit

t_SEKHOV

2

14

ns

TDM/SI outputs—External clock High Impedance

TDM/SI inputs—External clock input setup time

TDM/SI inputs—External clock input hold time

Notes:

t_SEKHOX

t_SEIVKH

t_SEIXKH

2

5

2

10

—

ns

1. Output specifications are measured from the 50% level of the rising edge of QE_CLK_IN to the 50% level of the signal.

Timings are measured at the pin.

2. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_SEKHOXsymbolizes the TDM/SI

outputs external timing (SE) for the time t_TDM/SImemory clock reference (K) goes from the high state (H) until outputs (O)

are invalid (X).

The following figure provides the AC test load for the TDM/SI.

OV_DD/2

Output

Z₀= 50 

R_L= 50 

Figure 18. TDM/SI AC Test Load

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

28

Freescale Semiconductor

HDLC

The following figure represents the AC timing from Table 27. Note that although the specifications

generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge

is the active edge.

TDM/SICLK (Input)

t_SEIXKH

t_SEIVKH

Input Signals:

TDM/SI

(See Note)

t_SEKHOV

Output Signals:

TDM/SI

(See Note)

t_SEKHOX

Note: The clock edge is selectable on TDM/SI.

Figure 19. TDM/SI AC Timing (External Clock) Diagram

10 HDLC

This section describes the DC and AC electrical specifications for the high level data link control (HDLC),

of the MPC8306S.

10.1 HDLC DC Electrical Characteristics

The following table provides the DC electrical characteristics for the MPC8306S HDLC protocol.

Table 28. HDLC DC Electrical Characteristics

Characteristic

Output high voltage

Symbol

Condition

Min

Max

Unit

V_OH

V_OL

V_IH

V_IL

I_OH= –2.0 mA

2.4

—

0.5

V

Output low voltage

Input high voltage

Input low voltage

Input current

I_OL= 3.2 mA

—

2.0

–0.3

—

OV_DD+ 0.3

0.8

V

I_IN

0 V  V_INOV_DD

±5

A

10.2 HDLC AC Timing Specifications

The following table provides the input and output AC timing specifications for HDLC protocol.

1

Table 29. HDLC AC Timing Specifications

Characteristic

Outputs—Internal clock delay

Symbol²

Min

Max

Unit

t_HIKHOV

0

9

ns

Outputs—External clock delay

t_HEKHOV

t_HIKHOX

1

0

12

ns

Outputs—Internal clock high impedance

5.5

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

Freescale Semiconductor

29

HDLC

1

Table 29. HDLC AC Timing Specifications (continued)

Characteristic

Symbol²

Min

Max

Unit

Outputs—External clock high impedance

Inputs—Internal clock input setup time

t_HEKHOX

t_HIIVKH

1

9

8

ns

—

Inputs—External clock input setup time

Inputs—Internal clock input hold time

Inputs—External clock input hold time

Notes:

t_HEIVKH

t_HIIXKH

t_HEIXKH

4

0

1

—

ns

1. Output specifications are measured from the 50% level of the rising edge of QE_CLK_IN to the 50% level of the signal.

Timings are measured at the pin.

2. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_HIKHOXsymbolizes the outputs

internal timing (HI) for the time t_serialmemory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X).

The following figure provides the AC test load.

OV_DD/2

Output

Z₀= 50 

R_L= 50 

Figure 20. AC Test Load

Figure 21 and Figure 22 represent the AC timing from Table 29. Note that although the specifications

generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge

is the active edge.

The following figure shows the timing with external clock.

Serial CLK (Input)

t_HEIXKH

t_HEIVKH

Input Signals:

(See Note)

t_HEKHOV

Output Signals:

(See Note)

t_HEKHOX

Note: The clock edge is selectable.

Figure 21. AC Timing (External Clock) Diagram

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

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Freescale Semiconductor

USB

The following figure shows the timing with internal clock.

Serial CLK (Output)

t_HIIXKH

t_HIIVKH

Input Signals:

(See Note)

t_HIKHOV

Output Signals:

(See Note)

t_HIKHOX

Note: The clock edge is selectable.

Figure 22. AC Timing (Internal Clock) Diagram

11 USB

11.1 USB Controller

This section provides the AC and DC electrical specifications for the USB (ULPI) interface.

11.1.1 USB DC Electrical Characteristics

The following table provides the DC electrical characteristics for the USB interface.

Table 30. USB DC Electrical Characteristics

Parameter

High-level input voltage

Symbol

Min

Max

Unit

V_IH

V_IL

2.0

–0.3

OV_DD+ 0.3

V

Low-level input voltage

0.8

±5

Input current

I_IN

—

A

V

High-level output voltage, I_OH= –100 A

Low-level output voltage, I_OL= 100 A

V_OH

V_OL

OV_DD– 0.2

—

0.2

V

11.1.2 USB AC Electrical Specifications

The following table describes the general timing parameters of the USB interface.

Table 31. USB General Timing Parameters

Parameter

Symbol¹

Min

Max

Unit

Note

USB clock cycle time

t_USCK

t_USIVKH

t_USIXKH

t_USKHOV

15

4

—

7

ns

—

Input setup to USB clock—all inputs

input hold to USB clock—all inputs

1

USB clock to output valid—all outputs (except

USBDR_STP_USBDR_STP)

—

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

Freescale Semiconductor

31

USB

Table 31. USB General Timing Parameters (continued)

Parameter

Symbol¹

Min

Max

Unit

Note

USB clock to output valid—USBDR_STP

Output hold from USB clock—all outputs

Note:

t_USKHOV

t_USKHOX

—

2

7.5

—

ns

—

1. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_USIXKHsymbolizes USB timing

(USB) for the input (I) to go invalid (X) with respect to the time the USB clock reference (K) goes high (H). Also, t_USKHOX

symbolizes us timing (USB) for the USB clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or

output hold time.

The following figures provide the AC test load and signals for the USB, respectively.

Output

OV_DD/2

Z₀= 50 

R_L= 50 

Figure 23. USB AC Test Load

USBDR_CLK

t_USIXKH

t_USIVKH

Input Signals

t_USKHOV

t_USKHOX

Output Signals

Figure 24. USB Signals

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

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Freescale Semiconductor

DUART

12 DUART

This section describes the DC and AC electrical specifications for the DUART interface of the MPC8306S.

12.1 DUART DC Electrical Characteristics

The following table provides the DC electrical characteristics for the DUART interface of the MPC8306S.

Table 32. DUART DC Electrical Characteristics

Parameter

Symbol

Min

Max

Unit

High-level input voltage

V_IH

V_IL

2

–0.3

OV_DD+ 0.3

V

Low-level input voltage OV_DD

0.8

—

High-level output voltage, I_OH= –100 A

V_OH

V_OL

I_IN

OV_DD– 0.2

—

V

Low-level output voltage, I_OL= 100 A

0.2

±5

V

1

Input current (0 V V_INOV_DD

)

—

A

Note:

1. Note that the symbol V_IN, in this case, represents the OV_INsymbol referenced in Table 1 and Table 2.

12.2 DUART AC Electrical Specifications

The following table provides the AC timing parameters for the DUART interface of the MPC8306S.

Table 33. DUART AC Timing Specifications

Parameter

Value

Unit

Note

Minimum baud rate

Maximum baud rate

Oversample rate

Notes:

256

>1,000,000

16

baud

—

1

2

1. Actual attainable baud rate is limited by the latency of interrupt processing.

2. The middle of a start bit is detected as the 8^thsampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are

sampled each 16^thsample.

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33

I²C

13 I²C

2

This section describes the DC and AC electrical characteristics for the I C interface of the MPC8306S.

2

13.1 I C DC Electrical Characteristics

2

The following table provides the DC electrical characteristics for the I C interface of the MPC8306S.

2

Table 34. I C DC Electrical Characteristics

At recommended operating conditions with OV_DDof 3.3 V ± 300mV.

Parameter

Symbol

Min

Max

Unit

Notes

Input high voltage level

Input low voltage level

V_IH

V_IL

0.7  OV_DD

OV_DD+ 0.3

0.3  OV_DD

0.4

V

—

1

–0.3

0

Low level output voltage

V_OL

V

Output fall time from V_IH(min) to V_IL(max) with a bus

capacitance from 10 to 400 pF

t

20 + 0.1  C_B

250

ns

2

I2KLKV

Pulse width of spikes which must be suppressed by the

input filter

t_I2KHKL

0

50

ns

3

Capacitance for each I/O pin

C_I

—

10

±5

pF

—

4

Input current (0 V V_INOV_DD

)

I_IN

A

Notes:

1. Output voltage (open drain or open collector) condition = 3 mA sink current.

2. C_B= capacitance of one bus line in pF.

3. Refer to the MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Reference Manual for information

on the digital filter used.

4. I/O pins obstructs the SDA and SCL lines if OV_DDis switched off.

2

13.2 I C AC Electrical Specifications

2

The following table provides the AC timing parameters for the I C interface of the MPC8306S.

2

Table 35. I C AC Electrical Specifications

All values refer to V_IH(min) and V_IL(max) levels (see Table 34).

Parameter

Symbol¹

Min

Max

Unit

SCL clock frequency

f_I2C

t_I2CL

0

400

—

kHz

s

Low period of the SCL clock

High period of the SCL clock

1.3

0.6

t_I2CH

—

s

Setup time for a repeated START condition

t_I2SVKH

t_I2SXKL

—

s

Hold time (repeated) START condition (after this period, the first clock

pulse is generated)

—

s

Data setup time

t_I2DVKH

t_I2DXKL

t_I2CR

100

300

—

ns

s

ns

Data hold time: I²C bus devices

0.9³

4

Rise time of both SDA and SCL signals

20 + 0.1 C_B

300

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

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Freescale Semiconductor

I²C

2

Table 35. I C AC Electrical Specifications (continued)

All values refer to V_IH(min) and V_IL(max) levels (see Table 34).

Parameter

Symbol¹

Min

Max

Unit

4

Fall time of both SDA and SCL signals

Setup time for STOP condition

20 + 0.1 C_B

300

—

ns

s

V

t

I2CF

t

0.6

1.3

I2PVKH

Bus free time between a STOP and START condition

t_I2KHDX

V_NL

—

Noise margin at the LOW level for each connected device (including

hysteresis)

0.1  OV_DD

—

Noise margin at the HIGH level for each connected device (including

hysteresis)

V_NH

0.2  OV_DD

—

V

Notes:

1. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_I2DVKHsymbolizes I²C timing (I2)

with respect to the time data input signals (D) reach the valid state (V) relative to the t_I2Cclock reference (K) going to the high

(H) state or setup time. Also, t_I2SXKLsymbolizes I²C timing (I2) for the time that the data with respect to the start condition

(S) went invalid (X) relative to the t_I2Cclock reference (K) going to the low (L) state or hold time. Also, t_I2PVKHsymbolizes I²C

timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the t_I2Cclock

reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate

letter: R (rise) or F (fall).

2. MPC8306S provides a hold time of at least 300 ns for the SDA signal (referred to the V_IH(min) of the SCL signal) to bridge the

undefined region of the falling edge of SCL.

3. The maximum t_I2DVKLhas only to be met if the device does not stretch the LOW period (t_I2CL) of the SCL signal.

4. C_B= capacitance of one bus line in pF.

2

The following figure provides the AC test load for the I C.

OV_DD/2

Output

Z₀= 50 

R_L= 50 

2

Figure 25. I C AC Test Load

2

The following figure shows the AC timing diagram for the I C bus.

SDA

t_I2CF

t_I2CL

t_I2DVKH

t_I2KHKL

t_I2CF

t_I2SXKL

t_I2CR

SCL

t_I2SXKL

t_I2CH

t_I2SVKH

t_I2PVKH

t_I2DXKL

S

Sr

Figure 26. I C Bus AC Timing Diagram

P

S

2

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

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35

Timers

14 Timers

This section describes the DC and AC electrical specifications for the timers of the MPC8306S.

14.1 Timer DC Electrical Characteristics

The following table provides the DC electrical characteristics for the MPC8306S timer pins, including

TIN, TOUT, TGATE, and RTC_PIT_CLK.

Table 36. Timer DC Electrical Characteristics

Characteristic

Output high voltage

Symbol

Condition

Min

Max

Unit

V_OH

V_OL

I_OH= –6.0 mA

I_OL= 6.0 mA

2.4

—

0.5

V

Output low voltage

Input high voltage

Input low voltage

Input current

V

I

= 3.2 mA

OL

—

0.4

V

OL

V_IH

V_IL

I_IN

—

2.0

–0.3

—

OV_DD+ 0.3

0.8

V

0 V  V_IN OV_DD

±5

A

14.2 Timer AC Timing Specifications

The following table provides the timer input and output AC timing specifications.

1

Table 37. Timer Input AC Timing Specifications

Characteristic

Timers inputs—minimum pulse width

Notes:

Symbol²

Min

Unit

t_TIWID

20

ns

1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of SYS_CLK_IN.

Timings are measured at the pin.

2. Timer inputs and outputs are asynchronous to any visible clock. Timer outputs should be synchronized before use by any

external synchronous logic. Timer inputs are required to be valid for at least t_TIWIDns to ensure proper operation.

The following figure provides the AC test load for the timers.

OV_DD/2

Output

Z₀= 50 

R_L= 50 

Figure 27. Timers AC Test Load

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

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Freescale Semiconductor

GPIO

15 GPIO

This section describes the DC and AC electrical specifications for the GPIO of the MPC8306S.

15.1 GPIO DC Electrical Characteristics

The following table provides the DC electrical characteristics for the MPC8306S GPIO.

Table 38. GPIO DC Electrical Characteristics

Characteristic

Output high voltage

Symbol

Condition

Min

Max

Unit

Notes

V_OH

V_OL

I_OH= –6.0 mA

I_OL= 6.0 mA

2.4

—

0.5

V

1

Output low voltage

Input high voltage

Input low voltage

Input current

V

I

= 3.2 mA

OL

—

0.4

V

1

OL

V_IH

V_IL

I_IN

—

2.0

–0.3

—

OV_DD+ 0.3

0.8

V

1

V

—

0 V V_INOV_DD

±5

A

Note:

1. This specification applies when operating from 3.3-V supply.

15.2 GPIO AC Timing Specifications

The following table provides the GPIO input and output AC timing specifications.

1

Table 39. GPIO Input AC Timing Specifications

Characteristic

GPIO inputs—minimum pulse width

Notes:

Symbol²

Min

20

Unit

t_PIWID

ns

1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of SYS_CLK_IN.

Timings are measured at the pin.

2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any

external synchronous logic. GPIO inputs are required to be valid for at least t_PIWIDns to ensure proper operation.

The following figure provides the AC test load for the GPIO.

OV_DD/2

Output

Z₀= 50 

R_L= 50 

Figure 28. GPIO AC Test Load

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

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37

IPIC

16 IPIC

This section describes the DC and AC electrical specifications for the external interrupt pins of the

MPC8306S.

16.1 IPIC DC Electrical Characteristics

The following table provides the DC electrical characteristics for the external interrupt pins of the

MPC8306S.

1,2

Table 40. IPIC DC Electrical Characteristics

Characteristic

Input high voltage

Symbol

Condition

Min

Max

Unit

V_IH

V_IL

—

2.0

–0.3

—

OV_DD+ 0.3

V

Input low voltage

Input current

0.8

±5

I_IN

—

A

V

Output High Voltage

Output low voltage

Notes:

V_OH

V_OL

I_OL= -8.0 mA

I_OL= 6.0 mA

2.4

—

0.5

0.4

V

I

= 3.2 mA

OL

—

V

OL

1. This table applies for pins IRQ, MCP_OUT, and QE ports Interrupts.

2. MCP_OUT is open drain pins, thus V_OHis not relevant for those pins.

16.2 IPIC AC Timing Specifications

The following table provides the IPIC input and output AC timing specifications.

1

Table 41. IPIC Input AC Timing Specifications

Characteristic

Symbol²

Min

Unit

IPIC inputs—minimum pulse width

t_PIWID

20

ns

Notes:

1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of SYS_CLK_IN.

Timings are measured at the pin.

2. IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by any

external synchronous logic. IPIC inputs are required to be valid for at least t_PIWIDns to ensure proper operation when working

in edge triggered mode.

17 SPI

This section describes the DC and AC electrical specifications for the SPI of the MPC8306S.

17.1 SPI DC Electrical Characteristics

The following table provides the DC electrical characteristics for the MPC8306S SPI.

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

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Freescale Semiconductor

SPI

Table 42. SPI DC Electrical Characteristics

Characteristic

Output high voltage

Symbol

Condition

Min

Max

Unit

V_OH

V_OL

I_OH= –6.0 mA

I_OL= 6.0 mA

2.4

—

0.5

V

Output low voltage

Input high voltage

Input low voltage

Input current

V

I

= 3.2 mA

OL

—

0.4

V

OL

V_IH

V_IL

I_IN

—

2.0

–0.3

—

OV_DD+ 0.3

0.8

V

0 V  V_IN OV_DD

±5

A

17.2 SPI AC Timing Specifications

The following table and provide the SPI input and output AC timing specifications.

1

Table 43. SPI AC Timing Specifications

Characteristic

Symbol²

Min

Max

Unit

SPI outputs—Master mode (internal clock) delay

SPI outputs—Slave mode (external clock) delay

SPI inputs—Master mode (internal clock) input setup time

SPI inputs—Master mode (internal clock) input hold time

SPI inputs—Slave mode (external clock) input setup time

SPI inputs—Slave mode (external clock) input hold time

Notes:

t_NIKHOV

t_NEKHOV

t_NIIVKH

0.5

2

6

ns

8

6

—

t_NIIXKH

0

t_NEIVKH

t_NEIXKH

4

2

1. Output specifications are measured from the 50% level of the rising edge of SPICLK to the 50% level of the signal. Timings

are measured at the pin.

2. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_NIKHOVsymbolizes the NMSI

outputs internal timing (NI) for the time t_SPImemory clock reference (K) goes from the high state (H) until outputs (O) are

valid (V).

3. All units of output delay must be enabled for 8306S output port spimosi (SPI Master Mode)

4. delay units must not be enabled for Slave Mode.

The following figure provides the AC test load for the SPI.

OV_DD/2

Output

Z₀= 50 

R_L= 50 

Figure 29. SPI AC Test Load

Figure 30 and Figure 31 represent the AC timing from Table 43. Note that although the specifications

generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge

is the active edge.

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

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39

JTAG

The following figure shows the SPI timing in slave mode (external clock).

SPICLK (Input)

t_NEIXKH

t_NEIVKH

Input Signals:

SPIMOSI

(See Note)

t_NEKHOV

Output Signals:

SPIMISO

(See Note)

Note: The clock edge is selectable on SPI.

Figure 30. SPI AC Timing in Slave Mode (External Clock) Diagram

The following figure shows the SPI timing in master mode (internal clock).

SPICLK (Output)

t_NIIXKH

t_NIIVKH

Input Signals:

SPIMISO

(See Note)

t_NIKHOV

Output Signals:

SPIMOSI

(See Note)

Note: The clock edge is selectable on SPI.

Figure 31. SPI AC Timing in Master Mode (Internal Clock) Diagram

18 JTAG

This section describes the DC and AC electrical specifications for the IEEE Std. 1149.1™ (JTAG)

interface of the MPC8306S.

18.1 JTAG DC Electrical Characteristics

The following table provides the DC electrical characteristics for the IEEE Std. 1149.1 (JTAG) interface

of the MPC8306S.

Table 44. JTAG Interface DC Electrical Characteristics

Characteristic

Output high voltage

Symbol

Condition

Min

Max

Unit

V_OH

V_OL

I_OH= –6.0 mA

I_OL= 6.0 mA

2.4

—

V

Output low voltage

0.5

0.4

V

I

= 3.2 mA

OL

—

OL

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

40

Freescale Semiconductor

JTAG

Table 44. JTAG Interface DC Electrical Characteristics (continued)

Characteristic

Input high voltage

Symbol

Condition

Min

Max

Unit

V_IH

V_IL

I_IN

—

2.0

–0.3

—

OV_DD+ 0.3

V

Input low voltage

Input current

0.8

±5

0 V  V_IN OV_DD

A

18.2 JTAG AC Electrical Characteristics

This section describes the AC electrical specifications for the IEEE Std. 1149.1 (JTAG) interface of the

MPC8306S. The following table provides the JTAG AC timing specifications as defined in Figure 33

through Figure 36.

1

Table 45. JTAG AC Timing Specifications (Independent of SYS_CLK_IN)

At recommended operating conditions (see Table 2).

Parameter

Symbol²

Min

Max

Unit

Notes

JTAG external clock frequency of operation

JTAG external clock cycle time

JTAG external clock pulse width measured at 1.4 V

JTAG external clock rise and fall times

TRST assert time

f_JTG

t _JTG

0

33.3

—

MHz

ns

—

3

30

11

0

t_JTKHKL

t_JTGR, t_JTGF

t_TRST

—

ns

2

ns

25

—

ns

Input setup times:

ns

Boundary-scan data

t_JTDVKH

t_JTIVKH

4

—

4

5

TMS, TDI

Input hold times:

Valid times:

ns

Boundary-scan data

TMS, TDI

t_JTDXKH

t_JTIXKH

10

—

Boundary-scan data

TDO

t_JTKLDV

t_JTKLOV

2

15

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41

JTAG

1

Table 45. JTAG AC Timing Specifications (Independent of SYS_CLK_IN) (continued)

At recommended operating conditions (see Table 2).

Parameter

Symbol²

Min

Max

Unit

Notes

Output hold times:

ns

Boundary-scan data

TDO

t_JTKLDX

t_JTKLOX

2

—

5

JTAG external clock to output high impedance:

ns

Boundary-scan data

TDO

t_JTKLDZ

t_JTKLOZ

2

19

9

5, 6

6

Notes:

1. All outputs are measured from the midpoint voltage of the falling/rising edge of t_TCLKto the midpoint of the signal in question.

The output timings are measured at the pins. All output timings assume a purely resistive 50-load (see Figure 32).

Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

2. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_JTDVKHsymbolizes JTAG device

timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t_JTGclock reference (K)

going to the high (H) state or setup time. Also, t_JTDXKHsymbolizes JTAG timing (JT) with respect to the time data input signals

(D) went invalid (X) relative to the t_JTGclock reference (K) going to the high (H) state. Note that, in general, the clock reference

symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the

latter convention is used with the appropriate letter: R (rise) or F (fall).

3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

4. Non-JTAG signal input timing with respect to t_TCLK

.

5. Non-JTAG signal output timing with respect to t_TCLK

6. Guaranteed by design and characterization.

.

The following figure provides the AC test load for TDO and the boundary-scan outputs of the MPC8306S.

OV_DD/2

Output

Z₀= 50 

R_L= 50 

Figure 32. AC Test Load for the JTAG Interface

The following figure provides the JTAG clock input timing diagram.

JTAG

External Clock

VM

t_JTKHKL

VM

t_JTGR

t_JTG

VM = Midpoint Voltage (OV /2)

t_JTGF

DD

Figure 33. JTAG Clock Input Timing Diagram

The following figure provides the TRST timing diagram.

TRST

VM

t_TRST

VM = Midpoint Voltage (OV /2)

DD

Figure 34. TRST Timing Diagram

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Freescale Semiconductor

JTAG

The following figure provides the boundary-scan timing diagram.

JTAG

VM

External Clock

t_JTDVKH

t_JTDXKH

Input

Data Valid

Boundary

Data Inputs

t_JTKLDV

t_JTKLDX

Boundary

Data Outputs

Output Data Valid

t_JTKLDZ

Output Data Valid

Boundary

Data Outputs

VM = Midpoint Voltage (OV /2)

DD

Figure 35. Boundary-Scan Timing Diagram

The following figure provides the test access port timing diagram.

JTAG

VM

External Clock

t_JTIVKH

t_JTIXKH

Input

Data Valid

TDI, TMS

t_JTKLOV

t_JTKLOX

TDO

Output Data Valid

t_JTKLOZ

Output Data Valid

VM = Midpoint Voltage (OV /2)

DD

Figure 36. Test Access Port Timing Diagram

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

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43

Package and Pin Listings

19 Package and Pin Listings

This section details package parameters, pin assignments, and dimensions. The MPC8306S is available in

a thermally enhanced MAPBGA (mold array process-ball grid array); see Section 19.1, “Package

Parameters for the MPC8306S,” and Section 19.2, “Mechanical Dimensions of the MPC8306S

MAPBGA,” for information on the MAPBGA.

19.1 Package Parameters for the MPC8306S

The package parameters are as provided in the following list.

Package outline

Package Type

Interconnects

19 mm 19 mm

MAPBGA

369

Pitch

0.80 mm

Module height (typical)

Solder Balls

1.48 mm; Min = 1.31mm and Max 1.61mm

96 Sn / 3.5 Ag / 0.5 Cu (VM package)

0.40 mm

Ball diameter (typical)

19.2 Mechanical Dimensions of the MPC8306S MAPBGA

The following figure shows the mechanical dimensions and bottom surface nomenclature of the

MPC8306S, 369-MAPBGA package.

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Package and Pin Listings

Figure 37. Mechanical Dimensions and Bottom Surface Nomenclature of the MPC8306S MAPBGA

Notes:

1. All dimensions are in millimeters.

2. Dimensions and tolerances per ASME Y14.5M-1994.

3. Maximum solder ball diameter measured parallel to datum A.

4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls.

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45

Package and Pin Listings

19.3 Pinout Listings

Following table shows the pin list of the MPC8306S.

Table 46. MPC8306S Pinout Listing

Signal

Package Pin Number

Pin Type

Power Supply

Notes

DDR Memory Controller Interface

MEMC_MDQ[0]

MEMC_MDQ[1]

MEMC_MDQ[2]

MEMC_MDQ[3]

MEMC_MDQ[4]

MEMC_MDQ[5]

MEMC_MDQ[6]

MEMC_MDQ[7]

MEMC_MDQ[8]

MEMC_MDQ[9]

MEMC_MDQ[10]

MEMC_MDQ[11]

MEMC_MDQ[12]

MEMC_MDQ[13]

MEMC_MDQ[14]

MEMC_MDQ[15]

MEMC_MDM[0]

MEMC_MDM[1]

MEMC_MDQS[0]

MEMC_MDQS[1]

MEMC_MBA[0]

MEMC_MBA[1]

MEMC_MBA[2]

MEMC_MA[0]

W5

V4

Y4

AB1

AA1

Y2

Y1

W2

G2

G1

F1

IO

O

GV_DD

—

E2

E1

E4

F4

D1

AB2

G4

V5

F5

O

IO

O

L2

L1

O

R4

M1

M4

N1

N2

P1

N4

P2

R1

O

MEMC_MA[1]

O

MEMC_MA[2]

O

MEMC_MA[3]

O

MEMC_MA[4]

O

MEMC_MA[5]

O

MEMC_MA[6]

O

MEMC_MA[7]

O

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Package and Pin Listings

Table 46. MPC8306S Pinout Listing (continued)

Signal

Package Pin Number

Pin Type

Power Supply

Notes

MEMC_MA[8]

T1

O

GV_DD

—

MEMC_MA[9]

P4

MEMC_MA[10]

MEMC_MA[11]

MEMC_MA[12]

MEMC_MA[13]

MEMC_MWE_B

MEMC_MRAS_B

MEMC_MCAS_B

MEMC_MCS_B[0]

MEMC_MCS_B[1]

MEMC_MCKE[0]

MEMC_MCK[0]

MEMC_MCK_B[0]

MEMC_MODT[0]

MEMC_MODT[1]

MEMC_MVREF

L4

T2

U1

U2

K1

K2

J1

J4

H1

U4

V1

W1

H2

H4

L8

Local Bus Controller Interface

LAD[0]

LAD[1]

LAD[2]

LAD[3]

LAD[4]

LAD[5]

LAD[6]

LAD[7]

LAD[8]

LAD[9]

LAD[10]

LAD[11]

LAD[12]

LAD[13]

LAD[14]

LAD[15]

LA[16]

B7

D9

IO

OV_DD

—

A6

B8

A7

A8

A9

D10

B10

A10

B11

D12

D11

A11

A12

B13

A13

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47

Package and Pin Listings

Table 46. MPC8306S Pinout Listing (continued)

Signal

Package Pin Number

Pin Type

Power Supply

Notes

LA[17]

B14

O

IO

O

OV_DD

—

3

LA[18]

A14

LA[19]

A15

LA[20]

A16

LA[21]

B16

LA[22]

A17

LA[23]

B17

LA[24]

A18

LA[25]

B19

LCS_B[0]

LCS_B[1]

LCS_B[2]

LCS_B[3]

LCLK[0]

LGPL[0]

LGPL[1]

LGPL[2]

LGPL[3]

LGPL[4]

LGPL[5]

LWE_B[0]

LWE_B[1]

LBCTL

A19

B20

3

A20

3

A21

3

D13

—

B22

D16

D19

D17

E18

E19

D15

D14

A22

LALE

B23

JTAG

TCK

A3

I

OV_DD

—

3

TDI

B5

TDO

D7

O

I

—

3

TMS

A4

TRST_B

D8

I

3

Test Interface

TEST_MODE

A5

I

OV_DD

—

System Control Signals

HRESET_B

U20

V20

IO

I

OV_DD

1

PORESET_B

—

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Package and Pin Listings

Table 46. MPC8306S Pinout Listing (continued)

Signal

Package Pin Number

Pin Type

Power Supply

Notes

Clock Interface

QE_CLK_IN

P23

I

OV_DD

—

SYS_CLK_IN

RTC_PIT_CLOCK

R23

V23

Miscellaneous Signals

QUIESCE_B

THERM0

A2

D6

O

I

OV_DD

—

GPIO

E5

GPIO[0]/MSRCID0 (DDR ID)

GPIO[1]/MSRCID1 (DDR ID)

GPIO[2]/MSRCID2 (DDR ID)

GPIO[3]/MSRCID3 (DDR ID)

GPIO[4]/MSRCID4 (DDR ID)

GPIO[5]/MDVAL (DDR ID)

GPIO[6]/QE_EXT_REQ_3

GPIO[7]/QE_EXT_REQ_1

IO

OV_DD

—

E6

D4

C2

C1

B1

B3

B2

USB

AC4

Y9

USBDR_PWRFAULT/IIC_SDA2/CE_PIO_1

USBDR_CLK/UART2_SIN[2]/UART2_CTS_B[1]

USBDR_DIR/IIC_SCL2

IO

I

OV_DD

2

AC3

AC2

AB3

IO

2

USBDR_NXT/UART2_SIN[1]/QE_EXT_REQ_4

—

USBDR_PCTL[0]/UART2_SOUT[1]/

LB_POR_CFG_BOOT_ECC

USBDR_PCTL[1]/UART2_SOUT[2]/

Y8

O

OV_DD

—

UART2_RTS_B1/LB_POR_BOOT_ERR

USBDR_STP/QE_EXT_REQ_2

W6

IO

OV_DD

—

USBDR_TXDRXD[0]/UART1_SOUT[1]/

GPIO[32]/QE_TRB_O

AB7

USBDR_TXDRXD[1]/UART1_SIN[1]/GPIO[33]/

QE_TRB_I

AB8

AC6

AC5

IO

OV_DD

—

USBDR_TXDRXD[2]/UART1_SOUT[2]/

UART1_RTS_B1/QE_BRG[1]

USBDR_TXDRXD[3]/UART1_SIN[2]/

UART1_CTS_B1/QE_BRG[2]

USBDR_TXDRXD[4]/GPIO[34]/QE_BRG[3]

USBDR_TXDRXD[5]/GPIO[35]/QE_BRG[4]

USBDR_TXDRXD[6]/GPIO[36]/QE_BRG[9]

AB5

Y7

IO

OV_DD

—

Y6

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Package and Pin Listings

Table 46. MPC8306S Pinout Listing (continued)

Signal

Package Pin Number

Pin Type

Power Supply

Notes

USBDR_TXDRXD[7]/GPIO[37]/QE_BRG[11]

Y5

DUART

C23

IO

OV_DD

—

UART1_SOUT[1]/LSRCID4/LCS_B[4]

UART1_SIN[1]/LDVAL/LCS_B[5]

O

IO

O

OV_DD

—

F19

UART1_SOUT[2]/UART1_RTS_B1/LCS_B[6]

UART1_SIN[2]/UART1_CTS_B[1]/LCS_B[7]

D23

D22

IO

Interrupts

E20

IRQ_B0_MCP_IN_B/CE_PI_0

IRQ_B1/MCP_OUT_B

IO

I

OV_DD

—

E23

IRQ_B2/CKSTOP_OUT_B

IRQ_B3/CKSTOP_IN_B

E22

F20

I2C / SPI

G20

IIC_SDA1

IO

O

OV_DD

2

IIC_SCL1

J20

LCLK1/IIC_SCL2/CKSTOP_IN_B

SPISEL_BOOT/IIC_SDA2/CKSTOP_OUT_B

SPIMOSI/LSRCID[2]

SPIMISO/LSRCID[3]

SPICLK/LSRCID[0]

H20

2

F23

2

G22

IO

I

—

K20

G23

SPISEL/LSRCID[1]

H22

FEC Management

H23

FEC_MDC

FEC_MDIO

O

OV_DD

—

L20

IO

FEC1/GTM/GPIO

AB20

AC21

Y17

FEC1_COL/GTM1_TIN[1]/GPIO[16]

FEC1_CRS/GTM1_TGATE1_B/GPIO[17]

FEC1_RX_CLK/GPIO[18]

IO

OV_DD

—

FEC1_RX_DV/GTM1_TIN[2]/GPIO[19]

FEC1_RX_ER/GTM1_TGATE[2]_B/GPIO[20]

FEC1_RXD0/GPIO[21]

Y18

AB19

AC20

AC19

AC18

AB17

Y15

FEC1_RXD1/GTM1_TIN[3]/GPIO[22]

FEC1_RXD2/GTM1_TGATE[3]_B/GPIO[23]

FEC1_RXD3/GPIO[24]

FEC1_TX_CLK/GTM1_TIN4/GPIO[25]

FEC1_TX_EN/GTM1_TGATE[4]_B/GPIO[26]

Y16

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Package and Pin Listings

Table 46. MPC8306S Pinout Listing (continued)

Signal

Package Pin Number

Pin Type

Power Supply

Notes

FEC1_TX_ER/GTM1_TOUT[4]_B/GPIO[27]

FEC1_TXD0/GTM1_TOUT[1]_B/GPIO[28]

FEC1_TXD1/GTM1_TOUT[2]_B/GPIO[29]

FEC1_TXD2/GTM1_TOUT[3]_B/GPIO[30]

FEC1_TXD3/GPIO[31]

AC17

AB16

AC16

AC15

AB14

FEC2/GPIO

AC14

AB13

Y14

IO

OV_DD

—

FEC2_COL/GPIO[32]

FEC2_CRS/GPIO[33]

FEC2_RX_CLK/GPIO[34]

FEC2_RX_DV/GPIO[35]

FEC2_RX_ER/GPIO[36]

FEC2_RXD0/GPIO[37]

FEC2_RXD1/GPIO[38]

FEC2_RXD2/GPIO[39]

FEC2_RXD3/GPIO[40]

FEC2_TX_CLK/GPIO[41]

FEC2_TX_EN/GPIO[42]

FEC2_TX_ER/GPIO[43]

FEC2_TXD0/GPIO[44]

FEC2_TXD1/GPIO[45]

FEC2_TXD2/GPIO[46]

FEC2_TXD3/GPIO[47]

IO

OV_DD

—

AC13

Y13

AC12

AB11

AC11

AB10

Y12

AC10

AC9

AC8

Y11

AC7

Y10

FEC3/GPIO

J23

FEC3_COL/GPIO[48]

IO

OV_DD

—

FEC3_CRS/GPIO[49]

K23

FEC3_RX_CLK/GPIO[50]

M20

FEC3_RX_DV/FEC1_TMR_TX_ESFD/GPIO[51]

FEC3_RX_ER/FEC1_TMR_RX_ESFD/GPIO[52]

FEC3_RXD0/FEC2_TMR_TX_ESFD/GPIO[53]

FEC3_RXD1/FEC2_TMR_RX_ESFD/GPIO[54]

FEC3_RXD2/TSEC_TMR_TRIG1/GPIO[55]

FEC3_RXD3/TSEC_TMR_TRIG2/GPIO[56]

FEC3_TX_CLK/TSEC_TMR_CLK/GPIO[57]

FEC3_TX_EN/TSEC_TMR_GCLK/GPIO[58]

FEC3_TX_ER/TSEC_TMR_PP1/GPIO[59]

K22

L22

L23

M23

N22

N23

N20

P20

P22

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

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Package and Pin Listings

Table 46. MPC8306S Pinout Listing (continued)

Signal

Package Pin Number

Pin Type

Power Supply

Notes

FEC3_TXD0/TSEC_TMR_PP2/GPIO[60]

FEC3_TXD1/TSEC_TMR_PP3/GPIO[61]

FEC3_TXD2/TSEC_TMR_ALARM1/GPIO[62]

FEC3_TXD3/TSEC_TMR_ALARM2/GPIO[63]

R20

IO

OV_DD

—

T22

T23

T20

HDLC/GPIO/TDM

U23

HDLC1_RXCLK/TDM1_RCK/GPIO[1]

HDLC1_RXD/TDM1_RD/GPIO[3]

IO

OV_DD

—

U22

HDLC1_TXCLK/GPIO[0]/TDM1_TCK/

QE_BRG[5]

AC22

HDLC1_TXD/GPIO[2]/TDM1_TD/

CFG_RESET_SOURCE[0]

W18

IO

OV_DD

—

HDLC1_CD_B/GPIO[4]/TDM1_TFS

HDLC1_CTS_B/GPIO[5]/TDM1_RFS

W19

Y20

IO

OV_DD

—

HDLC1_RTS_B/GPIO[6]/TDM1_STROBE_B/

CFG_RESET_SOURCE[1]

AB22

HDLC2_TXCLK/GPIO[16]/TDM2_TCK/

QE_BRG[7]

AB23

AA23

W20

IO

OV_DD

—

HDLC2_RXCLK/GPIO[17]/TDM2_RCK/

QE_BRG[8]

HDLC2_TXD/GPIO[18]/TDM2_TD/

CFG_RESET_SOURCE[2]

HDLC2_RXD/GPIO[19]/TDM2_RD

HDLC2_CD_B/GPIO[20]/TDM2_TFS

HDLC2_CTS_B/GPIO[21]/TDM2_RFS

Y23

Y22

W23

W22

IO

OV_DD

—

HDLC2_RTS_B/GPIO[22]/TDM2_STROBE_B/

CFG_RESET_SOURCE[3]

Power

L16

AV_DD1

AV_DD2

AV_DD3

GV_DD

—

M16

N8

G5, H5, J5, K5, L5, M5,

N5, P5, R5, T5, U5

OV_DD

E7,E8,E9,E10,E11,E12,

E13,E14, E15,

—

E16,E17,G19,H19,J19,K

19,L19,M19,

N19,P19,R19,T19,U19,

W7,W8,W9, W10,W11,

W12,W13, W14,W15,

W16, W17

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Package and Pin Listings

Table 46. MPC8306S Pinout Listing (continued)

Signal

Package Pin Number

Pin Type

Power Supply

Notes

V_DD

H8,H9,H10,H11,H12,H1

3,H14,H15,H16,J8,J16,K

8,K16,M8,N16,P8,P16,R

8,R16,T8,T9,T10,T11,T1

2,T13,T14,T15,T16

—

VSS

A1,B4,B6,B9,B12,B15,B

18,B21,C22,D2,D5,D18,

D20,F2,F22,J2,J9,J10,J

11,J12,J13,J14,J15,J22,

K4,K9,K10,K11,K12,K13

,K14,K15,L9,L10,L11,L1

2,L13,L14,L15,M2,M9,M

10,M11,M12,M13,M14,M

15,M22,N9,N10,N11,N1

2,N13,N14,N15,P9,P10,

P11,P12,P13,P14,P15,R

2,R9,R10,R11,R12,R13,

R14,R15,R22,T4,V2,V19

,V22,W4,Y19,AA2,AA22,

AB4,AB6,AB9,AB12,AB1

5,AB18,AB21,AC1,AC23

—

NC

A23

—

Notes

1. This pin is an open drain signal. A weak pull-up resistor (1 kΩ) should be placed on this pin to OV_DD

2. This pin is an open drain signal. A weak pull-up resistor (2-10 kΩ) should be placed on this pin to OV_DD

3. This pin has weak pull-up that is always enabled.

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

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53

Clocking

20 Clocking

The following figure Figure 39 shows the internal distribution of clocks within the MPC8306S.

Figure 38. MPC8306S Clock Subsystem

e300c3 core

MPC8306S

core_clk

Core PLL

to DDR

csb_clk

memory

controller

DDR

Clock

Divider

MEMC_MCK

DDR

Memory

Device

/2

ddr_clk

Clock

Unit

lbc_clk

System

PLL

/n

SYS_CLK_IN

Local Bus

Memory

Device

LBC

Clock

Divider

LCLK[0:1]

to local bus

csb_clk to rest

of the device

qe_clk

QE Block

CLK Gen

QE_CLK_IN

QE PLL

Figure 39. MPC8306S Clock Subsystem

The primary clock source for MPC8306S is SYS_CLK_IN.

Figure 40.

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Clocking

20.1 System Clock Domains

As shown in Figure 38, the primary clock input (frequency) is multiplied up by the system phase-locked

loop (PLL) and the clock unit to create four major clock domains:

•

The coherent system bus clock (csb_clk)

The QUICC Engine clock (qe_clk)

The internal clock for the DDR controller (ddr_clk)

The internal clock for the local bus controller (lbc_clk)

The csb_clk frequency is derived from the following equation:

csb_clk = SYS_CLK_IN × SPMF

Eqn. 1

The csb_clk serves as the clock input to the e300 core. A second PLL inside the core multiplies up the

csb_clk frequency to create the internal clock for the core (core_clk). The system and core PLL multipliers

are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL) which is

loaded at power-on reset or by one of the hard-coded reset options. For more information, see the Reset

Configuration chapter in the MPC8306S PowerQUICC II Pro Integrated Communications Processor

Family Reference Manual.

The qe_clk frequency is determined by the QUICC Engine PLL multiplication factor (RCWL[CEPMF])

and the QUICC Engine PLL division factor (RCWL[CEPDF]) as the following equation:

qe_clk = (QE_CLK_IN × CEPMF)  (1 + CEPDF)

Eqn. 2

Eqn. 3

For more information, see the QUICC Engine PLL Multiplication Factor section and the “QUICC Engine

PLL Division Factor” section in the MPC8306S PowerQUICC II Pro Integrated Communications

Processor Family Reference Manual for more information.

The DDR SDRAM memory controller operates with a frequency equal to twice the frequency of csb_clk.

Note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider

(2) to create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate

is the same frequency as ddr_clk.

The local bus memory controller operates with a frequency equal to the frequency of csb_clk. Note that

lbc_clk is not the external local bus frequency; lbc_clk passes through the LBC clock divider to create the

external local bus clock outputs (LCLK). The LBC clock divider ratio is controlled by LCRR[CLKDIV].

For more information, see the LBC Bus Clock and Clock Ratios section in the MPC8306S PowerQUICC

II Pro Integrated Communications Processor Family Reference Manual.

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Clocking

In addition, some of the internal units may be required to be shut off or operate at lower frequency than

the csb_clk frequency. These units have a default clock ratio that can be configured by a memory mapped

register after the device comes out of reset.

The following table specifies which units have a configurable clock frequency. For detailed description,

refer to the “System Clock Control Register (SCCR)” section in the MPC8306S PowerQUICC II Pro

Integrated Communications Processor Family Reference Manual.

Table 47. Configurable Clock Units

Unit

Default Frequency

Options

I2C,SDHC, USB, DMA Complex

csb_clk

Off, csb_clk, csb_clk/2, csb_clk/3

NOTE

Setting the clock ratio of these units must be performed prior to any access

to them.

The following table provides the maximum operating frequencies for the MPC8306S MAPBGA under

recommended operating conditions (see Table 2).

Table 48. Operating Frequencies for MAPBGA

Characteristic¹

e300 core frequency (core_clk)

Max Operating Frequency

Unit

266

133

233

167

66

MHz

Coherent system bus frequency (csb_clk)

QUICC Engine frequency (qe_clk)

DDR2 memory bus frequency (MCLK)²

Local bus frequency (LCLKn)³

Notes:

1. The SYS_CLK_IN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting

csb_clk, MCLK, LCLK, and core_clk frequencies do not exceed their respective maximum or minimum operating

frequencies.

2. The DDR2 data rate is 2× the DDR2 memory bus frequency.

3. The local bus frequency is 1/2, 1/4, or 1/8 of the lb_clk frequency (depending on LCRR[CLKDIV]) which is in turn 1× or 2×

the csb_clk frequency (depending on RCWL[LBCM]).

20.2 System PLL Configuration

The system PLL is controlled by the RCWL[SPMF] parameter. Table 49 shows the multiplication factor

encodings for the system PLL.

NOTE

System PLL VCO frequency = 2 × (CSB frequency) × (System PLL VCO

divider). The VCO divider needs to be set properly so that the System PLL

VCO frequency is in the range of 450–750 MHz.

As described in Section 20, “Clocking,” the LBCM, DDRCM, and SPMF parameters in the reset

configuration word low select the ratio between the primary clock input (SYS_CLK_IN) and the internal

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Freescale Semiconductor

Clocking

Table 49. System PLL Multiplication Factors

RCWL[SPMF]

System PLL Multiplication Factor

0000

0001

Reserved

× 2

0010

0011

× 3

0100

× 4

0101

× 5

0110

× 6

0111–1111

Reserved

coherent system bus clock (csb_clk). The following table shows the expected frequency values for the CSB

frequency for selected csb_clk to SYS_CLK_IN ratios.

Table 50. CSB Frequency Options

SYS_CLK_IN(MHz)

SPMF

csb_clk : sys_clk_in Ratio

25

33.33

66.67

csb_clk Frequency (MHz)

0010

0011

0100

0101

0110

2:1

3:1

4:1

5:1

6:1

133

167

125

20.3 Core PLL Configuration

RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300

core clock (core_clk). The following table shows the encodings for RCWL[COREPLL]. COREPLL

values not listed, and should be considered reserved.

Table 51. e300 Core PLL Configuration

RCWL[COREPLL]

core_clk : csb_clk Ratio

VCO Divider

0-1

2-5

6

nn

0000

n

PLL bypassed

(PLL off, csb_clk clocks core directly) (PLL off, csb_clk clocks core directly)

00

01

10

11

0001

0

1:1

2

4

8

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Clocking

Table 51. e300 Core PLL Configuration (continued)

RCWL[COREPLL]

2-5

core_clk : csb_clk Ratio

VCO Divider

0-1

6

00

01

10

11

00

01

10

11

00

01

10

11

00

01

10

11

0001

0010

0011

1

0

1

0

1.5:1

2:1

 2

 4

 8

 2

 4

 8

 2

 4

 8

 2

 4

 8

2:1

2.5:1

3:1

NOTE

Core VCO frequency = core frequency  VCO divider. The VCO divider

(RCWL[COREPLL[0:1]]), must be set properly so that the core VCO

frequency is in the range of 400–800 MHz.

20.4 QUICC Engine PLL Configuration

The QUICC Engine PLL is controlled by the RCWL[CEPMF] and RCWL[CEPDF] parameters. The

following table shows the multiplication factor encodings for the QUICC Engine PLL.

Table 52. QUICC Engine PLL Multiplication Factors

QUICC Engine PLL Multiplication Factor = RCWL[CEPMF]/

RCWL[CEPMF]

RCWL[CEPDF]

(1 + RCWL[CEPDF)

00000–00001

00010

0

Reserved

 2

00011

 3

00100

 4

00101

 5

00110

 6

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Clocking

Table 52. QUICC Engine PLL Multiplication Factors (continued)

QUICC Engine PLL Multiplication Factor = RCWL[CEPMF]/

RCWL[CEPMF]

RCWL[CEPDF]

(1 + RCWL[CEPDF)

00111

01000

0

 7

 8

01001–11111

Reserved

The RCWL[CEVCOD] denotes the QUICC Engine PLL VCO internal frequency as shown in the

following table.

Table 53. QUICC Engine PLL VCO Divider

RCWL[CEVCOD]

VCO Divider

00

01

10

11

2

4

8

Reserved

NOTE

The VCO divider (RCWL[CEVCOD]) must be set properly so that the

QUICC Engine VCO frequency is in the range of 300–600 MHz. The

QUICC Engine frequency is not restricted by the CSB and core frequencies.

The CSB, core, and QUICC Engine frequencies should be selected

according to the performance requirements.

The QUICC Engine VCO frequency is derived from the following

equations:

qe_clk = (primary clock input × CEPMF)  (1 + CEPDF)

QUICC Engine VCO Frequency = qe_clk × VCO divider × (1 + CEPDF)

20.5 Suggested PLL Configurations

To simplify the PLL configurations, the MPC8306S might be separated into two clock domains. The first

domain contains the CSB PLL and the core PLL. The core PLL is connected serially to the CSB PLL, and

has the csb_clk as its input clock. The second clock domain has the QUICC Engine PLL. The clock

domains are independent, and each of their PLLs is configured separately.

The following table shows suggested PLL configurations for 33 and 66 MHz input clocks.

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59

Clocking

Table 54. Suggested PLL Configurations

QUICC

Engine

Frequency

(MHz)

Input Clock

Frequency

(MHz)

CSB

Frequency

(MHz)

Core

Frequency

(MHz)

Core

PLL

Conf No.

SPMF

CEPMF

CEDF

1

2

3

4

5

0100

0010

0100

0101

0010

0000100

0000101

0111

1001

0111

0

1

0

1

33.33

66.67

33.33

25

133.33

125

266.66

333.33

312.5

233

225

233

66.67

133.33

333.33

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Thermal

21 Thermal

This section describes the thermal specifications of the MPC8306S.

21.1 Thermal Characteristics

The following table provides the package thermal characteristics for the 369, 19  19 mm MAPBGA of

the MPC8306S.

Table 55. Package Thermal Characteristics for MAPBGA

Characteristic

Board type

Symbol

Value

Unit

Notes

Junction-to-ambient natural convection

Junction-to-ambient (@200 ft/min)

Junction-to-board

Single-layer board (1s)

Four-layer board (2s2p)

Single-layer board (1s)

Four-layer board (2s2p)

—

R_JA

R_JMA

R_JB

R_JC

_JT

39

24

32

21

14

9

°C/W

1, 2

1, 2, 3

1, 3

4

Junction-to-case

—

5

Junction-to-package top

Notes:

Natural convection

2

6

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal

resistance.

2. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.

3. Per JEDEC JESD51-6 with the board horizontal.

4. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method

1012.1).

6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature

per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

21.1.1 Thermal Management Information

For the following sections, P = (V  I ) + P , where P is the power dissipation of the I/O

D

DD

I/O

drivers.

21.1.2 Estimation of Junction Temperature with Junction-to-Ambient

Thermal Resistance

An estimation of the chip junction temperature, T , can be obtained from the equation:

J

T = T + (R J  P )

Eqn. 1

J

A

D



where:

T = junction temperature (C)

J

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Thermal

T = ambient temperature for the package (C)

A

R

= junction-to-ambient thermal resistance (C/W)

JA

P = power dissipation in the package (W)

D

The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy

estimation of thermal performance. As a general statement, the value obtained on a single layer board is

appropriate for a tightly packed printed-circuit board. The value obtained on the board with the internal

planes is usually appropriate if the board has low power dissipation and the components are well separated.

Test cases have demonstrated that errors of a factor of two (in the quantity T – T ) are possible.

J

A

21.1.3 Estimation of Junction Temperature with Junction-to-Board

Thermal Resistance

The thermal performance of a device cannot be adequately predicted from the junction-to-ambient thermal

resistance. The thermal performance of any component is strongly dependent on the power dissipation of

surrounding components. In addition, the ambient temperature varies widely within the application. For

many natural convection and especially closed box applications, the board temperature at the perimeter

(edge) of the package is approximately the same as the local air temperature near the device. Specifying

the local ambient conditions explicitly as the board temperature provides a more precise description of the

local ambient conditions that determine the temperature of the device.

At a known board temperature, the junction temperature is estimated using the following equation:

T = T + (R J  P )

Eqn. 2

J

B

D



where:

T = junction temperature (C)

J

T = board temperature at the package perimeter (C)

B

R

= junction-to-board thermal resistance (C/W) per JESD51-8

JB

P = power dissipation in package (W)

D

When the heat loss from the package case to the air can be ignored, acceptable predictions of junction

temperature can be made. The application board should be similar to the thermal test condition: the

component is soldered to a board with internal planes.

21.1.4 Experimental Determination of Junction Temperature

To determine the junction temperature of the device in the application after prototypes are available, the

thermal characterization parameter ( ) can be used to determine the junction temperature with a

JT

measurement of the temperature at the top center of the package case using the following equation:

T = T + (_JT P )

Eqn. 3

J

T

D

where:

T = junction temperature (C)

J

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Freescale Semiconductor

Thermal

T = thermocouple temperature on top of package (C)

T



= thermal characterization parameter (C/W)

JT

P = power dissipation in package (W)

D

The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T

thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so

that the thermocouple junction rests on the package. A small amount of epoxy is placed over the

thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire

is placed flat against the package case to avoid measurement errors caused by cooling effects of the

thermocouple wire.

21.1.5 Heat Sinks and Junction-to-Case Thermal Resistance

In some application environments, a heat sink is required to provide the necessary thermal management of

the device. When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case

thermal resistance and a case to ambient thermal resistance as shown in the following equation:

R

= R

+ R

CA

Eqn. 4

JA

JC

where:

R

= junction-to-ambient thermal resistance (C/W)

= junction-to-case thermal resistance (C/W)

= case-to-ambient thermal resistance (C/W)

JA

JC

CA

R_is device related and cannot be influenced by the user. The user controls the thermal environment to

JC

change the case-to-ambient thermal resistance, R_. For instance, the user can change the size of the heat

CA

sink, the air flow around the device, the interface material, the mounting arrangement on printed-circuit

board, or change the thermal dissipation on the printed-circuit board surrounding the device.

To illustrate the thermal performance of the devices with heat sinks, the thermal performance has been

simulated with a few commercially available heat sinks. The heat sink choice is determined by the

application environment (temperature, air flow, adjacent component power dissipation) and the physical

space available. Because there is not a standard application environment, a standard heat sink is not

required.

Accurate thermal design requires thermal modeling of the application environment using computational

fluid dynamics software which can model both the conduction cooling and the convection cooling of the

air moving through the application. Simplified thermal models of the packages can be assembled using the

junction-to-case and junction-to-board thermal resistances listed in the thermal resistance table. More

detailed thermal models can be made available on request.

21.2 Heat Sink Attachment

When attaching heat sinks to these devices, an interface material is required. The best method is to use

thermal grease and a spring clip. The spring clip should connect to the printed-circuit board, either to the

board itself, to hooks soldered to the board, or to a plastic stiffener. Avoid attachment forces which would

lift the edge of the package or peel the package from the board. Such peeling forces reduce the solder joint

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63

System Design Information

lifetime of the package. Recommended maximum force on the top of the package is 10 lb (4.5 kg) force.

If an adhesive attachment is planned, the adhesive should be intended for attachment to painted or plastic

surfaces and its performance verified under the application requirements.

21.2.1 Experimental Determination of the Junction Temperature with a

Heat Sink

When heat sink is used, the junction temperature is determined from a thermocouple inserted at the

interface between the case of the package and the interface material. A clearance slot or hole is normally

required in the heat sink. Minimizing the size of the clearance is important to minimize the change in

thermal performance caused by removing part of the thermal interface to the heat sink. Because of the

experimental difficulties with this technique, many engineers measure the heat sink temperature and then

back calculate the case temperature using a separate measurement of the thermal resistance of the

interface.

From this case temperature, the junction temperature is determined from the junction-to-case thermal

resistance using the following equation:

T = T + (R

 P )

Eqn. 5

J

C

JC

D

where:

T = case temperature of the package (C)

C

R

= junction-to-case thermal resistance (C/W)

JC

P = power dissipation (W)

D

22 System Design Information

This section provides electrical and thermal design recommendations for successful application of the

MPC8306S.

22.1 System Clocking

The MPC8306S includes three PLLs.

•

The system PLL (AV

) generates the system clock from the externally supplied SYS_CLK_IN

DD2

input. The frequency ratio between the system and SYS_CLK_IN is selected using the system PLL

ratio configuration bits as described in Section 20.2, “System PLL Configuration.”

The e300 core PLL (AV

ratio between the e300 core clock and the system clock is selected using the e300 PLL ratio

configuration bits as described in Section 20.3, “Core PLL Configuration.”

) generates the core clock as a slave to the system clock. The frequency

DD3

The QUICC Engine PLL (AV

) which uses the same reference as the system PLL. The QUICC

DD1

Engine block generates or uses external sources for all required serial interface clocks.

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System Design Information

22.2 PLL Power Supply Filtering

Each of the PLLs listed above is provided with power through independent power supply pins. The voltage

level at each AV n pin should always be equivalent to V , and preferably these voltages are derived

DD

directly from V through a low frequency filter scheme such as the following.

DD

There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to

provide independent filter circuits as illustrated in Figure 41, one to each of the three AV pins. By

DD

providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the

other is reduced.

This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz

range. It should be built with surface mount capacitors with minimum effective series inductance (ESL).

Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook

of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a

single large value capacitor.

Each circuit should be placed as close as possible to the specific AV pin being supplied to minimize

DD

noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AV

pin, which is on the periphery of package, without the inductance of vias.

DD

The following figure shows the PLL power supply filter circuit.

10

V_DD

AV_DD

2.2 µF

Low ESL Surface Mount Capacitors (<0.5 nH)

GND

Figure 41. PLL Power Supply Filter Circuit

22.3 Decoupling Recommendations

Due to large address and data buses, and high operating frequencies, the MPC8306S can generate transient

power surges and high frequency noise in its power supply, especially while driving large capacitive loads.

This noise must be prevented from reaching other components in the MPC8306S system, and MPC8306S

itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system

designer place at least one decoupling capacitor at each V , OV , and GV pins of the MPC8306S.

DD

These decoupling capacitors should receive their power from separate V , OV , GV , and GND

DD

power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed directly

under the device using a standard escape pattern. Others may surround the part.

These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)

capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.

In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,

feeding the V , OV , and GV planes, to enable quick recharging of the smaller chip capacitors.

DD

These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick

response time necessary. They should also be connected to the power and ground planes through two vias

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System Design Information

to minimize inductance. Suggested bulk capacitors—100 to 330 µF (AVX TPS tantalum or Sanyo

OSCON).

22.4 Output Buffer DC Impedance

2

For all buses, the driver is a push-pull single-ended driver type (open drain for I C).

To measure Z for the single-ended drivers, an external resistor is connected from the chip pad to OV

0

DD

or GND. Then, the value of each resistor is varied until the pad voltage is OV /2 (see Figure 42). The

DD

output impedance is the average of two components, the resistances of the pull-up and pull-down devices.

When data is held high, SW1 is closed (SW2 is open) and R is trimmed until the voltage at the pad equals

P

OV /2. R then becomes the resistance of the pull-up devices. R and R are designed to be close to each

DD

P

N

other in value. Then, Z = (R + R )/2.

0

P

N

OV_DD

R_N

SW2

SW1

Pad

Data

R_P

OGND

Figure 42. Driver Impedance Measurement

The value of this resistance and the strength of the driver’s current source can be found by making two

measurements. First, the output voltage is measured while driving logic 1 without an external differential

termination resistor. The measured voltage is V = R

 I

. Second, the output voltage is measured

1

source

while driving logic 1 with an external precision differential termination resistor of value R . The

term

measured voltage is V = (1/(1/R + 1/R ))  I

. Solving for the output impedance gives

2

1

2

source

R

= R

 (V /V – 1). The drive current is then I

= V /R

.

source

term

1

2

source

1

source

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Ordering Information

The following table summarizes the signal impedance targets. The driver impedance is targeted at

minimum V , nominal OV , 105C.

DD

Table 56. Impedance Characteristics

Local Bus, Ethernet, DUART, Control,

Configuration and Power Management

Impedance

DDR DRAM

Symbol

Unit

R

42 Target

NA

20 Target

NA

Z₀

Ω

N

P

Differential

Z_DIFF

Note: Nominal supply voltages. See Table 1, T_j= 105C.

22.5 Configuration Pin Multiplexing

The MPC8306S provides the user with power-on configuration options which can be set through the use

of external pull-up or pull-down resistors of 4.7 k on certain output pins (Refer to the “Reset, Clocking

and Initialization” of MPC8306S PowerQUICC II Pro Integrated Communications Processor Family

Reference Manual). These pins are generally used as output only pins in normal operation.

While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins

while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled

and the I/O circuit takes on its normal function. Careful board layout with stubless connections to these

pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should minimize

the disruption of signal quality or speed for output pins thus configured.

23 Ordering Information

This section presents ordering information for the devices discussed in this document, and it shows an

example of how the parts are marked. Ordering information for the devices fully covered by this document

is provided in Section 23.1, “Part Numbers Fully Addressed by This Document.”

23.1 Part Numbers Fully Addressed by This Document

The following table provides the Freescale part numbering nomenclature for the MPC8306S family. Note

that the individual part numbers correspond to a maximum processor core frequency. For available

frequencies, contact your local Freescale sales office. In addition to the maximum processor core

frequency, the part numbering scheme also includes the maximum effective DDR memory speed and

QUICC Engine bus frequency. Each part number also contains a revision code which refers to the die mask

revision number.

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Ordering Information

Table 57. Part Numbering Nomenclature

MPC nnnn

VM

AF

D

C

A

C

QUICC

Engine

Frequency

Product

Code

Part

Identifier

Temperature

Range¹

e300 Core

DDR2

Frequency

Revision

Level

Package²

Frequency³

MPC

8306S

Blank = 0 to

105C

C = –40 to

VM = Pb-free

AB = 133MHz D = 266 MHz C = 233 MHz Contact local

AC = 200 MHz F = 333 MHz

AD = 266 MHz

Freescale

sales office

105C

AF = 333 MHz

Notes:

1. Contact local Freescale office on availability of parts with C temperature range.

2. See Section 19, “Package and Pin Listings,” for more information on available package types.

3. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this

specification support all core frequencies. Additionally, parts addressed by Part Number Specifications may support other

maximum core frequencies.

23.2 Part Marking

Parts are marked as in the example shown in the following figure.

MPCnnnnetppaaar

core/platform MHZ

ATWLYYWW

CCCCC

*MMMMM

YWWLAZ

MAPBGA

Notes:

ATWLYYWW is the traceability code.

CCCCC is the country code.

MMMMM is the mask number.

YWWLAZ is the assembly traceability code.

Figure 43. Freescale Part Marking for MAPBGA Devices

The following table shows the SVR Settings.

Table 58. SVR Settings

Device

MPC8306S

Note: PVR = 0x8085_0020

Package

MAPBGA

SVR (Rev 1.0)

0x8110_0210

SVR (Rev 1.1)

0x8110_0211

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Document Revision History

24 Document Revision History

The following table provides a revision history for this document.

Table 59. Document Revision History

Rev.

No.

Date

Substantive Change(s)

1

09/2011

• Added Power numbers for core frequency of 333 MHz in Table 5.

• Updated QUICC Engine frequency in Table 5.

• Added SPISEL_BOOT in MPC8306 Pin out Listing Table 46.

• Corrected SPISEL Pin Type in Table 46

• Updated QUICC Engine frequency from 200 MHz to 233 MHz in Table 48.

• Added new PLL configurations as per new core frequency in Table 54.

• Updated CEPMF and CEDF as per new QE frequency in Table 54.

• Added AF to indicate 333 MHz in Table 57

• Updated QE Frequency to 233 MHz in Table 57.

0

03/2011 Initial Release

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

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Document Number: MPC8306SEC

Rev. 1

09/2011


型号：	MPC8306SEC
厂家：	Freescale
描述：	PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications 的PowerQUICC II Pro的集成通信处理器系列硬件规格通信
文件：	总70页 (文件大小：453K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MPC8306SEC [FREESCALE]

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