MPC8308VMADDA_技术文档

Document Number: MPC8308EC

Freescale Semiconductor

Rev. 4, 12/2014

MPC8308 PowerQUICC II Pro

Processor Hardware Specification

Contents

This document provides an overview of the MPC8308

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

features and its hardware specifications, including a block

diagram showing the major functional components. The

MPC8308 is a cost-effective, low-power, highly integrated

host processor. The MPC8308 extends the PowerQUICC

family, adding higher CPU performance, additional

functionality, and faster interfaces while addressing the

requirements related to time-to-market, price, power

consumption, and package size.

2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 2

3. Power characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 6

4. Clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

5. RESET initialization . . . . . . . . . . . . . . . . . . . . . . . . . . 8

6. DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

8. Ethernet: Three-Speed Ethernet, MII management . 15

9. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

10. High-Speed Serial interfaces (HSSI) . . . . . . . . . . . . 25

11. PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

12. Enhanced Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . 41

13. Enhanced Secure Digital Host Controller (eSDHC) . 44

14. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

15. I²C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

16. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

17. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

18. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

19. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

20. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 59

21. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

22. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

23. System Design Information . . . . . . . . . . . . . . . . . . . 77

24. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 80

25. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Overview

1 Overview

This figure shows the major functional units within the MPC8308. The e300 core in the MPC8308, with

its 16 Kbytes of instruction and 16 Kbytes of data cache, implements the Power Architecture user

instruction set architecture and provides hardware and software debugging support. In addition, the

MPC8308 offers a PCI Express controller, two three-speed 10, 100, 1000 Mbps Ethernet controllers

(eTSEC), a DDR2 SDRAM memory controller, a SerDes block, an enhanced local bus controller (eLBC),

an integrated programmable interrupt controller (IPIC), a general purpose DMA controller, two I²C

controllers, dual UART (DUART), GPIOs, USB, general purpose timers, and an SPI controller. The high

level of integration in the MPC8308 helps simplify board design and offers significant bandwidth and

performance.

This figure shows a block diagram of the device.

e300c3 Core with

Power Management

16-Kbyte

D-Cache

16-Kbyte

I-Cache

DUART

I2C

Timers

GPIO, SPI

Enhanced

Local Bus

Interrupt

DDR2

Controller

FPU

Controller

DMA

USB 2.0 HS

Host/Device/OTG

PCI

Express

eTSEC2

Enhanced

Secure

Digital Host

Controller

eTSEC1

RGMII,MII

x1

RGMII,MII

ULPI

Figure 1. MPC8308 Block Diagram

2 Electrical Characteristics

This section provides the AC and DC electrical specifications and thermal characteristics for the

MPC8308. The device is currently targeted to these specifications. Some of these specifications are

independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer

design specifications.

2.1

Overall DC Electrical Characteristics

This section covers the ratings, conditions, and other characteristics.

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

2

Electrical Characteristics

2.1.1

Absolute maximum ratings

This table lists the absolute maximum ratings.

1

Table 1. Absolute maximum ratings

Characteristic

Symbol

Max Value

Unit

Notes

Core supply voltage

PLL supply voltage

V_DD

AV_DD1,AV_DD2

GV_DD

–0.3 to 1.26

–0.3 to 1.9

–0.3 to 3.6

V

—

7

DDR2 DRAM I/O voltage

Local bus, DUART, system control and power management,

eSDHC, I²C, USB, Interrupt, Ethernet management, SPI,

Miscellaneous and JTAG I/O voltage

NV_DD

SerDes PHY

XCOREV_DD

XPADV_DD

SDAV_DD

,

–0.3 to 1.26

V

—

,

eTSEC I/O Voltage

LV_DD1,LV_DD2

–0.3 to 2.75 or

–0.3 to 3.6

6, 8

Input voltage

DDR2 DRAM signals

DDR2 DRAM reference

eTSEC

MV_IN

MV_REF

LVIN

–0.3 to (GV_DD+ 0.3)

–0.3 to (LV_DD+ 0.3)

–0.3 to (NV_DD+ 0.3)

V

2, 5

4, 5,8

3, 5,7

Local bus, DUART, system control and power

management, eSDHC, I²C, Interrupt,

Ethernet management, SPI, Miscellaneous

and JTAG I/O voltage

OV_IN

Storage temperature range

T_STG

–55 to 150

C

—

Notes:

1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and

functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause

permanent damage to the device.

2. Caution: MV_INmust not exceed GV_DDby more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

3. Caution: OV_INmust not exceed NV_DDby more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

4. Caution: LV_INmust not exceed LV_DDby more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

5. (M, L, O)V_INand MV_REFmay overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2

6. The max value of supply voltage should be selected based on the RGMII mode. The lower range applies to RGMII mode.

7. NV_DDhere refers to NV_DDA, NV_DDB,NV_DDG, NV_DDH, NV_DDJ, NV_{DDP_K}from the ball map.

8. LV_DD1here refers to NV_DDCand LV_DD2refers to NV_DDFfrom the ball map

2.1.2

Power supply voltage specification

This table provides the recommended operating conditions for the device. Note that the values in this table

are the recommended and tested operating conditions. Proper device operation outside of these conditions

is not guaranteed.

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

3

Electrical Characteristics

Table 2. Recommended operating conditions

Characteristic

Symbol

Recommended Value¹

Unit

SerDes internal digital power

SerDes I/O digital power

XCOREV_DD

XCOREV_SS

XPADV_DD

SDAV_DD

SDAV_SS

XPADV_SS

V_DD

1.0 V 50 mV

0.0

V

1.0 V 50 mV

0

SerDes analog power for PLL

SerDes I/O digital power

0

Core supply voltage

1.0 V 50 mV

1.8 V 100 mV

GVDD/2 (0.49  GV_DDto

Analog supply for e300 core APLL²

Analog supply for system APLL²

DDR2 DRAM I/O voltage

AV_DD1

AV_DD2

GV_DD

Differential reference voltage for DDR controller

MV_REF

0.51  GV_DD

)

Standard I/O voltage (Local bus, DUART, system control and power

management, eSDHC, USB, I²C, Interrupt, Ethernet management,

SPI, Miscellaneous and JTAG I/O voltage)³

NV_DD

3.3 V 300 mV

V

eTSEC IO supply^4,5

LV_DD1, LV_DD2

2.5 V 125 mV

3.3 V 300 mV

Analog and digital ground

V_SS

0.0

V

Operating temperature range⁶

T_A/T_J

Standard = 0 to 105

C

Extended = -40 to 105

Notes:

1

GV_DD, NV_DD, AV_DD, and V_DDmust track each other and must vary in the same direction—either in the positive or negative

direction.

This voltage is the input to the filter discussed in Section 23.2, “PLL Power Supply Filtering,” and not necessarily the voltage

at the AV_DDpin, which may be reduced from V_DDby the filter.

2

3

4

5

6

NV_DDhere refers to NV_DDA, NV_DDB,NV_DDG, NV_DDH, NV_DDJand NV_{DDP_K}from the ball map.

The max value of supply voltage should be selected based on the RGMII mode. The lower range applies to RGMII mode.

LV_DD1here refers to NV_DDCand LV_DD2refers to NV_DDFfrom the ball map.

Minimum temperature is specified with T_A; Maximum temperature is specified with T_J.

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

4

Freescale Semiconductor

Electrical Characteristics

This figure shows the undershoot and overshoot voltages at the interfaces of the device.

G/L/NV_DD+ 20%

G/L/NV_DD+ 5%

G/L/NV_DD

V_IH

VSS

VSS – 0.3 V

V_IL

VSS – 0.7 V

Not to Exceed 10%

1

of t_interface

Note:

1. t_interfacerefers to the clock period associated with the bus clock interface.

Figure 2. Overshoot/Undershoot Voltage for GVDD/NVDD/LVDD

2.1.3

Output driver characteristics

This table provides information on the characteristics of the output driver strengths.

Table 3. Output Drive Capability

Driver Type

Output Impedance ()

Supply Voltage

Local bus interface utilities signals

DDR2 signals¹

42

18

42

NV_DD= 3.3 V

GV_DD= 1.8 V

NV_DD= 3.3 V

LV_DD= 2.5/3.3 V

DUART, system control, I²C, JTAG, eSDHC, GPIO,SPI, USB

eTSEC signals

1

Output Impedance can also be adjusted through configurable options in DDR Control Driver Register (DDRCDR).

For more information, see the MPC8308 PowerQUICC II Pro Processor Reference Manual.

2.1.4

Power sequencing

It is required to apply the core supply voltage (V ) before the I/O supply voltages (GV , LV , and

DD

NV ) and assert PORESET before the power supplies fully ramp up. The core voltage supply must rise

DD

to 90% of its nominal value before the I/O supplies reach 0.7 V; see Figure 3.

If this recommendation is not observed and I/O voltages are supplied before the core voltage, there might

be a period of time that all input and output pins are actively driven and cause contention and excessive

current. To overcome side effects of this condition, the application environment may require tuning of

external pull-up or pull-down resistors on particular signals to lesser values.

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

5

Power characteristics

The I/O power supply ramp-up slew rate should be slower than 4V/100 s, this requirement is for ESD

circuit. Note that there is no specific power down sequence requirement for the device. I/O voltage

supplies (GV , LV , and NV ) do not have any ordering requirements with respect to one another.

DD

I/O Voltage (GV_DD, LV_DD, and NV_DD

)

V

Core Voltage (V_DD

)

0.7 V

90%

t

0

PORESET

>= 32  t_{SYS_CLK_IN}

Figure 3. Power-Up sequencing example

3 Power characteristics

The estimated typical power dissipation, not including I/O supply power for the device is shown in this

table. Table 5 shows the estimated typical I/O power dissipation.

1

Table 4. MPC8308 power dissipation

Core Frequency (MHz) CSB Frequency (MHz) Typical²

Maximum ³

Unit

266

333

400

133

530

565

600

900

950

mW

1000

Note:

1

2

3

The values do not include I/O supply power but do include core (V_DD) and PLL (AV_DD1,

AV_DD2, XCOREV_DD, XPADV_DD, and SDAV_DD

Typical power is based on best process, a voltage of V_DD= 1.0 V and ambient temperature

of T_A= 25 C and an artificial smoker test.

Maximum power is estimated based on best process, a voltage of V_DD= 1.05 V, a junction

temperature of T_J= 105 C

)

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

6

Freescale Semiconductor

Clock input timing

This table describes a typical scenario where blocks with the stated percentage of utilization and

impedances consume the amount of power described.

1

Table 5. MPC8308 typical I/O power dissipation

GV_DD

(1.8 V)

NV_DD

(3.3 V)

LV_DD/

(3.3 V)

LV_DD

(2.5 V)

Interface

Parameter

Unit Comments

DDR2

R_s= 22 

R_t= 75 

250 MHz

32 bits+ECC

266 MHz

0.302

0.309

—

W

—

32 bits+ECC

Local bus I/O load = 20 pF

TSEC I/O load = 20 pF

62.5 MHz

66 MHZ

—

0.038

0.040

—

W

—

MII, 25 MHz

RGMII, 125 MHz

50 MHz

—

0.008

0.078

0.008

0.012

—

0.044

—

W

2 controllers

eSDHC IO Load = 40 pF

USB IO Load = 20 pF

Other I/O

—

60 MHz

—

0.017

—

4 Clock input timing

This section provides the clock input DC and AC electrical characteristics for the device.

4.1

DC electrical characteristics

This table provides the system clock input (SYS_CLK_IN) DC electrical specifications for the device.

Table 6. SYS_CLK_IN DC Electrical Characteristics

Parameter

Input high voltage

Condition

Symbol

Min

Max

Unit

—

V_IH

V_IL

I_IN

2.4

–0.3

—

NV_DD+ 0.3

V

Input low voltage

0.4

10

SYS_CLK_IN input current

0 V  V_IN NV_DD

A

This table provides the RTC clock input (RTC_PIT_CLOCK) DC electrical specifications for the device.

Table 7. RTC_PIT_CLOCK DC Electrical Characteristics

Parameter

Condition

Symbol

Min

Max

Unit

Input high voltage

Input low voltage

—

V_IH

V_IL

3.3 V – 400 mV

0

V

0.4

4.2

AC electrical characteristics

The primary clock source for the device is SYS_CLK_IN. This table provides the system clock input

(SYS_CLK_IN) AC timing specifications for the device.

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

7

RESET initialization

Table 8. SYS_CLK_IN AC Timing Specifications

Parameter/

Symbol

Min

Typ

Max

Unit

Notes

SYS_CLK_IN frequency

SYS_CLK_IN period

SYS_CLK_IN rise and fall time

SYS_CLK_IN duty cycle

SYS_CLK_IN jitter

f_{SYS_CLK_IN}

t_{SYS_CLK_IN}

t_KH, t_KL

24

15

0.6

40

—

66.67

41.67

1.2

MHz

ns

1, 6

—

2

ns

t_{KHK SYS_CLK_IN}

/t

—

60

%

3

—

150

ps

4, 5

Notes:

1. Caution: The system and core must not exceed their respective maximum or minimum operating frequencies.

2. Rise and fall times for SYS_CLK_IN are measured at 0.4 and 2.7 V.

3. Timing is guaranteed by design and characterization.

4. This represents the total input jitter—short term and long term—and is guaranteed by design.

5. The SYS_CLK_IN driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to

allow cascade-connected PLL-based devices to track SYS_CLK_IN drivers with the specified jitter.

6. Spread spectrum is allowed up to 1% down-spread @ 33 kHz (max rate).

Table 9. RTC_PIT_CLOCK AC Timing Specifications

Parameter/

Symbol

Min

Typ

Max

Unit

Notes

RTC_PIT_CLOCK frequency

RTC_PIT_CLOCK rise and fall time

RTC_PIT_CLOCK duty cycle

f_{RTC_PIT_CLOCK}

t_RTCH, t_RTCL

t_RTCHK/t_{RTC_PIT_CLO}

1

32768

—

3

Hz

s

%

—

1.5

45

—

55

CK

5 RESET initialization

This section describes the DC and AC electrical specifications for the reset initialization timing and

electrical requirements of the device.

5.1

RESET DC electrical characteristics

This table provides the DC electrical characteristics for the RESET pins.

Table 10. RESET Pins DC Electrical Characteristics

Characteristic

Symbol

Condition

Min

Max

Unit

Input high voltage

Input low voltage

Input current

V_IH

V_IL

—

2.0

NV_DD+ 0.3

V

—

–0.3

0.8

5

I_IN

0 V  V_IN NV_DD

I_OH= –8.0 mA

I_OL= 8.0 mA

A

V

Output high voltage

Output low voltage

V_OH

V_OL

2.4

—

0.5

0.4

V

I

= 3.2 mA

OL

—

V

OL

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

8

Freescale Semiconductor

RESET initialization

5.2

RESET AC electrical characteristics

This table provides the reset initialization AC timing specifications.

Table 11. RESET Initialization Timing Specifications

Parameter/Condition

Min

Max

Unit

Notes

Required assertion time of HRESET (input) to activate reset flow

32

—

t_{SYS_CLK_IN}

1

Required assertion time of PORESET with stable power and clock applied to

SYS_CLK_IN

—

HRESET assertion (output)

512

4

—

t_{SYS_CLK_IN}

1

Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:3]) with

respect to negation of PORESET

—

Input hold time for POR configuration signals with respect to negation of HRESET

0

—

4

ns

—

2

Time for the device to turn off POR configuration signal drivers with respect to the

assertion of HRESET

—

Time for the device to turn on POR configuration signal drivers with respect to the

negation of HRESET

1

—

ns

1, 2

Notes:

1. t_{SYS_CLK_IN}is the clock period of the input clock applied to SYS_CLK_IN.

2. POR configuration signals consists of CFG_RESET_SOURCE[0:3].

This table provides the PLL lock times.

Table 12. PLL Lock Times

Parameter/Condition

Min

Max

Unit

Note

System PLL lock time

—

100

s

—

e300 core PLL lock time

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

9

DDR2 SDRAM

6 DDR2 SDRAM

This section describes the DC and AC electrical specifications for the DDR2 SDRAM interface. Note that

DDR2 SDRAM is GV (typ) = 1.8 V.

DD

6.1

DDR2 SDRAM DC electrical characteristics

This table provides the recommended operating conditions for the DDR2 SDRAM component(s) when

GV (typ) = 1.8 V.

DD

Table 13. DDR2 SDRAM DC Electrical Characteristics for GV (typ) = 1.8 V

DD

Parameter/Condition

I/O supply voltage

Symbol

Min

Max

Unit

Note

GV_DD

MV_REF

V_TT

1.7

0.49  GV_DD

MV_REF– 0.04

MV_REF+ 0.125

–0.3

1.9

0.51  GV_DD

MV_REF+ 0.04

GV_DD+ 0.3

MV_REF– 0.125

9.9

V

1

2

I/O reference voltage

I/O termination voltage

Input high voltage

V

3

V_IH

V

—

4

Input low voltage

V_IL

V

Output leakage current

Output high current (V_OUT= 1.420 V)

Output low current (V_OUT= 0.280 V)

Notes:

I_OZ

–9.9

A

mA

I_OH

–13.4

—

I_OL

13.4

—

1. GV_DDis expected to be within 50 mV of the DRAM GV_DDat all times.

2. MV_REFis expected to be equal to 0.5  GV_DD, and to track GV_DDDC variations as measured at the receiver.

Peak-to-peak noise on MV_REFmay not exceed 2% of the DC value.

3. V_TTis not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MV_REF. This rail should track variations in the DC level of MV_REF

4. Output leakage is measured with all outputs disabled, 0 V  V_OUTGV_DD

.

This table provides the DDR2 capacitance when GV (typ) = 1.8 V.

DD

Table 14. DDR2 SDRAM Capacitance for GV (typ)=1.8 V

DD

Parameter/Condition

Symbol

Min

Max

Unit

Notes

Input/output capacitance: DQ, DQS, DQS

Delta input/output capacitance: DQ, DQS, DQS

Note:

C_IO

6

8

pF

1

C_DIO

—

0.5

1. This parameter is sampled. GV_DD= 1.8 V 0.090 V, f = 1 MHz, T_A= 25°C, V_OUT= GV_DD/2, V_OUT(peak-to-peak) = 0.2 V.

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

10

Freescale Semiconductor

DDR2 SDRAM

This table provides the current draw characteristics for MV

.

REF

Table 15. Current Draw Characteristics for MV

REF

Parameter / Condition

Symbol

Min

Max

Unit

Note

Current draw for MV_REF

Note:

I_MVREF

—

500

A

1

1. The voltage regulator for MV_REFmust be able to supply up to 500 A current.

6.2

DDR2 SDRAM AC electrical characteristics

This section provides the AC electrical characteristics for the DDR2 SDRAM interface.

6.2.1

DDR2 SDRAM input AC timing specifications

This table provides input AC timing specifications for the DDR2 SDRAM when GV (typ)=1.8 V.

DD

Table 16. DDR2 SDRAM Input AC Timing Specifications for 1.8 V Interface

At recommended operating conditions with GV_DDof 1.8 100 mV

Parameter

Symbol

Min

Max

Unit

Notes

AC input low voltage

AC input high voltage

V_IL

—

MV_REF– 0.45

—

V

—

V_IH

MV_REF+ 0.45

This table provides input AC timing specifications for the DDR2 SDRAM interface.

Table 17. DDR2 SDRAM Input AC Timing Specifications

At recommended operating conditions. with GV_DDof 1.8 100 mV

Parameter

Symbol

Min

Max

Unit

Notes

1, 2,3

Controller skew for MDQS—MDQ/MECC

t_CISKEW

–875

875

ps

266 MHz

Notes:

1. t_CISKEWrepresents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that is

captured with MDQS[n]. This should be subtracted from the total timing budget.

2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ or MECC signal is called t_DISKEW. This can

be determined by the following equation: t_DISKEW= +/–(T/4 – abs(t_CISKEW)) where T is the clock period and abs(t_CISKEW) is

the absolute value of t_CISKEW

.

3. Memory controller ODT value of 150  is recommended

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

11

DDR2 SDRAM

This figure illustrates the DDR2 input timing diagram showing the t

timing parameter.

DISKEW

MCK[n]

t_MCK

MDQS[n]

MDQ[x]/

MECC[x]

D0

D1

t_DISKEW

Figure 4. Timing Diagram for t

DISKEW

6.2.2

DDR2 SDRAM output AC timing specifications

Table 18. DDR2 SDRAM Output AC Timing Specifications

Parameter

Symbol ¹

Min

Max

Unit

Notes

MCK[n] cycle time, MCK[n]/MCK[n] crossing

ADDR/CMD output setup with respect to MCK

t_MCK

7.5

10

—

ns

2

3

t_DDKHAS

266 MHz

2.9

ns

ADDR/CMD output hold with respect to MCK

266 MHz

t_DDKHAX

t_DDKHCS

t_DDKHCX

t_DDKHMH

—

3

2.33

MCS[n] output setup with respect to MCK

266 MHz

2.5

MCS[n] output hold with respect to MCK

MCK to MDQS Skew

266 MHz

3.15

–0.6

ns

0.6

—

4

5

MDQ//MDM/MECC output setup with respect to

t_DDKHDS,

t_DDKLDS

MDQS

266 MHz

900

ps

MDQ//MDM/MECC output hold with respect to

t_DDKHDX,

t_DDKLDX

—

5

MDQS

266 MHz

1100

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

12

DDR2 SDRAM

Table 18. DDR2 SDRAM Output AC Timing Specifications (continued)

Parameter

MDQS preamble start

Symbol ¹

Min

Max

Unit

Notes

t_DDKHMP

0.75 x t_MCK

—

ns

6

MDQS epilogue end

t_DDKHME

0.4 x t_MCK

0.6 x t_MCK

6

Notes:

1. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state) (reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. Output hold time can be read as DDR timing

(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,

t_DDKHASsymbolizes DDR timing (DD) for the time t_MCKmemory clock reference (K) goes from the high (H) state until outputs

(A) are setup (S) or output valid time. Also, t_DDKLDXsymbolizes DDR timing (DD) for the time t_MCKmemory clock reference

(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.

2. All MCK/MCK referenced measurements are made from the crossing of the two signals 0.1 V.

3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.

4. Note that t_DDKHMHfollows the symbol conventions described in note 1. For example, t_DDKHMHdescribes the DDR timing (DD)

from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). t_DDKHMHcan be modified through control

of the DQSS override bits in the TIMING_CFG_2 register. This is typically set to the same delay as the clock adjust in the

CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same

adjustment value. For a description and understanding of the timing modifications enabled by use of these bits, see the

MPC8308 PowerQUICC II Pro Processor Reference Manual.

5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC

(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.

6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that t_DDKHMPfollows the

symbol conventions described in note 1.

This figure shows the DDR2 SDRAM output timing for the MCK to MDQS skew measurement

(tDDKHMH).

MCK[n]

t_MCK

t_{DDKHMHmax) = 0.6 ns}

MDQS

t_{DDKHMH(min) = –0.6 ns}

MDQS

Figure 5. Timing Diagram for t

DDKHMH

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

13

DUART

This figure shows the DDR2 SDRAM output timing diagram.

MCK[n]

t_MCK

t_{DDKHAS DDKHCS}

,t

t_{DDKHAX DDKHCX}

,t

ADDR/CMD

MDQS[n]

Write A0

t_DDKHMP

NOOP

t_DDKHMH

t_DDKHME

t_DDKHDS

t_DDKLDS

MDQ[x]/

MECC[x]

D0

D1

t_DDKLDX

t_DDKHDX

Figure 6. DDR2 SDRAM Output Timing Diagram

This figure provides the AC test load for the DDR2 bus.

GV_DD/2

Output

Z₀= 50 

R_L= 50 

Figure 7. DDR2 AC Test Load

7 DUART

This section describes the DC and AC electrical specifications for the DUART interface.

7.1

DUART DC electrical characteristics

This table provides the DC electrical characteristics for the DUART interface.

Table 19. DUART DC Electrical Characteristics

Parameter

Symbol

Min

Max

Unit

High-level input voltage

V_IH

V_IL

2.1

–0.3

NV_DD+ 0.3

V

Low-level input voltage NVDD

High-level output voltage, I_OH= –100 A

0.8

—

V_OH

NV_DD– 0.2

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

14

Ethernet: Three-Speed Ethernet, MII management

Table 19. DUART DC Electrical Characteristics (continued)

Parameter

Symbol

Min

Max

Unit

Low-level output voltage, I_OL= 100 A

V_OL

I_IN

—

0.2

5

V

Input current (0 V V_INNV_DD

)

A

7.2

DUART AC electrical specifications

This table provides the AC timing parameters for the DUART interface.

Table 20. DUART AC Timing Specifications

Parameter

Value

Unit

Notes

Minimum baud rate

Maximum baud rate

Oversample rate

Notes:

256

> 1,000,000

16

baud

—

1

2

1. Actual attainable baud rate is limited by the latency of interrupt processing.

2. The middle of a start bit is detected as the 8^thsampled 0 after the 1-to-0 transition of the start bit.

Subsequent bit values are sampled each 16^thsample.

8 Ethernet: Three-Speed Ethernet, MII management

This section provides the AC and DC electrical characteristics for three-speed, 10/100/1000, and MII

management. MPC8308 supports dual Ethernet controllers.

8.1

Enhanced Three-Speed Ethernet Controller (eTSEC)

(10/100/1000 Mbps)—MII/RGMII electrical characteristics

The electrical characteristics specified here apply to all the media independent interface (MII) and reduced

gigabit media independent interface (RGMII), signals except management data input/output (MDIO) and

management data clock (MDC). The RGMII interface is defined for 2.5 V, while the MII interface can be

operated at 3.3 V. The RGMII interface follows the Hewlett-Packard reduced pin-count interface for

Gigabit Ethernet Physical Layer Device Specification Version 1.2a (9/22/2000). The electrical

characteristics for MDIO and MDC are specified in Section 8.3, “Ethernet Management interface

electrical characteristics.”

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

15

Ethernet: Three-Speed Ethernet, MII management

8.1.1

eTSEC DC electrical characteristics

All MII and RGMII drivers and receivers comply with the DC parametric attributes specified in Table 21

and Table 22. The RGMII signals are based on a 2.5-V CMOS interface voltage as defined by JEDEC

EIA/JESD8-5.

Table 21. MII DC Electrical Characteristics

Parameter

Symbol

Conditions

Min

Max

Unit

Supply voltage 3.3 V

Output high voltage

LV_DD

V_OH

—

3.0

3.6

V

I_OH= –4.0 mA

LV_DD= Min

2.40

LV_DD+ 0.3

Output low voltage

Input high voltage

Input low voltage

Input high current

Input low current

Note:

V_OL

V_IH

V_IL

I_IH

I_OL= 4.0 mA

LV_DD= Min

VSS

2.1

0.50

LV_DD+ 0.3

0.90

V

—

–0.3

—

V

V_IN¹= LV_DD

V_IN¹= VSS

40

A

I_IL

–600

—

1. The symbol V_IN, in this case, represents the LV_INsymbol referenced in Table 1 and Table 2.

Table 22. RGMII DC Electrical Characteristics

Parameters

Symbol

Conditions

Min

Max

Unit

Supply voltage 2.5 V

Output high voltage

LV_DD

V_OH

—

2.37

2.00

2.63

V

I_OH= –1.0 mA

LV_DD= Min

LV_DD+ 0.3

Output low voltage

Input high voltage

V_OL

V_IH

I_OL= 1.0 mA

—

LV_DD= Min

VSS– 0.3

0.40

V

1.7

LV_DD+ 0.3

Input low voltage

Input high current

Input low current

Note:

V_IL

I_IH

I_IL

—

LV_DD= Min

–0.3

—

0.70

15

V

V_IN¹= LV_DD

V_IN¹= VSS

A

–15

—

1. V_IN, in this case, represents the LV_INsymbol referenced in Table 1 and Table 2.

8.2

MII and RGMII AC timing specifications

The AC timing specifications for MII and RGMII are presented in this section.

8.2.1

MII AC timing specifications

This section describes the MII transmit and receive AC timing specifications.

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

16

Freescale Semiconductor

Ethernet: Three-Speed Ethernet, MII management

8.2.1.1

MII Transmit AC timing specifications

This table provides the MII transmit AC timing specifications.

Table 23. MII Transmit AC Timing Specifications

At recommended operating conditions with LV_DDA/LV_DDB/NV_DDof 3.3 V 0.3V.

Parameter/Condition

TX_CLK clock period 10 Mbps

Symbol ¹

Min

Typ

Max

Unit

t_MTX

t_{MTXH/ MTX}

t_MTKHDX

t_MTXR

—

400

40

—

5

—

ns

%

TX_CLK clock period 100 Mbps

TX_CLK duty cycle

t

35

1

65

15

4.0

TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay

TX_CLK data clock rise V_IL(max) to V_IH(min)

TX_CLK data clock fall V_IH(min) to V_IL(max)

Note:

ns

1.0

—

t_MTXF

1. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state) (reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_MTKHDXsymbolizes MII transmit

timing (MT) for the time t_MTXclock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general,

the clock reference symbol representation is based on two to three letters representing the clock of a particular functional.

For example, the subscript of t_MTXrepresents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is

used with the appropriate letter: R (rise) or F (fall).

This figure shows the MII transmit AC timing diagram.

t_MTXR

t_MTX

TX_CLK

t_MTXF

t_MTXH

TXD[3:0]

TX_EN

TX_ER

t_MTKHDX

Figure 8. MII Transmit AC Timing Diagram

8.2.1.2

MII Receive AC timing specifications

This table provides the MII receive AC timing specifications.

Table 24. MII Receive AC Timing Specifications

At recommended operating conditions with LV_DD/NV_DDof 3.3 V 0.3V.

Parameter/Condition

Symbol ¹

Min

Typ

Max

Unit

RX_CLK clock period 10 Mbps

RX_CLK clock period 100 Mbps

RX_CLK duty cycle

t_MRX

t_MRXH/t_MRX

t_MRDVKH

—

400

40

—

65

—

ns

%

35

RXD[3:0], RX_DV, RX_ER setup time to RX_CLK

10.0

—

ns

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

17

Ethernet: Three-Speed Ethernet, MII management

Table 24. MII Receive AC Timing Specifications (continued)

At recommended operating conditions with LV_DD/NV_DDof 3.3 V 0.3V.

Parameter/Condition

Symbol ¹

Min

Typ

Max

Unit

RXD[3:0], RX_DV, RX_ER hold time to RX_CLK

RX_CLK clock rise V_IL(max) to V_IH(min)

RX_CLK clock fall time V_IH(min) to V_IL(max)

Note:

t_MRDXKH

t_MRXR

10.0

1.0

—

ns

4.0

t_MRXF

1.0

1. The symbols used for timing specifications herein follow the pattern of t_{(first two letters of functional block)(signal)(state) (reference)(state)}

for inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_MRDVKHsymbolizes MII

receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t_MRXclock reference

(K) going to the high (H) state or setup time. Also, t_MRDXKLsymbolizes MII receive timing (GR) with respect to the time data

input signals (D) went invalid (X) relative to the t_MRXclock reference (K) going to the low (L) state or hold time. Note that, in

general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.

For example, the subscript of t_MRXrepresents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is

used with the appropriate letter: R (rise) or F (fall).

This figure shows the MII receive AC timing diagram.

t_MRX

t_MRXR

RX_CLK

t_MRXF

Valid Data

t_MRXH

RXD[3:0]

RX_DV

RX_ER

t_MRDVKH

t_MRDXKH

Figure 9. MII Receive AC Timing Diagram RMII AC Timing Specifications

This figure provides the AC test load.

Output

NV_DD/

or

2

Z₀= 50 

R_L= 50 

LV_DD/2

Figure 10. AC Test Load

8.2.2

RGMII AC timing specifications

This table presents the RGMII AC timing specifications.

Table 25. RGMII AC Timing Specifications

At recommended operating conditions with LV_DDof 2.5 V 5%.

Parameter/Condition

Symbol ¹

Min

Typ

Max

Unit

Data to clock output skew (at transmitter)

Data to clock input skew (at receiver) ²

t_{SKRGT_TX}

t_{SKRGT_RX}

–0.6

1.0

—

0.6

ns

2.6

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

18

Ethernet: Three-Speed Ethernet, MII management

Table 25. RGMII AC Timing Specifications (continued)

At recommended operating conditions with LV_DDof 2.5 V 5%.

Clock cycle duration ³

t_RGT

t_RGTH/t_RGT

t_RGTR

t_RGTF

7.2

45

40

—

8.0

50

—

8.8

55

ns

%

Duty cycle for 1000Base-T ^{4, 5}

Duty cycle for 10BASE-T and 100BASE-TX ^{3, 5}

Rise time (20%–80%)

60

%

0.75

—

ns

%

Fall time (20%–80%)

—

6

GTX_CLK125 reference clock period

GTX_CLK125 reference clock duty cycle

Notes:

t_G12

—

8.0

—

t_{G125H G125}

/t

47

53

1. In general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII timing.

For example, the subscript of t_RGTrepresents the RGMII receive (RX) clock. Note also that the notation for rise (R) and fall

(F) times follows the clock symbol that is being represented. For symbols representing skews, the subscript is skew (SK)

followed by the clock that is being skewed (RGT).

2. This implies that PC board design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns is

added to the associated clock signal.

3. For 10 and 100 Mbps, t_RGTscales to 400 ns 40 ns and 40 ns 4 ns, respectively.

4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long

as the minimum duty cycle is not violated and stretching occurs for no more than three t_RGTof the lowest speed transitioned

between.

5. Duty cycle reference is 0.5*LV_DD

6. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

19

Ethernet: Three-Speed Ethernet, MII management

This figure shows the RGMII AC timing and multiplexing diagrams.

W

5*7

W

5*7+

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6.5*7B7;

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5*7

W

5*7+

ꢀ

ꢉ$Wꢀ3+<⁵ꢊꢀ^;RX^BW^&S^/X^.Wꢋꢀ

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ꢉ$Wꢀ3+<ꢊꢀRXWSXWꢋ

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6.5*7B7;

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5;'>ꢅ@

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Figure 11. RGMII AC Timing and Multiplexing Diagrams

8.3

Ethernet Management interface electrical characteristics

The electrical characteristics specified here apply to MII management interface signals MDIO

(management data input/output) and MDC (management data clock). The electrical characteristics for MII

and RGMII are specified in Section 8.1, “Enhanced Three-Speed Ethernet Controller (eTSEC)

(10/100/1000 Mbps)—MII/RGMII electrical characteristics.”

8.3.1

MII Management DC electrical characteristics

The MDC and MDIO are defined to operate at a supply voltage of 3.3 V. This table provides the DC

electrical characteristics for MDIO and MDC.

Table 26. MII Management DC Electrical Characteristics When Powered at 3.3 V

Parameter

Symbol

Conditions

Min

Max

Unit

Supply voltage (3.3 V)

Output high voltage

NV_DD

V_OH

—

3.0

3.6

V

I_OH= –1.0 mA

NV_DD= Min

2.10

NV_DD+ 0.3

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

20

Ethernet: Three-Speed Ethernet, MII management

Table 26. MII Management DC Electrical Characteristics When Powered at 3.3 V (continued)

Parameter

Symbol

Conditions

Min

Max

Unit

Output low voltage

Input high voltage

Input low voltage

Input high current

Input low current

Note:

V_OL

V_IH

V_IL

I_IH

I_OL= 1.0 mA

LV_DD= Min

VSS

2.0

0.50

—

V

—

0.80

40

V

NV_DD= Max

V_IN¹= 2.1 V

V_IN= 0.5 V

—

A

I_IL

–600

—

1. V_IN, in this case, represents the LV_INsymbol referenced in Table 1 and Table 2.

8.3.2

MII Management AC electrical specifications

This table provides the MII management AC timing specifications.

Table 27. MII Management AC Timing Specifications

At recommended operating conditions with LV_DDA/LV_DDBis 3.3 V 0.3V

Parameter/Condition

MDC frequency

Symbol ¹

Min

Typ

Max

Unit

Notes

f_MDC

t_MDC

—

32

10

5

2.5

400

—

MHz

ns

2

MDC period

—

3

MDC clock pulse width high

MDC to MDIO delay

MDIO to MDC setup time

MDIO to MDC hold time

MDC rise time

t_MDCH

—

ns

t_MDKHDX

t_MDDVKH

t_MDDXKH

t_MDCR

—

170

—

ns

—

ns

—

0

—

ns

—

10

ns

MDC fall time

t_MDHF

—

ns

Notes:

1. The symbols used for timing specifications Follow the pattern of t_{(first two letters of functional block)(signal)(state) (reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_MDKHDXsymbolizes management

data timing (MD) for the time t_MDCfrom clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time.

Also, t_MDDVKHsymbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state

(V) relative to the t_MDCclock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter

convention is used with the appropriate letter: R (rise) or F (fall).

2. This parameter is dependent on the csb_clk speed. (The MIIMCFG[Mgmt Clock Select] field determines the clock frequency

of the Mgmt Clock EC_MDC.)

3. This parameter is dependent on the cbs_clk speed (that is, for a csb_clk of 133 MHz, the delay is 60 ns).

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

21

Ethernet: Three-Speed Ethernet, MII management

This figure shows the MII management AC timing diagram.

t_MDC

t_MDCR

MDC

t_MDCF

t_MDCH

MDIO

(Input)

t_MDDVKH

t_MDDXKH

MDIO

(Output)

t_MDKHDX

Figure 12. MII Management Interface Timing Diagram

8.4

IEEE Std 1588™ Timer Specifications

This section describes the DC and AC electrical specifications for the 1588 timer.

8.4.1

IEEE 1588 Timer DC Specifications

This table provides the IEEE 1588 timer DC specifications.

Table 28. GPIO DC Electrical Characteristics

Characteristic

Output high voltage

Symbol

Condition

Min

Max

Unit

V_OH

V_OL

I_OH= –8.0 mA

I_OL= 8.0 mA

2.4

—

V

Output low voltage

Input high voltage

Input low voltage

Input current

0.5

V

I

= 3.2 mA

OL

—

0.4

V

OL

V_IH

V_IL

I_IN

—

2.0

–0.3

—

NVDD + 0.3

V

0.8

5

V

0 V V_INNVDD

A

8.4.2

IEEE 1588 Timer AC specifications

This table provides the IEEE 1588 timer AC specifications.

Table 29. IEEE 1588 Timer AC Specifications

Parameter

Symbol

Min

Max

Unit

Notes

Timer clock cycle time

t_TMRCK

t_TMRCKS

t_TMRCKH

0

70

—

MHz

—

1

Input setup to timer clock

Input hold from timer clock

—

2, 3

—

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

22

USB

Table 29. IEEE 1588 Timer AC Specifications (continued)

Parameter

Output clock to output valid

Symbol

Min

Max

Unit

Notes

t_GCLKNV

t_TMRAL

0

6

ns

—

2

Timer alarm to output valid

—

Note:

1. The timer can operate on rtc_clock or tmr_clock. These clocks get muxed and any one of them can be selected.

2. Asynchronous signals.

3. Inputs need to be stable at least one TMR clock.

9 USB

9.1

USB Dual-Role controllers

This section provides the AC and DC electrical specifications for the USB-ULPI interface.

9.1.1

USB DC electrical characteristics

This table lists the DC electrical characteristics for the USB interface.

Table 30. USB DC Electrical Characteristics

Parameter

Symbol

Min

Max

Unit

High-level input voltage

Low-level input voltage

Input current

V_IH

V_IL

2

–0.3

LVDD + 0.3

V

0.8

5

I_IN

—

A

V

High-level output voltage, I_OH= –100 A

Low-level output voltage, I_OL= 100 A

Note:

V_OH

V_OL

LVDD – 0.2

—

0.2

V

1. The symbol V_IN, in this case, represents the NV_INsymbol referenced in Table 1 and Table 2.

9.1.2

USB AC electrical specifications

This table lists the general timing parameters of the USB-ULPI interface.

Table 31. USB General Timing Parameters

Parameter

Symbol ¹

Min

Max

Unit

Notes

USB clock cycle time

t_USCK

t_USIVKH

t_USIXKH

15

4

—

ns

1, 2

1, 4

Input setup to USB clock—all inputs

Input hold to USB clock—all inputs

1

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

23

USB

Table 31. USB General Timing Parameters (continued)

Parameter

Symbol ¹

Min

Max

Unit

Notes

USB clock to output valid—all outputs

Output hold from USB clock—all outputs

Notes:

t_USKHOV

t_USKHOX

—

1

9

ns

1

—

1. The symbols used for timing specifications follow the pattern of t_{(First two letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(First two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_USIXKHsymbolizes usb timing

(US) for the input (I) to go invalid (X) with respect to the time the usb clock reference (K) goes high (H). Also, t_USKHOX

symbolizes usb timing (US) for the usb clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or

output hold time.

2. All timings are in reference to USB clock.

3. All signals are measured from NVDD/2 of the rising edge of USB clock to 0.4  NVDD of the signal in question for 3.3-V

signaling levels.

4. Input timings are measured at the pin.

5. For purposes of active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

The following two figures provide the AC test load and signals for the USB, respectively.

Z⁰= 50 

Output

NVDD/2

R^L= 50 

Figure 13. USB AC Test Load

USBDR_CLK

t_USIXKH

t_USIVKH

Input Signals

t_USKHOV

t_USKHOX

Output Signals

Figure 14. USB Signals

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24

High-Speed Serial interfaces (HSSI)

10 High-Speed Serial interfaces (HSSI)

This section describes the common portion of SerDes DC electrical specifications, which is the DC

requirement for SerDes reference clocks. The SerDes data lane’s transmitter and receiver reference circuits

are also shown.

10.1 Signal terms definition

The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms

used in the description and specification of differential signals.

Figure 15 shows how the signals are defined. For illustration purpose, only one SerDes lane is used for

description. The figure shows waveform for either a transmitter output (TXn and TXn) or a receiver input

(RXn and RXn). Each signal swings between A Volts and B Volts where A > B.

Using this waveform, the definitions are as follows. To simplify illustration, the following definitions

assume that the SerDes transmitter and receiver operate in a fully symmetrical differential signaling

environment.

•

Single-Ended Swing

The transmitter output signals and the receiver input signals TXn, TXn, RXn, and RXn each have

a peak-to-peak swing of A – B Volts. This is also referred as each signal wire’s single-ended swing.

•

Differential Output Voltage, V (or Differential Output Swing)

OD

The differential output voltage (or swing) of the transmitter, V , is defined as the difference of

OD

the two complimentary output voltages: V

negative.

– V . The V value can be either positive or

TXn

TXn OD

•

Differential Input Voltage, V (or Differential Input Swing)

ID

The differential input voltage (or swing) of the receiver, V , is defined as the difference of the two

ID

complimentary input voltages: V

– V

. The V value can be either positive or negative.

RXn

RXn ID

Differential Peak Voltage, V

The peak value of the differential transmitter output signal or the differential receiver input signal

is defined as Differential Peak Voltage, V = |A – B| Volts.

DIFFp

Differential Peak-to-Peak, V

DIFFp-p

Since the differential output signal of the transmitter and the differential input signal of the receiver

each range from A – B to –(A – B) Volts, the peak-to-peak value of the differential transmitter

output signal or the differential receiver input signal is defined as differential peak-to-peak voltage,

V

= 2*V

= 2 * |(A – B)| Volts, which is twice of differential swing in amplitude, or

DIFFp-p

DIFFp

twice of the differential peak. For example, the output differential peak-peak voltage can also be

calculated as V = 2*|V |.

TX-DIFFp-p

OD

•

Differential Waveform

The differential waveform is constructed by subtracting the inverting signal (for example, TXn)

from the non-inverting signal (for example, TXn) within a differential pair. There is only one signal

trace curve in a differential waveform. The voltage represented in the differential waveform is not

referenced to ground. Refer to Figure 24 as an example for differential waveform.

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High-Speed Serial interfaces (HSSI)

•

Common Mode Voltage, V

cm

The common mode voltage is equal to one-half of the sum of the voltages between each conductor

of a balanced interchange circuit and ground. In this example, for SerDes output,

V

= (V

+ V )/2 = (A + B) / 2, which is the arithmetic mean of the two complimentary

cm_out

TXn TXn

output voltages within a differential pair. In a system, the common mode voltage may often differ

from one component’s output to the other’s input. Sometimes, it may be even different between the

receiver input and driver output circuits within the same component. It is also referred as the DC

offset in some occasion.

TXn or RXn

A Volts

V_cm= (A + B) / 2

TXn or RXn

B Volts

Differential Swing, V_IDor V_OD= A – B

Differential Peak Voltage, V_DIFFp= |A – B|

Differential Peak-Peak Voltage, V_DIFFpp= 2*V_DIFFp(not shown)

Figure 15. Differential Voltage Definitions for Transmitter or Receiver

To illustrate these definitions using real values, consider the case of a current mode logic (CML)

transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing

that goes between 2.5 V and 2.0 V. Using these values, the peak-to-peak voltage swing of each signal (TD

or TD) is 500 mV p-p, which is referred as the single-ended swing for each signal. In this example, since

the differential signaling environment is fully symmetrical, the transmitter output’s differential swing

(V ) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges

OD

between 500 mV and –500 mV, in other words, V is 500 mV in one phase and –500 mV in the other

OD

phase. The peak differential voltage (V

is 1000 mV p-p.

) is 500 mV. The peak-to-peak differential voltage (V

)

DIFFp

DIFFp-p

10.2 SerDes reference clocks

The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by

the corresponding SerDes lanes. The SerDes reference clocks input is SD_REF_CLK and SD_REF_CLK

for PCI Express.

The following sections describe the SerDes reference clock requirements and some application

information.

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Freescale Semiconductor

High-Speed Serial interfaces (HSSI)

10.2.1 SerDes reference clock receiver characteristics

Figure 16 shows a receiver reference diagram of the SerDes reference clocks.

•

The supply voltage requirements for XCOREVDD are specified in Table 1 and Table 2.

SerDes reference clock receiver reference circuit structure

— The SD_REF_CLK and SD_REF_CLK are internally AC-coupled differential inputs as shown

in Figure 16. Each differential clock input (SD_REF_CLK or SD_REF_CLK) has a 50-

termination to XCOREVSS followed by on-chip AC-coupling.

— The external reference clock driver must be able to drive this termination.

— The SerDes reference clock input can be either differential or single-ended. Refer to the

Differential Mode and Single-ended Mode description below for further detailed requirements.

•

The maximum average current requirement that also determines the common mode voltage range

— When the SerDes reference clock differential inputs are DC coupled externally with the clock

driver chip, the maximum average current allowed for each input pin is 8mA. In this case, the

exact common mode input voltage is not critical as long as it is within the range allowed by the

maximum average current of 8 mA (refer to the following bullet for more detail), since the

input is AC-coupled on-chip.

— This current limitation sets the maximum common mode input voltage to be less than 0.4 V

(0.4 V/50 = 8 mA) while the minimum common mode input level is 0.1 V above XCOREVSS.

For example, a clock with a 50/50 duty cycle can be produced by a clock driver with output

driven by its current source from 0mA to 16mA (0–0.8 V), such that each phase of the

differential input has a single-ended swing from 0 V to 800 mV with the common mode voltage

at 400mV.

— If the device driving the SD_REF_CLK and SD_REF_CLK inputs cannot drive 50  to

XCOREVSS DC, or it exceeds the maximum input current limitations, then it must be

AC-coupled off-chip.

•

The input amplitude requirement

— This requirement is described in detail in the following sections.

50 

SD_REF_CLK

Input

Amp

SD_REF_CLK

50 

Figure 16. Receiver of SerDes Reference Clocks

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High-Speed Serial interfaces (HSSI)

10.2.2 DC level requirement for SerDes reference clocks

The DC level requirement for the MPC8308 SerDes reference clock inputs is different depending on the

signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described

below.

•

Differential Mode

— The input amplitude of the differential clock must be between 400 mV and 1600 mV

differential peak-peak (or between 200 mV and 800 mV differential peak). In other words,

each signal wire of the differential pair must have a single-ended swing less than 800 mV and

greater than 200 mV. This requirement is the same for both external DC-coupled or

AC-coupled connection.

— For external DC-coupled connection, as described in Section 10.2.1, “SerDes reference clock

receiver characteristics,” the maximum average current requirements sets the requirement for

average voltage (common mode voltage) to be between 100 mV and 400 mV. Figure 17 shows

the SerDes reference clock input requirement for DC-coupled connection scheme.

— For external AC-coupled connection, there is no common mode voltage requirement for the

clock driver. Since the external AC-coupling capacitor blocks the DC level, the clock driver

and the SerDes reference clock receiver operate in different command mode voltages. The

SerDes reference clock receiver in this connection scheme has its common mode voltage set to

XCOREVSS. Each signal wire of the differential inputs is allowed to swing below and above

the common mode voltage (XCOREVSS). Figure 18 shows the SerDes reference clock input

requirement for AC-coupled connection scheme.

•

Single-ended Mode

— The reference clock can also be single-ended. The SD_REF_CLK input amplitude

(single-ended swing) must be between 400 mV and 800 mV peak-peak (from Vmin to Vmax)

with SD_REF_CLK either left unconnected or tied to ground.

— The SD_REF_CLK input average voltage must be between 200 and 400 mV. Figure 19 shows

the SerDes reference clock input requirement for single-ended signaling mode.

— To meet the input amplitude requirement, the reference clock inputs might need to be DC or

AC-coupled externally. For the best noise performance, the reference of the clock could be DC

or AC-coupled into the unused phase (SD_REF_CLK) through the same source impedance as

the clock input (SD_REF_CLK) in use.

200 mV < Input Amplitude or Differential Peak < 800mV

SD_REF_CLK

Vmax < 80 0mV

100 mV < Vcm < 400 mV

Vmin > 0 V

SD_REF_CLK

Figure 17. Differential Reference Clock Input DC Requirements (External DC-Coupled)

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High-Speed Serial interfaces (HSSI)

200mV < Input Amplitude or Differential Peak < 800mV

SD_REF_CLK

Vmax < Vcm + 400 mV

Vcm

Vmin > Vcm – 400 mV

SD_REF_CLK

Figure 18. Differential Reference Clock Input DC Requirements (External AC-Coupled)

400 mV < SD_REF_CLK Input Amplitude < 800 mV

SD_REF_CLK

0 V

SD_REF_CLK

Figure 19. Single-Ended Reference Clock Input DC Requirements

10.2.3 Interfacing with other differential signaling levels

With on-chip termination to XCOREVSS, the differential reference clocks inputs are high-speed current

steering logic (HCSL) compatible and DC coupled.

Many other low voltage differential type outputs like low-voltage differential signaling (LVDS) can be

used but may need to be AC-coupled due to the limited common mode input range allowed (100–400 mV)

for DC-coupled connection.

LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at clock

driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to

AC-coupling.

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High-Speed Serial interfaces (HSSI)

NOTE

Figure 20–Figure 23 are for conceptual reference only. Due to the fact that

clock driver chip's internal structure, output impedance, and termination

requirements are different between various clock driver chip manufacturers,

it is very much possible that the clock circuit reference designs provided by

clock driver chip vendor are different from what is shown below. They

might also vary from one vendor to the other. Therefore, Freescale

Semiconductor can neither provide the optimal clock driver reference

circuits, nor guarantee the correctness of the following clock driver

connection reference circuits. The system designer is recommended to

contact the selected clock driver chip vendor for the optimal reference

circuits with the MPC8308 SerDes reference clock receiver requirement

provided in this document.

This figure shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It

assumes that the DC levels of the clock driver chip is compatible with MPC8308 SerDes reference clock

input’s DC requirement.

MPC8308

HCSL CLK Driver Chip

50 

SD_REF_CLK

CLK_Out

33 

SerDes Refer.

CLK Receiver

100 differential PWB trace

Clock Driver

CLK_Out

SD_REF_CLK

50 

Clock driver vendor dependent

source termination resistor

Total 50 Assume clock driver’s

output impedance is about 16 

Figure 20. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)

This figure shows the SerDes reference clock connection reference circuits for LVDS type clock driver.

Since LVDS clock driver’s common mode voltage is higher than the MPC8308’s SerDes reference clock

input’s allowed range (100–400 mV), AC-coupled connection scheme must be used. It assumes the LVDS

output driver features 50-termination resistor. It also assumes that the LVDS transmitter establishes its

own common mode level without relying on the receiver or other external component.

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Freescale Semiconductor

High-Speed Serial interfaces (HSSI)

MPC8308

LVDS CLK Driver Chip

50 

SD_REF_CLK

10 nF

CLK_Out

SerDes Refer.

CLK Receiver

100 differential PWB trace

Clock Driver

CLK_Out

10 nF

50 

Figure 21. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)

Figure 22 shows the SerDes reference clock connection reference circuits for LVPECL type clock driver.

Since LVPECL driver’s DC levels (both common mode voltages and output swing) are incompatible with

MPC8308 SerDes reference clock input’s DC requirement, AC-coupling has to be used.

This figure assumes that the LVPECL clock driver’s output impedance is 50 R1 is used to DC-bias the

LVPECL outputs prior to AC-coupling. Its value could be ranged from 140 to 240 depending on clock

driver vendor’s requirement. R2 is used together with the SerDes reference clock receiver’s 50-

termination resistor to attenuate the LVPECL output’s differential peak level such that it meets the

MPC8308’s SerDes reference clock’s differential input amplitude requirement (between 200 mV and

800 mV differential peak). For example, if the LVPECL output’s differential peak is 900 mV and the

desired SerDes reference clock input amplitude is selected as 600 mV, the attenuation factor is 0.67, which

requires R2 = 25 Please consult clock driver chip manufacturer to verify whether this connection

scheme is compatible with a particular clock driver chip.

LVPECL CLK

Driver Chip

MPC8308

50 

SD_REF_CLK

CLK_Out

10nF

R2

SerDes Refer.

CLK Receiver

R1

100 differential PWB trace

10 nF

Clock Driver

R2

SD_REF_CLK

CLK_Out

50 

Figure 22. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)

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31

High-Speed Serial interfaces (HSSI)

This figure shows the SerDes reference clock connection reference circuits for a single-ended clock driver.

It assumes the DC levels of the clock driver are compatible with the device’s SerDes reference clock

input’s DC requirement.

Single-Ended

CLK Driver Chip

MPC8308

Total 50 Assume clock driver’s

output impedance is about 16 

50 

SD_REF_CLK

33 

Clock Driver

CLK_Out

SerDes Refer.

CLK Receiver

100 differential PWB trace

SD_REF_CLK

50 

Figure 23. Single-Ended Connection (Reference Only)

10.2.4 AC requirements for SerDes reference clocks

The clock driver selected should provide a high quality reference clock with low phase noise and

cycle-to-cycle jitter. Phase noise less than 100 kHz can be tracked by the PLL and data recovery loops and

is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise

occurs in the 1–15 MHz range. The source impedance of the clock driver should be 50  to match the

transmission line and reduce reflections which are a source of noise to the system.

This table describes some AC parameters for PCI Express protocol.

Table 32. SerDes Reference Clock AC Parameters

At recommended operating conditions with XCOREVDD= 1.0V 5%

Parameter

Symbol

Min

Max

Unit

Notes

Rising Edge Rate

Falling Edge Rate

Rise Edge Rate

1.0

4.0

V/ns

mV

2, 3

2

Fall Edge Rate

Differential Input High Voltage

Differential Input Low Voltage

V_IH

V_IL

+200

—

–200

mV

2

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High-Speed Serial interfaces (HSSI)

Table 32. SerDes Reference Clock AC Parameters (continued)

At recommended operating conditions with XCOREVDD= 1.0V 5%

Parameter

Symbol

Min

Max

Unit

Notes

Rising edge rate (SD_REF_CLK) to falling edge rate

(SD_REF_CLK) matching

Rise-Fall

Matching

—

20

%

1, 4

Notes:

1. Measurement taken from single ended waveform.

2. Measurement taken from differential waveform.

3. Measured from –200 mV to +200 mV on the differential waveform (derived from SD_REF_CLK minus SD_REF_CLK). The

signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is centered

on the differential zero crossing (Figure 24).

4. Matching applies to rising edge rate for SD_REF_CLK and falling edge rate for SD_REF_CLK. It is measured using a 200

mV window centered on the median cross point where SD_REF_CLK rising meets SD_REF_CLK falling. The median cross

point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge Rate

of SD_REF_CLK should be compared to the Fall Edge Rate of SD_REF_CLK, the maximum allowed difference should not

exceed 20% of the slowest edge rate (See Figure 25).

V_IH

=

+200

0.0 V

V_IL= -200 mV

SD_REF_CLK

minus

SD_REF_CLK

Figure 24. Differential Measurement Points for Rise and Fall Time

SD_REF_CLK

Figure 25. Single-Ended Measurement Points for Rise and Fall Time Matching

The other detailed AC requirements of the SerDes reference clocks is defined by each interface protocol

based on application usage. For detailed information, see the following sections:

•

Section 11.2, “AC Requirements for PCI Express SerDes Clocks”

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PCI Express

10.2.4.1 Spread Spectrum Clock

SD_REF_CLK/SD_REF_CLK are not intended to be used with, and should not be clocked by, a spread

spectrum clock source.

10.3 SerDes Transmitter and Receiver Reference Circuits

This figure shows the reference circuits for SerDes data lane’s transmitter and receiver.

RXn

TXn

50 

Receiver

Transmitter

TXn

RXn

Figure 26. SerDes Transmitter and Receiver Reference Circuits

The DC and AC specification of SerDes data lanes are defined in Section 11, “PCI Express.”

Note that external AC coupling capacitor is required for the PCI Express serial transmission protocol with

the capacitor value defined in specification of PCI Express protocol section.

11 PCI Express

This section describes the DC and AC electrical specifications for the PCI Express bus.

11.1 DC Requirements for PCI Express SD_REF_CLK and

SD_REF_CLK

For more information, see Section 10.2, “SerDes reference clocks.”

11.2 AC Requirements for PCI Express SerDes Clocks

This table lists the PCI Express SerDes clock AC requirements.

Table 33. SD_REF_CLK and SD_REF_CLK AC Requirements

Symbol

Parameter Description

Min

Typ

Max

Units

Notes

t_REF

REFCLK cycle time (for 125 MHz and 100 MHz)

8

10

—

ns

ps

—

t_REFCJ

REFCLK cycle-to-cycle jitter. Difference in the period

of any two adjacent REFCLK cycles.

—

100

t_REFPJ

Phase jitter. Deviation in edge location with respect to

mean edge location.

–50

—

50

ps

—

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PCI Express

11.3 Clocking Dependencies

The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm)

of each other at all times. This is specified to allow bit rate clock sources with a ±300 ppm tolerance.

11.4 Physical Layer Specifications

Following is a summary of the specifications for the physical layer of PCI Express on this device. For

further details as well as the specifications of the transport and data link layer please use the PCI Express

Base Specification, Rev. 1.0a.

11.4.1 Differential Transmitter (TX) Output

This table defines the specifications for the differential output at all transmitters (TXs). The parameters are

specified at the component pins.

Table 34. Differential Transmitter (TX) Output Specifications

Parameter

Unit interval

Symbol

Comments

Min Typical Max Units Note

UI

Each U_PETXis 400 ps 300 ppm. U_PETX399.88

does not account for Spread Spectrum

Clock dictated variations.

400

400.12 ps

1

Differential peak-to-peak

output voltage

V_TX-DIFFp-p

V_PEDPPTX= 2*|V_TX-D+- V_TX-D-

|

0.8

—

1.2

V

2

De-Emphasized differential

output voltage (ratio)

V_TX-DE-RATIO

Ratio of the V_PEDPPTXof the second and –3.0

following bits after a transition divided by

the V_PEDPPTXof the first bit after a

transition.

–3.5

–4.0

dB

Minimum TX eye width

T_TX-EYE

The maximum Transmitter jitter can be

derived as T_{TX-MAX-JITTER}= 1 -

U_PEEWTX= 0.3 UI.

0.70

—

UI

2, 3

Maximum time between the T_{TX-EYE-MEDIAN-to-}Jitter is defined as the measurement

—

0.15

jitter median and maximum

deviation from the median

variation of the crossing points

MAX-JITTER

(V_PEDPPTX= 0 V) in relation to a

recovered TX UI. A recovered TX UI is

calculated over 3500 consecutive unit

intervals of sample data. Jitter is

measured using all edges of the 250

consecutive UI in the center of the 3500

UI used for calculating the TX UI.

D+/D- TX output rise/fall

time

T_TX-RISE, T_TX-FALL

—

0.125

—

UI

2, 5

2

RMS AC peak common

mode output voltage

V_TX-CM-ACp

V_PEACPCMTX= RMS(|V_TXD++ V_TXD-|/2 -

20

mV

V_TX-CM-DC

)

V_TX-CM-DC= DC_(avg)of |V_TX-D+

V_TX-D-|/2

+

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PCI Express

Table 34. Differential Transmitter (TX) Output Specifications (continued)

Symbol Comments Min Typical Max Units Note

V_{TX-CM-DC- ACTIVE-}|V_{TX-CM-DC (during L0)}- V_{TX-CM-Idle-DC}

Parameter

Absolute delta of DC

0

—

100

mV

2

common mode voltage

during L0 and electrical idle

_{(During Electrical Idle)}|<=100 mV

V_TX-CM-DC= DC_(avg)of |V_TX-D+

IDLE-DELTA

+

V_TX-D-|/2 [L0]

V_{TX-CM-Idle-DC}= DC_(avg)of |V_TX-D+

V_TX-D-|/2 [Electrical Idle]

+

Absolute delta of DC

common mode between D+

and D–

V_{TX-CM-DC-LINE-}|V_TX-CM-DC-D+- V_TX-CM-DC-D-| <= 25 mV

_TX-CM-DC-D+= DC_(avg)of |V_TX-D+

V_TX-CM-DC-D-= DC_(avg)of |V_TX-D-

0

—

25

mV

2

V

|

DELTA

|

Electrical idle differential

peak output voltage

V_{TX-IDLE-DIFFp}V_PEEIDPTX= |V_TX-IDLE-D+-V_TX-IDLE-D-

<= 20 mV

|

0

—

20

—

mV

2

6

Amount of voltage change

allowed during receiver

detection

V_{TX-RCV-DETECT}The total amount of voltage change that

a transmitter can apply to sense whether

—

600

a low impedance Receiver is present.

TX DC common mode

voltage

V_TX-DC-CM

The allowed DC Common Mode voltage

under any conditions.

—

50

3.6

—

90

—

V

6

TX short circuit current limit

I_TX-SHORT

The total current the Transmitter can

provide when shorted to its ground

mA

UI

—

Minimum time spent in

electrical idle

T_TX-IDLE-MIN

Minimum time a Transmitter must be in

Electrical Idle Utilized by the Receiver to

start looking for an Electrical Idle Exit

after successfully receiving an Electrical

Idle ordered set

—

Maximum time to transition T_{TX-IDLE-SET-TO-ID}After sending an Electrical Idle ordered

—

20

UI

—

to a valid electrical idle after

sending an electrical idle

ordered set

set, the Transmitter must meet all

Electrical Idle Specifications within this

time. This is considered a debounce time

for the Transmitter to meet Electrical Idle

after transitioning from L0.

LE

Maximum time to transition T_{TX-IDLE-TO-DIFF-D}Maximum time to meet all TX

to valid TX specifications

after leaving an electrical

idle condition

specifications when transitioning from

Electrical Idle to sending differential

data. This is considered a debounce

time for the TX to meet all TX

ATA

specifications after leaving Electrical Idle

Differential return loss

RL_TX-DIFF

RL_TX-CM

Measured over 50 MHz to 1.25 GHz.

12

6

—

dB



4

Common mode return loss

DC differential TX

impedance

Z_TX-DIFF-DC

TX DC Differential mode Low

Impedance

80

100

120

—

Transmitter DC impedance

Z_TX-DC

Required TX D+ as well as D- DC

Impedance during all states

40

—



—

Lane-to-Lane output skew

L_TX-SKEW

Static skew between any two Transmitter

Lanes within a single Link

500 + 2 ps

UI

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PCI Express

Table 34. Differential Transmitter (TX) Output Specifications (continued)

Parameter

Symbol

Comments

Min Typical Max Units Note

AC coupling capacitor

C_TX

All Transmitters shall be AC coupled.

The AC coupling is required either within

the media or within the transmitting

component itself. An external capacitor

of 100nF is recommended.

75

—

200

nF

—

Crosslink random timeout

T_crosslink

This random timeout helps resolve

conflicts in crosslink configuration by

eventually resulting in only one

0

—

1

ms

7

Downstream and one Upstream Port.

Notes:

1. No test load is necessarily associated with this value.

2. Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 29 and measured over any

250 consecutive TX UIs. (Also refer to the transmitter compliance eye diagram shown in Figure 27.)

3. A T_TX-EYE= 0.70 UI provides for a total sum of deterministic and random jitter budget of T_{TX-JITTER-MAX}= 0.30 UI for the

transmitter collected over any 250 consecutive TX UIs. The T_{TX-EYE-MEDIAN-to-MAX-JITTER}median is less than half of the total TX

jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The

jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to

the averaged time value.

4. The transmitter input impedance shall result in a differential return loss greater than or equal to 12 dB and a common mode return

loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to

all valid input levels. The reference impedance for return loss measurements is 50  to ground for both the D+ and D– line (that

is, as measured by a vector network analyzer with 50- probes, see Figure 29). Note that the series capacitors, C_TX, is optional

for the return loss measurement.

5. Measured between 20%–80% at transmitter package pins into a test load as shown in Figure 29 for both V_TX-D+and V_TX-D-

6. See Section 4.3.1.8 of the PCI Express Base Specifications, Rev 1.0a.

.

7. See Section 4.2.6.3 of the PCI Express Base Specifications, Rev 1.0a.

11.4.2 Transmitter Compliance Eye Diagrams

The TX eye diagram in Figure 27 is specified using the passive compliance/test measurement load

(Figure 29) in place of any real PCI Express interconnect + RX component. There are two eye diagrams

that must be met for the transmitter. Both diagrams must be aligned in time using the jitter median to locate

the center of the eye diagram. The different eye diagrams differ in voltage depending on whether it is a

transition bit or a de-emphasized bit. The exact reduced voltage level of the de-emphasized bit is always

relative to the transition bit.

The eye diagram must be valid for any 250 consecutive UIs.

A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is

created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX

UI.

NOTE

It is recommended that the recovered TX UI be calculated using all edges in

the 3500 consecutive UI interval with a fit algorithm using a minimization

merit function (that is, least squares and median deviation fits).

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

37

PCI Express

V_TX-DIFF= 0 mV

(D+ D– Crossing Point)

[Transition Bit]

_{TX-DIFFp-p-MIN}= 800 mV

V

[De-emphasized Bit]

566 mV (3 dB) >= V_{TX-DIFFp-p-MIN}>= 505 mV (4 dB)

0.7 UI = UI – 0.3 UI(J_TX-TOTAL-MAX

)

[Transition Bit]

_{TX-DIFFp-p-MIN}= 800 mV

V

Figure 27. Minimum Transmitter Timing and Voltage Output Compliance Specifications

11.4.3 Differential Receiver (RX) Input Specifications

This table defines the specifications for the differential input at all receivers (RXs). The parameters are

specified at the component pins.

Table 35. Differential Receiver (RX) Input Specifications

Parameter

Unit interval

Symbol

Comments

Min Typical Max Units Note

UI

Each U_PERXis 400 ps 300 ppm.

U_PERXdoes not account for Spread

Spectrum Clock dictated variations.

399.88

400

400.12 ps

1

Differential peak-to-peak

output voltage

V_RX-DIFFp-p

V_PEDPPRX= 2*|V_RX-D+- V_RX-D-

|

0.175

0.4

—

1.200

—

V

2

Minimum receiver eye width

T_RX-EYE

The maximum interconnect media and

Transmitter jitter that can be tolerated

by the Receiver can be derived as

T_{RX-MAX-JITTER}= 1 - U_PEEWRX= 0.6 UI.

UI

2, 3

Maximum time between the T_{RX-EYE-MEDIAN-to-}Jitter is defined as the measurement

—

0.3

UI

2, 3,

7

jitter median and maximum

deviation from the median.

variation of the crossing points

MAX-JITTER

(V_PEDPPRX= 0 V) in relation to a

recovered TX UI. A recovered TX UI is

calculated over 3500 consecutive unit

intervals of sample data. Jitter is

measured using all edges of the 250

consecutive UI in the center of the 3500

UI used for calculating the TX UI.

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

38

PCI Express

Table 35. Differential Receiver (RX) Input Specifications (continued)

Parameter

Symbol

Comments

Min Typical Max Units Note

AC peak common mode

input voltage

V_RX-CM-ACp

V_PEACPCMRX= |V_RXD++ V_RXD-|/2 -

V_RX-CM-DC

V_RX-CM-DC= DC_(avg)of |V_RX-D+

_RX-D-|/2

—

150

mV

2

+

V

Differential return loss

RL_RX-DIFF

Measured over 50 MHz to 1.25 GHz

with the D+ and D- lines biased at +300

mV and -300 mV, respectively.

15

—

dB

4

Common mode return loss

RL_RX-CM

Z_RX-DIFF-DC

Z_RX-DC

Measured over 50 MHz to 1.25 GHz

with the D+ and D- lines biased at 0 V.

6

80

—

100

50

—

120

60

dB



4

5

DC differential input

impedance

RX DC differential mode impedance.

DC Input Impedance

Required RX D+ as well as D- DC

Impedance (50 20% tolerance).

40



2, 5

Powered down DC input

impedance

Z_{RX-HIGH-IMP-DC}Required RX D+ as well as D- DC

Impedance when the Receiver

200 k

—



6

terminations do not have power.

Electrical idle detect

threshold

V_{RX-IDLE-DET-DIFFp-p}V_PEEIDT= 2*|V_RX-D+-V_RX-D-

|

65

—

175

10

mV

ms

Measured at the package pins of the

Receiver

—

Unexpected Electrical Idle

Enter Detect Threshold

Integration Time

T_{RX-IDLE-DET-DIFF-}An unexpected Electrical Idle

(Vrx-diffp-p < Vrx-idle-det-diffp-p) must

be recognized no longer than

ENTERTIME

Trx-idle-det-diff-entertime to signal an

unexpected idle condition.

Total Skew

L_RX-SKEW

Skew across all lanes on a Link. This

includes variation in the length of SKP

ordered set (for example, COM and one

to five SKP Symbols) at the RX as well

as any delay differences arising from

the interconnect itself.

—

20

ns

—

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

39

PCI Express

Table 35. Differential Receiver (RX) Input Specifications (continued)

Symbol Comments Min Typical Max Units Note

Parameter

Notes:

1. No test load is necessarily associated with this value.

2. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 29 should be used as

the RX device when taking measurements (also refer to the receiver compliance eye diagram shown in Figure 28). If the clocks

to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used

as a reference for the eye diagram.

3. A T_RX-EYE= 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and interconnect

collected any 250 consecutive UIs. The T_{RX-EYE-MEDIAN-to-MAX-JITTER}specification ensures a jitter distribution in which the

median and the maximum deviation from the median is less than half of the total. UI jitter budget collected over any 250

consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in

time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. If the clocks

to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used

as the reference for the eye diagram.

4. The receiver input impedance shall result in a differential return loss greater than or equal to 15 dB with the D+ line biased to

300 mV and the D– line biased to –300 mV and a common mode return loss greater than or equal to 6 dB (no bias required)

over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The reference

impedance for return loss measurements for is 50  to ground for both the D+ and D– line (that is, as measured by a vector

network analyzer with 50- probes, see Figure 29). Note that the series capacitors, C_TX, is optional for the return loss

measurement.

5. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM) there

is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.

6. The RX DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps ensure

that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be measured at

300 mV above the RX ground.

7. It is recommended that the recovered TX UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm

using a minimization merit function. Least squares and median deviation fits have worked well with experimental and simulated

data.

11.5 Receiver Compliance Eye Diagrams

The RX eye diagram in Figure 28 is specified using the passive compliance/test measurement load

(Figure 29) in place of any real PCI Express RX component. In general, the minimum receiver eye diagram

measured with the compliance/test measurement load (Figure 29) is larger than the minimum receiver eye

diagram measured over a range of systems at the input receiver of any real PCI Express component. The

degraded eye diagram at the input Receiver is due to traces internal to the package as well as silicon

parasitic characteristics which cause the real PCI Express component to vary in impedance from the

compliance/test measurement load. The input receiver eye diagram is implementation specific and is not

specified. RX component designer should provide additional margin to adequately compensate for the

degraded minimum Receiver eye diagram (shown in Figure 28) expected at the input receiver based on an

adequate combination of system simulations and the return loss measured looking into the RX package

and silicon. The RX eye diagram must be aligned in time using the jitter median to locate the center of the

eye diagram.

The eye diagram must be valid for any 250 consecutive UIs. A recovered TX UI is calculated over 3500

consecutive unit intervals of sample data. The eye diagram is created using all edges of the 250 consecutive

UI in the center of the 3500 UI used for calculating the TX UI.

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

40

Freescale Semiconductor

Enhanced Local Bus

NOTE

The reference impedance for return loss measurements is 50  to ground for

both the D+ and D- line (that is, as measured by a Vector Network Analyzer

with 50  probes—see Figure 29). Note that the series capacitors,

C

, are optional for the return loss measurement.

PEACCTX

V

= 0 mV

V

= 0 mV

RX-DIFF

(D+ D– Crossing Point)

V

> 175 mV

RX-DIFFp-p-MIN

0.4 UI = T

RX-EYE-MIN

Figure 28. Minimum Receiver Eye Timing and Voltage Compliance Specification

11.5.1 Compliance Test and Measurement Load

The AC timing and voltage parameters must be verified at the measurement point, as specified within

0.2 inches of the package pins, into a test/measurement load shown in Figure 29.

NOTE

The allowance of the measurement point to be within 0.2 inches of the

package pins is meant to acknowledge that package/board routing may

benefit from D+ and D– not being exactly matched in length at the package

pin boundary.

Figure 29. Compliance Test/Measurement Load

12 Enhanced Local Bus

This section describes the DC and AC electrical specifications for the enhanced local bus interface.

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

41

Enhanced Local Bus

12.1 Enhanced Local Bus DC Electrical Characteristics

This table provides the DC electrical characteristics for the local bus interface.

Table 36. Local Bus DC Electrical Characteristics at 3.3 V

Parameter

Symbol

Min

Max

Unit

High-level input voltage

Low-level input voltage

V_IH

V_IL

2.0

–0.3

NV_DD+ 0.3

V

0.8

5

Input current, (V_IN¹= 0 V or V_IN= LV_DD

)

I_IN

—

A

V

High-level output voltage, (LV_DD= min, I_OH= –2 mA)

Low-level output voltage, (LV_DD= min, I_OL= 2 mA)

V_OH

V_OL

NV_DD– 0.2

—

0.2

V

Note: The parameters stated in above table are valid for all revisions unless explicitly mentioned.

12.2 Enhanced Local Bus AC Electrical Specifications

This table describes the general timing parameters of the local bus interface.

Table 37. Local Bus General Timing Parameters

Parameter

Symbol ¹

Min

Max

Unit

Notes

Local bus cycle time

t_LBK

15

7

—

3

ns

2

3, 4

3

Input setup to local bus clock

Input hold from local bus clock

Local bus clock to output valid

Local bus clock to output high impedance for LD

Notes:

t_LBIVKH

t_LBIXKH

t_LBKHOV

t_LBKHOZ

1

—

4

5

1. The symbols used for timing specifications follow the pattern of t_{(First two letters of functional block)(signal)(state) (reference)(state)}for

inputs and t_{(First two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_LBIXKH1symbolizes local bus

timing (LB) for the input (I) to go invalid (X) with respect to the time the t_LBKclock reference (K) goes high (H), in this case

for clock one(1).

2. All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or rising edge of

LCLK0 (for all other inputs).

3. All signals are measured from NV_DD/2 of the rising/falling edge of LCLK0 to 0.4  NV_DDof the signal in question for 3.3-V

signaling levels.

4. Input timings are measured at the pin.

5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

This figure provides the AC test load for the local bus.

Output

NV_DD/2

Z₀= 50 

R_L= 50 

Figure 30. Local Bus AC Test Load

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

42

Enhanced Local Bus

Figure 31 through Figure 33 show the local bus signals. In what follows, T1, T2, T3, and T4 are internal

clock reference phase signals corresponding to LCCR[CLKDIV].

LCLK0

t

LBIXKH

t

LBIVKH

Input Signals:

LD[0:15]

t

LBIXKH

t

LBIVKH

Input Signal:

LGTA

t

LBIXKH

t

LBKHOV

Output Signals:

LBCTL//LOE/

t

LBKHOZ

t

LBKHOV

Output Signals:

LA[0:25]

Figure 31. Local Bus Signals, Non-Special Signals Only

LCLK0

T1

T3

t_LBKHOZ

t_LBKHOV

GPCM Mode Output Signals:

LCS[0:3]/LWE

t_LBIXKH

t_LBIVKH

UPM Mode Input Signal:

LUPWAIT

t_LBIXKH

t_LBIVKH

Input Signals:

LD[0:15]

t_LBKHOZ

t_LBKHOV

UPM Mode Output Signals:

LCS[0:3]/LBS[0:1]/LGPL[0:5]

Figure 32. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

43

Enhanced Secure Digital Host Controller (eSDHC)

LCLK

T1

T2

T3

T4

t_LBKHOZ

t_LBKHOV

GPCM Mode Output Signals:

LCS[0:3]/LWE

t_LBIXKH

t_LBIVKH

UPM Mode Input Signal:

LUPWAIT

t_LBIXKH

t_LBIVKH

Input Signals:

LD[0:15]

t_LBKHOZ

t_LBKHOV

UPM Mode Output Signals:

LCS[0:3]/LBS[0:1]/LGPL[0:5]

Figure 33. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4

13 Enhanced Secure Digital Host Controller (eSDHC)

This section describes the DC and AC electrical specifications for the eSDHC (SD/MMC/SDIO) interface

of the MPC8308.

The eSDHC controller always uses the falling edge of the SD_CLK in order to drive the

SD_DAT[0:3]/CMD as outputs and rising edge to sample the SD_DAT[0:3], CMD, CD and WP as inputs.

This behavior is true for both full and high speed modes.

13.1 eSDHC DC Electrical Characteristics

This table provides the DC electrical characteristics for the eSDHC (SD/MMC) interface of the device,

compatible with SDHC specifications. The eSDHC NV range is between 3.0 V and 3.6 V.

DD

Table 38. eSDHC interface DC Electrical Characteristics

Characteristic

Symbol

Condition

Min

Max

Unit

Output high voltage

Output low voltage

V_OH

V_OL

I_OH= –8.0 mA

I_OL= 8.0 mA

2.4

—

V

0.5

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

44

Freescale Semiconductor

Enhanced Secure Digital Host Controller (eSDHC)

Table 38. eSDHC interface DC Electrical Characteristics (continued)

Characteristic

Symbol

Condition

Min

Max

Unit

Output low voltage

Input high voltage

Input low voltage

V

I

= 3.2 mA

—

2.1

0.4

NV_DD+ 0.3

0.8

V

OL

V_IH

V_IL

—

–0.3

13.2 eSDHC AC Timing Specifications (Full Speed Mode)

This section describes the AC electrical specifications for the eSDHC (SD/MMC) interface of the device.

This table provides the eSDHC AC timing specifications for full speed mode as defined in Figure 35 and

Figure 36.

Table 39. eSDHC AC Timing Specifications for Full Speed Mode

At recommended operating conditions NV_DD= 3.3 V 300 mV.

Parameter

Symbol ¹

Min

Max

Unit

Notes

SD_CLK clock frequency—full speed mode

SD_CLK clock cycle

f_SFSCK

t_SFSCK

f_SIDCK

0

25

—

MHz

ns

—

2

40

0

SD_CLK clock frequency—identification mode

SD_CLK clock low time

400

—

kHz

ns

t_SFSCKL

t_SFSCKH

t_SFSCKR

15

—

SD_CLK clock high time

—

ns

2

SD_CLK clock rise and fall times

/

5

ns

2

t_SFSCKF

t_SFSIVKH

t_SFSIXKH

t_SFSKHOV

t_SFSKHOX

t_ISU

Input setup times: SD_CMD, SD_DATx to SD_CLK

Input hold times: SD_CMD, SD_DATx to SD_CLK

Output valid: SD_CLK to SD_CMD, SD_DATx valid

Output hold: SD_CLK to SD_CMD, SD_DATx valid

SD card input setup

3

2

—

3

ns

—

ns

2

—

–3

5

2

—

14

—

3

SD card input hold

t_IH

5

3

SD card output valid

t_ODLY

—

0

3

SD card output hold

t_OH

3

Notes:

1

The symbols used for timing specifications herein follow the pattern of t_{(first three letters of functional block)(signal)(state) (reference)(state)}

for inputs and t_{(first three letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_SFSIXKHsymbolizes eSDHC

full mode speed device timing (SFS) input (I) to go invalid (X) with respect to the clock reference (K) going to high (H). Also

t_SFSKHOVsymbolizes eSDHC full speed timing (SFS) for the clock reference (K) to go high (H), with respect to the output (O)

going valid (V) or data output valid time. Note that, in general, the clock reference symbol representation is based on five letters

representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter:

R (rise) or F (fall).

2

3

4

Measured at capacitive load of 40 pF.

For reference only, according to the SD card specifications.

Average, for reference only.

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

45

Enhanced Secure Digital Host Controller (eSDHC)

This figure provides the eSDHC clock input timing diagram.

eSDHC

External Clock

VM

operational mode

t_SFSCKL

t_SFSCKH

t_SFSCK

t_SFSCKF

t_SFSCKR

VM = Midpoint Voltage (NV_DD/2)

Figure 34. eSDHC Clock Input Timing Diagram

13.2.1 Full Speed Output Path (Write)

This figure provides the data and command output timing diagram.

t_SFSCK(Clock Cycle)

SD CLK at the

Driving

MPC8308 Pin

Edge

t_{CLK_DELAY}

SD CLK at

the Card Pin

Sampling

Edge

Output Valid Time: t_SFSKHOV

Output Hold Time: t_SFSKHOX

Output from the

t_SFSCKL

MPC8308 Pins

Input at the

MPC8308 Pins

t_{DATA_DELAY}

t_IH(5 ns)

t_ISU(5 ns)

Figure 35. Full Speed Output Path

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

46

Enhanced Secure Digital Host Controller (eSDHC)

13.2.2 Full Speed Input Path (Read)

This figure provides the data and command input timing diagram.

t_SFSCK(Clock Cycle)

SD CLK at the

MPC8308 Pin

Sampling

Edge

t_{CLK_DELAY}

SD CLK at

the Card Pin

Driving

Edge

t_{DATA_DELAY}

t_ODLY

t_OH

Output from the

SD Card Pins

Input at the

MPC8308 Pins

t_SFSIXKH

t_SFSIVKH

(MPC8308 Input Hold)

Figure 36. Full Speed Input Path

13.3 eSDHC AC Timing Specifications

This table provides the eSDHC AC timing specifications.

Table 40. eSDHC AC Timing Specifications for High Speed Mode

At recommended operating conditions NV_DD= 3.3 V 300 mV.

Parameter

Symbol ¹

Min

Max

Unit

Notes

SD_CLK clock frequency—high speed mode

SD_CLK clock cycle

f_SHSCK

t_SHSCK

f_SIDCK

0

20

0

50

—

MHz

ns

3

—

2

SD_CLK clock frequency—identification mode

SD_CLK clock low time

400

—

kHz

ns

t_SHSCKL

t_SHSCKH

t_SHSCKR/

7

SD_CLK clock high time

7

—

ns

2

SD_CLK clock rise and fall times

—

3

ns

2

t_SHSCKF

Input setup times: SD_CMD, SD_DATx

Input hold times: SD_CMD, SD_DATx

Output delay time: SD_CLK to SD_CMD, SD_DATx valid

Output Hold time: SD_CLK to SD_CMD, SD_DATx invalid

SD Card Input Setup

t_SHSIVKH

t_SHSIXKH

t_SHSKHOV

t_SHSKHOX

t_ISU

3

2

—

ns

2

3

–3

6

SD Card Input Hold

t_IH

2

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

47

Enhanced Secure Digital Host Controller (eSDHC)

Table 40. eSDHC AC Timing Specifications for High Speed Mode (continued)

At recommended operating conditions NV_DD= 3.3 V 300 mV.

Parameter

Symbol ¹

Min

Max

Unit

Notes

SD Card Output Valid

SD Card Output Hold

t_ODLY

t_OH

—

14

—

ns

3

2.5

Notes:

1

The symbols used for timing specifications herein follow the pattern of t_{(first three letters of functional block)(signal)(state) (reference)(state)}

for inputs and t_{(first three letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_SFSIXKHsymbolizes eSDHC

full mode speed device timing (SFS) input (I) to go invalid (X) with respect to the clock reference (K) going to high (H). Also

t_SFSKHOVsymbolizes eSDHC full speed timing (SFS) for the clock reference (K) to go high (H), with respect to the output (O)

going valid (V) or data output valid time. Note that, in general, the clock reference symbol representation is based on five

letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate

letter: R (rise) or F (fall).

2

3

Measured at capacitive load of 40 pF.

For reference only, according to the SD card specifications.

This figure provides the eSDHC clock input timing diagram.

eSDHC

External Clock

VM

operational mode

t_SHSCK

L

t_SHSCKH

t_SHSCK

t_SHSCKF

t_SHSCKR

VM = Midpoint Voltage (NVDD/2)

Figure 37. eSDHC Clock Input Timing Diagram

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

48

Enhanced Secure Digital Host Controller (eSDHC)

13.3.1 High Speed Output Path (Write)

This figure provides the data and command output timing diagram.

t_SHSCK(Clock Cycle)

SD CLK at the

Driving

MPC8308 Pin

Edge

t_{CLK_DELAY}

SD CLK at

the Card Pin

Sampling

Edge

Output Valid Time: t_SHSKHOV

Output Hold Time: t_SHSKHOX

t_SHSCKL

Output from the

MPC8308 Pins

Input at the

SD Card Pins

t_{DATA_DELAY}

t_IH(2 ns)

t_ISU(6 ns)

Figure 38. High Speed Output Path

13.3.2 High Speed Input Path (Read)

This figure provides the data and command input timing diagram.

t_SHSCK(Clock Cycle)

1/2 Cycle

SD CLK at the

MPC8308 Pin

Sampling

Edge

t_{CLK_DELAY}

Driving

Edge

SD CLK at

the Card Pin

t_ODLY

t_OH

t_{DATA_DELAY}

Output from the

SD Card Pins

Input at the

MPC8308 Pins

(MPC8308 Input

t_SHSIXKH

t_SHSIVKH

(MPC8308 Input

Figure 39. High Speed Input Path

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

49

JTAG

14 JTAG

This section describes the DC and AC electrical specifications for the IEEE Std 1149.1™ (JTAG)

interface.

14.1 JTAG DC Electrical Characteristics

This table provides the DC electrical characteristics for the IEEE 1149.1 (JTAG) interface.

Table 41. JTAG Interface DC Electrical Characteristics

Characteristic

Input high voltage

Symbol

Condition

Min

Max

Unit

V_IH

V_IL

—

2.1

NV_DD+ 0.3

V

Input low voltage

Input current

–0.3

0.8

5

I_IN

—

A

V

Output high voltage

Output low voltage

V_OH

V_OL

I_OH= –8.0 mA

I_OL= 8.0 mA

2.4

—

0.5

0.4

V

I

= 3.2 mA

—

V

OL

14.2 JTAG AC Timing Specifications

This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface.

This table provides the JTAG AC timing specifications as defined in Figure 41 through Figure 44.

1

Table 42. JTAG AC Timing Specifications (Independent of SYS_CLK_IN)

At recommended operating conditions (see Table 2).

Parameter

Symbol²

Min

Max

Unit

Note

JTAG external clock frequency of operation

JTAG external clock cycle time

JTAG external clock pulse width measured at 1.4 V

JTAG external clock rise and fall times

TRST assert time

f_JTG

t _JTG

0

33.3

—

2

MHz

ns

—

3

30

15

0

t_JTKHKL

t_JTGR& t_JTGF

t_TRST

ns

25

—

ns

Input setup times:

ns

Boundary-scan data

t_JTDVKH

t_JTIVKH

4

—

4

5

TMS, TDI

Input hold times:

Valid times:

ns

Boundary-scan data

TMS, TDI

t_JTDXKH

t_JTIXKH

10

—

Boundary-scan data

TDO

t_JTKLDV

t_JTKLOV

2

11

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

50

JTAG

1

Table 42. JTAG AC Timing Specifications (Independent of SYS_CLK_IN) (continued)

At recommended operating conditions (see Table 2).

Parameter

Symbol²

Min

Max

Unit

Note

Output hold times:

Boundary-scan data

TDO

t_JTKLDX

t_JTKLOX

2

—

ns

5

JTAG external clock to output high impedance:

Boundary-scan data

TDO

t_JTKLDZ

t_JTKLOZ

2

19

9

ns

5, 6

Notes:

1. All outputs are measured from the midpoint voltage of the falling/rising edge of t_TCLKto the midpoint of the signal in question.

The output timings are measured at the pins. All output timings assume a purely resistive 50-load (see Figure 40).

Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

2. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state) (reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_JTDVKHsymbolizes JTAG device

timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t_JTGclock reference (K)

going to the high (H) state or setup time. Also, t_JTDXKHsymbolizes JTAG timing (JT) with respect to the time data input signals

(D) went invalid (X) relative to the t_JTGclock reference (K) going to the high (H) state. Note that, in general, the clock reference

symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the

latter convention is used with the appropriate letter: R (rise) or F (fall).

3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

4. Non-JTAG signal input timing with respect to t_TCLK

.

5. Non-JTAG signal output timing with respect to t_TCLK

.

6. Guaranteed by design and characterization.

This figure provides the AC test load for TDO and the boundary-scan outputs.

Z₀= 50 

Output

NV_DD/2

R_L= 50 

Figure 40. AC Test Load for the JTAG Interface

This figure provides the JTAG clock input timing diagram.

JTAG

External Clock

VM

t_JTKHKL

VM

t_JTGR

t_JTGF

t_JTG

VM = Midpoint Voltage (NV_DD/2)

Figure 41. JTAG Clock Input Timing Diagram

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

51

JTAG

This figure provides the TRST timing diagram.

TRST

VM

t_TRST

VM = Midpoint Voltage (NV_DD/2)

Figure 42. TRST Timing Diagram

This figure provides the boundary-scan timing diagram.

JTAG

VM

External Clock

t_JTDVKH

t_JTDXKH

Boundary

Data Inputs

Input

Data Valid

t_JTKLDV

t_JTKLDX

Boundary

Data Outputs

Output Data Valid

t_JTKLDZ

Output Data Valid

Boundary

Data Outputs

VM = Midpoint Voltage (NV_DD/2)

Figure 43. Boundary-Scan Timing Diagram

This figure provides the test access port timing diagram.

JTAG

VM

External Clock

t_JTIVKH

t_JTIXKH

Input

TDI, TMS

TDO

Data Valid

t_JTKLOV

t_JTKLOX

Output Data Valid

t_JTKLOZ

Output Data Valid

TDO

VM = Midpoint Voltage (NV_DD/2)

Figure 44. Test Access Port Timing Diagram

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

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52

I²C

15 I²C

2

This section describes the DC and AC electrical characteristics for the I C interface.

2

15.1 I C DC Electrical Characteristics

2

This table provides the DC electrical characteristics for the I C interface.

2

Table 43. I C DC Electrical Characteristics

At recommended operating conditions with NV_DDof 3.3 V 0.3 V.

Parameter

Symbol

Min

Max

Unit Notes

Input high voltage level

Input low voltage level

Low level output voltage

High level output voltage

V_IH

V_IL

0.7  NV_DDNV_DD+ 0.3

V

—

1

–0.3

0

0.3  NV_DD

0.2  NV_DD

V_OL

V_OH

V

0.8 x NV_DDNV_DD+ 0.3

V

—

2

Output fall time from V_IH(min) to V_IL(max) with a bus capacitance from 10

to 400 pF

t

20 + 0.1  C_B

250

ns

I2KLKV

Pulse width of spikes which must be suppressed by the input filter

Capacitance for each I/O pin

t_I2KHKL

C_I

0

50

10

5

ns

pF

A

3

—

Input current, (0 V V_INNV_DD

)

I_IN

Notes:

1. Output voltage (open drain or open collector) condition = 3 mA sink current.

2. C_B= capacitance of one bus line in pF.

3. For information on the digital filter used, see the MPC8308 PowerQUICC II Pro Processor Reference Manual.

2

15.2 I C AC Electrical Specifications

2

This table provides the AC timing parameters for the I C interface.

2

Table 44. I C AC Electrical Specifications

All values refer to V_IH(min) and V_IL(max) levels (see Table 43).

Parameter

Symbol¹

Min

Max Unit

SCL clock frequency

f_I2C

0

400 kHz

Low period of the SCL clock

High period of the SCL clock

t_I2CL

1.3

0.6

100

—

s

ns

s

t_I2CH

Setup time for a repeated START condition

t_I2SVKH

t_I2SXKL

t_I2DVKH

t_I2DXKL

Hold time (repeated) START condition (after this period, the first clock pulse is generated)

Data setup time

Data hold time:

—

I²C bus devices

0 ²

0.9 ³

Fall time of both SDA and SCL signals⁵

t

—

300

ns

I2CF

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

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53

I²C

2

Table 44. I C AC Electrical Specifications (continued)

All values refer to V_IH(min) and V_IL(max) levels (see Table 43).

Parameter

Symbol¹

Min

Max Unit

Setup time for STOP condition

t

0.6

—

s

V

I2PVKH

Bus free time between a STOP and START condition

Noise margin at the LOW level for each connected device (including hysteresis)

Noise margin at the HIGH level for each connected device (including hysteresis)

Notes:

t_I2KHDX

V_NL

1.3

0.1  NV_DD

0.2  NV_DD

V_NH

V

1. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state) (reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_I2DVKHsymbolizes I²C timing (I2)

with respect to the time data input signals (D) reach the valid state (V) relative to the t_I2Cclock reference (K) going to the high

(H) state or setup time. Also, t_I2SXKLsymbolizes I²C timing (I2) for the time that the data with respect to the start condition (S)

went invalid (X) relative to the t_I2Cclock reference (K) going to the low (L) state or hold time. Also, t_I2PVKHsymbolizes I²C timing

(I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the t_I2Cclock reference

(K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R

(rise) or F (fall).

2. The device provides a hold time of at least 300 ns for the SDA signal (referred to the V_IHminof the SCL signal) to bridge the

undefined region of the falling edge of SCL.

3. The maximum t_I2DXKLhas only to be met if the device does not stretch the LOW period (t_I2CL) of the SCL signal.

4. C_B= capacitance of one bus line in pF.

5. The device does not follow the I²C-BUS Specifications, Version 2.1, regarding the t_I2CFAC parameter.

2

This figure provides the AC test load for the I C.

Output

NV_DD/2

Z₀= 50 

R_L= 50 

2

Figure 45. I C AC Test Load

2

This figure shows the AC timing diagram for the I C bus.

SDA

t_I2CF

t_I2CL

t_I2DVKH

t_I2KHKL

t_I2CF

t_I2SXKL

t_I2CR

SCL

t_I2SXKL

t_I2CH

t_I2SVKH

t_I2PVKH

t_I2DXKL

S

Sr

P

S

2

Figure 46. I C Bus AC Timing Diagram

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54

Timers

16 Timers

This section describes the DC and AC electrical specifications for the timers.

16.1 Timers DC Electrical Characteristics

This table provides the DC electrical characteristics for the MPC8308 timers pins, including TIN, TOUT,

and TGATE.

Table 45. Timers DC Electrical Characteristics

Characteristic

Symbol

Condition

Min

Max

Unit

Output high voltage

Output low voltage

Input high voltage

Input low voltage

Input current

V_OH

V_OL

I_OH= –8.0 mA

I_OL= 8.0 mA

2.4

—

V

0.5

V

I

= 3.2 mA

OL

—

0.4

V

OL

V_IH

V_IL

I_IN

—

2.1

–0.3

—

NV_DD+ 0.3

V

0.8

5

V

0 V V_INNV_DD

A

16.2 Timers AC Timing Specifications

This table provides the timers input and output AC timing specifications.

Table 46. Timers Input AC Timing Specifications

Characteristic

Symbol¹

Min

Unit

Timers inputs—minimum pulse width

t_TIWID

20

ns

Notes:

1. Timers inputs and outputs are asynchronous to any visible clock. Timers outputs should be synchronized before use by any

external synchronous logic. Timers inputs are required to be valid for at least t_TIWIDns to ensure proper operation

This figure provides the AC test load for the Timers.

Output

NV_DD/2

Z₀= 50 

R_L= 50 

Figure 47. Timers AC Test Load

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

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55

GPIO

17 GPIO

This section describes the DC and AC electrical specifications for the GPIO of MPC8308

17.1 GPIO DC Electrical Characteristics

This table provides the DC electrical characteristics for the GPIO.

Table 47. GPIO DC Electrical Characteristic

Characteristic

Symbol

Condition

Min

Max

Unit

Output high voltage

Output low voltage

Input high voltage

Input low voltage

Input current

V_OH

V_OL

I_OH= –8.0 mA

I_OL= 8.0 mA

2.4

—

V

0.5

V

I

= 3.2 mA

OL

—

0.4

V

OL

V_IH

V_IL

I_IN

—

2.1

–0.3

—

NV_DD+ 0.3

V

0.8

5

V

0 V  V_IN NV_DD

A

17.2 GPIO AC Timing Specifications

This table provides the GPIO input and output AC timing specifications.

Table 48. GPIO Input AC Timing Specifications

Characteristic

Symbol¹

Min

20

Unit

ns

GPIO inputs—minimum pulse width

t_PIWID

Note:

1. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized

before use by any external synchronous logic. GPIO inputs are required to be valid for at least t_PIWIDns to

ensure proper operation.

This figure provides the AC test load for the GPIO.

NV_DD/2

Output

Z₀= 50 

R_L= 50 

Figure 48. GPIO AC Test Load

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56

IPIC

18 IPIC

This section describes the DC and AC electrical specifications for the external interrupt pins.

18.1 IPIC DC Electrical Characteristics

This table provides the DC electrical characteristics for the external interrupt pins.

Table 49. IPIC DC Electrical Characteristics

Characteristic

Symbol

Condition

Min

Max

Unit

Input high voltage

Input low voltage

Input current

V_IH

V_IL

—

2.1

–0.3

—

NV_DD+ 0.3

V

0.8

5

I_IN

—

A

V

Output high voltage

Output low voltage

V_OH

V_OL

I_{OH =}–8.0 mA

I_OL= 8.0 mA

2.4

—

0.5

0.4

V

I

= 3.2 mA

OL

—

V

OL

18.2 IPIC AC Timing Specifications

This table provides the IPIC input and output AC timing specifications.

Table 50. IPIC Input AC Timing Specifications

Characteristic

Symbol¹

Min

Unit

IPIC inputs—minimum pulse width

t_PIWID

20

ns

Note:

1. IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized

before use by any external synchronous logic. IPIC inputs are required to be valid for at least t_PIWIDns

to ensure proper operation when working in edge triggered mode.

19 SPI

This section describes the DC and AC electrical specifications for the SPI of the device.

19.1 SPI DC Electrical Characteristics

This table provides the DC electrical characteristics for the MPC8308 SPI.

Table 51. SPI DC Electrical Characteristics

Characteristic

Symbol

Condition

Min

Max

Unit

Input high voltage

Input low voltage

Input current

V_IH

V_IL

I_IN

—

2.1

–0.3

—

NV_DD+ 0.3

V

0.8

5

0 V  V_IN NV_DD

A

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

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57

SPI

Table 51. SPI DC Electrical Characteristics (continued)

Characteristic

Symbol

Condition

Min

Max

Unit

Output high voltage

Output low voltage

V_OH

V_OL

I_OH= –8.0 mA

I_OL= 8.0 mA

2.4

—

V

0.5

0.4

V

I

= 3.2 mA

OL

—

OL

19.2 SPI AC Timing Specifications

This table and provide the SPI input and output AC timing specifications.

1

Table 52. SPI AC Timing Specifications

Characteristic

Symbol ²

Min

Max

Unit

SPI outputs valid—master mode (internal clock) delay

SPI outputs hold—master mode (internal clock) delay

SPI outputs valid—slave mode (external clock) delay

SPI outputs hold—slave mode (external clock) delay

SPI inputs—master mode (internal clock) input setup time

SPI inputs—master mode (internal clock) input hold time

SPI inputs—slave mode (external clock) input setup time

SPI inputs—slave mode (external clock) input hold time

Notes:

t_NIKHOV

t_NIKHOX

t_NEKHOV

t_NEKHOX

t_NIIVKH

—

6

—

8.5

—

ns

0.5

2

6

0

4

2

t_NIIXKH

t_NEIVKH

t_NEIXKH

1. Output specifications are measured from the 50% level of the rising edge of SPICLK to the 50% level of the signal.

Timings are measured at the pin.

2. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}

for inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_NIKHOXsymbolizes the

internal timing (NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X).

This figure provides the AC test load for the SPI.

NV_DD/2

Output

Z₀= 50 

R_L= 50 

Figure 49. SPI AC Test Load

Figure 50 through Figure 51 represent the AC timing from Table 52. Note that although the specifications

generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge

is the active edge.

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Freescale Semiconductor

Package and Pin Listings

This figure shows the SPI timing in slave mode (external clock).

SPICLK (input)

t_NEIXKH

t_NEIVKH

Input Signals:

SPIMOSI

(See Note)

t_NEKHOV

Output Signals:

SPIMISO

(See Note)

Note: The clock edge is selectable on SPI.

Figure 50. SPI AC Timing in Slave Mode (External Clock) Diagram

This figure shows the SPI timing in master mode (internal clock).

SPICLK (output)

t_NIIXKH

t_NIIVKH

Input Signals:

SPIMISO

(See Note)

t_NIKHOV

Output Signals:

SPIMOSI

(See Note)

Note: The clock edge is selectable on SPI.

Figure 51. SPI AC Timing in Master Mode (Internal Clock) Diagram

20 Package and Pin Listings

This section details package parameters, pin assignments, and dimensions. The MPC8308 is available in

a moulded array process ball grid array (MAPBGA). For information on the MAPBGA, see Section 20.1,

“Package Parameters for the MPC8308 MAPBGA,” and Section 20.2, “Mechanical Dimensions of the

MPC8308 MAPBGA.”

20.1 Package Parameters for the MPC8308 MAPBGA

The package parameters are as provided in the following list. The package type is 19 mm  19 mm, 473

MAPBGA.

Package outline

Interconnects

19 mm 19 mm

473

Pitch

0.80 mm

Module height (typical)

Solder Balls

1.39 mm

96.5 Sn/ 3.5Ag

0.40 mm

Ball diameter (typical)

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

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59

Package and Pin Listings

20.2 Mechanical Dimensions of the MPC8308 MAPBGA

This figure shows the mechanical dimensions and bottom surface nomenclature of the MAPBGA package.

Figure 52. Mechanical Dimension and Bottom Surface Nomenclature of the MPC8308 MAPBG

Notes:

1. All dimensions are in millimeters.

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Freescale Semiconductor

Package and Pin Listings

2. Dimensions and tolerances per ASME Y14.5M-1994.

3. Maximum solder ball diameter measured parallel to datum A.

4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls.

20.3 Pinout Listings

This table provides the pin-out listing for the MPC8308, MAPBGA package.

Table 53. MPC8308 Pinout Listing

Type

Power

Supply

Signal

Package Pin Number

Note

DDR Memory Controller Interface

MEMC_MDQ[0]

MEMC_MDQ[1]

MEMC_MDQ[2]

MEMC_MDQ[3]

MEMC_MDQ[4]

MEMC_MDQ[5]

MEMC_MDQ[6]

MEMC_MDQ[7]

MEMC_MDQ[8]

MEMC_MDQ[9]

MEMC_MDQ[10]

MEMC_MDQ[11]

MEMC_MDQ[12]

MEMC_MDQ[13]

MEMC_MDQ[14]

MEMC_MDQ[15]

MEMC_MDQ[16]

MEMC_MDQ[17]

MEMC_MDQ[18]

MEMC_MDQ[19]

MEMC_MDQ[20]

MEMC_MDQ[21]

MEMC_MDQ[22]

MEMC_MDQ[23]

MEMC_MDQ[24]

MEMC_MDQ[25]

MEMC_MDQ[26]

V6

Y4

I/O

GV_DDA

GV_DDB

—

AB3

AA3

AA2

AA1

W4

Y2

W3

W1

Y1

W2

U4

U3

V4

U6

T3

T2

R4

R3

P4

N6

P2

P1

N4

N3

N2

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61

Package and Pin Listings

Table 53. MPC8308 Pinout Listing (continued)

Package Pin Number

Type

Power

Supply

Signal

Note

MEMC_MDQ[27]

MEMC_MDQ[28]

MEMC_MDQ[29]

MEMC_MDQ[30]

MEMC_MDQ[31]

MEMC_MDM[0]

MEMC_MDM[1]

MEMC_MDM[2]

MEMC_MDM[3]

MEMC_MDM[8]

MEMC_MDQS[0]

MEMC_MDQS[1]

MEMC_MDQS[2]

MEMC_MDQS[3]

MEMC_MDQS[8]

MEMC_MBA[0]

MEMC_MBA[1]

MEMC_MBA[2]

MEMC_MA0

M6

M2

M3

L2

I/O

O

GV_DDB

GV_DDA

GV_DDB

GV_DDA

GV_DDB

—

L3

AB2

V3

P3

M7

K2

AC3

V1

R1

M1

K1

C3

B2

H4

C2

D2

D3

D4

E4

F4

O

I/O

O

MEMC_MA1

O

MEMC_MA2

O

MEMC_MA3

O

MEMC_MA4

O

MEMC_MA5

O

MEMC_MA6

E2

E1

F2

O

MEMC_MA7

O

MEMC_MA8

O

MEMC_MA9

F3

O

MEMC_MA10

MEMC_MA11

MEMC_MA12

MEMC_MA13

MEMC_MWE

C1

F7

O

G2

G3

D5

B4

O

MEMC_MRAS

O

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62

Package and Pin Listings

Table 53. MPC8308 Pinout Listing (continued)

Package Pin Number

Type

Power

Supply

Signal

Note

MEMC_MCAS

MEMC_MCS[0]

MEMC_MCS[1]

MEMC_MCKE

C5

O

GV_DDB

—

3

B6

C6

O

H3

O

MEMC_MCK [0]

MEMC_MCK [1]

MEMC_MCK [2]

MEMC_MCK [0]

MEMC_MCK [1]

MEMC_MCK [2]

MEMC_MODT[0]

MEMC_MODT[1]

MEMC_MECC[0]

MEMC_MECC[1]

MEMC_MECC[2]

MEMC_MECC[3]

MEMC_MECC[4]

MEMC_MECC[5]

MEMC_MECC[6]

MEMC_MECC[7]

MV_REF

A3

O

—

U2

O

G1

O

A4

O

U1

O

H1

O

A5

O

B5

O

L4

I/O

I

L6

K4

K3

J2

K6

J3

J6

G6

Local Bus Controller Interface

LD0

LD1

LD2

LD3

LD4

LD5

LD6

LD7

LD8

LD9

LD10

U18

V18

I/O

NV_{DDP_K}

8

U16

Y20

AA21

AC22

V17

AB21

Y19

AA20

Y17

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63

Package and Pin Listings

Table 53. MPC8308 Pinout Listing (continued)

Package Pin Number

Type

Power

Supply

Signal

Note

LD11

LD12

LD13

LD14

LD15

LA0

AC21

AB20

V16

I/O

O

NV_{DDP_K}

8

AA19

AC17

AC20

Y16

8

—

4

LA1

O

LA2

U15

O

LA3

V15

O

LA4

AA18

AA17

AC19

AA16

AB18

AC18

V14

O

LA5

O

LA6

O

LA7

O

LA8

O

LA9

O

LA10

LA11

LA12

LA13

LA14

LA15

LA16

LA17

LA18

LA19

LA20

LA21

LA22

LA23

LA24

LA25

LCS[0]

LCS[1]

LCS[2]

O

AB17

AA15

AC16

Y14

O

AC15

U13

O

V13

O

Y13

O

AB15

AA14

AB14

U12

O

V12

O

Y12

O

AC14

AA13

AB13

AA12

O

4

O

4

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64

Package and Pin Listings

Table 53. MPC8308 Pinout Listing (continued)

Package Pin Number

Type

Power

Supply

Signal

Note

LCS[3]

LWE[0] /LFWE0/LBS0

LWE[1]/LBS1

Y11

AB11

AC11

U11

O

NV_{DDP_K}

4

—

4

O

LBCTL

O

LGPL0/LFCLE

LGPL1/LFALE

LGPL2/LOE/LFRE

LGPL3/LFWP

Y10

O

AA10

AB10

AC10

AB9

O

—

4

LGPL4/LGTA/LUPWAIT/

LFRB

I/O

LGPL5

LCLK0

Y9

AC12

DUART

C17

O

NV_{DDP_K}

—

UART_SOUT1/MSRCID0/

LSRCID0

O

I/O

O

NV_DDB

—

UART_SIN1/MSRCID1/

LSRCID1

B18

D17

D18

UART_SOUT2/MSRCID2/

LSRCID2

UART_SIN2/MSRCID3/

LSRCID3

I/O

PEX PHY

C14

TXA

O

I

XPADVDD

XCOREVDD

—

C15

RXA

A13

RXA

B13

I

SD_IMP_CAL_RX

SD_REF_CLK

SD_PLL_TPD

SD_IMP_CAL_TX

SD_PLL_TPA_ANA

SDAVDD_0

SDAVSS_0

A15

I

C12

I

D12

I

F13

O

I

A11

XPADVDD

—

F11

O

I

G12

—

F12

I

—

I²C interface

IIC_SDA1

C9

I/O

NV_DDA

2

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

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65

Package and Pin Listings

Table 53. MPC8308 Pinout Listing (continued)

Package Pin Number

Type

Power

Supply

Signal

Note

IIC_SCL1

A9

D10

I/O

NV_DDA

2

IIC_SDA2/CKSTOP_OUT

IIC_SCL2/CKSTOP_IN

C10

Interrupts

A17

IRQ[0]/MCP_IN

IRQ[1]/MCP_OUT

I

NV_DDB

—

F16

I/O

I

IRQ[2] /CKSTOP_OUT

IRQ[3] / CKSTOP_IN / INTA

B17

A18

JTAG

Y7

TCK

TDI

I

NV_{DDP_K}

—

4

U9

TDO

TMS

TRST

AC5

O

I

3

AA6

4

V8

I

4

TEST

AC6

TEST_MODE

I

NV_{DDP_K}

5

System Control

AA9

HRESET

PORESET

SRESET

I/O

I

NV_{DDP_K}

1

AA8

—

AB7

I/O

Clocks

AC8

SYS_CLK_IN

I

NV_{DDP_K}

NV_DDJ

—

RTC_PIT_CLOCK

AA23

MISC

AA7

QUIESCE

THERM0

O

I

NV_{DDP_K}

—

6

AC7

ETSEC1

B20

TSEC1_COL

TSEC1_CRS

I

NV_DDC

—

3

B21

TSEC1_GTX_CLK

TSEC1_RX_CLK

TSEC1_RX_DV

TSEC1_RXD[3]

TSEC1_RXD[2]

F18

O

I

A22

—

D21

I

C22

I

C21

I

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Package and Pin Listings

Table 53. MPC8308 Pinout Listing (continued)

Package Pin Number

Type

Power

Supply

Signal

Note

TSEC1_RXD[1]

TSEC1_RXD[0]

TSEC1_RX_ER

C20

D20

C23

E23

I

NV_DDC

—

TSEC1_TX_CLK/

TSEC1_GTX_CLK125

TSEC1_TXD[3]/

CFG_RESET_SOURCE[0]

F22

F21

E21

D22

F20

E22

I/O

O

NV_DDC

—

7

TSEC1_TXD[2]/

CFG_RESET_SOURCE[1]

TSEC1_TXD[1]/

CFG_RESET_SOURCE[2]

TSEC1_TXD[0]/

CFG_RESET_SOURCE[3]

TSEC1_TX_EN/

LBC_PM_REF_10

TSEC1_TX_ER/

I/O

LB_POR_CFG_BOOT_ECC

Ethernet Mgmt

TSEC1_MDC

TSEC1_MDIO

A20

O

NV_DDB

—

9

C19

I/O

eSDHC/GTM

SD_CLK/GPIO[16]

SD_CMD/GPIO[17]

D7

G9

A7

O

I/O

I

NV_DDA

—

SD_CD/GTM1_TIN1/

GPIO[18]

SD_WP/GTM1_TGATE1/

GPIO[19]

D8

C8

B8

A8

B9

I

NV_DDA

—

SD_DAT[0]/GTM1_TOUT1/

GPIO[20]

I/O

SD_DAT[1]/GTM1_TOUT2/

GPIO[21]

SD_DAT[2]/GTM1_TIN2/

GPIO[22]

SD_DAT[3]/GTM1_TGATE2/

GPIO[23]

SPI

SPIMOSI/MSRCID4/

LSRCID4

AB5

I/O

NV_{DDP_K}

—

SPIMISO/MDVAL/LDVAL

Y6

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67

Package and Pin Listings

Table 53. MPC8308 Pinout Listing (continued)

Package Pin Number

Type

Power

Supply

Signal

Note

SPICLK

SPISEL

AA5

AB4

I/O

I

NV_{DDP_K}

—

GPIO/ETSEC2

G21

GPIO[0]/TSEC2_COL

GPIO[1]/TSEC2_TX_ER

GPIO[2]/TSEC2_GTX_CLK

GPIO[3]/TSEC2_RX_CLK

GPIO[4]/TSEC2_RX_DV

GPIO[5]/TSEC2_RXD3

GPIO[6]/TSEC2_RXD2

GPIO[7]/TSEC2_RXD1

GPIO[8]/TSEC2_RXD0

GPIO[9]/TSEC2_RX_ER

I/O

NV_DDF

—

K23

H18

G23

J18

J20

H22

H21

H20

J21

GPIO[10]/TSEC2_TX_CLK/

TSEC2_GTX_CLK125

J23

GPIO[11]/TSEC2_TXD3

GPIO[12]/TSEC2_TXD2

GPIO[13]/TSEC2_TXD1

GPIO[14]/TSEC2_TXD0

GPIO[15]/TSEC2_TX_EN

K22

I/O

NV_DDF

—

K20

K18

J17

K21

USB/IEEE1588/GTM

USBDR_PWR_FAULT

USBDR_CLK

P20

R23

R21

P18

T22

T21

U23

U22

T20

R18

V23

V22

R17

I

NV_DDH

—

I

USBDR_DIR

I

USBDR_NXT

I

USBDR_TXDRXD0

USBDR_TXDRXD1

USBDR_TXDRXD2

USBDR_TXDRXD3

USBDR_TXDRXD4

USBDR_TXDRXD5

USBDR_TXDRXD6

USBDR_TXDRXD7

USBDR_PCTL0

I/O

O

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68

Package and Pin Listings

Table 53. MPC8308 Pinout Listing (continued)

Package Pin Number

Type

Power

Supply

Signal

Note

USBDR_PCTL1

USBDR_STP

U20

V21

W23

T18

V20

W21

O

I

NV_DDH

—

TSEC_TMR_CLK/ GPIO[8]

GTM1_TOUT3/ GPIO[9]

GTM1_TOUT4/ GPIO[10]

O

I

TSEC_TMR_TRIG1/

GPIO[11]

TSEC_TMR_TRIG2/

GPIO[12]

Y21

I

NV_DDH

—

TSEC_TMR_GCLK

TSEC_TMR_PP1

L17

L18

L21

L22

L23

M23

O

NV_DDG

—

TSEC_TMR_PP2

TSEC_TMR_PP3/ GPIO[13]

TSEC_TMR_ALARM1

TSEC_TMR_ALARM2/

GPIO[14]

GPIO[7]

TSEC2_CRS/ GPIO[0]

GPIO[1]

M22

IO

I

—

10

—

10

M21

NV_DDG

NV_DDH

M18

GPIO[2]

M20

GPIO[3]

N23

GPIO[4]

N21

GTM1_TGATE3

GTM1_TIN4

GTM1_TGATE4/ GPIO[15]

GTM1_TIN3

GPIO[5]

N20

N18

I

P23

I

P22

I

N17

IO

GPIO[6]

P21

Power and Ground Supplies

AV_DD1

AV_DD2

R6

V10

I

—

NC, No Connection

V_DD

B11, B16, D16

—

I

Y23, H8, H9, H10, H14, H15, H16, J8, J16, K8, K16, L8, L16, M8,

M16, N8, N16, P8, P16, R8, R16, T8, T9, T10, T11, T12, T13, T14,

T15, T16

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Package and Pin Listings

Table 53. MPC8308 Pinout Listing (continued)

Package Pin Number

Type

Power

Supply

Signal

Note

VSS

A2, A21, B1, B19, B23, C4, C16, D6, D19, E3, F8, F15, F17, F23,

G7, G8, G10, G15, G16, G17, G20, H2, H6, H7, H17, H23, J7, J9,

J10, J11, J12, J13, J14, J15, K9, K10, K11, K12, K13, K14, K15,

L1, L7, L9, L10, L11, L12, L13, L14, L15, L20, M4, M9, M10, M11,

M12, M13, M14, M15, N9, N10, N11, N12, N13, N14, N15, P6, P7,

P9, P10, P11, P12, P13, P14, P15, R2, R7, R9, R10, R11, R12,

R13, R14, R15, R22, T6, T7, U8, U17, U21, V2, V7, V9, V11, W20,

Y8, Y15, AA4, AB1, AB6, AB12, AB19, AC2, AC9, AC23

I

—

NV_DDA

NV_DDB

NV_DDC

NV_DDF

NV_DDG

NV_DDH

NV_DDJ

B7, B10, C7, D9, F9

A16, A19, C18

I

—

A23, B22, D23, E20, G18

G22, J22, K17

M17, N22

P17, R20, T17, T23, W22, Y22

AB23, AA22

NV_{DDP_K}

U10, U14, Y5, Y18, AA11, AB8, AB16, AB22, AC4,

AC13

GV_DD

XPADVDD

A1, A6, B3, D1, F1, F6, G4, J1, J4, K7, N1, N7, T1, T4, U7, Y3, AC1

D15, F10, F14

I

—

XPADVSS

A10, B15, D14, G13, G14, H12

A14, B12, C13

XCOREVDD

XCOREVSS

Notes:

A12, B14, C11, D11, D13, G11, H11, H13

1. This pin is an open drain signal. A weak pull-up resistor (1 k) should be placed on this pin to NV_DD

2. This pin is an open drain signal. A weak pull-up resistor (2–10 k) should be placed on this pin to NV_DD

3. This output is actively driven during reset rather than being three-stated during reset.

4. This pin has weak internal pull-up that is always enabled.

5. This pin must always be tied to VSS.

6. Internal thermally sensitive resistor, resistor value varies linearly with temperature. Useful for determining the junction

temperature.

7. The LB_POR_CFG_BOOT_ECC is sampled only during the PORESET negation. This pin with an internal pull down resistor

enables the ECC by default. To disable the ECC an external strong pull up resistor or a buffer released to high impedance is

needed.

8. This pin has weak internal pull-down that is always enabled

9. A weak pull-up resistor (2–10 k) should be placed on this pin to NV_DD

10. Configure SICRH register to program the pin as GPIO. Refer to MPC8308 reference manual for more details.

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Freescale Semiconductor

Clocking

21 Clocking

This figure shows the internal distribution of clocks within the device.

e300 Core

MPC8308

x M¹

e300

PLL

csb_clk

MCK[0:2]

DDR

clk tree

DDR

Memory

Device

Clock

x L²

Divider

/2

ddr_clk

lbc_clk

System Clk

PLL

Gen

ref fb

/n

24–66 MHz

Local

Bus

Memory

Device

LBC

Clock

Divider

SYS_CLK_IN

USBDR_CLK

SD_CLK

USB

eTSEC1

TSEC1_RX_CLK

eSHDC

PCI Express

Protocol

Converter

TSEC1_TX_CLK/

TSEC1_GTX_CLK125

PCVTR Mux

RTC

SD_REF_CLK

SD_REF_CLK_B

+

-

RTC_PIT_CLOCK

(32 KHz)

SerDes PHY

PLL

Sys_ref

125/100 MHz

1

2

Multiplication factor M = 1, 1.5, 2, 2.5, and 3. Value is decided by RCWLR[COREPLL].

Multiplication factor L = 2, 3, 4, 5 and 6. Value is decided by RCWLR[SPMF].

Figure 53. MPC8308 Clock Subsystem

The following external clock sources are utilized on the MPC8308:

•

System clock (SYS_CLK_IN)

Ethernet Clock (TSEC1_RX_CLK/TSEC1_TX_CLK/TSEC1_GTX_CLK125 for eTSEC)

SerDes PHY clock

eSHDC clock (SD_CLK)

For more information, see the SerDes chapter in the MPC8308 PowerQUICC II Pro Processor

Reference Manual.

All clock inputs can be supplied using an external canned oscillator, a clock generation chip, or some other

source that provides a standard CMOS square wave input.

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71

Clocking

21.1 System Clock Domains

The primary clock input (SYS_CLK_IN) frequency is multiplied up by the system phase-locked loop

(PLL) and the clock unit to create three major clock domains:

•

The coherent system bus clock (csb_clk)

The internal clock for the DDR controller (ddr_clk)

The internal clock for the local bus interface unit (lbc_clk)

The csb_clk frequency is derived as follows:

csb_clk = [SYS_CLK_IN] × SPMF

The csb_clk serves as the clock input to the e300 core. A second PLL inside the core multiplies up the

csb_clk frequency to create the internal clock for the core (core_clk). The system and core PLL multipliers

are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL), which is

loaded at power-on reset or by one of the hard-coded reset options. For more information, see the Reset

Clock Configuration chapter in the MPC8308 PowerQUICC II Pro Processor Reference Manual.

The DDR SDRAM memory controller will operate with a frequency equal to twice the frequency of

csb_clk. Note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR

clock divider (2) to create the differential DDR memory bus clock outputs (MCK and MCK). However,

the data rate is the same frequency as ddr_clk.

The local bus memory controller will operate with a frequency equal to the frequency of csb_clk. Note that

lbc_clk is not the external local bus frequency; lbc_clk passes through the LBC clock divider to create the

external local bus clock outputs (LSYNC_OUT and LCLK0:2). The LBC clock divider ratio is controlled

by LCCR[CLKDIV]. For more information, see the Reset Clock Configuration chapter in the MPC8308

PowerQUICC II Pro Processor Reference Manual.

In addition, some of the internal units may be required to be shut off or operate at lower frequency than

the csb_clk frequency. These units have a default clock ratio that can be configured by a memory mapped

register after the device comes out of reset. Table 54 specifies which units have a configurable clock

frequency. For more information, see Reset Clock Configuration chapter in the MPC8308 PowerQUICC

II Pro Processor Reference Manual.

Table 54. Configurable Clock Units

Unit

Default Frequency

Options

eTSEC1,eTSEC2

I²C

csb_clk/3

csb_clk

Off, csb_clk, csb_clk/2, csb_clk/3

Off, csb_clk,csb_clk/2, csb_clk/3

Off, csb_clk,csb_clk/2,csb_clk/3

Off, csb_clk

DMA complex

PCIEXP

eSDHC

Off, csb_clk, csb_clk/2, csb_clk/3

USB

NOTE

The clock ratios of these units must be set before they are accessed.

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72

Freescale Semiconductor

Clocking

This table provides the operating frequencies for the device under recommended operating conditions

(Table 2).

Table 55. Operating Frequencies for MPC8308

Characteristic¹

Maximum Operating Frequency

Unit

e300 core frequency (core_clk)

Coherent system bus frequency (csb_clk)

DDR2 memory bus frequency (MCK)²

Local bus frequency (LCLK0)³

Notes:

400

133

66

MHz

1. The SYS_CLK_IN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting csb_clk,

MCK, LCLK0, and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies.

2. The DDR data rate is 2x the DDR memory bus frequency.

3. The local bus frequency is 1/2, 1/4, or 1/8 of the lbc_clk frequency (depending on LCCR[CLKDIV]) which is in turn, 1x or 2x

the csb_clk frequency (depending on RCWL[LBCM]).

21.2 System PLL Configuration

The system PLL is controlled by the RCWL[SPMF] parameter. This table shows the multiplication factor

encodings for the system PLL.

Table 56. System PLL Ratio

RCWL[SPMF]

csb_clk: SYS_CLK_IN

0000

0001

Reserved

2 : 1

0010

0011

3 : 1

0100

4 : 1

0101

5 : 1

0110–1111

Reserved

As described in Section 21, “Clocking,” the LBCM, DDRCM, and SPMF parameters in the reset

configuration word low select the ratio between the primary clock input (SYS_CLK_IN) and the internal

coherent system bus clock (csb_clk). This table shows the expected frequency values for the CSB

frequency for select csb_clk to SYS_CLK_IN ratios.

Table 57. CSB Frequency Options

Input Clock Frequency (MHz)

SPMF

csb_clk :Input Clock Ratio

25

33.33

66.67

0010

0100

0101

2:1

4:1

5:1

133

125

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73

Thermal

21.3 Core PLL Configuration

RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300

core clock (core_clk). This table shows the encodings for RCWL[COREPLL]. COREPLL values that are

not listed in this table should be considered as reserved.

NOTE

Core VCO frequency = core frequency VCO divider. The VCO divider,

which is determined by RCWLR[COREPLL], must be set properly so that

the core VCO frequency is in the range of 400–800 MHz.

Table 58. e300 Core PLL Configuration

RCWL[COREPLL]

core_clk: csb_clk Ratio¹

VCO Divider (VCOD)²

0–1

2–5

6

nn

0000

0

PLL bypassed

(PLL off, csb_clk clocks core directly)

11

00

nnnn

0001

0010

0011

n

0

1

0

1

0

n/a

1:1

n/a

2

4

8

2

4

8

2

4

8

2

4

8

2

4

8

01

1:1

10

1:1

00

1.5:1

2:1

01

10

00

01

2:1

10

2:1

00

2.5:1

3:1

01

10

00

01

3:1

10

3:1

Note:

1

2

For any core_clk:csb_clk ratios, the core_clk must not exceed its maximum operating frequency of 400 MHz.

Core VCO frequency = core frequency  VCO divider. Note that VCO divider has to be set properly so that the

core VCO frequency is in the range of 400–800 MHz.

22 Thermal

This section describes the thermal specifications of the device.

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

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74

Thermal

22.1 Thermal Characteristics

This table provides the package thermal characteristics for the 473, 19  19 mm MAPBGA.

Table 59. Package Thermal Characteristics for MAPBGA

Characteristic

Board Type

Symbol

Value

Unit

Note

Junction to Ambient Natural Convection

Junction to Ambient (@200 ft/min)

Junction to Board

Single layer board (1s)

Four layer board (2s2p)

Single layer board (1s)

Four layer board (2s2p)

—

R_JA

R_JMA

R_JB

R_JC

_JT

42

27

35

24

17

9

°C/W

1, 2

1, 2, 3

1, 3

4

Junction to Case

—

5

Junction to Package Top

Notes:

Natural Convection

2

6

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal

resistance.

2. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.

3. Per JEDEC JESD51-6 with the board horizontal.

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method

1012.1).

6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature

per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

22.2 Thermal Management Information

For the following sections, P = (V  I ) + P , where P is the power dissipation of the I/O drivers.

D

DD

I/O

22.2.1 Estimation of Junction Temperature with Junction-to-Ambient

Thermal Resistance

An estimation of the chip junction temperature, T , can be obtained from the equation:

J

T = T + (R

 P )

D

J

A

JA

where:

T = junction temperature (C)

J

T = ambient temperature for the package (C)

A

R

= junction-to-ambient thermal resistance (C/W)

JA

P = power dissipation in the package (W)

D

The junction-t-ambient thermal resistance is an industry standard value that provides a quick and easy

estimation of thermal performance. As a general statement, the value obtained on a single layer board is

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

75

Thermal

appropriate for a tightly packed printed-circuit board. The value obtained on the board with the internal

planes is usually appropriate if the board has low power dissipation and the components are well separated.

Test cases have demonstrated that errors of a factor of two (in the quantity T – T ) are possible.

J

A

22.2.2 Estimation of Junction Temperature with Junction-to-Board

Thermal Resistance

The thermal performance of a device cannot be adequately predicted from the junction-to-ambient thermal

resistance. The thermal performance of any component is strongly dependent on the power dissipation of

surrounding components. In addition, the ambient temperature varies widely within the application. For

many natural convection and especially closed box applications, the board temperature at the perimeter

(edge) of the package is approximately the same as the local air temperature near the device. Specifying

the local ambient conditions explicitly as the board temperature provides a more precise description of the

local ambient conditions that determine the temperature of the device.

At a known board temperature, the junction temperature is estimated using the following equation:

T = T + (R

 P )

D

J

B

JB

where:

T = junction temperature (C)

J

T = board temperature at the package perimeter (C)

B

R

= junction-to-board thermal resistance (C/W) per JESD51–8

JB

P = power dissipation in the package (W)

D

When the heat loss from the package case to the air can be ignored, acceptable predictions of junction

temperature can be made. The application board should be similar to the thermal test condition: the

component is soldered to a board with internal planes.

22.2.3 Experimental Determination of Junction Temperature

To determine the junction temperature of the device in the application after prototypes are available, the

thermal characterization parameter ( ) can be used to determine the junction temperature with a

JT

measurement of the temperature at the top center of the package case using the following equation:

T = T + (  P )

J

T

JT

D

where:

T = junction temperature (C)

J

T = thermocouple temperature on top of package (C)

T



= thermal characterization parameter (C/W)

JT

P = power dissipation in the package (W)

D

The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T

thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so

that the thermocouple junction rests on the package. A small amount of epoxy is placed over the

thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire

is placed flat against the package case to avoid measurement errors caused by cooling effects of the

thermocouple wire.

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76

Freescale Semiconductor

System Design Information

23 System Design Information

This section provides electrical and thermal design recommendations for successful application of the

device

23.1 System Clocking

The device includes two PLLs.

1. The platform PLL generates the platform clock from the externally supplied SYS_CLK_IN input.

The frequency ratio between the platform and SYS_CLK_IN is selected using the platform PLL

ratio configuration bits as described in Section 21.2, “System PLL Configuration.”

2. The e300 core PLL generates the core clock as a slave to the platform clock. The frequency ratio

between the e300 core clock and the platform clock is selected using the e300 PLL ratio

configuration bits as described in Section 21.3, “Core PLL Configuration.”

23.2 PLL Power Supply Filtering

Each of the PLLs listed above is provided with power through independent power supply pins (AV

for

DD1

core PLL and AV

for the platform PLL). The AV level should always be equivalent to V , and

DD2

DD DD

preferably these voltages are derived directly from V through a low pass filter scheme such as the

DD

following.

There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to

provide independent filter circuits as illustrated in Figure 54, one to each of the two AV pins. By

DD

providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the

other is reduced.

This circuit is intended to filter noise in the PLLs’ resonant frequency range from a 500 kHz to 10 MHz

range. It should be built with surface mount capacitors with minimum effective series inductance (ESL).

Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook

of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a

single large value capacitor.

Each circuit should be placed as close as possible to the specific AV pin being supplied to minimize

DD

noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AV

pin, which is on the periphery of package, without the inductance of vias.

DD

This figure shows the PLL power supply filter circuits.

10

V_DD

AV_DD1and AV_DD2

2.2 µF

Low ESL Surface Mount Capacitors

Figure 54. PLL Power Supply Filter Circuit

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77

System Design Information

23.3 Decoupling Recommendations

Due to large address and data buses, and high operating frequencies, the device can generate transient

power surges and high frequency noise in its power supply, especially while driving large capacitive loads.

This noise must be prevented from reaching other components in the MPC8308 system, and the MPC8308

itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system

designer place at least one decoupling capacitor at each V , NV , GV and LV pin of the device.

DD

These decoupling capacitors should receive their power from separate V , NV , GV , LV , and

DD

V

power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed

SS

directly under the device using a standard escape pattern. Others may surround the part.

These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)

capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.

In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,

feeding the V , NV , GV , LV planes, to enable quick recharging of the smaller chip capacitors.

DD

These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick

response time necessary. They should also be connected to the power and ground planes through two vias

to minimize inductance. Suggested bulk capacitors—100 to 330 µF (AVX TPS tantalum or Sanyo

OSCON). However, customers should work directly with their power regulator vendor for best values and

types of bulk capacitors.

23.4 Connection Recommendations

To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal

level. Unused active low inputs should be tied to NV , GV , LV as required. Unused active high

DD

inputs should be connected to VSS. All NC (no-connect) signals must remain unconnected.

Power and ground connections must be made to all external V , NV , AV , AV , GV , LV

DD

DD1

DD2

DD

and V pins of the device.

SS

23.5 Output Buffer DC Impedance

The device drivers are characterized over process, voltage, and temperature. For all buses, the driver is a

2

push-pull single-ended driver type (open drain for I C, MDIO and HRESET)

To measure Z for the single-ended drivers, an external resistor is connected from the chip pad to NV

0

DD

or V . Then, the value of each resistor is varied until the pad voltage is NV /2 (Figure 55). The output

SS

DD

impedance is the average of two components, the resistances of the pull-up and pull-down devices. When

data is held high, SW1 is closed (SW2 is open), and R is trimmed until the voltage at the pad equals

P

NV /2. R then becomes the resistance of the pull-up devices. R and R are designed to be close to each

DD

P

N

other in value. Then, Z = (R + R )/2.

0

P

N

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System Design Information

NV_DD

R_N

SW2

SW1

Pad

Data

R_P

VSS

Figure 55. Driver Impedance Measurement

The value of this resistance and the strength of the driver’s current source can be found by making two

measurements. First, the output voltage is measured while driving logic 1 without an external differential

termination resistor. The measured voltage is V = R

while driving logic 1 with an external precision differential termination resistor of value R . The

 I

. Second, the output voltage is measured

1

source

term

measured voltage is V = (1/(1/R + 1/R ))  I

. Solving for the output impedance gives R

=

2

1

2

source

R

 (V /V – 1). The drive current is then I

= V /R

.

term

1

2

source

1

source

This table summarizes the signal impedance targets. The driver impedance are targeted at minimum V

,

DD

nominal NV , 105C.

DD

Table 60. Impedance Characteristics

Local Bus, Ethernet, DUART, Control,

Configuration, Power Management

Impedance

DDR DRAM Symbol

Unit

R

42 Target

20 Target

Z₀



N

P

Note: Nominal supply voltages. See Table 2, T_j= 105C.

23.6 Configuration Pin Muxing

The device provides the user with power-on configuration options which can be set through the use of

external pull-up or pull-down resistors of 4.7 K on certain output pins (see customer visible

configuration pins). These pins are generally used as output only pins in normal operation.

While PORESET is asserted however, these pins are treated as inputs. The value presented on these pins

while PORESET is asserted, is latched when PORESET deasserts, at which time the input receiver is

disabled and the I/O circuit takes on its normal function. Careful board layout with stubless connections

to these pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should

minimize the disruption of signal quality or speed for output pins thus configured.

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Ordering Information

23.7 Pull-Up Resistor Requirements

The device requires high resistance pull-up resistors (10 k is recommended) on open drain type pins

2

including I C, Ethernet management MDIO, HRESET and IPIC (integrated programmable interrupt

controller).

Correct operation of the JTAG interface requires configuration of a group of system control pins as

demonstrated in Figure 56. Care must be taken to ensure that these pins are maintained at a valid deasserted

state under normal operating conditions because most have asynchronous behavior and spurious assertion,

which give unpredictable results.

24 Ordering Information

This section presents ordering information for the devices discussed in this document, and it shows an

example of how the parts are marked. Ordering information for the devices fully covered by this document

is provided in Section 24.1, “Part Numbers Fully Addressed by This Document.”

24.1 Part Numbers Fully Addressed by This Document

This table provides the Freescale part numbering nomenclature for the MPC8308 family. Note that the

individual part numbers correspond to a maximum processor core frequency. For available frequencies,

contact your local Freescale sales office. In addition to the maximum processor core frequency, the part

numbering scheme also includes the maximum effective DDR memory speed. Each part number also

contains a revision code which refers to the die mask revision number.

Table 61. Part Numbering Nomenclature

MPC nnnn

VM

AD

D

A

C

Product

Code

Part

Identifier

Temperature

Range^1,4

e300 Core

Frequency³

DDR

Frequency

Revision

Level

Package²

MPC

8308

Blank = 0 to 105C VM = Pb-free 473 MAPBGA AD = 266 MHz D = 266 MHz Contact local

AF = 333 MHz

Freescale

C = –40 to 105C ZQ = Pb 473 MAPBGA

AG = 400 MHz

sales office

Notes:

1. Contact local Freescale office on availability of parts with C temperature range.

2. See Section 20, “Package and Pin Listings,” for more information on available package types.

3. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this

specification support all core frequencies. Additionally, parts addressed by Part Number Specifications may support other

maximum core frequencies

4. Minimum temperature is specified with T_A; Maximum temperature is specified with T_J

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Ordering Information

24.2 Part marking

Parts are marked as in the example shown in this figure.

MPCnnnnCVMADDA

core/platform MHZ

ATWLYYWW

CCCCC

*MMMMM

YWWLAZ

PBGA

Notes:

ATWLYYWW is the traceability code.

CCCCC is the country code.

MMMMM is the mask number.

YWWLAZ is the assembly traceability code.

Figure 56. Freescale Part Marking for PBGA Devices

This table lists the SVR settings.

Table 62. SVR settings

Package

Device

Revision

SVR

MPC8308

1.1

1.0

MAPBGA

0x8101 _0111

0x8101 _0110

Note: PVR = 8085_0020 for the device.

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Revision history

25 Revision history

This table summarizes a revision history for this document.

Table 63. Revision history

Rev.

Number

Date

Substantive Change(s)

4

12/2014 • In Table 23 and Table 24, V_IL(min) is replaced with V_IL(max) and V_IH(max) is replaced with V_IL(min)

• In Table 25, Symbol t_SKRGTis updated

• Updated Figure 11

• In Table 53, removed TSEC2_TMR_RX_ESFD, TSEC2_TMR_TX_ESFD, TSEC1_TMR_RX_ESFD,

TSEC1_TMR_TX_ESFD signals

• In Table 53, added INTA signal

• In Table 53, added note 9 and note 10

• In Table 53, updated the note for eTSEC1_MDIO

• In Table 53, updated note of pin M22, N17 and P21

• In Table 57, removed 167 MHz Input Clock Frequency

• Updated Figure 53

• Updated Table 61

• Updated Table 62

3

2

10/2011 • In Section 2.1.4, “Power sequencing,” changed description.

• In Table 53, updated GPIOs pins as I/O.

• In Table 54, removed PCI Express = csb_clk/2 and csb_clk/3 options.

• In Table 61, added note 4.

02/2011 • Added NV_DDJto Note-7 in Table 1.

• In Table 2,

Added Note-2

Added NV_DDJto Note-3

Added “Extended Temperature range from -40 to 105 C, in the last row of the table

Changed “characteristic name Junction temperature” to “Operating temperature range”

• In Table 4, Note-3, changed ambient temperature to junction temperature, T_J= 105 C

• In Table 18,

t_DDKHCSchanged from 3.15ns to 2.5ns

t_DDKHMPand t_DDKHMEvalues updated

• In Figure 6, corrected t_DDKHMP& t_DDKHMEwaveform

• In Table 53,

Y23 Package Pin Number changed from NC to V_DDsignal group

TSEC2_CRS is muxed with GPIO[0], shown as TSEC2_CRS/ GPIO[0]

• In Table 58, note-1, core_clk maximum operating frequency 333 MHz replaced with 400 MHz

1

06/2010 • In Table 4, T_A= 105 replaced with T_J= 105

• In Table 8, f_{SYS_CLK_IN}(Max) = 66 replaced with 66.67 and t_{SYS_CLK_IN}(Min) = 15.15 replaced with 15

• In Table 53, TSEC1_TMR_RX_ESFD replaced with TSEC2_TMR_RX_ESFD

TSEC1_TMR_TX_ESFD replaced with TSEC2_TMR_TX_ESFD

TSEC0_TMR_RX_ESFD replaced with TSEC1_TMR_RX_ESFD

TSEC0_TMR_TX_ESFD replaced with TSEC1_TMR_TX_ESFD

• In Table 56, rows from 1000 to 1111 removed

• In Table 57, SPMF 5:1 Option 167 MHz added.

0

05/2010 Initial release

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Information in this document is provided solely to enable system and software

implementers to use Freescale Semiconductor products. There are no express or

implied copyright licenses granted hereunder to design or fabricate any integrated

circuits or integrated circuits based on the information in this document.

Freescale Semiconductor reserves the right to make changes without further notice to

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Freescale Semiconductor assume any liability arising out of the application or use of

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limitation consequential or incidental damages. “Typical” parameters which may be

provided in Freescale Semiconductor data sheets and/or specifications can and do

vary in different applications and actual performance may vary over time. All operating

parameters, including “Typicals” must be validated for each customer application by

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Freescale, the Freescale logo, CodeWarrior, ColdFire, PowerQUICC,

StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc.

Reg. U.S. Pat. & Tm. Off. CoreNet, QorIQ, QUICC Engine, and VortiQa are

trademarks of Freescale Semiconductor, Inc. All other product or service

names are the property of their respective owners. The Power Architecture

and Power.org word marks and the Power and Power.org logos and related

marks are trademarks and service marks licensed by Power.org. IEEE 1588

and 1149.1 are registered trademarks of the Institute of Electrical and

Electronics Engineers, Inc. (IEEE). This product is not endorsed or

approved by the IEEE.

Document Number: MPC8308EC

Rev. 4

12/2014


型号：	MPC8308VMADDA
厂家：	NXP
描述：	PowerQUICC, Power Architecture SoC 266MHz, DDR2, PCIe, GbE, USB, 0 to 105C, Rev 1.1 PC 双倍数据速率外围集成电路
文件：	总95页 (文件大小：959K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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