MPC8360ZUALDGA_技术文档

Document Number: MPC8360EEC

Rev. 5, 09/2011

Freescale Semiconductor

Technical Data

MPC8360E/MPC8358E

PowerQUICC II Pro Processor

Revision 2.x TBGA Silicon

Hardware Specifications

Contents

This document provides an overview of the MPC8360E/58E

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2. Electrical Characteristics . . . . . . . . . . . . . . . . . . 7

3. Power Characteristics . . . . . . . . . . . . . . . . . . . 12

4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . 14

5. RESET Initialization . . . . . . . . . . . . . . . . . . . . 16

6. DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . 18

7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8. UCC Ethernet Controller: Three-Speed Ethernet,

MII Management . . . . . . . . . . . . . . . . . . . . . . . 25

9. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

10. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

11. I²C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

12. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

13. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

14. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

15. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

16. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

17. TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

18. HDLC, BISYNC, Transparent, and Synchronous

UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

19. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

20. Package and Pin Listings . . . . . . . . . . . . . . . . . 63

21. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

22. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

23. System Design Information . . . . . . . . . . . . . . . 96

24. Ordering Information . . . . . . . . . . . . . . . . . . . . 99

25. Document Revision History . . . . . . . . . . . . . 100

PowerQUICC II Pro processor revision 2.x TBGA features, including a

block diagram showing the major functional components. This device is

a cost-effective, highly integrated communications processor that

addresses the needs of the networking, wireless infrastructure, and

telecommunications markets. Target applications include next generation

DSLAMs, network interface cards for 3G base stations (Node Bs),

routers, media gateways, and high end IADs. The device extends current

PowerQUICC II Pro offerings, adding higher CPU performance,

additional functionality, faster interfaces, and robust interworking

between protocols while addressing the requirements related to

time-to-market, price, power, and package size. This device can be used

for the control plane and also has data plane functionality.

For functional characteristics of the processor, refer to the MPC8360E

PowerQUICC II Pro Integrated Communications Processor Reference

Manual, Rev. 3.

To locate any updates for this document, refer to the MPC8360E product

summary page on our website listed on the back cover of this document

or contact your Freescale sales office.

1

Overview

This section describes a high-level overview including features and

general operation of the MPC8360E/58E PowerQUICC II Pro processor.

A major component of this device is the e300 core, which includes

32 Kbytes of instruction and data cache and is fully compatible with the

Power Architecture™ 603e instruction set. The new QUICC Engine

module provides termination, interworking, and switching between a

wide range of protocols including ATM, Ethernet, HDLC, and POS. The QUICC Engine module’s enhanced interworking eases

the transition and reduces investment costs from ATM to IP based systems. The other major features include a dual DDR

SDRAM memory controller for the MPC8360E, which allows equipment providers to partition system parameters and data in

an extremely efficient way, such as using one 32-bit DDR memory controller for control plane processing and the other for data

plane processing. The MPC8358E has a single DDR SDRAM memory controller. The MPC8360E/58E also offers a 32-bit PCI

controller, a flexible local bus, and a dedicated security engine.

This figure shows the MPC8360Eblock diagram.

System Interface Unit

(SIU)

e300 Core

Security Engine

32KB

Memory Controllers

GPCM/UPM/SDRAM

I-Cache

D-Cache

DDRC1

DDRC2

Classic G2 MMUs

32/64 DDR Interface Unit

PCI Bridge

Power

FPU

PCI

Management

Local

JTAG/COP

Timers

Local Bus

Bus Arbitration

DUART

QUICC Engine Module

Multi-User

Accelerators

RAM

Baud Rate

Generators

Serial DMA

&

2 Virtual

DMAs

Dual I2C

Dual 32-Bit RISC CP

4 Channel DMA

Interrupt Controller

Protection & Configuration

System Reset

Parallel I/O

Time Slot Assigner

Serial Interface

Clock Synthesizer

8 MII/

RMII

2 GMII/

RGMII/TBI/RTBI

2 UTOPIA/POS

(124 MPHY)

8 TDM Ports

Figure 1. MPC8360E Block Diagram

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

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This figure shows the MPC8358E block diagram.

System Interface Unit

(SIU)

e300 Core

Security Engine

32KB

Memory Controllers

GPCM/UPM/SDRAM

I-Cache

D-Cache

Classic G2 MMUs

DDRC

PCI

32/64 DDR Interface Unit

PCI Bridge

Power

FPU

Management

Local

JTAG/COP

Timers

Local Bus

Bus Arbitration

DUART

QUICC Engine Module

Multi-User

Accelerators

RAM

Baud Rate

Generators

Serial DMA

&

2 Virtual

DMAs

Dual I2C

Dual 32-Bit RISC CP

4 Channel DMA

Interrupt Controller

Protection & Configuration

System Reset

Parallel I/O

Time Slot Assigner

Serial Interface

Clock Synthesizer

6 MII/

RMII

2 GMII/

RGMII/TBI/RTBI

1 UTOPIA/POS

(31/124 MPHY)

4 TDM Ports

Figure 2. MPC8358E Block Diagram

Major features of the MPC8360E/58E are as follows:

•

e300 PowerPC processor core (enhanced version of the MPC603e core)

— Operates at up to 667 MHz (for the MPC8360E) and 400 MHz (for the MPC8358E)

— High-performance, superscalar processor core

— Floating-point, integer, load/store, system register, and branch processing units

— 32-Kbyte instruction cache, 32-Kbyte data cache

— Lockable portion of L1 cache

— Dynamic power management

— Software-compatible with the Freescale processor families implementing the Power Architecture™ technology

QUICC Engine unit

•

— Two 32-bit RISC controllers for flexible support of the communications peripherals, each operating up to

500 MHz (for the MPC8360E) and 400 MHz (for the MPC8358E)

— Serial DMA channel for receive and transmit on all serial channels

— QUICC Engine module peripheral request interface (for SEC, PCI, IEEE Std. 1588™)

— Eight universal communication controllers (UCCs) on the MPC8360E and six UCCs on the MPC8358E

supporting the following protocols and interfaces (not all of them simultaneously):

–

IEEE 1588 protocol supported

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

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–

10/100 Mbps Ethernet/IEEE Std. 802.3™ CDMA/CS interface through a media-independent interface (MII,

RMII, RGMII)

1

1000 Mbps Ethernet/IEEE 802.3 CDMA/CS interface through a media-independent interface (GMII, RGMII,

TBI, RTBI) on UCC1 and UCC2

–

9.6-Kbyte jumbo frames

ATM full-duplex SAR, up to 622 Mbps (OC-12/STM-4), AAL0, AAL1, and AAL5 in accordance ITU-T

I.363.5

–

ATM AAL2 CPS, SSSAR, and SSTED up to 155 Mbps (OC-3/STM-1) Mbps full duplex (with 4 CPS packets

per cell) in accordance ITU-T I.366.1 and I.363.2

ATM traffic shaping for CBR, VBR, UBR, and GFR traffic types compatible with ATM forum TM4.1 for up

to 64-Kbyte simultaneous ATM channels

ATM AAL1 structured and unstructured circuit emulation service (CES 2.0) in accordance with ITU-T I.163.1

and ATM Forum af-vtoa-00-0078.000

IMA (Inverse Multiplexing over ATM) for up to 31 IMA links over 8 IMA groups in accordance with the ATM

forum AF-PHY-0086.000 (Version 1.0) and AF-PHY-0086.001 (Version 1.1)

–

ATM Transmission Convergence layer support in accordance with ITU-T I.432

ATM OAM handling features compatible with ITU-T I.610

PPP, Multi-Link (ML-PPP), Multi-Class (MC-PPP) and PPP mux in accordance with the following RFCs:

1661, 1662, 1990, 2686, and 3153

–

IP support for IPv4 packets including TOS, TTL, and header checksum processing

Ethernet over first mile IEEE 802.3ah

Shim header

Ethernet-to-Ethernet/AAL5/AAL2 inter-working

L2 Ethernet switching using MAC address or IEEE Std. 802.1P/Q™ VLAN tags

ATM (AAL2/AAL5) to Ethernet (IP) interworking in accordance with RFC2684 including bridging of ATM

ports to Ethernet ports

–

Extensive support for ATM statistics and Ethernet RMON/MIB statistics

AAL2 protocol rate up to 4 CPS at OC-3/STM-1 rate

Packet over Sonet (POS) up to 622-Mbps full-duplex 124 MultiPHY

POS hardware; microcode must be loaded as an IRAM package

Transparent up to 70-Mbps full-duplex

HDLC up to 70-Mbps full-duplex

HDLC BUS up to 10 Mbps

Asynchronous HDLC

UART

BISYNC up to 2 Mbps

User-programmable Virtual FIFO size

QUICC multichannel controller (QMC) for 64 TDM channels

— One multichannel communication controller (MCC) only on the MPC8360E supporting the following:

–

256 HDLC or transparent channels

128 SS7 channels

Almost any combination of subgroups can be multiplexed to single or multiple TDM interfaces

— Two UTOPIA/POS interfaces on the MPC8360E supporting 124 MultiPHY each (optional 2*128 MultiPHY with

extended address) and one UTOPIA/POS interface on the MPC8358E supporting 31/124 MultiPHY

— Two serial peripheral interfaces (SPI); SPI2 is dedicated to Ethernet PHY management

1.SMII or SGMII media-independent interface is not currently supported.

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— Eight TDM interfaces on the MPC8360E and four TDM interfaces on the MPC8358E with 1-bit mode for E3/T3

rates in clear channel

— Sixteen independent baud rate generators and 30 input clock pins for supplying clocks to UCC and MCC serial

channels (MCC is only available on the MPC8360E)

— Four independent 16-bit timers that can be interconnected as four 32-bit timers

— Interworking functionality:

–

Layer 2 10/100-Base T Ethernet switch

ATM-to-ATM switching (AAL0, 2, 5)

Ethernet-to-ATM switching with L3/L4 support

PPP interworking

•

Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP, 802.11i®, iSCSI,

and IKE processing. The security engine contains four crypto-channels, a controller, and a set of crypto execution units

(EUs).

— Public key execution unit (PKEU) supporting the following:

–

RSA and Diffie-Hellman

Programmable field size up to 2048 bits

Elliptic curve cryptography

F2m and F(p) modes

Programmable field size up to 511 bits

— Data encryption standard execution unit (DEU)

–

DES, 3DES

Two key (K1, K2) or three key (K1, K2, K3)

ECB and CBC modes for both DES and 3DES

— Advanced encryption standard unit (AESU)

— Implements the Rinjdael symmetric key cipher

— Key lengths of 128, 192, and 256 bits, two key

–

ECB, CBC, CCM, and counter modes

— ARC four execution unit (AFEU)

–

Implements a stream cipher compatible with the RC4 algorithm

40- to 128-bit programmable key

— Message digest execution unit (MDEU)

–

SHA with 160-, 224-, or 256-bit message digest

MD5 with 128-bit message digest

HMAC with either SHA or MD5 algorithm

— Random number generator (RNG)

— Four crypto-channels, each supporting multi-command descriptor chains

–

Static and/or dynamic assignment of crypto-execution units via an integrated controller

Buffer size of 256 bytes for each execution unit, with flow control for large data sizes

— Storage/NAS XOR parity generation accelerator for RAID applications

•

Dual DDR SDRAM memory controllers on the MPC8360E and a single DDR SDRAM memory controller on the

MPC8358E

— Programmable timing supporting both DDR1 and DDR2 SDRAM

— On the MPC8360E, the DDR buses can be configured as two 32-bit buses or one 64-bit bus; on the MPC8358E,

the DDR bus can be configured as a 32- or 64-bit bus

— 32- or 64-bit data interface, up to 333 MHz (for the MPC8360E) and 266 MHz (for the MPC8358E) data rate

— Four banks of memory, each up to 1 Gbyte

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

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— DRAM chip configurations from 64 Mbits to 1 Gigabit with ×8/×16 data ports

— Full ECC support (when the MPC8360E is configured as 2×32-bit DDR memory controllers, both support ECC)

— Page mode support (up to 16 simultaneous open pages for DDR1, up to 32 simultaneous open pages for DDR2)

— Contiguous or discontiguous memory mapping

— Read-modify-write support

— Sleep mode support for self refresh SDRAM

— Supports auto refreshing

— Supports source clock mode

— On-the-fly power management using CKE

— Registered DIMM support

— 2.5-V SSTL2 compatible I/O for DDR1, 1.8-V SSTL2 compatible I/O for DDR2

— External driver impedance calibration

— On-die termination (ODT)

•

PCI interface

— PCI Specification Revision 2.3 compatible

— Data bus widths:

–

Single 32-bit data PCI interface that operates at up to 66 MHz

— PCI 3.3-V compatible (not 5-V compatible)

— PCI host bridge capabilities on both interfaces

— PCI agent mode supported on PCI interface

— Support for PCI-to-memory and memory-to-PCI streaming

— Memory prefetching of PCI read accesses and support for delayed read transactions

— Support for posting of processor-to-PCI and PCI-to-memory writes

— On-chip arbitration, supporting five masters on PCI

— Support for accesses to all PCI address spaces

— Parity support

— Selectable hardware-enforced coherency

— Address translation units for address mapping between host and peripheral

— Dual address cycle supported when the device is the target

— Internal configuration registers accessible from PCI

Local bus controller (LBC)

•

— Multiplexed 32-bit address and data operating at up to 133 MHz

— Eight chip selects support eight external slaves

— Up to eight-beat burst transfers

— 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller

— Three protocol engines available on a per chip select basis:

–

General-purpose chip select machine (GPCM)

Three user programmable machines (UPMs)

Dedicated single data rate SDRAM controller

— Parity support

— Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)

Programmable interrupt controller (PIC)

•

— Functional and programming compatibility with the MPC8260 interrupt controller

— Support for 8 external and 35 internal discrete interrupt sources

— Support for one external (optional) and seven internal machine checkstop interrupt sources

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

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— Programmable highest priority request

— Four groups of interrupts with programmable priority

— External and internal interrupts directed to communication processor

— Redirects interrupts to external INTA pin when in core disable mode

— Unique vector number for each interrupt source

2

•

Dual industry-standard I C interfaces

— Two-wire interface

— Multiple master support

2

— Master or slave I C mode support

— On-chip digital filtering rejects spikes on the bus

2

— System initialization data is optionally loaded from I C-1 EPROM by boot sequencer embedded hardware

DMA controller

— Four independent virtual channels

— Concurrent execution across multiple channels with programmable bandwidth control

— All channels accessible by local core and remote PCI masters

— Misaligned transfer capability

— Data chaining and direct mode

— Interrupt on completed segment and chain

— DMA external handshake signals: DMA_DREQ[0:3]/DMA_DACK[0:3]/DMA_DONE[0:3]. There is one set for

each DMA channel. The pins are multiplexed to the parallel IO pins with other QE functions.

•

DUART

— Two 4-wire interfaces (RxD, TxD, RTS, CTS)

— Programming model compatible with the original 16450 UART and the PC16550D

System timers

— Periodic interrupt timer

— Real-time clock

— Software watchdog timer

— Eight general-purpose timers

•

IEEE Std. 1149.1™-compliant, JTAG boundary scan

Integrated PCI bus and SDRAM clock generation

2

Electrical Characteristics

This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8360E/58E. The device

is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a

more complete reference. These are not purely I/O buffer design specifications.

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

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Overall DC Electrical Characteristics

2.1

Overall DC Electrical Characteristics

This section covers the ratings, conditions, and other characteristics.

2.1.1

Absolute Maximum Ratings

This table provides the absolute maximum ratings.

Table 1. Absolute Maximum Ratings

1

Characteristic

Core and PLL supply voltage for

Symbol

Max Value

Unit

Notes

V_DD& AV_DD

–0.3 to 1.32

V

—

MPC8358 Device Part Number with

Processor Frequency label of AD=266MHz and AG=400MHz &

QUICC Engine Frequency label of E=300MHz & G=400MHz

MPC8360 Device Part Number with

Processor Frequency label of AG=400MHz and AJ=533MHz &

QUICC Engine Frequency label of G=400MHz

Core and PLL supply voltage for

V_DD& AV_DD

–0.3 to 1.37

V

—

MPC8360 device Part Number with

Processor Frequency label of AL=667MHz and QUICC Engine

Frequency label of H=500MHz

DDR and DDR2 DRAM I/O voltage

GV_DD

DDR

DDR2

–0.3 to 2.75

–0.3 to 1.89

Three-speed Ethernet I/O, MII management voltage

LV_DD

–0.3 to 3.63

V

—

PCI, local bus, DUART, system control and power management,

I²C, SPI, and JTAG I/O voltage

OV_DD

Input voltage

DDR DRAM signals

MV_IN

MV_REF

LV_IN

–0.3 to (GV_DD+ 0.3)

–0.3 to (LV_DD+ 0.3)

–0.3 to (OV_DD+ 0.3)

V

2, 5

4, 5

3, 5

DDR DRAM reference

Three-speed Ethernet signals

Local bus, DUART, CLKIN, system

control and power management, I²C, SPI,

and JTAG signals

OV_IN

PCI

OV_IN

–0.3 to (OV_DD+ 0.3)

V

6

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

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Overall DC Electrical Characteristics

1

Table 1. Absolute Maximum Ratings (continued)

Characteristic

Symbol

Max Value

–55 to 150

Unit

Notes

Storage temperature range

T_STG

°C

—

Notes:

1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and

functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause

permanent damage to the device.

2. Caution: MV_INmust not exceed GV_DDby more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during

power-on reset and power-down sequences.

3. Caution: OV_INmust not exceed OV_DDby more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during

power-on reset and power-down sequences.

4. Caution: LV_INmust not exceed LV_DDby more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during

power-on reset and power-down sequences.

5. (M,L,O)V_INand MV_REFmay overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 3.

6. OV_INon the PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as

shown in Figure 4.

2.1.2

Power Supply Voltage Specification

This table provides the recommended operating conditions for the device. Note that the values in this table are the recommended

and tested operating conditions. Proper device operation outside of these conditions is not guaranteed.

Table 2. Recommended Operating Conditions

Recommended

Characteristic

Core and PLL supply voltage for

Symbol

Unit

Notes

Value

V_DD& AV_DD

1.2 V ± 60 mV

V

1, 3

MPC8358 Device Part Number with

Processor Frequency label of AD=266MHz and AG=400MHz &

QUICC Engine Frequency label of E=300MHz & G=400MHz

MPC8360 Device Part Number with

Processor Frequency label of AG=400MHz and AJ=533MHz &

QUICC Engine Frequency label of G=400MHz

Core and PLL supply voltage for

V_DD& AV_DD

1.3 V ± 50 mV

V

1, 3

MPC8360 Device Part Number with

Processor Frequency label of AL=667MHz and QUICC Engine

Frequency label of H=500MHz

DDR and DDR2 DRAM I/O supply voltage

GV_DD

—

DDR

DDR2

2.5 V ± 125 mV

1.8 V ± 90 mV

Three-speed Ethernet I/O supply voltage

LV_DD

0

1

2

3.3 V ± 330 mV

2.5 V ± 125 mV

V

—

3.3 V ± 330 mV

2.5 V ± 125 mV

3.3 V ± 330 mV

2.5 V ± 125 mV

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

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9

Overall DC Electrical Characteristics

Table 2. Recommended Operating Conditions (continued)

Recommended

Value

Characteristic

Symbol

Unit

Notes

PCI, local bus, DUART, system control and power management, I²C,

SPI, and JTAG I/O voltage

OV_DD

3.3 V ± 330 mV

V

—

Junction temperature

T_J

0 to 105

–40 to 105

°C

2

Notes:

1. GV_DD, LV_DD, OV_DD, AV_DD, and V_DDmust track each other and must vary in the same direction—either in the positive or

negative direction.

2. The operating conditions for junction temperature, T_J, on the 600/333/400 MHz and 500/333/500 MHz on rev. 2.0 silicon is

0° to 70 °C. Refer to Errata General9 in Chip Errata for the MPC8360E, Rev. 1.

3. For more information on Part Numbering, refer to Table 80.

This figure shows the undershoot and overshoot voltages at the interfaces of the device.

G/L/OV_DD+ 20%

G/L/OV_DD+ 5%

G/L/OV_DD

V_IH

GND

GND – 0.3 V

V_IL

GND – 0.7 V

Not to Exceed 10%

1

of t_interface

Note:

1. Note that t_interfacerefers to the clock period associated with the bus clock interface.

Figure 3. Overshoot/Undershoot Voltage for GV /OV /LV

DD

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

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Power Sequencing

This figure shows the undershoot and overshoot voltage of the PCI interface of the device for the 3.3-V signals, respectively.

11 ns

(Min)

+7.1 V

Overvoltage

Waveform

7.1 V p-to-p

(Min)

0 V

4 ns

(Max)

4 ns

(Max)

62.5 ns

+3.6 V

Undervoltage

Waveform

7.1 V p-to-p

(Min)

–3.5 V

Figure 4. Maximum AC Waveforms on PCI interface for 3.3-V Signaling

2.1.3

Output Driver Characteristics

This table provides information on the characteristics of the output driver strengths. The values are preliminary estimates.

Table 3. Output Drive Capability

Driver Type

Local bus interface utilities signals

Output Impedance (Ω)

Supply Voltage

42

25

42

OV_DD= 3.3 V

PCI signals

PCI output clocks (including PCI_SYNC_OUT)

DDR signal

20

GV_DD= 2.5 V

GV_DD= 1.8 V

36 (half-strength mode)¹

DDR2 signal

18

36 (half-strength mode)¹

10/100/1000 Ethernet signals

DUART, system control, I²C, SPI, JTAG

GPIO signals

42

LV_DD= 2.5/3.3 V

OV_DD= 3.3 V

LV_DD= 2.5/3.3 V

Note:

1. DDR output impedance values for half strength mode are verified by design and not tested.

2.2

Power Sequencing

This section details the power sequencing considerations for the MPC8360E/58E.

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Power Sequencing

2.2.1

Power-Up Sequencing

MPC8360E/58E does not require the core supply voltage (V and AV ) and I/O supply voltages (GV , LV , and OV )

DD

to be applied in any particular order. During the power ramp up, before the power supplies are stable and if the I/O voltages are

supplied before the core voltage, there may be a period of time that all input and output pins are actively be driven and cause

contention and excessive current from 3A to 5A. In order to avoid actively driving the I/O pins and to eliminate excessive current

draw, apply the core voltage (V ) before the I/O voltage (GV , LV , and OV ) and assert PORESET before the power

DD

supplies fully ramp up. In the case where the core voltage is applied first, the core voltage supply must rise to 90% of its nominal

value before the I/O supplies reach 0.7 V, see this figure.

Voltage

I/O Voltage (GV_DD, LV_DD, OV_DD

)

Core Voltage (V_DD, AV_DD

)

0.7 V

90%

Time

Figure 5. Power Sequencing Example

I/O voltage supplies (GV , LV , and OV ) do not have any ordering requirements with respect to one another.

DD

2.2.2

Power-Down Sequencing

The MPC8360E/58E does not require the core supply voltage and I/O supply voltages to be powered down in any particular

order.

3

Power Characteristics

The estimated typical power dissipation values are shown in these tables.

1

Table 4. MPC8360E TBGA Core Power Dissipation

Core

Frequency (MHz)

CSB

Frequency (MHz)

QUICC Engine

Frequency (MHz)

Typical

Maximum

Unit

Notes

266

400

533

667

500

266

333

500

400

500

5.0

4.5

4.8

5.8

5.9

5.6

5.0

5.3

6.3

6.4

W

2, 3, 5

2, 3, 4

3, 6, 7, 8

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

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Freescale Semiconductor

Power Sequencing

1

Table 4. MPC8360E TBGA Core Power Dissipation (continued)

Core

Frequency (MHz)

CSB

Frequency (MHz)

QUICC Engine

Frequency (MHz)

Typical

Maximum

Unit

Notes

667

333

500

6.1

6.8

W

2, 3, 5, 9

Notes:

1. The values do not include I/O supply power (OV_DD, LV_DD, GV_DD) or AV_DD. For I/O power values, see Table 6.

2. Typical power is based on a voltage of V_DD= 1.2 V or 1.3 V, a junction temperature of T_J= 105°C, and a Dhrystone

benchmark application.

3. Thermal solutions need to design to a value higher than typical power on the end application, T_Atarget, and I/O power.

4. Maximum power is based on a voltage of V_DD= 1.2 V, WC process, a junction T_J= 105° C, and an artificial smoke test.

5. Maximum power is based on a voltage of V_DD= 1.3 V for applications that use 667 MHz (CPU)/500 (QE) with WC process,

a junction T_J= 105°C, and an artificial smoke test.

6. Typical power is based on a voltage of V_DD= 1.3 V, a junction temperature of T_J= 70°C, and a Dhrystone benchmark

application.

7. Maximum power is based on a voltage of V_DD= 1.3 V for applications that use 667 MHz (CPU) or 500 (QE) with WC

process, a junction T_J= 70°C, and an artificial smoke test.

8. This frequency combination is only available for rev. 2.0 silicon.

9. This frequency combination is not available for rev. 2.0 silicon.

1

Table 5. MPC8358E TBGA Core Power Dissipation

Core

Frequency (MHz)

CSB

Frequency (MHz)

QUICC Engine

Frequency (MHz)

Typical

Maximum

Unit

Notes

266

400

266

300

400

4.1

4.5

5.0

W

2, 3, 4

Notes:

1. The values do not include I/O supply power (OV_DD, LV_DD, GV_DD) or AV_DD. For I/O power values, see Table 6.

2. Typical power is based on a voltage of V_DD= 1.2 V, a junction temperature of T_J= 105°C, and a Dhrystone benchmark

application.

3. Thermal solutions need to design to a value higher than typical power on the end application, T_Atarget, and I/O power.

4. Maximum power is based on a voltage of V_DD= 1.2 V, WC process, a junction T_J= 105° C, and an artificial smoke test.

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

Freescale Semiconductor

13

Power Sequencing

This table shows the estimated typical I/O power dissipation for the device.

Table 6. Estimated Typical I/O Power Dissipation

GV_DD

(1.8 V)

GV_DD

(2.5 V)

OV_DD

(3.3 V)

LV_DD

(3.3 V)

LV_DD

(2.5 V)

Interface

DDR I/O

65% utilization

R_s= 20 Ω

Parameter

Unit

Comments

200 MHz, 1 × 32 bits

200 MHz, 1 × 64 bits

200 MHz, 2 × 32 bits

266 MHz, 1 × 32 bits

266 MHz, 1 × 64 bits

266 MHz, 2 × 32 bits

333 MHz, 1 × 32 bits

333 MHz, 1 × 64 bits

333 MHz, 2 × 32 bits

133 MHz, 32 bits

83 MHz, 32 bits

66 MHz, 32 bits

50 MHz, 32 bits

33 MHz, 32 bits

66 MHz, 32 bits

MII or RMII

0.3

0.4

0.6

0.35

0.46

0.7

0.4

0.53

0.81

—

0.46

0.58

0.92

0.56

0.7

1.11

0.65

0.82

1.3

—

0.04

—

W

—

R_t= 50 Ω

2 pairs of clocks

—

Local Bus I/O

Load = 25 pf

3 pairs of clocks

0.22

0.14

0.12

0.09

0.05

0.07

—

PCI I/O

Load = 30 pF

—

10/100/1000

Ethernet I/O

Load = 20 pF

—

0.01

0.04

—

Multiply by

number of

interfaces used.

GMII or TBI

—

RGMII or RTBI

—

Other I/O

—

0.1

—

4

Clock Input Timing

This section provides the clock input DC and AC electrical characteristics for the MPC8360E/58E.

NOTE

The rise/fall time on QUICC Engine block input pins should not exceed 5 ns. This should

be enforced especially on clock signals. Rise time refers to signal transitions from 10% to

90% of V ; fall time refers to transitions from 90% to 10% of V

.

DD

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

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Freescale Semiconductor

DC Electrical Characteristics

4.1

DC Electrical Characteristics

This table provides the clock input (CLKIN/PCI_SYNC_IN) DC timing specifications for the device.

Table 7. CLKIN DC Electrical Characteristics

Parameter

Input high voltage

Condition

Symbol

Min

Max

Unit

—

V_IH

V_IL

I_IN

2.7

–0.3

—

OV_DD+ 0.3

0.4

V

Input low voltage

CLKIN input current

PCI_SYNC_IN input current

0 V ≤V_IN≤OV_DD

±10

μA

0 V ≤V_IN≤0.5V or

OV_DD– 0.5V ≤V_IN≤OV_DD

I_IN

—

±10

PCI_SYNC_IN input current

0.5 V ≤V_IN≤OV_DD– 0.5 V

I_IN

—

±100

μA

4.2

AC Electrical Characteristics

The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device is

configured in PCI host or PCI agent mode. This table provides the clock input (CLKIN/PCI_CLK) AC timing specifications for

the device.

Table 8. CLKIN AC Timing Specifications

Parameter/Condition

CLKIN/PCI_CLK frequency

Symbol

Min

Typical

Max

Unit

Notes

f_CLKIN

t_CLKIN

—

15

0.6

40

—

66.67

—

MHz

ns

1

—

2

CLKIN/PCI_CLK cycle time

CLKIN/PCI_CLK rise and fall time

CLKIN/PCI_CLK duty cycle

CLKIN/PCI_CLK jitter

Notes:

t_KH, t_KL

1.0

—

2.3

ns

t_{KHK CLKIN}

/t

60

%

3

—

±150

ps

4, 5

1. Caution: The system, core, USB, security, and 10/100/1000 Ethernet must not exceed their respective maximum or

minimum operating frequencies.

2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 V and 2.7 V.

3. Timing is guaranteed by design and characterization.

4. This represents the total input jitter—short term and long term—and is guaranteed by design.

5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low

to allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.

4.3

Gigabit Reference Clock Input Timing

This table provides the Gigabit reference clocks (GTX_CLK125) AC timing specifications.

Table 9. GTX_CLK125 AC Timing Specifications

At recommended operating conditions with LV_DD= 2.5 ± 0.125 mV/ 3.3 V ± 165 mV

Parameter/Condition

Symbol

Min

Typical

Max

Unit

Notes

GTX_CLK125 frequency

GTX_CLK125 cycle time

t_G125

—

125

8

—

MHz

ns

—

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

Freescale Semiconductor

15

RESET DC Electrical Characteristics

Table 9. GTX_CLK125 AC Timing Specifications

At recommended operating conditions with LV_DD= 2.5 ± 0.125 mV/ 3.3 V ± 165 mV (continued)

Parameter/Condition

Symbol

t_G125R/t_G125F

Min

Typical

Max

Unit

Notes

GTX_CLK rise and fall time

—

ns

1

LV_DD= 2.5 V

LV_DD= 3.3 V

0.75

1.0

GTX_CLK125 duty cycle

t_{G125H G125}

/t

—

%

2

GMII & TBI

45

47

55

53

1000Base-T for RGMII & RTBI

GTX_CLK125 jitter

Notes:

—

±150

ps

1. Rise and fall times for GTX_CLK125 are measured from 0.5 and 2.0 V for LV_DD= 2.5 V and from 0.6 and 2.7 V for

LV_DD= 3.3 V.

2. GTX_CLK125 is used to generate the GTX clock for the UCC Ethernet transmitter with 2% degradation. The GTX_CLK125

duty cycle can be loosened from 47%/53% as long as the PHY device can tolerate the duty cycle generated by GTX_CLK.

See Section 8.2.2, “MII AC Timing Specifications,” Section 8.2.3, “RMII AC Timing Specifications,” and Section 8.2.5,

“RGMII and RTBI AC Timing Specifications” for the duty cycle for 10Base-T and 100Base-T reference clock.

5

RESET Initialization

This section describes the DC and AC electrical specifications for the reset initialization timing and electrical requirements of

the MPC8360E/58E.

5.1

RESET DC Electrical Characteristics

This table provides the DC electrical characteristics for the RESET pins of the device.

1

Table 10. RESET Pins DC Electrical Characteristics

Characteristic

Symbol

Condition

Min

Max

Unit

Input high voltage

Input low voltage

Input current

V_IH

V_IL

I_IN

—

2.0

–0.3

—

OV_DD+ 0.3

V

0.8

±10

—

μA

V

2

Output high voltage

Output low voltage

Notes:

V_OH

I_OH= –8.0 mA

I_OL= 8.0 mA

2.4

—

V_OL

0.5

0.4

V

I

= 3.2 mA

OL

—

V

OL

1. This table applies for pins PORESET, HRESET, SRESET, and QUIESCE.

2. HRESET and SRESET are open drain pins, thus V_OHis not relevant for those pins.

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

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Freescale Semiconductor

RESET AC Electrical Characteristics

5.2

RESET AC Electrical Characteristics

This section describes the AC electrical specifications for the reset initialization timing requirements of the device. This table

provides the reset initialization AC timing specifications for the DDR SDRAM component(s).

Table 11. RESET Initialization Timing Specifications

Parameter/Condition

Min

Max

Unit

Notes

Required assertion time of HRESET or SRESET (input) to activate reset

flow

32

—

t_{PCI_SYNC_IN}

1

Required assertion time of PORESET with stable clock applied to CLKIN

when the device is in PCI host mode

32

—

t_CLKIN

2

1

Required assertion time of PORESET with stable clock applied to

PCI_SYNC_IN when the device is in PCI agent mode

t_{PCI_SYNC_IN}

HRESET/SRESET assertion (output)

512

16

4

—

t_{PCI_SYNC_IN}

t_CLKIN

1

2

HRESET negation to SRESET negation (output)

Input setup time for POR config signals (CFG_RESET_SOURCE[0:2] and

CFG_CLKIN_DIV) with respect to negation of PORESET when the device

is in PCI host mode

Input setup time for POR config signals (CFG_RESET_SOURCE[0:2] and

CFG_CLKIN_DIV) with respect to negation of PORESET when the device

is in PCI agent mode

4

—

t_{PCI_SYNC_IN}

1

Input hold time for POR config signals with respect to negation of HRESET

0

—

4

ns

—

3

Time for the device to turn off POR config signals with respect to the

assertion of HRESET

—

Time for the device to turn on POR config signals with respect to the

negation of HRESET

1

—

t_{PCI_SYNC_IN}

1, 3

Notes:

1. t_{PCI_SYNC_IN}is the clock period of the input clock applied to PCI_SYNC_IN. When the device is In PCI host mode the

primary clock is applied to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. Refer

MPC8360E PowerQUICC II Pro Integrated Communications Processor Reference Manual for more details.

2. t_CLKINis the clock period of the input clock applied to CLKIN. It is only valid when the device is in PCI host mode. Refer

MPC8360E PowerQUICC II Pro Integrated Communications Processor Reference Manual for more details.

3. POR config signals consists of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.

This table provides the PLL and DLL lock times.

Table 12. PLL and DLL Lock Times

Parameter/Condition

Min

Max

Unit

Notes

PLL lock times

DLL lock times

Notes:

—

100

μs

—

7680

122,880

csb_clk cycles

1, 2

1. DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk). A 2:1

ratio results in the minimum and an 8:1 ratio results in the maximum.

2. The csb_clk is determined by the CLKIN and system PLL ratio. See Section 21, “Clocking,” for more information.

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

Freescale Semiconductor

17

QUICC Engine Block Operating Frequency Limitations

5.3

QUICC Engine Block Operating Frequency Limitations

This section specify the limits of the AC electrical characteristics for the operation of the QUICC Engine block’s

communication interfaces.

NOTE

The settings listed below are required for correct hardware interface operation. Each

protocol by itself requires a minimal QUICC Engine block operating frequency setting for

meeting the performance target. Because the performance is a complex function of all the

QUICC Engine block settings, the user should make use of the QUICC Engine block

performance utility tool provided by Freescale to validate their system.

This table lists the maximal QUICC Engine block I/O frequencies and the minimal QUICC Engine block core frequency for

each interface.

Table 13. QUICC Engine Block Operating Frequency Limitations

Min QUICC Engine

Interface Operating Max Interface Bit

Interface

Operating

Notes

Frequency (MHz)

Rate (Mbps)

Frequency¹(MHz)

Ethernet Management: MDC/MDIO

MII

10 (max)

25 (typ)

10

100

20

50

—

2

RMII

50 (typ)

100

50

GMII/RGMII/TBI/RTBI

SPI (master/slave)

UCC through TDM

MCC

125 (typ)

10 (max)

50 (max)

25 (max)

50 (max)

10 (max)

50 (max)

1000

10

250

20

70

8 × F

16 × F

2 × F

20

16.67

800

2, 4

2

UTOPIA L2

POS-PHY L2

800

2

HDLC bus

10

—

2, 3

—

HDLC/transparent

UART/async HDLC

50

8/3 × F

20

3.68 (max internal ref

clock)

115 (Kbps)

BISYNC

USB

2 (max)

2

20

96

—

48 (ref clock)

12

Notes:

1. The QUICC Engine module needs to run at a frequency higher than or equal to what is listed in this table.

2. ‘F’ is the actual interface operating frequency.\

3. The bit rate limit is independent of the data bus width (that is, the same for serial, nibble, or octal interfaces).

4. TDM in high-speed mode for serial data interface.

6

DDR and DDR2 SDRAM

This section describes the DC and AC electrical specifications for the DDR and DDR2 SDRAM interface of the

MPC8360E/58E.

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

18

Freescale Semiconductor

DDR and DDR2 SDRAM DC Electrical Characteristics

6.1

DDR and DDR2 SDRAM DC Electrical Characteristics

This table provides the recommended operating conditions for the DDR2 SDRAM component(s) of the device when

GV (typ) = 1.8 V.

DD

Table 14. DDR2 SDRAM DC Electrical Characteristics for GV (typ) = 1.8 V

DD

Parameter/Condition

Symbol

Min

Max

Unit

Notes

I/O supply voltage

GV_DD

MV_REF

V_TT

V_IH

1.71

1.89

0.51 × GV_DD

MV_REF+ 0.04

GV_DD+ 0.3

MV_REF– 0.125

±10

V

1

2

I/O reference voltage

0.49 × GV_DD

I/O termination voltage

Input high voltage

MV_REF– 0.04

V

3

MV_REF+ 0.125

V

—

4

Input low voltage

V_IL

–0.3

—

V

Output leakage current

Output high current (V_OUT= 1.420 V)

Output low current (V_OUT= 0.280 V)

MV_REFinput leakage current

I_OZ

μA

mA

μA

I_OH

–13.4

13.4

—

I_OL

—

I_VREF

I_IN

±10

Input current (0 V ≤V_IN≤OV_DD

)

—

±10

Notes:

1. GV_DDis expected to be within 50 mV of the DRAM GV_DDat all times.

2. MV_REFis expected to equal 0.5 × GV_DD, and to track GV_DDDC variations as measured at the receiver. Peak-to-peak noise

on MV_REFcannot exceed ±2% of the DC value.

3. V_TTis not applied directly to the device. It is the supply to which far end signal termination is made and is expected to equal

MV_REF. This rail should track variations in the DC level of MV_REF

.

4. Output leakage is measured with all outputs disabled, 0 V ≤V_OUT≤GV_DD

.

This table provides the DDR2 capacitance when GV (typ) = 1.8 V.

DD

Table 15. DDR2 SDRAM Capacitance for GV (typ)=1.8 V

DD

Parameter/Condition

Symbol

Min

Max

Unit

Notes

Input/output capacitance: DQ, DQS, DQS

Delta input/output capacitance: DQ, DQS, DQS

Note:

C_IO

6

8

pF

1

C_DIO

—

0.5

1. This parameter is sampled. GV_DD= 1.8 V ± 0.090 V, f = 1 MHz, T_A= 25°C, V_OUT= GV_DD/2, V_OUT(peak-to-peak) = 0.2 V.

This table provides the recommended operating conditions for the DDR SDRAM component(s) of the device when

GV (typ) = 2.5 V.

DD

Table 16. DDR SDRAM DC Electrical Characteristics for GV (typ) = 2.5 V

DD

Parameter/Condition

Symbol

Min

Max

Unit

Notes

I/O supply voltage

GV_DD

MV_REF

V_TT

2.375

2.625

V

1

2

3

I/O reference voltage

I/O termination voltage

0.49 × GV_DD

MV_REF– 0.04

0.51 × GV_DD

MV_REF+ 0.04

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

Freescale Semiconductor

19

DDR and DDR2 SDRAM AC Electrical Characteristics

Table 16. DDR SDRAM DC Electrical Characteristics for GV (typ) = 2.5 V (continued)

DD

Parameter/Condition

Input high voltage

Symbol

Min

Max

Unit

Notes

V_IH

V_IL

MV_REF+ 0.18

GV_DD+ 0.3

V

—

4

Input low voltage

–0.3

—

MV_REF– 0.18

Output leakage current

I_OZ

±10

—

μA

mA

μA

Output high current (V_OUT= 1.95 V)

Output low current (V_OUT= 0.35 V)

MV_REFinput leakage current

I_OH

I_OL

I_VREF

I_IN

–15.2

15.2

—

±10

Input current (0 V ≤V_IN≤OV_DD

)

—

Notes:

1. GV_DDis expected to be within 50 mV of the DRAM GV_DDat all times.

2. MV_REFis expected to be equal to 0.5 × GV_DD, and to track GV_DDDC variations as measured at the receiver. Peak-to-peak

noise on MV_REFmay not exceed ±2% of the DC value.

3. V_TTis not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MV_REF. This rail should track variations in the DC level of MV_REF

.

4. Output leakage is measured with all outputs disabled, 0 V ≤V_OUT≤GV_DD

.

This table provides the DDR capacitance when GV (typ) = 2.5 V.

DD

Table 17. DDR SDRAM Capacitance for GV (typ) = 2.5 V

DD

Parameter/Condition

Input/output capacitance: DQ, DQS

Symbol

Min

Max

Unit

Notes

C_IO

6

8

pF

1

Delta input/output capacitance: DQ, DQS

C_DIO

—

0.5

Note:

1. This parameter is sampled. GV_DD= 2.5 V ± 0.125 V, f = 1 MHz, T_A= 25° C, V_OUT= GV_DD/2, V_OUT(peak-to-peak) = 0.2 V.

6.2

DDR and DDR2 SDRAM AC Electrical Characteristics

This section provides the AC electrical characteristics for the DDR and DDR2 SDRAM interface.

6.2.1

DDR and DDR2 SDRAM Input AC Timing Specifications

This table provides the input AC timing specifications for the DDR2 SDRAM interface when GV (typ) = 1.8 V.

DD

Table 18. DDR2 SDRAM Input AC Timing Specifications for GV (typ) = 1.8 V

DD

At recommended operating conditions with GV_DDof 1.8 V ± 5%.

Parameter

Symbol

Min

Max

Unit

Notes

AC input low voltage

AC input high voltage

V_IL

V_IH

—

MV_REF– 0.25

—

V

—

MV_REF+ 0.25

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

20

Freescale Semiconductor

DDR and DDR2 SDRAM AC Electrical Characteristics

This table provides the input AC timing specifications for the DDR SDRAM interface when GV (typ) = 2.5 V.

DD

Table 19. DDR SDRAM Input AC Timing Specifications

At recommended operating conditions with GV_DDof 2.5 V ± 5%.

Parameter

Symbol

Min

Max

Unit

Notes

AC input low voltage

AC input high voltage

V_IL

—

MV_REF– 0.31

—

V

—

V_IH

MV_REF+ 0.31

Table 20. DDR and DDR2 SDRAM Input AC Timing Specifications Mode

At recommended operating conditions with GV_DDof (1.8 or 2.5 V) ± 5%.

Parameter

Symbol

Min

Max

Unit

Notes

MDQS—MDQ/MECC input skew per byte

t_DISKEW

ps

1, 2

333 MHz

266 MHz

200 MHz

–750

–1125

–1250

750

1125

1250

Notes:

1. AC timing values are based on the DDR data rate, which is twice the DDR memory bus frequency.

2. Maximum possible skew between a data strobe (MDQS[n]) and any corresponding bit of data (MDQ[8n + {0...7}] if 0 ≤n ≤7)

or ECC (MECC[{0...7}] if n = 8).

This figure shows the input timing diagram for the DDR controller.

MCK[n]

t_MCK

MDQS[n]

MDQ[x]

D0

D1

t_DISKEW

Figure 6. DDR Input Timing Diagram

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

Freescale Semiconductor

21

DDR and DDR2 SDRAM AC Electrical Characteristics

6.2.2

DDR and DDR2 SDRAM Output AC Timing Specifications

Table 21 and Table 22 provide the output AC timing specifications and measurement conditions for the DDR and DDR2

SDRAM interface.

Table 21. DDR and DDR2 SDRAM Output AC Timing Specifications for Source

Synchronous Mode

At recommended operating conditions with GV_DDof (1.8 V or 2.5 V) ± 5%.

Parameter⁸

Symbol¹

Min

Max

Unit

Notes

MCK[n] cycle time, (MCK[n]/MCK[n] crossing)

Skew between any MCK to ADDR/CMD

t_MCK

6

10

ns

2

3

t_AOSKEW

333 MHz

266 MHz

200 MHz

–1.0

–1.1

–1.2

0.2

0.3

0.4

ADDR/CMD output setup with respect to MCK

333 MHz

t_DDKHAS

—

ns

4

2.1

2.8

3.5

266 MHz

200 MHz

ADDR/CMD output hold with respect to MCK

t_DDKHAX

—

333 MHz

2.0

2.7

2.8

3.5

266 MHz—DDR1

266 MHz—DDR2

200 MHz

MCS(n) output setup with respect to MCK

t_DDKHCS

t_DDKHCX

t_DDKHMH

—

ns

4

333 MHz

266 MHz

200 MHz

2.1

2.8

3.5

MCS(n) output hold with respect to MCK

MCK to MDQS

333 MHz

266 MHz

200 MHz

2.0

2.7

3.5

–0.8

0.7

—

ns

5, 9

6

MDQ/MECC/MDM output setup with respect to MDQS t_DDKHDS

,

333 MHz t_DDKLDS

266 MHz

200 MHz

0.7

1.0

1.2

MDQ/MECC/MDM output hold with respect to MDQS

t_DDKHDX

,

—

ns

6

7

333 MHz t_DDKLDX

266 MHz

200 MHz

0.7

1.0

1.2

MDQS preamble start

t_DDKHMP–0.5 × t_MCK– 0.6 –0.5 × t_MCK+ 0.6

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

22

Freescale Semiconductor

DDR and DDR2 SDRAM AC Electrical Characteristics

Table 21. DDR and DDR2 SDRAM Output AC Timing Specifications for Source

Synchronous Mode (continued)

At recommended operating conditions with GV_DDof (1.8 V or 2.5 V) ± 5%.

Parameter⁸

Symbol¹

Min

Max

Unit

Notes

MDQS epilogue end

t_DDKHME

–0.6

0.9

ns

7

Notes:

1. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. Output hold time can be read as DDR timing

(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,

t_DDKHASsymbolizes DDR timing (DD) for the time t_MCKmemory clock reference (K) goes from the high (H) state until outputs

(A) are setup (S) or output valid time. Also, t_DDKLDXsymbolizes DDR timing (DD) for the time t_MCKmemory clock reference

(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.

2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.

3. In the source synchronous mode, MCK/MCK can be shifted in ¼ applied cycle increments through the clock control register.

For the skew measurements referenced for t_AOSKEWit is assumed that the clock adjustment is set to align the

address/command valid with the rising edge of MCK.

4. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. For the

ADDR/CMD setup and hold specifications, it is assumed that the clock control register is set to adjust the memory clocks

by ½ applied cycle.

5. Note that t_DDKHMHfollows the symbol conventions described in note 1. For example, t_DDKHMHdescribes the DDR timing

(DD) from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). t_DDKHMHcan be modified through

control of the DQSS override bits in the TIMING_CFG_2 register. In source synchronous mode, this is typically set to the

same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these two

parameters have been set to the same adjustment value. Refer MPC8360E PowerQUICC II Pro Integrated Communications

Processor Reference Manual for a description and understanding of the timing modifications enabled by use of these bits.

6. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC

(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the device.

7. All outputs are referenced to the rising edge of MCK(n) at the pins of the device. Note that t_DDKHMPfollows the symbol

conventions described in note 1.

8. AC timing values are based on the DDR data rate, which is twice the DDR memory bus frequency.

9. In rev. 2.0 silicon, t_DDKHMHmaximum meets the specification of 0.6 ns. In rev. 2.0 silicon, due to errata, t_DDKHMHminimum

is –0.9 ns. Refer to Errata DDR18 in Chip Errata for the MPC8360E, Rev. 1.

This figure shows the DDR SDRAM output timing for address skew with respect to any MCK.

MCK[n]

t_MCK

t_AOSKEW(max)

ADDR/CMD

CMD

NOOP

t_AOSKEW(min)

CMD

NOOP

Figure 7. Timing Diagram for t

Measurement

AOSKEW

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

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23

DDR and DDR2 SDRAM AC Electrical Characteristics

This figure provides the AC test load for the DDR bus.

GV_DD/2

Output

Z₀= 50 Ω

R_L= 50 Ω

Figure 8. DDR AC Test Load

Table 22. DDR and DDR2 SDRAM Measurement Conditions

Symbol

DDR

DDR2

Unit

Notes

V_TH

MV_REF± 0.31 V

MV_REF± 0.25 V

V

1

2

V

0.5 × GV_DD

OUT

Notes:

1. Data input threshold measurement point.

2. Data output measurement point.

This figure shows the DDR SDRAM output timing diagram for source synchronous mode.

MCK[n]

t_MCK

t_DDKHAS, t_DDKHCS

t_DDKHAX, t_DDKHCX

ADDR/CMD

Write A0

t_DDKHMP

NOOP

t_DDKHMH

MDQS[n]

MDQ[x]

t_DDKHME

t_DDKHDS

t_DDKLDS

D0

D1

t_DDKLDX

t_DDKHDX

Figure 9. DDR SDRAM Output Timing Diagram for Source Synchronous Mode

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Freescale Semiconductor

DUART DC Electrical Characteristics

7

DUART

This section describes the DC and AC electrical specifications for the DUART interface of the MPC8360E/58E.

7.1

DUART DC Electrical Characteristics

This table provides the DC electrical characteristics for the DUART interface of the device.

Table 23. DUART DC Electrical Characteristics

Parameter

Symbol

Min

Max

Unit

Notes

High-level input voltage

V_IH

V_IL

2

–0.3

OV_DD+ 0.3

V

—

1

Low-level input voltage OV_DD

0.8

—

High-level output voltage, I_OH= –100 μA

Low-level output voltage, I_OL= 100 μA

V_OH

V_OL

I_IN

OV_DD– 0.4

—

V

0.2

±10

V

Input current (0 V ≤V_IN≤OV_DD

)

—

μA

Note:

1. Note that the symbol V_IN, in this case, represents the OV_INsymbol referenced in Table 1 and Table 2.

7.2

DUART AC Electrical Specifications

This table provides the AC timing parameters for the DUART interface of the device.

Table 24. DUART AC Timing Specifications

Parameter

Value

Unit

Notes

Minimum baud rate

Maximum baud rate

Oversample rate

256

>1,000,000

16

baud

—

1

2

Notes:

1. Actual attainable baud rate is limited by the latency of interrupt processing.

2. The middle of a start bit is detected as the eighth sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values

are sampled each sixteenth sample.

8

UCC Ethernet Controller: Three-Speed Ethernet,

MII Management

This section provides the AC and DC electrical characteristics for three-speed, 10/100/1000, and MII management.

8.1

Three-Speed Ethernet Controller (10/100/1000 Mbps)—

GMII/MII/RMII/TBI/RGMII/RTBI Electrical Characteristics

The electrical characteristics specified here apply to all GMII (gigabit media independent interface), MII (media independent

interface), RMII (reduced media independent interface), TBI (ten-bit interface), RGMII (reduced gigabit media independent

interface), and RTBI (reduced ten-bit interface) signals except MDIO (management data input/output) and MDC (management

data clock). The MII, RMII, GMII, and TBI interfaces are only defined for 3.3 V, while the RGMII and RTBI interfaces are only

defined for 2.5 V. The RGMII and RTBI interfaces follow the Hewlett-Packard reduced pin-count interface for Gigabit Ethernet

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GMII, MII, RMII, TBI, RGMII, and RTBI AC Timing Specifications

Physical Layer Device Specification Version 1.2a (9/22/2000). The electrical characteristics for the MDIO and MDC are

specified in Section 8.3, “Ethernet Management Interface Electrical Characteristics.”

8.1.1

10/100/1000 Ethernet DC Electrical Characteristics

The electrical characteristics specified here apply to media independent interface (MII), reduced gigabit media independent

interface (RGMII), reduced ten-bit interface (RTBI), reduced media independent interface (RMII) signals, management data

input/output (MDIO) and management data clock (MDC).

The MII and RMII interfaces are defined for 3.3 V, while the RGMII and RTBI interfaces can be operated at 2.5 V. The RGMII

and RTBI interfaces follow the Reduced Gigabit Media-Independent Interface (RGMII) Specification Version 1.3. The RMII

interface follows the RMII Consortium RMII Specification Version 1.2.

Table 25. RGMII/RTBI, GMII, TBI, MII, and RMII DC Electrical Characteristics (when operating at 3.3 V)

Parameter

Symbol

Conditions

Min

Max

Unit

Notes

Supply voltage 3.3 V

Output high voltage

Output low voltage

Input high voltage

Input low voltage

Input current

LV_DD

V_OH

V_OL

V_IH

V_IL

—

2.97

2.40

GND

2.0

3.63

LV_DD+ 0.3

0.50

V

1

I_OH= –4.0 mA

LV_DD= Min

—

I_OL= 4.0 mA

LV_DD= Min

V

—

LV_DD+ 0.3

0.90

V

–0.3

—

V

I_IN

0 V ≤V_IN≤LV_DD

±10

μA

Note:

1. GMII/MII pins that are not needed for RGMII, RMII, or RTBI operation are powered by the OV_DDsupply.

Table 26. RGMII/RTBI DC Electrical Characteristics (when operating at 2.5 V)

Parameters

Supply voltage 2.5 V

Symbol

Conditions

Min

Max

Unit

LV_DD

V_OH

V_OL

V_IH

V_IL

—

2.37

2.00

2.63

LV_DD+ 0.3

0.40

V

Output high voltage

Output low voltage

Input high voltage

Input low voltage

Input current

I_OH= –1.0 mA

LV_DD= Min

I_OL= 1.0 mA

GND – 0.3

1.7

V

—

LV_DD+ 0.3

0.70

V

–0.3

V

I_IN

0 V ≤V_IN≤LV_DD

—

±10

μA

8.2

GMII, MII, RMII, TBI, RGMII, and RTBI AC Timing Specifications

The AC timing specifications for GMII, MII, TBI, RGMII, and RTBI are presented in this section.

8.2.1

GMII Timing Specifications

This sections describe the GMII transmit and receive AC timing specifications.

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GMII, MII, RMII, TBI, RGMII, and RTBI AC Timing Specifications

8.2.1.1

GMII Transmit AC Timing Specifications

This table provides the GMII transmit AC timing specifications.

Table 27. GMII Transmit AC Timing Specifications

At recommended operating conditions with LV_DD/OV_DDof 3.3 V ± 10%.

Parameter/Condition

Symbol¹

Min

Typ

Max

Unit

Notes

GTX_CLK clock period

t_GTX

—

8.0

—

ns

%

—

3

GTX_CLK duty cycle

t_GTXH/tGTX

40

60

GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay

t_GTKHDX

t_GTKHDV

0.5

—

5.0

ns

GTX_CLK clock rise time, (20% to 80%)

GTX_CLK clock fall time, (80% to 20%)

GTX_CLK125 clock period

t_GTXR

t_GTXF

t_G125

—

45

—

1.0

—

ns

%

—

2

8.0

—

GTX_CLK125 reference clock duty cycle measured at

LV_DD/2

t_{G125H G125}

/t

55

2

Notes:

1. The symbols used for timing specifications follow the pattern t_{(first two letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_GTKHDVsymbolizes GMII

transmit timing (GT) with respect to the t_GTXclock reference (K) going to the high state (H) relative to the time date input

signals (D) reaching the valid state (V) to state or setup time. Also, t_GTKHDXsymbolizes GMII transmit timing (GT) with

respect to the t_GTXclock reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X)

or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock

of a particular functional. For example, the subscript of t_GTXrepresents the GMII(G) transmit (TX) clock. For rise and fall

times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

2. This symbol is used to represent the external GTX_CLK125 signal and does not follow the original symbol naming

convention.

3. In rev. 2.0 silicon, due to errata, t_GTKHDXminimum and t_GTKHDVmaximum are not supported when the GTX_CLK is

selected. Refer to Errata QE_ENET18 in Chip Errata for the MPC8360E, Rev. 1.

This figure shows the GMII transmit AC timing diagram.

t_GTXR

t_GTX

GTX_CLK

t_GTXH

t_GTXF

TXD[7:0]

TX_EN

TX_ER

t_GTKHDX

Figure 10. GMII Transmit AC Timing Diagram

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

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27

GMII, MII, RMII, TBI, RGMII, and RTBI AC Timing Specifications

8.2.1.2

GMII Receive AC Timing Specifications

This table provides the GMII receive AC timing specifications.

Table 28. GMII Receive AC Timing Specifications

At recommended operating conditions with LV_DD/OV_DDof 3.3 V ± 10%.

Parameter/Condition

Symbol¹

Min

Typ

Max

Unit

Notes

RX_CLK clock period

t_GRX

—

40

2.0

0.2

—

8.0

—

60

—

ns

%

—

2

RX_CLK duty cycle

t_GRXH/t_GRX

RXD[7:0], RX_DV, RX_ER setup time to RX_CLK

RXD[7:0], RX_DV, RX_ER hold time to RX_CLK

RX_CLK clock rise time, (20% to 80%)

RX_CLK clock fall time, (80% to 20%)

Notes:

t_GRDVKH

t_GRDXKH

t_GRXR

ns

—

1.0

—

t_GRXF

—

1. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_GRDVKHsymbolizes GMII

receive timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the t_RXclock

reference (K) going to the high state (H) or setup time. Also, t_GRDXKLsymbolizes GMII receive timing (GR) with respect to

the time data input signals (D) went invalid (X) relative to the t_GRXclock reference (K) going to the low (L) state or hold time.

Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a

particular functional. For example, the subscript of t_GRXrepresents the GMII (G) receive (RX) clock. For rise and fall times,

the latter convention is used with the appropriate letter: R (rise) or F (fall).

2. In rev. 2.0 silicon, due to errata, t_GRDXKHminimum is 0.5 which is not compliant with the standard. Refer to Errata

QE_ENET18 in Chip Errata for the MPC8360E, Rev. 1.

This figure shows the GMII receive AC timing diagram.

t_GRXR

t_GRX

RX_CLK

t_GRXH

t_GRXF

RXD[7:0]

RX_DV

RX_ER

t_GRDXKH

t_GRDVKH

Figure 11. GMII Receive AC Timing Diagram

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GMII, MII, RMII, TBI, RGMII, and RTBI AC Timing Specifications

8.2.2

MII AC Timing Specifications

This section describes the MII transmit and receive AC timing specifications.

8.2.2.1

MII Transmit AC Timing Specifications

This table provides the MII transmit AC timing specifications.

Table 29. MII Transmit AC Timing Specifications

At recommended operating conditions with LV_DD/OV_DDof 3.3 V ± 10%.

Parameter/Condition

Symbol¹

Min

Typ

Max

Unit

TX_CLK clock period 10 Mbps

TX_CLK clock period 100 Mbps

TX_CLK duty cycle

t_MTX

t_MTXH/t_MTX

t_MTKHDX

—

35

400

40

—

5

—

65

ns

%

TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay

1

—

ns

t_MTKHDV

t_MTXR

t_MTXF

—

15

TX_CLK data clock rise time, (20% to 80%)

TX_CLK data clock fall time, (80% to 20%)

Note:

1.0

—

4.0

ns

1. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_MTKHDXsymbolizes MII transmit

timing (MT) for the time t_MTXclock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general,

the clock reference symbol representation is based on two to three letters representing the clock of a particular functional.

For example, the subscript of t_MTXrepresents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is

used with the appropriate letter: R (rise) or F (fall).

This figure shows the MII transmit AC timing diagram.

t_MTXR

t_MTX

TX_CLK

t_MTXF

t_MTXH

TXD[3:0]

TX_EN

TX_ER

t_MTKHDX

Figure 12. MII Transmit AC Timing Diagram

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

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GMII, MII, RMII, TBI, RGMII, and RTBI AC Timing Specifications

8.2.2.2

MII Receive AC Timing Specifications

This table provides the MII receive AC timing specifications.

Table 30. MII Receive AC Timing Specifications

At recommended operating conditions with LV_DD/OV_DDof 3.3 V ± 10%.

Parameter/Condition

Symbol¹

Min

Typ

Max

Unit

RX_CLK clock period 10 Mbps

RX_CLK clock period 100 Mbps

RX_CLK duty cycle

t_MRX

t_MRXH/t_MRX

—

400

40

—

ns

%

35

65

—

RXD[3:0], RX_DV, RX_ER setup time to RX_CLK

RXD[3:0], RX_DV, RX_ER hold time to RX_CLK

RX_CLK clock rise time, (20% to 80%)

RX_CLK clock fall time, (80% to 20%)

Note:

t_MRDVKH

t_MRDXKH

t_MRXR

10.0

1.0

—

ns

—

4.0

t_MRXF

—

1. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_MRDVKHsymbolizes MII receive

timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t_MRXclock reference (K)

going to the high (H) state or setup time. Also, t_MRDXKLsymbolizes MII receive timing (GR) with respect to the time data

input signals (D) went invalid (X) relative to the t_MRXclock reference (K) going to the low (L) state or hold time. Note that, in

general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.

For example, the subscript of t_MRXrepresents the MII (M) receive (RX) clock. For rise and fall times, the latter convention

is used with the appropriate letter: R (rise) or F (fall).

This figure provides the AC test load.

Output

LV_DD/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 13. AC Test Load

This figure shows the MII receive AC timing diagram.

t_MRX

t_MRXR

RX_CLK

t_MRXF

Valid Data

t_MRXH

RXD[3:0]

RX_DV

RX_ER

t_MRDVKH

t_MRDXKH

Figure 14. MII Receive AC Timing Diagram

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GMII, MII, RMII, TBI, RGMII, and RTBI AC Timing Specifications

8.2.3

RMII AC Timing Specifications

This section describes the RMII transmit and receive AC timing specifications.

8.2.3.1

RMII Transmit AC Timing Specifications

This table provides the RMII transmit AC timing specifications.

Table 31. RMII Transmit AC Timing Specifications

At recommended operating conditions with LV_DD/OV_DDof 3.3 V ± 10%.

Parameter/Condition

Symbol¹

Min

Typ

Max

Unit

REF_CLK clock

t_RMX

—

20

—

ns

%

REF_CLK duty cycle

t_{RMXH RMX}

/t

35

65

REF_CLK to RMII data TXD[1:0], TX_EN delay

t_RMTKHDX

2

—

ns

t_RMTKHDV

t_RMXR

t_RMXF

—

10

REF_CLK data clock rise time

REF_CLK data clock fall time

Note:

1.0

—

4.0

ns

1. The symbols used for timing specifications follow the pattern of t_{(first three letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_RMTKHDXsymbolizes RMII

transmit timing (RMT) for the time t_RMXclock reference (K) going high (H) until data outputs (D) are invalid (X). Note that,

in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular

functional. For example, the subscript of t_RMXrepresents the RMII(RM) reference (X) clock. For rise and fall times, the latter

convention is used with the appropriate letter: R (rise) or F (fall).

This figure shows the RMII transmit AC timing diagram.

t_RMXR

t_RMX

REF_CLK

t_RMXF

t_RMXH

TXD[1:0]

TX_EN

t_RMTKHDX

Figure 15. RMII Transmit AC Timing Diagram

8.2.3.2

RMII Receive AC Timing Specifications

This table provides the RMII receive AC timing specifications.

Table 32. RMII Receive AC Timing Specifications

At recommended operating conditions with LV_DD/OV_DDof 3.3 V ± 10%.

Parameter/Condition

Symbol¹

Min

Typ

Max

Unit

REF_CLK clock period

REF_CLK duty cycle

t_RMX

—

20

—

ns

%

t_{RMXH RMX}

/t

35

65

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GMII, MII, RMII, TBI, RGMII, and RTBI AC Timing Specifications

Table 32. RMII Receive AC Timing Specifications (continued)

At recommended operating conditions with LV_DD/OV_DDof 3.3 V ± 10%.

Parameter/Condition

Symbol¹

Min

Typ

Max

Unit

RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK

RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK

REF_CLK clock rise time

t_RMRDVKH

t_RMRDXKH

t_RMXR

4.0

2.0

1.0

—

ns

4.0

REF_CLK clock fall time

t_RMXF

Note:

1. The symbols used for timing specifications follow the pattern of t_{(first three letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_RMRDVKHsymbolizes RMII

receive timing (RMR) with respect to the time data input signals (D) reach the valid state (V) relative to the t_RMXclock

reference (K) going to the high (H) state or setup time. Also, t_RMRDXKLsymbolizes RMII receive timing (RMR) with respect

to the time data input signals (D) went invalid (X) relative to the t_RMXclock reference (K) going to the low (L) state or hold

time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a

particular functional. For example, the subscript of t_RMXrepresents the RMII (RM) reference (X) clock. For rise and fall times,

the latter convention is used with the appropriate letter: R (rise) or F (fall).

This figure provides the AC test load.

Output

LV_DD/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 16. AC Test Load

This figure shows the RMII receive AC timing diagram.

t_RMXR

t_RMX

REF_CLK

t_RMXF

Valid Data

t_RMXH

RXD[1:0]

CRS_DV

RX_ER

t_RMRDVKH

t_RMRDXKH

Figure 17. RMII Receive AC Timing Diagram

8.2.4

TBI AC Timing Specifications

This section describes the TBI transmit and receive AC timing specifications.

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8.2.4.1

TBI Transmit AC Timing Specifications

This table provides the TBI transmit AC timing specifications.

Table 33. TBI Transmit AC Timing Specifications

At recommended operating conditions with LV_DD/OV_DDof 3.3 V ± 10%.

Parameter/Condition

GTX_CLK clock period

Symbol¹

Min

Typ

Max

Unit

Notes

t_TTX

t_TTXH/t_TTX

t_TTKHDX

—

8.0

—

ns

%

—

3

GTX_CLK duty cycle

40

60

GTX_CLK to TBI data TCG[9:0] delay

1.0

—

5.0

ns

t_TTKHDV

GTX_CLK clock rise time, (20% to 80%)

GTX_CLK clock fall time, (80% to 20%)

GTX_CLK125 reference clock period

GTX_CLK125 reference clock duty cycle

Notes:

t_TTXR

t_TTXF

t_G125

—

45

—

1.0

—

ns

—

2

8.0

—

t_{G125H G125}

/t

55

—

1. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state )(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_TTKHDVsymbolizes the TBI

transmit timing (TT) with respect to the time from t_TTX(K) going high (H) until the referenced data signals (D) reach the valid

state (V) or setup time. Also, t_TTKHDXsymbolizes the TBI transmit timing (TT) with respect to the time from t_TTX(K) going

high (H) until the referenced data signals (D) reach the invalid state (X) or hold time. Note that, in general, the clock reference

symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript

of t_TTXrepresents the TBI (T) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate

letter: R (rise) or F (fall).

2. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.

3. In rev. 2.0 silicon, due to errata, t_TTKHDXminimum is 0.7 ns for UCC1. Refer to Errata QE_ENET19 in Chip Errata for the

MPC8360E, Rev. 1.

This figure shows the TBI transmit AC timing diagram.

t_TTXR

t_TTX

GTX_CLK

t_TTXH

t_TTXF

TXD[7:0]

TX_EN

TX_ER

t_TTKHDX

Figure 18. TBI Transmit AC Timing Diagram

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

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33

GMII, MII, RMII, TBI, RGMII, and RTBI AC Timing Specifications

8.2.4.2

TBI Receive AC Timing Specifications

This table provides the TBI receive AC timing specifications.

Table 34. TBI Receive AC Timing Specifications

At recommended operating conditions with LV_DD/OV_DDof 3.3 V ± 10%.

Parameter/Condition

PMA_RX_CLK clock period

Symbol¹

Min

Typ

Max

Unit

Notes

t_TRX

—

7.5

40

16.0

—

8.5

60

—

ns

%

—

2

PMA_RX_CLK skew

t_SKTRX

RX_CLK duty cycle

t_{TRXH TRX}

t_TRDVKH

t_TRDXKH

/t

—

RCG[9:0] setup time to rising PMA_RX_CLK

2.5

—

ns

RCG[9:0] hold time to rising PMA_RX_CLK

1.0

—

ns

2

RX_CLK clock rise time, V_IL(min) to V_IH(max)

RX_CLK clock fall time, V_IH(max) to V_IL(min)

Notes:

t_TRXR

t_TRXF

0.7

—

2.4

ns

—

1. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_TRDVKHsymbolizes TBI receive

timing (TR) with respect to the time data input signals (D) reach the valid state (V) relative to the t_TRXclock reference (K)

going to the high (H) state or setup time. Also, t_TRDXKHsymbolizes TBI receive timing (TR) with respect to the time data

input signals (D) went invalid (X) relative to the t_TRXclock reference (K) going to the high (H) state. Note that, in general,

the clock reference symbol representation is based on three letters representing the clock of a particular functional. For

example, the subscript of t_TRXrepresents the TBI (T) receive (RX) clock. For rise and fall times, the latter convention is used

with the appropriate letter: R (rise) or F (fall). For symbols representing skews, the subscript is skew (SK) followed by the

clock that is being skewed (TRX).

2. Setup and hold time of even numbered RCG are measured from riding edge of PMA_RX_CLK1. Setup and hold time of

odd numbered RCG are measured from riding edge of PMA_RX_CLK0.

This figure shows the TBI receive AC timing diagram.

t_TRXR

t_TRX

PMA_RX_CLK1

RCG[9:0]

t_TRXH

t_TRXF

Even RCG

Odd RCG

t_TRDVKH

t_SKTRX

t_TRDXKH

PMA_RX_CLK0

t_TRDXKH

t_TRXH

t_TRDVKH

Figure 19. TBI Receive AC Timing Diagram

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GMII, MII, RMII, TBI, RGMII, and RTBI AC Timing Specifications

8.2.5

RGMII and RTBI AC Timing Specifications

This table presents the RGMII and RTBI AC timing specifications.

Table 35. RGMII and RTBI AC Timing Specifications

At recommended operating conditions with LV_DDof 2.5 V ± 5%.

Parameter/Condition

Symbol¹

Min

Typ

Max

Unit

Notes

Data to clock output skew (at transmitter)

Data to clock input skew (at receiver)

t_SKRGTKHDX

t_SKRGTKHDV

–0.5

—

0.5

ns

7

t_SKRGDXKH

t_SKRGDVKH

1.0

—

2.6

ns

2

Clock cycle duration

t_RGT

7.2

45

40

—

8.0

50

—

8.8

55

ns

%

3

4, 5

3, 5

—

Duty cycle for 1000Base-T

Duty cycle for 10BASE-T and 100BASE-TX

Rise time (20–80%)

t_{RGTH RGT}

/t

t_RGTH/t_RGT

60

%

t_RGTR

t_RGTF

t_G125

0.75

—

ns

%

Fall time (20–80%)

—

GTX_CLK125 reference clock period

GTX_CLK125 reference clock duty cycle

Notes:

—

8.0

—

6

t_{G125H G125}

/t

47

53

—

1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent

RGMII and RTBI timing. For example, the subscript of t_RGTrepresents the TBI (T) receive (Rx) clock. Note also that the

notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews,

the subscript is skew (SK) followed by the clock that is being skewed (RGT).

2. This implies that PC board design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns can

be added to the associated clock signal.

3. For 10 and 100 Mbps, t_RGTscales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.

4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as

long as the minimum duty cycle is not violated and stretching occurs for no more than three t_RGTof the lowest speed

transitioned between.

5. Duty cycle reference is LV_DD/2.

6. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.

7. In rev. 2.0 silicon, due to errata, t_SKRGTKHDXminimum is –2.3 ns and t_SKRGTKHDVmaximum is 1 ns for UCC1, 1.2 ns for

UCC2 option 1, and 1.8 ns for UCC2 option 2. In rev. 2.1 silicon, due to errata, t_SKRGTKHDXminimum is –0.65 ns for UCC2

option 1 and –0.9 for UCC2 option 2, and t_SKRGTKHDVmaximum is 0.75 ns for UCC1 and UCC2 option 1 and 0.85 for UCC2

option 2. Refer to Errata QE_ENET10 in Chip Errata for the MPC8360E, Rev. 1. UCC1 does meet t_SKRGTKHDXminimum for

rev. 2.1 silicon.

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

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35

Ethernet Management Interface Electrical Characteristics

This figure shows the RGMII and RTBI AC timing and multiplexing diagrams.

t_RGT

t_RGTH

GTX_CLK

(At Transmitter)

t_SKRGTKHDX

TXD[8:5][3:0]

TXD[7:4][3:0]

TXD[8:5]

TXD[7:4]

TXD[3:0]

TXD[9]

TXERR

TXD[4]

TXEN

TX_CTL

t_SKRGTKHDX

TX_CLK

(At PHY)

RXD[8:5][3:0]

RXD[7:4][3:0]

RXD[8:5]

RXD[7:4]

RXD[3:0]

t_SKRGTKHDX

RXD[9]

RXERR

RXD[4]

RXDV

RX_CTL

t_SKRGTKHDX

RX_CLK

(At PHY)

Figure 20. RGMII and RTBI AC Timing and Multiplexing Diagrams

8.3

Ethernet Management Interface Electrical Characteristics

The electrical characteristics specified here apply to MII management interface signals MDIO (management data input/output)

and MDC (management data clock). The electrical characteristics for GMII, RGMII, TBI, and RTBI are specified in

Section 8.1, “Three-Speed Ethernet Controller (10/100/1000 Mbps)— GMII/MII/RMII/TBI/RGMII/RTBI Electrical

Characteristics.”

8.3.1

MII Management DC Electrical Characteristics

The MDC and MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics for MDIO and MDC

are provided in this table.

Table 36. MII Management DC Electrical Characteristics When Powered at 3.3 V

Parameter

Symbol

Conditions

Min

Max

Unit

Supply voltage (3.3 V)

Output high voltage

Output low voltage

Input high voltage

Input low voltage

Input current

OV_DD

V_OH

V_OL

V_IH

—

2.97

2.10

GND

2.00

—

3.63

OV_DD+ 0.3

0.50

V

I_OH= –1.0 mA OV_DD= Min

I_OL= 1.0 mA

OV_DD= Min

V

—

V

V_IL

0.80

V

I_IN

0 V ≤V_IN≤OV_DD

—

±10

μA

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Ethernet Management Interface Electrical Characteristics

8.3.2

MII Management AC Electrical Specifications

This table provides the MII management AC timing specifications.

Table 37. MII Management AC Timing Specifications

At recommended operating conditions with LV_DDis 3.3 V ± 10%.

Parameter/Condition

MDC frequency

Symbol¹

Min

Typ

Max

Unit

Notes

f_MDC

t_MDC

—

32

2.5

400

—

MHz

ns

2

—

3

MDC period

MDC clock pulse width high

MDC to MDIO delay

t_MDCH

ns

t_MDTKHDX

t_MDTKHDV

10

—

110

ns

MDIO to MDC setup time

MDIO to MDC hold time

MDC rise time

t_MDRDVKH

t_MDRDXKH

t_MDCR

10

0

—

10

ns

—

MDC fall time

t_MDHF

Notes:

1. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_MDKHDXsymbolizes

management data timing (MD) for the time t_MDCfrom clock reference (K) high (H) until data outputs (D) are invalid (X) or

data hold time. Also, t_MDRDVKHsymbolizes management data timing (MD) with respect to the time data input signals (D)

reach the valid state (V) relative to the t_MDCclock reference (K) going to the high (H) state or setup time. For rise and fall

times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

2. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the maximum frequency is 8.3 MHz

and the minimum frequency is 1.2 MHz; for a csb_clk of 375 MHz, the maximum frequency is 11.7 MHz and the minimum

frequency is 1.7 MHz).

3. This parameter is dependent on the ce_clk speed (that is, for a ce_clk of 200 MHz, the delay is 90 ns and for a ce_clk of

300 MHz, the delay is 63 ns).

This figure shows the MII management AC timing diagram.

t_MDCR

t_MDC

MDC

t_MDCH

t_MDHF

MDIO

(Input)

t_MDRDVKH

t_MDRDXKH

MDIO

(Output)

t_MDTKHDX

Figure 21. MII Management Interface Timing Diagram

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

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Local Bus DC Electrical Characteristics

8.3.3

IEEE 1588 Timer AC Specifications

This table provides the IEEE 1588 timer AC specifications.

Table 38. IEEE 1588 Timer AC Specifications

Parameter

Symbol

Min

Max

Unit

Notes

Timer clock frequency

t_TMRCK

t_TMRCKS

t_TMRCKH

t_GCLKNV

t_TMRAL

0

70

—

6

MHz

—

1

2, 3

—

Input setup to timer clock

Input hold from timer clock

Output clock to output valid

Timer alarm to output valid

Notes:

—

0

—

ns

—

2

1. The timer can operate on rtc_clock or tmr_clock. These clocks get muxed and any one of them can be selected. The

minimum and maximum requirement for both rtc_clock and tmr_clock are the same.

2. These are asynchronous signals.

3. Inputs need to be stable at least one TMR clock.

9

Local Bus

This section describes the DC and AC electrical specifications for the local bus interface of the MPC8360E/58E.

9.1

Local Bus DC Electrical Characteristics

This table provides the DC electrical characteristics for the local bus interface.

Table 39. Local Bus DC Electrical Characteristics

Parameter

Symbol

Min

Max

Unit

High-level input voltage

Low-level input voltage

V_IH

V_IL

2

–0.3

OV_DD+ 0.3

V

0.8

—

High-level output voltage, I_OH= –100 μA

Low-level output voltage, I_OL= 100 μA

Input current

V_OH

V_OL

I_IN

OV_DD– 0.4

—

V

0.2

±10

V

—

μA

9.2

Local Bus AC Electrical Specifications

This table describes the general timing parameters of the local bus interface of the device.

Table 40. Local Bus General Timing Parameters—DLL Enabled

Parameter

Symbol¹

Min

Max

Unit

Notes

Local bus cycle time

t_LBK

7.5

1.7

1.9

1.0

—

ns

2

Input setup to local bus clock (except LUPWAIT)

LUPWAIT input setup to local bus clock

t_LBIVKH1

t_LBIVKH2

t_LBIXKH1

3, 4

Input hold from local bus clock (except LUPWAIT)

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Local Bus AC Electrical Specifications

Table 40. Local Bus General Timing Parameters—DLL Enabled (continued)

Parameter

Symbol¹

Min

Max

Unit

Notes

LUPWAIT input hold from local bus clock

t_LBIXKH2

t_LBOTOT1

t_LBOTOT2

t_LBOTOT3

t_LBKHLR

1.0

1.5

3.0

2.5

—

ns

3, 4

5

LALE output fall to LAD output transition (LATCH hold time)

Local bus clock to LALE rise

—

6

—

7

4.5

—

3

Local bus clock to output valid (except LAD/LDP and LALE)

Local bus clock to data valid for LAD/LDP

t_LBKHOV1

t_LBKHOV2

t_LBKHOV3

t_LBKHOX1

t_LBKHOX2

t_LBKHOZ

—

Local bus clock to address valid for LAD

—

3

Output hold from local bus clock (except LAD/LDP and LALE)

Output hold from local bus clock for LAD/LDP

Local bus clock to output high impedance for LAD/LDP

Notes:

1.0

—

3

—

3

3.8

8

1. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_LBIXKH1symbolizes local bus

timing (LB) for the input (I) to go invalid (X) with respect to the time the t_LBKclock reference (K) goes high (H), in this case

for clock one (1). Also, t_LBKHOXsymbolizes local bus timing (LB) for the t_LBKclock reference (K) to go high (H), with respect

to the output (O) going invalid (X) or output hold time.

2. All timings are in reference to rising edge of LSYNC_IN.

3. All signals are measured from OV_DD/2 of the rising edge of LSYNC_IN to 0.4 × OV_DDof the signal in question for 3.3-V

signaling levels.

4. Input timings are measured at the pin.

5. t_LBOTOT1should be used when RCWH[LALE] is not set and when the load on LALE output pin is at least 10 pF less than

the load on LAD output pins.

6. t_LBOTOT2should be used when RCWH[LALE] is set and when the load on LALE output pin is at least 10 pF less than the

load on LAD output pins.

7. t_LBOTOT3should be used when RCWH[LALE] is set and when the load on LALE output pin equals to the load on LAD output

pins.

8. For purposes of active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

This table describes the general timing parameters of the local bus interface of the device.

Table 41. Local Bus General Timing Parameters—DLL Bypass Mode⁹

Parameter

Symbol¹

Min

Max

Unit

Notes

Local bus cycle time

t_LBK

15

7

—

ns

2

3, 4

5

Input setup to local bus clock

t_LBIVKH

t_LBIXKH

Input hold from local bus clock

1.0

1.5

3

LALE output fall to LAD output transition (LATCH hold time)

t_LBOTOT1

t_LBOTOT2

t_LBOTOT3

6

2.5

7

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

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Local Bus AC Electrical Specifications

Table 41. Local Bus General Timing Parameters—DLL Bypass Mode⁹(continued)

Parameter

Local bus clock to output valid

Symbol¹

Min

Max

Unit

Notes

t_LBKHOV

t_LBKHOZ

—

3

4

ns

3

8

Local bus clock to output high impedance for LAD/LDP

Notes:

1. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_LBIXKH1symbolizes local bus

timing (LB) for the input (I) to go invalid (X) with respect to the time the t_LBKclock reference (K) goes high (H), in this case

for clock one (1). Also, t_LBKHOXsymbolizes local bus timing (LB) for the t_LBKclock reference (K) to go high (H), with respect

to the output (O) going invalid (X) or output hold time.

2. All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or rising edge of

LCLK0 (for all other inputs).

3. All signals are measured from OV_DD/2 of the rising/falling edge of LCLK0 to 0.4 × OV_DDof the signal in question for 3.3-V

signaling levels.

4. Input timings are measured at the pin.

5. t_LBOTOT1should be used when RCWH[LALE] is not set and when the load on LALE output pin is at least 10 pF less than

the load on LAD output pins.

6. t_LBOTOT2should be used when RCWH[LALE] is set and when the load on LALE output pin is at least 10 pF less than the

load on LAD output pins.

7. t_LBOTOT3should be used when RCWH[LALE] is set and when the load on LALE output pin equals to the load on LAD output

pins.

8. For purposes of active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

9. DLL bypass mode is not recommended for use at frequencies above 66 MHz.

This figure provides the AC test load for the local bus.

OV_DD/2

Output

Z₀= 50 Ω

R_L= 50 Ω

Figure 22. Local Bus C Test Load

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Freescale Semiconductor

Local Bus AC Electrical Specifications

These figures show the local bus signals.

LSYNC_IN

t_LBIXKH

t_LBIVKH

Input Signals:

LAD[0:31]/LDP[0:3]

t_LBIXKH

t_LBKHOX

t_LBKHOV

t_LBKHLR

Output Signals:

LSDA10/LSDWE/LSDRAS/

LSDCAS/LSDDQM[0:3]

LA[27:31]/LBCTL/LBCKE/LOE/

t_LBKHOZ

t_LBKHOX

Output (Data) Signals:

LAD[0:31]/LDP[0:3]

t_LBKHOZ

t_LBKHOX

Output (Address) Signal:

LAD[0:31]

t_LBOTOT

LALE

Figure 23. Local Bus Signals, Nonspecial Signals Only (DLL Enabled)

LCLK[n]

t_LBIXKH

t_LBIVKH

Input Signals:

LAD[0:31]/LDP[0:3]

t_LBIXKH

t_LBIVKH

Input Signal:

LGTA

t_LBIXKH

t_LBKHOV

Output Signals:

LSDA10/LSDWE/LSDRAS/

LSDCAS/LSDDQM[0:3]

LA[27:31]/LBCTL/LBCKE/LOE/

t_LBKHOZ

t_LBKHOV

Output Signals:

LAD[0:31]/LDP[0:3]

t_LBOTOT

LALE

Figure 24. Local Bus Signals, Nonspecial Signals Only (DLL Bypass Mode)

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

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Local Bus AC Electrical Specifications

LSYNC_IN

T1

T3

t_LBKHOZ1

t_LBKHOV1

GPCM Mode Output Signals:

LCS[0:3]/LWE

t_LBIXKH2

t_LBIVKH2

UPM Mode Input Signal:

LUPWAIT

t_LBIXKH1

t_LBIVKH1

Input Signals:

LAD[0:31]/LDP[0:3]

t_LBKHOZ1

t_LBKHOV1

UPM Mode Output Signals:

LCS[0:3]/LBS[0:3]/LGPL[0:5]

Figure 25. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 2 (DLL Enabled)

LCLK

T1

T3

t_LBKHOZ

t_LBKHOV

GPCM Mode Output Signals:

LCS[0:3]/LWE

t_LBIXKH

t_LBIVKH

UPM Mode Input Signal:

LUPWAIT

t_LBIXKH

t_LBIVKH

Input Signals:

LAD[0:31]/LDP[0:3]

(DLL Bypass Mode)

t_LBKHOZ

t_LBKHOV

UPM Mode Output Signals:

LCS[0:3]/LBS[0:3]/LGPL[0:5]

Figure 26. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 2 (DLL Bypass Mode)

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Local Bus AC Electrical Specifications

LCLK

T1

T2

T3

T4

t_LBKHOZ

t_LBKHOV

GPCM Mode Output Signals:

LCS[0:3]/LWE

t_LBIXKH

t_LBIVKH

UPM Mode Input Signal:

LUPWAIT

t_LBIXKH

t_LBIVKH

Input Signals:

LAD[0:31]/LDP[0:3]

(DLL Bypass Mode)

t_LBKHOZ

t_LBKHOV

UPM Mode Output Signals:

LCS[0:3]/LBS[0:3]/LGPL[0:5]

Figure 27. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4 (DLL Bypass Mode)

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JTAG DC Electrical Characteristics

LSYNC_IN

T1

T2

T3

T4

t_LBKHOZ1

t_LBKHOV1

GPCM Mode Output Signals:

LCS[0:3]/LWE

t_LBIXKH2

t_LBIVKH2

UPM Mode Input Signal:

LUPWAIT

t_LBIXKH1

t_LBIVKH1

Input Signals:

LAD[0:31]/LDP[0:3]

t_LBKHOZ1

t_LBKHOV1

UPM Mode Output Signals:

LCS[0:3]/LBS[0:3]/LGPL[0:5]

Figure 28. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4 (DLL Enabled)

10 JTAG

This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the MPC8360E/58E.

10.1 JTAG DC Electrical Characteristics

This table provides the DC electrical characteristics for the IEEE 1149.1 (JTAG) interface of the device.

Table 42. JTAG interface DC Electrical Characteristics

Characteristic

Output high voltage

Symbol

Condition

Min

Max

Unit

V_OH

V_OL

I_OH= –6.0 mA

I_OL= 6.0 mA

2.4

—

0.5

V

Output low voltage

Input high voltage

Input low voltage

Input current

V

I

= 3.2 mA

OL

—

0.4

V

OL

V_IH

V_IL

I_IN

—

2.5

–0.3

—

OV_DD+ 0.3

0.8

V

0 V ≤V_IN≤OV_DD

±10

μA

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JTAG AC Electrical Characteristics

10.2 JTAG AC Electrical Characteristics

This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the device.

This table provides the JTAG AC timing specifications as defined in Figure 30 through Figure 33.

1

Table 43. JTAG AC Timing Specifications (Independent of CLKIN)

At recommended operating conditions (see Table 2).

Parameter

Symbol ²

Min

Max

Unit

Notes

JTAG external clock frequency of operation

JTAG external clock cycle time

JTAG external clock duty cycle

JTAG external clock rise and fall times

TRST assert time

f_JTG

t_JTG

0

33.3

—

MHz

ns

—

3

30

45

0

t

_JTKHKL/t_JTG

55

2

%

t_JTGR& t_JTGF

t_TRST

ns

25

—

ns

Input setup times:

ns

4

Boundary-scan data

TMS, TDI

t_JTDVKH

t_JTIVKH

4

—

Input hold times:

Valid times:

ns

4

5

Boundary-scan data

TMS, TDI

t_JTDXKH

t_JTIXKH

10

—

Boundary-scan data

TDO

t_JTKLDV

t_JTKLOV

2

11

Output hold times:

5

Boundary-scan data

TDO

t_JTKLDX

t_JTKLOX

2

—

JTAG external clock to output high impedance:

Boundary-scan data

TDO

5, 6

t_JTKLDZ

t_JTKLOZ

2

19

9

Notes:

1. All outputs are measured from the midpoint voltage of the falling/rising edge of t_TCLKto the midpoint of the signal in

question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see

Figure 22). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

2. The symbols used for timing specifications herein follow the pattern of t_{(first two letters of functional block)(signal)(state)}

_{(reference)(state)}for inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_JTDVKH

symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to

the t_JTGclock reference (K) going to the high (H) state or setup time. Also, t_JTDXKHsymbolizes JTAG timing (JT) with respect

to the time data input signals (D) went invalid (X) relative to the t_JTGclock reference (K) going to the high (H) state. Note

that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular

functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

4. Non-JTAG signal input timing with respect to t_TCLK

.

5. Non-JTAG signal output timing with respect to t_TCLK

.

6. Guaranteed by design and characterization.

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JTAG AC Electrical Characteristics

This figure provides the AC test load for TDO and the boundary-scan outputs of the device.

Z₀= 50 Ω

OV_DD/2

Output

R_L= 50 Ω

Figure 29. AC Test Load for the JTAG Interface

This figure provides the JTAG clock input timing diagram.

JTAG

External Clock

VM

t_JTKHKL

VM

t_JTGR

t_JTGF

t_JTG

VM = Midpoint Voltage (OV /2)

DD

Figure 30. JTAG Clock Input Timing Diagram

This figure provides the TRST timing diagram.

TRST

VM

t_TRST

VM = Midpoint Voltage (OV /2)

DD

Figure 31. TRST Timing Diagram

This figure provides the boundary-scan timing diagram.

JTAG

VM

External Clock

t_JTDVKH

t_JTDXKH

Boundary

Data Inputs

Input

Data Valid

t_JTKLDV

t_JTKLDX

Boundary

Data Outputs

Output Data Valid

t_JTKLDZ

Boundary

Output Data Valid

Data Outputs

VM = Midpoint Voltage (OV /2)

DD

Figure 32. Boundary-Scan Timing Diagram

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I2C DC Electrical Characteristics

This figure provides the test access port timing diagram.

JTAG

VM

External Clock

t_JTIVKH

t_JTIXKH

Input

Data Valid

TDI, TMS

t_JTKLOV

t_JTKLOX

TDO

Output Data Valid

t_JTKLOZ

TDO

Output Data Valid

VM = Midpoint Voltage (OV /2)

DD

Figure 33. Test Access Port Timing Diagram

11 I²C

2

This section describes the DC and AC electrical characteristics for the I C interface of the MPC8360E/58E.

2

11.1 I C DC Electrical Characteristics

2

This table provides the DC electrical characteristics for the I C interface of the device.

2

Table 44. I C DC Electrical Characteristics

At recommended operating conditions with OV_DDof 3.3 V ± 10%.

Parameter

Symbol

Min

Max

Unit

Notes

Input high voltage level

Input low voltage level

Low level output voltage

V_IH

V_IL

0.7 × OV_DD

OV_DD+ 0.3

0.3 × OV_DD

0.4

V

—

1

–0.3

0

V_OL

V

Output fall time from V_IH(min) to V_IL(max) with a bus

capacitance from 10 to 400 pF

t

20 + 0.1 × C_B

250

ns

2

I2KLKV

Pulse width of spikes which must be suppressed by the input

filter

t_I2KHKL

0

50

ns

3

Capacitance for each I/O pin

C_I

—

10

pF

—

4

Input current (0 V ≤V_IN≤OV_DD

)

I_IN

±10

μA

Notes:

1. Output voltage (open drain or open collector) condition = 3 mA sink current.

2. C_B= capacitance of one bus line in pF.

3. Refer to the MPC8360E Integrated Communications Processor Reference Manual for information on the digital filter used.

4. I/O pins obstruct the SDA and SCL lines if OV_DDis switched off.

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I2C AC Electrical Specifications

2

11.2 I C AC Electrical Specifications

2

This table provides the AC timing parameters for the I C interface of the device.

2

Table 45. I C AC Electrical Specifications

All values refer to V_IH(min) and V_IL(max) levels (see Table 44).

Parameter

Symbol¹

Min

Max

Unit

Note

SCL clock frequency

f_I2C

t_I2CL

0

400

—

kHz

μs

2

Low period of the SCL clock

1.3

0.6

—

High period of the SCL clock

t_I2CH

—

μs

Setup time for a repeated START condition

t_I2SVKH

t_I2SXKL

—

μs

Hold time (repeated) START condition (after this period, the

first clock pulse is generated)

—

μs

Data setup time

t_I2DVKH

t_I2DXKL

100

—

ns

3

Data hold time:

μs

—

CBUS compatible masters

I²C bus devices

—

0²

—

0.9³

4

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

Set-up time for STOP condition

t_I2CR

t_I2CF

20 + 0.1 C_b

0.6

300

—

ns

μs

V

—

t

I2PVKH

Bus free time between a STOP and START condition

t_I2KHDX

V_NL

1.3

—

Noise margin at the LOW level for each connected device

(including hysteresis)

0.1 × OV_DD

—

Noise margin at the HIGH level for each connected device

(including hysteresis)

V_NH

0.2 × OV_DD

—

V

—

Notes:

1. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional}

_{block)(signal)(state)(reference)(state)}for inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For

example, t_I2DVKHsymbolizes I²C timing (I2) with respect to the time data input signals (D) reach the valid state (V)

relative to the t_I2Cclock reference (K) going to the high (H) state or setup time. Also, t_I2SXKLsymbolizes I²C timing

(I2) for the time that the data with respect to the start condition (S) went invalid (X) relative to the t_I2Cclock

reference (K) going to the low (L) state or hold time. Also, t_I2PVKHsymbolizes I²C timing (I2) for the time that the

data with respect to the stop condition (P) reaching the valid state (V) relative to the t_I2Cclock reference (K) going

to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter:

R (rise) or F (fall).

2. The device provides a hold time of at least 300 ns for the SDA signal (referred to the V_IHmin of the SCL signal) to

bridge the undefined region of the falling edge of SCL.

3. The maximum t_I2DVKHhas only to be met if the device does not stretch the LOW period (t_I2CL) of the SCL signal.

4. C_B= capacitance of one bus line in pF.

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PCI DC Electrical Characteristics

2

This figure provides the AC test load for the I C.

OV_DD/2

Output

Z₀= 50 Ω

R_L= 50 Ω

2

Figure 34. I C AC Test Load

2

This figure shows the AC timing diagram for the I C bus.

SDA

t_I2CF

t_I2CL

t_I2DVKH

t_I2KHKL

t_I2CF

t_I2SXKL

t_I2CR

SCL

t_I2SXKL

t_I2CH

t_I2SVKH

t_I2PVKH

t_I2DXKL

S

Sr

P

S

2

Figure 35. I C Bus AC Timing Diagram

12 PCI

This section describes the DC and AC electrical specifications for the PCI bus of the MPC8360E/58E.

12.1 PCI DC Electrical Characteristics

This table provides the DC electrical characteristics for the PCI interface of the device.

Table 46. PCI DC Electrical Characteristics

Parameter

High-level input voltage

Symbol

Test Condition

Min

Max

Unit

V_IH

V_IL

V_OUT≥ V_OH(min) or

V_OUT≤V_OL(max)

I_OH= –500 μA

0.5 × OV_DD

OV_DD+ 0.5

0.3 × OV_DD

—

V

Low-level input voltage

High-level output voltage

Low-level output voltage

Input current

-0.5

V_OH

V_OL

I_IN

0.9 × OV_DD

V

I_OL= 1500 μA

—

0.1 × OV_DD

±10

V

0 V ≤V_IN¹≤OV_DD

μA

12.2 PCI AC Electrical Specifications

This section describes the general AC timing parameters of the PCI bus of the device. Note that the PCI_CLK or PCI_SYNC_IN

signal is used as the PCI input clock depending on whether the device is configured as a host or agent device. This table provides

the PCI AC timing specifications at 66 MHz.

.

Table 47. PCI AC Timing Specifications at 66 MHz

Parameter

Symbol¹

Min

Max

Unit

Notes

Clock to output valid

t_PCKHOV

t_PCKHOX

—

1

6.0

—

ns

2, 5

2

Output hold from clock

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PCI AC Electrical Specifications

Table 47. PCI AC Timing Specifications at 66 MHz (continued)

Parameter

Symbol¹

Min

Max

Unit

Notes

Clock to output high impedance

Input setup to clock

Input hold from clock

Notes:

t_PCKHOZ

t_PCIVKH

t_PCIXKH

—

14

—

ns

2, 3

2, 4

3.0

0.3

2, 4, 6

1. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_PCIVKHsymbolizes PCI timing

(PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, t_SYS, reference

(K) going to the high (H) state or setup time. Also, t_PCRHFVsymbolizes PCI timing (PC) with respect to the time hard reset

(R) went high (H) relative to the frame signal (F) going to the valid (V) state.

2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.

3. For purposes of active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

4. Input timings are measured at the pin.

5. In rev. 2.0 silicon, due to errata, t_PCIHOVmaximum is 6.6 ns. Refer to Errata PCI21 in Chip Errata for the MPC8360E, Rev. 1.

6. In rev. 2.0 silicon, due to errata, t_PCIXKHminimum is 1 ns. Refer to Errata PCI17 in Chip Errata for the MPC8360E, Rev. 1.

Table 48. PCI AC Timing Specifications at 33 MHz

Parameter

Symbol¹

Min

Max

Unit

Notes

Clock to output valid

t_PCKHOV

t_PCKHOX

t_PCKHOZ

t_PCIVKH

t_PCIXKH

—

2

11

—

14

—

ns

2

Output hold from clock

Clock to output high impedance

Input setup to clock

Input hold from clock

Notes:

—

2, 3

2, 2

2, 4, 5

7.0

0.3

1. The symbols used for timing specifications herein follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}

for inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_PCIVKHsymbolizes PCI

timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, t_SYS

,

reference (K) going to the high (H) state or setup time. Also, t_PCRHFVsymbolizes PCI timing (PC) with respect to the time

hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.

2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.

3. For purposes of active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

4. Input timings are measured at the pin.

5. In rev. 2.0 silicon, due to errata, t_PCIXKHminimum is 1 ns. Refer to Errata PCI17 in Chip Errata for the MPC8360E, Rev. 1.

This figure provides the AC test load for PCI.

OV_DD/2

Output

Z₀= 50 Ω

R_L= 50 Ω

Figure 36. PCI AC Test Load

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Timers DC Electrical Characteristics

This figure shows the PCI input AC timing conditions.

CLK

t_PCIVKH

t_PCIXKH

Input

Figure 37. PCI Input AC Timing Measurement Conditions

This figure shows the PCI output AC timing conditions.

CLK

t_PCKHOV

t_PCKHOX

Output Delay

t_PCKHOZ

High-Impedance

Output

Figure 38. PCI Output AC Timing Measurement Condition

13 Timers

This section describes the DC and AC electrical specifications for the timers of the MPC8360E/58E.

13.1 Timers DC Electrical Characteristics

This table provides the DC electrical characteristics for the device timer pins, including TIN, TOUT, TGATE, and RTC_CLK.

Table 49. Timers DC Electrical Characteristics

Characteristic

Output high voltage

Symbol

Condition

Min

Max

Unit

V_OH

V_OL

I_OH= –6.0 mA

I_OL= 6.0 mA

I_OL= 3.2 mA

—

2.4

—

0.5

V

Output low voltage

Input high voltage

Input low voltage

Input current

V

—

0.4

V

OL

V_IH

V_IL

I_IN

2.0

–0.3

—

OV_DD+ 0.3

0.8

V

—

V

0 V ≤V_IN≤OV_DD

±10

μA

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Timers AC Timing Specifications

13.2 Timers AC Timing Specifications

This table provides the timer input and output AC timing specifications.

1

Table 50. Timers Input AC Timing Specifications

Characteristic

Symbol²

Typ

Unit

Timers inputs—minimum pulse width

Notes:

t_TIWID

20

ns

1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are

measured at the pin.

2. Timers inputs and outputs are asynchronous to any visible clock. Timers outputs should be synchronized before use by any

external synchronous logic. Timers inputs are required to be valid for at least t_TIWIDns to ensure proper operation.

This figure provides the AC test load for the timers.

Output

OV_DD/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 39. Timers AC Test Load

14 GPIO

This section describes the DC and AC electrical specifications for the GPIO of the MPC8360E/58E.

14.1 GPIO DC Electrical Characteristics

This table provides the DC electrical characteristics for the device GPIO.

Table 51. GPIO DC Electrical Characteristics

Characteristic

Output high voltage

Symbol

Condition

Min

Max

Unit

Notes

V_OH

V_OL

I_OH= –6.0 mA

I_OL= 6.0 mA

2.4

—

0.5

V

1

Output low voltage

Input high voltage

Input low voltage

Input current

V

I

= 3.2 mA

OL

—

0.4

V

1

OL

V_IH

V_IL

I_IN

—

2.0

–0.3

—

OV_DD+ 0.3

0.8

V

1

V

—

0 V ≤V_IN≤OV_DD

±10

μA

Note:

1. This specification applies when operating from 3.3-V supply.

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GPIO AC Timing Specifications

14.2 GPIO AC Timing Specifications

This table provides the GPIO input and output AC timing specifications.

1

Table 52. GPIO Input AC Timing Specifications

Characteristic

Symbol²

Typ

Unit

GPIO inputs—minimum pulse width

t_PIWID

20

ns

Notes:

1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are

measured at the pin.

2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any

external synchronous logic. GPIO inputs are required to be valid for at least t_PIWIDns to ensure proper operation.

This figure provides the AC test load for the GPIO.

Output

OV_DD/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 40. GPIO AC Test Load

15 IPIC

This section describes the DC and AC electrical specifications for the external interrupt pins of the MPC8360E/58E.

15.1 IPIC DC Electrical Characteristics

This table provides the DC electrical characteristics for the external interrupt pins of the IPIC.

Table 53. IPIC DC Electrical Characteristics

Characteristic

Symbol

Condition

Min

Max

Unit

Input high voltage

Input low voltage

Input current

V_IH

V_IL

I_IN

—

2.0

–0.3

—

OV_DD+ 0.3

V

0.8

±10

0.5

0.4

—

μA

V

Output low voltage

Notes:

V_OL

I_OL= 6.0 mA

I_OL= 3.2 mA

—

V

—

V

OL

1. This table applies for pins IRQ[0:7], IRQ_OUT, MCP_OUT, and CE ports Interrupts.

2. IRQ_OUT and MCP_OUT are open drain pins, thus V_OHis not relevant for those pins.

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IPIC AC Timing Specifications

15.2 IPIC AC Timing Specifications

This table provides the IPIC input and output AC timing specifications.

1

Table 54. IPIC Input AC Timing Specifications

Characteristic

Symbol²

Min

Unit

IPIC inputs—minimum pulse width

t_PIWID

20

ns

Notes:

1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are

measured at the pin.

2. IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by any

external synchronous logic. IPIC inputs are required to be valid for at least t_PIWIDns to ensure proper operation when

working in edge triggered mode.

16 SPI

This section describes the DC and AC electrical specifications for the SPI of the MPC8360E/58E.

16.1 SPI DC Electrical Characteristics

This table provides the DC electrical characteristics for the device SPI.

Table 55. SPI DC Electrical Characteristics

Characteristic

Output high voltage

Symbol

Condition

Min

Max

Unit

V_OH

V_OL

I_OH= –6.0 mA

I_OL= 6.0 mA

2.4

—

0.5

V

Output low voltage

Input high voltage

Input low voltage

Input current

V

I

= 3.2 mA

OL

—

0.4

V

OL

V_IH

V_IL

I_IN

—

2.0

–0.3

—

OV_DD+ 0.3

0.8

V

0 V ≤V_IN≤OV_DD

±10

μA

16.2 SPI AC Timing Specifications

This table and provide the SPI input and output AC timing specifications.

1

Table 56. SPI AC Timing Specifications

Characteristic

Symbol²

t_NIKHOX

Min

Max

Unit

SPI outputs—Master mode (internal clock) delay

0.3

—

8

ns

t_NIKHOV

SPI outputs—Slave mode (external clock) delay

t_NEKHOX

t_NEKHOV

2

—

8

ns

SPI inputs—Master mode (internal clock) input setup time

SPI inputs—Master mode (internal clock) input hold time

SPI inputs—Slave mode (external clock) input setup time

t_NIIVKH

t_NIIXKH

t_NEIVKH

8

0

4

—

ns

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SPI AC Timing Specifications

1

Table 56. SPI AC Timing Specifications

Characteristic

Symbol²

Min

Max

Unit

SPI inputs—Slave mode (external clock) input hold time

t_NEIXKH

2

—

ns

Notes:

1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings

are measured at the pin.

2. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_NIKHOVsymbolizes the NMSI

outputs internal timing (NI) for the time t_SPImemory clock reference (K) goes from the high state (H) until outputs (O) are

valid (V).

This figure provides the AC test load for the SPI.

Output

OV_DD/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 41. SPI AC Test Load

These figures represent the AC timing from Table 56. Note that although the specifications generally reference the rising edge

of the clock, these AC timing diagrams also apply when the falling edge is the active edge.

This figure shows the SPI timing in slave mode (external clock).

SPICLK (Input)

t_NEIXKH

t_NEIVKH

Input Signals:

SPIMOSI

(See Note)

t_NEKHOV

Output Signals:

SPIMISO

(See Note)

Note: The clock edge is selectable on SPI.

Figure 42. SPI AC Timing in Slave Mode (External Clock) Diagram

This figure shows the SPI timing in Master mode (internal clock).

SPICLK (Output)

t_NIIXKH

t_NIIVKH

Input Signals:

SPIMISO

(See Note)

t_NIKHOV

Output Signals:

SPIMOSI

(See Note)

Note: The clock edge is selectable on SPI.

Figure 43. SPI AC Timing in Master Mode (Internal Clock) Diagram

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TDM/SI DC Electrical Characteristics

17 TDM/SI

This section describes the DC and AC electrical specifications for the time-division-multiplexed and serial interface of the

MPC8360E/58E.

17.1 TDM/SI DC Electrical Characteristics

This table provides the DC electrical characteristics for the device TDM/SI.

Table 57. TDM/SI DC Electrical Characteristics

Characteristic

Output high voltage

Symbol

Condition

Min

Max

Unit

V_OH

V_OL

V_IH

V_IL

I_OH= –2.0 mA

I_OL= 3.2 mA

—

2.4

—

0.5

V

Output low voltage

Input high voltage

Input low voltage

Input current

2.0

–0.3

—

OV_DD+ 0.3

0.8

V

—

V

I_IN

0 V ≤V_IN≤OV_DD

±10

μA

17.2 TDM/SI AC Timing Specifications

This table provides the TDM/SI input and output AC timing specifications.

1

Table 58. TDM/SI AC Timing Specifications

Characteristic

TDM/SI outputs—External clock delay

Symbol²

Min

Max³

Unit

t_SEKHOV

t_SEKHOX

t_SEIVKH

t_SEIXKH

2

5

2

10

—

ns

TDM/SI outputs—External clock high impedance

TDM/SI inputs—External clock input setup time

TDM/SI inputs—External clock input hold time

Notes:

1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings

are measured at the pin.

2. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_SEKHOXsymbolizes the TDM/SI

outputs external timing (SE) for the time t_TDM/SImemory clock reference (K) goes from the high state (H) until outputs (O)

are invalid (X).

3. Timings are measured from the positive or negative edge of the clock, according to SIxMR [CE] and SITXCEI[TXCEIx].

Refer MPC8360E Integrated Communications Processor Reference Manual for more details.

This figure provides the AC test load for the TDM/SI.

OV_DD/2

Output

Z₀= 50 Ω

R_L= 50 Ω

Figure 44. TDM/SI AC Test Load

Figure 45 represents the AC timing from Table 56. Note that although the specifications generally reference the rising edge of

the clock, these AC timing diagrams also apply when the falling edge is the active edge.

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UTOPIA/POS

This figure shows the TDM/SI timing with external clock.

TDM/SICLK (Input)

t_SEIXKH

t_SEIVKH

Input Signals:

TDM/SI

(See Note)

t_SEKHOV

Output Signals:

TDM/SI

(See Note)

t_SEKHOX

Note: The clock edge is selectable on TDM/SI

Figure 45. TDM/SI AC Timing (External Clock) Diagram

17.3 UTOPIA/POS

This section describes the DC and AC electrical specifications for the UTOPIA/POS of the MPC8360E/58E.

17.4 UTOPIA/POS DC Electrical Characteristics

This table provides the DC electrical characteristics for the device UTOPIA.

Table 59. UTOPIA DC Electrical Characteristics

Characteristic

Output high voltage

Symbol

Condition

Min

Max

Unit

V_OH

V_OL

V_IH

V_IL

I_OH= –8.0 mA

I_OL= 8.0 mA

—

2.4

—

0.5

V

Output low voltage

Input high voltage

Input low voltage

Input current

2.0

–0.3

—

OV_DD+ 0.3

0.8

V

—

V

I_IN

0 V ≤V_IN≤OV_DD

±10

μA

17.5 UTOPIA/POS AC Timing Specifications

This table provides the UTOPIA input and output AC timing specifications.

1

Table 60. UTOPIA AC Timing Specifications

Characteristic

Symbol²

Min

Max

Unit

Notes

UTOPIA outputs—Internal clock delay

t_UIKHOV

t_UEKHOV

t_UIKHOX

t_UEKHOX

t_UIIVKH

0

1

0

1

6

4

11.5

11.6

8.0

ns

—

3

UTOPIA outputs—External clock delay

UTOPIA outputs—Internal clock high impedance

UTOPIA outputs—External clock high impedance

UTOPIA inputs—Internal clock input setup time

UTOPIA inputs—External clock input setup time

10.0

—

t_UEIVKH

—

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UTOPIA/POS AC Timing Specifications

1

Table 60. UTOPIA AC Timing Specifications (continued)

Characteristic

Symbol²

Min

Max

Unit

Notes

UTOPIA inputs—Internal clock input hold time

UTOPIA inputs—External clock input hold time

Notes:

t_UIIXKH

2.4

1

—

ns

—

3

t_UEIXKH

1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings

are measured at the pin.

2. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_UIKHOXsymbolizes the UTOPIA

outputs internal timing (UI) for the time t_UTOPIAmemory clock reference (K) goes from the high state (H) until outputs (O)

are invalid (X).

3. In rev. 2.0 silicon, due to errata, t_UEIVKHminimum is 4.3 ns and t_UEIXKHminimum is 1.4 ns under specific conditions. Refer

to Errata QE_UPC3 in Chip Errata for the MPC8360E, Rev. 1.

This figure provides the AC test load for the UTOPIA.

Output

OV_DD/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 46. UTOPIA AC Test Load

These figures represent the AC timing from Table 56. Note that although the specifications generally reference the rising edge

of the clock, these AC timing diagrams also apply when the falling edge is the active edge.

This figure shows the UTOPIA timing with external clock.

UtopiaCLK (Input)

t_UEIXKH

t_UEIVKH

Input Signals:

UTOPIA

t_UEKHOV

Output Signals:

UTOPIA

t_UEKHOX

Figure 47. UTOPIA AC Timing (External Clock) Diagram

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HDLC, BISYNC, Transparent, and Synchronous UART DC Electrical Characteristics

This figure shows the UTOPIA timing with internal clock.

UtopiaCLK (Output)

t_UIIXKH

t_UIIVKH

Input Signals:

UTOPIA

t_UIKHOV

Output Signals:

UTOPIA

t_UIKHOX

Figure 48. UTOPIA AC Timing (Internal Clock) Diagram

18 HDLC, BISYNC, Transparent, and Synchronous

UART

This section describes the DC and AC electrical specifications for the high level data link control (HDLC), BISYNC,

transparent, and synchronous UART protocols of the MPC8360E/58E.

18.1 HDLC, BISYNC, Transparent, and Synchronous UART DC

Electrical Characteristics

This table provides the DC electrical characteristics for the device HDLC, BISYNC, transparent, and synchronous UART

protocols.

Table 61. HDLC, BISYNC, Transparent, and Synchronous UART DC Electrical Characteristics

Characteristic

Output high voltage

Symbol

Condition

Min

Max

Unit

V_OH

V_OL

V_IH

V_IL

I_OH= –2.0 mA

I_OL= 3.2 mA

—

2.4

—

0.5

V

Output low voltage

Input high voltage

Input low voltage

Input current

2.0

–0.3

—

OV_DD+ 0.3

0.8

V

—

V

I_IN

0 V ≤V_IN≤OV_DD

±10

μA

18.2 HDLC, BISYNC, Transparent, and Synchronous UART AC Timing

Specifications

These tables provide the input and output AC timing specifications for HDLC, BISYNC, transparent, and synchronous UART

protocols.

1

Table 62. HDLC, BISYNC, and Transparent AC Timing Specifications

Characteristic

Symbol²

Min

Max

Unit

Outputs—Internal clock delay

Outputs—External clock delay

t_HIKHOV

t_HEKHOV

0

1

11.2

10.8

ns

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HDLC, BISYNC, Transparent, and Synchronous UART AC Timing Specifications

1

Table 62. HDLC, BISYNC, and Transparent AC Timing Specifications (continued)

Characteristic

Symbol²

Min

Max

Unit

Outputs—Internal clock high impedance

Outputs—External clock high impedance

Inputs—Internal clock input setup time

Inputs—External clock input setup time

Inputs—Internal clock input hold time

Inputs—External clock input hold time

Notes:

t_HIKHOX

t_HEKHOX

t_HIIVKH

-0.5

1

5.5

8

ns

8.5

4

—

t_HEIVKH

t_HIIXKH

1.4

1

t_HEIXKH

1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings

are measured at the pin.

2. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_HIKHOXsymbolizes the outputs

internal timing (HI) for the time t_serialmemory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X).

1

Table 63. Synchronous UART AC Timing Specifications

Characteristic

Outputs—Internal clock delay

Symbol²

Min

Max

Unit

t_UAIKHOV

t_UAEKHOV

t_UAIKHOX

t_UAEKHOX

t_UAIIVKH

0

1

0

1

6

8

1

11.3

14

11

14

—

ns

Outputs—External clock delay

Outputs—Internal clock high impedance

Outputs—External clock high impedance

Inputs—Internal clock input setup time

Inputs—External clock input setup time

Inputs—Internal clock input hold time

Inputs—External clock input hold time

Notes:

t_UAEIVKH

t_UAIIXKH

—

t_UAEIXKH

—

1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings

are measured at the pin.

2. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_HIKHOXsymbolizes the outputs

internal timing (HI) for the time t_serialmemory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X).

This figure provides the AC test load.

Output

OV_DD/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 49. AC Test Load

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AC Test Load

18.3 AC Test Load

These figures represent the AC timing from Table 62 and Table 63. Note that although the specifications generally reference the

rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge.

This figure shows the timing with external clock.

Serial CLK (Input)

t_HEIXKH

t_HEIVKH

Input Signals:

(See Note)

t_HEKHOV

Output Signals:

(See Note)

t_HEKHOX

Note: The clock edge is selectable.

Figure 50. AC Timing (External Clock) Diagram

This figure shows the timing with internal clock.

Serial CLK (Output)

t_HIIXKH

t_HIIVKH

Input Signals:

(See Note)

tHIKHOV

Output Signals:

(See Note)

t_HIKHOX

Note: The clock edge is selectable.

Figure 51. AC Timing (Internal Clock) Diagram

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USB DC Electrical Characteristics

19 USB

This section provides the AC and DC electrical specifications for the USB interface of the MPC8360E/58E.

19.1 USB DC Electrical Characteristics

This table provides the DC electrical characteristics for the USB interface.

Table 64. USB DC Electrical Characteristics

Parameter

Symbol

Min

Max

Unit

High-level input voltage

Low-level input voltage

V_IH

V_IL

2

–0.3

OV_DD+ 0.3

V

0.8

—

High-level output voltage, I_OH= –100 μA

Low-level output voltage, I_OL= 100 μA

Input current

V_OH

V_OL

I_IN

OV_DD– 0.4

—

V

0.2

±10

V

—

μA

19.2 USB AC Electrical Specifications

This table describes the general timing parameters of the USB interface of the device.

Table 65. USB General Timing Parameters

Parameter

USB clock cycle time

Symbol¹

Min

Max

Unit

Notes

Note

t_USCK

20.83

166.67

—

ns

Full speed 48 MHz

Low speed 6 MHz

—

2

USB clock cycle time

Skew between TXP and TXN

Skew among RXP, RXN, and RXD

Notes:

t_USTSPN

t_USRSPND

t_USRPND

5

—

10

100

Full speed transitions

Low speed transitions

2

—

2

1. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(state)(signal)}for

receive signals and t_{(first two letters of functional block)(state)(signal)}for transmit signals. For example, t_USRSPND

symbolizes USB timing (US) for the USB receive signals skew (RS) among RXP, RXN, and RXD (PND). Also,

t_USTSPNsymbolizes USB timing (US) for the USB transmit signals skew (TS) between TXP and TXN (PN).

2. Skew measurements are done at OV_DD/2 of the rising or falling edge of the signals.

This figure provide the AC test load for the USB.

OV_DD/2

Output

Z₀= 50 Ω

R_L= 50 Ω

Figure 52. USB AC Test Load

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Package Parameters for the TBGA Package

20 Package and Pin Listings

This section details package parameters, pin assignments, and dimensions. The MPC8360E/58E is available in a tape ball grid

array (TBGA), see Section 20.1, “Package Parameters for the TBGA Package,” and Section 20.2, “Mechanical Dimensions of

the TBGA Package,” for information on the package.

20.1 Package Parameters for the TBGA Package

The package parameters for rev. 2.0 silicon are as provided in the following list. The package type is 37.5 mm × 37.5 mm, 740

tape ball grid array (TBGA).

Package outline

Interconnects

Pitch

37.5 mm × 37.5 mm

740

1.00 mm

Module height (typical)

Solder Balls

1.46 mm

62 Sn/36 Pb/2 Ag (ZU package)

95.5 Sn/0.5 Cu/4Ag (VV package)

0.64 mm

Ball diameter (typical)

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Mechanical Dimensions of the TBGA Package

20.2 Mechanical Dimensions of the TBGA Package

This figure depicts the mechanical dimensions and bottom surface nomenclature of the device, 740-TBGA package.

Figure 53. Mechanical Dimensions and Bottom Surface Nomenclature of the TBGA Package

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Pinout Listings

20.3 Pinout Listings

Refer to AN3097, “MPC8360/MPC8358E PowerQUICC Design Checklist,” for proper pin termination and usage.

This table shows the pin list of the MPC8360E TBGA package.

Table 66. MPC8360E TBGA Pinout Listing

Power

Supply

Signal

Package Pin Number

Pin Type

Notes

Primary DDR SDRAM Memory Controller Interface

MEMC1_MDQ[0:31]

AJ34, AK33, AL33, AL35, AJ33, AK34, AK32,

AM36, AN37, AN35, AR34, AT34, AP37, AP36,

AR36, AT35, AP34, AR32, AP32, AM31, AN33,

AM34, AM33, AM30, AP31, AM27, AR30, AT32,

AN29, AP29, AN27, AR29

I/O

GV_DD

—

MEMC1_MDQ[32:63]/

MEMC2_MDQ[0:31]

AN8, AN7, AM8, AM6, AP9, AN9, AT7, AP7, AU6,

AP6, AR4, AR3, AT6, AT5, AR5, AT3, AP4, AM5,

AP3, AN3, AN5, AL5, AN4, AM2, AL2, AH5, AK3,

AJ2, AJ3, AH4, AK4, AH3

I/O

GV_DD

—

MEMC1_MECC[0:4]/

MSRCID[0:4]

AP24, AN22, AM19, AN19, AM24

I/O

GV_DD

—

MEMC1_MECC[5]/

MDVAL

AM23

MEMC1_MECC[6:7]

MEMC1_MDM[0:3]

AM22, AN18

I/O

O

GV_DD

—

AL36, AN34, AP33, AN28

AT9, AU4, AM3, AJ6

MEMC1_MDM[4:7]/

MEMC2_MDM[0:3]

O

MEMC1_MDM[8]

AP27

O

GV_DD

—

MEMC1_MDQS[0:3]

AK35, AP35, AN31, AM26

AT8, AU3, AL4, AJ5

I/O

MEMC1_MDQS[4:7]/

MEMC2_MDQS[0:3]

MEMC1_MDQS[8]

MEMC1_MBA[0:1]

MEMC1_MBA[2]

MEMC1_MA[0:14]

AP26

I/O

O

GV_DD

—

AU29, AU30

AT30

O

AU21, AP22, AP21, AT21, AU25, AU26, AT23,

AR26, AU24, AR23, AR28, AU23, AR22, AU20,

AR18

O

MEMC1_MODT[0:1]

AG33, AJ36

AT1, AK2

O

GV_DD

6

MEMC1_MODT[2:3]/

MEMC2_MODT[0:1]

MEMC1_MWE

MEMC1_MRAS

MEMC1_MCAS

MEMC1_MCS[0:1]

AT26

O

GV_DD

—

AT29

AT24

AU27, AT27

AU8, AU7

MEMC1_MCS[2:3]/

MEMC2_MCS[0:1]

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Pinout Listings

Table 66. MPC8360E TBGA Pinout Listing (continued)

Package Pin Number Pin Type

Power

Supply

Signal

Notes

MEMC1_MCKE[0:1]

MEMC1_MCK[0:1]

AL32, AU33

AK37, AT37

AN1, AR2

O

GV_DD

3

—

MEMC1_MCK[2:3]/

MEMC2_MCK[0:1]

MEMC1_MCK[4:5]/

MEMC2_MCKE[0:1]

AN25, AK1

O

GV_DD

—

MEMC1_MCK[0:1]

AL37, AT36

AP2, AT2

O

GV_DD

—

MEMC1_MCK[2:3]/

MEMC2_MCK[0:1]

MEMC1_MCK[4]/

MEMC2_MDM[8]

AN24

O

GV_DD

—

10

MEMC1_MCK[5]/

MEMC2_MDQS[8]

AL1

MDIC[0:1]

AH6, AP30

I/O

Secondary DDR SDRAM Memory Controller Interface

MEMC2_MECC[0:7]

AN16, AP18, AM16, AM17, AN17, AP13, AP15,

AN13

I/O

GV_DD

—

MEMC2_MBA[0:2]

MEMC2_MA[0:14]

AU12, AU15, AU13

O

GV_DD

—

AT12, AP11, AT13, AT14, AR13, AR15, AR16,

AT16, AT18, AT17, AP10, AR20, AR17, AR14,

AR11

MEMC2_MWE

MEMC2_MRAS

MEMC2_MCAS

AU10

AT11

AU11

O

GV_DD

—

PCI

PCI_INTA/IRQ_OUT/CE_PF[5]

PCI_RESET_OUT/CE_PF[6]

PCI_AD[31:30]/CE_PG[31:30]

PCI_AD[29:25]/CE_PG[29:25]

PCI_AD[24]/CE_PG[24]

A20

I/O

LV_DD

2

E19

—

D20, D21

A24, B23, C23, E23, A26

B21

OV_DD

LV_DD

2

PCI_AD[23:0]/CE_PG[23:0]

C24, C25, D25, B25, E24, F24, A27, A28, F27, A30,

C30, D30, E29, B31, C31, D31, D32, A32, C33,

B33, F30, E31, A34, D33

OV_DD

PCI_C/BE[3:0]/CE_PF[10:7]

PCI_PAR/CE_PF[11]

E22, B26, E28, F28

I/O

OV_DD

—

5

D28

D26

C27

C28

B28

PCI_FRAME/CE_PF[12]

PCI_TRDY/CE_PF[13]

PCI_IRDY/CE_PF[14]

PCI_STOP/CE_PF[15]

5

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Pinout Listings

Table 66. MPC8360E TBGA Pinout Listing (continued)

Power

Supply

Signal

Package Pin Number

Pin Type

Notes

PCI_DEVSEL/CE_PF[16]

PCI_IDSEL/CE_PF[17]

PCI_SERR/CE_PF[18]

PCI_PERR/CE_PF[19]

PCI_REQ[0]/CE_PF[20]

E26

F22

B29

A29

F19

A21

I/O

OV_DD

5

—

5

LV_DD

2

—

PCI_REQ[1]/CPCI_HS_ES/

CE_PF[21]

LV_DD

PCI_REQ[2]/CE_PF[22]

PCI_GNT[0]/CE_PF[23]

C21

E20

B20

I/O

LV_DD

2

—

PCI_GNT[1]/CPCI1_HS_LED/

CE_PF[24]

PCI_GNT[2]/CPCI1_HS_ENUM/

CE_PF[25]

C20

I/O

LV_DD

2

—

PCI_MODE

D36

B37

I

OV_DD

—

M66EN/CE_PF[4]

I/O

Local Bus Controller Interface

LAD[0:31]

N32, N33, N35, N36, P37, P32, P34, R36, R35,

R34, R33, T37, T35, T34, T33, U37, T32, U36, U34,

V36, V35, W37, W35, V33, V32, W34, Y36, W32,

AA37, Y33, AA35, AA34

I/O

OV_DD

—

LDP[0]/CKSTOP_OUT

LDP[1]/CKSTOP_IN

LDP[2]/LCS[6]

AB37

I/O

O

OV_DD

—

AB36

AB35

LDP[3]/LCS[7]

AA33

LA[27:31]

AC37, AA32, AC36, AC34, AD36

LCS[0:5]

AD33, AG37, AF34, AE33, AD32, AH37

O

LWE[0:3]/LSDDQM[0:3]/LBS[0:3]

LBCTL

AG35, AG34, AH36, AE32

O

AD35

M37

O

LALE

O

LGPL0/LSDA10/cfg_reset_source0

LGPL1/LSDWE/cfg_reset_source1

LGPL2/LSDRAS/LOE

LGPL3/LSDCAS/cfg_reset_source2

LGPL4/LGTA/LUPWAIT/LPBSE

LGPL5/cfg_clkin_div

LCKE

AB32

AE37

AC33

AD34

AE35

AF36

G36

I/O

O

I/O

O

LCLK[0]

J33

O

LCLK[1]/LCS[6]

J34

O

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Pinout Listings

Table 66. MPC8360E TBGA Pinout Listing (continued)

Power

Supply

Signal

Package Pin Number

Pin Type

Notes

LCLK[2]/LCS[7]

LSYNC_OUT

LSYNC_IN

G37

F34

G35

O

I

OV_DD

—

Programmable Interrupt Controller

MCP_OUT

E34

C37

F35

O

I

OV_DD

2

IRQ0/MCP_IN

—

IRQ[1]/M1SRCID[4]/M2SRCID[4]/

LSRCID[4]

I/O

IRQ[2]/M1DVAL/M2DVAL/LDVAL

IRQ[3]/CORE_SRESET

IRQ[4:5]

F36

H34

I/O

OV_DD

—

G33, G32

E35

IRQ[6]/LCS[6]/CKSTOP_OUT

IRQ[7]/LCS[7]/CKSTOP_IN

H36

DUART

UART1_SOUT/M1SRCID[0]/

M2SRCID[0]/LSRCID[0]

E32

B34

C34

A35

O

I/O

O

OV_DD

—

UART1_SIN/M1SRCID[1]/

M2SRCID[1]/LSRCID[1]

UART1_CTS/M1SRCID[2]/

M2SRCID[2]/LSRCID[2]

UART1_RTS/M1SRCID[3]/

M2SRCID[3]/LSRCID[3]

I²C Interface

IIC1_SDA

IIC1_SCL

IIC2_SDA

IIC2_SCL

D34

B35

E33

C35

I/O

OV_DD

2

QUICC Engine Block

CE_PA[0]

F8

I/O

LV_DD0

OV_DD

—

CE_PA[1:2]

CE_PA[3:7]

CE_PA[8]

AH1, AG5

F6, D4, C3, E5, A3

LV_DD0

AG3

OV_DD

LV_DD0

OV_DD

LV_DD0

OV_DD

LV_DD1

CE_PA[9:12]

CE_PA[13:14]

CE_PA[15]

CE_PA[16]

CE_PA[17:21]

F7, B3, E6, B4

AG1, AF6

B2

AF4

B16, A16, E17, A17, B17

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Pinout Listings

Table 66. MPC8360E TBGA Pinout Listing (continued)

Package Pin Number Pin Type

Power

Supply

Signal

Notes

CE_PA[22]

AF3

I/O

OV_DD

LV_DD1

OV_DD

—

CE_PA[23:26]

CE_PA[27:28]

CE_PA[29]

C18, D18, E18, A18

AF2, AE6

B19

LV_DD

1

CE_PA[30]

AE5

OV_DD

LV_DD1

OV_DD

CE_PA[31]

F16

CE_PB[0:27]

AE2, AE1, AD5, AD3, AD2, AC6, AC5, AC4, AC2,

AC1, AB5, AB4, AB3, AB1, AA6, AA4, AA2, Y6, Y4,

Y3, Y2, Y1, W6, W5, W2, V5, V3, V2

CE_PC[0:1]

CE_PC[2:3]

CE_PC[4:6]

CE_PC[7]

V1, U6

I/O

OV_DD

—

C16, A15

U4, U3, T6

C19

LV_DD1

OV_DD

LV_DD2

LV_DD0

OV_DD

CE_PC[8:9]

CE_PC[10:30]

A4, C5

T5, T4, T2, T1, R5, R3, R1, C11, D12, F13, B10,

C10, E12, A9, B8, D10, A14, E15, B14, D15, AH2

CE_PD[0:27]

CE_PE[0:31]

CE_PF[0:3]

E11, D9, C8, F11, A7, E9, C7, A6, F10, B6, D7, E8,

B5, A5, C2, E4, F5, B1, D2, G5, D1, E2, H6, F3, E1,

F2, G3, H4

I/O

OV_DD

—

K3, J2, F1, G2, J5, H3, G1, H2, K6, J3, K5, K4, L6,

P6, P4, P3, P1, N4, N5, N2, N1, M2, M3, M5, M6,

L1, L2, L4, E14, C13, C14, B13

F14, D13, A12, A11

Clocks

PCI_CLK_OUT[0]/CE_PF[26]

PCI_CLK_OUT[1:2]/CE_PF[27:28]

CLKIN

B22

I/O

I

LV_DD

2

—

3

D22, A23

E37

OV_DD

PCI_CLOCK/PCI_SYNC_IN

PCI_SYNC_OUT/CE_PF[29]

M36

I

D37

I/O

JTAG

TCK

TDI

K33

K34

H37

J36

L32

I

OV_DD

—

4

TDO

TMS

TRST

O

I

3

4

I

4

Test

TEST

L35

I

OV_DD

GV_DD

7

TEST_SEL

AU34

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

Freescale Semiconductor

69

Pinout Listings

Table 66. MPC8360E TBGA Pinout Listing (continued)

Power

Supply

Signal

Package Pin Number

PMC

Pin Type

Notes

QUIESCE

B36

O

OV_DD

—

System Control

PORESET

HRESET

SRESET

L37

L36

M33

I

OV_DD

—

1

I/O

2

Thermal Management

THERM0

THERM1

AP19

AT31

I

GV_DD

—

Power and Ground Signals

AV_DD

GND

1

2

5

6

K35

Power for

LBIU DLL

(1.2 V)

AV_DD

—

1

2

5

6

—

K36

Power for

CE PLL

(1.2 V)

AM29

K37

Power for

e300 PLL

(1.2 V)

Power for

system

PLL (1.2 V)

A2, A8, A13, A19, A22, A25, A31, A33, A36, B7,

B12, B24, B27, B30, C4, C6, C9, C15, C26, C32,

D3, D8, D11, D14, D17, D19, D23, D27, E7, E13,

E25, E30, E36, F4, F37, G34, H1, H5, H32, H33, J4,

J32, J37, K1, L3, L5, L33, L34, M1, M34, M35, N37,

P2, P5, P35, P36, R4, T3, U1, U5, U35, V37, W1,

W4, W33, W36, Y34, AA3, AA5, AC3, AC32, AC35,

AD1, AD37, AE4, AE34, AE36, AF33, AG4, AG6,

AG32, AH35, AJ1, AJ4, AJ32, AJ35, AJ37, AK36,

AL3, AL34, AM4, AN6, AN23, AN30, AP8, AP12,

AP14, AP16, AP17, AP20, AP25, AR6, AR8, AR9,

AR19, AR24, AR31, AR35, AR37, AT4, AT10, AT19,

AT20, AT25, AU14, AU22, AU28, AU35

—

GV_DD

AD4, AE3, AF1, AF5, AF35, AF37, AG2, AG36,

AH33, AH34, AK5, AM1, AM35, AM37, AN2, AN10,

AN11, AN12, AN14, AN32, AN36, AP5, AP23,

AP28, AR1, AR7, AR10, AR12, AR21, AR25, AR27,

AR33, AT15, AT22, AT28, AT33, AU2, AU5, AU16,

AU31, AU36

Power for

DDR

DRAM I/O

voltage

(2.5 or

GV_DD

—

1.8 V)

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

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Freescale Semiconductor

Pinout Listings

Table 66. MPC8360E TBGA Pinout Listing (continued)

Package Pin Number Pin Type

Power

Supply

Signal

Notes

LV_DD

0

1

D5, D6

Power for

UCC1

Ethernet

interface

(2.5 V,

LV_DD

0

—

3.3 V)

LV_DD

C17, D16

Power for

UCC2

Ethernet

interface

option 1

(2.5 V,

LV_DD

1

9

3.3 V)

LV_DD2

B18, E21

Power for

UCC2

LV_DD

2

Ethernet

interface

option 2

(2.5 V,

3.3 V)

V_DD

C36, D29, D35, E16, F9, F12, F15, F17, F18, F20, Power for

V_DD

—

F21, F23, F25, F26, F29, F31, F32, F33, G6, J6,

K32, M32, N6, P33, R6, R32, U32, V6, Y5, Y32,

AB6, AB33, AD6, AF32, AK6, AL6, AM7, AM9,

AM10, AM11, AM12, AM13, AM14, AM15, AM18,

AM21, AM25, AM28, AM32, AN15, AN21, AN26,

AU9, AU17

core

(1.2 V)

OV_DD

A10, B9, B15, B32, C1, C12, C22, C29, D24, E3,

E10, E27, G4, H35, J1, J35, K2, M4, N3, N34, R2,

R37, T36, U2, U33, V4, V34, W3, Y35, Y37, AA1,

AA36, AB2, AB34

PCI,

10/100

Ethernet,

and other

standard

(3.3 V)

OV_DD

MVREF1

MVREF2

AN20

AU32

I

DDR

reference

voltage

—

I

DDR

reference

voltage

SPARE1

SPARE3

SPARE4

SPARE5

B11

I/O

—

OV_DD

GV_DD

8

7

8

AH32

AU18

AP1

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

Freescale Semiconductor

71

Pinout Listings

Table 66. MPC8360E TBGA Pinout Listing (continued)

Power

Supply

Signal

Package Pin Number

No Connect

Pin Type

Notes

NC

AM20, AU19

—

Notes:

1. This pin is an open drain signal. A weak pull-up resistor (1 kΩ) should be placed on this pin to OV_DD

2. This pin is an open drain signal. A weak pull-up resistor (2–10 kΩ) should be placed on this pin to OV_DD

3. This output is actively driven during reset rather than being three-stated during reset.

4. These JTAG pins have weak internal pull-up P-FETs that are always enabled.

.

5. This pin should have a weak pull up if the chip is in PCI host mode. Follow PCI specifications recommendation.

6. These are On Die Termination pins, used to control DDR2 memories internal termination resistance.

7. This pin must always be tied to GND.

8. This pin must always be left not connected.

9. Refer to MPC8360E PowerQUICC II Pro Integrated Communications Processor Reference Manual section on “RGMII Pins,”

for information about the two UCC2 Ethernet interface options.

10.It is recommended that MDIC0 be tied to GND using an 18.2 Ω resistor and MDIC1 be tied to DDR power using an 18.2 Ω

resistor for DDR2.

This table shows the pin list of the MPC8358E TBGA package.

Table 67. MPC8358E TBGA Pinout Listing

Power

Supply

Signal

Package Pin Number

Pin Type

Notes

DDR SDRAM Memory Controller Interface

MEMC1_MDQ[0:63]

AJ34, AK33, AL33, AL35, AJ33, AK34, AK32,

AM36, AN37, AN35, AR34, AT34, AP37, AP36,

AR36, AT35, AP34, AR32, AP32, AM31, AN33,

AM34, AM33, AM30, AP31, AM27, AR30, AT32,

AN29, AP29, AN27, AR29, AN8, AN7, AM8, AM6,

AP9, AN9, AT7, AP7, AU6, AP6, AR4, AR3, AT6,

AT5, AR5, AT3, AP4, AM5, AP3, AN3, AN5, AL5,

AN4, AM2, AL2, AH5, AK3, AJ2, AJ3, AH4, AK4,

AH3

I/O

GV_DD

—

MEMC_MECC[0:4]/MSRCID[0:4]

MEMC_MECC[5]/MDVAL

MEMC_MECC[6:7]

AP24, AN22, AM19, AN19, AM24

I/O

O

GV_DD

—

AM23

AM22, AN18

MEMC_MDM[0:8]

AL36, AN34, AP33, AN28,AT9, AU4, AM3,

AJ6,AP27

MEMC_MDQS[0:8]

AK35, AP35, AN31, AM26,AT8, AU3, AL4, AJ5,

AP26

I/O

GV_DD

—

MEMC_MBA[0:1]

MEMC_MBA[2]

MEMC_MA[0:14]

AU29, AU30

AT30

O

GV_DD

—

AU21, AP22, AP21, AT21, AU25, AU26, AT23,

AR26, AU24, AR23, AR28, AU23, AR22, AU20,

AR18

MEMC_MODT[0:3]

AG33, AJ36, AT1, AK2

O

GV_DD

6

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

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Freescale Semiconductor

Pinout Listings

Table 67. MPC8358E TBGA Pinout Listing (continued)

Package Pin Number Pin Type

Power

Supply

Signal

Notes

MEMC_MWE

MEMC_MRAS

MEMC_MCAS

AT26

AT29

AT24

O

GV_DD

—

3

O

MEMC_MCS[0:3]

MEMC_MCKE[0:1]

MEMC_MCK[0:5]

MDIC[0:1]

AU27, AT27, AU8, AU7

AL32, AU33

O

AK37, AT37, AN1, AR2, AN25, AK1

AL37, AT36, AP2, AT2, AN24, AL1

AH6, AP30

O

—

11

O

I/O

PCI

PCI_INTA/IRQ_OUT/CE_PF[5]

PCI_RESET_OUT/CE_PF[6]

PCI_AD[31:30]/CE_PG[31:30]

PCI_AD[29:25]/CE_PG[29:25]

PCI_AD[24]/CE_PG[24]

A20

I/O

LV_DD

2

E19

—

D20, D21

A24, B23, C23, E23, A26

B21

OV_DD

LV_DD

2

PCI_AD[23:0]/CE_PG[23:0]

C24, C25, D25, B25, E24, F24, A27, A28, F27, A30,

C30, D30, E29, B31, C31, D31, D32, A32, C33,

B33, F30, E31, A34, D33

OV_DD

PCI_C/BE[3:0]/CE_PF[10:7]

PCI_PAR/CE_PF[11]

E22, B26, E28, F28

I/O

OV_DD

—

5

D28

D26

C27

C28

B28

E26

F22

B29

A29

F19

A21

PCI_FRAME/CE_PF[12]

PCI_TRDY/CE_PF[13]

PCI_IRDY/CE_PF[14]

PCI_STOP/CE_PF[15]

PCI_DEVSEL/CE_PF[16]

PCI_IDSEL/CE_PF[17]

PCI_SERR/CE_PF[18]

PCI_PERR/CE_PF[19]

PCI_REQ[0]/CE_PF[20]

5

—

5

LV_DD

2

—

PCI_REQ[1]/CPCI_HS_ES/

CE_PF[21]

LV_DD

PCI_REQ[2]/CE_PF[22]

PCI_GNT[0]/CE_PF[23]

C21

E20

B20

I/O

LV_DD

2

—

PCI_GNT[1]/CPCI1_HS_LED/

CE_PF[24]

PCI_GNT[2]/CPCI1_HS_ENUM/

CE_PF[25]

C20

I/O

LV_DD

2

—

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

Freescale Semiconductor

73

Pinout Listings

Table 67. MPC8358E TBGA Pinout Listing (continued)

Power

Supply

Signal

Package Pin Number

Pin Type

Notes

PCI_MODE

D36

B37

I

OV_DD

—

M66EN/CE_PF[4]

I/O

Local Bus Controller Interface

LAD[0:31]

N32, N33, N35, N36, P37, P32, P34, R36, R35,

R34, R33, T37, T35, T34, T33, U37, T32, U36, U34,

V36, V35, W37, W35, V33, V32, W34, Y36, W32,

AA37, Y33, AA35, AA34

I/O

OV_DD

—

LDP[0]/CKSTOP_OUT

LDP[1]/CKSTOP_IN

LDP[2]/LCS[6]

AB37

I/O

O

OV_DD

—

AB36

AB35

LDP[3]/LCS[7]

AA33

LA[27:31]

AC37, AA32, AC36, AC34, AD36

LCS[0:5]

AD33, AG37, AF34, AE33, AD32, AH37

O

LWE[0:3]/LSDDQM[0:3]/LBS[0:3]

LBCTL

AG35, AG34, AH36, AE32

O

AD35

M37

AB32

AE37

AC33

AD34

AE35

AF36

G36

O

LALE

O

LGPL0/LSDA10/cfg_reset_source0

LGPL1/LSDWE/cfg_reset_source1

LGPL2/LSDRAS/LOE

LGPL3/LSDCAS/cfg_reset_source2

LGPL4/LGTA/LUPWAIT/LPBSE

LGPL5/cfg_clkin_div

LCKE

I/O

O

I/O

O

LCLK[0]

J33

O

LCLK[1]/LCS[6]

J34

O

LCLK[2]/LCS[7]

G37

O

LSYNC_OUT

F34

O

LSYNC_IN

G35

I

Programmable Interrupt Controller

MCP_OUT

E34

C37

F35

O

I

OV_DD

2

IRQ0/MCP_IN

—

IRQ[1]/M1SRCID[4]/M2SRCID[4]/

LSRCID[4]

I/O

IRQ[2]/M1DVAL/M2DVAL/LDVAL

IRQ[3]/CORE_SRESET

F36

H34

I/O

OV_DD

—

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

74

Freescale Semiconductor

Pinout Listings

Table 67. MPC8358E TBGA Pinout Listing (continued)

Package Pin Number Pin Type

Power

Supply

Signal

Notes

IRQ[4:5]

G33, G32

E35

I/O

OV_DD

—

IRQ[6]/LCS[6]/CKSTOP_OUT

IRQ[7]/LCS[7]/CKSTOP_IN

H36

DUART

UART1_SOUT/M1SRCID[0]/

M2SRCID[0]/LSRCID[0]

E32

B34

C34

A35

O

I/O

O

OV_DD

—

UART1_SIN/M1SRCID[1]/

M2SRCID[1]/LSRCID[1]

UART1_CTS/M1SRCID[2]/

M2SRCID[2]/LSRCID[2]

UART1_RTS/M1SRCID[3]/

M2SRCID[3]/LSRCID[3]

I²C Interface

IIC1_SDA

IIC1_SCL

IIC2_SDA

IIC2_SCL

D34

B35

E33

C35

I/O

OV_DD

2

QUICC Engine

CE_PA[0]

F8

I/O

LV_DD0

OV_DD

LV_DD0

OV_DD

—

CE_PA[1:2]

CE_PA[3:7]

CE_PA[8]

AH1, AG5

F6, D4, C3, E5, A3

AG3

CE_PA[9:12]

CE_PA[13:14]

CE_PA[15]

CE_PA[16]

CE_PA[17:21]

CE_PA[22]

CE_PA[23:26]

CE_PA[27:28]

CE_PA[29]

CE_PA[30]

CE_PA[31]

F7, B3, E6, B4

LV_DD

OV_DD

LV_DD

0

AG1, AF6

B2

0

AF4

OV_DD

LV_DD1

OV_DD

B16, A16, E17, A17, B17

AF3

C18, D18, E18, A18

LV_DD

OV_DD

LV_DD

1

AF2, AE6

B19

1

AE5

OV_DD

F16

LV_DD1

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

Freescale Semiconductor

75

Pinout Listings

Table 67. MPC8358E TBGA Pinout Listing (continued)

Power

Supply

Signal

Package Pin Number

Pin Type

Notes

CE_PB[0:27]

AE2, AE1, AD5, AD3, AD2, AC6, AC5, AC4, AC2,

AC1, AB5, AB4, AB3, AB1, AA6, AA4, AA2, Y6, Y4,

Y3, Y2, Y1, W6, W5, W2, V5, V3, V2

I/O

OV_DD

—

CE_PC[0:1]

CE_PC[2:3]

CE_PC[4:6]

CE_PC[7]

V1, U6

I/O

OV_DD

C16, A15

U4, U3, T6

C19

LV_DD

1

—

OV_DD

LV_DD

2

0

CE_PC[8:9]

CE_PC[10:30]

A4, C5

LV_DD

T5, T4, T2, T1, R5, R3, R1, C11, D12, F13, B10,

C10, E12, A9, B8, D10, A14, E15, B14, D15, AH2

OV_DD

CE_PD[0:27]

CE_PE[0:31]

CE_PF[0:3]

E11, D9, C8, F11, A7, E9, C7, A6, F10, B6, D7, E8,

B5, A5, C2, E4, F5, B1, D2, G5, D1, E2, H6, F3, E1,

F2, G3, H4

I/O

OV_DD

—

K3, J2, F1, G2, J5, H3, G1, H2, K6, J3, K5, K4, L6,

P6, P4, P3, P1, N4, N5, N2, N1, M2, M3, M5, M6,

L1, L2, L4, E14, C13, C14, B13

OV_DD

F14, D13, A12, A11

Clocks

PCI_CLK_OUT[0]/CE_PF[26]

PCI_CLK_OUT[1:2]/CE_PF[27:28]

CLKIN

B22

I/O

I

LV_DD2

OV_DD

—

3

D22, A23

E37

PCI_CLOCK/PCI_SYNC_IN

PCI_SYNC_OUT/CE_PF[29]

M36

I

D37

I/O

JTAG

TCK

TDI

K33

K34

H37

J36

L32

I

OV_DD

—

4

TDO

TMS

TRST

O

I

3

4

I

4

Test

TEST

L35

I

OV_DD

GV_DD

7

TEST_SEL

AU34

10

PMC

QUIESCE

B36

O

OV_DD

—

System Control

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

76

Freescale Semiconductor

Pinout Listings

Table 67. MPC8358E TBGA Pinout Listing (continued)

Power

Supply

Signal

Package Pin Number

Pin Type

Notes

PORESET

HRESET

SRESET

L37

L36

M33

I

OV_DD

—

1

I/O

2

Thermal Management

THERM0

THERM1

AP19

AT31

I

GV_DD

—

Power and Ground Signals

AV_DD1

AV_DD2

AV_DD5

AV_DD6

GND

K35

Power for

LBIU DLL

(1.2 V)

AV_DD1

—

K36

Power for

CE PLL

(1.2 V)

AV_DD

—

2

5

6

AM29

K37

Power for

e300 PLL

(1.2 V)

Power for

system

PLL (1.2 V)

A2, A8, A13, A19, A22, A25, A31, A33, A36, B7,

B12, B24, B27, B30, C4, C6, C9, C15, C26, C32,

D3, D8, D11, D14, D17, D19, D23, D27, E7, E13,

E25, E30, E36, F4, F37, G34, H1, H5, H32, H33, J4,

J32, J37, K1, L3, L5, L33, L34, M1, M34, M35, N37,

P2, P5, P35, P36, R4, T3, U1, U5, U35, V37, W1,

W4, W33, W36, Y34, AA3, AA5, AC3, AC32, AC35,

AD1, AD37, AE4, AE34, AE36, AF33, AG4, AG6,

AG32, AH35, AJ1, AJ4, AJ32, AJ35, AJ37, AK36,

AL3, AL34, AM4, AN6, AN23, AN30, AP8, AP12,

AP14, AP16, AP17, AP20, AP25, AR6, AR8, AR9,

AR19, AR24, AR31, AR35, AR37, AT4, AT10, AT19,

AT20, AT25, AU14, AU22, AU28, AU35

—

GV_DD

AD4, AE3, AF1, AF5, AF35, AF37, AG2, AG36,

AH33, AH34, AK5, AM1, AM35, AM37, AN2, AN10,

AN11, AN12, AN14, AN32, AN36, AP5, AP23,

AP28, AR1, AR7, AR10, AR12, AR21, AR25, AR27,

AR33, AT15, AT22, AT28, AT33, AU2, AU5, AU16,

AU31, AU36

Power for

DDR

DRAM I/O

voltage

(2.5 or

GV_DD

—

1.8 V)

LV_DD

0

D5, D6

Power for

UCC1

LV_DD0

Ethernet

interface

(2.5 V,

3.3 V)

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

Freescale Semiconductor

77

Pinout Listings

Table 67. MPC8358E TBGA Pinout Listing (continued)

Package Pin Number Pin Type

Power

Supply

Signal

Notes

LV_DD

1

C17, D16

Power for

UCC2

LV_DD

1

9

Ethernet

interface

option 1

(2.5 V,

3.3 V)

LV_DD2

B18, E21

Power for

UCC2

LV_DD

2

9

Ethernet

interface

option 2

(2.5 V,

3.3 V)

V_DD

C36, D29, D35, E16, F9, F12, F15, F17, F18, F20, Power for

V_DD

—

F21, F23, F25, F26, F29, F31, F32, F33, G6, J6,

K32, M32, N6, P33, R6, R32, U32, V6, Y5, Y32,

AB6, AB33, AD6, AF32, AK6, AL6, AM7, AM9,

AM10, AM11, AM12, AM13, AM14, AM15, AM18,

AM21, AM25, AM28, AM32, AN15, AN21, AN26,

AU9, AU17

core

(1.2 V)

OV_DD

A10, B9, B15, B32, C1, C12, C22, C29, D24, E3,

E10, E27, G4, H35, J1, J35, K2, M4, N3, N34, R2,

R37, T36, U2, U33, V4, V34, W3, Y35, Y37, AA1,

AA36, AB2, AB34

PCI,

10/100

Ethernet,

and other

standard

(3.3 V)

OV_DD

MVREF1

MVREF2

AN20

AU32

I

DDR

reference

voltage

—

I

DDR

reference

voltage

SPARE1

SPARE3

SPARE4

SPARE5

B11

I/O

—

OV_DD

GV_DD

8

7

8

AH32

AU18

AP1

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

78

Freescale Semiconductor

Pinout Listings

Table 67. MPC8358E TBGA Pinout Listing (continued)

Power

Supply

Signal

Package Pin Number

No Connect

Pin Type

Notes

NC

AM16, AM17, AM20, AN13, AN16, AN17, AP10,

AP11, AP13, AP15, AP18, AR11, AR13, AR14,

AR15, AR16, AR17, AR20, AT11, AT12, AT13,

AT14, AT16, AT17, AT18, AU10, AU11, AU12,

AU13, AU15, AU19

—

Notes:

1. This pin is an open drain signal. A weak pull-up resistor (1 kΩ) should be placed on this pin to OV_DD.

2. This pin is an open drain signal. A weak pull-up resistor (2–10 kΩ) should be placed on this pin to OV_DD

3. This output is actively driven during reset rather than being three-stated during reset.

4. These JTAG pins have weak internal pull-up P-FETs that are always enabled.

.

5. This pin should have a weak pull up if the chip is in PCI host mode. Follow PCI specifications recommendation.

6. These are On Die Termination pins, used to control DDR2 memories internal termination resistance.

7. This pin must always be tied to GND.

8. This pin must always be left not connected.

9. Refer to MPC8360E PowerQUICC II Pro Integrated Communications Processor Reference Manual section on “RGMII Pins,”

for information about the two UCC2 Ethernet interface options.

10.This pin must always be tied to GV_DD

.

11.It is recommended that MDIC0 be tied to GND using an 18.2 Ω resistor and MDIC1 be tied to DDR power using an 18.2 Ω

resistor for DDR2.

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

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Pinout Listings

21 Clocking

This figure shows the internal distribution of clocks within the MPC8360E.

MPC8360E

e300 Core

Core PLL

core_clk

csb_clk

ce_clk to QUICC Engine Block

DDRC1

/2

DDRC1

Memory

Device

MEMC1_MCK[0:5]

ddr1_clk

MEMC2_MCK[0:1] DDRC2

Memory

DDRC2

/2

QUICC

Engine

PLL

Clock

Unit

MEMC2_MCK[0:1]

Device

System

PLL

lb_clk

/n

LCLK[0:2]

To Local

Bus/DDRC2

Controller

Local Bus

Memory

Device

LSYNC_OUT

LSYNC_IN

LBIU

DLL

csb_clk to Rest

of the Device

PCI_CLK/

PCI_SYNC_IN

CFG_CLKIN_DIV

CLKIN

PCI_SYNC_OUT

PCI Clock

Divider

PCI_CLK_OUT[0:2]

Figure 54. MPC8360E Clock Subsystem

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Pinout Listings

This figure shows the internal distribution of clocks within the MPC8358E.

MPC8358E

e300 Core

Core PLL

core_clk

csb_clk

ce_clk to QUICC Engine Block

DDRC

/2

DDRC

Memory

Device

MEMC1_MCK[0:5]

ddr1_clk

QUICC

Engine

PLL

Clock

Unit

System

PLL

lb_clk

/n

LCLK[0:2]

Local Bus

Memory

Device

LSYNC_OUT

LSYNC_IN

LBIU

DLL

csb_clk to Rest

of the Device

PCI_CLK/

PCI_SYNC_IN

CFG_CLKIN_DIV

CLKIN

PCI_SYNC_OUT

PCI Clock

Divider

PCI_CLK_OUT[0:2]

Figure 55. MPC8358E Clock Subsystem

The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device is

configured in PCI host or PCI agent mode. Note that in PCI host mode, the primary clock input also depends on whether PCI

clock outputs are selected with RCWH[PCICKDRV]. When the device is configured as a PCI host device (RCWH[PCIHOST]

= 1) and PCI clock output is selected (RCWH[PCICKDRV] = 1), CLKIN is its primary input clock. CLKIN feeds the PCI clock

divider (÷2) and the multiplexors for PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration input

selects whether CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The OCCR[PCIOENn] parameters enable

the PCI_CLK_OUTn, respectively.

PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subystem to synchronize to the system

PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN, with equal delay to all PCI agent devices in the

system, to allow the device to function. When the device is configured as a PCI agent device, PCI_CLK is the primary input

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

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Pinout Listings

clock. When the device is configured as a PCI agent device the CLKIN and the CFG_CLKIN_DIV signals should be tied to

GND.

When the device is configured as a PCI host device (RCWH[PCIHOST] = 1) and PCI clock output is disabled

(RCWH[PCICKDRV] = 0), clock distribution and balancing done externally on the board. Therefore, PCI_SYNC_IN is the

primary input clock.

As shown in Figure 54 and Figure 55, the primary clock input (frequency) is multiplied by the QUICC Engine block

phase-locked loop (PLL), the system PLL, and the clock unit to create the QUICC Engine clock (ce_clk), the coherent system

bus clock (csb_clk), the internal DDRC1 controller clock (ddr1_clk), and the internal clock for the local bus interface unit and

DDR2 memory controller (lb_clk).

The csb_clk frequency is derived from a complex set of factors that can be simplified into the following equation:

csb_clk = {PCI_SYNC_IN × (1 + CFG_CLKIN_DIV)} × SPMF

In PCI host mode, PCI_SYNC_IN × (1 + CFG_CLKIN_DIV) is the CLKIN frequency; in PCI agent mode, CFG_CLKIN_DIV

must be pulled down (low), so PCI_SYNC_IN × (1 + CFG_CLKIN_DIV) is the PCI_CLK frequency.

The csb_clk serves as the clock input to the e300 core. A second PLL inside the e300 core multiplies up the csb_clk frequency

to create the internal clock for the e300 core (core_clk). The system and core PLL multipliers are selected by the SPMF and

COREPLL fields in the reset configuration word low (RCWL) which is loaded at power-on reset or by one of the hard-coded

reset options. See Chapter 4, “Reset, Clocking, and Initialization,” in the MPC8360E PowerQUICC II Pro Integrated

Communications Processor Reference Manual for more information on the clock subsystem.

The ce_clk frequency is determined by the QUICC Engine PLL multiplication factor (RCWL[CEPMF) and the QUICC Engine

PLL division factor (RCWL[CEPDF]) according to the following equation:

ce_clk = (primary clock input × CEPMF) ÷ (1 + CEPDF)

The internal ddr1_clk frequency is determined by the following equation:

ddr1_clk = csb_clk × (1 + RCWL[DDR1CM])

Note that the lb_clk clock frequency (for DDRC2) is determined by RCWL[LBCM]. The internal ddr1_clk frequency is not the

external memory bus frequency; ddr1_clk passes through the DDRC1 clock divider (÷2) to create the differential DDRC1

memory bus clock outputs (MEMC1_MCK and MEMC1_MCK). However, the data rate is the same frequency as ddr1_clk.

The internal lb_clk frequency is determined by the following equation:

lb_clk = csb_clk × (1 + RCWL[LBCM])

Note that lb_clk is not the external local bus or DDRC2 frequency; lb_clk passes through the a LB clock divider to create the

external local bus clock outputs (LSYNC_OUT and LCLK[0:2]). The LB clock divider ratio is controlled by LCRR[CLKDIV].

Additionally, some of the internal units may be required to be shut off or operate at lower frequency than the csb_clk frequency.

Those units have a default clock ratio that can be configured by a memory mapped register after the device comes out of reset.

This table specifies which units have a configurable clock frequency.

Table 68. Configurable Clock Units

Default

Frequency

Unit

Options

Security core

csb_clk/3

Off, csb_clk¹, csb_clk/2,

csb_clk/3

PCI and DMA complex

csb_clk

Off, csb_clk

1

With limitation, only for slow csb_clk rates, up to 166 MHz.

This table provides the operating frequencies for the TBGA package under recommended operating conditions (see Table 2).

All frequency combinations shown in the table below may not be available. Maximum operating frequencies depend on the part

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

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Freescale Semiconductor

System PLL Configuration

ordered, see Section 24.1, “Part Numbers Fully Addressed by this Document,” for part ordering details and contact your

Freescale sales representative or authorized distributor for more information.

Table 69. Operating Frequencies for the TBGA Package

Characteristic¹

e300 core frequency (core_clk)

400 MHz

533 MHz

667 MHz²

Unit

266–400

266–533

133–333

266–500

100–166.67

16.67–133

25–66.67

133

266–667

MHz

Coherent system bus frequency (csb_clk)

QUICC Engine frequency³(ce_clk)

DDR and DDR2 memory bus frequency (MCLK)⁴

Local bus frequency (LCLKn)⁵

PCI input frequency (CLKIN or PCI_CLK)

Security core maximum internal operating frequency

Notes:

133

166

1. The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting csb_clk,

MCLK, LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies.

2. The 667 MHz core frequency is based on a 1.3 V V_DDsupply voltage.

3. The 500 MHz QE frequency is based on a 1.3 V V_DDsupply voltage.

4. The DDR data rate is 2x the DDR memory bus frequency.

5. The local bus frequency is 1/2, 1/4, or 1/8 of the lb_clk frequency (depending on LCRR[CLKDIV]) which is in turn 1× or 2×

the csb_clk frequency (depending on RCWL[LBCM]).

21.1 System PLL Configuration

The system PLL is controlled by the RCWL[SPMF] and RCWL[SVCOD] parameters. This table shows the multiplication

factor encodings for the system PLL.

Table 70. System PLL Multiplication Factors

System PLL

RCWL[SPMF]

Multiplication Factor

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

× 16

Reserved

× 2

× 3

× 4

× 5

× 6

× 7

× 8

× 9

× 10

× 11

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System PLL Configuration

Table 70. System PLL Multiplication Factors (continued)

System PLL

RCWL[SPMF]

Multiplication Factor

1100

1101

1110

1111

× 12

× 13

× 14

× 15

The RCWL[SVCOD] denotes the system PLL VCO internal frequency as shown in this table.

Table 71. System PLL VCO Divider

RCWL[SVCOD]

VCO Divider

00

01

10

11

4

8

2

Reserved

NOTE

The VCO divider must be set properly so that the system VCO frequency is in the range of

600–1400 MHz.

The system VCO frequency is derived from the following equations:

•

csb_clk = {PCI_SYNC_IN × (1 + CFG_CLKIN_DIV)} × SPMF

System VCO Frequency = csb_clk × VCO divider (if both RCWL[DDRCM] and RCWL[LBCM] are cleared)

OR

•

System VCO frequency = 2 × csb_clk × VCO divider (if either RCWL[DDRCM] or RCWL[LBCM] are set).

As described in Section 21, “Clocking,” the LBCM, DDRCM, and SPMF parameters in the reset configuration word low and

the CFG_CLKIN_DIV configuration input signal select the ratio between the primary clock input (CLKIN or PCI_CLK) and

the internal coherent system bus clock (csb_clk). This table shows the expected frequency values for the CSB frequency for

select csb_clk to CLKIN/PCI_SYNC_IN ratios.

Table 72. CSB Frequency Options

Input Clock Frequency (MHz)²

CFG_CLKIN_DIV

at Reset¹

csb_clk:

SPMF

16.67

25

33.33

66.67

Input Clock Ratio²

csb_clk Frequency (MHz)

Low

0010

0011

0100

0101

2:1

3:1

4:1

5:1

133

200

266

333

100

125

133

166

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System PLL Configuration

Table 72. CSB Frequency Options (continued)

Input Clock Frequency (MHz)²

CFG_CLKIN_DIV

at Reset¹

csb_clk:

SPMF

16.67

25

33.33

66.67

Input Clock Ratio²

csb_clk Frequency (MHz)

Low

High

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0000

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0000

6:1

7:1

100

150

175

200

225

250

275

300

325

200

233

266

300

333

116

133

150

166

183

200

216

8:1

9:1

10:1

11:1

12:1

13:1

14:1

15:1

16:1

2:1

233

250

266

133

200

266

333

3:1

100

133

166

200

233

4:1

5:1

6:1

7:1

8:1

9:1

10:1

11:1

12:1

13:1

14:1

15:1

16:1

1

2

CFG_CLKIN_DIV is only used for host mode; CLKIN must be tied low and CFG_CLKIN_DIV must be pulled down (low) in

agent mode.

CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.

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Core PLL Configuration

21.2 Core PLL Configuration

RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300 core clock

(core_clk). This table shows the encodings for RCWL[COREPLL]. COREPLL values not listed in this table should be

considered reserved.

Table 73. e300 Core PLL Configuration

RCWL[COREPLL]

core_clk:csb_clk

VCO divider

Ratio

0–1

nn

2–5

6

0000

n

PLL bypassed

(PLL off, csb_clk

clocks core directly) clocks core directly)

00

01

10

11

00

01

10

11

00

01

10

11

00

01

10

11

00

01

10

11

0001

0010

0011

0

1

0

1

0

1:1

÷2

÷4

÷8

÷2

÷4

÷8

÷2

÷4

÷8

÷2

÷4

÷8

÷2

÷4

÷8

1:1

1.5:1

2:1

2.5:1

3:1

NOTE

Core VCO frequency = Core frequency × VCO divider. The VCO divider

(RCWL[COREPLL[0:1]]) must be set properly so that the core VCO frequency is in the

range of 800–1800 MHz. Having a core frequency below the CSB frequency is not a

possible option because the core frequency must be equal to or greater than the CSB

frequency.

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QUICC Engine Block PLL Configuration

21.3 QUICC Engine Block PLL Configuration

The QUICC Engine block PLL is controlled by the RCWL[CEPMF], RCWL[CEPDF], and RCWL[CEVCOD] parameters.

This table shows the multiplication factor encodings for the QUICC Engine block PLL.

Table 74. QUICC Engine Block PLL Multiplication Factors

QUICC Engine PLL

RCWL[CEPMF] RCWL[CEPDF] Multiplication Factor = RCWL[CEPMF]/

(1 + RCWL[CEPDF])

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

0

× 16

Reserved

× 2

× 3

× 4

× 5

× 6

× 7

× 8

× 9

× 10

× 11

× 12

× 13

× 14

× 15

× 16

× 17

× 18

× 19

× 20

× 21

× 22

× 23

× 24

× 25

× 26

× 27

× 28

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QUICC Engine Block PLL Configuration

Table 74. QUICC Engine Block PLL Multiplication Factors (continued)

QUICC Engine PLL

RCWL[CEPMF] RCWL[CEPDF] Multiplication Factor = RCWL[CEPMF]/

(1 + RCWL[CEPDF])

11101

11110

11111

00011

00101

00111

01001

01011

01101

01111

10001

10011

10101

10111

11001

11011

11101

0

1

× 29

× 30

× 31

× 1.5

× 2.5

× 3.5

× 4.5

× 5.5

× 6.5

× 7.5

× 8.5

× 9.5

× 10.5

× 11.5

× 12.5

× 13.5

× 14.5

Note:

1. Reserved modes are not listed.

The RCWL[CEVCOD] denotes the QUICC Engine Block PLL VCO internal frequency as shown in this table.

Table 75. QUICC Engine Block PLL VCO Divider

RCWL[CEVCOD]

VCO Divider

00

01

10

11

4

8

2

Reserved

NOTE

The VCO divider (RCWL[CEVCOD]) must be set properly so that the QUICC Engine

block VCO frequency is in the range of 600–1400 MHz. The QUICC Engine block

frequency is not restricted by the CSB and core frequencies. The CSB, core, and QUICC

Engine block frequencies should be selected according to the performance requirements.

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Suggested PLL Configurations

The QUICC Engine block VCO frequency is derived from the following equations:

ce_clk = (primary clock input × CEPMF) ÷ (1 + CEPDF)

QE VCO Frequency = ce_clk × VCO divider × (1 + CEPDF)

21.4 Suggested PLL Configurations

To simplify the PLL configurations, the device might be separated into two clock domains. The first domain contains the CSB

PLL and the core PLL. The core PLL is connected serially to the CSB PLL, and has the csb_clk as its input clock. The second

clock domain has the QUICC Engine block PLL. The clock domains are independent, and each of their PLLs are configured

separately. Both of the domains has one common input clock. This table shows suggested PLL configurations for 33 and

66 MHz input clocks and illustrates each of the clock domains separately. Any combination of clock domains setting with same

input clock are valid. Refer to Section 21, “Clocking,” for the appropriate operating frequencies for your device.

Table 76. Suggested PLL Configurations

Input

CEPMF CEPDF ClockFreq

(MHz)

QUICC

Engine

Freq (MHz)

Conf

No.¹

CORE

PLL

CSBFreq CoreFreq

(MHz) (MHz)

400

533

667

SPMF

(MHz) (MHz) (MHz)

33 MHz CLKIN/PCI_SYNC_IN Options

s1

s2

0100

0101

0110

0111

1000

1001

1010

æ

0000100

0000101

0000100

0000101

0000100

0000110

0000011

0000100

0000101

0000011

0000100

0000101

0000010

0000011

0000100

0000010

0000011

0000100

æ

0

33

133

166

200

233

266

300

333

—

266

333

416

400

600

350

466

583

400

533

667

300

450

600

333

500

667

—

∞

s3

æ

—

∞

s4

æ

—

∞

s5

æ

—

∞

s6

æ

—

∞

—

∞

s7

æ

—

s8

æ

—

∞

s9

æ

—

∞

s10

s11

s12

s13

s14

s15

s16

s17

s18

c1

æ

—

æ

—

∞

æ

—

∞

æ

—

æ

—

∞

æ

—

∞

æ

—

æ

—

∞

æ

—

∞

01001

01100

01110

01111

300

400

466

500

c2

æ

0

—

∞

c3

æ

0

—

∞

c4

æ

0

—

∞

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Suggested PLL Configurations

Table 76. Suggested PLL Configurations (continued)

Input

CEPMF CEPDF ClockFreq

(MHz)

QUICC

Engine

Freq (MHz)

Conf

No.¹

CORE

PLL

CSBFreq CoreFreq

400

533

667

SPMF

(MHz)

(MHz) (MHz) (MHz)

c5

c6

æ

10000

10001

0

33

—

533

566

—

∞

—

66 MHz CLKIN/PCI_SYNC_IN Options

s1h

s2h

s3h

s4h

s5h

s6h

s7h

s8h

s9h

c1h

c2h

c3h

c4h

c5h

Note:

0011

0100

0101

æ

0000110

0000101

0000110

0000011

0000100

0000101

0000010

0000011

0000100

æ

0

66

200

266

333

—

400

500

600

400

533

667

333

500

667

—

∞

—

∞

æ

—

∞

æ

—

æ

—

∞

æ

—

∞

æ

—

æ

—

∞

æ

—

∞

00101

00110

00111

01000

01001

333

400

466

533

600

æ

0

—

∞

æ

0

—

∞

æ

0

—

∞

æ

0

—

1. The Conf No. consist of prefix, an index and a postfix. The prefix “s” and “c” stands for “syset” and “ce” respectively. The

postfix “h” stands for “high input clock.’”The index is a serial number.

The following steps describe how to use above table. See Example 1.

2. Choose the up or down sections in the table according to input clock rate 33 MHz or 66 MHz.

3. Select a suitable CSB and core clock rates from Table 76. Copy the SPMF and CORE PLL configuration bits.

4. Select a suitable QUICC Engine block clock rate from Table 76. Copy the CEPMF and CEPDF configuration bits.

5. Insert the chosen SPMF, COREPLL, CEPMF and CEPDF to the RCWL fields, respectively.

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Thermal Characteristics

Example 1. Sample Table Use

Input Clock CSB Freq CoreFreq

QUICC

EngineFreq

(MHz)

CORE

PLL

400

533

667

Index SPMF

CEPMF CEPDF

(MHz)

(MHz) (MHz) (MHz)

A

B

1000

0100

0000011 01001

0000100 00110

0

33

66

266

400

533

300

400

∞

•

Example A. To configure the device with CSB clock rate of 266 MHz, core rate of 400 MHz, and QUICC Engine

clock rate 300 MHz while the input clock rate is 33 MHz. Conf No. ‘s10’ and ‘c1’ are selected from Table 76. SPMF

is 1000, CORPLL is 0000011, CEPMF is 01001, and CEPDF is 0.

Example B. To configure the device with CSBCSB clock rate of 266 MHz, core rate of 533 MHz and QUICC Engine

clock rate 400 MHz while the input clock rate is 66 MHz. Conf No. ‘s5h’ and ‘c2h’ are selected from Table 76. SPMF

is 0100, CORPLL is 0000100, CEPMF is 00110, and CEPDF is 0.

22 Thermal

This section describes the thermal specifications of the MPC8360E/58E.

22.1 Thermal Characteristics

This table provides the package thermal characteristics for the 37.5 mm × 37.5 mm 740-TBGA package.

Table 77. Package Thermal Characteristics for the TBGA Package

Characteristic

Symbol

Value

Unit

Notes

Junction-to-ambient natural convection on single-layer board (1s)

Junction-to-ambient natural convection on four-layer board (2s2p)

Junction-to-ambient (@1 m/s) on single-layer board (1s)

Junction-to-ambient (@ 1 m/s) on four-layer board (2s2p)

Junction-to-ambient (@ 2 m/s) on single-layer board (1s)

Junction-to-ambient (@ 2 m/s) on four-layer board (2s2p)

Junction-to-board thermal

R_θJA

15

11

10

8

° C/W

1, 2

1, 3

4

R_θJMA

R_θJB

9

7

4.5

1.1

Junction-to-case thermal

R_θJC

5

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Thermal Management Information

Table 77. Package Thermal Characteristics for the TBGA Package (continued)

Characteristic

Symbol

Value

Unit

Notes

Junction-to-package natural convection on top

ψ

1

° C/W

6

JT

Notes

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal

resistance.

2. Per JEDEC JESD51-2 and SEMI G38-87 with the single layer board horizontal.

3. Per JEDEC JESD51-6 with the board horizontal. 1 m/sec is approximately equal to 200 linear feet per minute (LFM).

4. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured

on the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1).

6. Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written

as Psi-JT.

22.2 Thermal Management Information

For the following sections, P = (V × I ) + P where P is the power dissipation of the I/O drivers. See Table 6 for

D

DD

I/O

typical power dissipations values.

22.2.1 Estimation of Junction Temperature with Junction-to-Ambient

Thermal Resistance

An estimation of the chip junction temperature, T , can be obtained from the equation:

J

T = T + (R

× P )

D

J

A

θJA

where:

T = junction temperature (° C)

J

T = ambient temperature for the package (°C)

A

R

= junction-to-ambient thermal resistance (°C/W)

θJA

P = power dissipation in the package (W)

D

The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal

performance. As a general statement, the value obtained on a single-layer board is appropriate for a tightly packed

printed-circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power

dissipation and the components are well separated. Test cases have demonstrated that errors of a factor of two (in the quantity

T – T ) are possible.

J

A

22.2.2 Estimation of Junction Temperature with Junction-to-Board

Thermal Resistance

The thermal performance of a device cannot be adequately predicted from the junction-to-ambient thermal resistance. The

thermal performance of any component is strongly dependent on the power dissipation of surrounding components.

Additionally, the ambient temperature varies widely within the application. For many natural convection and especially closed

box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air

temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise

description of the local ambient conditions that determine the temperature of the device. At a known board temperature, the

junction temperature is estimated using the following equation:

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

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Freescale Semiconductor

Thermal Management Information

T = T + (R

× P )

D

J

B

θJB

where:

T = junction temperature (° C)

J

T = board temperature at the package perimeter (° C)

B

R

= junction to board thermal resistance (°C/W) per JESD51-8

θJA

P = power dissipation in the package (W)

D

When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made.

The application board should be similar to the thermal test condition: the component is soldered to a board with internal planes.

22.2.3 Experimental Determination of Junction Temperature

To determine the junction temperature of the device in the application after prototypes are available, the Thermal

Characterization Parameter (Ψ ) can be used to determine the junction temperature with a measurement of the temperature at

JT

the top center of the package case using the following equation:

T = T + (Ψ × P )

J

T

JT

D

where:

T = junction temperature (° C)

J

T = thermocouple temperature on top of package (°C)

T

Ψ

= junction-to-ambient thermal resistance (°C/W)

JT

P = power dissipation in the package (W)

D

The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied

to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the

package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the

junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects

of the thermocouple wire.

22.2.4 Heat Sinks and Junction-to-Ambient Thermal Resistance

In some application environments, a heat sink is required to provide the necessary thermal management of the device. When a

heat sink is used, the thermal resistance is expressed as the sum of a junction to case thermal resistance and a case to ambient

thermal resistance:

R

= R

+ R

θJC θCA

θJA

where:

R

= junction-to-ambient thermal resistance (°C/W)

= junction-to-case thermal resistance (°C/W)

= case-to-ambient thermal resistance (° C/W)

θJA

θJC

θCA

R_θis device related and cannot be influenced by the user. The user controls the thermal environment to change the

JC

case-to-ambient thermal resistance, R_θ. For instance, the user can change the size of the heat sink, the airflow around the

CA

device, the interface material, the mounting arrangement on printed-circuit board, or change the thermal dissipation on the

printed-circuit board surrounding the device.

To illustrate the thermal performance of the devices with heat sinks, the thermal performance has been simulated with a few

commercially available heat sinks. The heat sink choice is determined by the application environment (temperature, airflow,

adjacent component power dissipation) and the physical space available. Because there is not a standard application

environment, a standard heat sink is not required.

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93

Thermal Management Information

This table shows heat sinks and junction-to-ambient thermal resistance for TBGA package.

Table 78. Heat Sinks and Junction-to-Ambient Thermal Resistance of TBGA Package

35 × 35 mm TBGA

Heat Sink Assuming Thermal Grease

Airflow

Junction-to-Ambient

Thermal Resistance

AAVID 30 × 30 × 9.4 mm pin fin

Natural convention

1 m/s

10.7

6.2

5.3

8.1

4.4

3.7

5.4

3.2

2.4

6.4

3.8

2.5

2.8

AAVID 30 × 30 × 9.4 mm pin fin

2 m/s

AAVID 31 × 35 × 23 mm pin fin

Natural convention

1 m/s

AAVID 31 × 35 × 23 mm pin fin

2 m/s

Wakefield, 53 × 53 × 25 mm pin fin

Natural convention

1 m/s

Wakefield, 53 × 53 × 25 mm pin fin

2 m/s

MEI, 75 × 85 × 12 no adjacent board, extrusion

MEI, 75 × 85 × 12 mm, adjacent board, 40 mm side bypass

Natural convention

1 m/s

2 m/s

1 m/s

Accurate thermal design requires thermal modeling of the application environment using computational fluid dynamics

software which can model both the conduction cooling and the convection cooling of the air moving through the application.

Simplified thermal models of the packages can be assembled using the junction-to-case and junction-to-board thermal

resistances listed in the thermal resistance table. More detailed thermal models can be made available on request.

Heat sink vendors include the following:

Aavid Thermalloy

80 Commercial St.

Concord, NH 03301

Internet: www.aavidthermalloy.com

603-224-9988

408-749-7601

818-842-7277

Alpha Novatech

473 Sapena Ct. #15

Santa Clara, CA 95054

Internet: www.alphanovatech.com

International Electronic Research Corporation (IERC)

413 North Moss St.

Burbank, CA 91502

Internet: www.ctscorp.com

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

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Heat Sink Attachment

Millennium Electronics (MEI)

Loroco Sites

671 East Brokaw Road

San Jose, CA 95112

408-436-8770

800-522-6752

603-635-5102

Internet: www.mei-millennium.com

Tyco Electronics

Chip Coolers™

P.O. Box 3668

Harrisburg, PA 17105-3668

Internet: www.chipcoolers.com

Wakefield Engineering

33 Bridge St.

Pelham, NH 03076

Internet: www.wakefield.com

Interface material vendors include the following:

Chomerics, Inc.

77 Dragon Ct.

Woburn, MA 01888-4014

Internet: www.chomerics.com

781-935-4850

800-248-2481

Dow-Corning Corporation

Dow-Corning Electronic Materials

2200 W. Salzburg Rd.

Midland, MI 48686-0997

Internet: www.dowcorning.com

Shin-Etsu MicroSi, Inc.

10028 S. 51st St.

Phoenix, AZ 85044

888-642-7674

800-347-4572

Internet: www.microsi.com

The Bergquist Company

18930 West 78th St.

Chanhassen, MN 55317

Internet: www.bergquistcompany.com

22.3 Heat Sink Attachment

When attaching heat sinks to these devices, an interface material is required. The best method is to use thermal grease and a

spring clip. The spring clip should connect to the printed-circuit board, either to the board itself, to hooks soldered to the board,

or to a plastic stiffener. Avoid attachment forces which would lift the edge of the package or peel the package from the board.

Such peeling forces reduce the solder joint lifetime of the package. Recommended maximum force on the top of the package is

10 lb force (4.5 kg force). If an adhesive attachment is planned, the adhesive should be intended for attachment to painted or

plastic surfaces and its performance verified under the application requirements.

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

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95

System Clocking

22.3.1 Experimental Determination of the Junction Temperature with a

Heat Sink

When heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case

of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimizing the size of

the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to

the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature

and then back calculate the case temperature using a separate measurement of the thermal resistance of the interface. From this

case temperature, the junction temperature is determined from the junction-to-case thermal resistance.

T = T + (R

× P )

D

J

C

θJC

where:

T = junction temperature (° C)

J

T = case temperature of the package (°C)

C

R

= junction to case thermal resistance (°C/W)

θJC

P = power dissipation (W)

D

23 System Design Information

This section provides electrical and thermal design recommendations for successful application of the MPC8360E/58E.

Additional information can be found in MPC8360E/MPC8358E PowerQUICC Design Checklist (AN3097).

23.1 System Clocking

The device includes two PLLs, as follows.

•

The platform PLL (AV 1) generates the platform clock from the externally supplied CLKIN input. The frequency

DD

ratio between the platform and CLKIN is selected using the platform PLL ratio configuration bits as described in

Section 21.1, “System PLL Configuration.”

•

The e300 core PLL (AV 2) generates the core clock as a slave to the platform clock. The frequency ratio between

DD

the e300 core clock and the platform clock is selected using the e300 PLL ratio configuration bits as described in

Section 21.2, “Core PLL Configuration.”

23.2 PLL Power Supply Filtering

Each of the PLLs listed above is provided with power through independent power supply pins (AV 1, AV 2, respectively).

DD

The AV level should always be equivalent to V , and preferably these voltages are derived directly from V through a

DD

low frequency filter scheme such as the following.

There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to provide five independent

filter circuits as illustrated in Figure 56, one to each of the five AV pins. By providing independent filters to each PLL, the

DD

opportunity to cause noise injection from one PLL to the other is reduced.

This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz range. It should be built

with surface mount capacitors with minimum Effective Series Inductance (ESL). Consistent with the recommendations of Dr.

Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors

of equal value are recommended over a single large value capacitor.

Each circuit should be placed as close as possible to the specific AV pin being supplied to minimize noise coupled from

DD

nearby circuits. It should be possible to route directly from the capacitors to the AV pin, which is on the periphery of package,

DD

without the inductance of vias.

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Decoupling Recommendations

This figure shows the PLL power supply filter circuit.

10 Ω

V_DD

AV_DDn

2.2 µF

Low ESL Surface Mount Capacitors

GND

Figure 56. PLL Power Supply Filter Circuit

23.3 Decoupling Recommendations

Due to large address and data buses as well as high operating frequencies, the device can generate transient power surges and

high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from

reaching other components in the device system, and the device itself requires a clean, tightly regulated source of power.

Therefore, it is recommended that the system designer place at least one decoupling capacitor at each V , OV , GV , and

DD

LV pins of the device. These decoupling capacitors should receive their power from separate V , OV , GV , LV , and

DD

GND power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed directly under the device

using a standard escape pattern. Others may surround the part.

These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology) capacitors should be

used to minimize lead inductance, preferably 0402 or 0603 sizes.

Additionally, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the V

,

DD

OV , GV , and LV planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have

DD

a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to

the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS

tantalum or Sanyo OSCON).

23.4 Connection Recommendations

To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. Unused active

low inputs should be tied to OV , GV , or LV as required. Unused active high inputs should be connected to GND. All

DD

NC (no-connect) signals must remain unconnected.

Power and ground connections must be made to all external V , GV , LV , OV , and GND pins of the device.

DD

23.5 Output Buffer DC Impedance

The device drivers are characterized over process, voltage, and temperature. For all buses, the driver is a push-pull single-ended

2

driver type (open drain for I C).

To measure Z for the single-ended drivers, an external resistor is connected from the chip pad to OV or GND. Then, the

0

DD

value of each resistor is varied until the pad voltage is OV /2 (see Figure 57). The output impedance is the average of two

DD

components, the resistances of the pull-up and pull-down devices. When data is held high, SW1 is closed (SW2 is open) and

R is trimmed until the voltage at the pad equals OV /2. R then becomes the resistance of the pull-up devices. R and R are

P

DD

P

N

designed to be close to each other in value. Then, Z = (R + R )/2.

0

P

N

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97

Configuration Pin Muxing

OV_DD

R_N

SW2

SW1

Pad

Data

R_P

OGND

Figure 57. Driver Impedance Measurement

The value of this resistance and the strength of the driver’s current source can be found by making two measurements. First, the

output voltage is measured while driving logic 1 without an external differential termination resistor. The measured voltage is

V = R

× I

. Second, the output voltage is measured while driving logic 1 with an external precision differential

1

source

termination resistor of value R . The measured voltage is V = 1/(1/R + 1/R )) × I

gives R

. Solving for the output impedance

term

2

1

2

source

= R

× (V /V – 1). The drive current is then I

= V /R

.

source

term

1

2

source

1

source

This table summarizes the signal impedance targets. The driver impedance are targeted at minimum V , nominal OV

,

DD

105° C.

Table 79. Impedance Characteristics

Local Bus, Ethernet, DUART,

Impedance

Control, Configuration, Power

Management

PCI

DDR DRAM

Symbol

Unit

R

42 Target

NA

25 Target

NA

20 Target

NA

Z₀

W

N

P

Differential

Z_DIFF

Note: Nominal supply voltages. See Table 1, T_J= 105° C.

23.6 Configuration Pin Muxing

The device provides the user with power-on configuration options that can be set through the use of external pull-up or

pull-down resistors of 4.7 kΩon certain output pins (see customer visible configuration pins). These pins are generally used as

output only pins in normal operation.

While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins while HRESET is

asserted, is latched when HRESET deasserts, at which time the input receiver is disabled and the I/O circuit takes on its normal

function. Careful board layout with stubless connections to these pull-up/pull-down resistors coupled with the large value of the

pull-up/pull-down resistor should minimize the disruption of signal quality or speed for output pins thus configured.

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

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Freescale Semiconductor

Pull-Up Resistor Requirements

23.7 Pull-Up Resistor Requirements

The device requires high resistance pull-up resistors (10 kΩis recommended) on open drain type pins including I C pins,

Ethernet Management MDIO pin, and EPIC interrupt pins.

2

For more information on required pull-up resistors and the connections required for the JTAG interface, see

MPC8360E/MPC8358E PowerQUICC Design Checklist (AN3097).

24 Ordering Information

24.1 Part Numbers Fully Addressed by this Document

This table provides the Freescale part numbering nomenclature for the MPC8360E/58E. Note that the individual part numbers

correspond to a maximum processor core frequency. For available frequencies, contact your local Freescale sales office.

Additionally to the processor frequency, the part numbering scheme also includes an application modifier, which may specify

special application conditions. Each part number also contains a revision code that refers to the die mask revision number.

1

Table 80. Part Numbering Nomenclature

MPC nnnn

e

t

pp

aa

a

A

QUICC

Engine

Frequency

Product

Code Identifier Acceleration

Part

Encryption Temperature

Range

Processor

Platform

Frequency

Die

Revision

Package²

Frequency³

MPC

8358

8360

Blank = not Blank = 0° C ZU = TBGA e300 core speed D = 266 MHz E = 300 MHz A = rev. 2.1

included

T_Ato 105° C VV = TBGA AD = 266 MHz

G = 400 MHz

silicon

E = included

T_J

(no lead)

AG = 400 MHz

C= –40° C T_A

to 105° C T_J

e300 core speed D = 266 MHz G = 400 MHz A = rev. 2.1

AG = 400 MHz F = 333 MHz H = 500 MHz

AJ = 533 MHz

silicon

—

AL = 667 MHz

MPC

(rev. 2.0

silicon

only)

8360

Blank = not

included

E = included

0° C T_Ato ZU = TBGA e300 core speed F = 333 MHz G = 400 MHz

70° C T_JVV = TBGA AH = 500 MHz H = 500 MHz

(no lead) AL = 667 MHz

Notes:

1. Not all processor, platform, and QUICC Engine block frequency combinations are supported. For available frequency

combinations, contact your local Freescale sales office or authorized distributor.

2. See Section 20, “Package and Pin Listings,” for more information on available package types.

3. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this

specification support all core frequencies. Additionally, parts addressed by part number specifications may support other

maximum core frequencies.

This table shows the SVR settings by device and package type.

Table 81. SVR Settings

SVR

(Rev. 2.0)

SVR

(Rev. 2.1)

Device

Package

MPC8360E

MPC8360

TBGA

0x8048_0020

0x8049_0020

0x8048_0021

0x8049_0021

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

Freescale Semiconductor

99

Part Numbers Fully Addressed by this Document

Table 81. SVR Settings (continued)

SVR

(Rev. 2.0)

SVR

(Rev. 2.1)

Device

Package

MPC8358E

MPC8358

TBGA

0x804A_0020

0x804B_0020

0x804A_0021

0x804B_0021

25 Document Revision History

This table provides a revision history for this document.

Table 82. Revision History

Rev.

Number

Date

Substantive Change(s)

5

09/2011 • Section 2.2.1, “Power-Up Sequencing”, added the current limitation “3A to 5A” for the excessive current.

• Section 2.1.2, “Power Supply Voltage Specification, Updated the Characteristic for TBGA (MPC8358 &

MPC8360 Device) with specific frequency for Core and PLL voltages.

• Added table footnote 3 to Table 2.

• Applied table footnotes 1 and 2 to Table 10.

• Removed table footnotes from Table 19.

• Applied table footnote 8 to the last row of Table 40.

• Applied table footnotes 8 and 9 to Table 41.

• Applied table footnotes 2and 3 to Table 45.

• Removed table footnotes from Table 46.

• Applied table footnote to last three rows of Table 65.

4

01/2011 • Updated references to the LCRR register throughout

• Removed references to DDR DLL mode in Section 6.2.2, “DDR and DDR2 SDRAM Output AC Timing

Specifications.”

• Changed “Junction-to-Case” to “Junction-to-Ambient” in Section 22.2.4, “Heat Sinks and

Junction-to-Ambient Thermal Resistance,” and Table 78, “Heat Sinks and Junction-to-Ambient Thermal

Resistance of TBGA Package,” titles.

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

100 Freescale Semiconductor

Part Numbers Fully Addressed by this Document

Table 82. Revision History (continued)

Substantive Change(s)

Rev.

Number

Date

3

03/2010 • Changed references to RCWH[PCICKEN] to RCWH[PCICKDRV].

• In Table 2, added extended temperature characteristics.

• Added Figure 6, “DDR Input Timing Diagram.”

• In Figure 53, “Mechanical Dimensions and Bottom Surface Nomenclature of the TBGA Package,”

removed watermark.

• Updated the title of Table 19,”DDR SDRAM Input AC Timing Specifications.”

• In Table 20, “DDR and DDR2 SDRAM Input AC Timing Specifications Mode,” changed table subtitle.

• In Table 27–Table 30, and Table 33—Table 34, changed the rise and fall time specifications to reference

20–80% and 80–20% of the voltage supply, respectively.

• In Table 38, “IEEE 1588 Timer AC Specifications,” changed first parameter to “Timer clock frequency.”

• In Table 45, “I2C AC Electrical Specifications,” changed units to “ns” for t_I2DVKH

.

• In Table 66, “MPC8360E TBGA Pinout Listing,” and Table 67 “MPC8358E TBGA Pinout Listing, added

note 7: “This pin must always be tied to GND” to the TEST pin and added a note to SPARE1 stating: “This

pin must always be left not connected.”

• In Section 4, “Clock Input Timing,” added note regarding rise/fall time on QUICC Engine block input pins.

• Added Section 4.3, “Gigabit Reference Clock Input Timing.”

• Updated Section 8.1.1, “10/100/1000 Ethernet DC Electrical Characteristics.”

• In Section 20.3, “Pinout Listings,” added sentence stating “Refer to AN3097, ‘MPC8360/MPC8358E

PowerQUICC Design Checklist,’ for proper pin termination and usage.”

• In Section 21, “Clocking,” removed statement: “The OCCR[PCICDn] parameters select whether CLKIN

or CLKIN/2 is driven out on the PCI_CLK_OUTn signals.”

• In Section 21.1, “System PLL Configuration,” updated the system VCO frequency conditions.

• In Table 80, added extended temperature characteristics.

2

12/2007 Initial release.

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

Freescale Semiconductor 101

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Information in this document is provided solely to enable system and software

implementers to use Freescale Semiconductor products. There are no express or

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Document Number: MPC8360EEC

Rev. 5

09/2011


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MPC8360ZUALDGA [FREESCALE]

相关型号：

MPC8360ZUALDHA

MPC8360ZUALFGA

MPC8360ZUALFHA

MPC8360ZUALFHA

MPC8377CVRAFDA

MPC8377CVRAFFA

MPC8377CVRAFGA

MPC8377CVRAGDA

MPC8377CVRAGFA

MPC8377CVRAGGA

MPC8377CVRAJD

MPC8377CVRAJDA