MPC8360ZUALFHA [NXP]
32-BIT, 667MHz, RISC PROCESSOR, PBGA740, 37.50 X 37.50 MM, 1.46 MM HEIGHT, 1 MM PITCH, TBGA-740;
| 型号： | MPC8360ZUALFHA |
| 厂家： | 
NXP |
| 描述： | 32-BIT, 667MHz, RISC PROCESSOR, PBGA740, 37.50 X 37.50 MM, 1.46 MM HEIGHT, 1 MM PITCH, TBGA-740 时钟 外围集成电路 |
| 文件： | 总112页 (文件大小：1114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MPC8360EEC
Rev. 2, 12/2007
Freescale Semiconductor
Technical Data
MPC8360E/MPC8358E
PowerQUICC™ II Pro Processor
Revision 2.x TBGA Silicon
Hardware Specifications
Contents
This document provides an overview of the MPC8360E/58E
PowerQUICC II Pro processor revision 2.x TBGA
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 8
3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 13
4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 16
6. DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 19
7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8. UCC Ethernet Controller: Three-Speed Ethernet, MII
Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
10. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
11. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
12. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
13. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
14. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
15. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
16. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
17. TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
18. UTOPIA/POS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
™
features, including a block diagram showing the major
functional components. This device is a cost-effective,
highly integrated communications processor that addresses
the needs of the networking, wireless infrastructure and
telecommunications markets. Target applications include
next generation DSLAMs, network interface cards for 3G
basestations (Node Bs), routers, media gateways and high
end IADs. The device extends current PowerQUICC II Pro
offerings, adding higher CPU performance, additional
functionality, faster interfaces and robust interworking
between protocols while addressing the requirements related
to time-to-market, price, power, and package size. This
device can be used for the control plane along with data
plane functionality.
19. HDLC, BISYNC, Transparent, and Synchronous
UART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
For functional characteristics of the processor, refer to the
MPC8360E Integrated Communications Processor Family
Reference Manual, Rev. 2.
20. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
21. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . . 68
22. Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
23. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
24. System Design Information . . . . . . . . . . . . . . . . . . . 104
25. Document Revision History. . . . . . . . . . . . . . . . . . . 108
26. Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . 108
To locate any published errata or updates for this document,
contact your Freescale sales office.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
Overview
1 Overview
This section describes a high-level overview including features and general operation of the
MPC8360E/58E PowerQUICC™ II Pro processor. A major component of this device is the e300 core
which includes 32 Kbytes of instruction and data cache and is fully compatible with the PowerPC™ 603e
™
instruction set. The new QUICC Engine module provides termination, interworking, and switching
between a wide range of protocols including ATM, Ethernet, HDLC, and POS. The QUICC Engine
module's enhanced interworking eases the transition and reduces investment costs from ATM to IP based
systems. The other major features include a dual DDR SDRAM memory controller for the MPC8360E,
which allows equipment providers to partition system parameters and data in an extremely efficient way,
such as using one 32-bit DDR memory controller for control plane processing and the other for data plane
processing. The MPC8358E has a single DDR SDRAM memory controller. The MPC8360E/58E also
offers a 32-bit PCI controller, a flexible local bus, and a dedicated security engine.
System Interface Unit
(SIU)
e300 Core
Security Engine
32KB
32KB
Memory Controllers
GPCM/UPM/SDRAM
I-Cache
D-Cache
DDRC1
DDRC2
Classic G2 MMUs
32/64 DDR Interface Unit
PCI Bridge
Power
FPU
PCI
Management
Local
JTAG/COP
Timers
Local Bus
Bus Arbitration
DUART
QUICC Engine Module
Multi-User
Accelerators
RAM
Baud Rate
Generators
Serial DMA
&
2 Virtual
DMAs
2
Dual I C
Dual 32-bit RISC CP
4 Channel DMA
Interrupt Controller
Protection & Configuration
System Reset
Parallel I/O
Time Slot Assigner
Serial Interface
Clock Synthesizer
8 MII/
RMII
2 GMII/
RGMII/TBI/RTBI
2 UTOPIA/POS
(124 MPHY)
8 TDM Ports
Figure 1. MPC8360E Block Diagram
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
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Freescale Semiconductor
Overview
System Interface Unit
(SIU)
e300 Core
Security Engine
32KB
32KB
Memory Controllers
GPCM/UPM/SDRAM
I-Cache
D-Cache
Classic G2 MMUs
DDRC
32/64 DDR Interface Unit
PCI Bridge
Power
PCI
FPU
Management
Local
JTAG/COP
Timers
Local Bus
Bus Arbitration
DUART
QUICC Engine Module
Multi-User
Accelerators
RAM
Baud Rate
Generators
Serial DMA
&
2 Virtual
DMAs
2
Dual I C
Dual 32-bit RISC CP
4 Channel DMA
Interrupt Controller
Protection & Configuration
System Reset
Parallel I/O
Time Slot Assigner
Serial Interface
Clock Synthesizer
6 MII/
RMII
2 GMII/
RGMII/TBI/RTBI
1 UTOPIA/POS
(31/124 MPHY)
4 TDM Ports
Figure 2. MPC8358E Block Diagram
Major features of the MPC8360E/58E are as follows:
• e300 PowerPC processor core (enhanced version of the MPC603e core)
— Operates at up to 667 MHz (for the MPC8360E) and 400 MHz (for the MPC8358E)
— High-performance, superscalar processor core
— Floating-point, integer, load/store, system register, and branch processing units
— 32-Kbyte instruction cache, 32-Kbyte data cache
— Lockable portion of L1 cache
— Dynamic power management
— Software-compatible with the Freescale processor families implementing the Power
Architecture™ technology
•
QUICC Engine unit
— Two 32-bit RISC controllers for flexible support of the communications peripherals, each
operating up to 500 MHz (for the MPC8360E) and 400 MHz (for the MPC8358E)
— Serial DMA channel for receive and transmit on all serial channels
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Overview
— QE peripheral request interface (for SEC, PCI, IEEE® Std 1588™)
— Eight universal communication controllers (UCCs) on the MPC8360E and six UCCs on the
MPC8358E supporting the following protocols and interfaces (not all of them simultaneously):
– IEEE Std. 1588 protocol supported
– 10/100 Mbps Ethernet/IEEE Std. 802.3® CDMA/CS interface through a
1
media-independent interface (MII, RMII, RGMII)
– 1000 Mbps Ethernet/IEEE Std. 802.3 CDMA/CS interface through a media-independent
interface (GMII, RGMII, TBI, RTBI) on UCC1 and UCC2
– 9.6K jumbo frames
– ATM full-duplex SAR, up to 622 Mbps (OC-12/STM-4), AAL0, AAL1 and AAL5 in
accordance ITU-T I.363.5
– ATM AAL2 CPS, SSSAR, and SSTED up to 155 Mbps (OC-3/STM-1) Mbps full duplex
(with 4 CPS packets per cell) in accordance ITU-T I.366.1 and I.363.2
– ATM traffic shaping for CBR, VBR, UBR, and GFR traffic types compatible with ATM
forum TM4.1 for up to 64K simultaneous ATM channels
– ATM AAL1 structured and unstructured circuit emulation service (CES 2.0) in accordance
with ITU-T I.163.1 and ATM Forum af-vtoa-00-0078.000
– IMA (Inverse Multiplexing over ATM) for up to 31 IMA links over 8 IMA groups in
accordance with the ATM forum AF-PHY-0086.000 (Version 1.0) and AF-PHY-0086.001
(Version 1.1)
– ATM Transmission Convergence layer support in accordance with ITU-T I.432
– ATM OAM handling features compatible with ITU-T I.610
– PPP, Multi-Link (ML-PPP), Multi-Class (MC-PPP) and PPP mux in accordance with the
following RFCs: 1661, 1662, 1990, 2686 and 3153
– IP support for IPv4 packets including TOS, TTL and header checksum processing
– Ethernet over first mile IEEE Std. 802.3ah®
– Shim header
– Ethernet-to-Ethernet/AAL5/AAL2 inter-working
– L2 Ethernet switching using MAC address or IEEE Std. 802.1P/Q® VLAN tags
– ATM (AAL2/AAL5) to Ethernet (IP) interworking in accordance with RFC2684 including
bridging of ATM ports to Ethernet ports
– Extensive support for ATM statistics and Ethernet RMON/MIB statistics
– AAL2 protocol rate up to 4 CPS at OC-3/STM-1 rate
– Packet over Sonet (POS) up to 622-Mbps full-duplex 124 MultiPHY
– POS hardware; microcode must be loaded as an IRAM package
– Transparent up to 70-Mbps full-duplex
– HDLC up to 70-Mbps full-duplex
– HDLC BUS up to 10 Mbps
1. SMII or SGMII media-independent interface is not currently supported
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Overview
– Asynchronous HDLC
– UART
– BISYNC up to 2 Mbps
– User-programmable Virtual FIFO size
– QUICC Multichannel Controller (QMC) for 64 TDM channels
— One multichannel communication controller (MCC) only on the MPC8360E supporting the
following:
– 256 HDLC or transparent channels
– 128 SS7 channels
– Almost any combination of subgroups can be multiplexed to single or multiple TDM
interfaces
— Two UTOPIA/POS interfaces on the MPC8360E supporting 124 MultiPHY each (optional
2*128 MultiPHY with extended address) and one UTOPIA/POS interface on the MPC8358E
supporting 31/124 MultiPHY
— Two serial peripheral interfaces (SPI); SPI2 is dedicated to Ethernet PHY management
— Eight TDM interfaces on the MPC8360E and four TDM interfaces on the MPC8358E with
1-bit mode for E3/T3 rates in clear channel
— Sixteen independent baud rate generators and 30 input clock pins for supplying clocks to UCC
and MCC serial channels (MCC is only available on the MPC8360E)
— Four independent 16-bit timers that can be interconnected as four 32-bit timers
— Interworking functionality:
– Layer 2 10/100-Base T Ethernet switch
– ATM-to-ATM switching (AAL0, 2, 5)
– Ethernet-to-ATM switching with L3/L4 support
– PPP interworking
•
Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP,
802.11i, iSCSI, and IKE processing. The security engine contains four crypto-channels, a
controller, and a set of crypto execution units (EUs).
— Public key execution unit (PKEU) supporting the following:
– RSA and Diffie-Hellman
– Programmable field size up to 2048 bits
– Elliptic curve cryptography
– F2m and F(p) modes
– Programmable field size up to 511 bits
— Data encryption standard execution unit (DEU)
– DES, 3DES
– Two key (K1, K2) or three key (K1, K2, K3)
– ECB and CBC modes for both DES and 3DES
— Advanced encryption standard unit (AESU)
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
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5
Overview
— Implements the Rinjdael symmetric key cipher
— Key lengths of 128, 192, and 256 bits, two key
– ECB, CBC, CCM, and counter modes
— ARC four execution unit (AFEU)
– Implements a stream cipher compatible with the RC4 algorithm
– 40- to 128-bit programmable key
— Message digest execution unit (MDEU)
– SHA with 160-, 224-, or 256-bit message digest
– MD5 with 128-bit message digest
– HMAC with either SHA or MD5 algorithm
— Random number generator (RNG)
— Four crypto-channels, each supporting multi-command descriptor chains
– Static and/or dynamic assignment of crypto-execution units via an integrated controller
– Buffer size of 256 bytes for each execution unit, with flow control for large data sizes
— Storage/NAS XOR parity generation accelerator for RAID applications
•
Dual DDR SDRAM memory controllers on the MPC8360E and a single DDR SDRAM memory
controller on the MPC8358E
— Programmable timing supporting both DDR1 and DDR2 SDRAM
— On the MPC8360E, the DDR buses can be configured as two 32-bit buses or one 64-bit bus;
on the MPC8358E, the DDR bus can be configured as a 32-bit or a 64-bit bus
— 32- or 64-bit data interface, up to 333 MHz (for the MPC8360E) and 266 MHz (for the
MPC8358E) data rate
— Four banks of memory, each up to 1 Gbyte
— DRAM chip configurations from 64 Mbits to 1 Gigabit with x8/x16 data ports
— Full ECC support (when the MPC8360E is configured as 2x32 bit DDR memory controllers,
both support ECC)
— Page mode support (up to 16 simultaneous open pages for DDR1, up to 32 simultaneous open
pages for DDR2)
— Contiguous or discontiguous memory mapping
— Read-modify-write support
— Sleep mode support for self refresh SDRAM
— Supports auto refreshing
— Supports source clock mode
— On-the-fly power management using CKE
— Registered DIMM support
— 2.5-V SSTL2 compatible I/O for DDR1, 1.8-V SSTL2 compatible I/O for DDR2
— External driver impedance calibration
— On-die termination (ODT)
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
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Overview
•
PCI interface
— PCI Specification Revision 2.3 compatible
— Data bus widths:
– Single 32-bit data PCI interface that operates at up to 66 MHz
— PCI 3.3-V compatible (not 5-V compatible)
— PCI host bridge capabilities on both interfaces
— PCI agent mode supported on PCI interface
— Support for PCI-to-memory and memory-to-PCI streaming
— Memory prefetching of PCI read accesses and support for delayed read transactions
— Support for posting of processor-to-PCI and PCI-to-memory writes
— On-chip arbitration, supporting five masters on PCI
— Support for accesses to all PCI address spaces
— Parity support
— Selectable hardware-enforced coherency
— Address translation units for address mapping between host and peripheral
— Dual address cycle supported when the device is the target
— Internal configuration registers accessible from PCI
Local bus controller (LBC)
•
— Multiplexed 32-bit address and data operating at up to 133 MHz
— Eight chip selects support eight external slaves
— Up to eight-beat burst transfers
— 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller
— Three protocol engines available on a per chip select basis:
– General-purpose chip select machine (GPCM)
– Three user programmable machines (UPMs)
– Dedicated single data rate SDRAM controller
— Parity support
— Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)
Programmable interrupt controller (PIC)
•
— Functional and programming compatibility with the MPC8260 interrupt controller
— Support for 8 external and 35 internal discrete interrupt sources
— Support for one external (optional) and seven internal machine checkstop interrupt sources
— Programmable highest priority request
— Four groups of interrupts with programmable priority
— External and internal interrupts directed to communication processor
— Redirects interrupts to external INTA pin when in core disable mode
— Unique vector number for each interrupt source
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
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7
Electrical Characteristics
2
•
Dual industry-standard I C interfaces
— Two-wire interface
— Multiple master support
2
— Master or slave I C mode support
— On-chip digital filtering rejects spikes on the bus
2
— System initialization data is optionally loaded from I C-1 EPROM by boot sequencer
embedded hardware
•
DMA controller
— Four independent virtual channels
— Concurrent execution across multiple channels with programmable bandwidth control
— All channels accessible by local core and remote PCI masters
— Misaligned transfer capability
— Data chaining and direct mode
— Interrupt on completed segment and chain
— DMA external handshake signals: DMA_DREQ[0:3]/DMA_DACK[0:3]/DMA_DONE[0:3].
There is one set for each DMA channel. The pins are multiplexed to the parallel IO pins with
other QE functions.
•
•
DUART
— Two 4-wire interfaces (RxD, TxD, RTS, CTS)
— Programming model compatible with the original 16450 UART and the PC16550D
System timers
— Periodic interrupt timer
— Real-time clock
— Software watchdog timer
— Eight general-purpose timers
•
•
IEEE Std. 1149.1™ compliant, JTAG boundary scan
Integrated PCI bus and SDRAM clock generation
2 Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the
MPC8360E/58E. The device is currently targeted to these specifications. Some of these specifications are
independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer
design specifications.
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
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Freescale Semiconductor
Electrical Characteristics
2.1
Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
2.1.1
Absolute Maximum Ratings
Table 1 provides the absolute maximum ratings.
1
Table 1. Absolute Maximum Ratings
Characteristic Symbol
Max Value
Unit
Notes
Core supply voltage
V
V
DD
–0.3 to 1.32
–0.3 to 1.37
For QE frequencies <500 MHz and e300 frequencies <667 MHz
For a QE frequency of 500 MHz or an e300 frequency of 667 MHz
PLL supply voltage
AV
V
V
DD
–0.3 to 1.32
–0.3 to 1.37
For QE frequencies <500 MHz and e300 frequencies <667 MHz
For a QE frequency of 500 MHz or an e300 frequency of 667 MHz
DDR and DDR2 DRAM I/O voltage
GV
DD
–0.3 to 2.75
–0.3 to 1.89
DDR
DDR2
Three-speed Ethernet I/O, MII management voltage
LV
OV
–0.3 to 3.63
–0.3 to 3.63
V
V
DD
PCI, local bus, DUART, system control and power management,
DD
2
I C, SPI, and JTAG I/O voltage
Input voltage
DDR DRAM signals
MV
–0.3 to (GV + 0.3)
V
V
V
V
2, 5
2, 5
4, 5
3, 5
IN
DD
DDR DRAM reference
MV
–0.3 to (GV + 0.3)
DD
REF
Three-speed Ethernet signals
Local bus, DUART, CLKIN, system
LV
–0.3 to (LV + 0.3)
DD
IN
OV
–0.3 to (OV + 0.3)
DD
IN
2
control and power management, I C,
SPI, and JTAG signals
PCI
OV
–0.3 to (OV + 0.3)
V
6
IN
DD
Storage temperature range
T
–55 to 150
°C
STG
Notes:
1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or
cause permanent damage to the device.
2. Caution: MV must not exceed GV by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during
IN
DD
power-on reset and power-down sequences.
3. Caution: OV must not exceed OV by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during
IN
DD
power-on reset and power-down sequences.
4. Caution: LV must not exceed LV by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during
IN
DD
power-on reset and power-down sequences.
5. (M,L,O)V and MV may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 3.
IN
REF
6. OV on the PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation,
IN
as shown in Figure 4.
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
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9
Electrical Characteristics
2.1.2
Power Supply Voltage Specification
Table 2 provides the recommended operating conditions for the device. Note that the values in Table 2 are
the recommended and tested operating conditions. Proper device operation outside of these conditions is
not guaranteed.
Table 2. Recommended Operating Conditions
Recommended
Characteristic
Symbol
Unit
Notes
Value
Core supply voltage
V
V
1
DD
1.2 V 60 mV
1.3 V 50 mV
For QE frequencies <500 MHz and e300 frequencies <667 MHz
For a QE frequency of 500 MHz or an e300 frequency of 667 MHz
PLL supply voltage
AV
V
V
1
DD
1.2 V 60 mV
1.3 V 50 mV
For QE frequencies <500 MHz and e300 frequencies <667 MHz
For a QE frequency of 500 MHz or an e300 frequency of 667 MHz
DDR and DDR2 DRAM I/O supply voltage
GV
DD
2.5 V 125 mV
1.8V 90 mV
DDR
DDR2
Three-speed Ethernet I/O supply voltage
Three-speed Ethernet I/O supply voltage
Three-speed Ethernet I/O supply voltage
LV
LV
LV
0
1
2
3.3 V 330 mV
2.5 V 125 mV
V
V
DD
DD
DD
3.3 V 330 mV
2.5 V 125 mV
3.3 V 330 mV
2.5 V 125 mV
V
2
PCI, local bus, DUART, system control and power management, I C, SPI,
OV
3.3 V 330 mV
V
DD
J
and JTAG I/O voltage
Junction temperature
Notes:
T
0 to 105
°C
2
1. GV , LV , OV , AV , and V must track each other and must vary in the same direction—either in the positive or
DD
DD
DD
DD
DD
negative direction.
2. .The operating conditions for junction temperature, T , on the 600/333/400 MHz and 500/333/500 MHz on rev2.0 silicon is
J
0 °C to 70 °C. Please refer to General9 in the device errata document.
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
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Freescale Semiconductor
Electrical Characteristics
Figure 3 shows the undershoot and overshoot voltages at the interfaces of the device.
G/L/OV + 20%
DD
G/L/OV + 5%
DD
G/L/OV
V
DD
IH
GND
GND – 0.3 V
V
IL
GND – 0.7 V
Not to Exceed 10%
1
of t
interface
Note:
1. Note that t
refers to the clock period associated with the bus clock interface.
interface
Figure 3. Overshoot/Undershoot Voltage for GV /OV /LV
DD
DD
DD
Figure 4 shows the undershoot and overshoot voltage of the PCI interface of the device for the 3.3-V
signals, respectively.
11 ns
(Min)
+7.1 V
Overvoltage
Waveform
7.1 V p-to-p
(Min)
0 V
4 ns
(Max)
4 ns
(Max)
62.5 ns
+3.6 V
7.1 V p-to-p
(Min)
Undervoltage
Waveform
–3.5 V
Figure 4. Maximum AC Waveforms on PCI interface for 3.3-V Signaling
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
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11
Electrical Characteristics
2.1.3
Output Driver Characteristics
Table 3 provides information on the characteristics of the output driver strengths. The values are
preliminary estimates.
Table 3. Output Drive Capability
Driver Type
Output Impedance (Ω)
Supply Voltage
OV = 3.3 V
Local bus interface utilities signals
PCI signals
42
25
42
20
DD
PCI output clocks (including PCI_SYNC_OUT)
DDR signal
GV = 2.5 V
DD
1
36 (half strength mode)
DDR2 signal
18
GV = 1.8 V
DD
1
36 (half strength mode)
10/100/1000 Ethernet signals
42
42
42
LV = 2.5/3.3 V
DD
2
DUART, system control, I C, SPI, JTAG
OV = 3.3 V
DD
GPIO signals
OV = 3.3 V
DD
LV = 2.5/3.3 V
DD
1
DDR output impedance values for half strength mode are verified by design and not tested
2.2
Power Sequencing
This section details the power sequencing considerations for the MPC8360E/58E.
2.2.1
Power-Up Sequencing
MPC8360E/58E does not require the core supply voltage (V and AV ) and I/O supply voltages
DD
DD
(GV , LV , and OV ) to be applied in any particular order. During the power ramp up, before the
DD
DD
DD
power supplies are stable and if the I/O voltages are supplied before the core voltage, there may be a period
of time that all input and output pins will actively be driven and cause contention and excessive current.
In order to avoid actively driving the I/O pins and to eliminate excessive current draw, apply the core
voltage (V ) before the I/O voltage (GV , LV , and OV ) and assert PORESET before the power
DD
DD
DD
DD
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
12 Freescale Semiconductor
Power Characteristics
supplies fully ramp up. In the case where the core voltage is applied first, the core voltage supply must rise
to 90% of its nominal value before the I/O supplies reach 0.7 V, see Figure 5.
Figure 5. Power Sequencing Example
Voltage
I/O Voltage (GV , LV , OV
)
DD
DD
DD
Core Voltage (V , AV
)
DD
DD
0.7 V
90%
Time
I/O voltage supplies (GV , LV , and OV ) do not have any ordering requirements with respect to one
DD
DD
DD
another.
2.2.2
Power-Down Sequencing
The MPC8360E/58E does not require the core supply voltage and I/O supply voltages to be powered-down
in any particular order.
3 Power Characteristics
The estimated typical power dissipation values are shown in Table 4 and Table 5.
1
Table 4. MPC8360E TBGA Core Power Dissipation
Core
CSB
QUICC Engine
Typical
Maximum
Unit
Notes
Frequency (MHz) Frequency (MHz) Frequency (MHz)
266
400
533
667
500
266
266
266
333
333
500
400
400
400
500
5.0
4.5
4.8
5.8
5.9
5.6
5.0
5.3
6.3
6.4
W
W
W
W
W
2, 3, 5
2, 3, 4
2, 3, 4
3, 6, 7, 8
3, 6, 7, 8
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 13
Power Characteristics
Core
1
Table 4. MPC8360E TBGA Core Power Dissipation (continued)
CSB
QUICC Engine
Typical
Maximum
Unit
Notes
Frequency (MHz) Frequency (MHz) Frequency (MHz)
667 333 500
6.1
6.8
W
2, 3, 5, 9
Notes:
1. The values do not include I/O supply power (OV , LV , GV ) or AV . For I/O power values, see Table 6.
DD
DD
DD
DD
2. Typical power is based on a voltage of V = 1.2 V or 1.3 V, a junction temperature of T = 105°C, and a Dhrystone
DD
J
benchmark application.
3. Thermal solutions will likely need to design to a value higher than typical power on the end application, T target, and I/O
A
power.
4. Maximum power is based on a voltage of V = 1.2 V, WC process, a junction T = 105°C, and an artificial smoke test.
DD
J
5. Maximum power is based on a voltage of V = 1.3 V for applications that use 667MHz(CPU)/500(QE) with WC process,
DD
a junction T = 105°C, and an artificial smoke test.
J
6. Typical power is based on a voltage of V = 1.3 V, a junction temperature of T = 70°C, and a Dhrystone benchmark
DD
J
application.
7. Maximum power is based on a voltage of V = 1.3 V for applications that use 667MHz(CPU) or 500(QE) with WC
DD
process, a junction T = 70°C, and an artificial smoke test.
J
8. This frequency combination is only available for rev2.0 silicon.
9. This frequency combination is not available for rev2.0 silicon.
1
Table 5. MPC8358E TBGA Core Power Dissipation
Core
CSB
QUICC Engine
Typical
Maximum
Unit
Notes
Frequency (MHz) Frequency (MHz) Frequency (MHz)
266
400
266
266
300
400
4.1
4.5
4.5
5.0
W
W
2, 3, 4
2, 3, 4
Notes:
1. The values do not include I/O supply power (OV , LV , GV ) or AV . For I/O power values, see Table 6.
DD
DD
DD
DD
2. Typical power is based on a voltage of V = 1.2 V, a junction temperature of T = 105°C, and a Dhrystone benchmark
DD
J
application.
3. Thermal solutions will likely need to design to a value higher than typical power on the end application, T target, and I/O
A
power.
4. Maximum power is based on a voltage of V = 1.2 V, WC process, a junction T = 105°C, and an artificial smoke test.
DD
J
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
14 Freescale Semiconductor
Clock Input Timing
Table 6 shows the estimated typical I/O power dissipation for the device.
Table 6. Estimated Typical I/O Power Dissipation
GV
GV
OV
LV
LV
DD
DD
DD
DD
DD
Interface
DDR I/O
Parameter
Unit
Comments
(1.8 V) (2.5 V) (3.3 V) (3.3 V) (2.5 V)
200 MHz, 1x32 bits
200 MHz, 1x64 bits
200 MHz, 2x32 bits
266 MHz, 1x32 bits
266 MHz, 1x64 bits
266 MHz, 2x32 bits
333 MHz, 1x32 bits
333 MHz, 1x64 bits
333 MHz, 2x32 bits
0.3
0.4
0.46
0.58
0.92
0.56
0.7
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
65% utilization
R = 20 Ω
s
0.6
R = 50 Ω
t
2 pairs of
clocks
0.35
0.46
0.7
1.11
0.65
0.82
1.3
0.4
0.53
0.81
Local Bus I/O 133 MHz, 32 bits
0.22
0.14
0.12
0.09
0.05
0.07
Load = 25 pf
83 MHz, 32 bits
3 pairs of
clocks
66 MHz, 32 bits
50 MHz, 32 bits
33 MHz, 32 bits
66 MHz, 32 bits
MII or RMII
PCI I/O
Load = 30 pf
10/100/1000
Ethernet I/O
0.01
0.04
Multiply by number
of interfaces used.
GMII or TBI
Load = 20 pf
RGMII or RTBI
0.04
Other I/O
0.1
4 Clock Input Timing
This section provides the clock input DC and AC electrical characteristics for the MPC8360E/58E.
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor
15
RESET Initialization
4.1
DC Electrical Characteristics
Table 7 provides the clock input (CLKIN/PCI_SYNC_IN) DC timing specifications for the device.
Table 7. CLKIN DC Electrical Characteristics
Parameter
Condition
Symbol
Min
Max
Unit
Input high voltage
—
—
V
2.7
–0.3
—
OV + 0.3
V
V
IH
DD
Input low voltage
V
I
0.4
10
10
IL
CLKIN input current
PCI_SYNC_IN input current
0 V ≤ V ≤ OV
μA
μA
IN
DD
IN
IN
0 V ≤ V ≤ 0.5V or
I
—
IN
OV – 0.5V ≤ V ≤ OV
DD
IN
DD
PCI_SYNC_IN input current
0.5 V ≤ V ≤ OV – 0.5 V
I
—
100
μA
IN
DD
IN
4.2
AC Electrical Characteristics
The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on
whether the device is configured in PCI host or PCI agent mode. Table 8 provides the clock input
(CLKIN/PCI_CLK) AC timing specifications for the device.
Table 8. CLKIN AC Timing Specifications
Parameter/Condition
CLKIN/PCI_CLK frequency
Symbol
Min
Typical
Max
Unit
Notes
f
t
—
15
0.6
40
—
—
—
66.67
—
MHz
ns
1
—
2
CLKIN
CLKIN
CLKIN/PCI_CLK cycle time
CLKIN/PCI_CLK rise and fall time
CLKIN/PCI_CLK duty cycle
CLKIN/PCI_CLK jitter
Notes:
t
, t
1.0
—
2.3
ns
KH KL
t
/t
60
%
3
KHK CLKIN
—
—
150
ps
4, 5
1. Caution: The system, core, USB, security, and 10/100/1000 Ethernet must not exceed their respective maximum or
minimum operating frequencies.
2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 V and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set
low to allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.
5 RESET Initialization
This section describes the DC and AC electrical specifications for the reset initialization timing and
electrical requirements of the MPC8360E/58E.
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
16
Freescale Semiconductor
RESET Initialization
5.1
RESET DC Electrical Characteristics
Table 9 provides the DC electrical characteristics for the RESET pins of the device.
Table 9. RESET Pins DC Electrical Characteristics
Characteristic
Input high voltage
Symbol
Condition
Min
Max
Unit
V
2.0
OV + 0.3
V
V
IH
DD
Input low voltage
Input current
V
I
–0.3
0.8
10
IL
μA
V
IN
Output high voltage
Output low voltage
Output low voltage
Notes:
V
I
= –8.0 mA
OH
2.4
—
—
OH
V
I
= 8.0 mA
= 3.2 mA
OL
0.5
0.4
V
OL
OL
V
I
—
V
OL
1. This table applies for pins PORESET, HRESET, SRESET and QUIESCE.
2. HRESET and SRESET are open drain pins, thus V is not relevant for those pins.
OH
5.2
RESET AC Electrical Characteristics
This section describes the AC electrical specifications for the reset initialization timing requirements of
the device. Table 10 provides the reset initialization AC timing specifications for the DDR SDRAM
component(s).
Table 10. RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Notes
Required assertion time of HRESET or SRESET
(input) to activate reset flow
32
—
t
1
PCI_SYNC_IN
Required assertion time of PORESET with stable
clock applied to CLKIN when the device is in PCI host
mode
32
32
—
—
t
2
1
CLKIN
Required assertion time of PORESET with stable
clock applied to PCI_SYNC_IN when the device is in
PCI agent mode
t
PCI_SYNC_IN
HRESET/SRESET assertion (output)
512
16
4
—
—
—
t
t
1
1
2
PCI_SYNC_IN
HRESET negation to SRESET negation (output)
PCI_SYNC_IN
Input setup time for POR config signals
(CFG_RESET_SOURCE[0:2] and
t
CLKIN
CFG_CLKIN_DIV) with respect to negation of
PORESET when the device is in PCI host mode
Input setup time for POR config signals
(CFG_RESET_SOURCE[0:2] and
CFG_CLKIN_DIV) with respect to negation of
PORESET when the device is in PCI agent mode
4
0
—
—
t
1
PCI_SYNC_IN
Input hold time for POR config signals with respect to
negation of HRESET
ns
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 17
RESET Initialization
Table 10. RESET Initialization Timing Specifications (continued)
Time for the device to turn off POR config signals with
—
4
ns
3
respect to the assertion of HRESET
Time for the device to turn on POR config signals with
respect to the negation of HRESET
1
—
t
1, 3
PCI_SYNC_IN
Notes:
1. t
is the clock period of the input clock applied to PCI_SYNC_IN. When the device is In PCI host mode
PCI_SYNC_IN
the primary clock is applied to the CLKIN input, and PCI_SYNC_IN period depends on the value of
CFG_CLKIN_DIV. See the MPC8360E Integrated Communications Processor Reference Manual, Rev. 2 for more
details.
2. t
is the clock period of the input clock applied to CLKIN. It is only valid when the device is in PCI host mode.
CLKIN
See the MPC8360E Integrated Communications Processor Reference Manual, Rev. 2 for more details.
3. POR config signals consists of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.
Table 11 provides the PLL and DLL lock times.
Table 11. PLL and DLL Lock Times
Parameter/Condition
Min
Max
Unit
Notes
PLL lock times
DLL lock times
Notes:
—
100
μs
7680
122,880
csb_clk cycles
1, 2
1. DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk).
A 2:1 ratio results in the minimum and an 8:1 ratio results in the maximum.
2. The csb_clk is determined by the CLKIN and system PLL ratio. See Section 22, “Clocking,” for more information.
5.3
QE Operating Frequency Limitations
This section specify the limits of the AC electrical characteristics for the operation of the QE’s
communication interfaces.
NOTE
The settings listed below are required for correct hardware interface
operation. Each protocol by itself requires a minimal QE operating
frequency setting for meeting the performance target. Because the
performance is a complex function of all the QE settings, the user should
make use of the QE performance utility tool provided by Freescale to
validate their system.
Table 12 lists the maximal QE I/O frequencies and the minimal QE core frequency for each interface.
Table 12. QE Operating Frequency Limitations
Interface Operating
Frequency (MHz)
Max interface
Bit Rate (Mbps) Frequency (MHz)
Min QE Operating
Interface
Notes
1
Ethernet Management:
MDC/MDIO
10 (max)
10
20
50
MII
25 (typ)
100
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
18 Freescale Semiconductor
DDR and DDR2 SDRAM
Table 12. QE Operating Frequency Limitations (continued)
Interface Operating
Frequency (MHz)
Max interface
Bit Rate (Mbps) Frequency (MHz)
Min QE Operating
Interface
Notes
1
RMII
50 (typ)
125 (typ)
10 (max)
50 (max)
25 (max)
50 (max)
50 (max)
10 (max)
50 (max)
100
1000
10
50
250
GMII/RGMII/TBI/RTBI
SPI (master/slave)
UCC through TDM
MCC
20
70
8 × F
16 × F
2 × F
2 × F
20
2
2, 4
2
16.67
800
UTOPIA L2
POS-PHY L2
800
2
HDLC Bus
10
HDLC/Transparent
UART/Async HDLC
50
8/3 × F
20
2, 3
3.68 (max internal ref
clock)
115 (Kbps)
BISYNC
USB
2 (max)
2
20
96
48 (ref clock)
12
Note:
1. The QE needs to run at a frequency higher than or equal to what is listed in this table.
2. ‘F’ is the actual interface operating frequency.
3. The bit rate limit is independent of the data bus width (i.e. the same for serial, nibble, or octal
interfaces).
4. TDM in high-speed mode for serial data interface.
6 DDR and DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR and DDR2 SDRAM interface
of the MPC8360E/58E.
6.1
DDR and DDR2 SDRAM DC Electrical Characteristics
Table 13 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the
device when GV (typ) = 1.8 V.
DD
Table 13. DDR2 SDRAM DC Electrical Characteristics for GV (typ) = 1.8 V
DD
Parameter/Condition
I/O supply voltage
Symbol
Min
Max
Unit
Notes
GV
MV
1.71
1.89
V
V
V
V
V
1
2
3
DD
I/O reference voltage
I/O termination voltage
Input high voltage
0.49 × GV
0.51 × GV
DD
REF
TT
DD
V
MV
– 0.04
MV
+ 0.04
REF
REF
REF
V
MV
+ 0.125
GV + 0.3
DD
IH
Input low voltage
V
–0.3
MV
– 0.125
REF
IL
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 19
DDR and DDR2 SDRAM
Table 13. DDR2 SDRAM DC Electrical Characteristics for GV (typ) = 1.8 V (continued)
DD
Output leakage current
Output high current (V
I
—
–13.4
13.4
—
10
—
μA
mA
mA
μA
4
OZ
= 1.420 V)
I
OH
OUT
Output low current (V
= 0.280 V)
I
—
OUT
OL
MV
input leakage current
I
10
REF
VREF
Input current (0 V ≤V ≤ OV
)
I
—
10
μA
IN
DD
IN
Notes:
1. GV is expected to be within 50 mV of the DRAM GV at all times.
DD
DD
2. MV
is expected to equal 0.5 × GV , and to track GV DC variations as measured at the receiver. Peak-to-peak noise
DD DD
REF
REF
on MV
cannot exceed 2% of the DC value.
3. V is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to equal
TT
MV . This rail should track variations in the DC level of MV
.
REF
REF
4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GV
.
DD
Table 14 provides the DDR2 capacitance when GVDD(typ) = 1.8 V.
Table 14. DDR2 SDRAM Capacitance for GV (typ)=1.8 V
DD
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input/output capacitance: DQ, DQS, DQS
Delta input/output capacitance: DQ, DQS, DQS
Note:
C
6
8
pF
pF
1
1
IO
C
—
0.5
DIO
1. This parameter is sampled. GV = 1.8 V 0.090 V, f = 1 MHz, T = 25°C, V
= GV /2, V
(peak-to-peak) = 0.2 V.
DD
A
OUT
DD
OUT
Table 15 provides the recommended operating conditions for the DDR SDRAM component(s) of the
device when GV (typ) = 2.5 V.
DD
Table 15. DDR SDRAM DC Electrical Characteristics for GV (typ) = 2.5 V
DD
Parameter/Condition
I/O supply voltage
Symbol
Min
Max
Unit
Notes
GV
MV
2.375
2.625
V
V
1
2
3
DD
I/O reference voltage
I/O termination voltage
Input high voltage
0.49 × GV
0.51 × GV
DD
REF
TT
DD
V
MV
– 0.04
+ 0.18
MV
+ 0.04
REF
V
REF
REF
V
MV
GV + 0.3
V
IH
DD
Input low voltage
V
I
–0.3
MV
– 0.18
REF
V
IL
Output leakage current
—
–15.2
15.2
—
10
μA
mA
mA
μA
4
OZ
OH
Output high current (V
= 1.95 V)
I
—
—
10
OUT
Output low current (V
= 0.35 V)
I
OL
OUT
MV
input leakage current
I
VREF
REF
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
20 Freescale Semiconductor
DDR and DDR2 SDRAM
Table 15. DDR SDRAM DC Electrical Characteristics for GV (typ) = 2.5 V (continued)
DD
Input current (0 V ≤V ≤ OV
)
I
IN
—
10
μA
IN
DD
Notes:
1. GV is expected to be within 50 mV of the DRAM GV at all times.
DD
DD
2. MV
is expected to be equal to 0.5 × GV , and to track GV DC variations as measured at the receiver.
DD DD
REF
Peak-to-peak noise on MV
may not exceed 2% of the DC value.
REF
3. V is not applied directly to the device. It is the supply to which far end signal termination is made and is expected
TT
to be equal to MV
. This rail should track variations in the DC level of MV
.
REF
REF
4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GV
.
DD
Table 16 provides the DDR capacitance when GV (typ) = 2.5 V.
DD
Table 16. DDR SDRAM Capacitance for GV (typ) = 2.5 V
DD
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input/output capacitance: DQ, DQS
Delta input/output capacitance: DQ, DQS
Note:
C
6
8
pF
pF
1
1
IO
C
—
0.5
DIO
1. This parameter is sampled. GV = 2.5 V 0.125 V, f = 1 MHz, T = 25°C, V
= GV /2, V
(peak to peak) =
DD
A
OUT
DD
OUT
0.2 V.
6.2
DDR and DDR2 SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR and DDR2 SDRAM interface.
6.2.1
DDR and DDR2 SDRAM Input AC Timing Specifications
Table 17 provides the input AC timing specifications for the DDR2 SDRAM interface when
GV (typ) = 1.8 V.
DD
Table 17. DDR2 SDRAM Input AC Timing Specifications for GV (typ) = 1.8 V
DD
At recommended operating conditions with GVDD of 1.8 V 5%.
Parameter Symbol
Min
Max
Unit
Notes
AC input low voltage
AC input high voltage
V
—
MV
– 0.25
REF
V
V
IL
V
MV
+ 0.25
—
IH
REF
Table 18 provides the input AC timing specifications for the DDR SDRAM interface when
GV (typ) = 2.5 V.
DD
Table 18. DDR SDRAM Input AC Timing Specifications Mode for GV (typ) = 2.5 V
DD
At recommended operating conditions with GVDD of 2.5 V 5%.
Parameter Symbol
AC input low voltage
Min
Max
– 0.31
REF
Unit
Notes
V
—
MV
V
IL
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 21
DDR and DDR2 SDRAM
Table 18. DDR SDRAM Input AC Timing Specifications Mode for GV (typ) = 2.5 V (continued)
DD
At recommended operating conditions with GVDD of 2.5 V 5%.
AC input high voltage
V
MV
+ 0.31
—
V
IH
REF
Notes:
1. Maximum possible skew between a data strobe (MDQS[n]) and any corresponding bit of data (MDQ[8n + {0...7}] if
0 ≤ n ≤ 7) or ECC (MECC[{0...7}] if n = 8).
Table 19. DDR and DDR2 SDRAM Input AC Timing Specifications Mode for GV (typ) = 2.5 V
DD
At recommended operating conditions with GVDD of 2.5 V 5%.
Parameter
Symbol
Min
Max
Unit
Notes
MDQS—MDQ/MECC input skew per byte
t
ps
1, 2
DISKEW
-750
-1125
-1250
750
1125
1250
333 MHz
266 MHz
200 MHz
Notes:
1. AC timing values are based on the DDR data rate, which is twice the DDR memory bus frequency.
2. Maximum possible skew between a data strobe (MDQS[n]) and any corresponding bit of data (MDQ[8n + {0...7}] if
0 ≤ n ≤ 7) or ECC (MECC[{0...7}] if n = 8).
6.2.2
DDR and DDR2 SDRAM Output AC Timing Specifications
Table 20 and Table 21 provide the output AC timing specifications and measurement conditions for the
DDR and DDR2 SDRAM interface.
Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications for Source Synchronous Mode
At recommended operating conditions with GVDD of (1.8 V or 2.5 V) 5%.
8
1
Parameter
Symbol
Min
Max
Unit
Notes
MCK[n] cycle time, (MCK[n]/MCK[n] crossing)
Skew between any MCK to ADDR/CMD
t
6
10
ns
ns
2
3
MCK
t
AOSKEW
-1.0
-1.1
-1.2
0.2
0.3
0.4
333 MHz
266 MHz
200 MHz
ADDR/CMD output setup with respect to MCK
t
—
ns
ns
4
4
DDKHAS
2.1
2.8
3.5
333 MHz
266 MHz
200 MHz
ADDR/CMD output hold with respect to MCK
t
—
DDKHAX
2.0
2.72.8
3.5
333 MHz
266 MHz - DDR1
266 MHz - DDR2
200 MHz
MCS(n) output setup with respect to MCK
t
—
ns
4
DDKHCS
2.1
2.8
3.5
333 MHz
266 MHz
200 MHz
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
22 Freescale Semiconductor
DDR and DDR2 SDRAM
Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications for Source Synchronous Mode
(continued)
8
1
Parameter
MCS(n) output hold with respect to MCK
Symbol
Min
Max
Unit
Notes
t
—
ns
4
DDKHCX
2.0
2.7
3.5
333 MHz
266 MHz
200 MHz
MCK to MDQS
t
–0.8
0.7
—
ns
ns
5, 9
6
DDKHMH
MDQ/MECC/MDM output setup with respect to MDQS
t
,
DDKHDS
t
0.7
1.0
1.2
333 MHz
266 MHz
200 MHz
DDKLDS
MDQ/MECC/MDM output hold with respect to MDQS
t
,
—
ns
6
DDKHDX
t
0.7
1.0
1.2
333 MHz
266 MHz
200 MHz
DDKLDX
MDQS preamble start
MDQS epilogue end
Notes:
t
t
-0.5 × t
– 0.6 -0.5 × t
+ 0.6
ns
ns
7
7
DDKHMP
MCK
MCK
–0.6
0.9
DDKHME
1. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state) (reference)(state)
inputs and t
for outputs. Output hold time can be read as DDR timing
(first two letters of functional block)(reference)(state)(signal)(state)
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
symbolizes DDR timing (DD) for the time t memory clock reference (K) goes from the high (H) state until outputs
t
DDKHAS
MCK
(A) are setup (S) or output valid time. Also, t
symbolizes DDR timing (DD) for the time t
memory clock reference
DDKLDX
MCK
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals 0.1 V.
3. In the source synchronous mode, MCK/MCK can be shifted in 1/4 applied cycle increments through the Clock Control
Register. For the skew measurements referenced for t
address/command valid with the rising edge of MCK.
it is assumed that the clock adjustment is set to align the
AOSKEW
4. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. For the
ADDR/CMD setup and hold specifications, it is assumed that the Clock Control register is set to adjust the memory clocks
by 1/2 applied cycle.
5. Note that t
follows the symbol conventions described in note 1. For example, t
describes the DDR timing
DDKHMH
DDKHMH
(DD) from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). t
can be modified through
DDKHMH
control of the DQSS override bits in the TIMING_CFG_2 register. In source synchronous mode, this will typically be set to
the same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these
2 parameters have been set to the same adjustment value. See the MPC8360E Integrated Communications Processor
Reference Manual, Rev. 2 for a description and understanding of the timing modifications enabled by use of these bits.
6. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the device.
7. All outputs are referenced to the rising edge of MCK(n) at the pins of the device. Note that t
conventions described in note 1.
follows the symbol
DDKHMP
8. AC timing values are based on the DDR data rate, which is twice the DDR memory bus frequency.
9. In rev2.0 silicon, t maximum meets the specification of 0.6ns. In rev 2.0 silicon, due to errata, t
minimum is
DDKHMH
DDKHMH
-0.9 ns. Please refer to DDR18 in the device errata document.
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 23
DDR and DDR2 SDRAM
Figure 6 shows the DDR SDRAM output timing for address skew with respect to any MCK.
MCK[n]
MCK[n]
t
MCK
t
AOSKEW(max)
ADDR/CMD
ADDR/CMD
CMD
NOOP
t
AOSKEW(min)
CMD
NOOP
Figure 6. Timing Diagram for t
Measurement
AOSKEW
Figure 7 provides the AC test load for the DDR bus.
Output
GV /2
DD
Z = 50 Ω
0
R = 50 Ω
L
Figure 7. DDR AC Test Load
Table 21. DDR and DDR2 SDRAM Measurement Conditions
Symbol
DDR
DDR2
Unit
Notes
V
V
MV
0.31 V
MV
0.25 V
0.5 × GV
V
V
1
2
TH
REF
REF
0.5 × GV
DD
DD
OUT
Notes:
1. Data input threshold measurement point.
2. Data output measurement point.
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
24 Freescale Semiconductor
DDR and DDR2 SDRAM
Figure 8 shows the DDR SDRAM output timing diagram for source synchronous mode.
MCK[n]
MCK[n]
t
MCK
t
,t
DDKHAS DDKHCS
t
,t
DDKHAX DDKHCX
ADDR/CMD
Write A0
NOOP
t
DDKHMP
t
DDKHMH
MDQS[n]
MDQ[x]
t
DDKHME
t
DDKHDS
t
DDKLDS
D0
D1
t
DDKLDX
t
DDKHDX
Figure 8. DDR SDRAM Output Timing Diagram for Source Synchronous Mode
Table 22 provides approximate delay information that can be expected for the address and command
signals of the DDR controller for various loadings, which can be useful for a system utilizing the DLL.
These numbers are the result of simulations for one topology. The delay numbers will strongly depend on
the topology used. These delay numbers show the total delay for the address and command to arrive at the
DRAM devices. The actual delay could be different than the delays seen in simulation, depending on the
system topology. If a heavily loaded system is used, the DLL loop may need to be adjusted to meet setup
requirements at the DRAM.
Table 22. Expected Delays for Address/Command
Load
Delay
Unit
4 devices (12 pF)
9 devices (27 pF)
3.0
3.6
5.0
5.2
ns
ns
ns
ns
36 devices (108 pF) + 40 pF compensation capacitor
36 devices (108 pF) + 80 pF compensation capacitor
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 25
DUART
7 DUART
This section describes the DC and AC electrical specifications for the DUART interface of the
MPC8360E/58E.
7.1
DUART DC Electrical Characteristics
Table 23 provides the DC electrical characteristics for the DUART interface of the device.
Table 23. DUART DC Electrical Characteristics
Parameter
High-level input voltage
Symbol
Min
Max
Unit
Notes
V
2
OV + 0.3
V
V
V
IH
DD
Low-level input voltage OV
V
–0.3
0.8
—
DD
IL
High-level output voltage,
V
OV – 0.4
OH
DD
I
= –100 μA
OH
Low-level output voltage,
= 100 μA
V
—
—
0.2
10
V
OL
I
OL
Input current
I
μA
1
IN
(0 V ≤V ≤ OV
)
DD
IN
Note:
1. Note that the symbol V , in this case, represents the OV symbol referenced in Table 1 and Table 2.
IN
IN
7.2
DUART AC Electrical Specifications
Table 24 provides the AC timing parameters for the DUART interface of the device.
Table 24. DUART AC Timing Specifications
Parameter
Minimum baud rate
Value
Unit
Notes
256
> 1,000,000
16
baud
baud
—
Maximum baud rate
Oversample rate
Notes:
1
2
1. Actual attainable baud rate will be limited by the latency of interrupt processing.
th
2. The middle of a start bit is detected as the 8 sampled 0 after the 1-to-0 transition
th
of the start bit. Subsequent bit values are sampled each 16 sample.
8 UCC Ethernet Controller: Three-Speed Ethernet, MII
Management
This section provides the AC and DC electrical characteristics for three-speed, 10/100/1000, and MII
management.
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
26
Freescale Semiconductor
UCC Ethernet Controller: Three-Speed Ethernet, MII Management
8.1
Three-Speed Ethernet Controller (10/100/1000 Mbps)—
GMII/MII/RMII/TBI/RGMII/RTBI Electrical Characteristics
The electrical characteristics specified here apply to all GMII (gigabit media independent interface), MII
(media independent interface), RMII (reduced media independent interface), TBI (ten-bit interface),
RGMII (reduced gigabit media independent interface), and RTBI (reduced ten-bit interface) signals except
MDIO (management data input/output) and MDC (management data clock). The MII, RMII, GMII and
TBI interfaces are only defined for 3.3V, while the RGMII and RTBI interfaces are only defined for 2.5 V.
The RGMII and RTBI interfaces follow the Hewlett-Packard reduced pin-count interface for Gigabit
Ethernet Physical Layer Device Specification Version 1.2a (9/22/2000). The electrical characteristics for
the MDIO and MDC are specified in Section 8.3, “Ethernet Management Interface Electrical
Characteristics.”
8.1.1
10/100/1000 Ethernet DC Electrical Characteristics
All GMII, MII, RMII, TBI, RGMII, and RTBI drivers and receivers comply with the DC parametric
attributes specified in Table 25 and Table 26. The potential applied to the input of a GMII, MII, RMII, TBI,
RGMII, or RTBI receiver may exceed the potential of the receiver’s power supply (i.e., a RGMII driver
powered from a 3.6-V supply driving V into a RGMII receiver powered from a 2.5 V supply). Tolerance
OH
for dissimilar RGMII driver and receiver supply potentials is implicit in these specifications. The RGMII
and RTBI signals are based on a 2.5-V CMOS interface voltage as defined by JEDEC EIA/JESD8-5.
Table 25. RGMII/RTBI, GMII, TBI, MII, and RMII DC Electrical Characteristics (when operating at 3.3 V)
Parameter
Symbol
Conditions
Min
Max
Unit
Notes
Supply voltage 3.3 V
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Input current
LV
—
2.97
2.40
GND
2.0
3.63
V
V
1
DD
V
IOH = –4.0 mA
LV = Min
LV + 0.3
OH
DD
DD
V
IOL = 4.0 mA
LV = Min
0.50
V
OL
DD
V
—
—
—
—
LV + 0.3
V
IH
DD
V
I
–0.3
—
0.90
10
V
IL
0 V ≤ V ≤ LV
DD
μA
IN
IN
Note:
1. GMII/MII pins that are not needed for RGMII, RMII or RTBI operation are powered by the OV supply.
DD
Table 26. RGMII/RTBI DC Electrical Characteristics (when operating at 2.5 V)
Parameters
Symbol
LV
Conditions
Min
Max
Unit
Supply voltage 2.5 V
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Input current
—
2.37
2.00
2.63
V
V
DD
V
IOH = –1.0 mA
LV = Min
LV + 0.3
OH
DD
DD
V
I
= 1.0 mA
LV = Min
GND – 0.3
1.7
0.40
V
OL
OL
DD
V
—
—
LV = Min
LV + 0.3
V
IH
DD
DD
V
LV = Min
–0.3
0.70
10
V
IL
DD
I
0 V ≤ V ≤ LV
DD
—
μA
IN
IN
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 27
UCC Ethernet Controller: Three-Speed Ethernet, MII Management
8.2
GMII, MII, RMII, TBI, RGMII, and RTBI AC Timing Specifications
The AC timing specifications for GMII, MII, TBI, RGMII, and RTBI are presented in this section.
8.2.1
GMII Timing Specifications
This sections describe the GMII transmit and receive AC timing specifications.
8.2.1.1
GMII Transmit AC Timing Specifications
Table 27 provides the GMII transmit AC timing specifications.
Table 27. GMII Transmit AC Timing Specifications
At recommended operating conditions with LVDD / OVDD of 3.3 V 10%.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit Notes
GTX_CLK clock period
t
—
8.0
—
—
ns
%
GTX
GTX_CLK duty cycle
t
40
60
GTXH/tGTX
GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay
t
t
0.5
—
—
—
5.0
ns
3
GTKHDX
GTKHDV
GTX_CLK clock rise time, VIL(min) to VIH(max)
GTX_CLK clock fall time, VIH(max) to VIL(min)
GTX_CLK125 clock period
t
—
—
—
45
—
—
1.0
1.0
—
ns
ns
ns
%
GTXR
t
GTXF
t
8.0
—
2
2
G125
GTX_CLK125 reference clock duty cycle measured at LV
t
/t
55
DD/2
G125H G125
Notes:
1. The symbols used for timing specifications herein follow the pattern t
(first two letters of functional block)(signal)(state)
for inputs and t
for outputs. For example, t
(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
GTKHDV
symbolizes GMII transmit timing (GT) with respect to the t
clock reference (K) going to the high state (H) relative to the
GTX
time date input signals (D) reaching the valid state (V) to state or setup time. Also, t
symbolizes GMII transmit
GTKHDX
timing (GT) with respect to the t
clock reference (K) going to the high state (H) relative to the time date input signals
GTX
(D) going invalid (X) or hold time. Note that, in general, the clock reference symbol representation is based on three letters
representing the clock of a particular functional. For example, the subscript of t represents the GMII(G) transmit (TX)
GTX
clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. This symbol is used to represent the external GTX_CLK125 signal and does not follow the original symbol naming
convention.
3. In rev 2.0 silicon, due to errata, t
minimum and t
maximum are not supported when the GTX_CLK is
GTKHDX
GTKHDV
selected. Please refer to QE_ENET18 in the device errata document.
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
28
Freescale Semiconductor
UCC Ethernet Controller: Three-Speed Ethernet, MII Management
Figure 9 shows the GMII transmit AC timing diagram.
t
t
GTX
GTXR
GTX_CLK
t
t
GTXF
GTXH
TXD[7:0]
TX_EN
TX_ER
t
GTKHDX
Figure 9. GMII Transmit AC Timing Diagram
8.2.1.2
GMII Receive AC Timing Specifications
Table 28 provides the GMII receive AC timing specifications.
Table 28. GMII Receive AC Timing Specifications
At recommended operating conditions with LVDD / OVDD of 3.3 V 10%.
Parameter/Condition Symbol
RX_CLK clock period
1
Min
Typ
Max
Unit
Notes
t
—
40
2.0
0.2
—
8.0
—
—
—
—
—
—
60
—
ns
%
GRX
RX_CLK duty cycle
t
/t
GRXH GRX
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
RX_CLK clock rise time, VIL(min) to VIH(max)
RX_CLK clock fall time, VIH(max) to VIL(min)
Note:
t
ns
ns
ns
ns
GRDVKH
t
—
2
GRDXKH
t
1.0
1.0
GRXR
t
—
GRXF
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t
for outputs. For example, t
symbolizes GMII
(first two letters of functional block)(reference)(state)(signal)(state)
GRDVKH
receive timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the t clock reference
RX
(K) going to the high state (H) or setup time. Also, t
symbolizes GMII receive timing (GR) with respect to the time data
GRDXKL
input signals (D) went invalid (X) relative to the t
clock reference (K) going to the low (L) state or hold time. Note that, in
GRX
general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.
For example, the subscript of t represents the GMII (G) receive (RX) clock. For rise and fall times, the latter convention is
GRX
used with the appropriate letter: R (rise) or F (fall).
2. In rev 2.0 silicon, due to errata, t
in the device errata document.
minimum is 0.5 which is not compliant with the standard. Please refer to QE_ENET18
GRDXKH
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 29
UCC Ethernet Controller: Three-Speed Ethernet, MII Management
Figure 10 shows the GMII receive AC timing diagram.
t
t
GRXR
GRX
RX_CLK
t
t
GRXF
GRXH
RXD[7:0]
RX_DV
RX_ER
t
GRDXKH
t
GRDVKH
Figure 10. GMII Receive AC Timing Diagram
8.2.2
MII AC Timing Specifications
This section describes the MII transmit and receive AC timing specifications.
8.2.2.1
MII Transmit AC Timing Specifications
Table 29 provides the MII transmit AC timing specifications.
Table 29. MII Transmit AC Timing Specifications
At recommended operating conditions with LVDD / OVDD of 3.3 V 10%.
Parameter/Condition Symbol
TX_CLK clock period 10 Mbps
1
Min
Typ
Max
Unit
t
t
—
—
35
400
40
—
5
—
—
65
ns
ns
%
MTX
MTX
TX_CLK clock period 100 Mbps
TX_CLK duty cycle
t
/t
MTXH MTX
TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay
t
1
—
ns
MTKHDX
t
—
15
MTKHDV
TX_CLK data clock rise time, VIL(min) to VIH(max)
TX_CLK data clock fall time, VIH(max) to VIL(min)
Note:
t
1.0
1.0
—
—
4.0
4.0
ns
ns
MTXR
t
MTXF
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state)
for inputs and t
for outputs. For example,
(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
t
symbolizes MII transmit timing (MT) for the time t
clock reference (K) going high (H) until data outputs
MTKHDX
MTX
(D) are invalid (X). Note that, in general, the clock reference symbol representation is based on two to three letters
representing the clock of a particular functional. For example, the subscript of t represents the MII(M) transmit
MTX
(TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
30
Freescale Semiconductor
UCC Ethernet Controller: Three-Speed Ethernet, MII Management
Figure 11 shows the MII transmit AC timing diagram.
t
t
MTXR
MTX
TX_CLK
t
t
MTXF
MTXH
TXD[3:0]
TX_EN
TX_ER
t
MTKHDX
Figure 11. MII Transmit AC Timing Diagram
8.2.2.2
MII Receive AC Timing Specifications
Table 30 provides the MII receive AC timing specifications.
Table 30. MII Receive AC Timing Specifications
At recommended operating conditions with LVDD / OVDD of 3.3 V 10%.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
RX_CLK clock period 10 Mbps
RX_CLK clock period 100 Mbps
t
t
—
—
400
40
—
—
—
ns
ns
%
MRX
MRX
RX_CLK duty cycle
t
/t
35
65
—
MRXH MRX
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
RX_CLK clock rise time, VIL(min) to VIH(max)
RX_CLK clock fall time, VIH(max) to VIL(min)
Note:
t
10.0
10.0
1.0
1.0
—
ns
ns
ns
ns
MRDVKH
MRDXKH
t
—
—
t
—
4.0
4.0
MRXR
t
—
MRXF
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state)
for inputs and t
for outputs. For example, t
(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
MRDVKH
symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to
the t clock reference (K) going to the high (H) state or setup time. Also, t symbolizes MII receive timing
MRX
MRDXKL
(GR) with respect to the time data input signals (D) went invalid (X) relative to the t
clock reference (K) going to
MRX
the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three
letters representing the clock of a particular functional. For example, the subscript of t represents the MII (M)
MRX
receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
Figure 12 provides the AC test load.
Output
LV /2
DD
Z = 50 Ω
0
R = 50 Ω
L
Figure 12. AC Test Load
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 31
UCC Ethernet Controller: Three-Speed Ethernet, MII Management
Figure 13 shows the MII receive AC timing diagram.
t
t
MRXR
MRX
RX_CLK
t
t
MRXH
MRXF
RXD[3:0]
RX_DV
RX_ER
Valid Data
t
MRDVKH
t
MRDXKH
Figure 13. MII Receive AC Timing Diagram
8.2.3
RMII AC Timing Specifications
This section describes the RMII transmit and receive AC timing specifications.
8.2.3.1
RMII Transmit AC Timing Specifications
Table 31 provides the RMII transmit AC timing specifications.
Table 31. RMII Transmit AC Timing Specifications
At recommended operating conditions with LVDD / OVDD of 3.3 V 10%.
1
Parameter/Condition Symbol
Min
Typ
Max
Unit
REF_CLK clock
t
—
20
—
—
—
65
ns
%
RMX
REF_CLK duty cycle
t
/t
35
RMXH RMX
REF_CLK to RMII data TXD[1:0], TX_EN delay
t
t
2
—
—
10
ns
RMTKHDX
RMTKHDV
REF_CLK data clock rise time, VIL(min) to VIH(max)
REF_CLK data clock fall time, VIH(max) to VIL(min)
Note:
t
1.0
1.0
—
—
4.0
4.0
ns
ns
RMXR
t
RMXF
1. The symbols used for timing specifications herein follow the pattern of t
(first three letters of functional block)(signal)(state)
for inputs and t
for outputs. For example,
(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
t
symbolizes RMII transmit timing (RMT) for the time t
clock reference (K) going high (H) until data
RMX
RMTKHDX
outputs (D) are invalid (X). Note that, in general, the clock reference symbol representation is based on two to three
letters representing the clock of a particular functional. For example, the subscript of t represents the RMII(RM)
RMX
reference (X) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
32
Freescale Semiconductor
UCC Ethernet Controller: Three-Speed Ethernet, MII Management
Figure 14 shows the RMII transmit AC timing diagram.
t
t
RMXR
RMX
REF_CLK
t
t
RMXF
RMXH
TXD[1:0]
TX_EN
t
RMTKHDX
Figure 14. RMII Transmit AC Timing Diagram
8.2.3.2
RMII Receive AC Timing Specifications
Table 32 provides the RMII receive AC timing specifications.
Table 32. RMII Receive AC Timing Specifications
At recommended operating conditions with LVDD / OVDD of 3.3 V 10%.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
REF_CLK clock period
t
—
20
—
—
—
—
—
—
65
—
ns
%
RMX
REF_CLK duty cycle
t
/t
35
RMXH RMX
RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK
RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK
REF_CLK clock rise time, VIL(min) to VIH(max)
REF_CLK clock fall time, VIH(max) to VIL(min)
Note:
t
4.0
2.0
1.0
1.0
ns
ns
ns
ns
RMRDVKH
RMRDXKH
t
—
t
4.0
4.0
RMXR
t
RMXF
1. The symbols used for timing specifications herein follow the pattern of t
(first three letters of functional block)(signal)(state)
for inputs and t
for outputs. For example,
(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
t
symbolizes RMII receive timing (RMR) with respect to the time data input signals (D) reach the valid state
RMRDVKH
(V) relative to the t
clock reference (K) going to the high (H) state or setup time. Also, t
symbolizes RMII
RMX
RMRDXKL
receive timing (RMR) with respect to the time data input signals (D) went invalid (X) relative to the t
clock
RMX
reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation
is based on three letters representing the clock of a particular functional. For example, the subscript of t
RMX
represents the RMII (RM) reference (X) clock. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
Figure 15 provides the AC test load.
Output
LV /2
DD
Z = 50 Ω
0
R = 50 Ω
L
Figure 15. AC Test Load
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 33
UCC Ethernet Controller: Three-Speed Ethernet, MII Management
Figure 16 shows the RMII receive AC timing diagram.
t
t
RMXR
RMX
REF_CLK
t
t
RMXH
RMXF
RXD[1:0]
CRS_DV
RX_ER
Valid Data
t
RMRDVKH
t
RMRDXKH
Figure 16. RMII Receive AC Timing Diagram
8.2.4
TBI AC Timing Specifications
This section describes the TBI transmit and receive AC timing specifications.
8.2.4.1
TBI Transmit AC Timing Specifications
Table 33 provides the TBI transmit AC timing specifications.
Table 33. TBI Transmit AC Timing Specifications
At recommended operating conditions with LVDD / OVDD of 3.3 V 10%.
Parameter/Condition Symbol
GTX_CLK clock period
1
Min
Typ
Max
Unit
Notes
t
—
8.0
—
—
ns
%
TTX
GTX_CLK duty cycle
t
/t
40
60
TTXH TTX
GTX_CLK to TBI data TCG[9:0] delay
t
t
1.0
—
—
—
5.0
ns
3
TTKHDX
TTKHDV
GTX_CLK clock rise time, VIL(min) to VIH(max)
GTX_CLK clock fall time, VIH(max) to VIL(min)
GTX_CLK125 reference clock period
GTX_CLK125 reference clock duty cycle
Notes:
t
—
—
—
45
—
—
1.0
1.0
—
ns
ns
ns
ns
TTXR
t
TTXF
t
8.0
—
2
G125
t
/t
55
G125H G125
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state
for inputs and t
for outputs. For example, t
)(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
TTKHDV
symbolizes the TBI transmit timing (TT) with respect to the time from t
(K) going high (H) until the referenced data
TTX
signals (D) reach the valid state (V) or setup time. Also, t
symbolizes the TBI transmit timing (TT) with respect to
TTKHDX
the time from t
(K) going high (H) until the referenced data signals (D) reach the invalid state (X) or hold time. Note
TTX
that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular
functional. For example, the subscript of t represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter
TTX
convention is used with the appropriate letter: R (rise) or F (fall).
2. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.
3. In rev 2.0 silicon, due to errata, t
document.
minimum is 0.7 ns for UCC1. Please refer to QE_ENET19 in the device errata
TTKHDX
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
34 Freescale Semiconductor
UCC Ethernet Controller: Three-Speed Ethernet, MII Management
Figure 17 shows the TBI transmit AC timing diagram.
t
t
TTX
TTXR
GTX_CLK
t
TTXH
t
TTXF
TXD[7:0]
TX_EN
TX_ER
t
TTKHDX
Figure 17. TBI Transmit AC Timing Diagram
8.2.4.2
TBI Receive AC Timing Specifications
Table 34 provides the TBI receive AC timing specifications.
Table 34. TBI Receive AC Timing Specifications
At recommended operating conditions with LVDD / OVDD of 3.3 V 10%.
Parameter/Condition Symbol
PMA_RX_CLK clock period
1
Min
Typ
Max
Unit
Notes
t
16.0
—
ns
ns
%
TRX
PMA_RX_CLK skew
t
7.5
40
8.5
60
—
SKTRX
RX_CLK duty cycle
t
/t
—
TRXH TRX
RCG[9:0] setup time to rising PMA_RX_CLK
2.5
—
ns
2
2
t
TRDVKH
TRDXKH
RCG[9:0] hold time to rising PMA_RX_CLK
1.0
—
—
ns
t
RX_CLK clock rise time, VIL(min) to VIH(max)
RX_CLK clock fall time, VIH(max) to VIL(min)
Notes:
t
0.7
0.7
—
—
2.4
2.4
ns
ns
TRXR
t
TRXF
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state)
for inputs and t
for outputs. For example, t
(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
TRDVKH
symbolizes TBI receive timing (TR) with respect to the time data input signals (D) reach the valid state (V) relative to the
clock reference (K) going to the high (H) state or setup time. Also, t symbolizes TBI receive timing (TR) with
t
TRX
TRDXKH
respect to the time data input signals (D) went invalid (X) relative to the t
clock reference (K) going to the high (H) state.
TRX
Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a
particular functional. For example, the subscript of t represents the TBI (T) receive (RX) clock. For rise and fall times,
TRX
the latter convention is used with the appropriate letter: R (rise) or F (fall). For symbols representing skews, the subscript
is skew (SK) followed by the clock that is being skewed (TRX).
2. Setup and hold time of even numbered RCG are measured from riding edge of PMA_RX_CLK1. Setup and hold time of
odd numbered RCG are measured from riding edge of PMA_RX_CLK0.
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor
35
UCC Ethernet Controller: Three-Speed Ethernet, MII Management
Figure 18 shows the TBI receive AC timing diagram.
t
t
TRXR
TRX
PMA_RX_CLK1
t
t
TRXH
TRXF
RCG[9:0]
Even RCG
Odd RCG
t
TRDVKH
t
TRDXKH
t
SKTRX
PMA_RX_CLK0
t
t
TRDXKH
TRXH
t
TRDVKH
Figure 18. TBI Receive AC Timing Diagram
8.2.5
RGMII and RTBI AC Timing Specifications
Table 35 presents the RGMII and RTBI AC timing specifications.
Table 35. RGMII and RTBI AC Timing Specifications
At recommended operating conditions with LVDD of 2.5 V 5%.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Notes
Data to clock output skew (at transmitter)
t
t
–0.5
—
—
—
0.5
ns
7
SKRGTKHDX
SKRGTKHDV
Data to clock input skew (at receiver)
t
t
1.0
—
—
—
2.6
ns
2
SKRGDXKH
SKRGDVKH
Clock cycle duration
t
7.2
45
40
—
8.0
50
50
—
8.8
55
ns
%
3
RGT
Duty cycle for 1000Base-T
Duty cycle for 10BASE-T and 100BASE-TX
Rise time (20%–80%)
t
t
/t
4, 5
3, 5
RGTH RGT
/t
60
%
RGTH RGT
t
0.75
0.75
—
ns
ns
ns
RGTR
Fall time (20%–80%)
t
—
—
RGTF
GTX_CLK125 reference clock period
t
—
8.0
6
G125
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
36 Freescale Semiconductor
UCC Ethernet Controller: Three-Speed Ethernet, MII Management
Table 35. RGMII and RTBI AC Timing Specifications (continued)
At recommended operating conditions with LVDD of 2.5 V 5%.
GTX_CLK125 reference clock duty cycle
t
/t
47
—
53
%
G125H G125
Notes:
1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent
RGMII and RTBI timing. For example, the subscript of t represents the TBI (T) receive (RX) clock. Note also that the
RGT
notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews,
the subscript is skew (SK) followed by the clock that is being skewed (RGT).
2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns
will be added to the associated clock signal.
3. For 10 and 100 Mbps, t
scales to 400 ns 40 ns and 40 ns 4 ns, respectively.
RGT
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long
as the minimum duty cycle is not violated and stretching occurs for no more than three t
between.
of the lowest speed transitioned
RGT
5. Duty cycle reference is LV /2.
DD
6. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.
7. In rev 2.0 silicon, due to errata, t
minimum is -2.3 ns and t
maximum is 1 ns for UCC1, 1.2 ns for UCC2
minimum is -0.65 ns for UCC2 option 1 and
SKRGTKHDX
SKRGTKHDV
option 1, and 1.8 for UCC2 option 2. In rev2.1 silicon, due to errata, t
-0.9 for UCC2 option 2, and t
SKRGTKHDX
maximum is 0.75 ns for UCC1 and UCC2 option 1 and 0.85 for UCC2 option 2.
SKRGTKHDV
Please refer to QE_ENET10 in the device errata document. UCC1 does meet t
minimum for rev2.1 silicon.
SKRGTKHDX
Figure 19 shows the RGMII and RTBI AC timing and multiplexing diagrams.
t
RGT
t
RGTH
GTX_CLK
(At Transmitter)
t
SKRGTKHDX
TXD[8:5][3:0]
TXD[7:4][3:0]
TXD[8:5]
TXD[7:4]
TXD[3:0]
TXD[9]
TXERR
TXD[4]
TXEN
TX_CTL
t
SKRGTKHDX
TX_CLK
(At PHY)
RXD[8:5][3:0]
RXD[7:4][3:0]
RXD[8:5]
RXD[7:4]
RXD[3:0]
t
SKRGTKHDX
RXD[9]
RXERR
RXD[4]
RXDV
RX_CTL
t
SKRGTKHDX
RX_CLK
(At PHY)
Figure 19. RGMII and RTBI AC Timing and Multiplexing Diagrams
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 37
UCC Ethernet Controller: Three-Speed Ethernet, MII Management
8.3
Ethernet Management Interface Electrical Characteristics
The electrical characteristics specified here apply to MII management interface signals MDIO
(management data input/output) and MDC (management data clock). The electrical characteristics for
GMII, RGMII, TBI and RTBI are specified in Section 8.1, “Three-Speed Ethernet Controller
(10/100/1000 Mbps)— GMII/MII/RMII/TBI/RGMII/RTBI Electrical Characteristics.”
8.3.1
MII Management DC Electrical Characteristics
The MDC and MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics
for MDIO and MDC are provided in Table 36.
Table 36. MII Management DC Electrical Characteristics when powered at 3.3V
Parameter
Symbol
OV
Conditions
Min
Max
Unit
Supply voltage (3.3 V)
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Input current
—
2.97
2.10
GND
2.00
—
3.63
V
V
DD
V
I
= -1.0 mA
= 1.0 mA
OV = Min
OV + 0.3
OH
OH
DD
DD
V
I
OV = Min
0.50
—
V
OL
OL
DD
V
—
—
V
IH
V
I
0.80
10
V
IL
0 V ≤ V ≤ OV
DD
—
μA
IN
IN
8.3.2
MII Management AC Electrical Specifications
Table 37 provides the MII management AC timing specifications.
Table 37. MII Management AC Timing Specifications
At recommended operating conditions with LVDD is 3.3 V 10%
1
Parameter/Condition
MDC frequency
Symbol
Min
Typ
Max
Unit
Notes
f
t
—
—
32
2.5
400
—
—
—
—
MHz
ns
2
MDC
MDC period
MDC
MDC clock pulse width high
MDC to MDIO delay
t
ns
MDCH
t
t
10
—
—
—
110
ns
3
MDTKHDX
MDTKHDV
MDRDVKH
MDRDXKH
MDIO to MDC setup time
MDIO to MDC hold time
MDC rise time
t
t
10
0
—
—
—
—
—
10
ns
ns
ns
t
—
MDCR
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
38 Freescale Semiconductor
UCC Ethernet Controller: Three-Speed Ethernet, MII Management
Table 37. MII Management AC Timing Specifications (continued)
At recommended operating conditions with LVDD is 3.3 V 10%
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Notes
MDC fall time
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
t
—
—
10
ns
MDHF
(first two letters of functional block)(signal)(state)
for inputs and t
for outputs. For example,
(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
t
symbolizes management data timing (MD) for the time t
from clock reference (K) high (H) until data
MDKHDX
MDC
outputs (D) are invalid (X) or data hold time. Also, t
symbolizes management data timing (MD) with respect
MDRDVKH
to the time data input signals (D) reach the valid state (V) relative to the t
clock reference (K) going to the high
MDC
(H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F
(fall).
2. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the maximum frequency is
8.3 MHz and the minimum frequency is 1.2 MHz; for a csb_clk of 375 MHz, the maximum frequency is 11.7 MHz
and the minimum frequency is 1.7 MHz).
3. This parameter is dependent on the ce_clk speed (that is, for a ce_clk of 200 MHz, the delay is 90 ns and for a ce_clk
of 300 MHz, the delay is 63 ns).
Figure 20 shows the MII management AC timing diagram.
t
t
MDCR
MDC
MDC
t
t
MDHF
MDCH
MDIO
(Input)
t
MDRDVKH
t
MDRDXKH
MDIO
(Output)
t
MDTKHDX
Figure 20. MII Management Interface Timing Diagram
8.3.3
IEEE Std. 1588™ Timer AC Specifications
Table 38 provides the IEEE Std. 1588 timer AC specifications.
Table 38. 1588 Timer AC Specifications
Parameter
Symbol
Min
Max
Unit
Notes
Timer clock cycle time
t
0
—
—
0
70
—
—
6
MHz
—
1
TMRCK
Input Setup to timer clock
Input Hold from timer clock
Output clock to output valid
t
2,3
2,3
TMRCKS
TMRCKH
t
—
t
ns
GCLKNV
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 39
Local Bus
Table 38. 1588 Timer AC Specifications (continued)
Parameter
Symbol
Min
Max
Unit
Notes
Timer alarm to output valid
t
—
—
—
2
TMRAL
Notes:
1. The timer can operate on rtc_clock or tmr_clock. These clocks get muxed and any one of them can be selected. Min and
Max requirement for both rtc_clock and tmr_clock are the same.
2. These are asynchronous signals.
3. Inputs need to be stable at least one TMR clock.
9 Local Bus
This section describes the DC and AC electrical specifications for the local bus interface of the
MPC8360E/58E.
9.1
Local Bus DC Electrical Characteristics
Table 39 provides the DC electrical characteristics for the local bus interface.
Table 39. Local Bus DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
High-level input voltage
Low-level input voltage
High-level output voltage,
V
2
OV + 0.3
V
V
V
IH
DD
V
–0.3
0.8
—
IL
V
OV – 0.4
OH
DD
I
= –100 μA
OH
Low-level output voltage,
= 100 μA
V
—
—
0.2
10
V
OL
IN
I
OL
Input current
I
μA
9.2
Local Bus AC Electrical Specifications
Table 40 describes the general timing parameters of the local bus interface of the device.
Table 40. Local Bus General Timing Parameters—DLL Enabled
1
Parameter
Symbol
Min
Max
Unit
Notes
Local bus cycle time
t
7.5
1.7
1.9
1.0
1.0
1.5
3.0
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
2
LBK
Input setup to local bus clock (except LUPWAIT)
LUPWAIT input setup to local bus clock
t
t
t
t
3, 4
3, 4
3, 4
3, 4
5
LBIVKH1
LBIVKH2
LBIXKH1
LBIXKH2
Input hold from local bus clock (except LUPWAIT)
LUPWAIT Input hold from local bus clock
LALE output fall to LAD output transition (LATCH hold time)
LALE output fall to LAD output transition (LATCH hold time)
t
t
LBOTOT1
LBOTOT2
6
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
40 Freescale Semiconductor
Local Bus
Table 40. Local Bus General Timing Parameters—DLL Enabled (continued)
1
Parameter
Symbol
Min
Max
Unit
Notes
LALE output fall to LAD output transition (LATCH hold time)
Local bus clock to LALE rise
t
2.5
—
—
4.5
4.5
4.5
4.5
—
ns
ns
ns
ns
ns
ns
ns
ns
7
LBOTOT3
t
LBKHLR
LBKHOV1
LBKHOV2
LBKHOV3
LBKHOX1
LBKHOX2
Local bus clock to output valid (except LAD/LDP and LALE)
Local bus clock to data valid for LAD/LDP
Local bus clock to address valid for LAD
Output hold from local bus clock (except LAD/LDP and LALE)
Output hold from local bus clock for LAD/LDP
Local bus clock to output high impedance for LAD/LDP
Notes:
t
t
t
t
t
—
—
3
3
3
3
—
1.0
1.0
—
—
t
3.8
LBKHOZ
1. The symbols used for timing specifications herein follow the pattern of t
(First two letters of functional block)(signal)(state)
for inputs and t
for outputs. For example, t
(reference)(state)
(First two letters of functional block)(reference)(state)(signal)(state)
LBIXKH1
symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the t
clock reference (K) goes
clock reference (K) to go
LBK
LBK
high (H), in this case for clock one(1). Also, t
symbolizes local bus timing (LB) for the t
LBKHOX
high (H), with respect to the output (O) going invalid (X) or output hold time.
2. All timings are in reference to rising edge of LSYNC_IN.
3. All signals are measured from OV /2 of the rising edge of LSYNC_IN to 0.4 × OV of the signal in question for 3.3-V
DD
DD
signaling levels.
4. Input timings are measured at the pin.
5.t
6.t
7.t
should be used when RCWH[LALE] is not set and when the load on LALE output pin is at least 10pF less than
the load on LAD output pins.
LBOTOT1
should be used when RCWH[LALE] is set and when the load on LALE output pin is at least 10pF less than the
load on LAD output pins.
LBOTOT2
should be used when RCWH[LALE] is set and when the load on LALE output pin equals to the load on LAD output
LBOTOT3
pins.
8. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
Table 41 describes the general timing parameters of the local bus interface of the device.
Table 41. Local Bus General Timing Parameters—DLL Bypass Mode
1
Parameter
Symbol
Min
Max
Unit
Notes
Local bus cycle time
t
15
7
—
—
—
—
—
—
3
ns
ns
ns
ns
ns
ns
ns
2
3, 4
3, 4
5
LBK
Input setup to local bus clock
t
LBIVKH
LBIXKH
Input hold from local bus clock
t
1.0
1.5
3
LALE output fall to LAD output transition (LATCH hold time)
LALE output fall to LAD output transition (LATCH hold time)
LALE output fall to LAD output transition (LATCH hold time)
Local bus clock to output valid
t
LBOTOT1
t
6
LBOTOT2
t
2.5
—
7
LBOTOT3
t
3
LBKHOV
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 41
Local Bus
Table 41. Local Bus General Timing Parameters—DLL Bypass Mode (continued)
1
Parameter
Symbol
Min
Max
Unit
Notes
Local bus clock to output high impedance for LAD/LDP
Notes:
t
—
4
ns
LBKHOZ
1. The symbols used for timing specifications herein follow the pattern of t
(First two letters of functional block)(signal)(state)
for inputs and t
for outputs. For example, t
(reference)(state)
(First two letters of functional block)(reference)(state)(signal)(state)
LBIXKH1
symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the t
clock reference (K) goes
clock reference (K) to go
LBK
LBK
high (H), in this case for clock one(1). Also, t
symbolizes local bus timing (LB) for the t
LBKHOX
high (H), with respect to the output (O) going invalid (X) or output hold time.
2. All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or rising edge of
LCLK0 (for all other inputs).
3. All signals are measured from OV /2 of the rising/falling edge of LCLK0 to 0.4 × OV of the signal in question for 3.3-V
DD
DD
signaling levels.
4. Input timings are measured at the pin.
5.t
6.t
7.t
should be used when RCWH[LALE] is not set and when the load on LALE output pin is at least 10pF less than
the load on LAD output pins.
LBOTOT1
should be used when RCWH[LALE] is set and when the load on LALE output pin is at least 10pF less than the
load on LAD output pins.
LBOTOT2
should be used when RCWH[LALE] is set and when the load on LALE output pin equals to the load on LAD output
LBOTOT3
pins.
8. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
9. DLL bypass mode is not recommended for use at frequencies above 66MHz.
Figure 21 provides the AC test load for the local bus.
Output
OV /2
DD
Z = 50 Ω
0
R = 50 Ω
L
Figure 21. Local Bus C Test Load
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
42 Freescale Semiconductor
Local Bus
Figure 22 through Figure 27 show the local bus signals.
LSYNC_IN
t
t
LBIXKH
LBIXKH
t
LBIVKH
Input Signals:
LAD[0:31]/LDP[0:3]
t
t
t
t
t
LBKHOX
LBKHOV
LBKHOV
Output Signals:
LSDA10/LSDWE/LSDRAS/
LSDCAS/LSDDQM[0:3]
LA[27:31]/LBCTL/LBCKE/LOE/
t
LBKHOZ
LBKHOX
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
t
LBKHOZ
LBKHOX
t
LBKHOV
Output (Address) Signal:
LAD[0:31]
t
LBOTOT
t
LBKHLR
LALE
Figure 22. Local Bus Signals, Nonspecial Signals Only (DLL Enabled)
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 43
Local Bus
LCLK[n]
t
LBIXKH
t
LBIVKH
Input Signals:
LAD[0:31]/LDP[0:3]
t
LBIXKH
t
LBIVKH
Input Signal:
LGTA
t
LBIXKH
t
LBKHOV
Output Signals:
LSDA10/LSDWE/LSDRAS/
LSDCAS/LSDDQM[0:3]
LA[27:31]/LBCTL/LBCKE/LOE/
t
LBKHOZ
t
LBKHOV
Output Signals:
LAD[0:31]/LDP[0:3]
t
LBOTOT
LALE
Figure 23. Local Bus Signals, Nonspecial Signals Only (DLL Bypass Mode)
LSYNC_IN
T1
T3
t
LBKHOZ1
t
LBKHOV1
GPCM Mode Output Signals:
LCS[0:3]/LWE
t
t
LBIXKH2
t
t
LBIVKH2
UPM Mode Input Signal:
LUPWAIT
LBIXKH1
LBIVKH1
Input Signals:
LAD[0:31]/LDP[0:3]
t
LBKHOZ1
t
LBKHOV1
UPM Mode Output Signals:
LCS[0:3]/LBS[0:3]/LGPL[0:5]
Figure 24. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (DLL Enabled)
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
44
Freescale Semiconductor
Local Bus
LCLK
T1
T3
t
LBKHOZ
t
LBKHOV
GPCM Mode Output Signals:
LCS[0:3]/LWE
t
LBIXKH
t
LBIVKH
UPM Mode Input Signal:
LUPWAIT
t
LBIXKH
t
LBIVKH
Input Signals:
LAD[0:31]/LDP[0:3]
(DLL Bypass Mode)
t
LBKHOZ
t
LBKHOV
UPM Mode Output Signals:
LCS[0:3]/LBS[0:3]/LGPL[0:5]
Figure 25. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (DLL Bypass Mode)
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor
45
Local Bus
LCLK
T1
T2
T3
T4
t
LBKHOZ
t
LBKHOV
GPCM Mode Output Signals:
LCS[0:3]/LWE
t
LBIXKH
t
LBIVKH
UPM Mode Input Signal:
LUPWAIT
t
LBIXKH
t
LBIVKH
Input Signals:
LAD[0:31]/LDP[0:3]
(DLL Bypass Mode)
t
LBKHOZ
t
LBKHOV
UPM Mode Output Signals:
LCS[0:3]/LBS[0:3]/LGPL[0:5]
Figure 26. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (DLL Bypass Mode)
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
46
Freescale Semiconductor
JTAG
LSYNC_IN
T1
T2
T3
T4
t
LBKHOZ1
t
LBKHOV1
GPCM Mode Output Signals:
LCS[0:3]/LWE
t
t
LBIXKH2
t
t
LBIVKH2
UPM Mode Input Signal:
LUPWAIT
LBIXKH1
LBIVKH1
Input Signals:
LAD[0:31]/LDP[0:3]
t
LBKHOZ1
t
LBKHOV1
UPM Mode Output Signals:
LCS[0:3]/LBS[0:3]/LGPL[0:5]
Figure 27. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (DLL Enabled)
10 JTAG
This section describes the DC and AC electrical specifications for the IEEE Std. 1149.1 (JTAG) interface
of the MPC8360E/58E.
10.1 JTAG DC Electrical Characteristics
Table 42 provides the DC electrical characteristics for the IEEE Std. 1149.1 (JTAG) interface of the device.
Table 42. JTAG interface DC Electrical Characteristics
Characteristic
Output high voltage
Symbol
Condition
Min
Max
Unit
V
I
= -6.0 mA
= 6.0 mA
= 3.2 mA
—
2.4
—
—
V
V
OH
OH
Output low voltage
Output low voltage
Input high voltage
Input low voltage
Input current
V
I
0.5
0.4
OL
OL
V
I
—
V
OL
OL
V
2.5
–0.3
—
OV + 0.3
V
IH
DD
V
—
0.8
10
V
IL
I
0 V ≤ V ≤ OV
DD
μA
IN
IN
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 47
JTAG
This section describes the AC electrical specifications for the IEEE Std. 1149.1 (JTAG) interface of the
device.
Table 43 provides the JTAG AC timing specifications as defined in Figure 29 through Figure 32.
1
Table 43. JTAG AC Timing Specifications (Independent of CLKIN)
At recommended operating conditions (see Table 2).
2
Parameter
Symbol
Min
Max
Unit
Notes
JTAG external clock frequency of operation
JTAG external clock cycle time
JTAG external clock duty cycle
JTAG external clock rise and fall times
TRST assert time
f
0
33.3
—
MHz
ns
JTG
t
30
45
0
JTG
t
/t
55
2
%
JTKHKL JTG
t
& t
ns
JTGR
JTGF
t
25
—
ns
3
4
TRST
Input setup times:
ns
t
t
4
4
—
—
Boundary-scan data
JTDVKH
t
TMS, TDI
JTIVKH
Input hold times:
Valid times:
ns
ns
ns
ns
10
10
—
—
4
5
5
Boundary-scan data
TMS, TDI
JTDXKH
t
JTIXKH
t
t
2
2
11
11
Boundary-scan data
TDO
JTKLDV
JTKLOV
Output hold times:
t
t
2
2
—
—
Boundary-scan data
TDO
JTKLDX
JTKLOX
JTAG external clock to output high impedance:
Boundary-scan data
TDO
t
t
2
2
19
9
5, 6
6
JTKLDZ
JTKLOZ
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of t
to the midpoint of the signal
TCLK
in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load
(see Figure 21). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state)
for inputs and t
for outputs. For example,
(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
t
symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state
JTDVKH
(V) relative to the t
clock reference (K) going to the high (H) state or setup time. Also, t
symbolizes JTAG
JTG
JTDXKH
timing (JT) with respect to the time data input signals (D) went invalid (X) relative to the t
clock reference (K)
JTG
going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters
representing the clock of a particular functional. For rise and fall times, the latter convention is used with the
appropriate letter: R (rise) or F (fall).
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to t
.
TCLK
5. Non-JTAG signal output timing with respect to t
6. Guaranteed by design and characterization.
.
TCLK
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
48 Freescale Semiconductor
JTAG
Figure 28 provides the AC test load for TDO and the boundary-scan outputs of the device.
Z = 50 Ω
OV /2
Output
0
DD
R = 50 Ω
L
Figure 28. AC Test Load for the JTAG Interface
Figure 29 provides the JTAG clock input timing diagram.
JTAG
External Clock
VM
t
VM
VM
t
JTGR
JTKHKL
t
t
JTG
JTGF
VM = Midpoint Voltage (OV /2)
DD
Figure 29. JTAG Clock Input Timing Diagram
Figure 30 provides the TRST timing diagram.
TRST
VM
VM
t
TRST
VM = Midpoint Voltage (OV /2)
DD
Figure 30. TRST Timing Diagram
Figure 31 provides the boundary-scan timing diagram.
JTAG
VM
VM
External Clock
t
JTDVKH
t
JTDXKH
Boundary
Data Inputs
Input
Data Valid
t
JTKLDV
t
JTKLDX
Boundary
Data Outputs
Output Data Valid
t
JTKLDZ
Boundary
Data Outputs
Output Data Valid
VM = Midpoint Voltage (OV /2)
DD
Figure 31. Boundary-Scan Timing Diagram
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 49
I2C
Figure 32 provides the test access port timing diagram.
JTAG
VM
VM
External Clock
t
JTIVKH
t
JTIXKH
Input
TDI, TMS
TDO
Data Valid
t
JTKLOV
t
JTKLOX
Output Data Valid
t
JTKLOZ
TDO
Output Data Valid
VM = Midpoint Voltage (OV /2)
DD
Figure 32. Test Access Port Timing Diagram
11 I2C
2
This section describes the DC and AC electrical characteristics for the I C interface of the
MPC8360E/58E.
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
50
Freescale Semiconductor
I2C
2
11.1 I C DC Electrical Characteristics
2
Table 44 provides the DC electrical characteristics for the I C interface of the device.
2
Table 44. I C DC Electrical Characteristics
At recommended operating conditions with OVDD of 3.3 V 10%.
Parameter
Input high voltage level
Symbol
Min
Max
Unit
Notes
V
0.7 × OV
–0.3
0
OV + 0.3
V
V
IH
DD
DD
Input low voltage level
V
0.3 × OV
IL
DD
Low level output voltage
V
0.4
V
1
2
OL
I2KLKV
Output fall time from V (min) to V (max) with a
t
20 + 0.1 × C
B
250
ns
IH
IL
bus capacitance from 10 to 400 pF
Pulse width of spikes which must be suppressed
by the input filter
t
0
50
ns
3
4
I2KHKL
Capacitance for each I/O pin
Input current
C
I
—
—
10
10
pF
I
μA
IN
(0 V ≤V ≤ OV
)
DD
IN
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. C = capacitance of one bus line in pF.
B
3. Refer to the MPC8360E Integrated Communications Processor Reference Manual, Rev. 2 for information on the
digital filter used.
4. I/O pins will obstruct the SDA and SCL lines if OV is switched off.
DD
2
11.2 I C AC Electrical Specifications
2
Table 45 provides the AC timing parameters for the I C interface of the device.
2
Table 45. I C AC Electrical Specifications
All values refer to VIH (min) and VIL (max) levels (see Table 44).
1
Parameter
Symbol
Min
Max
Unit
SCL clock frequency
f
0
400
—
kHz
μs
I2C
Low period of the SCL clock
t
t
1.3
0.6
0.6
0.6
I2CL
High period of the SCL clock
—
μs
I2CH
Setup time for a repeated START condition
t
—
μs
I2SVKH
Hold time (repeated) START condition (after this period, the
first clock pulse is generated)
t
—
μs
I2SXKL
Data setup time
t
100
—
—
—
νσ
I2DVKH
Data hold time:
t
μs
I2DXKL
CBUS compatible masters
2
3
2
0
0.9
I C bus devices
4
Rise time of both SDA and SCL signals
t
20 + 0.1 C
300
ns
I2CR
b
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 51
I2C
2
Table 45. I C AC Electrical Specifications (continued)
All values refer to VIH (min) and VIL (max) levels (see Table 44).
1
Parameter
Symbol
Min
Max
Unit
4
Fall time of both SDA and SCL signals
Set-up time for STOP condition
t
20 + 0.1 C
0.6
300
—
ns
μs
μs
V
I2CF
b
t
I2PVKH
Bus free time between a STOP and START condition
t
1.3
—
I2KHDX
Noise margin at the LOW level for each connected device
(including hysteresis)
V
0.1 × OV
—
NL
DD
DD
Noise margin at the HIGH level for each connected device
(including hysteresis)
V
0.2 × OV
—
V
NH
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state)
for inputs and t
for outputs. For example, t
(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
I2DVKH
2
symbolizes I C timing (I2) with respect to the time data input signals (D) reach the valid state (V) relative to the t
clock reference (K) going to the high (H) state or setup time. Also, t
I2C
2
symbolizes I C timing (I2) for the time that
I2SXKL
the data with respect to the start condition (S) went invalid (X) relative to the t
clock reference (K) going to the low
I2C
2
(L) state or hold time. Also, t
symbolizes I C timing (I2) for the time that the data with respect to the stop
I2PVKH
condition (P) reaching the valid state (V) relative to the t
clock reference (K) going to the high (H) state or setup
I2C
time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. The device provides a hold time of at least 300 ns for the SDA signal (referred to the V
bridge the undefined region of the falling edge of SCL.
of the SCL signal) to
IHmin
3. The maximum t
has only to be met if the device does not stretch the LOW period (t
) of the SCL signal.
I2DVKH
I2CL
4. C = capacitance of one bus line in pF.
B
2
Figure 33 provides the AC test load for the I C.
Output
OV /2
DD
Z = 50 Ω
0
R = 50 Ω
L
2
Figure 33. I C AC Test Load
2
Figure 34 shows the AC timing diagram for the I C bus.
SDA
t
t
t
t
I2CF
I2CF
I2DVKH
I2KHKL
t
t
t
I2CR
I2CL
I2SXKL
SCL
t
t
t
t
I2PVKH
I2SXKL
I2CH
I2SVKH
t
I2DXKL
S
Sr
P
S
2
Figure 34. I C Bus AC Timing Diagram
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
52 Freescale Semiconductor
PCI
12 PCI
This section describes the DC and AC electrical specifications for the PCI bus of the MPC8360E/58E.
12.1 PCI DC Electrical Characteristics
Table 46 provides the DC electrical characteristics for the PCI interface of the device.
Table 46. PCI DC Electrical Characteristics
Parameter
Symbol
Test Condition
Min
Max
Unit
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
Input current
V
V
≥ V (min) or
0.5 × OV
-0.5
OV + 0.5
V
V
IH
OUT
OH
DD
DD
V
V
≤ V (max)
0.3 × OV
IL
OUT
OL
DD
V
I
= –500 μA
0.9 × OV
—
—
V
OH
OH
DD
V
I
= 1500 μA
0.1 × OV
V
OL
OL
DD
1
I
0 V ≤ V
≤ OV
DD
—
10
μA
IN
IN
Notes:
1. Note that the symbol V , in this case, represents the OV symbol referenced in Table 1 and Table 2.
IN
IN
12.2 PCI AC Electrical Specifications
This section describes the general AC timing parameters of the PCI bus of the device. Note that the
PCI_CLK or PCI_SYNC_IN signal is used as the PCI input clock depending on whether the device is
configured as a host or agent device. Table 47 provides the PCI AC timing specifications at 66 MHz.
.
Table 47. PCI AC Timing Specifications at 66 MHz
1
Parameter
Clock to output valid
Symbol
Min
Max
Unit
Notes
t
t
t
—
1
6.0
—
ns
ns
ns
ns
2, 5
2
PCKHOV
PCKHOX
PCKHOZ
Output hold from Clock
Clock to output high impedance
Input setup to Clock
—
3.0
14
—
2, 3
2, 4
t
PCIVKH
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 53
PCI
Table 47. PCI AC Timing Specifications at 66 MHz (continued)
1
Parameter
Symbol
Min
Max
Unit
Notes
Input hold from Clock
Notes:
1. Note that the symbols used for timing specifications herein follow the pattern of t
t
0.3
—
ns
2, 4, 6
PCIXKH
(first two letters of functional
for inputs and t
for outputs. For
block)(signal)(state) (reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
example, t
symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V)
PCIVKH
relative to the PCI_SYNC_IN clock, t
, reference (K) going to the high (H) state or setup time. Also, t
SYS
PCRHFV
symbolizes PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going
to the valid (V) state.
2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.
3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current
delivered through the component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
5. In rev 2.0 silicon, due to errata, t
6. In rev 2.0 silicon, due to errata, t
maximum is 6.6ns. Please refer to PCI21 in the device errata document.
minimum is 1 ns. Please refer to PCI17 in the device errata document.
PCIHOV
PCIXKH
Table 48. PCI AC Timing Specifications at 33 MHz
1
Parameter
Clock to output valid
Symbol
Min
Max
Unit
Notes
t
t
t
—
2
11
—
14
—
—
ns
ns
ns
ns
ns
2
2
PCKHOV
PCKHOX
PCKHOZ
Output hold from Clock
Clock to output high impedance
Input setup to Clock
Input hold from Clock
Notes:
—
2, 3
2, 4
2, 4, 5
t
7.0
0.3
PCIVKH
t
PCIXKH
1. Note that the symbols used for timing specifications herein follow the pattern of t
(first two letters of functional
for inputs and t
for outputs. For
block)(signal)(state) (reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
example, t
symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V)
PCIVKH
relative to the PCI_SYNC_IN clock, t
, reference (K) going to the high (H) state or setup time. Also, t
SYS
PCRHFV
symbolizes PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going
to the valid (V) state.
2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.
3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current
delivered through the component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
5. In rev 2.0 silicon, due to errata, t
minimum is 1 ns. Please refer to PCI17 in the device errata document.
PCIXKH
Figure 35 provides the AC test load for PCI.
OV /2
Output
Z = 50 Ω
DD
0
R = 50 Ω
L
Figure 35. PCI AC Test Load
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
54 Freescale Semiconductor
Timers
Figure 36 shows the PCI input AC timing conditions.
CLK
t
PCIVKH
t
PCIXKH
Input
Figure 36. PCI Input AC Timing Measurement Conditions
Figure 37 shows the PCI output AC timing conditions.
CLK
t
PCKHOV
t
PCKHOX
Output Delay
t
PCKHOZ
High-Impedance
Output
Figure 37. PCI Output AC Timing Measurement Condition
13 Timers
This section describes the DC and AC electrical specifications for the timers of the MPC8360E/58E.
13.1 Timers DC Electrical Characteristics
Table 49 provides the DC electrical characteristics for the device timer pins, including TIN, TOUT,
TGATE and RTC_CLK.
Table 49. Timers DC Electrical Characteristics
Characteristic
Output high voltage
Symbol
Condition
= –6.0 mA
OH
Min
Max
Unit
V
I
2.4
—
—
V
V
OH
Output low voltage
Output low voltage
Input high voltage
Input low voltage
Input current
V
I
= 6.0 mA
= 3.2 mA
—
0.5
0.4
OL
OL
V
I
—
V
OL
OL
V
2.0
–0.3
—
OV + 0.3
V
IH
DD
V
—
0.8
10
V
IL
I
0 V ≤ V ≤ OV
DD
μA
IN
IN
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 55
GPIO
13.2 Timers AC Timing Specifications
Table 50 provides the timer input and output AC timing specifications.
1
Table 50. Timers Input AC Timing Specifications
2
Characteristic
Symbol
Typ
Unit
Timers inputs—minimum pulse width
Notes:
t
20
ns
TIWID
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN.
Timings are measured at the pin.
2. Timers inputs and outputs are asynchronous to any visible clock. Timers outputs should be synchronized before use
by any external synchronous logic. Timers inputs are required to be valid for at least t
operation.
ns to ensure proper
TIWID
Figure 38 provides the AC test load for the timers.
OV /2
Output
Z = 50 Ω
DD
0
R = 50 Ω
L
Figure 38. Timers AC Test Load
14 GPIO
This section describes the DC and AC electrical specifications for the GPIO of the MPC8360E/58E.
14.1 GPIO DC Electrical Characteristics
Table 51 provides the DC electrical characteristics for the device GPIO.
Table 51. GPIO DC Electrical Characteristics
Characteristic
Output high voltage
Symbol
Condition
= –6.0 mA
OH
Min
Max
Unit
Notes
V
I
2.4
—
—
V
V
1
1
1
1
OH
Output low voltage
Output low voltage
Input high voltage
Input low voltage
Input current
V
I
= 6.0 mA
= 3.2 mA
—
0.5
0.4
OL
OL
V
I
—
V
OL
OL
V
2.0
–0.3
—
OV + 0.3
V
IH
DD
V
—
0.8
10
V
IL
I
0 V ≤ V ≤ OV
DD
μA
IN
IN
Note: This specification applies when operating from 3.3V supply.
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
56 Freescale Semiconductor
IPIC
14.2 GPIO AC Timing Specifications
Table 52 provides the GPIO input and output AC timing specifications.
1
Table 52. GPIO Input AC Timing Specifications
2
Characteristic
Symbol
Typ
Unit
GPIO inputs—minimum pulse width
Notes:
t
20
ns
PIWID
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN.
Timings are measured at the pin.
2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use
by any external synchronous logic. GPIO inputs are required to be valid for at least t
operation.
ns to ensure proper
PIWID
Figure 39 provides the AC test load for the GPIO.
OV /2
Output
Z = 50 Ω
DD
0
R = 50 Ω
L
Figure 39. GPIO AC Test Load
15 IPIC
This section describes the DC and AC electrical specifications for the external interrupt pins of the
MPC8360E/58E.
15.1 IPIC DC Electrical Characteristics
Table 53 provides the DC electrical characteristics for the external interrupt pins of the IPIC.
Table 53. IPIC DC Electrical Characteristics
Characteristic
Input high voltage
Symbol
Condition
Min
Max
Unit
V
2.0
OV + 0.3
V
V
IH
DD
Input low voltage
Input current
V
I
–0.3
0.8
10
IL
μA
V
IN
Output low voltage
Output low voltage
Notes:
V
I
= 6.0 mA
= 3.2 mA
OL
—
—
0.5
0.4
OL
OL
V
I
V
OL
1. This table applies for pins IRQ[0:7], IRQ_OUT, MCP_OUT, and CE ports Interrupts.
2. IRQ_OUT and MCP_OUT are open drain pins, thus V is not relevant for those pins.
OH
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 57
SPI
15.2 IPIC AC Timing Specifications
Table 54 provides the IPIC input and output AC timing specifications.
1
Table 54. IPIC Input AC Timing Specifications
2
Characteristic
Symbol
Min
Unit
IPIC inputs—minimum pulse width
Notes:
t
20
ns
PIWID
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN.
Timings are measured at the pin.
2.IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by
any external synchronous logic. IPIC inputs are required to be valid for at least t
when working in edge triggered mode.
ns to ensure proper operation
PIWID
16 SPI
This section describes the DC and AC electrical specifications for the SPI of the MPC8360E/58E.
16.1 SPI DC Electrical Characteristics
Table 55 provides the DC electrical characteristics for the device SPI.
Table 55. SPI DC Electrical Characteristics
Characteristic
Output high voltage
Symbol
Condition
= –6.0 mA
OH
Min
Max
Unit
V
I
2.4
—
—
V
V
OH
Output low voltage
Output low voltage
Input high voltage
Input low voltage
Input current
V
I
= 6.0 mA
= 3.2 mA
—
0.5
0.4
OL
OL
V
I
—
V
OL
OL
V
2.0
–0.3
—
OV + 0.3
V
IH
DD
V
—
0.8
10
V
IL
I
0 V ≤ V ≤ OV
DD
μA
IN
IN
16.2 SPI AC Timing Specifications
Table 56 and provide the SPI input and output AC timing specifications.
1
Table 56. SPI AC Timing Specifications
2
Characteristic
Symbol
Min
Max
Unit
SPI outputs—Master mode (internal clock) delay
t
t
0.3
—
—
8
ns
NIKHOX
NIKHOV
SPI outputs—Slave mode (external clock) delay
t
t
2
—
—
8
ns
NEKHOX
NEKHOV
SPI inputs—Master mode (internal clock) input setup time
SPI inputs—Master mode (internal clock) input hold time
t
8
0
—
—
ns
ns
NIIVKH
t
NIIXKH
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
58 Freescale Semiconductor
SPI
1
Table 56. SPI AC Timing Specifications
2
Characteristic
Symbol
Min
Max
Unit
SPI inputs—Slave mode (external clock) input setup time
SPI inputs—Slave mode (external clock) input hold time
Notes:
t
t
4
2
—
—
ns
ns
NEIVKH
NEIXKH
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.
Timings are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t
(first two letters of functional block)(signal)(state)
for inputs and t
for outputs. For example,
(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
t
symbolizes the NMSI outputs internal timing (NI) for the time t
memory clock reference (K) goes from the
NIKHOV
SPI
high state (H) until outputs (O) are valid (V).
Figure 40 provides the AC test load for the SPI.
Output
OV /2
Z = 50 Ω
DD
0
R = 50 Ω
L
Figure 40. SPI AC Test Load
Figure 41 through Figure 42 represent the AC timing from Table 56. Note that although the specifications
generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge
is the active edge.
Figure 41 shows the SPI timing in slave mode (external clock).
SPICLK (input)
t
NEIXKH
t
NEIVKH
Input Signals:
SPIMOSI
(See Note)
t
NEKHOV
Output Signals:
SPIMISO
(See Note)
Note: The clock edge is selectable on SPI.
Figure 41. SPI AC Timing in Slave mode (External Clock) Diagram
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor
59
TDM/SI
Figure 42 shows the SPI timing in Master mode (internal clock).
SPICLK (output)
t
NIIXKH
t
NIIVKH
Input Signals:
SPIMISO
(See Note)
t
NIKHOV
Output Signals:
SPIMOSI
(See Note)
Note: The clock edge is selectable on SPI.
Figure 42. SPI AC Timing in Master mode (Internal Clock) Diagram
17 TDM/SI
This section describes the DC and AC electrical specifications for the time-division-multiplexed and serial
interface of the MPC8360E/58E.
17.1 TDM/SI DC Electrical Characteristics
Table 57 provides the DC electrical characteristics for the device TDM/SI.
Table 57. TDM/SI DC Electrical Characteristics
Characteristic
Output high voltage
Symbol
Condition
= –2.0 mA
OH
Min
Max
Unit
V
I
2.4
—
—
V
V
OH
Output low voltage
Input high voltage
Input low voltage
Input current
V
I
= 3.2 mA
OL
0.5
OL
V
—
—
2.0
–0.3
—
OV + 0.3
V
IH
DD
V
I
0.8
10
V
IL
0 V ≤ V ≤ OV
DD
μA
IN
IN
17.2 TDM/SI AC Timing Specifications
Table 58 provides the TDM/SI input and output AC timing specifications.
1
Table 58. TDM/SI AC Timing Specifications
2
3
Characteristic
Symbol
Min
Max
Unit
TDM/SI outputs—External clock delay
t
t
2
2
5
10
10
—
ns
ns
ns
SEKHOV
SEKHOX
TDM/SI outputs—External clock high impedance
TDM/SI inputs—External clock input setup time
t
SEIVKH
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60 Freescale Semiconductor
TDM/SI
1
Table 58. TDM/SI AC Timing Specifications (continued)
2
3
Characteristic
Symbol
Min
Max
Unit
TDM/SI inputs—External clock input hold time
t
2
—
ns
SEIXKH
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.
Timings are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t
(first two letters of functional block)(signal)(state)
for inputs and t
for outputs. For example,
(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
t
symbolizes the TDM/SI outputs external timing (SE) for the time t
memory clock reference (K) goes
SEKHOX
TDM/SI
from the high state (H) until outputs (O) are invalid (X).
3. Timings are measured from the positive or negative edge of the clock, according to SIxMR [CE] and
SITXCEI[TXCEIx]. See the MPC8360E Integrated Communications Processor Reference Manual, Rev. 2 for more
details.
Figure 43 provides the AC test load for the TDM/SI.
OV /2
Output
Z = 50 Ω
DD
0
R = 50 Ω
L
Figure 43. TDM/SI AC Test Load
Figure 44 represents the AC timing from Table 56. Note that although the specifications generally
reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the
active edge.
Figure 44 shows the TDM/SI timing with external clock.
TDM/SICLK (input)
t
SEIXKH
t
SEIVKH
Input Signals:
TDM/SI
(See Note)
t
SEKHOV
Output Signals:
TDM/SI
(See Note)
tSEKHOX
Note: The clock edge is selectable on TDM/SI
Figure 44. TDM/SI AC Timing (External Clock) Diagram
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 61
UTOPIA/POS
18 UTOPIA/POS
This section describes the DC and AC electrical specifications for the UTOPIA/POS of the
MPC8360E/58E.
18.1 UTOPIA/POS DC Electrical Characteristics
Table 59 provides the DC electrical characteristics for the device UTOPIA.
Table 59. UTOPIA DC Electrical Characteristics
Characteristic
Output high voltage
Symbol
Condition
= –8.0 mA
OH
Min
Max
Unit
V
I
2.4
—
—
V
V
OH
Output low voltage
Input high voltage
Input low voltage
Input current
V
I
= 8.0 mA
0.5
OL
OL
V
—
—
2.0
–0.3
—
OV + 0.3
V
IH
DD
V
I
0.8
10
V
IL
0 V ≤ V ≤ OV
DD
μA
IN
IN
18.2 Utopia/POS AC Timing Specifications
Table 60 provides the UTOPIA input and output AC timing specifications.
1
Table 60. UTOPIA AC Timing Specifications
2
Characteristic
Symbol
Min
Max
Unit
Notes
UTOPIA outputs—Internal clock delay
UTOPIA outputs—External clock delay
UTOPIA outputs—Internal clock High Impedance
UTOPIA outputs—External clock High Impedance
UTOPIA inputs—Internal clock input setup time
UTOPIA inputs—External clock input setup time
UTOPIA inputs—Internal clock input Hold time
UTOPIA inputs—External clock input hold time
Notes:
t
0
1
11.5
11.6
8.0
10.0
—
ns
ns
ns
ns
ns
ns
ns
ns
UIKHOV
t
UEKHOV
t
0
UIKHOX
t
1
UEKHOX
t
6
UIIVKH
t
4
—
3
3
UEIVKH
t
2.4
1
—
UIIXKH
t
—
UEIXKH
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state) (reference)(state)
inputs and t
for outputs. For example, t
symbolizes the UTOPIA
(first two letters of functional block)(reference)(state)(signal)(state)
UIKHOX
outputs internal timing (UI) for the time t
invalid (X).
memory clock reference (K) goes from the high state (H) until outputs (O) are
UTOPIA
3. In rev 2.0 silicon, due to errata, t
minimum is 4.3 ns and t
minimum is 1.4 ns under specific conditions. Please
UEIVKH
UEIXKH
refer to QE_UPC3 in the device errata document.
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62 Freescale Semiconductor
HDLC, BISYNC, Transparent, and Synchronous UART
Figure 45 provides the AC test load for the UTOPIA.
Output
OV /2
Z = 50 Ω
DD
0
R = 50 Ω
L
Figure 45. UTOPIA AC Test Load
Figure 46 and Figure 47 represent the AC timing from Table 56. Note that although the specifications
generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge
is the active edge.
Figure 46 shows the UTOPIA timing with external clock.
UtopiaCLK (input)
t
UEIXKH
t
UEIVKH
Input Signals:
UTOPIA
t
UEKHOV
Output Signals:
UTOPIA
tUEKHOX
Figure 46. UTOPIA AC Timing (External Clock) Diagram
Figure 47 shows the UTOPIA timing with internal clock.
UtopiaCLK (output)
t
UIIXKH
t
UIIVKH
Input Signals:
UTOPIA
t
UIKHOV
Output Signals:
UTOPIA
t
UIKHOX
Figure 47. UTOPIA AC Timing (Internal Clock) Diagram
19 HDLC, BISYNC, Transparent, and Synchronous UART
This section describes the DC and AC electrical specifications for the high level data link control (HDLC),
BiSync, transparent, and synchronous UART protocols of the MPC8360E/58E.
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63
HDLC, BISYNC, Transparent, and Synchronous UART
19.1 HDLC, BISYNC, Transparent, and Synchronous UART DC
Electrical Characteristics
Table 61 provides the DC electrical characteristics for the device HDLC, BISYNC, transparent, and
synchronous UART protocols.
Table 61. HDLC, BISYNC, Transparent, and Synchronous UART DC Electrical Characteristics
Characteristic
Output high voltage
Symbol
Condition
= –2.0 mA
OH
Min
Max
Unit
V
I
2.4
—
—
V
V
OH
Output low voltage
Input high voltage
Input low voltage
Input current
V
I
= 3.2 mA
0.5
OL
OL
V
—
—
2.0
–0.3
—
OV + 0.3
V
IH
DD
V
I
0.8
10
V
IL
0 V ≤ V ≤ OV
DD
μA
IN
IN
19.2 HDLC, BISYNC, Transparent, and Synchronous UART AC Timing
Specifications
Table 62 and Table 63 provide the input and output AC timing specifications for HDLC, BiSync,
transparent, and synchronous UART protocols.
1
Table 62. HDLC, BISYNC, and Transparent AC Timing Specifications
2
Characteristic
Outputs—Internal clock delay
Symbol
Min
Max
Unit
t
0
1
11.2
10.8
5.5
8
ns
ns
ns
ns
ns
ns
ns
ns
HIKHOV
Outputs—External clock delay
t
HEKHOV
Outputs—Internal clock High Impedance
Outputs—External clock High Impedance
Inputs—Internal clock input setup time
Inputs—External clock input setup time
Inputs—Internal clock input Hold time
Inputs—External clock input hold time
Notes:
t
-0.5
1
HIKHOX
t
HEKHOX
t
8.5
4
—
HIIVKH
t
—
HEIVKH
t
1.4
1
—
HIIXKH
t
—
HEIXKH
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.
Timings are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t
(first two letters of functional block)(signal)(state)
for inputs and t
for outputs. For example,
(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
t
symbolizes the outputs internal timing (HI) for the time t
memory clock reference (K) goes from the high
HIKHOX
serial
state (H) until outputs (O) are invalid (X).
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64 Freescale Semiconductor
HDLC, BISYNC, Transparent, and Synchronous UART
1
Table 63. Synchronous UART AC Timing Specifications
2
Characteristic
Outputs—Internal clock delay
Symbol
Min
Max
Unit
t
0
1
0
1
6
8
1
1
11.3
14
11
14
—
ns
ns
ns
ns
ns
ns
ns
ns
UAIKHOV
Outputs—External clock delay
t
UAEKHOV
Outputs—Internal clock High Impedance
Outputs—External clock High Impedance
Inputs—Internal clock input setup time
Inputs—External clock input setup time
Inputs—Internal clock input Hold time
Inputs—External clock input hold time
Notes:
t
UAIKHOX
UAEKHOX
t
t
UAIIVKH
t
—
UAEIVKH
t
—
UAIIXKH
t
—
UAEIXKH
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.
Timings are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t
(first two letters of functional block)(signal)(state)
for inputs and t
for outputs. For example,
(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
t
symbolizes the outputs internal timing (HI) for the time t
memory clock reference (K) goes from the high
HIKHOX
serial
state (H) until outputs (O) are invalid (X).
Figure 48 provides the AC test load.
Output
OV /2
Z = 50 Ω
DD
0
R = 50 Ω
L
Figure 48. AC Test Load
19.3 AC Test Load
Figure 49 and Figure 50 represent the AC timing from Table 62 and Table 63. Note that although the
specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when
the falling edge is the active edge.
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor
65
HDLC, BISYNC, Transparent, and Synchronous UART
Figure 49 shows the timing with external clock.
Serial CLK (input)
t
HEIXKH
t
HEIVKH
Input Signals:
(See Note)
t
HEKHOV
Output Signals:
(See Note)
tHEKHOX
Note: The clock edge is selectable.
Figure 49. AC Timing (External Clock) Diagram
Figure 50 shows the timing with internal clock.
Serial CLK (output)
t
HIIXKH
t
HIIVKH
Input Signals:
(See Note)
t
HIKHOV
Output Signals:
(See Note)
t
HIKHOX
Note: The clock edge is selectable.
Figure 50. AC Timing (Internal Clock) Diagram
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
66
Freescale Semiconductor
USB
20 USB
This section provides the AC and DC electrical specifications for the USB interface of the
MPC8360E/58E.
20.1 USB DC Electrical Characteristics
Table 64 provides the DC electrical characteristics for the USB interface.
Table 64. USB DC Electrical Characteristics
Parameter
High-level input voltage
Symbol
Min
Max
Unit
V
2
OV + 0.3
V
V
V
IH
DD
Low-level input voltage
V
–0.3
0.8
—
IL
High-level output voltage,
V
OV – 0.4
OH
DD
I
= –100 μA
OH
Low-level output voltage,
= 100 μA
V
I
—
—
0.2
10
V
OL
I
OL
Input current
μA
IN
Note:
1. Note that the symbol V , in this case, represents the OV symbol referenced in Table 1 and
IN
IN
Table 2.
20.2 USB AC Electrical Specifications
Table 65 describes the general timing parameters of the USB interface of the device.
Table 65. USB General Timing Parameters
1
Parameter
usb clock cycle time
Symbol
Min
Max
Unit
Notes
t
t
20.83
166.67
—
—
—
ns
ns
ns
ns
ns
full speed 48MHz
low speed 6MHz
USCK
USCK
usb clock cycle time
skew between TXP and TXN
skew among RXP, RXN and RXD
skew among RXP, RXN and RXD
Notes:
t
5
USTSPN
t
—
10
100
full speed transitions
low speed transitions
USRSPND
t
—
USRPND
1. The symbols used for timing specifications herein follow the pattern of t
(First two letters of functional block)(state)
for receive signals and t
for transmit signals. For example,
(signal)
(First two letters of functional block)(state)(signal)
t
symbolizes usb timing (US) for the usb receive signals skew (RS) among RXP, RXN, and RXD
USRSPND
(PND). Also, t
TXN (PN).
symbolizes usb timing (US) for the usb transmit signals skew (TS) between TXP and
USTSPN
2.Skew measurements are done at OV /2 of the rising or falling edge of the signals.
DD
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 67
Package and Pin Listings
Figure 51 provide the AC test load for the USB.
Output
OV /2
DD
Z = 50 Ω
0
R = 50 Ω
L
Figure 51. USB AC Test Load
21 Package and Pin Listings
This section details package parameters, pin assignments, and dimensions. The MPC8360E/58E is
available in a tape ball grid array (TBGA), see Section 21.1, “Package Parameters for the TBGA Package
and Section 21.2, “Mechanical Dimensions of the TBGA Package,” for information on the package.
21.1 Package Parameters for the TBGA Package
The package parameters for rev 2.0 silicon are as provided in the following list. The package type is 37.5
mm × 37.5 mm, 740 tape ball grid array (TBGA).
Package outline
Interconnects
Pitch
37.5 mm × 37.5 mm
740
1.00 mm
Module height (typical)
Solder Balls
1.46 mm
62 Sn/36 Pb/2 Ag (ZU package)
95.5 Sn/0.5 Cu/4Ag (VV package)
0.64 mm
Ball diameter (typical)
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
68 Freescale Semiconductor
Package and Pin Listings
21.2 Mechanical Dimensions of the TBGA Package
Figure 52 depicts the mechanical dimensions and bottom surface nomenclature of the device, 740-TBGA
package.
Figure 52. Mechanical Dimensions and Bottom Surface Nomenclature of the TBGA Package
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor
69
Package and Pin Listings
21.3 Pinout Listings
Table 66 shows the pin list of the MPC8360E TBGA package.
Table 66. MPC8360E TBGA Pinout Listing
Power
Supply
Signal
Package Pin Number
Pin Type
Notes
Primary DDR SDRAM Memory Controller Interface
MEMC1_MDQ[0:31]
AJ34, AK33, AL33, AL35, AJ33, AK34, AK32, AM36,
AN37, AN35, AR34, AT34, AP37, AP36, AR36, AT35,
AP34, AR32, AP32, AM31, AN33, AM34, AM33, AM30,
AP31, AM27, AR30, AT32, AN29, AP29, AN27, AR29
I/O
GV
DD
DD
MEMC1_MDQ[32:63]/
MEMC2_MDQ[0:31]
AN8, AN7, AM8, AM6, AP9, AN9, AT7, AP7, AU6, AP6,
AR4, AR3, AT6, AT5, AR5, AT3, AP4, AM5, AP3, AN3,
AN5, AL5, AN4, AM2, AL2, AH5, AK3, AJ2, AJ3, AH4,
AK4, AH3
I/O
GV
MEMC1_MECC[0:4]/
MSRCID[0:4]
AP24, AN22, AM19, AN19, AM24
I/O
I/O
GV
GV
DD
MEMC1_MECC[5]/
MDVAL
AM23
DD
MEMC1_MECC[6:7]
MEMC1_MDM[0:3]
AM22, AN18
I/O
O
GV
GV
GV
DD
DD
DD
AL36, AN34, AP33, AN28
AT9, AU4, AM3, AJ6
MEMC1_MDM[4:7]/
MEMC2_MDM[0:3]
O
MEMC1_MDM[8]
AP27
O
GV
GV
GV
DD
DD
DD
MEMC1_MDQS[0:3]
AK35, AP35, AN31, AM26
AT8, AU3, AL4, AJ5
I/O
I/O
MEMC1_MDQS[4:7]/
MEMC2_MDQS[0:3]
MEMC1_MDQS[8]
MEMC1_MBA[0:1]
MEMC1_MBA[2]
MEMC1_MA[0:14]
AP26
I/O
O
GV
GV
GV
GV
DD
DD
DD
DD
AU29, AU30
AT30
O
AU21, AP22, AP21, AT21, AU25, AU26, AT23, AR26,
AU24, AR23, AR28, AU23, AR22, AU20, AR18
O
MEMC1_MODT[0:1]
AG33, AJ36
AT1, AK2
O
O
GV
GV
6
6
DD
MEMC1_MODT[2:3]/
MEMC2_MODT[0:1]
DD
MEMC1_MWE
AT26
O
O
O
O
O
GV
GV
GV
GV
GV
DD
DD
DD
DD
DD
MEMC1_MRAS
MEMC1_MCAS
MEMC1_MCS[0:1]
AT29
AT24
AU27, AT27
AU8, AU7
MEMC1_MCS[2:3]/
MEMC2_MCS[0:1]
MEMC1_MCKE[0:1]
MEMC1_MCK[0:1]
AL32, AU33
AK37, AT37
AN1, AR2
O
O
O
GV
GV
GV
3
DD
DD
DD
MEMC1_MCK[2:3]/
MEMC2_MCK[0:1]
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
70 Freescale Semiconductor
Package and Pin Listings
Power
Table 66. MPC8360E TBGA Pinout Listing (continued)
Signal
MEMC1_MCK[4:5]/
Package Pin Number
Pin Type
Notes
Supply
AN25, AK1
O
GV
DD
MEMC2_MCKE[0:1]
MEMC1_MCK[0:1]
AL37, AT36
AP2, AT2
O
O
GV
GV
DD
MEMC1_MCK[2:3]/
MEMC2_MCK[0:1]
DD
MEMC1_MCK[4]/
MEMC2_MDM[8]
AN24
AL1
O
O
GV
GV
GV
DD
DD
DD
MEMC1_MCK[5]/
MEMC2_MDQS[8]
MDIC[0:1]
AH6, AP30
I/O
10
Secondary DDR SDRAM Memory Controller Interface
MEMC2_MECC[0:7]
MEMC2_MBA[0:2]
MEMC2_MA[0:14]
AN16, AP18, AM16, AM17, AN17, AP13, AP15, AN13
AU12, AU15, AU13
I/O
O
GV
GV
GV
DD
DD
DD
AT12, AP11, AT13, AT14, AR13, AR15, AR16, AT16,
AT18, AT17, AP10, AR20, AR17, AR14, AR11
O
MEMC2_MWE
MEMC2_MRAS
MEMC2_MCAS
AU10
AT11
AU11
O
O
O
GV
GV
GV
DD
DD
DD
PCI
PCI_INTA/
IRQ_OUT/
CE_PF[5]
A20
I/O
LV
2
2
DD
PCI_RESET_OUT/
CE_PF[6]
E19
I/O
I/O
I/O
I/O
I/O
LV
LV
2
2
DD
PCI_AD[31:30]/
CE_PG[31:30]
D20, D21
DD
PCI_AD[29:25]/
CE_PG[29:25]
A24, B23, C23, E23, A26
B21
OV
DD
PCI_AD[24]/
CE_PG[24]
LV
2
DD
PCI_AD[23:0]/
CE_PG[23:0]
C24, C25, D25, B25, E24, F24, A27, A28, F27, A30, C30,
D30, E29, B31, C31, D31, D32, A32, C33, B33, F30, E31,
A34, D33
OV
DD
PCI_C/
E22, B26, E28, F28
I/O
OV
DD
BE[3:0]/
CE_PF[10:7]
PCI_PAR/
CE_PF[11]
D28
D26
C27
I/O
I/O
I/O
OV
OV
OV
DD
DD
DD
PCI_FRAME/
CE_PF[12]
5
5
PCI_TRDY/
CE_PF[13]
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 71
Package and Pin Listings
Table 66. MPC8360E TBGA Pinout Listing (continued)
Power
Supply
Signal
Package Pin Number
Pin Type
Notes
PCI_IRDY/
CE_PF[14]
C28
I/O
OV
OV
OV
OV
OV
OV
5
DD
DD
DD
DD
DD
DD
PCI_STOP/
CE_PF[15]
B28
E26
F22
B29
A29
F19
A21
I/O
I/O
I/O
I/O
I/O
I/O
I/O
5
5
PCI_DEVSEL/
CE_PF[16]
PCI_IDSEL/
CE_PF[17]
PCI_SERR/
CE_PF[18]
5
5
PCI_PERR/
CE_PF[19]
PCI_REQ[0]/
CE_PF[20]
LV
LV
2
2
DD
DD
PCI_REQ[1]/
CPCI_HS_ES/
CE_PF[21]
PCI_REQ[2]/
CE_PF[22]
C21
E20
B20
I/O
I/O
I/O
LV
LV
LV
2
2
2
DD
DD
DD
PCI_GNT[0]/
CE_PF[23]
PCI_GNT[1]/
CPCI1_HS_LED/
CE_PF[24]
PCI_GNT[2]/
C20
I/O
LV
2
DD
CPCI1_HS_ENUM/
CE_PF[25]
PCI_MODE
D36
B37
I
OV
OV
DD
M66EN/
I/O
DD
CE_PF[4]
Local Bus Controller Interface
LAD[0:31]
N32, N33, N35, N36, P37, P32, P34, R36, R35, R34,
R33, T37, T35, T34, T33, U37, T32, U36, U34, V36, V35,
W37, W35, V33, V32, W34, Y36, W32, AA37, Y33, AA35,
AA34
I/O
OV
DD
LDP[0]/
CKSTOP_OUT
AB37
AB36
AB35
AA33
I/O
I/O
I/O
I/O
OV
OV
OV
OV
DD
DD
DD
DD
LDP[1]/
CKSTOP_IN
LDP[2]/
LCS[6]
LDP[3]/
LCS[7]
LA[27:31]
LCS[0:5]
AC37, AA32, AC36, AC34, AD36
O
O
OV
OV
DD
AD33, AG37, AF34, AE33, AD32, AH37
DD
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
72 Freescale Semiconductor
Package and Pin Listings
Power
Table 66. MPC8360E TBGA Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Notes
Supply
LWE[0:3]/
AG35, AG34, AH36, AE32
O
OV
DD
LSDDQM[0:3]/
LBS[0:3]
LBCTL
LALE
AD35
M37
O
O
OV
OV
OV
DD
DD
DD
LGPL0/
AB32
I/O
LSDA10/
cfg_reset_source0
LGPL1/
LSDWE/
cfg_reset_source1
AE37
AC33
AD34
AE35
I/O
O
OV
OV
OV
OV
DD
DD
DD
DD
LGPL2/
LSDRAS/
LOE
LGPL3/
LSDCAS/
cfg_reset_source2
I/O
I/O
LGPL4/
LGTA/
LUPWAIT/
LPBSE
LGPL5/
AF36
I/O
OV
DD
cfg_clkin_div
LCKE
G36
J33
J34
O
O
O
OV
OV
OV
DD
DD
DD
LCLK[0]
LCLK[1]/
LCS[6]
LCLK[2]/
LCS[7]
G37
O
OV
DD
LSYNC_OUT
LSYNC_IN
F34
G35
O
I
OV
OV
DD
DD
Programmable Interrupt Controller
MCP_OUT
E34
C37
O
I
OV
OV
2
DD
IRQ0/
DD
MCP_IN
IRQ[1]/
F35
F36
H34
I/O
I/O
I/O
OV
OV
OV
DD
DD
DD
M1SRCID[4]/
M2SRCID[4]/
LSRCID[4]
IRQ[2]/
M1DVAL/
M2DVAL/
LDVAL
IRQ[3]/
CORE_SRESET
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 73
Package and Pin Listings
Table 66. MPC8360E TBGA Pinout Listing (continued)
Package Pin Number
Power
Supply
Signal
Pin Type
Notes
IRQ[4:5]
G33, G32
E35
I/O
I/O
OV
OV
DD
IRQ[6]/
DD
LCS[6]/
CKSTOP_OUT
IRQ[7]/
H36
I/O
OV
DD
LCS[7]/
CKSTOP_IN
DUART
UART1_SOUT/
M1SRCID[0]/
M2SRCID[0]/
LSRCID[0]
E32
O
I/O
I/O
O
OV
OV
OV
OV
DD
DD
DD
DD
UART1_SIN/
M1SRCID[1]/
M2SRCID[1]/
LSRCID[1]
B34
C34
A35
UART1_CTS/
M1SRCID[2]/
M2SRCID[2]/
LSRCID[2]
UART1_RTS
M1SRCID[3]/
M2SRCID[3]/
LSRCID[3]
2
I C Interface
IIC1_SDA
IIC1_SCL
IIC2_SDA
IIC2_SCL
D34
B35
E33
C35
I/O
I/O
I/O
I/O
OV
OV
OV
OV
2
2
2
2
DD
DD
DD
DD
TM
QUICC Engine
CE_PA[0]
F8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
LV
DD0
CE_PA[1:2]
CE_PA[3:7]
CE_PA[8]
AH1, AG5
OV
DD
F6, D4, C3, E5, A3
AG3
LV
0
DD
OV
DD
CE_PA[9:12]
CE_PA[13:14]
CE_PA[15]
F7, B3, E6, B4
AG1, AF6
LV
0
DD
OV
DD
B2
LV
0
DD
CE_PA[16]
AF4
OV
DD
CE_PA[17:21]
CE_PA[22]
B16, A16, E17, A17, B17
AF3
LV
1
DD
OV
DD
CE_PA[23:26]
CE_PA[27:28]
C18, D18, E18, A18
AF2, AE6
LV
1
DD
OV
DD
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
74 Freescale Semiconductor
Package and Pin Listings
Power
Table 66. MPC8360E TBGA Pinout Listing (continued)
Package Pin Number
Signal
Pin Type
Notes
Supply
CE_PA[29]
CE_PA[30]
CE_PA[31]
CE_PB[0:27]
B19
AE5
F16
I/O
I/O
I/O
I/O
LV
1
DD
OV
DD
LV
1
DD
AE2, AE1, AD5, AD3, AD2, AC6, AC5, AC4, AC2, AC1,
AB5, AB4, AB3, AB1, AA6, AA4, AA2, Y6, Y4, Y3, Y2,
Y1, W6, W5, W2, V5, V3, V2
OV
DD
CE_PC[0:1]
CE_PC[2:3]
CE_PC[4:6]
CE_PC[7]
V1, U6
I/O
I/O
I/O
I/O
I/O
I/O
OV
DD
C16, A15
U4, U3, T6
C19
LV
1
DD
OV
DD
LV
LV
2
0
DD
DD
CE_PC[8:9]
CE_PC[10:30]
A4, C5
T5, T4, T2, T1, R5, R3, R1, C11, D12, F13, B10, C10,
E12, A9, B8, D10, A14, E15, B14, D15, AH2
OV
DD
CE_PD[0:27]
CE_PE[0:31]
CE_PF[0:3]
E11, D9, C8, F11, A7, E9, C7, A6, F10, B6, D7, E8, B5,
A5, C2, E4, F5, B1, D2, G5, D1, E2, H6, F3, E1, F2, G3,
H4
I/O
I/O
I/O
OV
DD
K3, J2, F1, G2, J5, H3, G1, H2, K6, J3, K5, K4, L6, P6,
P4, P3, P1, N4, N5, N2, N1, M2, M3, M5, M6, L1, L2, L4,
E14, C13, C14, B13
OV
OV
DD
F14, D13, A12, A11
DD
Clocks
PCI_CLK_OUT[0]/
CE_PF[26]
B22
I/O
I/O
LV
2
DD
PCI_CLK_OUT[1:2]/
CE_PF[27:28]
D22, A23
OV
DD
CLKIN
E37
M36
I
I
OV
OV
DD
PCI_CLOCK/
DD
PCI_SYNC_IN
PCI_SYNC_OUT/
CE_PF[29]
D37
I/O
OV
3
DD
JTAG
TCK
TDI
K33
K34
H37
J36
L32
I
I
OV
OV
OV
OV
OV
DD
DD
DD
DD
DD
4
3
4
4
TDO
TMS
TRST
O
I
I
Test
TEST
L35
I
I
OV
GV
7
7
DD
TEST_SEL
AU34
DD
PMC
QUIESCE
B36
O
OV
DD
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 75
Package and Pin Listings
Table 66. MPC8360E TBGA Pinout Listing (continued)
Power
Supply
Signal
Package Pin Number
System Control
Pin Type
Notes
PORESET
HRESET
SRESET
L37
L36
M33
I
OV
OV
OV
DD
DD
DD
I/O
I/O
1
2
Thermal Management
THERM0
THERM1
AP19
AT31
I
I
GV
GV
DD
DD
Power and Ground Signals
AV
AV
AV
AV
1
2
5
6
K35
Power for AV
LBIU DLL
(1.2 V)
1
DD
DD
DD
DD
DD
DD
DD
DD
K36
Power for AV
CE PLL
(1.2 V)
2
5
6
AM29
K37
Power for AV
e300 PLL
(1.2 V)
Power for AV
system
PLL (1.2
V)
GND
A2, A8, A13, A19, A22, A25, A31, A33, A36, B7, B12,
B24, B27, B30, C4, C6, C9, C15, C26, C32, D3, D8, D11,
D14, D17, D19, D23, D27, E7, E13, E25, E30, E36, F4,
F37, G34, H1, H5, H32, H33, J4, J32, J37, K1, L3, L5,
L33, L34, M1, M34, M35, N37, P2, P5, P35, P36, R4, T3,
U1, U5, U35, V37, W1, W4, W33, W36, Y34, AA3, AA5,
AC3, AC32, AC35, AD1, AD37, AE4, AE34, AE36, AF33,
AG4, AG6, AG32, AH35, AJ1, AJ4, AJ32, AJ35, AJ37,
AK36, AL3, AL34, AM4, AN6, AN23, AN30, AP8, AP12,
AP14, AP16, AP17, AP20, AP25, AR6, AR8, AR9, AR19,
AR24, AR31, AR35, AR37, AT4, AT10, AT19, AT20,
AT25, AU14, AU22, AU28, AU35
—
—
GV
AD4, AE3, AF1, AF5, AF35, AF37, AG2, AG36, AH33,
AH34, AK5, AM1, AM35, AM37, AN2, AN10, AN11,
AN12, AN14, AN32, AN36, AP5, AP23, AP28, AR1, AR7,
AR10, AR12, AR21, AR25, AR27, AR33, AT15, AT22,
AT28, AT33, AU2, AU5, AU16, AU31, AU36
Power for
DDR
DRAM
I/O
Voltage
(2.5 V or
1.8 V)
GV
DD
DD
LV
0
D5, D6
Power for LV
UCC1
0
DD
DD
Ethernet
Interface
(2.5V,
3.3V)
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
76 Freescale Semiconductor
Package and Pin Listings
Power
Table 66. MPC8360E TBGA Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Notes
Supply
LV
LV
1
2
C17, D16
Power for
UCC2
Ethernet
Interface
option 1
(2.5V,
LV
9
DD
DD1
3.3V)
B18, E21
Power for LV
UCC2
2
DD
9
DD
Ethernet
Interface
Option 2
(2.5V,
3.3V)
V
C36, D29, D35, E16, F9, F12, F15, F17, F18, F20, F21, Power for
V
DD
DD
F23, F25, F26, F29, F31, F32, F33, G6, J6, K32, M32,
N6, P33, R6, R32, U32, V6, Y5, Y32, AB6, AB33, AD6,
AF32, AK6, AL6, AM7, AM9, AM10, AM11, AM12, AM13,
AM14, AM15, AM18, AM21, AM25, AM28, AM32, AN15,
AN21, AN26, AU9, AU17
Core
(1.2 V)
OV
A10, B9, B15, B32, C1, C12, C22, C29, D24, E3, E10,
E27, G4, H35, J1, J35, K2, M4, N3, N34, R2, R37, T36,
PCI,
10/100
OV
DD
DD
U2, U33, V4, V34, W3, Y35, Y37, AA1, AA36, AB2, AB34 Ethernet,
and other
Standard
(3.3 V)
MVREF1
MVREF2
AN20
AU32
I
DDR
Referenc
e
Voltage
I
DDR
Referenc
e
Voltage
SPARE1
SPARE3
SPARE4
SPARE5
B11
I/O
—
—
—
OV
GV
GV
GV
DD
DD
DD
DD
AH32
AU18
AP1
8
7
8
No Connect
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 77
Package and Pin Listings
Table 66. MPC8360E TBGA Pinout Listing (continued)
Power
Supply
Signal
Package Pin Number
Pin Type
Notes
NC
AM20, AU19
—
—
—
Notes:
1. This pin is an open drain signal. A weak pull-up resistor (1 kΩ) should be placed on this pin to OV
DD
2. This pin is an open drain signal. A weak pull-up resistor (2–10 kΩ) should be placed on this pin to OV
3. This output is actively driven during reset rather than being three-stated during reset.
4. These JTAG pins have weak internal pull-up P-FETs that are always enabled.
.
DD
5.This pin should have a weak pull up if the chip is in PCI host mode. Follow PCI specifications recommendation.
6. These are On Die Termination pins, used to control DDR2 memories internal termination resistance
7. This pin must always be tied to GND.
8. This pin must always be left not connected.
9. Refers to MPC8360E PowerQUICC II™ Pro Integrated Communications Processor Reference Manual section on "RGMII
Pins" for information about the two UCC2 Ethernet interface options.
10. It is recommended that MDIC0 be tied to GND using an 18.2 Ω resistor and MDIC1 be tied to DDR power using an 18.2 Ω
resistor for DDR2.
Table 67 shows the pin list of the MPC8358E TBGA package.
Table 67. MPC8358E TBGA Pinout Listing
Power
Signal
Package Pin Number
Pin Type
Notes
Supply
DDR SDRAM Memory Controller Interface
MEMC1_MDQ[0:63]
AJ34, AK33, AL33, AL35, AJ33, AK34, AK32, AM36,
AN37, AN35, AR34, AT34, AP37, AP36, AR36, AT35,
AP34, AR32, AP32, AM31, AN33, AM34, AM33, AM30,
AP31, AM27, AR30, AT32, AN29, AP29, AN27, AR29,
AN8, AN7, AM8, AM6, AP9, AN9, AT7, AP7, AU6, AP6,
AR4, AR3, AT6, AT5, AR5, AT3, AP4, AM5, AP3, AN3,
AN5, AL5, AN4, AM2, AL2, AH5, AK3, AJ2, AJ3, AH4,
AK4, AH3
I/O
GV
DD
MEMC_MECC[0:4]/
MSRCID[0:4]
AP24, AN22, AM19, AN19, AM24
I/O
I/O
GV
GV
DD
MEMC_MECC[5]/
MDVAL
AM23
DD
MEMC_MECC[6:7]
MEMC_MDM[0:8]
MEMC_MDQS[0:8]
MEMC_MBA[0:1]
MEMC_MBA[2]
AM22, AN18
I/O
O
GV
GV
GV
GV
GV
GV
DD
DD
DD
DD
DD
DD
AL36, AN34, AP33, AN28,AT9, AU4, AM3, AJ6,AP27
AK35, AP35, AN31, AM26,AT8, AU3, AL4, AJ5, AP26
I/O
O
AU29, AU30
AT30
O
MEMC_MA[0:14]
AU21, AP22, AP21, AT21, AU25, AU26, AT23, AR26,
AU24, AR23, AR28, AU23, AR22, AU20, AR18
O
MEMC_MODT[0:3]
MEMC_MWE
AG33, AJ36, AT1, AK2
O
O
O
O
GV
GV
GV
GV
6
DD
DD
DD
DD
AT26
AT29
AT24
MEMC_MRAS
MEMC_MCAS
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
78 Freescale Semiconductor
Package and Pin Listings
Power
Table 67. MPC8358E TBGA Pinout Listing (continued)
Package Pin Number
Signal
MEMC_MCS[0:3]
Pin Type
Notes
Supply
AU27, AT27, AU8, AU7
AL32, AU33
O
O
GV
GV
GV
GV
GV
DD
DD
DD
DD
DD
MEMC_MCKE[0:1]
MEMC_MCK[0:5]
MEMC_MCK[0:5]
MDIC[0:1]
3
AK37, AT37, AN1, AR2, AN25, AK1
AL37, AT36, AP2, AT2, AN24, AL1
AH6, AP30
O
O
I/O
11
2
PCI
PCI_INTA/
IRQ_OUT/
CE_PF[5]
A20
I/O
LV
2
DD
PCI_RESET_OUT/
CE_PF[6]
E19
I/O
I/O
I/O
I/O
I/O
LV
LV
2
2
DD
PCI_AD[31:30]/
CE_PG[31:30]
D20, D21
DD
PCI_AD[29:25]/
CE_PG[29:25]
A24, B23, C23, E23, A26
B21
OV
DD
PCI_AD[24]/
CE_PG[24]
LV
2
DD
PCI_AD[23:0]/
CE_PG[23:0]
C24, C25, D25, B25, E24, F24, A27, A28, F27, A30, C30,
D30, E29, B31, C31, D31, D32, A32, C33, B33, F30, E31,
A34, D33
OV
DD
PCI_C/
E22, B26, E28, F28
I/O
OV
DD
BE[3:0]/
CE_PF[10:7]
PCI_PAR/
CE_PF[11]
D28
D26
C27
C28
B28
E26
F22
B29
A29
F19
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
OV
OV
OV
OV
OV
OV
OV
OV
OV
DD
DD
DD
DD
DD
DD
DD
DD
DD
PCI_FRAME/
CE_PF[12]
5
5
5
5
5
PCI_TRDY/
CE_PF[13]
PCI_IRDY/
CE_PF[14]
PCI_STOP/
CE_PF[15]
PCI_DEVSEL/
CE_PF[16]
PCI_IDSEL/
CE_PF[17]
PCI_SERR/
CE_PF[18]
5
5
PCI_PERR/
CE_PF[19]
PCI_REQ[0]/
CE_PF[20]
LV
2
DD
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 79
Package and Pin Listings
Table 67. MPC8358E TBGA Pinout Listing (continued)
Power
Supply
Signal
Package Pin Number
Pin Type
Notes
PCI_REQ[1]/
CPCI_HS_ES/
CE_PF[21]
A21
I/O
LV
2
DD
PCI_REQ[2]/
CE_PF[22]
C21
E20
B20
I/O
I/O
I/O
LV
LV
LV
2
2
2
DD
DD
DD
PCI_GNT[0]/
CE_PF[23]
PCI_GNT[1]/
CPCI1_HS_LED/
CE_PF[24]
PCI_GNT[2]/
C20
I/O
LV
2
DD
CPCI1_HS_ENUM/
CE_PF[25]
PCI_MODE
D36
B37
I
OV
OV
DD
M66EN/CE_PF[4]
I/O
DD
Local Bus Controller Interface
LAD[0:31]
N32, N33, N35, N36, P37, P32, P34, R36, R35, R34,
R33, T37, T35, T34, T33, U37, T32, U36, U34, V36, V35,
W37, W35, V33, V32, W34, Y36, W32, AA37, Y33, AA35,
AA34
I/O
OV
DD
LDP[0]/
CKSTOP_OUT
AB37
AB36
AB35
AA33
I/O
I/O
I/O
I/O
OV
OV
OV
OV
DD
DD
DD
DD
LDP[1]/
CKSTOP_IN
LDP[2]/
LCS[6]
LDP[3]/
LCS[7]
LA[27:31]
LCS[0:5]
AC37, AA32, AC36, AC34, AD36
AD33, AG37, AF34, AE33, AD32, AH37
AG35, AG34, AH36, AE32
O
O
O
OV
OV
OV
DD
DD
DD
LWE[0:3]/
LSDDQM[0:3]/
LBS[0:3]
LBCTL
LALE
AD35
M37
O
O
OV
OV
OV
DD
DD
DD
LGPL0/
AB32
I/O
LSDA10/
cfg_reset_source0
LGPL1/
LSDWE/
cfg_reset_source1
AE37
AC33
I/O
O
OV
OV
DD
LGPL2/
LSDRAS/
LOE
DD
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
80 Freescale Semiconductor
Package and Pin Listings
Power
Table 67. MPC8358E TBGA Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Notes
Supply
LGPL3/
LSDCAS/
cfg_reset_source2
AD34
I/O
I/O
OV
DD
LGPL4/
LGTA/
AE35
OV
DD
LUPWAIT/
LPBSE
LGPL5/
AF36
I/O
OV
DD
cfg_clkin_div
LCKE
G36
J33
J34
O
O
O
OV
OV
OV
DD
DD
DD
LCLK[0]
LCLK[1]/
LCS[6]
LCLK[2]/
LCS[7]
G37
O
OV
DD
LSYNC_OUT
LSYNC_IN
F34
G35
O
I
OV
OV
DD
DD
Programmable Interrupt Controller
MCP_OUT
E34
C37
O
I
OV
OV
2
DD
IRQ0/
DD
MCP_IN
IRQ[1]/
F35
F36
H34
I/O
I/O
I/O
OV
OV
OV
DD
DD
DD
M1SRCID[4]/
M2SRCID[4]/
LSRCID[4]
IRQ[2]/
M1DVAL/
M2DVAL/
LDVAL
IRQ[3]/
CORE_SRESET
IRQ[4:5]
G33, G32
E35
I/O
I/O
OV
OV
DD
IRQ[6]/
DD
LCS[6]/
CKSTOP_OUT
IRQ[7]/
LCS[7]/
CKSTOP_IN
H36
I/O
O
OV
DD
DD
DUART
UART1_SOUT/
M1SRCID[0]/
M2SRCID[0]/
LSRCID[0]
E32
OV
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 81
Package and Pin Listings
Table 67. MPC8358E TBGA Pinout Listing (continued)
Power
Supply
Signal
Package Pin Number
Pin Type
Notes
UART1_SIN/
M1SRCID[1]/
M2SRCID[1]/
LSRCID[1]
B34
I/O
OV
OV
OV
DD
DD
DD
UART1_CTS/
M1SRCID[2]/
M2SRCID[2]/
LSRCID[2]
C34
A35
I/O
O
UART1_RTS/
M1SRCID[3]/
M2SRCID[3]/
LSRCID[3]
2
I C Interface
IIC1_SDA
IIC1_SCL
IIC2_SDA
IIC2_SCL
D34
B35
E33
C35
I/O
I/O
I/O
I/O
OV
OV
OV
OV
2
2
2
2
DD
DD
DD
DD
TM
QUICC Engine
CE_PA[0]
F8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
LV
DD0
CE_PA[1:2]
CE_PA[3:7]
CE_PA[8]
AH1, AG5
OV
DD
F6, D4, C3, E5, A3
LV
0
DD
AG3
OV
DD
CE_PA[9:12]
CE_PA[13:14]
CE_PA[15]
CE_PA[16]
CE_PA[17:21]
CE_PA[22]
CE_PA[23:26]
CE_PA[27:28]
CE_PA[29]
CE_PA[30]
CE_PA[31]
CE_PB[0:27]
F7, B3, E6, B4
LV
0
DD
AG1, AF6
OV
DD
B2
LV
0
DD
AF4
OV
DD
B16, A16, E17, A17, B17
LV
1
DD
AF3
OV
DD
C18, D18, E18, A18
LV
1
DD
AF2, AE6
B19
OV
DD
LV
1
DD
AE5
OV
DD
F16
LV
1
DD
AE2, AE1, AD5, AD3, AD2, AC6, AC5, AC4, AC2, AC1,
AB5, AB4, AB3, AB1, AA6, AA4, AA2, Y6, Y4, Y3, Y2,
Y1, W6, W5, W2, V5, V3, V2
OV
DD
CE_PC[0:1]
CE_PC[2:3]
CE_PC[4:6]
CE_PC[7]
V1, U6
I/O
I/O
I/O
I/O
I/O
OV
DD
C16, A15
U4, U3, T6
C19
LV
1
DD
OV
DD
LV
LV
2
0
DD
DD
CE_PC[8:9]
A4, C5
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
82 Freescale Semiconductor
Package and Pin Listings
Power
Table 67. MPC8358E TBGA Pinout Listing (continued)
Package Pin Number
Signal
Pin Type
Notes
Supply
CE_PC[10:30]
CE_PD[0:27]
T5, T4, T2, T1, R5, R3, R1, C11, D12, F13, B10, C10,
E12, A9, B8, D10, A14, E15, B14, D15, AH2
I/O
I/O
OV
DD
E11, D9, C8, F11, A7, E9, C7, A6, F10, B6, D7, E8, B5,
OV
DD
A5, C2, E4, F5, B1, D2, G5, D1, E2, H6, F3, E1, F2, G3,
H4
CE_PE[0:31]
CE_PF[0:3]
K3, J2, F1, G2, J5, H3, G1, H2, K6, J3, K5, K4, L6, P6,
P4, P3, P1, N4, N5, N2, N1, M2, M3, M5, M6, L1, L2, L4,
E14, C13, C14, B13
I/O
I/O
OV
OV
DD
F14, D13, A12, A11
DD
Clocks
PCI_CLK_OUT[0]/
CE_PF[26]
B22
I/O
I/O
LV
2
DD
PCI_CLK_OUT[1:2]/
CE_PF[27:28]
D22, A23
OV
DD
CLKIN
E37
M36
I
I
OV
OV
DD
PCI_CLOCK/
DD
PCI_SYNC_IN
PCI_SYNC_OUT/
CE_PF[29]
D37
I/O
OV
3
DD
JTAG
TCK
TDI
K33
K34
H37
J36
L32
I
I
OV
OV
OV
OV
OV
DD
DD
DD
DD
DD
4
3
4
4
TDO
TMS
TRST
O
I
I
Test
TEST
L35
I
I
OV
GV
7
DD
TEST_SEL
AU34
10
DD
PMC
QUIESCE
B36
O
OV
DD
System Control
PORESET
HRESET
SRESET
L37
L36
M33
I
OV
OV
OV
DD
DD
DD
I/O
I/O
1
2
Thermal Management
THERM0
THERM1
AP19
AT31
I
I
GV
GV
DD
DD
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 83
Package and Pin Listings
Table 67. MPC8358E TBGA Pinout Listing (continued)
Package Pin Number
Power
Supply
Signal
Pin Type
Notes
Power and Ground Signals
AV
AV
AV
AV
1
2
5
6
K35
Power for AV
LBIU DLL
(1.2 V)
1
2
5
6
DD
DD
DD
DD
DD
DD
DD
DD
K36
Power for AV
CE PLL
(1.2 V)
AM29
K37
Power for AV
e300 PLL
(1.2 V)
Power for AV
system
PLL (1.2
V)
GND
A2, A8, A13, A19, A22, A25, A31, A33, A36, B7, B12,
B24, B27, B30, C4, C6, C9, C15, C26, C32, D3, D8, D11,
D14, D17, D19, D23, D27, E7, E13, E25, E30, E36, F4,
F37, G34, H1, H5, H32, H33, J4, J32, J37, K1, L3, L5,
L33, L34, M1, M34, M35, N37, P2, P5, P35, P36, R4, T3,
U1, U5, U35, V37, W1, W4, W33, W36, Y34, AA3, AA5,
AC3, AC32, AC35, AD1, AD37, AE4, AE34, AE36, AF33,
AG4, AG6, AG32, AH35, AJ1, AJ4, AJ32, AJ35, AJ37,
AK36, AL3, AL34, AM4, AN6, AN23, AN30, AP8, AP12,
AP14, AP16, AP17, AP20, AP25, AR6, AR8, AR9, AR19,
AR24, AR31, AR35, AR37, AT4, AT10, AT19, AT20,
AT25, AU14, AU22, AU28, AU35
—
—
GV
AD4, AE3, AF1, AF5, AF35, AF37, AG2, AG36, AH33,
AH34, AK5, AM1, AM35, AM37, AN2, AN10, AN11,
AN12, AN14, AN32, AN36, AP5, AP23, AP28, AR1, AR7,
AR10, AR12, AR21, AR25, AR27, AR33, AT15, AT22,
AT28, AT33, AU2, AU5, AU16, AU31, AU36
Power for
DDR
DRAM
I/O
Voltage
(2.5 V or
1.8 V)
GV
DD
DD
LV
LV
0
1
D5, D6
Power for LV
UCC1
Ethernet
Interface
(2.5V,
0
1
DD
DD
DD
3.3V)
C17, D16
Power for LV
UCC2
9
DD
Ethernet
Interface
option 1
(2.5V,
3.3V)
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
84 Freescale Semiconductor
Package and Pin Listings
Power
Table 67. MPC8358E TBGA Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Notes
Supply
LV
2
B18, E21
Power for LV
UCC2
2
DD
9
DD
Ethernet
Interface
Option 2
(2.5V,
3.3V)
V
C36, D29, D35, E16, F9, F12, F15, F17, F18, F20, F21, Power for
V
DD
DD
F23, F25, F26, F29, F31, F32, F33, G6, J6, K32, M32,
N6, P33, R6, R32, U32, V6, Y5, Y32, AB6, AB33, AD6,
AF32, AK6, AL6, AM7, AM9, AM10, AM11, AM12, AM13,
AM14, AM15, AM18, AM21, AM25, AM28, AM32, AN15,
AN21, AN26, AU9, AU17
Core
(1.2 V)
OV
A10, B9, B15, B32, C1, C12, C22, C29, D24, E3, E10,
E27, G4, H35, J1, J35, K2, M4, N3, N34, R2, R37, T36,
PCI,
10/100
OV
DD
DD
U2, U33, V4, V34, W3, Y35, Y37, AA1, AA36, AB2, AB34 Ethernet,
and other
Standard
(3.3 V)
MVREF1
MVREF2
AN20
AU32
I
DDR
Referenc
e
Voltage
I
DDR
Referenc
e
Voltage
SPARE1
SPARE3
SPARE4
SPARE5
B11
I/O
—
—
—
OV
GV
GV
GV
DD
DD
DD
DD
AH32
AU18
AP1
8
7
8
No Connect
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 85
Package and Pin Listings
Table 67. MPC8358E TBGA Pinout Listing (continued)
Package Pin Number
Power
Supply
Signal
Pin Type
Notes
NC
AM16, AM17, AM20, AN13, AN16, AN17, AP10, AP11,
AP13, AP15, AP18, AR11, AR13, AR14, AR15, AR16,
AR17, AR20, AT11, AT12, AT13, AT14, AT16, AT17,
AT18, AU10, AU11, AU12, AU13, AU15, AU19
—
—
—
Notes:
1. This pin is an open drain signal. A weak pull-up resistor (1 kΩ) should be placed on this pin to OV
DD.
2. This pin is an open drain signal. A weak pull-up resistor (2–10 kΩ) should be placed on this pin to OV
3. This output is actively driven during reset rather than being three-stated during reset.
4. These JTAG pins have weak internal pull-up P-FETs that are always enabled.
.
DD
5. This pin should have a weak pull up if the chip is in PCI host mode. Follow PCI specifications recommendation.
6. These are On Die Termination pins, used to control DDR2 memories internal termination resistance.
7. This pin must always be tied to GND.
8. This pin must always be left not connected.
9. Refers to MPC8360E PowerQUICC II™ Pro Integrated Communications Processor Reference Manual section on "RGMII
Pins" for information about the two UCC2 Ethernet interface options.
10. This pin must always be tied to GV
.
DD
11. It is recommended that MDIC0 be tied to GND using an 18.2 Ω resistor and MDIC1 be tied to DDR power using an 18.2 Ω
resistor for DDR2.
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
86
Freescale Semiconductor
Clocking
22 Clocking
Figure 53 shows the internal distribution of clocks within the MPC8360E.
MPC8360E
e300 core
core_clk
Core PLL
csb_clk
ce_clk to QUICC Engine block
DDRC1
DDRC1
Memory
Device
MEMC1_MCK[0:5]
MEMC1_MCK[0:5]
/2
ddr1_clk
lb_clk
DDRC2
Memory
Device
DDRC2
/2
MEMC2_MCK[0:1]
MEMC2_MCK[0:1]
QUICC
Clock
Engine
PLL
Unit
System
PLL
/n
LCLK[0:2]
to local bus/
Local Bus
Memory
Device
DDRC2
LBIU
DLL
LSYNC_OUT
LSYNC_IN
controller
csb_clk to rest
of the device
PCI_CLK/
PCI_SYNC_IN
CFG_CLKIN_DIV
CLKIN
PCI_SYNC_OUT
PCI Clock
Divider
PCI_CLK_OUT[0:2]
Figure 53. MPC8360E Clock Subsystem
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 87
Clocking
Figure 54 shows the internal distribution of clocks within the MPC8358E.
MPC8358E
e300 core
core_clk
Core PLL
csb_clk
ce_clk to QUICC Engine block
DDRC
/2
DDRC
Memory
Device
MEMC1_MCK[0:5]
MEMC1_MCK[0:5]
ddr1_clk
lb_clk
QUICC
Engine
PLL
Clock
Unit
System
PLL
/n
LCLK[0:2]
Local Bus
Memory
Device
LBIU
DLL
LSYNC_OUT
LSYNC_IN
csb_clk to rest
of the device
PCI_CLK/
PCI_SYNC_IN
CFG_CLKIN_DIV
CLKIN
PCI_SYNC_OUT
PCI Clock
Divider
PCI_CLK_OUT[0:2]
Figure 54. MPC8358E Clock Subsystem
The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on
whether the device is configured in PCI host or PCI agent mode. Note that in PCI host mode, the primary
clock input also depends on whether PCI clock outputs are selected with RCWH[PCICKEN]. When the
device is configured as a PCI host device (RCWH[PCIHOST] = 1) and PCI clock output is selected
(RCWH[PCICKEN] = 1), CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (÷2) and
the multiplexors for PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration input
selects whether CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The OCCR[PCICDn]
parameters select whether CLKIN or CLKIN/2 is driven out on the PCI_CLK_OUTn signals.The
OCCR[PCIOENn] parameters enable the PCI_CLK_OUTn respectively.
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
88
Freescale Semiconductor
Clocking
PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subystem to
synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN,
with equal delay to all PCI agent devices in the system, to allow the device to function. When the device
is configured as a PCI agent device, PCI_CLK is the primary input clock. When the device is configured
as a PCI agent device the CLKIN and the CFG_CLKIN_DIV signals should be tied to GND.
When the device is configured as a PCI host device (RCWH[PCIHOST] = 1) and PCI clock output is
disabled (RCWH[PCICKEN] = 0), clock distribution and balancing done externally on the board.
Therefore, PCI_SYNC_IN is the primary input clock.
As shown in Figure 53, the primary clock input (frequency) is multiplied by the QUICC Engine block
phase-locked loop (PLL), the system PLL, and the clock unit to create the QUICC Engine clock (ce_clk),
the coherent system bus clock (csb_clk), the internal DDRC1 controller clock (ddr1_clk), and the internal
clock for the local bus interface unit and DDR2 memory controller (lb_clk).
The csb_clk frequency is derived from a complex set of factors that can be simplified into the following
equation:
csb_clk = {PCI_SYNC_IN × (1 + CFG_CLKIN_DIV)} × SPMF
In PCI host mode, PCI_SYNC_IN × (1 + CFG_CLKIN_DIV) is the CLKIN frequency; in PCI agent
mode, CFG_CLKIN_DIV must be pulled down (low), so PCI_SYNC_IN × (1 + CFG_CLKIN_DIV) is
the PCI_CLK frequency.
The csb_clk serves as the clock input to the e300 core. A second PLL inside the e300 core multiplies up
the csb_clk frequency to create the internal clock for the e300 core (core_clk). The system and core PLL
multipliers are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL)
which is loaded at power-on reset or by one of the hard-coded reset options. See Chapter 4, “Reset,
Clocking, and Initialization,” in the MPC8360E Integrated Communications Processor Reference
Manual, Rev. 2 for more information on the clock subsystem.
The ce_clk frequency is determined by the QUICC Engine PLL multiplication factor (RCWL[CEPMF)
and the QUICC Engine PLL division factor (RCWL[CEPDF]) according to the following equation:
ce_clk = (primary clock input × CEPMF) ÷ (1 + CEPDF)
The internal ddr1_clk frequency is determined by the following equation:
ddr1_clk = csb_clk × (1 + RCWL[DDR1CM])
Note that the lb_clk clock frequency (for DDRC2) is determined by RCWL[LBCM]. The internal
ddr1_clk frequency is not the external memory bus frequency; ddr1_clk passes through the DDRC1 clock
divider (÷2) to create the differential DDRC1 memory bus clock outputs (MEMC1_MCK and
MEMC1_MCK). However, the data rate is the same frequency as ddr1_clk.
The internal lb_clk frequency is determined by the following equation:
lb_clk = csb_clk × (1 + RCWL[LBCM])
Note that lb_clk is not the external local bus or DDRC2 frequency; lb_clk passes through the a LB clock
divider to create the external local bus clock outputs (LSYNC_OUT and LCLK[0:2]). The LB clock
divider ratio is controlled by LCCR[CLKDIV].
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor
89
Clocking
In addition, some of the internal units may be required to be shut off or operate at lower frequency than
the csb_clk frequency. Those units have a default clock ratio that can be configured by a memory mapped
register after the device comes out of reset. Table 68 specifies which units have a configurable clock
frequency.
Table 68. Configurable Clock Units
Default
Frequency
Unit
Security Core
Options
csb_clk/3
Off, csb_clk 1, csb_clk/2,
csb_clk/3
PCI and DMA complex
csb_clk
Off, csb_clk
1
with limitation, only for slow csb_clk rates, up to 166MHz
Table 69 provides the operating frequencies for the TBGA package under recommended operating
conditions (see Table 2). All frequency combinations shown in the table below may not be available.
Maximum operating frequencies depend on the part ordered, see Section 26.1, “Part Numbers Fully
Addressed by this Document” for part ordering details and contact your Freescale Sales Representative or
authorized distributor for more information.
Table 69. Operating Frequencies for the TBGA Package
1
2
Characteristic
400 MHz
533 MHz
667 MHz
Unit
e300 core frequency (core_clk)
266–400
266–533
133–333
266–667
MHz
MHz
Coherent system bus frequency
(csb_clk)
3
QUICC Engine frequency
266–500
100–166.67
16.67–133
MHz
MHz
MHz
(ce_clk)
DDR and DDR2 memory bus frequency
4
(MCLK)
Local bus frequency
5
(LCLKn)
PCI input frequency (CLKIN or PCI_CLK)
25–66.67
133
MHz
MHz
Security core maximum internal operating frequency
133
166
1
The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting csb_clk, MCLK,
LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies.
2
3
4
5
The 667 MHz core frequency is based on a 1.3 V V supply voltage.
DD
The 500 MHz QE frequency is based on a 1.3 V V supply voltage.
DD
The DDR data rate is 2x the DDR memory bus frequency.
The local bus frequency is 1/2, 1/4, or 1/8 of the lb_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1x or 2x the
csb_clk frequency (depending on RCWL[LBCM]).
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
90
Freescale Semiconductor
Clocking
22.1 System PLL Configuration
The system PLL is controlled by the RCWL[SPMF] and RCWL[SVCOD] parameters. Table 70 shows the
multiplication factor encodings for the system PLL.
Table 70. System PLL Multiplication Factors
System PLL Multiplication
RCWL[SPMF]
Factor
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
× 16
Reserved
× 2
× 3
× 4
× 5
× 6
× 7
× 8
× 9
× 10
× 11
× 12
× 13
× 14
× 15
The RCWL[SVCOD] denotes the system PLL VCO internal frequency as shown in Table 71.
Table 71. System PLL VCO Divider
RCWL[SVCOD]
VCO Divider
00
01
10
11
4
8
2
Reserved
NOTE
The VCO divider must be set properly so that the system VCO frequency is
in the range of 600-1400 MHz.
The system VCO frequency is derived from the following equations:
csb_clk = {PCI_SYNC_IN × (1 + CFG_CLKIN_DIV)} × SPMF
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91
Clocking
System VCO Frequency = csb_clk × VCO divider
As described in Section 22, “Clocking,” the LBCM, DDRCM, and SPMF parameters in the reset
configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the
primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk). Table 72
shows the expected frequency values for the CSB frequency for select csb_clk to CLKIN/PCI_SYNC_IN
ratios.
Table 72. CSB Frequency Options
2
Input Clock Frequency (MHz)
csb_clk :
CFG_CLKIN_DIV
SPMF
Input Clock
16.67
25
33.33
66.67
1
at reset
2
Ratio
csb_clk Frequency (MHz)
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
2 : 1
3 : 1
133
200
266
333
100
4 : 1
100
125
150
175
200
225
250
275
300
325
133
166
200
233
266
300
333
5 : 1
6 : 1
100
7 : 1
116
133
150
166
183
200
216
8 : 1
9 : 1
10 : 1
11 : 1
12 : 1
13 : 1
14 : 1
15 : 1
16 : 1
233
250
266
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Clocking
Table 72. CSB Frequency Options (continued)
Input Clock Frequency (MHz)
2
csb_clk :
CFG_CLKIN_DIV
SPMF
Input Clock
16.67
25
33.33
66.67
1
at reset
2
Ratio
csb_clk Frequency (MHz)
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
2 : 1
3 : 1
133
200
266
333
100
133
166
200
233
4 : 1
5 : 1
6 : 1
7 : 1
8 : 1
9 : 1
10 : 1
11 : 1
12 : 1
13 : 1
14 : 1
15 : 1
16 : 1
1
2
CFG_CLKIN_DIV is only used for host mode; CLKIN must be tied low and CFG_CLKIN_DIV must be
pulled down (low) in agent mode.
CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
22.2 Core PLL Configuration
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk). Table 73 shows the encodings for RCWL[COREPLL]. COREPLL values not listed
in Table 73 should be considered reserved.
Table 73. e300 Core PLL Configuration
RCWL[COREPLL]
core_clk : csb_clk Ratio
VCO divider
0-1
nn
2-5
6
0000
n
PLL bypassed
PLL bypassed
(PLL off, csb_clk clocks core (PLL off, csb_clk clocks core
directly)
directly)
00
01
0001
0001
0
0
1:1
÷2
1:1
÷4
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 93
Clocking
Table 73. e300 Core PLL Configuration (continued)
RCWL[COREPLL]
core_clk : csb_clk Ratio
VCO divider
0-1
2-5
6
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
0001
0001
0001
0001
0001
0001
0010
0010
0010
0010
0010
0010
0010
0010
0011
0011
0011
0011
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1:1
1:1
÷8
÷8
÷2
÷4
÷8
÷8
÷2
÷4
÷8
÷8
÷2
÷4
÷8
÷8
÷2
÷4
÷8
÷8
1.5:1
1.5:1
1.5:1
1.5:1
2:1
2:1
2:1
2:1
2.5:1
2.5:1
2.5:1
2.5:1
3:1
3:1
3:1
3:1
NOTE
Core VCO frequency = Core frequency × VCO divider. VCO divider
(RCWL[COREPLL[0:1]]) must be set properly so that the core VCO
frequency is in the range of 800–1800 MHz. Having a core frequency below
the CSB frequency is not a possible option because the core frequency must
be equal to or greater than the CSB frequency.
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Clocking
22.3 QUICC Engine PLL Configuration
The QUICC Engine PLL is controlled by the RCWL[CEPMF], RCWL[CEPDF], and RCWL[CEVCOD]
parameters. Table 74 shows the multiplication factor encodings for the QUICC Engine PLL.
Table 74. QUICC Engine PLL Multiplication Factors
QUICC Engine PLL Multiplication
RCWL[CEPMF]
RCWL[CEPDF]
Factor = RCWL[CEPMF] /
(1+RCWL[CEPDF])
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
× 16
Reserved
× 2
× 3
× 4
× 5
× 6
× 7
× 8
× 9
× 10
× 11
× 12
× 13
× 14
× 15
× 16
× 17
× 18
× 19
× 20
× 21
× 22
× 23
× 24
× 25
× 26
× 27
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 95
Clocking
Table 74. QUICC Engine PLL Multiplication Factors (continued)
QUICC Engine PLL Multiplication
RCWL[CEPMF]
RCWL[CEPDF]
Factor = RCWL[CEPMF] /
(1+RCWL[CEPDF])
11100
11101
11110
11111
00011
00101
00111
01001
01011
01101
01111
10001
10011
10101
10111
11001
11011
11101
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
× 28
× 29
× 30
× 31
× 1.5
× 2.5
× 3.5
× 4.5
× 5.5
× 6.5
× 7.5
× 8.5
× 9.5
× 10.5
× 11.5
× 12.5
× 13.5
× 14.5
Notes
1. Reserved modes are not listed.
The RCWL[CEVCOD] denotes the QE PLL VCO internal frequency as shown in Table 75.
Table 75. QE PLL VCO Divider
RCWL[CEVCOD]
VCO Divider
00
01
10
11
4
8
2
Reserved
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96 Freescale Semiconductor
Clocking
NOTE
The VCO divider (RCWL[CEVCOD]) must be set properly so that the QE
VCO frequency is in the range of 600–1400 MHz. The QE frequency is not
restricted by the CSB and core frequencies. The CSB, core, and QE
frequencies should be selected according to the performance requirements.
The QE VCO frequency is derived from the following equations:
ce_clk = (primary clock input × CEPMF) ÷ (1 + CEPDF)
QE VCO Frequency = ce_clk × VCO divider × (1 + CEPDF)
22.4 Suggested PLL Configurations
To simplify the PLL configurations, the device might be separated into two clock domains. The first
domain contains the CSB PLL and the core PLL. The core PLL is connected serially to the CSB PLL, and
has the csb_clk as its input clock. The second clock domain has the QUICC Engine PLL. The clock
domains are independent, and each of their PLLs are configured separately. Both of the domains has one
common input clock. Table 76 shows suggested PLL configurations for 33 MHz and 66 MHz input clocks
and illustrates each of the clock domains separately. Any combination of clock domains setting with same
input clock are valid. Refer to Section 22, “Clocking,” for the appropriate operating frequencies for your
device.
Table 76. Suggested PLL Configurations
Input
CEPMF CEPDF Clock Freq
(MHz)
QUICC
Engine
Freq (MHz)
Conf
No.
CORE
PLL
CSBFreq CoreFreq
(MHz) (MHz)
400
533
667
SPMF
1
(MHz) (MHz) (MHz)
33 MHz CLKIN / PCI_SYNC_IN Options
s1
s2
0100
0100
0101
0101
0110
0110
0111
0111
0111
1000
1000
1000
1001
1001
1001
0000100
0000101
0000100
0000101
0000100
0000110
0000011
0000100
0000101
0000011
0000100
0000101
0000010
0000011
0000100
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
133
133
166
166
200
200
233
233
233
266
266
266
300
300
300
266
333
333
416
400
600
350
466
583
400
533
667
300
450
600
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
s3
s4
s5
∞
∞
s6
s7
∞
∞
s8
s9
s10
s11
s12
s13
s14
s15
∞
∞
∞
∞
∞
∞
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 97
Clocking
Conf
Table 76. Suggested PLL Configurations (continued)
Input
CEPMF CEPDF Clock Freq
(MHz)
QUICC
Engine
Freq (MHz)
CORE
PLL
CSBFreq CoreFreq
400
533
667
SPMF
1
No.
(MHz)
(MHz)
(MHz) (MHz) (MHz)
s16
s17
s18
c1
1010
1010
1010
æ
0000010
æ
æ
æ
æ
0
33
33
33
33
33
33
33
33
33
333
333
333
333
500
667
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
0000011
æ
0000100
æ
æ
æ
æ
æ
æ
æ
01001
01100
01110
01111
10000
10001
300
400
466
500
533
566
∞
∞
∞
∞
∞
∞
∞
c2
æ
0
c3
æ
0
c4
æ
0
c5
æ
0
c6
æ
0
66 MHz CLKIN / PCI_SYNC_IN Options
s1h
s2h
s3h
s4h
s5h
s6h
s7h
s8h
s9h
c1h
c2h
c3h
c4h
0011
0011
0011
0100
0100
0100
0101
0101
0101
æ
0000110
0000101
0000110
0000011
0000100
0000101
0000010
0000011
0000100
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
0
66
66
66
66
66
66
66
66
66
66
66
66
66
66
200
200
200
266
266
266
333
333
333
400
500
600
400
533
667
333
500
667
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
æ
æ
∞
∞
æ
æ
æ
∞
∞
æ
æ
00101
00110
00111
01000
01001
333
400
466
533
600
∞
∞
∞
∞
∞
∞
æ
æ
0
æ
æ
0
æ
æ
0
c5h
æ
æ
0
1
The Conf No. consist of prefix, an index and a postfix. The prefix ‘s’ and ‘c’ stands for ‘syset’ and ‘ce’ respectively. the postfix
‘h’ stands for ‘high input clock.’ The index is a serial number.
The following steps describe how to use Table 76. See the example that follows:
1. Choose the up or down sections in the table according to input clock rate 33 MHz or 66 MHz.
2. Select a suitable CSB and core clock rates from Table 76. Copy the SPMF and CORE PLL
configuration bits.
3. Select a suitable QUICC Engine clock rate from Table 76. Copy the CEPMF and CEPDF
configuration bits.
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Freescale Semiconductor
Thermal
4. Insert the chosen SPMF, COREPLL, CEPMF and CEPDF to the RCWL fields respectively.
Example:
QUICC
EngineFreq
(MHz)
CORE
PLL
Input Clock CSB Freq Core Freq
400
533
667
Index SPMF
CEPMF CEPDF
(MHz)
(MHz)
(MHz)
(MHz) (MHz) (MHz)
A
B
1000
0100
0000011 01001
0000100 00110
0
0
33
66
266
266
400
533
300
400
∞
∞
∞
∞
∞
∞
•
•
Example A. To configure the device with CSB clock rate of 266 MHz, core rate of 400 MHz, and
QUICC Engine clock rate 300 MHz while the input clock rate is 33 MHz. Conf No. “s10” and “c1”
are selected from Table 76. SPMF is “1000,” CORPLL is “0000011,” CEPMF is “01001,” and
CEPDF is “0.”
Example B. To configure the device with CSBCSB clock rate of 266 MHz, core rate of 533 MHz
and QUICC Engine clock rate 400 MHz while the input clock rate is 66 MHz. Conf No. “s5h” and
“c2h” are selected from Table 76. SPMF is “0100,” CORPLL is “0000100,” CEPMF is “00110”
and CEPDF is “0.”
23 Thermal
This section describes the thermal specifications of the MPC8360E/58E.
23.1 Thermal Characteristics
Table 77 provides the package thermal characteristics for the 740 37.5 mm x 37.5 mm TBGA package.
Table 77. Package Thermal Characteristics for the TBGA Package
Characteristic
Symbol
Value
Unit
Notes
Junction-to-ambient Natural Convection on single layer board (1s)
Junction-to-ambient Natural Convection on four layer board (2s2p)
Junction-to-ambient (@1 m/s) on single layer board (1s)
Junction-to-ambient (@ 1 m/s) on four layer board (2s2p)
Junction-to-ambient (@ 2 m/s) on single layer board (1s)
Junction-to-ambient (@ 2 m/s) on four layer board (2s2p)
Junction-to-board thermal
R
R
15
11
10
8
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
1, 2
1, 3
1, 3
1, 3
1, 3
1, 3
4
θJA
θJA
R
R
R
R
θJMA
θJMA
θJMA
θJMA
9
7
R
4.5
1.1
θJB
θJC
Junction-to-case thermal
R
5
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 99
Thermal
Table 77. Package Thermal Characteristics for the TBGA Package (continued)
Characteristic
Symbol
Value
Unit
Notes
Junction-to-Package Natural Convection on Top
ψ
1
°C/W
6
JT
Notes
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2. Per JEDEC JESD51-2 and SEMI G38-87with the single layer board horizontal.
3. Per JEDEC JESD51-6 with the board horizontal. 1 m/sec is approximately equal to 200 linear feet per minute (LFM).
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter
is written as Psi-JT.
23.2 Thermal Management Information
For the following sections, P = (V X I ) + P where P is the power dissipation of the I/O drivers.
D
DD
DD
I/O
I/O
See Table 6 for typical power dissipations values.
23.2.1 Estimation of Junction Temperature with Junction-to-Ambient
Thermal Resistance
An estimation of the chip junction temperature, T , can be obtained from the equation:
J
T = T + (R
× P )
D
J
A
θJA
where:
T = junction temperature (°C)
J
T = ambient temperature for the package (°C)
A
R
= junction to ambient thermal resistance (°C/W)
θJA
P = power dissipation in the package (W)
D
The junction to ambient thermal resistance is an industry standard value that provides a quick and easy
estimation of thermal performance. As a general statement, the value obtained on a single layer board is
appropriate for a tightly packed printed circuit board. The value obtained on the board with the internal
planes is usually appropriate if the board has low power dissipation and the components are well separated.
Test cases have demonstrated that errors of a factor of two (in the quantity T - T ) are possible.
J
A
23.2.2 Estimation of Junction Temperature with Junction-to-Board
Thermal Resistance
The thermal performance of a device cannot be adequately predicted from the junction to ambient thermal
resistance. The thermal performance of any component is strongly dependent on the power dissipation of
surrounding components. In addition, the ambient temperature varies widely within the application. For
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
100
Freescale Semiconductor
Thermal
many natural convection and especially closed box applications, the board temperature at the perimeter
(edge) of the package will be approximately the same as the local air temperature near the device.
Specifying the local ambient conditions explicitly as the board temperature provides a more precise
description of the local ambient conditions that determine the temperature of the device. At a known board
temperature, the junction temperature is estimated using the following equation:
T = T + (R
× P )
D
J
B
θJB
where:
T = junction temperature (°C)
J
T = board temperature at the package perimeter (°C)
B
R
= junction to board thermal resistance (°C/W) per JESD51-8
θJA
P = power dissipation in the package (W)
D
When the heat loss from the package case to the air can be ignored, acceptable predictions of junction
temperature can be made. The application board should be similar to the thermal test condition: the
component is soldered to a board with internal planes.
23.2.3 Experimental Determination of Junction Temperature
To determine the junction temperature of the device in the application after prototypes are available, the
Thermal Characterization Parameter (Ψ ) can be used to determine the junction temperature with a
JT
measurement of the temperature at the top center of the package case using the following equation:
T = T + (Ψ × P )
J
T
JT
D
where:
T = junction temperature (°C)
J
T = thermocouple temperature on top of package (°C)
T
Ψ = junction to ambient thermal resistance (°C/W)
JT
P = power dissipation in the package (W)
D
The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so
that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire
is placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
23.2.4 Heat Sinks and Junction-to-Case Thermal Resistance
In some application environments, a heat sink will be required to provide the necessary thermal
management of the device. When a heat sink is used, the thermal resistance is expressed as the sum of a
junction to case thermal resistance and a case to ambient thermal resistance:
R
= R
+ R
θJA
θJC θCA
where:
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 101
Thermal
R
R
R
= junction to ambient thermal resistance (°C/W)
= junction to case thermal resistance (°C/W)
= case to ambient thermal resistance (°C/W)
θJA
θJC
θCA
Rθ is device related and cannot be influenced by the user. The user controls the thermal environment to
JC
change the case to ambient thermal resistance, Rθ . For instance, the user can change the size of the heat
CA
sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit
board, or change the thermal dissipation on the printed circuit board surrounding the device.
To illustrate the thermal performance of the devices with heat sinks, the thermal performance has been
simulated with a few commercially available heat sinks. The heat sink choice is determined by the
application environment (temperature, air flow, adjacent component power dissipation) and the physical
space available. Because there is not a standard application environment, a standard heat sink is not
required.
Table 78 shows heat sinks and junction-to-case thermal resistance for TBGA package.
Table 78. Heat Sinks and Junction-to-Case Thermal Resistance of TBGA Package
35x35 mm TBGA
Heat Sink Assuming Thermal Grease
Air Flow
Junction-to-Ambient
Thermal Resistance
AAVID 30x30x9.4 mm Pin Fin
AAVID 30x30x9.4 mm Pin Fin
Natural Convention
1 m/s
10.7
6.2
5.3
8.1
4.4
3.7
5.4
3.2
2.4
6.4
3.8
2.5
2.8
AAVID 30x30x9.4 mm Pin Fin
2 m/s
AAVID 31x35x23 mm Pin Fin
Natural Convention
1 m/s
AAVID 31x35x23 mm Pin Fin
AAVID 31x35x23 mm Pin Fin
2 m/s
Wakefield, 53x53x25 mm Pin Fin
Natural Convention
1 m/s
Wakefield, 53x53x25 mm Pin Fin
Wakefield, 53x53x25 mm Pin Fin
2 m/s
MEI, 75x85x12 no adjacent board, extrusion
MEI, 75x85x12 no adjacent board, extrusion
MEI, 75x85x12 no adjacent board, extrusion
MEI, 75x85x12 mm, adjacent board, 40 mm Side bypass
Natural Convention
1 m/s
2 m/s
1 m/s
Accurate thermal design requires thermal modeling of the application environment using computational
fluid dynamics software which can model both the conduction cooling and the convection cooling of the
air moving through the application. Simplified thermal models of the packages can be assembled using the
junction-to-case and junction-to-board thermal resistances listed in the thermal resistance table. More
detailed thermal models can be made available on request.
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
102
Freescale Semiconductor
Thermal
Heat sink vendors include the following:
Aavid Thermalloy
80 Commercial St.
Concord, NH 03301
Internet: www.aavidthermalloy.com
Alpha Novatech
603-224-9988
408-749-7601
473 Sapena Ct. #15
Santa Clara, CA 95054
Internet: www.alphanovatech.com
International Electronic Research Corporation (IERC)
413 North Moss St.
Burbank, CA 91502
818-842-7277
408-436-8770
Internet: www.ctscorp.com
Millennium Electronics (MEI)
Loroco Sites
671 East Brokaw Road
San Jose, CA 95112
Internet: www.mei-millennium.com
Tyco Electronics
Chip Coolers™
P.O. Box 3668
Harrisburg, PA 17105-3668
Internet: www.chipcoolers.com
800-522-6752
603-635-5102
Wakefield Engineering
33 Bridge St.
Pelham, NH 03076
Internet: www.wakefield.com
Interface material vendors include the following:
Chomerics, Inc.
77 Dragon Ct.
Woburn, MA 01888-4014
Internet: www.chomerics.com
781-935-4850
800-248-2481
Dow-Corning Corporation
Dow-Corning Electronic Materials
2200 W. Salzburg Rd.
Midland, MI 48686-0997
Internet: www.dowcorning.com
Shin-Etsu MicroSi, Inc.
10028 S. 51st St.
888-642-7674
Phoenix, AZ 85044
Internet: www.microsi.com
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 103
System Design Information
The Bergquist Company
800-347-4572
18930 West 78th St.
Chanhassen, MN 55317
Internet: www.bergquistcompany.com
23.3 Heat Sink Attachment
When attaching heat sinks to these devices, an interface material is required. The best method is to use
thermal grease and a spring clip. The spring clip should connect to the printed circuit board, either to the
board itself, to hooks soldered to the board, or to a plastic stiffener. Avoid attachment forces which would
lift the edge of the package or peel the package from the board. Such peeling forces reduce the solder joint
lifetime of the package. Recommended maximum force on the top of the package is 10 lb force (4.5 kg
force). If an adhesive attachment is planned, the adhesive should be intended for attachment to painted or
plastic surfaces and its performance verified under the application requirements.
23.3.1 Experimental Determination of the Junction Temperature with a
Heat Sink
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimizing the size of the clearance is important to minimize the change in
thermal performance caused by removing part of the thermal interface to the heat sink. Because of the
experimental difficulties with this technique, many engineers measure the heat sink temperature and then
back calculate the case temperature using a separate measurement of the thermal resistance of the
interface. From this case temperature, the junction temperature is determined from the junction to case
thermal resistance.
T = T + (R
× P )
D
J
C
θJC
where:
T = junction temperature (°C)
J
T = case temperature of the package (°C)
C
R
= junction to case thermal resistance (°C/W)
θJC
P = power dissipation (W)
D
24 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8360E/58E. Additional information can be found in AN3097, MPC8360E/MPC8358E
PowerQUICC™ Design Checklist, Rev. 1.
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
104
Freescale Semiconductor
System Design Information
24.1 System Clocking
The device includes two PLLs.
1. The platform PLL (AV 1) generates the platform clock from the externally supplied CLKIN
DD
input. The frequency ratio between the platform and CLKIN is selected using the platform PLL
ratio configuration bits as described in Section 22.1, “System PLL Configuration.”
2. The e300 core PLL (AV 2) generates the core clock as a slave to the platform clock. The
DD
frequency ratio between the e300 core clock and the platform clock is selected using the e300
PLL ratio configuration bits as described in Section 22.2, “Core PLL Configuration.”
24.2 PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins (AV 1,
DD
AV 2 respectively). The AV level should always be equivalent to V , and preferably these voltages
DD
DD
DD
will be derived directly from V through a low frequency filter scheme such as the following.
DD
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide five independent filter circuits as illustrated in Figure 55, one to each of the five AV pins. By
DD
providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the
other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AV pin being supplied to minimize
DD
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AV
pin, which is on the periphery of package, without the inductance of vias.
DD
Figure 55 shows the PLL power supply filter circuit.
10 Ω
V
AV
n
DD
DD
2.2 µF
2.2 µF
Low ESL Surface Mount Capacitors
GND
Figure 55. PLL Power Supply Filter Circuit
24.3 Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the device can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the device system, and the device itself
requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer
place at least one decoupling capacitor at each V , OV , GV , and LV pins of the device. These
DD
DD
DD
DD
decoupling capacitors should receive their power from separate V , OV , GV , LV , and GND
DD
DD
DD
DD
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 105
System Design Information
power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed directly
under the device using a standard escape pattern. Others may surround the part.
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the V , OV , GV , and LV planes, to enable quick recharging of the smaller chip
DD
DD
DD
DD
capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the
quick response time necessary. They should also be connected to the power and ground planes through two
vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS tantalum or Sanyo
OSCON).
24.4 Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to OV , GV , or LV as required. Unused active high
DD
DD
DD
inputs should be connected to GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external V , GV , LV , OV , and GND pins of
DD
DD
DD
DD
the device.
24.5 Output Buffer DC Impedance
The device drivers are characterized over process, voltage, and temperature. For all buses, the driver is a
2
push-pull single-ended driver type (open drain for I C).
To measure Z for the single-ended drivers, an external resistor is connected from the chip pad to OV
0
DD
or GND. Then, the value of each resistor is varied until the pad voltage is OV /2 (see Figure 56). The
DD
output impedance is the average of two components, the resistances of the pull-up and pull-down devices.
When data is held high, SW1 is closed (SW2 is open) and R is trimmed until the voltage at the pad equals
P
OV /2. R then becomes the resistance of the pull-up devices. R and R are designed to be close to each
DD
P
P
N
other in value. Then, Z = (R + R )/2.
0
P
N
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
106 Freescale Semiconductor
System Design Information
OV
DD
R
N
SW2
SW1
Pad
Data
R
P
OGND
Figure 56. Driver Impedance Measurement
The value of this resistance and the strength of the driver’s current source can be found by making two
measurements. First, the output voltage is measured while driving logic 1 without an external differential
termination resistor. The measured voltage is V = R
while driving logic 1 with an external precision differential termination resistor of value R . The
× I
. Second, the output voltage is measured
1
source
source
term
measured voltage is V = 1/(1/R + 1/R )) × I
. Solving for the output impedance gives R
= R
2
1
2
source
source term
× (V /V – 1). The drive current is then I
= V /R
.
1
2
source
1
source
Table 79 summarizes the signal impedance targets. The driver impedance are targeted at minimum V
,
DD
nominal OV , 105°C.
DD
Table 79. Impedance Characteristics
Local Bus, Ethernet,
DUART, Control,
Configuration, Power
Management
Impedance
PCI
DDR DRAM Symbol
Unit
R
N
42 Target
42 Target
NA
25 Target
25 Target
NA
20 Target
20 Target
NA
Z
Z
W
W
W
0
0
R
P
Differential
Z
DIFF
Note: Nominal supply voltages. See Table 1, T = 105°C.
J
24.6 Configuration Pin Muxing
The device provides the user with power-on configuration options which can be set through the use of
external pull-up or pull-down resistors of 4.7 kΩ on certain output pins (see customer visible configuration
pins). These pins are generally used as output only pins in normal operation.
While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins
while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor
107
Document Revision History
and the I/O circuit takes on its normal function. Careful board layout with stubless connections to these
pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should minimize
the disruption of signal quality or speed for output pins thus configured.
24.7 Pull-Up Resistor Requirements
The device requires high resistance pull-up resistors (10 kΩ is recommended) on open drain type pins
2
including I C pins, Ethernet Management MDIO pin, and EPIC interrupt pins.
For more information on required pull-up resistors and the connections required for the JTAG interface,
see AN3097, MPC8360E/MPC8358E PowerQUICC™ Design Checklist, Rev. 1.
25 Document Revision History
Table 80 provides a revision history for this hardware specification.
Table 80. Document Revision History
Rev.
Number
Date
Substantive Change(s)
0
12/07/2007 Initial release.
26 Ordering Information
Ordering information for the parts fully covered by this specification document is provided in
Section 26.1, “Part Numbers Fully Addressed by this Document.”
26.1 Part Numbers Fully Addressed by this Document
Table 81 provides the Freescale part numbering nomenclature for the MPC8360E/58E. Note that the
individual part numbers correspond to a maximum processor core frequency. For available frequencies,
contact your local Freescale sales office. In addition to the processor frequency, the part numbering scheme
also includes an application modifier which may specify special application conditions. Each part number
also contains a revision code which refers to the die mask revision number.
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
108
Freescale Semiconductor
Ordering Information
1
Table 81. Part Numbering Nomenclature
MPC
nnnn
Part
e
t
pp
aa
a
a
A
QUICC
Engine
Frequency
Product
Code Identifier Acceleration
Encryption Temperature
Processor
Frequency
Platform
Frequency
Die
Revision
2
Package
3
Range
MPC
8358
Blank = Not
included
E = included
0°C T to
ZU = TBGA
e300
core speed
AD = 266 MHz
AG = 400 MHz
D = 266 MHz E = 300 MHz A=revision
G = 400 MHz 2.1 silicon
A
105°C T
VV=TBGA
(no lead)
J
8360
e300
D = 266 MHz G = 400 MHz A=revision
core speed
F = 333 MHz H = 500 MHz
2.1 silicon
AG = 400 MHz
AJ = 533 MHz
AL = 667 MHz
MPC
(rev2.0
silicon
only)
8360
Blank = Not
included
E = included
0°C T to
ZU = TBGA
e300
core speed
AH = 500 MHz
AL = 667 MHz
F = 333 MHz G = 400 MHz
H = 500 MHz
A
70°C T
VV=TBGA
(no lead)
J
1
Not all processor, platform, and QUICC Engine frequency combinations are supported. For available frequency combinations,
contact your local Freescale Sales Office or authorized distributor.
2
3
See Section 21, “Package and Pin Listings,” for more information on available package types.
Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this
specification support all core frequencies. Additionally, parts addressed by Part Number Specifications may support other
maximum core frequencies.
Table 82 shows the SVR settings by device and package type.
Table 82. SVR Settings
SVR
(Rev 2.0)
SVR
(Rev 2.1)
Device
MPC8360E
Package
TBGA
TBGA
TBGA
TBGA
0x8048_0020
0x8049_0020
0x804A_0020
0x804B_0020
0x8048_0021
0x8049_0021
0x804A_0021
0x804B_0021
MPC8360
MPC8358E
MPC8358
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 109
Ordering Information
THIS PAGE INTENTIONALLY LEFT BLANK
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
110 Freescale Semiconductor
Ordering Information
THIS PAGE INTENTIONALLY LEFT BLANK
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Freescale Semiconductor 111
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© Freescale Semiconductor, Inc., 2007. Printed in the United States of
America. All rights reserved.
Document Number: MPC8360EEC
Rev. 2
12/2007
相关型号：
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