MPC8536ECVTAVL [FREESCALE]
PowerQUICC™ III Integrated Processor Hardware Specifications; 的PowerQUICC ™III集成处理器硬件规格
| 型号： | MPC8536ECVTAVL |
| 厂家： | 
Freescale |
| 描述： | PowerQUICC™ III Integrated Processor Hardware Specifications |
| 文件： | 总128页 (文件大小：1674K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MPC8536EEC
Rev. 2, 09/2009
Freescale Semiconductor
Data Sheet: Product Preview
MPC8536E
PowerQUICC™ III
Integrated Processor
Hardware Specifications
FC-PBGA–783
29 mm × 29 mm
• High-performance, 32-bit e500 core, scaling up to
1.5 GHz, that implements the Power Architecture™
technology
– Support for various Ethernet physical interfaces: GMII,
TBI, RTBI, RGMII, MII, RGMII, RMII, and SGMII
– Support TCP/IP acceleration and QOS features
– MAC address recognition and RMON statistics support
– Support ARP parsing and generating wake-up events
based on the parsing results while in deep sleep mode
– Support accepting and storing packets while in deep
sleep mode
– 36-bit physical addressing
– Double-precision embedded floating point APU using
64-bit operands
– Embedded vector and scalar single-precision
floating-point APUs using 32- or 64-bit operands
– Memory management unit (MMU)
• High-speed interfaces (multiplexed) supporting:
– Three PCI Express interfaces
• Integrated L1/L2 cache
– L1 cache—32-Kbyte data and 32-Kbyte instruction
– L2 cache—512-Kbyte (8-way set associative)
• DDR2/DDR3 SDRAM memory controller with full ECC
support
– PCI Express 1.0a compatible
– One x8/x4/x2/x1 PCI Express interface
– Two x4/x2/x1 ports, or,
– One x4/x2/x1 port and Two x2/x1 ports
– Two SGMII interfaces
– One 64-bit/32-bit data bus
– Up to 333-MHz clock (667-MHz data rate)
– Supporting up to 16 Gbytes of main memory
– Using ECC, detects and corrects all single-bit errors and
detects all double-bit errors and all errors within a nibble
– Invoke a level of system power management by
asserting MCKE SDRAM signal on-the-fly to put the
memory into a low-power sleep mode
– Two Serial ATA (SATA) Controllers support SATA I and
SATA II data rates
• PCI 2.2 compatible PCI controller
• Three universal serial bus (USB) dual-role controllers
comply with USB specification revision 2.0
• 133-MHz, 32-bit, enhanced local bus (eLBC) with memory
controller
– Both hardware and software options to support
battery-backed main memory
• Enhanced secured digital host controller (eSDHC) used for
SD/MMC card interface
• Integrated security engine (SEC) optimized to process all
the algorithms associated with IPsec, IKE, SSL/TLS,
iSCSI, SRTP, IEEE Std 802.16e™, and 3GPP.
– XOR engine for parity checking in RAID storage
applications
– Support boot capability from eSDHC
• Integrated four-channel DMA controller
• Dual I C and dual universal asynchronous
receiver/transmitter (DUART) support
• Programmable interrupt controller (PIC)
2
• Enhanced Serial peripheral interfaces (eSPI)
– Support boot capability from eSPI
• Two enhanced three-speed Ethernet controllers (eTSECs)
with SGMII support
• Power management, low standby power
– Support Doze, Nap, Sleep, Jog, and Deep Sleep mode
– PMC wake on: LAN activity, USB connection or remote
wakeup, GPIO, internal timer, or external interrupt event
• System performance monitor
• IEEE Std 1149.1™-compatible, JTAG boundary scan
• 783-pin FC-PBGA package, 29 mm × 29 mm
– Three-speed support (10/100/1000 Mbps)
– Two IEEE Std 802.3™, IEEE 802.3u, IEEE 802.3x,
IEEE 802.3z, IEEE 802.3ac, IEEE 802.3ab, and
IEEE Std 1588™-compatible controllers
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2009. All rights reserved.
Table of Contents
1
2
Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .3
2.21 PCI Express. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
2.23 Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
2.24 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . 114
3.1 System Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
3.2 Power Supply Design and Sequencing . . . . . . . . . . . 115
3.3 Pin States in Deep Sleep State . . . . . . . . . . . . . . . . . 116
3.4 Decoupling Recommendations . . . . . . . . . . . . . . . . . 116
1.1 Pin Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.1 Overall DC Electrical Characteristics . . . . . . . . . . . . . .21
2.2 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.3 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.4 Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.5 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.6 DDR2 and DDR3 SDRAM . . . . . . . . . . . . . . . . . . . . . .32
2.7 eSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
2.8 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
2.9 Ethernet: Enhanced Three-Speed Ethernet (eTSEC),
MII Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
2.10 Ethernet Management Interface Electrical Characteristics
61
3
3.5 SerDes
Block
Power
Supply
Decoupling
Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . 116
3.6 Connection Recommendations . . . . . . . . . . . . . . . . . 116
3.7 Pull-Up and Pull-Down Resistor Requirements. . . . . 117
3.8 Output Buffer DC Impedance . . . . . . . . . . . . . . . . . . 117
3.9 Configuration Pin Muxing . . . . . . . . . . . . . . . . . . . . . 118
3.10 JTAG Configuration Signals . . . . . . . . . . . . . . . . . . . 118
3.11 Guidelines for High-Speed Interface Termination . . . 121
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
4.1 Part Numbers Fully Addressed by This Document . . 123
4.2 Part Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.3 Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5.1 Package Parameters for the MPC8536E FC-PBGA . 124
5.2 Mechanical Dimensions of the MPC8536E FC-PBGA125
Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . 126
2.11 USB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
2.12 enhanced Local Bus Controller (eLBC) . . . . . . . . . . . .66
2.13 Enhanced Secure Digital Host Controller (eSDHC) . . .75
2.14 Programmable Interrupt Controller (PIC) . . . . . . . . . . .77
2.15 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
2.16 Serial ATA (SATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
2.17 I2C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
2.18 GPIO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
2.19 PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
2.20 High-Speed Serial Interfaces . . . . . . . . . . . . . . . . . . . .91
4
5
6
7
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
2
Figure 1 shows the major functional units within the MPC8536E.
e500 Core
512-Kbyte
L2 Cache
Power
Management
32-Kbyte
D-Cache
32-Kbyte
I-Cache
MPC8536E
64-bit
DDR2/DDR3
SDRAM Controller
with ECC
Performance
Async
Queue
eSPI
Enhanced
Local Bus
Coherency
Module
Monitor
Timers
DUART
SEC
OpenPIC
2
2x I C
PCI 32
PCI-e
DMA
Gigabit
Ethernet
Gigabit
USB
Host/
USB
USB
SD
MMC
Ethernet
Host/
Host/
Device
Device
Device
SATA
SATA w/ IEEE 1588 w/ IEEE 1588
PCI-e
PCI-e
SGMII
SGMII
ULPI
ULPI
ULPI
2 Lane SERDES
8 Lane SERDES
Figure 1. MPC8536E Block Diagram
1
Pin Assignments and Reset States
NOTE
The naming convention of TSEC1 and TSEC3 is used to allow the splitting voltage rails
for the eTSEC blocks and to ease the port of existing PowerQUICC III software
NOTE
The UART_SOUT[0:1] and TEST_SEL pins must be set to a proper state during POR
configuration. Please refer to Table 1 for more details.
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
3
Pin Map
1.1
Pin Map
Figure 2 provides a bottom view of the pin map of the MPC8536E.
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AVDD_
SRDS2
TSEC3_
RXD
TSEC1_
RXD
[1]
MDQ
[32]
MDQ
[46]
MDQ
[47]
MDQ
[34]
MDQ
[56]
MDQ
[57]
MDQS
[7]
MDQ
[58]
MDQ
[59]
MDQS
[5]
TSEC3_
RX_CLK
TSEC1_
TX_EN
TSEC1_
RX_DV
USB1_
CLK
USB1_ USB1_
USB1_D USB1_D
[0] [2]
USB1_D USB1_D
GV
DD
GV
DD
GND
GND
1
2
1
2
3
4
5
6
7
8
9
10
STP
DIR
[5]
[7]
[3]
USB1_
PWR-
FAULT
TSEC3_
RXD
[1]
TSEC1_ TSEC1_
RXD
[0]
AGND_
SRDS2
TSEC1_
GTX_CLK
MDQ
[44]
MDQ
[40]
MDM
[5]
MDQS
[5]
MDQ
[42]
MDQ
[43]
MDQ
[35]
MDQ
[60]
MDQ
[61]
MDM
[7]
MDM
[62]
MDQ
[63]
TSEC3_
RX_DV
MDQS
[7]
USB1_
NXT
USB1_D USB1_D USB1_D USB1_D
GV
DD
OV
DD
GND
RXD
[3]
[1]
[3]
[4]
[6]
USB1_
PCTL0/
GPIO[6]
SD2_
PLL_
TPA
TSEC3_ TSEC3_ TSEC1_ TSEC1_
TSEC1_
MDQ
[38]
MDM
[6]
MDQ
[50]
MDQ
[51]
MDQ
[45]
MDQ
[41]
MCS
[0]
MDQ
[33]
MDQ
[52]
MDQS
[6]
TSEC1_
RX_CLK
USB2_D USB2_D
[0] [1]
USB3_D USB3_D
[1] [0]
GV
DD
GV
DD
GV
DD
GND
GND
GND
3
RXD
RXD
TXD
RXD
RXD
[2]
[0]
[3]
[2]
[7]
USB1_
TSEC1_
TXD
[1]
MBA
[0]
MDQ
[36]
MDM
[4]
MDQ
[39]
MDQ
[53]
MDQ
[49]
MDQ
[54]
MDQ
[55]
Rvsd TSEC3_
RX_ER
TSEC1_
TX_CLK
MCS
[2]
MDQS
[6]
USB2_D USB2_D USB3_D USB3_D
[2] [3] [3] [2]
GV
DD
TV
LV
PCTL1/ OV
MWE
GND
GND
GND
GND
4
DD
DD
DD
GPIO[7]
TSEC3_
TXD
[1]
TSEC1_ TSEC1_ TSEC1_
Rvsd
TSEC3_
GTX_CLK
MA
[10]
MBA
[1]
MODT
[0]
MDQ
[37]
MDQS
[4]
MDQ
[48]
TSEC3_
TX_EN
TSEC1_
TX_ER
MDQS
[4]
USB2_ USB2_D USB2_D USB3_D USB3_
CLK
GV
DD
GV
DD
GV
DD
MRAS
GND
GND
GND
GND
GND
5
TXD
[2]
TXD
[4]
TXD
[6]
[4]
[5]
[4]
CLK
DMA_
DACK[0]/
GPIO[10]
SD2_
IMP_CAL
_TX
SD2_
REF_
CLK
TSEC3_ TSEC3_ TSEC3_ TSEC1_ TSEC1_
TXD
[0]
MODT MODT
[2]
MCK
[2]
SD2_RX
[0]
TSEC1_
COL
MCS
[3]
MCS
[1]
MCK
[2]
EC_GTX_
CLK125
MAPAR_
OUT
USB2_D
[6]
USB2_D
[7]
USB3_D USB3_D
[6] [5]
GV
DD
NC
S2GND
S2V
DD
OV
DD
6
RXD
[5]
RXD
[4]
TXD
RXD
[3]
[0]
[4]
TSEC_
1588_TRIG
_IN[1]
SD2_
REF_
CLK
SD2_
IMP_CAL
_RX
SD2_
PLL_
TPD
TSEC3_
TXD
[2]
TSEC1_
RXD
[6]
MA
[0]
MA
[13]
MODT
[1]
SD2_RX
[0]
USB2_ USB2_
NXT STP
USB2_ USB3_ USB3_D
GV
DD
GV
DD
TV
LV
MCAS
GND
GND
NC
GND
GND
GND
NC
NC
S2V
DD
GND
7
DD
DD
DIR
NXT
[7]
SEE DETAIL A
SEE DETAIL B
SDHC_
DAT[4]/SPI
_CS[0]
TSEC_
1588_TRIG
_IN[0]
USB2_
PWR-
FAULT
TSEC3_ TSEC3_ TSEC3_
TXD
[3]
TSEC1_ TSEC1_ TSEC1_
SPI_
CLK
SPI_
MOSI
MCK
[3]
MCK
[3]
MA
[2]
MA
[1]
MCK
[5]
MCK
[5]
SD2_RX
[1]
USB3_ USB3_
GV
DD
GND
GND
Rsvd
Rsvd
NC
S2GND
S2GND
S2GND
NC
NC
NC
NC
8
TXD
[5]
TXD
[6]
TXD
TXD
RXD
DIR
STP
[5]
[7]
[5]
SDHC_
DAT[6]/SPI
_CS[2]
USB2_
PCTL1/
GPIO[9]
USB2_
PCTL0/
GPIO[8]
TSEC_
1588_
CLK
TSEC3_
SPI_
MISO
MCK
[0]
MCK
[0]
MA
[4]
MA
[8]
MA
[7]
MCKE
[3]
TSEC3_ TSEC3_
COL TX_ER
TSEC1_ TSEC1_
RX_ER
SD2_RX
[1]
GV
DD
GV
DD
NC
GV
S2V
DD
GND
GND
Rsvd
9
TXD
CRS
[4]
SDHC_
SDHC_
TSEC_
1588_TRIG
_OUT[1]
TSEC_
1588_CLK
_OUT
DMA_
DMA_
DACK[1]/
GPIO[11]
SDHC_
SOUT WP/GPIO
UART_
EC_
MDC
MA
[3]
MA
[5]
MA
[14]
MA
[15]
TSEC3_ TSEC3_
CRS TX_CLK
SDHC_
CMD
MCKE
[2]
MCKE
[0]
MCKE
[1]
OV
DD
GND
NC
DAT[7]/SPI DREQ[0]/ DAT[5]/SPI
GPIO[14]
X2GND
NC
DD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
_CS[3]
DMA_
_CS[1]
GND
[0]
[5]
TSEC_
TSEC_
TSEC_
DMA_
DMA_
DREQ[1]/
GPIO[15]
SDHC_
UART_
CTS
[0]
SDHC_
DAT
[3]
EC_
MDIO
MA
[6]
MECC
[3]
MA
[12]
MECC
[2]
MCK
[1]
MCK
[1]
SD2_TX
[1]
SD2_TX
[0]
MSRCID
[4]
GV
DD
GV
DD
GV
DD
1588_PULSE 1588_TRIG1588_PULSE
_OUT2
DDONE[0]/ DDONE[1]/
GPIO[12] GPIO[13]
OV
DD
GND
X2V
DD
X2GND
X2V
DD
CD/GPIO 11
_OUT[0]
_OUT1
[4]
UART_ UART_ UART_ UART_ UART_
UART_
SIN
SDHC_ SDHC_
TSEC3_ TSEC3_
MA
[11]
MA
[9]
MECC
[7]
MECC
[0]
SD2_TX
[1]
SD2_TX
[0]
MSRCID MSRCID
GV
DD
GV
DD
X2V
DD
GND
GND
GND
X2GND
GND
X2GND
GND
GND
NC
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SOUT
[1]
SIN
[0]
DAT
[0]
DAT
[1]
TXD
[7]
RXD
[7]
CTS
[1]
RTS
[0]
RTS
[1]
[2]
[0]
[1]
IRQ[10]/
DMA_
DACK[2] DREQ[2]
IRQ[9]/
DMA_
PCI1_
REQ
[2]
SDHC_
DAT
[2]
TSEC3_
VDD_
CORE
VDD_
CORE
VDD_
CORE
VDD_
CORE
TEST_
SEL
MBA
[2]
MECC MDQS
MDM
[8]
MCK
[4]
SDHC_
CLK
MDQS
[8]
MCK
[4]
MAPAR_
ERR
MSRCID
[1]
GND
MDVAL
GND
MCP
GND
OV
DD
DDRCLK
PCI1_GNT
RXD
[6]
[8]
[6]
IRQ[11]/
DMA_
DDONE[2]
PCI1_
MECC
[1]
MECC MECC
VDD_
CORE
VDD_
CORE
VDD_
CORE
VDD_
CORE
IIC2_
SDA
MDQ
[27]
MSRCID
[3]
OV
DD
GV
DD
GV
DD
GV
DD
GV
DD
GND
GND
GND
GND
GND
SYSCLK
GND
GND
GND
UDE
GNT
[5]
[4]
[4]/GPIO
[2]
[3]
SENSE-
VDD_
CORE
PCI1_
AD
[31]
PCI1_
AD
[28]
PCI1_REQ PCI1_GNT
[3]/GPIO [3]/GPIO
PCI1_REQ
CLK_
OUT
IIC2_
SCL
MDQ
[26]
MDIC
[0]
MDIC
[1]
VDD_
CORE
VDD_
CORE
VDD_
CORE
MDQ
[31]
HRESET_
REQ
GV
DD
GV
DD
GND
GND
GND
GND
GND
GND
GND
GND
RTC
[4]/GPIO
[0]
[2]
[1]
LCS5/
DMA_
DREQ2
LCS6/
DMA_
DACK2
PCI1_
REQ
[1]
PCI1_
GNT
[1]
PCI1_
REQ
[0]
PCI1_
AD
[26]
VDD_
CORE
VDD_
CORE
VDD_
CORE
VDD_
CORE
PCI1_
IDSEL
AVDD_
CORE
MDQ
[30]
MDQS
[3]
MDQ
[19]
MDQ
[23]
MDQ
[18]
LA
[28]
IRQ
[5]
LCS
[4]
SENSE-
VSS
OV
DD
OV
DD
GND
GND
GND
HRESET
GND
SENSE- PCI1_
PCI1_
AD
[29]
PCI1_
AD
[27]
PCI1_
AD
[24]
PCI1_
AD
[23]
MDM
[3]
VDD_
PLAT
VDD_
PLAT
VDD_
PLAT
VDD_
PLAT
IRQ_
OUT
IRQ
[1]
IRQ
[4]
MDQS
[2]
MDQ
[22]
LA
[31]
LA
[30]
LA
[29]
CKSTP_
OUT
MDQS
[3]
GV
DD
GND
GND
GND
GND
GND
GND
AD
VDD_
PLAT
[30]
LCS7/
DMA_
DDONE2
PCI1_
C_BE
[3]
PCI1_
OV
PCI1_
AD
[25]
PCI1_
AD
[22]
PCI1_
AD
[20]
PCI1_
AD
[18]
VDD_
PLAT
VDD_
PLAT
VDD_
PLAT
AVDD_
PLAT
MDQ
[25]
MDQ
[24]
MDM
[2]
MDQ
[21]
MDQS
[2]
LCS
[0]
LGPL3/
LFWP
CKSTP_
IN
GV
DD
BV
DD
OV
DD
GND
GND
GND
GND
GND
TRIG_
DD
GNT
[0]
PCI1_
AD
PCI1_
AD
PCI1_
AD
MDQ
[29]
MDQ
[28]
MDQ
[17]
MDQ
[16]
MDQ
[20]
LA
[27]
VDD_
PLAT
VDD_
PLAT
VDD_
PLAT
AVDD_
DDR
IRQ
[7]
IRQ
[3]
LCS
[1]
LCS
[2]
OUT/READY TRIG_IN
BV
DD
NC
LGPL5
GND
GND
GND
GND
GND
SRESET
ASLEEP
[21]
[19]
[17]
/QUIESCE
LGPL4/
PCI1_
C_BE
[2]
LGPL2/
LOE/
LFRE
PCI1_
AD
LGTA/
LUPWAIT/
LPBSE/
LFRB
L2_
TSTCLK
PCI1_
FRAME
AVDD_
PCI1
MDQ
[11]
MDQ
[10]
PCI1_
IRDY
LCS
[3]
LGPL0/ LGPL1/
LFCLE LFALE
SD1_TX
[1]
SD1_TX
[3]
SD1_TX
[4]
SD1_TX
XGND
GV
DD
BV
DD
XV
DD
XV
DD
XV
DD
OV
DD
GND
GND
XGND
[6]
[16]
L1_
PCI1_
PCI1_
STOP
PCI1_
TRDY
IIC1_
SCL
MDQ
[15]
MDQ
[14]
MDQ
[3]
MDQ
[7]
LAD
[31]
LWE[3]/
LBS[3]
LAD
[1]
SD1_TX
[1]
SD1_TX
[3]
SD1_TX
[4]
SD1_TX
[6]
PCI1_
GV
DD
BV
XV
DD
XV
DD
GND
DD
XGND
XGND
Rsvd
Rsvd
XGND
GND
TRST
GND
TSTCLK PERR DEVSEL
SEE DETAIL C
SEE DETAIL D
PCI1_
C_BE
[1]
LWE0/
LBS0/
LFWE
MDQS
[1]
MDQ
[2]
MDQ
[6]
LAD
[29]
LAD
[30]
LWE[1]/
LBS[1]
LAD
[0]
LAD
[2]
PCI1_
PAR
PCI1_
SERR
IIC1_
SDA
IRQ
[6]
IRQ
[8]
IRQ
[0]
MDQS
[1]
SD1_TX
[0]
SD1_TX
[2]
SD1_TX
XV
SD1_TX
[7]
GV
DD
XV
DD
OV
DD
XGND
XGND
DD
[5]
PCI1_
AD
PCI1_
AD
PCI1_
AD
PCI1_
AD
MDQ
[9]
MDM
[1]
MDQS
[0]
LAD
[27]
LAD
[28]
LWE[2]/
LBS[2]
SD1_TX
[0]
SD1_TX
[2]
SD1_TX
XGND
SD1_TX
[7]
IRQ
[2]
LAD
[3]
BV
DD
BV
DD
BV
DD
XV
DD
XV
DD
XV
DD
GND
XGND
GND
GND
[5]
[13]
[14]
[15]
[11]
PCI1_
AD
[5]
PCI1_
AD
[7]
PCI1_
AD
[9]
PCI1_
AD
[10]
PCI1_
AD
[12]
MDQ
[8]
MDQ
[13]
MDQS
[0]
LAD
[24]
LAD
[23]
LAD
[26]
LCLK
[0]
LCLK
[1]
LAD
[4]
LAD
[5]
GV
DD
SV
DD
SV
DD
SV
DD
SV
DD
OV
DD
XGND
NC
NC
SGND
SGND SGND
SGND
SGND
PCI1_
C_BE
[0]
PCI1_
AD
PCI1_
AD
PCI1_
AD
MDQ
[12]
MDQ
[5]
MDM
[0]
MDQ
[4]
LCLK
[2]
LAD
[7]
LAD
[6]
LDP
[3]
LAD
[19]
LSSD_
MODE
SD1_RX
[1]
SD1_RX
[3]
SD1_RX
[4]
SD1_RX
[6]
SV
DD
SV
DD
SV
DD
OV
DD
SGND
NC
GND
LBCTL
LALE
GND
SGND
[1]
[4]
[8]
SD1_
IMP_CAL
_RX
SD1_
PLL_
TPA
PCI1_
AD
[0]
PCI1_
AD
[2]
PCI1_
AD
[3]
MDQ
[0]
MDQ
[1]
PCI1_
CLK
LAD
[25]
LAD
[22]
LAD
[18]
LAD
[16]
SD1_RX
[1]
SD1_RX
[3]
SD1_RX
[4]
SD1_RX
[6]
LDP
[0]
POWER_
OK
BV
DD
SV
DD
SV
DD
GND
GND
SGND
SGND
SGND
GND
SD1_
REF_
CLK
PCI1_
AD
LDP
[2]
LAD
[21]
LAD
[15]
LAD
[14]
LAD
[11]
LAD
[9]
AGND_
SRDS
SD1_RX
[0]
SD1_RX
[2]
SD1_RX
[5]
SD1_RX
[7]
POWER_
EN
LSYNC_
IN
OV
DD
SV
DD
SV
DD
SV
DD
GND
GND
GND
SV
DD
SGND
NC
SGND
TMS
[6]
SD1_
REF_
CLK
SD1_
PLL_
TPD
SD1_
AVDD_
SRDS
AVDD_ LSYNC_ LAD
[20]
LAD
[17]
LAD
[13]
LAD
[12]
LAD
[10]
LAD
[8]
SD1_RX
[0]
SD1_RX
[2]
SD1_RX
[5]
SD1_RX
[7]
LDP
[1]
SV
DD
SV
DD
MVREF
A
GND
B
SGND
M
SGND
T
SGND
Y
SGND IMP_CAL TDO
_TX
TCK
AG
TDI
LBIU
OUT
C
D
E
F
G
H
J
K
L
N
P
R
U
V
W
AA
AB
AC
AD
AE
AF
AH
Figure 2. MPC8536E Pin Map Bottom View
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
4
Pin Map
A
B
C
D
E
F
G
H
J
K
L
M
N
P
MDQ
[32]
MDQ
[46]
MDQ
[47]
MDQ
[34]
MDQ
[56]
MDQ
[57]
MDQS
[7]
MDQ
[58]
MDQS
[5]
GV
DD
GV
DD
GND
GND
1
2
MDQ
[42]
MDQ
[35]
MDQ
[44]
MDQ
[40]
MDM
[5]
MDQS
[5]
MDQ
[43]
MDQ
[60]
MDQ
[61]
MDM
[7]
MDM
[62]
MDQS
[7]
GV
DD
GND
MDQ
[38]
MDM
[6]
MDQ
[50]
MDQ
[51]
MDQ
[45]
MDQ
[41]
MCS
[0]
MDQ
[33]
MDQ
[52]
MDQS
[6]
GV
DD
GV
DD
GND
GND
3
MBA
[0]
MDQ
[36]
MDM
[4]
MDQ
[39]
MDQ
[53]
MDQ
[49]
MDQ
[54]
MDQ
[55]
MCS
[2]
MDQS
[6]
GV
DD
MWE
GND
GND
4
MA
[10]
MBA
[1]
MODT
[0]
MDQ
[37]
MDQS
[4]
MDQ
[48]
MDQS
[4]
GV
DD
GV
DD
GV
DD
MRAS
GND
GND
GND
GND
5
SD2_
IMP_CAL
_TX
SD2_
REF_
CLK
MODT
[2]
MODT
[3]
MCK
[2]
SD2_RX
[0]
MCS
[3]
MCS
[1]
MCK
[2]
MAPAR_
OUT
GV
DD
NC
S2GND
6
SD2_
REF_
CLK
SD2_
PLL_
TPD
MA
[0]
MA
MODT
[1]
SD2_RX
[0]
GV
DD
GV
DD
MCAS
GND
GND
NC
GND
NC
S2V
DD
7
NC
[13]
MCK
[3]
MCK
[3]
MA
[2]
MA
[1]
MCK
[5]
MCK
[5]
SD2_RX
[1]
GV
DD
GND
GND
Rsvd
Rsvd
NC
S2GND
S2GND
S2GND
NC
8
MCK
[0]
MCK
[0]
MA
[4]
MA
[8]
MA
[7]
MCKE
[3]
SD2_RX
[1]
GV
DD
GV
DD
NC
S2V
DD
9
MA
[3]
MA
[5]
MA
[14]
MA
[15]
MCKE
[2]
MCKE
[0]
MCKE
[1]
GV
DD
GND
NC
X2GND
NC
10
11
12
13
14
MA
[6]
MECC
[3]
MA
MECC
[2]
MCK
[1]
MCK
[1]
SD2_TX
[1]
SD2_TX
[0]
GV
DD
GV
DD
GV
DD
GND
X2V
DD
X2GND
[12]
MA
[11]
MA
[9]
MECC
[7]
MECC
[0]
SD2_TX
[1]
SD2_TX
[0]
GV
DD
GV
DD
X2V
DD
GND
GND
GND
X2GND
GND
NC
MBA
[2]
MECC
[6]
VDD_
CORE
VDD_
CORE
VDD_
CORE
MDQS
[8]
MDM
[8]
MCK
[4]
MDQS
[8]
MCK
[4]
MAPAR_
ERR
GND
GND
MDQ
[27]
MECC
[1]
MECC
[5]
MECC
[4]
VDD_
CORE
VDD_
CORE
GV
DD
GV
DD
GV
DD
GV
DD
GND
GND
GND
GND
DETAIL A
Figure 3. MPC8536E Pin Map Detail A
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
5
Pin Map
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
TSEC3_
RXD
[3]
TSEC1_
RXD
[1]
AVDD_
SRDS2
MDQ
[59]
TSEC3_
RX_CLK
TSEC1_
TX_EN
TSEC1_
RX_DV
USB1_
CLK
USB1_
STP
USB1_
DIR
USB1_D USB1_D
[0] [2]
USB1_D USB1_D
1
[5]
[7]
USB1_
PWR-
FAULT
TSEC3_
RXD
[1]
TSEC1_ TSEC1_
AGND_
SRDS2
TSEC1_
GTX_CLK
MDQ
[63]
TSEC3_
RX_DV
USB1_
NXT
USB1_D USB1_D USB1_D USB1_D
OV
DD
2
RXD
RXD
[1]
[3]
[4]
[6]
[0]
[3]
USB1_
PCTL0/
GPIO[6]
SD2_
PLL_
TPA
TSEC3_ TSEC3_ TSEC1_ TSEC1_
TSEC1_
RXD
[7]
TSEC1_
RX_CLK
USB2_D USB2_D
[0] [1]
USB3_D USB3_D
[1] [0]
GV
DD
GND
3
RXD
RXD
TXD
RXD
[2]
[0]
[3]
[2]
USB1_
PCTL1/
GPIO[7]
TSEC1_
TXD
[1]
Rvsd
TSEC3_
RX_ER
TSEC1_
TX_CLK
USB2_D USB2_D USB3_D USB3_D
[2] [3] [3] [2]
TV
LV
OV
DD
GND
GND
4
DD
DD
TSEC3_
TXD
[1]
TSEC1_ TSEC1_ TSEC1_
TSEC3_
GTX_CLK
TSEC3_
TX_EN
TSEC1_
TX_ER
USB2_ USB2_D USB2_D USB3_D USB3_
GND
5
TXD
TXD
TXD
Rvsd
CLK
[4]
[5]
[4]
CLK
[2]
[4]
[6]
DMA_
DACK[0]/
GPIO[10]
TSEC3_ TSEC3_ TSEC3_ TSEC1_ TSEC1_
TSEC1_
COL
EC_GTX_
CLK125
USB2_D
[6]
USB2_D
[7]
USB3_D USB3_D
[6] [5]
S2V
DD
OV
DD
6
TXD
RXD
RXD
TXD
RXD
[0]
[5]
[4]
[0]
[4]
TSEC_
1588_TRIG
_IN[1]
SD2_
IMP_CAL
_RX
TSEC3_
TXD
[2]
TSEC1_
RXD
[6]
USB2_
NXT
USB2_
STP
USB2_
DIR
USB3_ USB3_D
TV
LV
GND
GND
GND
7
DD
DD
NXT
[7]
SDHC_
DAT[4]/SPI
_CS[0]
TSEC_
1588_TRIG
_IN[0]
USB2_
PWR-
FAULT
TSEC1_ TSEC1_ TSEC1_
TSEC3_ TSEC3_ TSEC3_
SPI_
CLK
SPI_
MOSI
USB3_
DIR
USB3_
STP
NC
NC
NC
8
TXD
TXD
RXD
TXD
TXD
TXD
[5]
[7]
[5]
[3]
[5]
[6]
SDHC_
DAT[6]/SPI
_CS[2]
USB2_
PCTL1/
GPIO[9]
USB2_
PCTL0/
GPIO[8]
TSEC_
1588_
CLK
TSEC3_
TXD
[4]
SPI_
MISO
TSEC3_ TSEC3_
COL TX_ER
TSEC1_ TSEC1_
GND
Rsvd
GND
9
RX_ER
CRS
TSEC_
1588_TRIG
_OUT[1]
SDHC_
DAT[7]/SPI
_CS[3]
SDHC_
DAT[5]/SPI
_CS[1]
TSEC_
1588_CLK
_OUT
DMA_
DREQ[0]/
GPIO[14]
DMA_
DACK[1]/
GPIO[11]
SDHC_
WP/GPIO
[5]
UART_
SOUT
[0]
EC_
MDC
TSEC3_ TSEC3_
SDHC_
CMD
OV
DD
10
11
12
13
14
CRS
TX_CLK
TSEC_
TSEC_
TSEC_
DMA_
DDONE[0]/ DDONE[1]/
GPIO[12]
DMA_
DMA_
DREQ[1]/
GPIO[15]
SDHC_
CD/GPIO
[4]
UART_
CTS
[0]
SDHC_
DAT
[3]
EC_
MDIO
MSRCID
[4]
1588_PULSE 1588_TRIG 1588_PULSE
OV
DD
X2V
DD
GND
GPIO[13]
_OUT[0]
_OUT2
_OUT1
UART_
CTS
[1]
UART_
RTS
[0]
UART_
RTS
[1]
UART_
SOUT
[1]
UART_
SIN
[0]
UART_
SIN
[1]
SDHC_ SDHC_
DAT
[0]
TSEC3_ TSEC3_
MSRCID MSRCID
X2GND
GND
GND
DAT
[1]
TXD
[7]
RXD
[7]
[2]
[0]
IRQ[9]/
DMA_
DREQ[2]
IRQ[10]/
DMA_
DACK[2]
PCI1_
REQ
[2]
SDHC_
DAT
[2]
TSEC3_
RXD
[6]
TEST_
SEL
VDD_
CORE
SDHC_
CLK
MSRCID
[1]
MDVAL
GND
MCP
DDRCLK
OV
DD
IRQ[11]/
DMA_
DDONE[2]
PCI1_
GNT
[2]
PCI1_GNT
[4]/GPIO
[3]
IIC2_
SDA
VDD_
CORE
VDD_
CORE
MSRCID
[3]
OV
DD
GND
GND
GND
SYSCLK
UDE
DETAIL B
Figure 4. MPC8536E Pin Map Detail B
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
6
Pin Map
DETAIL C
MDQ
[26]
MDIC
MDIC
[1]
VDD_
CORE
VDD_
CORE
MDQ
[31]
GV
DD
GV
DD
GND
GND
GND
[0]
GND
GND
GND
15
16
17
18
19
20
21
22
23
24
25
26
27
28
LCS5/
DMA_
DREQ2
LCS6/
DMA_
DACK2
VDD_
CORE
VDD_
CORE
MDQ
[30]
MDQS
[3]
MDQ
[19]
MDQ
[23]
MDQ
[18]
LA
[28]
LCS
[4]
GND
GND
GND
MDM
[3]
VDD_
PLAT
VDD_
PLAT
MDQS
[2]
MDQ
[22]
LA
[31]
LA
[30]
LA
[29]
MDQS
[3]
GV
DD
GND
GND
GND
GND
LCS7/
DMA_
DDONE2
MDQ
[25]
MDQ
[24]
MDM
[2]
MDQ
[21]
VDD_
PLAT
MDQS
[2]
LCS
[0]
LGPL3/
LFWP
GV
DD
BV
DD
GND
GND
GND
VDD_
PLAT
VDD_
PLAT
MDQ
[29]
MDQ
[28]
MDQ
[17]
MDQ
[16]
MDQ
[20]
LA
[27]
LCS
[1]
LCS
[2]
BV
DD
NC
LGPL5
GND
LGPL4/
LGPL2/
LOE/
LFRE
LGTA/
LUPWAIT/
LPBSE/
LFRB
MDQ
[11]
MDQ
[10]
LGPL0/ LGPL1/
LCS
[3]
SD1_TX
[1]
GV
DD
BV
DD
XV
DD
GND
GND
XGND
LFCLE
LFALE
MDQ
[15]
MDQ
[14]
MDQ
[3]
MDQ
[7]
LAD
[31]
LAD
[1]
LWE[3]/
LBS[3]
SD1_TX
[1]
GV
DD
BV
DD
XV
DD
GND
XGND
GND
LWE0/
LBS0/
LFWE
MDQS
[1]
MDQ
[2]
MDQ
[6]
LAD
[29]
LAD
[30]
LWE[1]/
LBS[1]
LAD
[0]
LAD
[2]
MDQS
[1]
SD1_TX
[0]
SD1_TX
[2]
GV
DD
XGND
MDQ
[9]
MDM
[1]
MDQS
[0]
LAD
[27]
LAD
[28]
LWE[2]/
LBS[2]
SD1_TX
[0]
SD1_TX
[2]
LAD
[3]
BV
DD
BV
DD
BV
DD
XV
DD
GND
MDQ
[8]
MDQ
[13]
MDQS
[0]
LAD
[24]
LAD
[23]
LAD
[26]
LCLK
[0]
LCLK
[1]
LAD
[4]
LAD
[5]
GV
DD
XGND
NC
NC
SGND
MDQ
[12]
MDQ
[5]
MDM
[0]
MDQ
[4]
LCLK
[2]
LAD
[7]
LAD
[6]
LDP
[3]
LAD
[19]
SD1_RX
[1]
SV
DD
LBCTL
LALE
GND
GND
SD1_
IMP_CAL
_RX
MDQ
[0]
MDQ
[1]
LAD
[25]
LAD
[22]
LAD
[18]
LAD
[16]
SD1_RX
[1]
LDP
[0]
BV
DD
GND
GND
SGND
LDP
[2]
LAD
[21]
LAD
[15]
LAD
[14]
LAD
[11]
LAD
[9]
SD1_RX
[0]
LSYNC_
IN
SGND
SV
DD
GND
GND
GND
AVDD_ LSYNC_
LAD
[20]
LAD
[17]
LAD
[13]
LAD
[12]
LAD
[10]
LAD
[8]
SD1_RX
[0]
LDP
[1]
SV
DD
MVREF
A
GND
B
SGND
M
LBIU
OUT
C
D
E
F
G
H
J
K
L
N
P
Figure 5. MPC8536E Pin Map Detail C
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
7
Pin Map
DETAIL D
SENSE-
VDD_
CORE
PCI1_
AD
PCI1_
AD
PCI1_REQ PCI1_GNT
CLK_
OUT
PCI1_REQ
[4]/GPIO
[1]
IIC2_
SCL
VDD_
CORE
HRESET_
REQ
GND
GND
GND
RTC
15
16
17
18
19
20
21
22
23
24
25
26
27
28
[3]/GPIO
[0]
[3]/GPIO
[2]
[31]
[28]
PCI1_
REQ
[1]
PCI1_
PCI1_
PCI1_
AD
[26]
PCI1_
IDSEL
VDD_
CORE
VDD_
CORE
IRQ
[5]
AVDD_
CORE
SENSE-
VSS
OV
DD
OV
DD
GND
HRESET
GNT
[1]
REQ
[0]
SENSE-
VDD_
PLAT
PCI1_
AD
[30]
PCI1_
AD
[29]
PCI1_
AD
[27]
PCI1_
AD
[24]
PCI1_
AD
[23]
VDD_
PLAT
VDD_
PLAT
IRQ_
OUT
IRQ
[1]
IRQ
[4]
CKSTP_
OUT
GND
GND
PCI1_
C_BE
[3]
PCI1_
GNT
[0]
PCI1_
AD
[20]
PCI1_
AD
[18]
PCI1_
AD
[25]
PCI1_
AD
[22]
VDD_
PLAT
VDD_
PLAT
AVDD_
PLAT
CKSTP_
IN
OV
DD
OV
DD
GND
GND
TRIG_
OUT/READY
/QUIESCE
PCI1_
AD
[21]
PCI1_
AD
[19]
PCI1_
AD
[17]
VDD_
PLAT
AVDD_
DDR
IRQ
[7]
IRQ
[3]
GND
GND
GND
GND
SRESET
ASLEEP
TRIG_IN
PCI1_
C_BE
[2]
PCI1_
AD
[16]
L2_
PCI1_
AVDD_
PCI1
PCI1_
IRDY
SD1_TX
[3]
SD1_TX
[4]
SD1_TX
[6]
XV
DD
XV
DD
OV
DD
XGND
TSTCLK
FRAME
L1_
PCI1_
DEVSEL
PCI1_
STOP
PCI1_
TRDY
IIC1_
SCL
PCI1_
PERR
SD1_TX
[3]
SD1_TX
[4]
SD1_TX
[6]
XV
DD
GND
TRST
XGND
Rsvd
Rsvd
XGND
TSTCLK
PCI1_
C_BE
[1]
IIC1_
SDA
PCI1_
SERR
PCI1_
PAR
IRQ
[6]
IRQ
[8]
IRQ
[0]
SD1_TX
[5]
SD1_TX
[7]
XV
DD
XV
DD
OV
DD
XGND
PCI1_
AD
[13]
PCI1_
AD
[14]
PCI1_
AD
[15]
PCI1_
AD
[11]
SD1_TX
[5]
SD1_TX
[7]
IRQ
[2]
XV
DD
XV
DD
XGND
XGND
GND
GND
PCI1_
AD
[5]
PCI1_
AD
[7]
PCI1_
AD
[9]
PCI1_
AD
[10]
PCI1_
AD
[12]
SV
DD
SV
DD
SV
DD
SV
DD
OV
DD
SGND
SGND
NC
SGND
SGND
PCI1_
C_BE
[0]
PCI1_
AD
[1]
PCI1_
AD
[4]
PCI1_
AD
[8]
LSSD_
MODE
SD1_RX
[3]
SD1_RX
[4]
SD1_RX
[6]
SV
DD
SV
DD
OV
DD
SGND
SGND
SD1_
PLL_
TPA
PCI1_
AD
[0]
PCI1_
AD
[2]
PCI1_
AD
[3]
PCI1_
CLK
SD1_RX
[3]
SD1_RX
[4]
SD1_RX
[6]
POWER_
OK
SV
DD
SV
DD
SGND
SGND
GND
SD1_
REF_
CLK
PCI1_
AD
[6]
AGND_
SRDS
SD1_RX
[2]
SD1_RX
[5]
SD1_RX
[7]
POWER_
EN
OV
DD
SV
DD
SV
DD
SV
DD
TMS
NC
SGND
SD1_
REF_
CLK
SD1_
PLL_
TPD
SD1_
SGND IMP_CAL
_TX
AVDD_
SRDS
SD1_RX
[2]
SD1_RX
[5]
SD1_RX
[7]
SV
DD
TDO
AF
TCK
AG
TDI
AH
SGND
T
SGND
Y
R
U
V
W
AA
AB
AC
AD
AE
Figure 6. MPC8536E Pin Map Detail D
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
8
Pin Map
Table 1 provides the pin-out listing for the MPC8536E 783 FC-PBGA package.
Table 1. MPC8536E Pinout Listing
Power
Supply
Signal
Signal Name
Package Pin Number Pin Type
Notes
PCI
AB15,Y17,AA17,AC15,
PCI1_AD[31:0]
Muxed Address / data
I/O
OV
—
DD
AB17,AC16,AA18,
AD17,AE17,AB18,
AB19,AE18,AC19,
AF18,AE19,AC20,
AF23,AE23,AC23,
AH24,AH23,AG24,
AE24,AG25,AD24,
AG27,AC24,AF25,
AG26,AF26,AE25,
AD26
PCI1_C_BE[3:0]
Command/Byte Enable
AD18, AD20,AD22,
AH25
I/O
OV
29
DD
PCI1_PAR
Parity
AC22
I/O
I/O
I/O
I/O
I/O
I/O
I
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
29
2,29
2,29
2,29
2,29
2,29
29
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
PCI1_FRAME
PCI1_TRDY
Frame
AE20
Target Ready
Initiator Ready
Stop
AF21
PCI1_IRDY
AB20
PCI1_STOP
AD21
PCI1_DEVSEL
PCI1_IDSEL
Device Select
Init Device Select
Parity Error
System Error
Request
AC21
AE16
PCI1_PERR
AB21
I/O
I/O
I
2,29
2,4,29
—
PCI1_SERR
AF22
PCI1_REQ[4:3]/GPIO[1:0]
PCI1_REQ[2:1]
PCI1_REQ[0]
PCI1_GNT[4:3]/GPIO[3:2]
PCI1_GNT[2:1]
PCI1_GNT[0]
PCI1_CLK
AE15,Y15
AF13,W16
AA16
Request
I
29
Request
I/O
O
29
Grant
AC14, AA15
AF14,Y16
W18
Grant
O
5,9,25,29
Grant
I/O
I
29
29
PCI Clock
AH26
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
9
Pin Map
Table 1. MPC8536E Pinout Listing (continued)
Signal Name Package Pin Number Pin Type
Power
Supply
Signal
Notes
DDR SDRAM Memory Interface
A26,B26,C22,D21,D25,
MDQ[0:63]
Data
I/O
GV
—
DD
B25,D22,E21,A24,A23,
B20,A20,A25,B24,B21,
A21,E19,D19,E16,C16,
F19,F18,F17,D16,B18,
A18,A15,B14,B19,A19,
A16,B15,D1,F3,G1,H2,
E4,G5,H3,J4,B2,C3,F2,
G2,A2,B3,E1,F1,L5,L4,
N3,P3,J3,K4,N4,P4,J1,
K1,P1,R1,J2,K2,P2,R2
MECC[0:7]
Error Correcting Code
G12,D14,F11,C11,
G14,F14,C13,D12
I/O
GV
—
DD
MAPAR_ERR
MAPAR_OUT
MDM[0:8]
Address Parity Error
Address Parity Out
Data Mask
A13
A6
I
GV
GV
GV
—
—
—
DD
DD
DD
O
O
C25,B23,D18,B17,G4,
C2,L3,L2,F13
MDQS[0:8]
MDQS[0:8]
MA[0:15]
Data Strobe
Data Strobe
Address
D24,B22,C18,A17,J5,
C1,M4,M2,E13
I/O
I/O
O
GV
GV
GV
—
—
—
DD
DD
DD
C23,A22,E17,B16,K5,
D2,M3,N1,D13
B7,G8,C8,A10,D9,C10,
A11,F9,E9,B12,A5,
A12,D11,F7,E10,F10
MBA[0:2]
MWE
Bank Select
A4,B5,B13
O
O
O
O
O
O
O
GV
GV
GV
GV
GV
GV
GV
—
—
—
—
—
11
—
DD
DD
DD
DD
DD
DD
DD
Write Enable
B4
MRAS
Row Address Strobe
Column Address Strobe
Chip Select
C5
MCAS
E7
MCS[0:3]
MCKE[0:3]
MCK[0:5]
D3,H6,C4,G6
H10,K10,G10,H9
A9,J11,J6,A8,J13,H8
Clock Enable
Differential Clock 3 Pairs /
DIMM
MCK[0:5]
Differential Clock 3 Pairs /
DIMM
B9,H11,K6,B8,H13,J8
O
GV
—
DD
MODT[0:3]
MDIC[0:1]
On Die Termination
Calibration
E5,H7,E6,F6
H15,K15
O
GV
GV
—
26
DD
DD
I/O
Local Bus Controller Interface
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
10
Pin Map
Table 1. MPC8536E Pinout Listing (continued)
Power
Supply
Signal
Signal Name
Package Pin Number Pin Type
Notes
LAD[0:31]
Muxed data / address
K22,L21,L22,K23,K24,
L24,L25,K25,L28,L27,
K28,K27,J28,H28,H27,
G27,G26,F28,F26,F25,
E28,E27,E26,F24,E24,
C26,G24,E23,G23,F22,
G22,G21
I/O
BV
5,9,29
DD
LDP[0:3]
LA[27]
Data parity
K26,G28,B27,E25
L19
I/O
O
BV
BV
BV
BV
BV
BV
BV
BV
BV
BV
BV
BV
29
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
Burst address
Port address
Chip selects
5,9,29
5,7,9,29
29
LA[28:31]
LCS[0:4]
K16,K17,H17,G17
K18,G19,H19,H20,G16
O
O
LCS5/DMA_DREQ2
LCS6/DMA_DACK2
LCS7/DMA_DDONE2
LWE0/LBS0/LFWE
LWE[1:3]/LBS[1:3]
LBCTL
Chips selects / DMA Request H16
I/O
O
1,29
Chips selects / DMA Ack
Chips selects / DMA Done
Write enable / Byte select
Write enable / Byte select
Buffer control
J16
1,29
L18
O
1,29
J22
O
5,9,29
5,9,29
5,8,9,29
5,8,9,29
5,9,29
H22,H23,H21
O
J25
J26
O
LALE
Address latch enable
O
LGPL0/LFCLE
UPM general purpose line 0 / J20
FLash command latch enable
O
LGPL1/LFALE
UPM general purpose line 1 / K20
Flash address latch enable
O
O
BV
BV
5,9,29
DD
DD
LGPL2/LOE/LFRE
UPM general purpose line 2 / G20
Output enable/Flash read
enable
5,8,9,29
LGPL3/LFWP
UPM general purpose line 3 / H18
Flash write protect
O
BV
BV
5,9,29
29
DD
DD
LGPL4/LGTA/LUPWAIT
/LPBSE/LFRB
UPM general purpose line 4 / L20
Target Ack/Wait/SDRAM
parity byte select/Flash
Ready-busy
I/O
LGPL5
UPM general purpose line 5 / K19
Amux
O
BV
5,9,29
DD
LCLK[0:2]
Local bus clock
Synchronization
Local bus DLL
H24,J24,H25
O
I
BV
BV
BV
29
29
29
DD
DD
DD
LSYNC_IN
LSYNC_OUT
D27
D28
O
DMA
AD6,AE10
DMA_DACK[0:1]
/GPIO[10:11]
DMA Acknowledge
O
OV
—
DD
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
11
Pin Map
Table 1. MPC8536E Pinout Listing (continued)
Signal Name Package Pin Number Pin Type
DMA Request
Power
Supply
Signal
Notes
DMA_DREQ[0:1]
/GPIO[14:15]
AB10,AD11
AA11,AB11
I
OV
—
DD
DMA_DDONE[0:1]
/GPIO[12:13]
DMA Done
O
OV
—
DD
DMA_DREQ[2]/LCS[5]
DMA_DACK[2]/LCS[6]
DMA_DDONE[2]/LCS[7]
DMA_DREQ[3]/IRQ[9]
Chips selects / DMA Request H16
I/O
O
O
I
BV
BV
BV
OV
1,29
1,29
1,29
1
DD
DD
DD
DD
Chips selects / DMA Ack
Chips selects / DMA Done
J16
L18
External interrupt/DMA
request
AE13
DMA_DACK[3]/IRQ[10]
DMA_DDONE[3]/IRQ[11]
External interrupt/DMA Ack
AD13
I/O
I/O
OV
OV
1
1
DD
DD
External interrupt/DMA done AD14
USB Port 1
USB1_D[7:0]
USB1 Data bits
AF1,AE2,AE1,AD2,
I/O
OV
—
DD
AC2,AC1,AB2,AB1
USB1_NXT
USB1 Next data
AF2
AH1
AG1
AH2
AC3
AC4
AD1
I
I
OV
OV
OV
OV
OV
OV
OV
—
—
5,9
—
—
—
—
DD
DD
DD
DD
DD
DD
DD
USB1_DIR
USB1 Data Direction
USB1 Stop
USB1_STP
O
I
USB1_PWRFAULT
USB1_PCTL0/GPIO[6]
USB1_PCTL1/GPIO[7]
USB1_CLK
USB1 bus power fault.
USB1 Port control 0
USB1 Port control 1
USB1 bus clock
O
O
I
USB Port 2
USB2_D[7:0]
USB2 Data bits
AE6,AC6,AF5,AE5,
AF4,AE4,AE3,AD3
I/O
OV
—
DD
USB2_NXT
USB2 Next data
AC7
AF7
AD7
AC8
AG9
AC9
AD5
I
I
OV
OV
OV
OV
OV
OV
OV
—
—
5,9
—
—
—
—
DD
DD
DD
DD
DD
DD
DD
USB2_DIR
USB2 Data Direction
USB2 Stop
USB2_STP
O
I
USB2_PWRFAULT
USB2_PCTL0/GPIO[8]
USB2_PCTL1/GPIO[9]
USB2_CLK
USB2 bus power fault.
USB2 Port control 0
USB2 Port control 1
USB2 bus clock
O
O
I
USB Port 3
USB3_D[7:0]
USB3_NXT
USB3 Data bits
USB3 Next data
AH7,AG6,AH6,AG5,
AG4,AH4,AG3,AH3
I/O
I
OV
OV
—
—
DD
DD
AG7
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
12
Pin Map
Notes
Table 1. MPC8536E Pinout Listing (continued)
Power
Supply
Signal
Signal Name
Package Pin Number Pin Type
USB3_DIR
USB3_STP
Reserved
USB3 Data Direction
USB3 Stop
AG8
AH8
AH9
AH5
I
O
—
I
OV
OV
—
—
27
—
DD
DD
—
—
USB3_CLK
USB3 bus clock
OV
DD
Programmable Interrupt Controller
MCP
Machine check processor
Y14
I
I
I
OV
OV
OV
—
—
—
DD
DD
DD
UDE
Unconditional debug event
External interrupts
AB14
IRQ[0:8]
AG22,AF17,AB23,
AF19,AG17,AF16,
AA22,Y19,AB22
IRQ[9]/DMA_DREQ[3]
External interrupt/DMA
request
AE13
I
OV
1
DD
IRQ[10]/DMA_DACK[3]
IRQ[11]/DMA_DDONE[3]
IRQ_OUT
External interrupt/DMA Ack
AD13
I/O
I/O
O
OV
OV
OV
1
1
DD
DD
DD
External interrupt/DMA done AD14
Interrupt output AC17
Ethernet Management Interface
2,4
EC_MDC
EC_MDIO
Management data clock
Management data In/Out
Y10
Y11
O
OV
OV
5,9,22
—
DD
DD
I/O
Gigabit Reference Clock
EC_GTX_CLK125
TSEC1_TXD[7:0]
Reference clock
AA6
I
LV
LV
31
DD
DD
Three-Speed Ethernet Controller (Gigabit Ethernet 1)
Transmit data
AA8,AA5,Y8,Y5,W3,
W5,W4,W6
O
5,9,22
TSEC1_TX_EN
TSEC1_TX_ER
TSEC1_TX_CLK
TSEC1_GTX_CLK
TSEC1_CRS
Transmit Enable
Transmit Error
Transmit clock In
Transmit clock Out
Carrier sense
W1
O
O
I
LV
LV
LV
LV
LV
LV
LV
23
5,9
—
DD
DD
DD
DD
DD
DD
DD
AB5
AB4
W2
O
I/O
I
—
AA9
AB6
17
—
TSEC1_COL
Collision detect
Receive data
TSEC1_RXD[7:0]
AB3,AB7,AB8,Y6,AA2,
Y3,Y1,Y2
I
—
TSEC1_RX_DV
TSEC1_RX_ER
TSEC1_RX_CLK
Receive data valid
Receive data error
Receive clock
AA1
Y9
I
I
I
LV
LV
LV
—
—
—
DD
DD
DD
AA3
Three-Speed Ethernet Controller (Gigabit Ethernet 3)
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
13
Pin Map
Table 1. MPC8536E Pinout Listing (continued)
Signal Name Package Pin Number Pin Type
Transmit data
Power
Supply
Signal
Notes
TSEC3_TXD[7:0]
T12,V8,U8,V9,T8,T7,
T5,T6
O
LV
5,9,22
DD
TSEC3_TX_EN
TSEC3_TX_ER
TSEC3_TX_CLK
TSEC3_GTX_CLK
TSEC3_CRS
Transmit Enable
Transmit Error
Transmit clock In
Transmit clock Out
Carrier sense
V5
O
O
I
LV
LV
LV
LV
LV
LV
LV
23
5,9
—
DD
DD
DD
DD
DD
DD
DD
U9
U10
U5
O
I/O
I
—
T10
T9
17
—
TSEC3_COL
Collision detect
Receive data
TSEC3_RXD[7:0]
U12,U13,U6,V6,V1,U3,
U2,V3
I
—
TSEC3_RX_DV
TSEC3_RX_ER
TSEC3_RX_CLK
Receive data valid
Receive data error
Receive clock
V2
T4
U1
I
I
I
LV
LV
LV
—
—
—
DD
DD
DD
IEEE 1588
TSEC_1588_CLK
Clock In
W9
I
LV
LV
LV
LV
LV
LV
29
DD
DD
DD
DD
DD
DD
TSEC_1588_TRIG_IN[0:1]
Trigger In
W8,W7
U11,W10
V10
I
29
TSEC_1588_TRIG_OUT[0:1] Trigger Out
TSEC_1588_CLK_OUT Clock Out
O
O
O
O
5,9,29
5,9,29
5,9,29
5,9,29
TSEC_1588_PULSE_OUT1 Pulse Out1
TSEC_1588_PULSE_OUT2 Pulse Out2
V11
T11
eSDHC
SDHC_CMD
Command line
Card detection
Data line
AH10
AH11
I/O
I
OV
OV
OV
29
—
29
DD
DD
DD
SDHC_CD/GPIO[4]
SDHC_DAT[0:3]
AG12,AH12,AH13,
AG11
I/O
SDHC_DAT[4:7] /
SPI_CS[0:3]
8-bit MMC Data line / SPI chip AE8,AC10,AF9,AA10
select
I/O
OV
29
DD
SDHC_CLK
SD/MMC/SDIO clock
Card write protection
AG13
AG10
I/O
I
OV
OV
29
DD
DD
SDHC_WP/GPIO[5]
1, 32
eSPI
SPI_MOSI
SPI_MISO
SPI_CLK
Master Out Slave In
Master In Slave Out
eSPI clock
AF8
AD9
AD8
I/O
I
OV
OV
OV
OV
29
29
29
29
DD
DD
DD
DD
I/O
I/O
SPI_CS[0:3] /
SDHC_DAT[4:7]
eSPI chip select / SDHC 8-bit AE8,AC10,AF9,AA10
MMC data
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
14
Pin Map
Notes
Table 1. MPC8536E Pinout Listing (continued)
Signal Name Package Pin Number Pin Type
Power
Supply
Signal
DUART
AE11,Y12
UART_CTS[0:1]
Clear to send
I
O
I
OV
OV
OV
OV
29
29
29
DD
DD
DD
DD
UART_RTS[0:1]
UART_SIN[0:1]
UART_SOUT[0:1]
Ready to send
Receive data
Transmit data
AB12,AD12
AC12,AF12
AF10,AA12
O
5,9,22,
10,29
2
I C interface
IIC1_SCL
IIC1_SDA
IIC2_SCL
IIC2_SDA
Serial clock
Serial data
Serial clock
Serial data
AG21
AH22
AH15
AG14
I/O
I/O
I/O
I/O
OV
OV
OV
OV
4,21,29
4,21,29
4,21,29
4,21,29
DD
DD
DD
DD
SerDes1(x8)
SD1_TX[7:0]
SD1_TX[7:0]
SD1_RX[7:0]
SD1_RX[7:0]
Transmit Data (+)
Transmit Data(-)
Receive Data(+)
Receive Data(–)
Y23,W21,V23,U21,
R21,P23,N21,M23
O
O
I
XV
XV
XV
XV
—
—
—
—
DD
DD
DD
DD
Y22,W20,V22,U20,
R20,P22,N20,M22
AC28,AB26,AA28,Y26,
T26,R28,P26,N28
AC27,AB25,AA27,Y25,
T25,R27,P25,N27
I
SD1_PLL_TPD
SD1_REF_CLK
SD1_REF_CLK
PLL test point Digital
PLL Reference clock
V28
U28
U27
O
I
XV
XV
XV
18
—
—
DD
DD
DD
PLL Reference clock
complement
I
Reserved
Reserved
—
—
T22
T23
—
—
—
18
18
—
SerDes2(x2)
SD2_TX[1:0]
SD2_TX[1:0]
SD2_RX[1:0]
SD2_RX[1:0]
SD2_PLL_TPD
SD2_REF_CLK
SD2_REF_CLK
Transmit data(+)
Transmit data(-)
M11, P11
M12, P12
N8, P6
N9, P7
L7
O
O
I
X2V
X2V
X2V
X2V
X2V
X2V
X2V
—
—
—
—
18
—
—
DD
DD
DD
DD
DD
DD
DD
Receive data(+)
Receive data(-)
I
PLL test point Digital
PLL Reference clock
O
I
M6
PLL Reference clock
complement
M7
I
Reserved
—
L8
—
X2V
18
DD
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
15
Pin Map
Table 1. MPC8536E Pinout Listing (continued)
Power
Supply
Signal
Signal Name
Package Pin Number Pin Type
Notes
Reserved
—
L9
—
X2V
18
DD
General-Purpose Input/Output
GPIO[0:1]/PCI1_REQ[3:4]
GPIO[2:3]/PCI1_GNT[3:4]
GPIO[4]/SDHC_CD
GPIO/PCI request
GPIO/PCI grant
Y15,AE15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
OV
OV
OV
OV
OV
OV
OV
OV
OV
—
—
—
32
—
—
—
—
—
DD
DD
DD
DD
DD
DD
DD
DD
DD
AA15,AC14
GPIO/SDHC card detection AH11
GPIO/SDHC write protection AG10
GPIO[5]/SDHC_WP
GPIO[6]/USB1_PCTL0
GPIO[7]/USB1_PCTL1
GPIO[8]/USB2_PCTL0
GPIO[9]/USB2_PCTL1
GPIO/USB1 PCTL0
GPIO/USB1 PCTL1
GPIO/USB2 PCTL0
GPIO/USB2 PCTL1
GPIO/DMA Ack
AC3
AC4
AG9
AC9
GPIO[10:11]
AD6,AE10
/DMA_DACK[0:1]
GPIO[12:13]
/DMA_DDONE[0:1]
GPIO/DMA done
AA11,AB11
AB10,AD11
I/O
I/O
OV
OV
—
—
DD
DD
GPIO[14:15]
GPIO/DMA request
/DMA_DREQ[0:1]
System Control
HRESET
Hard reset
AG16
AG15
AG19
AG18
AH17
I
O
I
OV
OV
OV
OV
OV
—
22
—
DD
DD
DD
DD
DD
HRESET_REQ
SRESET
Hard reset - request
Soft reset
CKSTP_IN
CKSTP_OUT
CheckStop in
CheckStop Output
I
—
O
2,4
Debug
TRIG_IN
Trigger in
W19
V19
I
OV
OV
—
DD
DD
TRIG_OUT/READY
/QUIESCE
Trigger out/Ready/Quiesce
O
22
MSRCID[0:1]
MSRCID[2:4]
MDVAL
Memory debug source port ID W12,W13
O
O
O
O
OV
OV
OV
OV
6,9
6,9,22
6,22
11
DD
DD
DD
DD
Memory debug source port ID V12, W14,W11
Memory debug data valid
Clock Out
V13
CLK_OUT
W15
Clock
RTC
Real time clock
AF15
AH14
AC13
I
I
I
OV
OV
OV
—
—
30
DD
DD
DD
SYSCLK
DDRCLK
System clock / PCI clock
DDR clock
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
16
Pin Map
Notes
Table 1. MPC8536E Pinout Listing (continued)
Signal Name Package Pin Number Pin Type
Power
Supply
Signal
JTAG
AG28
TCK
TDI
Test clock
I
I
OV
OV
OV
OV
OV
—
12
11
12
12
DD
DD
DD
DD
DD
Test data in
AH28
AF28
AH27
AH21
TDO
TMS
TRST
Test data out
Test mode select
Test reset
O
I
I
DFT
L1_TSTCLK
L2_TSTCLK
LSSD_MODE
TEST_SEL
L1 test clock
L2 test clock
LSSD Mode
Test select
AA21
AA20
AC25
AA13
I
I
I
I
OV
OV
OV
OV
19
19
19
19
DD
DD
DD
DD
Power Management
ASLEEP
Asleep
AG20
AC26
AE27
O
I
OV
OV
OV
9,16,22
—
DD
DD
DD
POWER_OK
POWER_EN
Power OK
Power enable
O
—
Power and Ground Signals
OVDD
General I/O supply
Y18,AG2,AD4,AB16,
AF6,AC18,AB13,AD10,
AE14,AD16,AD25,
AF27,AE22,AF11,
AF20,AF24
—
—
OV
—
DD
PVDD
LVDD
—
—
3.3 V
LV
—
—
GMAC 1 I/O supply
AA7, AA4
Power for
TSEC1
DD
interfaces
TVDD
GVDD
GMAC 3 I/O supply
SSTL2 DDR supply
V4,U7
Power for
TSEC3
interfaces
TV
—
—
DD
B1,B11,C7,C9,C14,
C17,D4,D6,R3,D15,E2,
E8,C24,E18,F5,E14,
C21,G3,G7,G9,G11,
H5,H12,E22,F15,J10,
K3,K12,K14,H14,D20,
E11,M1,N5
Power for
DDR
DRAM I/O
GV
DD
BVDD
Local bus I/O supply
L23,J18,J23,J19,F20,
F23,H26,J21
Power for
Local Bus
BV
—
DD
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
17
Pin Map
Table 1. MPC8536E Pinout Listing (continued)
Power
Supply
Signal
Signal Name
Package Pin Number Pin Type
Notes
SVDD
XVDD
SerDes 1 core logic supply
M27,N25,P28,R24,
R26,T24,T27,U25,
W24,W26,Y24,Y27,
AA25,AB28,AD27
—
SV
—
DD
SerDes 1 transceiver supply M21,N23,P20,R22,T20,
—
XV
—
DD
U23,V21,W22,Y20,
AA23
S2VDD
X2VDD
SerDes 2 core logic supply
R6,N7,M9
—
—
—
S2V
X2V
—
—
—
DD
SerDes 2 transceiver supply R11,N12,L11
DD
VDD_CORE
Core, L2 logic supply
Platform logic supply
P13,U16,L16,M15,N14,
V
DD_CORE
R14,P15,N16,M13,
U14,T13,L14,T15,R16,
K13
VDD_PLAT
T19,T17,V17,U18,R18,
N18,M19,P19,P17,M17
—
V
—
DD_PLAT
AVDD_CORE
AVDD_PLAT
AVDD_DDR
CPU PLL supply
Platform PLL supply
DDR PLL supply
Local Bus PLL supply
PCI PLL supply
SerDes 1 PLL supply
SerDes 2 PLL supply
—
AH16
AH18
AH19
C28
—
—
—
—
—
—
—
—
—
—
AV
20,28
20
DD_CORE
AV
DD_PLAT
AV
AV
AV
20
DD_DDR
AVDD_LBIU
20
DD_LBIU
AVDD_PCI1
AVDD_SRDS
AVDD_SRDS2
SENSEVDD_CORE
SENSEVDD_PLAT
GND
AH20
W28
T1
20
DD_PCI1
AV
20
DD_SRDS
DD_SRDS2
DD_CORE
AV
20
V15
V
13
—
W17
V
13
DD_PLAT
Ground
D5,AE7,F4,D26,D23,
C12,C15,E20,D8,B10,
AF3,E3,J14,K21,F8,A3,
F16,E12,E15,D17,L1,
F21,H1,G13,G15,G18,
C6,A14,A7,G25,H4,
C20,J12,J15,J17,F27,
M5,J27,K11,L26,K7,
K8,T14,V14,M16,M18,
P14,N15,N17,N19,N2,
P5,P16,P18,M14,R15,
R17,R19,T16,T18,L17,
U15,U17,U19,V18,C27,
Y13,AE26,AA19,AE21,
B28,AC11,AD19,AD23,
L15,AD15,AG23,AE9,
A27,V7,Y7,AC5,U4,Y4,
AE12,AB9,AA14,N13,
R13,L13
—
—
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
18
Pin Map
Table 1. MPC8536E Pinout Listing (continued)
Power
Supply
Signal
Signal Name
Package Pin Number Pin Type
Notes
XGND
SGND
SerDes 1Transceiver pad
GND (xpadvss)
M20,M24,N22,P21,
R23,T21,U22,V20,
W23, Y21
—
—
—
SerDes 1 Transceiver core
logic GND (xcorevss)
M28,N26,P24,P27,
R25,T28,U24,U26,V24,
W25,Y28,AA24,AA26,
AB24,AB27,AD28
—
—
—
X2GND
S2GND
SerDes 2 Transceiver pad
GND (xpadvss)
R12,M10,N11,L12
—
—
—
—
—
—
SerDes 2 Transceiver core
logic GND (xcorevss)
P8,P9,N6,M8
AGND_SRDS
AGND_SRDS2
SENSEVSS
SerDes 1 PLL GND
SerDes 2 PLL GND
GND Sensing
V27
T2
—
—
—
—
—
—
—
—
13
V16
Analog Signals
MVREF
SSTL2 reference voltage
A28
Reference
voltage for
DDR
GVDD/2
—
SD1_IMP_CAL_RX
SD1_IMP_CAL_TX
SD1_PLL_TPA
Rx impedance calibration
Tx impedance calibration
PLL test point analog
M26
AE28
V26
R7
—
—
—
—
—
—
200Ω (±1%)
—
—
18
—
—
18
to GND
100Ω (±1%)
to GND
AVDD_SRD
S analog
SD2_IMP_CAL_RX
SD2_IMP_CAL_TX
SD2_PLL_TPA
Rx impedance calibration
Tx impedance calibration
PLL test point analog
200Ω (±1%)
to GND
L6
100Ω (±1%)
to GND
T3
AVDD_SRD
S2 analog
Reserved
Reserved
R4
R5
—
—
—
—
No Connect Pins
NC
—
C19,D7,D10,L10,R10,
B6,F12,J7,P10,M25,
W27,N24,N10,R8,J9,
K9,V25,R9
—
—
—
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
19
Pin Map
Notes:
Table 1. MPC8536E Pinout Listing (continued)
Signal Name Package Pin Number Pin Type
Power
Supply
Signal
Notes
1. All multiplexed signals may be listed only once and may not re-occur.
2. Recommend a weak pull-up resistor (2–10 KΩ) be placed on this pin to OV
3. This pin must always be pulled-high.
.
DD
4. This pin is an open drain signal.
5. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in the
reset state. This pull-up is designed such that it can be overpowered by an external 4.7-kΩ pull-down resistor. However, if
the signal is intended to be high after reset, and if there is any device on the net which might pull down the value of the net
at reset, then a pullup or active driver is needed.
6. Treat these pins as no connects (NC) unless using debug address functionality.
7. The value of LA[28:31] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7-kΩ pull-up or pull-down
resistors. See Section 22.2, “CCB/SYSCLK PLL Ratio.”
8. The value of LALE, LGPL2 and LBCTL at reset set the e500 core clock to CCB Clock PLL ratio. These pins require 4.7-kΩ
pull-up or pull-down resistors. See the Section 22.3, “e500 Core PLL Ratio.”
9. Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or
because it has other manufacturing test functions. This pin will therefore be described as an I/O for boundary scan.
10. For proper state of these signals during reset, these pins can be left without any pulldowns, thus relying on the internal
pullup to get the values to the require 2'b11.However, if there is any device on the net which might pull down the value of the
net at reset, then a pullup is needed.
11. This output is actively driven during reset rather than being three-stated during reset.
12. These JTAG pins have weak internal pull-up P-FETs that are always enabled.
13. These pins are connected to the V
improve tracking and regulation.
/V
/GND planes internally and may be used by the core power supply to
DD_CORE DD_PLAT
15. These pins have other manufacturing or debug test functions. It is recommended to add both pull-up resistor pads to OVDD
and pull-down resistor pads to GND on board to support future debug testing when needed.
16. If this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a safe
state during reset.
17. This pin is only an output in FIFO mode when used as Rx Flow Control.
18. Do not connect.
19.These must be pulled up (100 Ω- 1 kΩ) to OVDD.
20. Independent supplies derived from board VDD.
21. Recommend a pull-up resistor (1 KΩ) be placed on this pin to OVDD.
22. The following pins must NOT be pulled down during power-on reset: MDVAL, UART_SOUT[0:1], EC_MDC,
TSEC1_TXD[3], TSEC3_TXD[7], HRESET_REQ, TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP.
23. This pin requires an external 4.7-kΩ pull-down resistor to prevent PHY from seeing a valid Transmit Enable before it is
actively driven.
24. General-Purpose POR configuration of user system.
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
20
Freescale Semiconductor
Overall DC Electrical Characteristics
Table 1. MPC8536E Pinout Listing (continued)
Signal Name Package Pin Number Pin Type
Power
Supply
Signal
Notes
25. When a PCI block is disabled, either the POR config pin that selects between internal and external arbiter must be pulled
down to select external arbiter if there is any other PCI device connected on the PCI bus, or leave the address pins as “No
Connect” or terminated through 2–10 KΩ pull-up resistors with the default of internal arbiter if the address pins are not
connected to any other PCI device. The PCI block will drive the address pins if it is configured to be the PCI arbiter—through
POR config pins—irrespective of whether it is disabled via the DEVDISR register or not. It may cause contention if there is
any other PCI device connected on the bus.
26. MDIC[0] is grounded through an 18.2-Ω (full-strength mode) or 36.4-Ω (half-strength mode) precision 1% resistor and
MDIC[1] is connected to GVDD through an 18.2-Ω (full-strength mode) or 36.4-Ω (half-strength mode) precision 1% resistor.
These pins are used for automatic calibration of the DDR IOs.
27. Connect to GND through a pull down 1 kΩ resistor
28. It must be the same as VDD_CORE
29. The output pads are tristated and the receivers of pad inputs are disabled during the Deep Sleep state when
GCR[DEEPSLEEP_Z] =1.
30. DDRCLK input is only required when the DDR controller is running in asynchronous mode. When the DDR controller is
configured to run in synchronous mode via POR setting cfg_ddr_pll[0:2]=111, the DDRCLK input is not required. It is
recommended to tie it off to GND when DDR controller is running in synchronous mode. See the MPC8536E
PowerQUICC™ III Integrated Host Processor Family Reference Manual, Rev.0, Table 4-3 in section 4.2.2 “Clock Signals”,
section 4.4.3.2 “DDR PLL Ratio” and Table 4-10 “DDR Complex Clock PLL Ratio” for more detailed description regarding
DDR controller operation in asynchronous and synchronous modes.
31. EC_GTX_CLK125 is a 125-MHz input clock shared among all eTSEC ports in the following modes: GMII, TBI, RGMII and
RTBI. If none of the eTSEC ports is operating in these modes, the EC_GTX_CLK125 input can be tied off to GND.
32. SDHC_WP is active low signal, which follows SDHC Host controller specification. However, it is reversed polarity for
SD/MMC card specification.
2
Electrical Characteristics
2.1
Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
2.1.1
Absolute Maximum Ratings
Table 2 provides the absolute maximum ratings.
1
Table 2. Absolute Maximum Ratings
Characteristic
Symbol
Max Value
Unit Notes
Core supply voltage
V
–0.3 to 1.21
–0.3 to 1.1
–0.3 to 1.21
–0.3 to 1.1
–0.3 to 1.1
–0.3 to 1.1
V
V
V
V
V
V
—
—
—
—
—
—
DD_CORE
Platform supply voltage
PLL core supply voltage
PLL other supply voltage
V
DD_PLAT
AV
DD_CORE
AV
DD
Core power supply for SerDes transceivers
SV , S2V
DD
DD
Pad power supply for SerDes transceivers and PCI Express
XV
X2V
DD,
DD
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
21
Overall DC Electrical Characteristics
Table 2. Absolute Maximum Ratings (continued)
1
Characteristic
Symbol
GV
Max Value
Unit Notes
DDR SDRAM
Controller I/O
supply voltage
DDR2 SDRAM Interface
DDR3 SDRAM Interface
–0.3 to 1.98
–0.3 to 1.65
V
—
DD
Three-speed Ethernet I/O, MII management voltage
LV (eTSEC1)
–0.3 to 3.63
–0.3 to 2.75
V
V
V
V
2
2
DD
TV (eTSEC3)
–0.3 to 3.63
–0.3 to 2.75
DD
2
PCI, DUART, system control and power management, I C, USB,
eSDHC, eSPI and JTAG I/O voltage
OV
–0.3 to 3.63
—
—
DD
DD
Local bus I/O voltage
BV
–0.3 to 3.63
–0.3 to 2.75
–0.3 to 1.98
Input voltage
DDR2/DDR3 DRAM signals
DDR2/DDR3 DRAM reference
Three-speed Ethernet signals
MV
–0.3 to (GV + 0.3)
V
V
V
3
—
3
IN
DD
MV
–0.3 to (GV + 0.3)
DD
REF
LV
–0.3 to (LV + 0.3)
DD
IN
TV
–0.3 to (TV + 0.3)
IN
DD
Local bus signals
BV
–0.3 to (BV + 0.3)
—
V
—
3
IN
DD
PCI, DUART, SYSCLK, system control and
power management, I C, and JTAG signals
OV
–0.3 to (OV + 0.3)
IN
DD
2
0
Storage temperature range
T
–55 to 150
C
—
STG
Notes:
1. Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2. The 3.63-V maximum is only supported when the port is configured in GMII, MII, RMII or TBI modes; otherwise the 2.75V
maximum applies. See Section 2.9.2, “FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications,” for details on
the recommended operating conditions per protocol.
3. (M,L,O)V and MV
may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
REF
IN
2.1.2
Recommended Operating Conditions
Table 3 provides the recommended operating conditions for this device. Note that the values in Table 2 are the recommended
and tested operating conditions. Proper device operation outside these conditions is not guaranteed.
Table 3. Recommended Operating Conditions
Characteristic
Symbol
Recommended Value Unit Notes
Core supply voltage
V
1.0 50 mV
1.1 55 mV
V
1
DD_CORE
Platform supply voltage
PLL core supply voltage
V
1.0 50 mV
V
V
—
DD_PLAT
AV
1.0 50 mV
1.1 55 mV
1,2
DD_CORE
PLL other supply voltage
AV
SV
1.0 50 mV
1.0 50 mV
V
V
2
DD
Core power supply for SerDes transceivers
—
DD
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
22
Overall DC Electrical Characteristics
Table 3. Recommended Operating Conditions (continued)
Characteristic
Symbol
Recommended Value Unit Notes
Pad power supply for SerDes transceivers and PCI Express
XV
GV
1.0 50 mV
1.8 V 90 mV
1.5 V 75 mV
V
V
—
3
DD
DDR SDRAM
Controller I/O supply
voltage
DDR2 SDRAM Interface
DDR3 SDRAM Interface
DD
Three-speed Ethernet I/O voltage
LV
(eTSEC1)
3.3 V 165 mV
2.5 V 125 mV
V
5
DD
TV
(eTSEC3)
3.3 V 165 mV
2.5 V 125 mV
DD
2
PCI, DUART, system control and power management, I C, USB, eSDHC,
eSPI and JTAG I/O voltage
OV
3.3 V 165 mV
V
V
4
DD
Local bus I/O voltage
BV
3.3 V 165 mV
2.5 V 125 mV
1.8 V 90 mV
—
DD
Input voltage
DDR2 and DDR3 SDRAM Interface signals
DDR2 and DDR3 SDRAM Interface reference
Three-speed Ethernet signals
MV
GND to GV
V
V
V
3
—
5
IN
DD
MV
GV /2 1%
DD
REF
LV
GND to LV
DD
IN
TV
GND to TV
GND to BV
GND to OV
IN
DD
DD
DD
Local bus signals
BV
V
V
—
4
IN
PCI, Local bus, DUART, SYSCLK, system control
and power management, I C, and JTAG signals
OV
IN
2
Operating
Temperature range
Commercial
TA= 0 (min) to
TJ= 90(max)
TA= 0 (min) to
TJ= 105 (max)
Industrial
TA
TJ
°C
6
standard temperature range
Extended temperature range
TA= -40 (min) to
TJ= 105 (max)
Notes:
1. VDD = 1.0 V for 600 to 1333 MHz, 1.1 V for 1500 MHz,
2. This voltage is the input to the filter discussed in Section 3.2.1, “PLL Power Supply Filtering,” and not necessarily the voltage
at the AVDD pin, which may be reduced from VDD by the filter.
3. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
4. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
5. Caution: L/TVIN must not exceed L/TVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
6. Minimum temperature is specified with TA; maximum temperature is specified with TJ.
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
23
Overall DC Electrical Characteristics
Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8536E.
B/G/L/OV + 20%
DD
B/G/L/OV + 5%
DD
B/G/L/OV
V
DD
IH
GND
GND – 0.3 V
V
IL
GND – 0.7 V
Not to Exceed 10%
1
of t
CLOCK
Note:
1. t
refers to the clock period associated with the respective interface:
CLOCK
2
For I C and JTAG, t
references SYSCLK.
CLOCK
For DDR, t
references MCLK.
CLOCK
CLOCK
For eTSEC, t
references EC_GTX_CLK125.
For eLBC, t
references LCLK.
CLOCK
For PCI, t
references PCI1_CLK or SYSCLK.
CLOCK
2. With the PCI overshoot allowed (as specified above), the device
does not fully comply with the maximum AC ratings and device protection
guideline outlined in the PCI rev. 2.2 standard (section 4.2.2.3).
Figure 7. Overshoot/Undershoot Voltage for GV /OV /LV
DD
DD
DD
The core voltage must always be provided at nominal 1.0 Vor 1.1 V (See Table 2 for actual recommended core voltage). Voltage
to the processor interface I/Os are provided through separate sets of supply pins and must be provided at the voltages shown in
Table 2. The input voltage threshold scales with respect to the associated I/O supply voltage. OV and LV based receivers
DD
DD
are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR2 and DDR3 SDRAM interface
uses differential receivers referenced by the externally supplied MVREFn signal (nominally set to GVDD/2) as is appropriate
for the SSTL_1.8 electrical signaling standard for DDR2 or 1.5-V electrical signaling for DDR3. The DDR DQS receivers
cannot be operated in single-ended fashion. The complement signal must be properly driven and cannot be grounded.
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
24
Freescale Semiconductor
Power Sequencing
2.1.3
Output Driver Characteristics
Table 3 provides information on the characteristics of the output driver strengths. The values are preliminary estimates.
Table 4. Output Drive Capability
Programmable
Supply
Driver Type
Output Impedance
Notes
Voltage
(Ω)
Local bus interface utilities signals
25
35
BV = 3.3 V
1
DD
BV = 2.5 V
DD
45(default)
45(default)
125
BV = 3.3 V
DD
BV = 2.5 V
DD
BV = 1.8 V
DD
PCI signals
25
OV = 3.3 V
2
DD
42 (default)
DDR2 signal
DDR3 signal
16
GV = 1.8 V
3
2
DD
32 (half strength mode)
20
GV = 1.5 V
DD
40 (half strength mode)
TSEC signals
42
42
LV = 2.5/3.3 V
—
—
—
DD
DUART, system control, JTAG
OV = 3.3 V
DD
2
I C
150
OV = 3.3 V
DD
Notes:
1. The drive strength of the local bus interface is determined by the configuration of the appropriate bits in PORIMPSCR.
2. The drive strength of the PCI interface is determined by the setting of the PCI1_GNT1 signal at reset.
3. The drive strength of the DDR2 or DDR3 interface in half-strength mode is at T = 105°C and at GV (min)
j
DD
2.2
Power Sequencing
The MPC8536E requires its power rails to be applied in a specific sequence in order to ensure proper device operation. These
requirements are as follows for power up:
1.
V
, V
(if POWER_EN is not used to control V
), AV , BV , LV , OV
,
DD
DD_PLAT DD_CORE
DD_CORE
DD
DD
DD
SV ,S2V , TV , XV and X2V
DD
DD
DD
DD
DD
DD_CORE
2. [Wait for POWER_EN to assert], then V
(if POWER_EN is used to control V
)
DD_CORE
3. GV
DD
All supplies must be at their stable values within 50 ms.
Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered
sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step
reach 10% of theirs.
In order to guarantee MCKE low during power-up, the above sequencing for GV is required. If there is no concern about any
DD
of the DDR signals being in an indeterminate state during power-up, then the sequencing for GV is not required.
DD
From a system standpoint, if any of the I/O power supplies ramp prior to the VDD platform supply, the I/Os associated with
that I/O supply may drive a logic one or zero during power-up, and extra current may be drawn by the device.
During the Deep Sleep state, the VDD core supply is removed. But all other power supplies remain applied. Therefore, there is
no requirement to apply the VDD core supply before any other power rails when the silicon waking from Deep Sleep.
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
25
Power Characteristics
2.3
Power Characteristics
The estimated power dissipation for the core complex bus (CCB) versus the core frequency for this family of PowerQUICC III
devices is shown in Table 5.
5
Table 5. MPC8536E Power Dissipation
Core
CCB
DDR
V
Junction
Tempera
ture
DD
V
Core
9
DD
Frequen Frequen Frequen Platfor
Core Power
Platform Power
5
Power Mode
Notes
cy
cy
cy
m
7
7
(MHz)
(MHz)
(MHz)
(V)
(V)
(°C)
mean
Max
mean
Max
Maximum (A)
Thermal (W)
Typical (W)
Doze (W)
105
/90
—
—
4.1/3.3
3.7/2.9
—
—
—
4.7/3.7 1, 3, 8
4.7/3.7 1, 4, 8
1.5
1.2
0.8
0.8
0
1.5
1.4
1.4
1.0
0.6
—
1, 2
1
1.9
1.9
1.9
1.6
1.1
600
400
400
400
400
400
400
1.0
1.0
1.0
1.0
1.0
1.0
65
Nap (W)
1.5
1
Sleep (W)
1.5
1
Deep Sleep
(W)
35
0
6
Maximum (A)
Thermal (W)
Typical (W)
Doze (W)
105
/ 90
—
—
4.5/3.7
3.9/3.1
—
—
—
4.7/3.7 1, 3, 8
4.7/3.7 1, 4, 8
1.7
1.3
0.8
0.8
0
1.5
1.4
1.4
1.0
0.6
—
1, 2
1
2.1
1.9
1.9
1.6
1.1
800
65
Nap (W)
1.5
1
Sleep (W)
1.5
1
Deep Sleep
(W)
35
0
1,6
Maximum (A)
Thermal (W)
Typical (W)
Doze (W)
105
/ 90
—
—
4.8/4.0
4.1/3.3
—
—
—
4.7/3.7 1, 3, 8
4.7/3.7 1, 4, 8
1.9
1.4
0.8
0.8
0
1.5
1.4
1.4
1.0
0.6
—
1, 2
1
2.2
1.9
1.9
1.6
1.1
1000
65
35
Nap (W)
1.6
1
Sleep (W)
1.6
1
Deep Sleep
(W)
0
1, 6
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
26
Power Characteristics
5
Table 5. MPC8536E Power Dissipation (continued)
Core
CCB
DDR
V
Junction
Tempera
ture
DD
V
Core
9
DD
Frequen Frequen Frequen Platfor
Core Power
Platform Power
5
Power Mode
Notes
cy
cy
cy
m
7
7
(MHz)
(MHz)
(MHz)
(V)
(V)
(°C)
mean
Max
mean
Max
Maximum (A)
Thermal (W)
Typical (W)
Doze (W)
105
/ 90
—
5.3/4.4
4.4/3.6
—
—
5.0/4.0 1, 3, 8
5.0/4.0 1, 4, 8
1
1250
500
500
1.0
1.0
—
2.2
1.6
0.8
0.8
0
65
1.7
1.5
1.5
1.1
0.6
2.4
1.6
1.6
0
2.1
2.1
1.7
1.2
1
1
Nap (W)
Sleep (W)
1
Deep Sleep
(W)
35
1, 6
Maximum (A)
Thermal (W)
—
—
5.4/4.6
4.5/3.7
—
—
5.2/4.1 1, 3, 8
5.2/4.1 1, 4, 8
1333
533
667
1.0
1.0
105
/ 90
Typical (W)
Doze (W)
Nap (W)
65
2.3
1.7
0.8
0.8
0
1.8
1.6
1.6
1.2
0.6
—
1, 2
1
2.5
1.6
1.6
0
2.1
2.1
1.7
1.2
1
Sleep (W)
1
Deep Sleep
(W)
35
1, 6
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
27
Power Characteristics
Core
5
Table 5. MPC8536E Power Dissipation (continued)
CCB
DDR
V
Junction
Tempera
ture
DD
V
Core
9
DD
Frequen Frequen Frequen Platfor
Core Power
Platform Power
5
Power Mode
Notes
cy
cy
cy
m
7
7
(MHz)
(MHz)
(MHz)
(V)
(V)
(°C)
mean
Max
mean
Max
Maximum (A)
Thermal (W)
Typical (W)
Doze (W)
105
/ 90
—
7.1/6.1
5.9/4.9
—
—
5.0/4.0 1, 3, 8
5.0/4.0 1, 4, 8
1, 2
1500
500
667
1.0
1.1
—
3.0
2.2
1.1
1.1
0
65
1.7
1.5
1.5
1.1
0.6
3.3
2.1
2.1
0
2.1
2.1
1.7
1.2
1
1
Nap (W)
Sleep (W)
1
Deep Sleep
(W)
35
1, 6
Notes:
1. These values specify the power consumption at nominal voltage and apply to all valid processor bus frequencies and
configurations. The values do not include power dissipation for I/O supplies.
2. Typical power is an average value measured at the nominal recommended core voltage (V ) and 65°C junction temperature
DD
(see Table 3) while running the Dhrystone benchmark.
3. Maximum power is the maximum power measured with the worst process and recommended core and platform voltage (V
at maximum operating junction temperature (see Table 3) while running a smoke test which includes an entirely
L1-cache-resident, contrived sequence of instructions which keep the execution unit maximally busy.
4. Thermal power is the maximum power measured with worst case process and recommended core and platform voltage (V
at maximum operating junction temperature (see Table 3) while running the Dhrystone benchmark.
5. VDD Core = 1.0 V for 600 to 1333 MHz, 1.1 V for 1500 MHz.
)
DD
)
DD
6. Maximum power is the maximum number measured with USB1, eTSEC1, and DDR blocks enabled. The Mean power is the
mean power measured with only external interrupts enabled and DDR in self refresh.
7. Mean power is provided for information purposes only and is the mean power consumed by a statistically significant range of
devices.
0
0
8. Maximum operating junction temperature (see Table 3) for Commercial Tier is 90 C, for Industrial Tier is 105 C.
9. Platform power is the power supplied to all the V pins.
DD_PLAT
See Section 2.23.6.1, “SYSCLK to Platform Frequency Options,” for the full range of CCB frequencies that MPC8536E
supports.
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
28
Freescale Semiconductor
Input Clocks
2.4
Input Clocks
2.4.1
System Clock Timing
Table 6 provides the system clock (SYSCLK) AC timing specifications for the MPC8536E.
Table 6. SYSCLK AC Timing Specifications
At recommended operating conditions (see Table 2) with OV = 3.3 V 165 mV.
DD
Parameter/Condition
SYSCLK frequency
Symbol
Min
Typical
Max
Unit
Notes
f
t
33
7.5
0.6
40
—
—
—
133
30
MHz
ns
1
—
2
SYSCLK
SYSCLK cycle time
SYSCLK rise and fall time
SYSCLK duty cycle
SYSCLK jitter
SYSCLK
t
, t
1.0
—
2.1
ns
KH KL
t
/t
60
%
—
3, 4
KHK SYSCLK
—
—
+/-150
ps
Notes:
1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting
SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum
operating frequencies. See Section 2.23.2, “CCB/SYSCLK PLL Ratio,” and Section 2.23.3, “e500 Core PLL Ratio,” for ratio
settings.
2. Rise and fall times for SYSCLK are measured at 0.6 V and 2.7 V.
3. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set low to allow
cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter.
4. For spread spectrum clocking, guidelines are +0% to -1% down spread at a modulation rate between 20 KHz and 60 KHz on
SYSCLK.
2.4.2
PCI Clock Timing
When the PCI controller is configured for asynchronous operation, the reference clock for the PCI controller is not the SYSCLK
input, but instead the PCI_CLK. Table 7 provides the PCI reference clock AC timing specifications for the MPC8536E.
Table 7. PCICLK AC Timing Specifications
At recommended operating conditions (see Table 2) with OV = 3.3 V 165 mV.
DD
Parameter/Condition
PCICLK frequency
Symbol
Min
Typical
Max
Unit
Notes
f
t
t
33
15
0.6
40
—
—
66
30
2.1
60
MHz
ns
—
—
1
PCICLK
PCICLK
PCICLK cycle time
PCICLK rise and fall time
PCICLK duty cycle
Notes:
, t
1.0
—
ns
KH KL
t
/t
%
—
KHK PCICLK
1. Rise and fall times for PCICLK are measured at 0.6 V and 2.7 V.
2.4.3
Real Time Clock Timing
The RTC input is sampled by the platform clock (CCB clock). The output of the sampling latch is then used as an input to the
counters of the PIC and the TimeBase unit of the e500. There is no jitter specification. The minimum pulse width of the RTC
signal should be greater than 2x the period of the CCB clock. That is, minimum clock high time is 2 × t
, and minimum clock
CCB
low time is 2 × t
. There is no minimum RTC frequency; RTC may be grounded if not needed.
CCB
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
29
Input Clocks
2.4.4
eTSEC Gigabit Reference Clock Timing
Table 8 provides the eTSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications for the MPC8536E.
Table 8. EC_GTX_CLK125 AC Timing Specifications
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Notes
EC_GTX_CLK125 frequency
EC_GTX_CLK125 cycle time
EC_GTX_CLK rise and fall time
f
t
—
—
—
125
8
—
—
MHz
ns
—
—
1
G125
G125
t
/t
—
ns
G125R G125F
LV
LV
TV
TV
2.5V
3.3V
0.75
1.0
DD,
DD,
DD =
DD =
EC_GTX_CLK125 duty cycle
t
/t
—
%
2
G125H G125
GMII, TBI
1000Base-T for RGMII, RTBI
45
47
55
53
Notes:
1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5V and 2.0V for L/TVDD=2.5V, and from 0.6 and 2.7V for
L/TVDD=3.3V at 0.6 V and 2.7 V.
2. EC_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation. EC_GTX_CLK125
duty cycle can be loosened from 47/53% as long as the PHY device can tolerate the duty cycle generated by the eTSEC
GTX_CLK. See Section 2.9.2.6, “RGMII and RTBI AC Timing Specifications,” for duty cycle for 10Base-T and 100Base-T
reference clock.
2.4.5 DDR Clock Timing
Table 9 provides the DDR clock (DDRCLK) AC timing specifications for the MPC8536E.
Table 9. DDRCLK AC Timing Specifications
At recommended operating conditions with OVDD of 3.3V 5%.
Parameter/Condition
DDRCLK frequency
Symbol
Min
Typical
Max
Unit
Notes
f
t
66
6.0
0.6
40
—
—
166
15.15
1.2
MHz
ns
1
—
2
DDRCLK
DDRCLK cycle time
DDRCLK rise and fall time
DDRCLK duty cycle
DDRCLK jitter
DDRCLK
t
, t
1.0
—
ns
KH KL
t
/t
60
%
—
3, 4
KHK DDRCLK
—
—
—
+/– 150
ps
Notes:
1. Caution: The DDR complex clock to DDRCLK ratio settings must be chosen such that the resulting DDR complex
clock frequency does not exceed the maximum or minimum operating frequencies. See Section 2.23.4,
“DDR/DDRCLK PLL Ratio,” for ratio settings.
2. Rise and fall times for DDRCLK are measured at 0.6 V and 2.7 V.
3. The DDRCLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to
allow cascade-connected PLL-based devices to track DDRCLK drivers with the specified jitter.
4. For spread spectrum clocking, guidelines are +0% to –1% down spread at a modulation rate between 20 kHz and
60 kHz on DDRCLK.
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
30
Freescale Semiconductor
RESET Initialization
2.4.6
Platform to FIFO Restrictions
Please note the following FIFO maximum speed restrictions based on platform speed. The “platform clock (CCB) frequency”
in the following formula refers to the maximum platform (CCB) frequency of the speed bins the part belongs to, which is
defined in Table 73.
For FIFO GMII mode:
FIFO TX/RX clock frequency <= platform clock frequency/3.2
For example, if the platform frequency is 533 MHz, the FIFO TX/RX clock frequency should be no more than 167 MHz
For FIFO encoded mode:
FIFO TX/RX clock frequency <= platform clock frequency/3.2
For example, if the platform frequency is 533 MHz, the FIFO TX/RX clock frequency should be no more than
167 MHz
2.4.7
Other Input Clocks
For information on the input clocks of other functional blocks of the platform such as SerDes, and eTSEC, see the specific
section of this document.
2.5
RESET Initialization
This section describes the AC electrical specifications for the RESET initialization timing requirements of the MPC8536E.
Table 10 provides the RESET initialization AC timing specifications for the DDR SDRAM component(s).
Table 10. RESET Initialization Timing Specifications
Parameter/Condition
Min Max
Unit
Notes
Required assertion time of HREST
Minimum assertion time for SRESET
100
3
—
—
—
—
μs
Sysclk
μs
—
1
PLL input setup time with stable SYSCLK before HRESET negation
100
4
—
1
Input setup time for POR configurations (other than PLL config) with respect to negation of
HRESET
SYSCLKs
Input hold time for all POR configurations (including PLL config) with respect to negation of
HRESET
2
—
5
SYSCLKs
SYSCLKs
SYSCLK
1
1
Maximum valid-to-high impedance time for actively driven POR configurations with respect to
negation of HRESET
—
—
HRESET rise time
1
—
Notes:
1. SYSCLK is the primary clock input for the MPC8536E.
Table 11 provides the PLL lock times.
Table 11. PLL Lock Times
Parameter/Condition
Min
Max
Unit
Notes
PLL lock times
Local bus PLL
—
—
—
100
50
μs
μs
μs
—
—
—
PCI bus lock time
50
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
31
DDR2 and DDR3 SDRAM
2.6
DDR2 and DDR3 SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the MPC8536E. Note that
DDR2 SDRAM is GV (type) = 1.8 V and DDR3 SDRAM is GV (type) = 1.5 V.
DD
DD
2.6.1
DDR2 and DDR3 SDRAM DC Electrical Characteristics
Table 12 provides the recommended operating conditions for the DDR SDRAM component(s) of the MPC8536E when
interfacing to DDR2 SDRAM.
Table 12. DDR2 SDRAM DC Electrical Characteristics for GV (typ) = 1.8 V
DD
Parameter/Condition
I/O supply voltage
Symbol
Min
Max
Unit
Notes
GV
MV
1.7
1.9
V
V
1
2
DD
I/O reference voltage
I/O termination voltage
Input high voltage
0.49 × GV
0.51 × GV
DD
REF
TT
DD
V
MV
– 0.04
MV
+ 0.04
REF
V
3
REF
V
MV
+ 0.125
GV + 0.3
V
—
—
4
IH
REF
DD
Input low voltage
V
I
–0.3
MV
– 0.125
REF
V
IL
Output leakage current
–50
–13.4
13.4
50
μA
mA
mA
OZ
OH
Output high current (V
= 1.420 V)
I
—
—
—
—
OUT
Output low current (V
= 0.280 V)
I
OL
OUT
Notes:
1. GV is expected to be within 50 mV of the DRAM GV at all times.
DD
DD
2. MV
is expected to be equal to 0.5 × GV , and to track GV DC variations as measured at the receiver.
REF
DD DD
may not exceed 2% of the DC value.
Peak-to-peak noise on MV
REF
3. V is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
TT
equal to MV . This rail should track variations in the DC level of MV
.
REF
REF
4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GV
.
DD
Table 13 provides the recommended operating conditions for the DDR SDRAM Controller of the MPC8536E when interfacing
to DDR3 SDRAM.
Table 13. DDR3 SDRAM Interface DC Electrical Characteristics for GV (typ) = 1.5 V
DD
Parameter/Condition
I/O supply voltage
Symbol
GV
Min
Max
Unit
Notes
1.425
1.575
V
V
1
2
DD
I/O reference voltage
Input high voltage
Input low voltage
Output leakage current
Notes:
MV
n
0.49 × GV
0.51 × GV
DD
REF
DD
V
MV
n + 0.100
GV
DD
V
—
—
3
IH
REF
V
GND
–50
MV
n – 0.100
50
V
IL
REF
I
μA
OZ
1. GV is expected to be within 50 mV of the DRAM GV at all times.
DD
DD
2. MV
n is expected to be equal to 0.5 × GV , and to track GV DC variations as measured at the receiver.
DD DD
REF
Peak-to-peak noise on MV
n may not exceed 1% of the DC value.
REF
3. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GV
.
DD
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
32
DDR2 and DDR3 SDRAM
Table 14 provides the DDR capacitance when GV (type) = 1.8 V.
DD
Table 14. DDR2 SDRAM Capacitance for GV (typ)=1.8 V
DD
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input/output capacitance: DQ, DQS, DQS
Delta input/output capacitance: DQ, DQS, DQS
Note:
C
6
8
pF
pF
1, 2
1, 2
IO
C
—
0.5
DIO
1. This parameter is sampled. GV = 1.8 V 0.090 V (for DDR2), f = 1 MHz, T = 25°C, V
= GV /2, V
DD OUT
DD
A
OUT
(peak-to-peak) = 0.2 V.
2. This parameter is sampled. GVDD = 1.5 V 0.075 V (for DDR3), f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT
(peak-to-peak) = 0.175 V.
Table 15 provides the current draw characteristics for MV
.
REF
Table 15. Current Draw Characteristics for MV
REF
Max
Parameter/Condition
Current draw for MV
Symbol
Min
Unit
Note
n
DDR2 SDRAM
DDR3 SDRAM
I
—
1500
1250
μA
1
REF
MVREFn
1.The voltage regulator for MV
must be able to supply up to 500 μA or 1250 uA current for DDR2 or DDR3 respectively.
REF
2.6.2
DDR2 and DDR3 SDRAM Interface AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR SDRAM Controller interface. The DDR controller supports
both DDR2 and DDR3 memories. Please note that although the minimum data rate for most off-the-shelf DDR3 DIMMs
available is 800 MHz, JEDEC specification does allow the DDR3 to run at the data rate as low as 606 MHz. Unless otherwise
specified, the AC timing specifications described in this section for DDR3 is applicable for data rate between 606 MHz and
667 MHz, as long as the DC and AC specifications of the DDR3 memory to be used are compliant to both JEDEC specifications
as well as the specifications and requirements described in this MPC8536E hardware specifications document.
2.6.2.1
DDR2 and DDR3 SDRAM Interface Input AC Timing Specifications
Table 16 through Table 18 provide the input AC timing specifications for the DDR controller.
Table 16. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface
At recommended operating conditions with GVDD of 1.8 V 5%
Parameter
AC input low voltage
Symbol
Min
Max
Unit
667
V
—
—
MV
MV
– 0.20
V
V
V
V
ILAC
REF
<=533
667
– 0.25
REF
AC input high voltage
V
MV
MV
+ 0.20
—
IHAC
REF
REF
<=533
+ 0.25
—
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
33
DDR2 and DDR3 SDRAM
Table 17. DDR3 SDRAM Input AC Timing Specifications for 1.5-V Interface
At recommended operating conditions with GVDD of 1.5 V 5%. DDR3 data rate is between 606MHz and 667MHz.
Parameter
AC input low voltage
AC input high voltage
Symbol
Min
Max
– 0.175
REF
Unit
Notes
V
—
MV
V
V
—
—
IL
V
MV
+ 0.175
REF
—
IH
Table 18. DDR2 and DDR3 SDRAM Interface Input AC Timing Specifications
At recommended operating conditions with GVDD of 1.8 V 5% for DDR2 or 1.5 V 5% for DDR3.
Parameter
Symbol
Min
Max
Unit
Notes
Controller Skew for MDQS—MDQ/MECC
t
—
—
ps
1, 2
CISKEW
667 MHz
533 MHz
400 MHz
—
–240
–300
–365
240
300
365
—
—
—
3
—
—
—
—
Note:
1. t
represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that will
CISKEW
be captured with MDQS[n]. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t
.This can be determined
DISKEW
by the following equation: t
=+/-(T/4 - abs(t
)) where T is the clock period and abs(t
) is the absolute value
DISKEW
CISKEW
CISKEW
of t
.
CISKEW
3. Maximum DDR2 and DDR3 frequency is 667MHz.
3
Figure 8 shows the DDR2 and DDR3 SDRAM interface input timing diagram.
MCK[n]
MCK[n]
t
MCK
MDQS[n]
MDQ[x]
D0
D1
t
DISKEW
t
DISKEW
Figure 8. DDR SDRAM Input Timing Diagram
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
34
DDR2 and DDR3 SDRAM
2.6.2.2
DDR2 and DDR3 SDRAM Interface Output AC Timing Specifications
Table 19 contains the output AC timing targets for the DDR2 and DDR3 SDRAM interface.
Table 19. DDR SDRAM Output AC Timing Specifications
At recommended operating conditions with GVDD of 1.8 V 5% for DDR2 or 1.5 V 5% for DDR3.
1
Parameter
Symbol
Min
Max
Unit
Notes
MCK[n] cycle time, MCK[n]/MCK[n] crossing
t
3.0
5
ns
ns
2
3
7
MCK
ADDR/CMD output setup with respect to MCK
t
t
t
t
DDKHAS
DDKHAX
DDKHCS
DDKHCX
667 MHz
1.10
1.48
1.95
—
—
—
533 MHz
400 MHz
ADDR/CMD output hold with respect to MCK
ns
ns
ns
3
7
667 MHz
1.10
1.48
1.95
—
—
—
533 MHz
400 MHz
MCS[n] output setup with respect to MCK
3
7
667 MHz
1.10
1.48
1.95
—
—
—
533 MHz
400 MHz
MCS[n] output hold with respect to MCK
3
7
667 MHz
1.10
1.48
1.95
—
—
—
533 MHz
400 MHz
MCK to MDQS Skew
t
ns
ps
4
7
5
DDKHMH
<= 667 MHz
–0.6
0.6
MDQ/MECC/MDM output setup with respect to
MDQS
t
t
DDKHDS,
DDKLDS
667 MHz
533 MHz
400 MHz
450
538
700
—
—
—
7
MDQ/MECC/MDM output hold with respect to
MDQS
t
t
ps
ns
5
7
DDKHDX,
DDKLDX
667 MHz
450
538
700
—
—
—
533 MHz
400 MHz
MDQS preamble start
t
6
DDKHMP
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
35
DDR2 and DDR3 SDRAM
Table 19. DDR SDRAM Output AC Timing Specifications (continued)
At recommended operating conditions with GVDD of 1.8 V 5% for DDR2 or 1.5 V 5% for DDR3.
1
Parameter
Symbol
Min
Max
Unit
Notes
<= 667 MHz
<= 667 MHz
0.9 × t
7
6
7
MCK
MDQS epilogue end
t
ns
DDKHME
0.4 × t
0.6 × t
MCK
MCK
Note:
1. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state) (reference)(state)
inputs and t
for outputs. Output hold time can be read as DDR timing
(first two letters of functional block)(reference)(state)(signal)(state)
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
symbolizes DDR timing (DD) for the time t memory clock reference (K) goes from the high (H) state until outputs
t
DDKHAS
MCK
(A) are setup (S) or output valid time. Also, t
symbolizes DDR timing (DD) for the time t
memory clock reference
DDKLDX
MCK
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals 0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.
4. Note that t follows the symbol conventions described in note 1. For example, t describes the DDR timing (DD)
DDKHMH
DDKHMH
from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). t
can be modified through control
DDKHMH
of the DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock adjust in the
CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same
adjustment value. See the MPC8536E PowerQUICC™ III Integrated Processor Reference Manual for a description and
understanding of the timing modifications enabled by use of these bits.
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that t
symbol conventions described in note 1.
follows the
DDKHMP
7. Maximum DDR2 and DDR3 frequency is 667 MHz
NOTE
For the ADDR/CMD setup and hold specifications in Table 19, it is assumed that the Clock
Control register is set to adjust the memory clocks by 1/2 applied cycle.
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
36
Freescale Semiconductor
DDR2 and DDR3 SDRAM
).
Figure 9 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (t
DDKHMH
MCK[n]
MCK[n]
t
MCK
t
DDKHMHmax) = 0.6 ns
MDQS
MDQS
t
DDKHMH(min) = –0.6 ns
Figure 9. Timing Diagram for tDDKHMH
Figure 10 shows the DDR SDRAM output timing diagram.
MCK[n]
MCK[n]
t
MCK
t
,t
DDKHAS DDKHCS
t
,t
DDKHAX DDKHCX
ADDR/CMD
Write A0
NOOP
t
DDKHMP
t
DDKHMH
MDQS[n]
MDQ[x]
t
DDKHME
t
DDKHDS
t
DDKLDS
D0
D1
t
DDKLDX
t
DDKHDX
Figure 10. DDR SDRAM Output Timing Diagram
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
37
eSPI
Figure 11 provides the AC test load for the DDR bus.
GV /2
Output
Z = 50 Ω
0
DD
R = 50 Ω
L
Figure 11. DDR AC Test Load
2.7
eSPI
This section describes the DC and AC electrical specifications for the eSPI of the MPC8536E.
2.7.1 eSPI DC Electrical Characteristics
Table 20 provides the DC electrical characteristics for the device eSPI.
Table 20. SPI DC Electrical Characteristics
Characteristic
Output high voltage
Symbol
Condition
= –6.0 mA
OH
Min
Max
Unit
V
I
2.4
—
—
V
V
OH
Output low voltage
Output low voltage
Input high voltage
Input low voltage
Input current
V
V
I
= 6.0 mA
= 3.2 mA
—
0.5
0.4
OL
OL
I
—
V
OL
OL
V
2.0
–0.3
—
OV + 0.3
V
IH
DD
V
—
0.8
10
V
IL
I
0 V ≤ V ≤ OV
DD
μA
IN
IN
2.7.2 eSPI AC Timing Specifications
Table 21 and provide the eSPI input and output AC timing specifications.
1
Table 21. SPI AC Timing Specifications
2
Characteristic
Symbol
Min
Max
Unit
Note
SPI_MOSI output—Master data (internal clock) hold time
t
t
0.5
4.0
—
—
ns
ns
ns
—
3
NIKHOX
NIKHOX
SPI_MOSI output—Master data (internal clock) delay
SPI_CS outputs—Master data (internal clock) hold time
t
t
—
—
6.0
7.4
3
—
NIKHOV
NIKHOV
t
0
—
—
NIKHOX2
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
38
eSPI
1
Table 21. SPI AC Timing Specifications (continued)
2
Characteristic
Symbol
Min
Max
Unit
Note
SPI_CS outputs—Master data (internal clock) delay
SPI inputs—Master data (internal clock) input setup time
SPI inputs—Master data (internal clock) input hold time
Notes:
t
—
5
6.0
—
ns
ns
ns
—
—
—
NIKHOV2
t
NIIVKH
t
0
—
NIIXKH
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are
measured at the pin.
2. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state) (reference)(state)
inputs and t
for outputs. For example, t
symbolizes the NMSI
(first two letters of functional block)(reference)(state)(signal)(state)
NIKHOV
outputs internal timing (NI) for the time t
(V).
memory clock reference (K) goes from the high state (H) until outputs (O) are valid
SPI
3. The greater of the two output timings for t
and t
are used when the SPCOM[RxDelay] bit of eSPI Command
NIKHOX
NIKHOV
Register is set. For example, the t
is 4.0 and t
is 7.4 if SPCOM[RxDelay] is set to be 1.
NIKHOX
NIKHOV
Figure 12 provides the AC test load for the SPI.
OV /2
Output
Z = 50 Ω
DD
0
R = 50 Ω
L
Figure 12. SPI AC Test Load
Figure 13 represent the AC timing from Table 21. Note that although the specifications generally reference the rising edge of
the clock, these AC timing diagrams also apply when the falling edge is the active edge.
Figure 13 shows the SPI timing in Master mode (internal clock).
SPICLK (output)
t
NIIXKH
t
NIIVKH
Input Signals:
SPIMISO
(See Note)
t
NIKHOX
t
NIKHOV
Output Signals:
SPIMOSI
(See Note)
t
NIKHOV2
tNIKHOX2
Output Signals:
SPI_CS[0:3]
(See Note)
Note: The clock edge is selectable on SPI.
Figure 13. SPI AC Timing in Master mode (Internal Clock) Diagram
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
39
DUART
2.8
DUART
This section describes the DC and AC electrical specifications for the DUART interface of the MPC8536E.
2.8.1
DUART DC Electrical Characteristics
Table 22 provides the DC electrical characteristics for the DUART interface.
Table 22. DUART DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
High-level input voltage
Low-level input voltage
V
2
– 0.3
—
OV + 0.3
V
V
IH
DD
V
I
0.8
5
IL
Input current
μA
IN
1
(V
= 0 V or V = V
IN
IN DD)
High-level output voltage
(OV = min, I = –2 mA)
V
2.4
—
—
V
V
OH
DD
OH
Low-level output voltage
(OV = min, I = 2 mA)
V
0.4
OL
DD
OL
Note:
1. Note that the symbol V , in this case, represents the OV symbol referenced in Table 1 and Table 2.
IN
IN
2.8.2
DUART AC Electrical Specifications
Table 23 provides the AC timing parameters for the DUART interface.
Table 23. DUART AC Timing Specifications
Parameter
Minimum baud rate
Value
Unit
Notes
CCB clock/1,048,576
CCB clock/16
16
baud
baud
—
2
2,3
4
Maximum baud rate
Oversample rate
Notes:
2. CCB clock refers to the platform clock.
3. Actual attainable baud rate will be limited by the latency of interrupt processing.
th
4. The middle of a start bit is detected as the 8 sampled 0 after the 1-to-0 transition of the start bit.
th
Subsequent bit values are sampled each 16 sample.
2.9
Ethernet: Enhanced Three-Speed Ethernet (eTSEC),
MII Management
This section provides the AC and DC electrical characteristics for enhanced three-speed and MII management.
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
40
Freescale Semiconductor
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
2.9.1
Enhanced Three-Speed Ethernet Controller (eTSEC)
(10/100/1000 Mbps) — FIFO/GMII/MII/TBI/RGMII/RTBI/RMII Electrical
Characteristics
The electrical characteristics specified here apply to all FIFO mode, gigabit media independent interface (GMII), media
independent interface (MII), ten-bit interface (TBI), reduced gigabit media independent interface (RGMII), reduced ten-bit
interface (RTBI), and reduced media independent interface (RMII) signals except management data input/output (MDIO) and
management data clock (MDC), and serial gigabit media independent interface (SGMII). The RGMII, RTBI and FIFO mode
interfaces are defined for 2.5 V, while the GMII, MII, RMII, and TBI interfaces can operate at 3.3V.
The GMII, MII, or TBI interface timing is compliant with IEEE 802.3. The RGMII and RTBI interfaces follow the Reduced
Gigabit Media-Independent Interface (RGMII) Specification Version 1.3 (12/10/2000). The RMII interface follows the RMII
Consortium RMII Specification Version 1.2 (3/20/1998).
The electrical characteristics for MDIO and MDC are specified in Section 2.10, “Ethernet Management Interface Electrical
Characteristics.”
The electrical characteristics for SGMII is specified in Section 2.9.3, “SGMII Interface Electrical Characteristics.” The SGMII
interface conforms (with exceptions) to the Serial-GMII Specification Version 1.8.
2.9.1.1
GMII, MII, TBI, RGMII, RMII and RTBI DC Electrical Characteristics
All GMII, MII, TBI, RGMII, RMII and RTBI drivers and receivers comply with the DC parametric attributes specified in
Table 24 and Table 25. The RGMII and RTBI signals are based on a 2.5-V CMOS interface voltage as defined by JEDEC
EIA/JESD8-5.
Table 24. GMII, MII, RMII, and TBI DC Electrical Characteristics
Parameter
Supply voltage 3.3 V
Symbol
LV
Min
Max
Unit
Notes
1, 2
3.13
3.47
V
DD
TV
DD
Output high voltage
(LV /TV = Min, IOH = –4.0 mA)
VOH
VOL
2.40
LV /TV + 0.3
V
V
—
—
—
DD
DD
DD
DD
Output low voltage
(LV /TV = Min, IOL = 4.0 mA)
GND
0.50
DD
DD
Input high voltage
Input low voltage
Input high current
V
1.90
–0.3
—
LV /TV + 0.3
V
V
IH
DD
DD
V
I
0.90
—
IL
1, 2,3
40
μA
IH
(V = LV , V = TV )
IN
DD IN
DD
3
Input low current
I
–600
—
μA
IL
(V = GND)
IN
Notes:
1
2
3
LV supports eTSECs 1.
DD
TV supports eTSECs 3.
DD
The symbol V , in this case, represents the LV and TV symbols referenced in Table 1 and Table 2.
IN
IN
IN
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
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41
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
Table 25. RGMII, RTBI, and FIFO DC Electrical Characteristics
Parameters
Supply voltage 2.5 V
Output high voltage
Symbol
LV /TV
Min
2.37
2.00
Max
Unit
V
Notes
1,2
2.63
DD
DD
V
LV /TV + 0.3
V
—
—
—
OH
DD
DD
(LV /TV = Min, IOH = –1.0 mA)
DD
DD
Output low voltage
(LV /TV = Min, I = 1.0 mA)
V
GND – 0.3
0.40
V
OL
DD
DD
OL
Input high voltage
Input low voltage
Input high current
V
1.70
–0.3
—
LV /TV + 0.3
V
V
IH
DD
DD
V
I
0.70
—
IL
1, 2,3
10
μA
IH
(V = LV , V = TV )
IN
DD IN
DD
3
Input low current
I
–15
—
μA
IL
(V = GND)
IN
Note:
1
2
3
LV supports eTSECs 1.
DD
TV supports eTSECs 3.
DD
Note that the symbol V , in this case, represents the LV and TV symbols referenced in Table 1 and Table 2.
IN
IN
IN
2.9.2
FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications
The AC timing specifications for FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI are presented in this section.
2.9.2.1
FIFO AC Specifications
The basis for the AC specifications for the eTSEC’s FIFO modes is the double data rate RGMII and RTBI specifications, since
they have similar performance and are described in a source-synchronous fashion like FIFO modes. However, the FIFO
interface provides deliberate skew between the transmitted data and source clock in GMII fashion.
When the eTSEC is configured for FIFO modes, all clocks are supplied from external sources to the relevant eTSEC interface.
That is, the transmit clock must be applied to the eTSECn’s TSECn_TX_CLK, while the receive clock must be applied to pin
TSECn_RX_CLK. The eTSEC internally uses the transmit clock to synchronously generate transmit data and outputs an echoed
copy of the transmit clock back out onto the TSECn_GTX_CLK pin (while transmit data appears on TSECn_TXD[7:0], for
example). It is intended that external receivers capture eTSEC transmit data using the clock on TSECn_GTX_CLK as a source-
synchronous timing reference. Typically, the clock edge that launched the data can be used, since the clock is delayed by the
eTSEC to allow acceptable set-up margin at the receiver. Note that there is relationship between the maximum FIFO speed and
the platform speed. For more information see Section 2.4.6, “Platform to FIFO Restrictions.”
A summary of the FIFO AC specifications appears in Table 26 and Table 27.
Table 26. FIFO Mode Transmit AC Timing Specification
Parameter/Condition
Symbol
Min
Typ
Max
Unit
2
TX_CLK, GTX_CLK clock period
t
6.0
45
—
8.0
50
—
100
55
ns
%
FIT
TX_CLK, GTX_CLK duty cycle
t
FITH
TX_CLK, GTX_CLK peak-to-peak jitter
t
250
ps
FITJ
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
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42
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
Table 26. FIFO Mode Transmit AC Timing Specification (continued)
Parameter/Condition
Rise time TX_CLK (20%–80%)
Symbol
Min
Typ
Max
Unit
t
—
—
—
—
—
0.75
0.75
3.0
ns
ns
ns
FITR
Fall time TX_CLK (80%–20%)
t
FITF
1
GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN hold time
t
0.5
FITDX
Note:
1. Data valid tFITDV to GTX_CLK Min Setup time is a function of clock period and max hold time. (Min Setup = Cycle time
– Max Hold)
2. The minimum cycle period (or maximum frequency) of the RX_CLK is dependent on the maximum platform frequency
of the speed bins the part belongs to as well as the FIFO mode under operation. See Section 2.4.6, “Platform to FIFO
Restrictions,” for more detailed description.
Table 27. FIFO Mode Receive AC Timing Specification
Parameter/Condition
Symbol
Min
Typ
Max
Unit
1
RX_CLK clock period
t
6.0
45
—
8.0
50
—
—
—
—
—
100
55
ns
%
FIR
RX_CLK duty cycle
t
/t
FIRH FIRH
RX_CLK peak-to-peak jitter
Rise time RX_CLK (20%–80%)
Fall time RX_CLK (80%–20%)
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
Note:
t
250
0.75
0.75
—
ps
ns
ns
ns
ns
FIRJ
t
—
FIRR
t
—
FIRF
t
1.5
0.5
FIRDV
FIRDX
t
—
1. The minimum cycle period (or maximum frequency) of the RX_CLK is dependent on the maximum platform frequency
of the speed bins the part belongs to as well as the FIFO mode under operation. See Section 2.4.6, “Platform to FIFO
Restrictions,” for more detailed description.
Timing diagrams for FIFO appear in Figure 14 and Figure 15.
.
t
t
FITR
FITF
t
FIT
GTX_CLK
t
t
t
FITDX
FITH
FITDV
TXD[7:0]
TX_EN
TX_ER
Figure 14. FIFO Transmit AC Timing Diagram
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
43
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
t
FIRR
t
FIR
RX_CLK
t
FIRH
t
FIRF
RXD[7:0]
RX_DV
RX_ER
valid data
t
t
FIRDV
FIRDX
Figure 15. FIFO Receive AC Timing Diagram
2.9.2.2
GMII AC Timing Specifications
This section describes the GMII transmit and receive AC timing specifications.
2.9.2.2.1
GMII Transmit AC Timing Specifications
Table 28 provides the GMII transmit AC timing specifications.
Table 28. GMII Transmit AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V 5%.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
GTX_CLK clock period
t
—
0.5
—
8.0
—
—
—
—
ns
ns
ns
ns
GTK
3
GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay
GTX_CLK data clock rise time (20%-80%)
GTX_CLK data clock fall time (80%-20%)
Notes:
t
5.0
1.0
1.0
GTKHDX
t
GTXR
t
—
GTXF
1. The symbols used for timing specifications herein follow the pattern t
(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t
for outputs. For example, t
symbolizes GMII
(first two letters of functional block)(reference)(state)(signal)(state)
GTKHDV
transmit timing (GT) with respect to the t
clock reference (K) going to the high state (H) relative to the time date input
GTX
signals (D) reaching the valid state (V) to state or setup time. Also, t
symbolizes GMII transmit timing (GT) with respect
GTKHDX
to the t
clock reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold
GTX
time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a
particular functional. For example, the subscript of t represents the GMII(G) transmit (TX) clock. For rise and fall times,
GTX
the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. Data valid tGTKHDV to GTX_CLK Min Setup time is a function of clock period and max hold time. (Min Setup = Cycle time -
Max Hold)
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
44
Freescale Semiconductor
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 16 shows the GMII transmit AC timing diagram.
t
t
GTXR
GTX
GTX_CLK
t
t
GTXH
GTXF
TXD[7:0]
TX_EN
TX_ER
t
GTKHDX
t
GTKHDV
Figure 16. GMII Transmit AC Timing Diagram
2.9.2.2.2
GMII Receive AC Timing Specifications
Table 29 provides the GMII receive AC timing specifications.
Table 29. GMII Receive AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V 5%.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
RX_CLK clock period
t
—
35
2.0
0
8.0
—
—
—
—
—
—
65
—
ns
ns
ns
ns
ns
ns
GRX
RX_CLK duty cycle
t
/t
GRXH GRX
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
RX_CLK clock rise (20%-80%)
RX_CLK clock fall time (80%-20%)
Note:
t
GRDVKH
t
—
GRDXKH
t
—
—
1.0
1.0
GRXR
t
GRXF
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t
for outputs. For example, t
symbolizes GMII
(first two letters of functional block)(reference)(state)(signal)(state)
GRDVKH
receive timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the t clock
RX
reference (K) going to the high state (H) or setup time. Also, t
symbolizes GMII receive timing (GR) with respect to the
GRDXKL
time data input signals (D) went invalid (X) relative to the t
clock reference (K) going to the low (L) state or hold time. Note
GRX
that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular
functional. For example, the subscript of t represents the GMII (G) receive (RX) clock. For rise and fall times, the latter
GRX
convention is used with the appropriate letter: R (rise) or F (fall).
Figure 17 provides the AC test load for eTSEC.
Output
LV /2
DD
Z = 50 Ω
0
R = 50 Ω
L
Figure 17. eTSEC AC Test Load
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
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Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 18 shows the GMII receive AC timing diagram.
t
t
GRXR
GRX
RX_CLK
t
t
GRXF
GRXH
RXD[7:0]
RX_DV
RX_ER
t
GRDXKH
t
GRDVKH
Figure 18. GMII Receive AC Timing Diagram
2.9.2.3
MII AC Timing Specifications
This section describes the MII transmit and receive AC timing specifications.
2.9.2.3.1
MII Transmit AC Timing Specifications
Table 30 provides the MII transmit AC timing specifications.
Table 30. MII Transmit AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V 5%.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
TX_CLK clock period 10 Mbps
TX_CLK clock period 100 Mbps
TX_CLK duty cycle
t
—
—
400
40
—
5
—
—
ns
ns
%
MTX
t
MTX
t
t
35
1
65
15
4.0
4.0
MTXH/ MTX
TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay
TX_CLK data clock rise (20%-80%)
TX_CLK data clock fall (80%-20%)
Note:
t
ns
ns
ns
MTKHDX
t
1.0
1.0
—
—
MTXR
t
MTXF
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t
for outputs. For example, t
symbolizes MII
(first two letters of functional block)(reference)(state)(signal)(state)
MTKHDX
transmit timing (MT) for the time t
clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in
MTX
general, the clock reference symbol representation is based on two to three letters representing the clock of a particular
functional. For example, the subscript of t represents the MII(M) transmit (TX) clock. For rise and fall times, the latter
MTX
convention is used with the appropriate letter: R (rise) or F (fall).
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Figure 19 shows the MII transmit AC timing diagram.
t
t
MTXR
MTX
TX_CLK
t
t
MTXF
MTXH
TXD[3:0]
TX_EN
TX_ER
t
MTKHDX
Figure 19. MII Transmit AC Timing Diagram
2.9.2.3.2
MII Receive AC Timing Specifications
Table 31 provides the MII receive AC timing specifications.
Table 31. MII Receive AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V 5%.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
RX_CLK clock period 10 Mbps
RX_CLK clock period 100 Mbps
RX_CLK duty cycle
t
t
—
—
400
40
—
—
—
ns
ns
%
MRX
MRX
t
/t
35
65
—
MRXH MRX
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
RX_CLK clock rise (20%–80%)
RX_CLK clock fall time (80%–20%)
Note:
t
10.0
10.0
1.0
1.0
—
ns
ns
ns
ns
MRDVKH
t
—
—
MRDXKH
t
—
4.0
4.0
MRXR
t
—
MRXF
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t
for outputs. For example, t
symbolizes MII receive
clock reference (K) going
(first two letters of functional block)(reference)(state)(signal)(state)
MRDVKH
timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
MRX
to the high (H) state or setup time. Also, t
symbolizes MII receive timing (GR) with respect to the time data input signals
MRDXKL
(D) went invalid (X) relative to the t
clock reference (K) going to the low (L) state or hold time. Note that, in general, the
MRX
clock reference symbol representation is based on three letters representing the clock of a particular functional. For example,
the subscript of t represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the
MRX
appropriate letter: R (rise) or F (fall).
Figure 20 provides the AC test load for eTSEC.
LV /2
Output
Z = 50 Ω
DD
0
R = 50 Ω
L
Figure 20. eTSEC AC Test Load
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Figure 21 shows the MII receive AC timing diagram.
t
t
MRX
MRXR
RX_CLK
t
t
MRXF
MRXH
RXD[3:0]
RX_DV
RX_ER
Valid Data
t
MRDVKH
t
MRDXKL
Figure 21. MII Receive AC Timing Diagram
2.9.2.4
TBI AC Timing Specifications
This section describes the TBI transmit and receive AC timing specifications.
2.9.2.4.1
TBI Transmit AC Timing Specifications
Table 32 provides the TBI transmit AC timing specifications.
Table 32. TBI Transmit AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V 5%.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
GTX_CLK clock period
GTX_CLK duty cycle
t
—
40
1.0
—
8.0
—
—
—
—
—
60
ns
%
TTX
t
/t
TTXH TTX
2
GTX_CLK to TCG[9:0] delay time
GTX_CLK rise (20%–80%)
GTX_CLK fall time (80%–20%)
Notes:
t
5.0
1.0
1.0
ns
ns
ns
TTKHDX
t
TTXR
t
—
TTXF
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state )(reference)(state)
for inputs and t
for outputs. For example, t
symbolizes the TBI
(first two letters of functional block)(reference)(state)(signal)(state)
TTKHDV
transmit timing (TT) with respect to the time from t
(K) going high (H) until the referenced data signals (D) reach the valid
TTX
state (V) or setup time. Also, t
symbolizes the TBI transmit timing (TT) with respect to the time from t
(K) going high
TTKHDX
TTX
(H) until the referenced data signals (D) reach the invalid state (X) or hold time. Note that, in general, the clock reference symbol
representation is based on three letters representing the clock of a particular functional. For example, the subscript of t
TTX
represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R
(rise) or F (fall).
2. Data valid tTTKHDV to GTX_CLK Min Setup time is a function of clock period and max hold time. (Min Setup = Cycle time - Max
Hold)
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Figure 22 shows the TBI transmit AC timing diagram.
t
t
TTXR
TTX
GTX_CLK
t
TTXH
t
TTXF
t
TTXF
TCG[9:0]
t
t
TTXR
TTKHDV
t
TTKHDX
Figure 22. TBI Transmit AC Timing Diagram
2.9.2.4.2
TBI Receive AC Timing Specifications
Table 33 provides the TBI receive AC timing specifications.
Table 33. TBI Receive AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V 5%.
2
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Clock period for TBI Receive Clock 0, 1
Skew for TBI Receive Clock 0, 1
t
—
16.0
—
—
8.5
60
—
ns
ns
%
TRX
t
7.5
40
SKTRX
Duty cycle for TBI Receive Clock 0, 1
t
/t
—
TRXH TRX
RCG[9:0] setup time to rising edge of TBI Receive Clock 0, 1
RCG[9:0] hold time to rising edge of TBI Receive Clock 0, 1
Clock rise time (20%-80%) for TBI Receive Clock 0, 1
Clock fall time (80%-20%) for TBI Receive Clock 0, 1
Note:
t
2.5
1.5
0.7
0.7
—
ns
ns
ns
ns
TRDVKH
TRDXKH
t
—
—
t
—
2.4
2.4
TRXR
t
—
TRXF
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state)
for inputs and t
for outputs. For example, t
(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
TRDVKH
symbolizes TBI receive timing (TR) with respect to the time data input signals (D) reach the valid state (V) relative to the
t
clock reference (K) going to the high (H) state or setup time. Also, t
symbolizes TBI receive timing (TR) with
clock reference (K) going to the high (H)
TRX
TRDXKH
respect to the time data input signals (D) went invalid (X) relative to the t
TRX
state. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of
a particular functional. For example, the subscript of t represents the TBI (T) receive (RX) clock. For rise and fall times,
TRX
the latter convention is used with the appropriate letter: R (rise) or F (fall). For symbols representing skews, the subscript
is skew (SK) followed by the clock that is being skewed (TRX).
2. The signals “TBI Receive Clock 0” and “TBI Receive Clock 1” refer to TSECn_RX_CLK and TSECn_TX_CLK pins
respectively. These two clock signals are also referred as PMA_RX_CLK[0:1].
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Figure 23 shows the TBI receive AC timing diagram.
t
t
TRXR
TRX
TBI Receive Clock 1
(TSECn_TX_CLK)
t
t
TRXH
TRXF
RCG[9:0]
Valid Data
Valid Data
t
TRDVKH
t
t
SKTRX
TRDXKH
TBI Receive Clock 0
(TSECn_RX_CLK)
t
t
TRDXKH
TRXH
t
TRDVKH
Figure 23. TBI Receive AC Timing Diagram
2.9.2.5
TBI Single-Clock Mode AC Specifications
When the eTSEC is configured for TBI modes, all clocks are supplied from external sources to the relevant eTSEC interface.
In single-clock TBI mode, when a 125-MHz TBI receive clock is supplied on TSECn pin (no receive clock is used on in this
mode, whereas for the dual-clock mode this is the PMA0 receive clock). The 125-MHz transmit clock is applied on the in all
TBI modes.
A summary of the single-clock TBI mode AC specifications for receive appears in Table 34.
Table 34. TBI single-clock Mode Receive AC Timing Specification
At recommended operating conditions with LVDD/TVDD of 3.3 V 5%
Parameter/Condition
RX_CLK clock period
Symbol
Min
Typ
Max
Unit
t
7.5
40
—
8.0
50
—
—
—
—
—
8.5
60
ns
%
TRR
RX_CLK duty cycle
t
t
TRRH
RX_CLK peak-to-peak jitter
t
250
1.0
1.0
—
ps
ns
ns
ns
ns
TRRJ
Rise time RX_CLK (20%–80%)
Fall time RX_CLK (80%–20%)
RCG[9:0] setup time to RX_CLK rising edge
RCG[9:0] hold time to RX_CLK rising edge
—
TRRR
t
—
TRRF
t
2.0
1.0
TRRDV
TRRDX
t
—
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A timing diagram for TBI receive appears in Figure 24.
.
t
TRRR
t
TRR
RX_CLK
RCG[9:0]
t
TRRH
t
TRRF
valid data
t
t
TRRDV
TRRDX
Figure 24. TBI Single-Clock Mode Receive AC Timing Diagram
2.9.2.6
RGMII and RTBI AC Timing Specifications
Table 35 presents the RGMII and RTBI AC timing specifications.
Table 35. RGMII and RTBI AC Timing Specifications
At recommended operating conditions with L/TVDD of 2.5 V 5%.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Data to clock output skew (at transmitter)
t
–500
1.0
7.2
45
0
500
2.8
ps
ns
ns
%
SKRGT_TX
2
Data to clock input skew (at receiver)
t
—
8.0
—
50
—
—
SKRGT_RX
3
Clock period duration
t
8.8
RGT
4
Duty cycle for 1000BASE-T
t
t
/t
55
RGTH RGT
3, 4
Duty cycle for 10BASE-T and 100BASE-TX
/t
40
60
%
RGTH RGT
Rise time (20%–80%)
Fall time (20%–80%)
Notes:
t
—
0.75
0.75
ns
ns
RGTR
t
—
RGTF
1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to
represent RGMII and RTBI timing. For example, the subscript of t represents the TBI (T) receive (RX) clock. Note
RGT
also that the notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols
representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT).
2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than
1.5 ns will be added to the associated clock signal.
3. For 10 and 100 Mbps, t
scales to 400 ns 40 ns and 40 ns 4 ns, respectively.
RGT
4. Duty cycle may be stretched/shrunk during speed changes or while transition to a received packet's clock domains as
long as the minimum duty cycle is not violated and stretching occurs for no more than three t
transitioned between.
of the lowest speed
RGT
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Figure 25 shows the RGMII and RTBI AC timing and multiplexing diagrams.
t
RGT
t
RGTH
GTX_CLK
(At Transmitter)
t
SKRGT_TX
TXD[8:5][3:0]
TXD[7:4][3:0]
TXD[8:5]
TXD[7:4]
TXD[3:0]
TXD[9]
TXERR
TXD[4]
TXEN
TX_CTL
t
SKRGT_TX
TX_CLK
(At PHY)
RXD[8:5][3:0]
RXD[7:4][3:0]
RXD[8:5]
RXD[7:4]
RXD[3:0]
t
SKRGT_RX
RXD[9]
RXERR
RXD[4]
RXDV
RX_CTL
t
SKRGT_RX
RX_CLK
(At PHY)
Figure 25. RGMII and RTBI AC Timing and Multiplexing Diagrams
2.9.2.7
RMII AC Timing Specifications
This section describes the RMII transmit and receive AC timing specifications.
2.9.2.7.1
RMII Transmit AC Timing Specifications
The RMII transmit AC timing specifications are in Table 36.
Table 36. RMII Transmit AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V 5%.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
TSECn_TX_CLK clock period
TSECn_TX_CLK duty cycle
t
15.0
35
20.0
50
25.0
65
ns
%
RMT
t
RMTH
TSECn_TX_CLK peak-to-peak jitter
t
—
—
250
ps
RMTJ
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Table 36. RMII Transmit AC Timing Specifications (continued)
At recommended operating conditions with L/TVDD of 3.3 V 5%.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Rise time TSECn_TX_CLK (20%–80%)
Fall time TSECn_TX_CLK (80%–20%)
TSECn_TX_CLK to RMII data TXD[1:0], TX_EN delay
Note:
t
1.0
1.0
2.0
—
—
—
2.0
2.0
ns
ns
ns
RMTR
t
RMTF
t
10.0
RMTDX
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state)
for inputs and t
for outputs. For example, t
(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
MTKHDX
symbolizes MII transmit timing (MT) for the time t
clock reference (K) going high (H) until data outputs (D) are invalid
MTX
(X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock
of a particular functional. For example, the subscript of t represents the MII(M) transmit (TX) clock. For rise and fall
MTX
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
Figure 26 shows the RMII transmit AC timing diagram.
t
t
RMT
RMTR
TSECn_TX_CLK
t
t
RMTF
RMTH
TXD[1:0]
TX_EN
TX_ER
t
RMTDX
Figure 26. RMII Transmit AC Timing Diagram
2.9.2.7.2
RMII Receive AC Timing Specifications
Table 37. RMII Receive AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V 5%.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
TSECn_RX_CLK clock period
t
15.0
35
20.0
50
25.0
65
ns
%
RMR
TSECn_RX_CLK duty cycle
t
RMRH
TSECn_RX_CLK peak-to-peak jitter
Rise time TSECn_RX_CLK (20%–80%)
t
—
—
250
2.0
ps
ns
RMRJ
RMRR
t
1.0
—
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Table 37. RMII Receive AC Timing Specifications (continued)
At recommended operating conditions with L/TVDD of 3.3 V 5%.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Fall time TSECn_RX_CLK (80%–20%)
t
1.0
4.0
2.0
—
—
—
2.0
—
ns
ns
ns
RMRF
RXD[1:0], CRS_DV, RX_ER setup time to TSECn_RX_CLK rising edge
RXD[1:0], CRS_DV, RX_ER hold time to TSECn_RX_CLK rising edge
t
RMRDV
t
—
RMRDX
Note:
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t
for outputs. For example, t
symbolizes MII receive
(first two letters of functional block)(reference)(state)(signal)(state)
MRDVKH
timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
clock reference (K) going
MRX
to the high (H) state or setup time. Also, t
symbolizes MII receive timing (GR) with respect to the time data input signals
MRDXKL
(D) went invalid (X) relative to the t
clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock
MRX
reference symbol representation is based on three letters representing the clock of a particular functional. For example, the
subscript of t represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the
MRX
appropriate letter: R (rise) or F (fall).
Figure 27 provides the AC test load for eTSEC.
LV /2
Output
Z = 50 Ω
DD
0
R = 50 Ω
L
Figure 27. eTSEC AC Test Load
Figure 28 shows the RMII receive AC timing diagram.
t
t
RMRR
RMR
TSECn_RX_CLK
t
t
RMRH
RMRF
RXD[1:0]
CRS_DV
RX_ER
Valid Data
t
RMRDV
t
RMRDX
Figure 28. RMII Receive AC Timing Diagram
2.9.3
SGMII Interface Electrical Characteristics
Each SGMII port features a 4-wire AC-Coupled serial link from the dedicated SerDes 2 interface of MPC8536E as shown in
Figure 29, where C is the external (on board) AC-Coupled capacitor. Each output pin of the SerDes transmitter differential
TX
pair features 50-Ω output impedance. Each input of the SerDes receiver differential pair features 50-Ω on-die termination to
S2GND (xcorevss). The reference circuit of the SerDes transmitter and receiver is shown in Figure 68.
When an eTSEC port is configured to operate in SGMII mode, the parallel interface’s output signals of this eTSEC port can be
left floating. The input signals should be terminated based on the guidelines described in Section 3.6, “Connection
Recommendations,” as long as such termination does not violate the desired POR configuration requirement on these pins, if
applicable.
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When operating in SGMII mode, the eTSEC EC_GTX_CLK125 clock is not required for this port. Instead, SerDes reference
clock is required on SD2_REF_CLK and SD2_REF_CLK pins.
2.9.3.1
DC Requirements for SGMII SD2_REF_CLK and SD2_REF_CLK
The characteristics and DC requirements of the separate SerDes reference clock are described in Section 2.20, “High-Speed
Serial Interfaces.”
2.9.3.2 AC Requirements for SGMII SD2_REF_CLK and SD2_REF_CLK
Table 38 lists the SGMII SerDes reference clock AC requirements. Please note that SD2_REF_CLK and SD2_REF_CLK are
not intended to be used with, and should not be clocked by, a spread spectrum clock source.
Table 38. SD2_REF_CLK and SD2_REF_CLK AC Requirements
Symbol
Parameter Description
Min Typical Max Units Notes
t
REFCLK cycle time
—
—
10 (8)
—
—
ns
ps
1
REF
t
REFCLK cycle-to-cycle jitter. Difference in the period of any two adjacent
REFCLK cycles
100
—
REFCJ
t
Phase jitter. Deviation in edge location with respect to mean edge location
–50
—
50
ps
2,3
REFPJ
Notes:
1. 8 ns applies only when 125 MHz SerDes2 reference clock frequency is selected via cfg_srds_sgmii_refclk during POR.
2. In a frequency band from 150 kHz to 15 MHz, at BER of 10E-12.
3. Total peak-to-peak deterministic jitter “Dj” should be less than or equal to 50 ps.
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2.9.3.3 SGMII Transmitter and Receiver DC Electrical Characteristics
Table 39 and Table 40 describe the SGMII SerDes transmitter and receiver AC-Coupled DC electrical characteristics.
Transmitter DC characteristics are measured at the transmitter outputs (SD2_TX[n] and SD2_TX[n]) as depicted in Figure 30.
Table 39. SGMII DC Transmitter Electrical Characteristics
Parameter
Supply Voltage
Symbol
X2V
Min
Typ
Max
1.05
Unit
Notes
0.95
—
1.0
—
V
—
1
DD
Output high voltage
Output low voltage
Output ringing
VOH
X2V
|V
/2 +
/2
mV
DD-Typ
|
OD -max
VOL
X2V
|V
/2 -
/2
—
—
mV
%
1
DD-Typ
|
OD -max
V
—
—
10
—
RING
323
500
725
Equalization
setting: 1.0x
296
269
243
215
189
162
459
417
376
333
292
250
665
604
545
483
424
362
Equalization
setting: 1.09x
Equalization
setting: 1.2x
2, 3, 5
Output differential voltage
Equalization
setting: 1.33x
|V
|
mV
OD
Equalization
setting: 1.5x
Equalization
setting: 1.71x
Equalization
setting: 2.0x
Output offset voltage
V
425
40
—
500
—
575
60
10
25
25
40
mV
Ω
1, 4
—
OS
Output impedance (single-ended)
Mismatch in a pair
R
O
Δ R
—
%
—
O
Change in V between “0” and “1”
Δ |V
|
—
—
mV
mV
mA
—
OD
OD
Change in V between “0” and “1”
Δ V
—
—
—
OS
OS
Output current on short to GND
I
, I
—
—
—
SA SB
Notes:
1. This will not align to DC-coupled SGMII. X2V
=1.0V.
DD-Typ
2. |V | = |V
- V
|. |V | is also referred as output differential peak voltage. V
= 2*|V |
OD .
OD
SD2_TXn
SD2_TXn
OD
TX-DIFFp-p
3. The |V | value shown in the table assumes the following transmit equalization setting in the XMITEQAB (for SerDes 2 lanes
OD
A & B) or XMITEQEF (for SerDes 2 lanes E & E) bit field of MPC8536E’s SerDes 2 Control Register:
• The MSbit (bit 0) of the above bit field is set to zero (selecting the full V
amplitude - power up default);
DD-DIFF-p-p
• The LSbits (bit [1:3]) of the above bit field is set based on the equalization setting shown in table.
4. V is also referred to as output common mode voltage.
OS
• 5.The |V | value shown in the Typ column is based on the condition of X2V
=1.0V, no common mode offset variation
OD
DD-Typ
(VOS =550mV), SerDes2 transmitter is terminated with 100-Ω differential load between SD2_TX[n] and SD2_TX[n].
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
56
Freescale Semiconductor
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
SD2_TXn
SD_RXm
50 Ω
50 Ω
C
TX
50 Ω
50 Ω
Receiver
Transmitter
C
TX
SD2_TXn
SD2_RXn
SD_RXm
MPC8536E SGMII
SerDes Interface
C
SD_TXm
SD_TXm
50 Ω
TX
50 Ω
50 Ω
Receiver
Transmitter
50 Ω
C
TX
SD2_RXn
Figure 29. 4-Wire AC-Coupled SGMII Serial Link Connection Example
MPC8536E SGMII
SerDes Interface
SD2_TXn
50 Ω
50
50
Ω
Transmitter
V
V
OD
os
50 Ω
Ω
SD2_TXn
Figure 30. SGMII Transmitter DC Measurement Circuit
Table 40. SGMII DC Receiver Electrical Characteristics
Parameter
Supply Voltage
Symbol
X2V
Min
Typ
Max
Unit
Notes
0.95
1.0
N/A
—
1.05
V
—
1
DD
DC Input voltage range
Input differential voltage
—
—
LSTS = 0
LSTS = 1
V
100
175
1200
mV
2, 4
RX_DIFFp-p
—
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
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Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
Table 40. SGMII DC Receiver Electrical Characteristics (continued)
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Loss of signal threshold
LSTS = 0
LSTS = 1
VLOS
30
65
—
80
20
—
—
100
175
100
120
35
mV
3, 4
Input AC common mode voltage
V
—
mV
Ω
5
CM_ACp-p
Receiver differential input impedance
Z
100
—
—
—
RX_DIFF
Receiver common mode input
impedance
Z
Ω
RX_CM
Common mode input voltage
V
—
V
—
V
6
CM
xcorevss
Notes:
1. Input must be externally AC-coupled.
2. V
is also referred to as peak to peak input differential voltage
RX_DIFFp-p
3. The concept of this parameter is equivalent to the Electrical Idle Detect Threshold parameter in PCI Express. See PCI
Express Differential Receiver (RX) Input Specifications section for further explanation.
4. The LSTS shown in the table refers to the LSTSA or LSTSE bit field of MPC8536’s SerDes 2 Control Register.
5. V
is also referred to as peak to peak AC common mode voltage.
CM_ACp-p
6. On-chip termination to S2GND (xcorevss).
2.9.3.4
SGMII AC Timing Specifications
This section describes the SGMII transmit and receive AC timing specifications. Transmitter and receiver characteristics are
measured at the transmitter outputs (SD2_TX[n] and SD2_TX[n]) or at the receiver inputs (SD2_RX[n] and SD2_RX[n]) as
depicted in Figure 32 respectively.
2.9.3.4.1
SGMII Transmit AC Timing Specifications
Table 41 provides the SGMII transmit AC timing targets. A source synchronous clock is not provided.
Table 41. SGMII Transmit AC Timing Specifications
At recommended operating conditions with X2VDD = 1.0V 5%.
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Deterministic Jitter
Total Jitter
JD
JT
—
—
—
—
0.17
0.35
UI p-p
UI p-p
ps
—
—
1
Unit Interval
UI
799.92
50
800
—
800.08
120
V
fall time (80%-20%)
rise time (20%-80%)
tfall
ps
—
—
OD
V
t
50
—
120
ps
OD
rise
Notes:
1. Each UI is 800 ps 100 ppm.
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
58
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
2.9.3.4.2
SGMII Receive AC Timing Specifications
Table 42 provides the SGMII receive AC timing specifications. Source synchronous clocking is not supported. Clock is
recovered from the data. Figure 31 shows the SGMII Receiver Input Compliance Mask eye diagram.
Table 42. SGMII Receive AC Timing Specifications
At recommended operating conditions with X2VDD = 1.0V 5%.
Parameter
Deterministic Jitter Tolerance
Symbol
Min
Typ
Max
Unit
Notes
JD
JDR
JSIN
JT
0.37
0.55
0.1
—
—
—
—
—
—
UI p-p
UI p-p
UI p-p
UI p-p
1
1
Combined Deterministic and Random Jitter Tolerance
Sinusoidal Jitter Tolerance
Total Jitter Tolerance
—
1
0.65
—
—
1
-12
Bit Error Ratio
BER
UI
—
10
—
2
Unit Interval
799.92
5
800
—
800.08
200
ps
AC Coupling Capacitor
C
nF
3
TX
Notes:
1. Measured at receiver.
2. Each UI is 800 ps 100 ppm.
3. The external AC coupling capacitor is required. It is recommended to be placed near the device transmitter outputs.
V
/2
RX_DIFFp-p-max
V
/2
RX_DIFFp-p-min
0
− V
− V
/2
RX_DIFFp-p-min
/2
RX_DIFFp-p-max
1
0
0.275
0.4
0.6
0.725
Time (UI)
Figure 31. SGMII Receiver Input Compliance Mask
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
59
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 32. SGMII AC Test/Measurement Load
2.9.4
eTSEC IEEE 1588 AC Specifications
Figure 33 shows the data and command output timing diagram.
t
T1588CLKOUT
t
T1588CLKOUTH
TSEC_1588_CLK_OUT
t
T1588OV
TSEC_1588_PULSE_OUT
TSEC_1588_TRIG_OUT
Figure 33. eTSEC IEEE 1588 Output AC timing
The output delay is count starting rising edge if t is non-inverting. Otherwise, it is count starting falling edge.
1
T1588CLKOUT
Figure 34 provides the data and command input timing diagram.
t
T1588CLK
t
T1588CLKH
TSEC_1588_CLK
TSEC_1588_TRIG_IN
t
T1588TRIGH
Figure 34. eTSEC IEEE 1588 Input AC timing
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
60
Ethernet Management Interface Electrical Characteristics
The IEEE 1588 AC timing specifications are in Table 43.
Table 43. eTSEC IEEE 1588 AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V 5%.
Parameter/Condition
TSEC_1588_CLK clock period
TSEC_1588_CLK duty cycle
Symbol
Min
Typ
Max
Unit
Note
t
T
*7
TX_CLK
3.8
—
ns
1
T1588CLK
t
—
T1588CLKH
40
50
60
%
/t
T1588CLK
TSEC_1588_CLK peak-to-peak jitter
Rise time eTSEC_1588_CLK (20%–80%)
Fall time eTSEC_1588_CLK (80%–20%)
TSEC_1588_CLK_OUT clock period
TSEC_1588_CLK_OUT duty cycle
t
—
—
—
—
—
—
—
—
—
—
250
2.0
2.0
—
ps
ns
ns
ns
T1588CLKINJ
t
1.0
1.0
T1588CLKINR
t
T1588CLKINF
t
2*t
T1588CLK
T1588CLKOUT
t
T1588CLKOTH
30
50
70
%
/t
T1588CLKOUT
TSEC_1588_PULSE_OUT
TSEC_1588_TRIG_IN pulse width
Note:
t
0.5
—
—
3.0
—
ns
ns
—
2
T1588OV
t
2*t
T1588CLK_MAX
T1588TRIGH
1. When TMR_CTRL[CKSEL]=00, the external TSEC_1588_CLK input is selected as the 1588 timer reference clock source,
with the timing defined in the Table above. The maximum value of t is defined in terms of T , which is the
T1588CLK
TX_CLK
maximum clock cycle period of the equivalent interface speed that the eTSEC1 port is running.
When eTSEC1 is configured to operate in the parallel mode, the T is the maximum clock period of the
TX_CLK
TSEC1_TX_CLK. When eTSEC1 operates in SGMII mode, the maximum value of t
is defined in terms of the
T1588CLK
recovered clock from SGMII SerDes. For example, for 10/100/1000 Mbps modes, the maximum value of t
2800, 280, and 56 ns respectively.
will be
T1588CLK
See the MPC8536E PowerQUICC™ III Integrated Communications Processor Reference Manual for a description of
TMR_CTRL registers.
2. It need to be at least two times of clock period of clock selected by TMR_CTRL[CKSEL]. See the MPC8536E
PowerQUICC™ III Integrated Processor Reference Manual for a description of TMR_CTRL registers.
2.10 Ethernet Management Interface Electrical Characteristics
The electrical characteristics specified here apply to MII management interface signals EC_MDIO (management data
input/output) and EC_MDC (management data clock). The electrical characteristics for GMII, SGMII, RGMII, RMII, TBI and
RTBI are specified in Section 2.9, “Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management”
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
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61
Ethernet Management Interface Electrical Characteristics
2.10.1 MII Management DC Electrical Characteristics
The EC_MDC and EC_MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics for
EC_MDIO and EC_MDC are provided in Table 44.
Table 44. MII Management DC Electrical Characteristics
Parameter
Symbol
OV
Min
Max
Unit
Supply voltage (3.3 V)
Output high voltage
3.13
2.10
3.47
V
V
DD
V
OV + 0.3
OH
DD
(OV = Min, I = –1.0 mA)
DD
OH
Output low voltage
(OV =Min, I = 1.0 mA)
V
GND
0.50
V
OL
DD
OL
Input high voltage
Input low voltage
Input high current
V
2.0
—
—
0.90
40
V
V
IH
V
I
IL
—
μA
IH
1
(OV = Max, V
= 2.1 V)
DD
IN
Input low current
(OV = Max, V = 0.5 V)
I
–600
—
μA
IL
DD
IN
Note:
1. Note that the symbol V , in this case, represents the OV symbol referenced in Table 1 and Table 2.
IN
IN
2.10.2 MII Management AC Electrical Specifications
Table 45 provides the MII management AC timing specifications.
Table 45. MII Management AC Timing Specifications
At recommended operating conditions with OVDD is 3.3 V 5%.
1
Parameter/Condition
EC_MDC frequency
Symbol
Min
Typ
Max
Unit
Notes
f
t
0.74
120
32
2.5
400
—
8.3
1350
—
MHz
ns
2
—
MDC
EC_MDC period
MDC
EC_MDC clock pulse width high
EC_MDC to EC_MDIO delay
EC_MDIO to EC_MDC setup time
t
ns
—
MDCH
t
(16 * t
)-3
—
(16 * t
)+3
ns
3,5,6
—
MDKHDX
plb_clk
plb_clk
t
5
—
—
ns
MDDVKH
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
62
USB
Table 45. MII Management AC Timing Specifications (continued)
At recommended operating conditions with OVDD is 3.3 V 5%.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Notes
EC_MDIO to EC_MDC hold time
EC_MDC rise time
EC_MDC fall time
Notes:
t
0
—
—
—
—
10
10
ns
ns
ns
—
—
—
MDDXKH
t
—
—
MDCR
t
MDHF
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state)
for inputs and t
for outputs. For example, t
(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
MDKHDX
symbolizes management data timing (MD) for the time t
from clock reference (K) high (H) until data outputs (D) are
MDC
invalid (X) or data hold time. Also, t
symbolizes management data timing (MD) with respect to the time data input
MDDVKH
signals (D) reach the valid state (V) relative to the t
clock reference (K) going to the high (H) state or setup time. For rise
MDC
and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. This parameter is dependent on the eTSEC system clock speed, which is half of the Platform Frequency (f
). The actual
CCB
EC_MDC output clock frequency for a specific eTSEC port can be programmed by configuring the MgmtClk bit field of
MPC8536E’s MIIMCFG register, based on the platform (CCB) clock running for the device. The formula is: Platform
Frequency (CCB)/(2*Frequency Divider determined by MIICFG[MgmtClk] encoding selection). For example, if
MIICFG[MgmtClk] = 000 and the platform (CCB) is currently running at 533 MHz, f
= 533/(2*4*8) = 533/64 = 8.3 MHz.
MDC
That is, for a system running at a particular platform frequency (f
), the EC_MDC output clock frequency can be
CCB
programmed between maximum f
= f
/64 and minimum f
= f
/448. See the MPC8536E reference manual’s
MDC
CCB
MDC
CCB
MIIMCFG register section for more detail.
3. This parameter is dependent on the platform clock frequency. The delay is equal to 16 platform clock periods +/-3ns. For
example, with a platform clock of 333MHz, the min/max delay is 48ns +/-3ns. Similarly, if the platform clock is 400MHz, the
min/max delay is 40ns +/-3ns).
5. t
is the platform (CCB) clock
CLKplb_clk
6. EC_MDC to EC_MDIO Data valid t
time - Max Hold)
is a function of clock period and max delay time t
. (Min Setup = Cycle
MDKHDX
MDKHDV
Figure 35 shows the MII management AC timing diagram.
t
t
MDCR
MDC
EC_MDC
t
t
MDCH
MDCF
EC_MDIO
(Input)
t
MDDVKH
t
MDDXKH
EC_MDIO
(Output)
t
MDKHDX
Figure 35. MII Management Interface Timing Diagram
2.11 USB
This section provides the AC and DC electrical specifications for the USB interface of the MPC8536E.
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
63
USB
2.11.1 USB DC Electrical Characteristics
Table 46 provides the DC electrical characteristics for the USB interface.
Table 46. USB DC Electrical Characteristics
Parameter Symbol
Min
Max
Unit
High-level input voltage
Low-level input voltage
Input current
V
2
OV + 0.3
V
V
IH
DD
V
I
–0.3
—
0.8
5
IL
μA
V
IN
High-level output voltage,
V
OV – 0.2
—
OH
DD
I
= –100 μA
OH
Low-level output voltage,
= 100 μA
V
—
0.2
V
OL
I
OL
Note:
1. The symbol V , in this case, represents the OV symbol referenced in Table 1 and Table 2.
IN
IN
2.11.2 USB AC Electrical Specifications
Table 47 describes the general timing parameters of the USB interface of the MPC8536E.
Table 47. USB General Timing Parameters
1
Parameter
usb clock cycle time
Symbol
Min
Max
Unit
Notes
t
15
4
—
—
—
7
ns
ns
ns
ns
ns
2-5
2-5
2-5
2-5
2-5
USCK
Input setup to usb clock - all inputs
input hold to usb clock - all inputs
usb clock to output valid - all outputs
Output hold from usb clock - all outputs
Notes:
t
USIVKH
t
1
USIXKH
t
—
2
USKHOV
USKHOX
t
—
1. The symbols for timing specifications follow the pattern of t
for inputs
(First two letters of functional block)(signal)(state) (reference)(state)
and t
for outputs. For example, t
symbolizes usb timing (US) for
(First two letters of functional block)(reference)(state)(signal)(state)
USIXKH
the input (I) to go invalid (X) with respect to the time the usb clock reference (K) goes high (H). Also, t
symbolizes USB
USKHOX
timing (US) for the USB clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time.
2. All timings are in reference to USB clock.
3. All signals are measured from OV /2 of the rising edge of the USB clock to 0.4 × OV of the signal in question for 3.3 V
DD
DD
signaling levels.
4. Input timings are measured at the pin.
5. For active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the
component pin is less than or equal to that of the leakage current specification.
Figure 36 and Figure 37 provide the AC test load and signals for the USB, respectively.
OV /2
Output
Z = 50 Ω
DD
0
R = 50 Ω
L
Figure 36. USB AC Test Load
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
64
USB
USB0_CLK/USB1_CLK/DR_CLK
Input Signals
t
USIXKH
t
USIVKH
t
t
USKHOX
USKHOV
Output Signals:
Figure 37. USB Signals
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
65
enhanced Local Bus Controller (eLBC)
2.12 enhanced Local Bus Controller (eLBC)
This section describes the DC and AC electrical specifications for the local bus interface of the MPC8536E.
2.12.1 Local Bus DC Electrical Characteristics
Table 48 provides the DC electrical characteristics for the local bus interface operating at BV = 3.3 V DC.
DD
Table 48. Local Bus DC Electrical Characteristics (3.3 V DC)
Parameter
Symbol
Min
Max
Unit
Supply voltage 3.3V
BV
3.13
1.9
3.47
V
V
DD
High-level input voltage
Low-level input voltage
V
BV + 0.3
IH
DD
V
I
–0.3
—
0.8
5
V
IL
Input current
μA
IN
1
(BV
= 0 V or BV = BV
)
DD
IN
IN
High-level output voltage
(BV = min, I = –2 mA)
V
2.4
—
—
V
V
OH
DD
OH
Low-level output voltage
V
0.4
OL
(BV = min, I = 2 mA)
DD
OL
Note:
1. Note that the symbol BV , in this case, represents the BV symbol referenced in Table 1.
IN
IN
Table 49 provides the DC electrical characteristics for the local bus interface operating at BV = 2.5 V DC.
DD
Table 49. Local Bus DC Electrical Characteristics (2.5 V DC)
Parameter
Supply voltage 2.5V
Symbol
Min
Max
Unit
BV
2.37
1.70
–0.3
—
2.63
V
V
DD
High-level input voltage
Low-level input voltage
V
BV + 0.3
IH
DD
V
I
0.7
10
V
IL
Input current
μA
IH
1
(BV
= 0 V or BV = BV
)
IN
IN
DD
I
–15
IL
High-level output voltage
(BV = min, I = –1 mA)
V
2.0
BV + 0.3
V
V
OH
DD
DD
OH
Low-level output voltage
V
GND – 0.3
0.4
OL
(BV = min, I = 1 mA)
DD
OL
Note:
1. Note that the symbol BV , in this case, represents the BV symbol referenced in Table 1.
IN
IN
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
66
enhanced Local Bus Controller (eLBC)
Table 50 provides the DC electrical characteristics for the local bus interface operating at BV = 1.8 V DC.
DD
Table 50. Local Bus DC Electrical Characteristics (1.8 V DC)
Parameter
Supply voltage 1.8V
Symbol
Condition
Min
Max
Unit
BV
—
—
—
—
1.71
0.65*BV
–0.3
1.89
V
V
DD
High-level input voltage
Low-level input voltage
V
0.3+BV
IH
DD
DD
V
I
0.35*BV
10
V
IL
DD
Input current
-15
μA
IN
1
(BV
= 0 V or BV = BV
)
IN
IN
DD
I
= –100 μA
BV – 0.2
—
—
OH
DD
High-level output voltage
V
V
V
OH
I
= –2 mA
BV – 0.45
OH
DD
I
= 100 μA
—
—
0.2
0.45
OH
Low-level output voltage
V
OL
I
= 2 mA
OH
Note:
1. Note that the symbol BV , in this case, represents the BV symbol referenced in Table 1.
IN
IN
2.12.2 Local Bus AC Electrical Specifications
Table 51 describes the general timing parameters of the local bus interface at BV = 3.3 V DC. For information about the
DD
frequency range of local bus see Section 2.23.1, “Clock Ranges.”
Table 51. Local Bus General Timing Parameters (BV = 3.3 V DC)
DD
1
Parameter
Symbol
Min
Max
Unit Notes
Local bus cycle time
Local bus duty cycle
t
7.5
43
12
57
ns
%
2
—
7
LBK
t
t
LBKH/ LBK
tLBKSKEW
150
ps
LCLK[n] skew to LCLK[m] or LSYNC_OUT
Input setup to local bus clock (except LUPWAIT)
LUPWAIT input setup to local bus clock
t
t
t
t
1.8
1.7
1.0
1.0
1.5
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3, 4
3, 4
3, 4
3, 4
6
LBIVKH1
LBIVKH2
LBIXKH1
LBIXKH2
Input hold from local bus clock (except LUPWAIT)
LUPWAIT input hold from local bus clock
—
—
LALE output transition to LAD/LDP output transition (LATCH setup and hold time)
Local bus clock to output valid (except LAD/LDP and LALE)
Local bus clock to data valid for LAD/LDP
t
—
LBOTOT
t
t
t
t
t
2.3
2.4
2.3
2.3
—
—
3
LBKHOV1
LBKHOV2
LBKHOV3
LBKHOV4
LBKHOX1
—
Local bus clock to address valid for LAD
—
3
Local bus clock to LALE assertion
—
3
Output hold from local bus clock (except LAD/LDP and LALE)
0.7
3
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
67
enhanced Local Bus Controller (eLBC)
Table 51. Local Bus General Timing Parameters (BV = 3.3 V DC) (continued)
DD
1
Parameter
Symbol
Min
Max
Unit Notes
Output hold from local bus clock for LAD/LDP
t
0.7
—
—
ns
ns
ns
3
5
5
LBKHOX2
Local bus clock to output high Impedance (except LAD/LDP and LALE)
Local bus clock to output high impedance for LAD/LDP
t
2.5
2.5
LBKHOZ1
LBKHOZ2
t
—
Note:
1. The symbols used for timing specifications herein follow the pattern of t
(First two letters of functional block)(signal)(state) (reference)(state)
for inputs and t
for outputs. For example, t
symbolizes local bus
(First two letters of functional block)(reference)(state)(signal)(state)
LBIXKH1
timing (LB) for the input (I) to go invalid (X) with respect to the time the t
clock reference (K) goes high (H), in this case for
LBK
clock one(1). Also, t
symbolizes local bus timing (LB) for the t
clock reference (K) to go high (H), with respect to the
LBKHOX
LBK
output (O) going invalid (X) or output hold time.
2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.
3. All signals are measured from BV /2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL
DD
bypass mode to 0.4 × BV of the signal in question for 3.3-V signaling levels.
DD
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through
the component pin is less than or equal to the leakage current specification.
6.t
is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBOTOT is guaranteed
LBOTOT
with LBCR[AHD] = 0.
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at BVDD/2.
Table 52 describes the general timing parameters of the local bus interface at BV = 2.5 V DC.
DD
Table 52. Local Bus General Timing Parameters (BV = 2.5 V DC)
DD
1
Parameter
Configuration Symbol
Min
Max
Unit
Notes
Local bus cycle time
Local bus duty cycle
—
—
—
t
7.5
43
—
12
57
ns
%
2
—
7
LBK
t
t
LBKH/ LBK
tLBKSKEW
150
ps
LCLK[n] skew to LCLK[m] or LSYNC_OUT
Input setup to local bus clock (except LUPWAIT)
LUPWAIT input setup to local bus clock
—
—
—
—
—
t
1.9
1.8
1.1
1.1
1.5
—
—
—
—
—
ns
ns
ns
ns
ns
3, 4
3, 4
3, 4
3, 4
6
LBIVKH1
t
LBIVKH2
Input hold from local bus clock (except LUPWAIT)
LUPWAIT input hold from local bus clock
t
LBIXKH1
t
LBIXKH2
LALE output transition to LAD/LDP output transition (LATCH
setup and hold time)
t
LBOTOT
Local bus clock to output valid (except LAD/LDP and LALE)
Local bus clock to data valid for LAD/LDP
—
—
—
—
—
t
t
t
t
t
—
—
2.4
2.5
2.4
2.4
—
ns
ns
ns
ns
ns
—
3
LBKHOV1
LBKHOV2
LBKHOV3
LBKHOV4
LBKHOX1
Local bus clock to address valid for LAD
—
3
Local bus clock to LALE assertion
—
3
Output hold from local bus clock (except LAD/LDP and LALE)
0.8
3
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
68
enhanced Local Bus Controller (eLBC)
Table 52. Local Bus General Timing Parameters (BV = 2.5 V DC) (continued)
DD
1
Parameter
Configuration Symbol
Min
Max
Unit
Notes
Output hold from local bus clock for LAD/LDP
—
—
t
t
0.8
—
—
ns
ns
3
5
LBKHOX2
Local bus clock to output high Impedance (except LAD/LDP
and LALE)
2.6
LBKHOZ1
Local bus clock to output high impedance for LAD/LDP
—
t
—
2.6
ns
5
LBKHOZ2
Note:
1. The symbols used for timing specifications herein follow the pattern of t
(First two letters of functional block)(signal)(state) (reference)(state)
for inputs and t
for outputs. For example, t
symbolizes local bus
(First two letters of functional block)(reference)(state)(signal)(state)
LBIXKH1
timing (LB) for the input (I) to go invalid (X) with respect to the time the t
clock reference (K) goes high (H), in this case for
LBK
clock one(1). Also, t
symbolizes local bus timing (LB) for the t
clock reference (K) to go high (H), with respect to the
LBKHOX
LBK
output (O) going invalid (X) or output hold time.
2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.
3. All signals are measured from BV /2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL
DD
bypass mode to 0.4 × BV of the signal in question for 2.5-V signaling levels.
DD
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through
the component pin is less than or equal to the leakage current specification.
6. t
is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBOTOT is guaranteed
LBOTOT
with LBCR[AHD] = 0.
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at BVDD/2.
Table 53 describes the general timing parameters of the local bus interface at BV = 1.8 V DC
DD
Table 53. Local Bus General Timing Parameters (BV = 1.8 V DC)
DD
1
Parameter
Configuration Symbol
Min
Max
Unit
Notes
Local bus cycle time
Local bus duty cycle
—
—
—
t
7.5
43
12
57
ns
%
2
LBK
t
t
LBKH/ LBK
tLBKSKEW
150
ps
7
LCLK[n] skew to LCLK[m] or LSYNC_OUT
Input setup to local bus clock (except LUPWAIT)
LUPWAIT input setup to local bus clock
—
—
—
—
—
t
t
t
t
2.4
1.9
1.1
1.1
1.2
—
—
—
—
—
ns
ns
ns
ns
ns
3, 4
3, 4
3, 4
3, 4
6
LBIVKH1
LBIVKH2
LBIXKH1
LBIXKH2
Input hold from local bus clock (except LUPWAIT)
LUPWAIT input hold from local bus clock
LALE output transition to LAD/LDP output transition (LATCH
setup and hold time)
t
LBOTOT
Local bus clock to output valid (except LAD/LDP and LALE)
Local bus clock to data valid for LAD/LDP
—
—
—
—
—
t
t
t
t
t
—
—
3.2
3.2
3.2
3.2
—
ns
ns
ns
ns
ns
—
3
LBKHOV1
LBKHOV2
LBKHOV3
LBKHOV4
LBKHOX1
Local bus clock to address valid for LAD
—
3
Local bus clock to LALE assertion
—
3
Output hold from local bus clock (except LAD/LDP and LALE)
0.9
3
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
69
enhanced Local Bus Controller (eLBC)
Table 53. Local Bus General Timing Parameters (BV = 1.8 V DC) (continued)
DD
1
Parameter
Configuration Symbol
Min
Max
Unit
Notes
Output hold from local bus clock for LAD/LDP
—
—
t
t
0.9
—
—
ns
ns
3
5
LBKHOX2
Local bus clock to output high Impedance (except LAD/LDP
and LALE)
2.6
LBKHOZ1
Local bus clock to output high impedance for LAD/LDP
—
t
—
2.6
ns
5
LBKHOZ2
Note:
1. The symbols used for timing specifications herein follow the pattern of t
(First two letters of functional block)(signal)(state) (reference)(state)
for inputs and t
for outputs. For example, t
symbolizes local bus
(First two letters of functional block)(reference)(state)(signal)(state)
LBIXKH1
timing (LB) for the input (I) to go invalid (X) with respect to the time the t
clock reference (K) goes high (H), in this case for
LBK
clock one(1). Also, t
symbolizes local bus timing (LB) for the t
clock reference (K) to go high (H), with respect to the
LBKHOX
LBK
output (O) going invalid (X) or output hold time.
2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.
3. All signals are measured from BV /2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL
DD
bypass mode to 0.4 × BV of the signal in question for 1.8-V signaling levels.
DD
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through
the component pin is less than or equal to the leakage current specification.
6. t
is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBOTOT is guaranteed
LBOTOT
with LBCR[AHD] = 0.
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at BVDD/2.
Figure 38 provides the AC test load for the local bus.
Figure 38. Local Bus AC Test Load
BV /2
Output
Z = 50 Ω
DD
0
R = 50 Ω
L
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
70
enhanced Local Bus Controller (eLBC)
Figure 39 to Figure 42 show the local bus signals.
LSYNC_IN
t
t
LBIXKH1
LBIXKH2
t
t
LBIVKH1
Input Signals:
LAD[0:31]/LDP[0:3]
LBIVKH2
Input Signal:
LGTA
UPM Mode Input Signal:
LUPWAIT
t
LBKHOZ1
LBKHOX1
t
t
t
LBKHOV1
Output Signals:
LA[27:31]/LBCTL/LOE
t
LBKHOZ2
LBKHOX2
t
t
LBKHOV2
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
t
LBKHOZ2
t
LBKHOV3
LBKHOX2
Output (Address) Signal:
LAD[0:31]
t
LBOTOT
t
LBKHOV4
LALE
Figure 39. Local Bus Signals, Non-Special Signals Only (PLL Enabled)
NOTE
In PLL bypass mode, some signals are launched and captured on the opposite edge of
LCLK[n] to that used in PLL Enable Mode. In this mode, output signals are launched at the
falling edge of the LCLK[n] and inputs signals are captured at the rising edge of LCLK[n]
with the exception of LGTA/LUPWAIT (which is captured at the falling edge of the
LCLK[n]).
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
71
enhanced Local Bus Controller (eLBC)
LCLK[n]
t
LBIVKH1
t
LBIXKH1
Input Signals:
LAD[0:31]/LDP[0:3]
Input Signal:
LGTA
t
LBIXKL2
t
LBIVKL2
UPM Mode Input Signal:
LUPWAIT
t
LBKLOV1
t
LBKLOZ1
t
LBKLOX1
Output Signals:
LA[27:31]/LBCTL/LOE
t
LBKLOZ2
t
LBKLOV2
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
t
t
LBKLOX2
LBKLOV3
Output (Address) Signal:
LAD[0:31]
t
t
LBOTOT
LBKLOV4
LALE
Figure 40. Local Bus Signals (PLL Bypass Mode)
Table 54 describes the general timing parameters of the local bus interface at V = 3.3 V DC with PLL disabled.
DD
Table 54. Local Bus General Timing Parameters—PLL Bypassed
1
Parameter
Symbol
Min
Max
Unit Notes
Local bus cycle time
Local bus duty cycle
t
12
43
—
57
—
—
—
—
—
0.5
ns
%
2
LBK
t
t
—
LBKH/ LBK
Input setup to local bus clock (except LUPWAIT)
LUPWAIT input setup to local bus clock
t
5.1
4.2
-1.4
-2.0
1.4
—
ns
ns
ns
ns
ns
ns
4, 5
4, 5
4, 5
4, 5
6
LBIVKH1
t
LBIVKL2
t
LBIXKH1
Input hold from local bus clock (except LUPWAIT)
LUPWAIT input hold from local bus clock
t
LBIXKL2
LALE output transition to LAD/LDP output transition (LATCH hold time)
Local bus clock to output valid (except LAD/LDP and LALE)
t
LBOTOT
t
4
LBKLOV1
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
72
enhanced Local Bus Controller (eLBC)
Table 54. Local Bus General Timing Parameters—PLL Bypassed (continued)
1
Parameter
Local bus clock to data valid for LAD/LDP
Symbol
Min
Max
Unit Notes
t
t
t
t
t
t
t
—
—
—
—
—
—
—
0.5
0.5
0.5
2.2
2.2
0.1
0.1
ns
ns
ns
ns
ns
ns
ns
4
4
LBKLOV2
Local bus clock to address valid for LAD, and LALE
Local bus clock to LALE assertion
LBKLOV3
LBKLOV4
LBKLOX1
LBKLOX2
LBKLOZ1
LBKLOZ2
4
Output hold from local bus clock (except LAD/LDP and LALE)
Output hold from local bus clock for LAD/LDP
4,8
4,8
7
Local bus clock to output high Impedance (except LAD/LDP and LALE)
Local bus clock to output high impedance for LAD/LDP
7
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
(First two letters of functional block)(signal)(state) (reference)(state)
for inputs and t
for outputs. For example, t
symbolizes local bus
(First two letters of functional block)(reference)(state)(signal)(state)
LBIXKH1
timing (LB) for the input (I) to go invalid (X) with respect to the time the t
clock reference (K) goes high (H), in this case for
LBK
clock one(1). Also, t
symbolizes local bus timing (LB) for the t
clock reference (K) to go high (H), with respect to the
LBKHOX
LBK
output (O) going invalid (X) or output hold time.
2. All timings are in reference to local bus clock for PLL bypass mode.
3. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at BV /2.
DD
4. All signals are measured from BVDD/2 of the rising edge of local bus clock for PLL bypass mode to 0.4 x BVDD of the signal
in question for 3.3-V signaling levels.
5. Input timings are measured at the pin.
6. t
is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBOTOT is guaranteed
LBOTOT
with LBCR[AHD] = 0.
7. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through
the component pin is less than or equal to the leakage current specification.
8. These timing parameters for PLL bypass mode are defined in the opposite direction of the PLL enabled output hold timing
parameters.
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
73
enhanced Local Bus Controller (eLBC)
LSYNC_IN
T1
T3
t
LBKHOZ1
t
LBKHOV1
GPCM Mode Output Signals:
LCS[0:7]/LWE
GPCM Mode Input Signal:
LGTA
t
LBIXKH2
t
LBIVKH2
UPM Mode Input Signal:
LUPWAIT
t
LBIXKH1
t
LBIVKH1
Input Signals:
LAD[0:31]/LDP[0:3]
t
LBKHOZ1
t
LBKHOV1
UPM Mode Output Signals:
LCS[0:7]/LBS[0:3]/LGPL[0:5]
Figure 41. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4(PLL Enabled)
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
74
Enhanced Secure Digital Host Controller (eSDHC)
LSYNC_IN
T1
T2
T3
T4
t
LBKHOZ1
t
LBKHOV1
GPCM Mode Output Signals:
LCS[0:7]/LWE
GPCM Mode Input Signal
LGTA
t
LBIXKH2
t
LBIVKH2
UPM Mode Input Signal:
LUPWAIT
t
LBIXKH1
t
LBIVKH1
Input Signals:
LAD[0:31]/LDP[0:3]
(PLL Bypass Mode)
t
LBKHOZ1
t
LBKHOV1
UPM Mode Output Signals:
LCS[0:7]/LBS[0:3]/LGPL[0:5]
Figure 42. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 8 or 16(PLL Enabled)
2.13 Enhanced Secure Digital Host Controller (eSDHC)
This section describes the DC and AC electrical specifications for the eSDHC interface of the MPC8536E.
2.13.1 eSDHC DC Electrical Characteristics
Table 55 provides the DC electrical characteristics for the eSDHC interface of the MPC8536E.
Table 55. eSDHC interface DC Electrical Characteristics
At recommended operating conditions (see Table 3)
Characteristic
Input high voltage
Symbol
Condition
Min
Max
Unit
Notes
V
—
—
—
0.625 * OVDD
–0.3
OVDD+0.3
V
V
—
—
—
—
IH
Input low voltage
V
0.25 * OVDD
IL
Input/Output leakage current
Output high voltage
I /I
–10
10
—
uA
V
IN OZ
V
I
= -100 uA @OVDDmin 0.75 * OVDD
OH
OH
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
75
Enhanced Secure Digital Host Controller (eSDHC)
Table 55. eSDHC interface DC Electrical Characteristics (continued)
At recommended operating conditions (see Table 3)
Characteristic
Symbol
Condition
Min
Max
Unit
Notes
Output low voltage
Output high voltage
Output low voltage
Notes:
V
I
= 100uA @OVDDmin
OL
—
0.125 * OVDD
V
—
2
OL
V
I
= -100 uA
OV - 0.2
—
—
—
OH
OH
DD
V
I
= 2 mA
OL
—
0.3
2
OL
1. The min V and V values are based on the respective min and max OV values found in Table 3.
IL
IH
IN
2. Open drain mode for MMC cards only.
2.13.2 eSDHC AC Timing Specifications
Table 56 provides the eSDHC AC timing specifications as defined in Figure 44.
Table 56. eSDHC AC Timing Specifications
At recommended operating conditions (see Table 3)
1
Parameter
SD_CLK clock frequency:
Symbol
Min
Max
Unit
Notes
f
MHz
2, 5
SHSCK
SD/SDIO Full speed/high speed mode
MMC Full speed/high speed mode
0
25/50
20/52
SD_CLK clock frequency - identification mode
f
0
400
KHz
3, 5
SIDCK
100
SD_CLK clock low time - High speed/Full speed mode
SD_CLK clock high time - High speed/Full speed mode
SD_CLK clock rise and fall times
t
7/10
7/10
—
—
—
3
ns
ns
ns
5
5
5
SHSCKL
t
SHSCKH
t
SHSCKR/
t
SHSCKF
Input setup times: SD_CMD, SD_DATx, SD_CD to
SD_CLK
t
5
—
ns
5
SHSIVKH
Input hold times: SD_CMD, SD_DATx, SD_CD to SD_CLK
Output delay time: SD_CLK to SD_CMD, SD_DATx valid
Notes:
t
2.5
–3
—
3
ns
ns
4,5
5
SHSIXKH
t
SHSKHOV
1. The symbols used for timing specifications herein follow the pattern of t
(first three letters of functional block)(signal)(state) (reference)(state)
for inputs and t
for outputs. For example, t
symbolizes eSDHC
(first three letters of functional block)(reference)(state)(signal)(state)
FHSKHOV
high speed mode device timing (SHS) clock reference (K) going to the high (H) state, with respect to the output (O) reaching
the invalid state (X) or output hold time. Note that, in general, the clock reference symbol representation is based on five letters
representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter:
R (rise) or F (fall).
2. In full speed mode, clock frequency value can be 0–25 MHz for a SD/SDIO card and 0–20 MHz for a MMC card. In high speed
mode, clock frequency value can be 0–50 MHz for a SD/SDIO card and 0–52MHz for a MMC card.
3. 0 Hz means to stop the clock. The given minimum frequency range is for cases were a continuous clock is required.
4. To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2ns.
5. C
≤10 pF, (1 card), and C = C
+ C
+C
≤ 40 pF
CARD
CARD
L
BUS
HOST
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
76
Programmable Interrupt Controller (PIC)
Figure 43 provides the eSDHC clock input timing diagram.
eSDHC
External Clock
VM
VM
VM
operational mode
t
t
SHSCKL
SHSCKH
t
SHSCK
t
SHSCKF
t
SHSCKR
VM = Midpoint Voltage (OV /2)
DD
Figure 43. eSDHC Clock Input Timing Diagram
Figure 44 provides the data and command input/output timing diagram.
VM
VM
VM
VM
SD_CK
External Clock
t
t
SHSIXKH
SHSIVKH
SD_DAT/CMD
Inputs
SD_DAT/CMD
Outputs
t
SHSKHOV
VM = Midpoint Voltage (OV /2)
DD
Figure 44. eSDHC Data and Command Input/Output Timing Diagram Referenced to Clock
2.14 Programmable Interrupt Controller (PIC)
In IRQ edge trigger mode, when an external interrupt signal is asserted (according to the programmed polarity), it must remain
the assertion for at least 3 system clocks (SYSCLK periods).
2.15 JTAG
This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the MPC8536E.
2.15.1 JTAG DC Electrical Characteristics
Table 57 provides the DC electrical characteristics for the JTAG interface.
Table 57. JTAG DC Electrical Characteristics
1
Parameter
Symbol
Min
Max
Unit
High-level input voltage
Low-level input voltage
V
2
OV + 0.3
V
V
IH
DD
V
-0.3
0.8
IL
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
77
JTAG
Table 57. JTAG DC Electrical Characteristics (continued)
1
Parameter
Input current
Symbol
Min
Max
Unit
I
—
5
μA
IN
1
(V
= 0 V or V = V
)
IN
IN
DD
High-level output voltage
(OV = min, I = -2 mA)
V
2.4
—
—
V
V
OH
DD
OH
Low-level output voltage
V
0.4
OL
(OV = min, I = 2 mA)
DD
OL
Notes:
1. Note that the symbol V , in this case, represents the OV
IN
IN.
2.15.2 JTAG AC Electrical Specifications
This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the MPC8536E.
Table 58 provides the JTAG AC timing specifications as defined in Figure 45 through Figure 48.
Table 58. JTAG AC Timing Specifications (Independent of SYSCLK)
At recommended operating conditions (see Table 3).
1
Parameter
Symbol
Min
Max
Unit
Notes
JTAG external clock frequency of operation
JTAG external clock cycle time
JTAG external clock pulse width measured at 1.4 V
JTAG external clock rise and fall times
TRST assert time
f
0
30
15
0
33.3
—
—
2
MHz
ns
—
—
—
—
2
JTG
JTG
t
t
ns
JTKHKL
t
& t
ns
JTGR
JTGF
t
25
4
—
—
—
10
—
ns
TRST
Input setup times:
t
t
ns
JTDVKH
JTDXKH
Input hold times:
10
—
0
ns
Output Valid times:
t
ns
3
3
JTKLDV
Output hold times:
t
ns
JTKLDX
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t
for outputs. For example, t
symbolizes JTAG
(first two letters of functional block)(reference)(state)(signal)(state)
JTDVKH
device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t
clock reference
JTG
(K) going to the high (H) state or setup time. Also, t
symbolizes JTAG timing (JT) with respect to the time data input
JTDXKH
signals (D) went invalid (X) relative to the t
clock reference (K) going to the high (H) state. Note that, in general, the clock
JTG
reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
3.) The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load. Time-of-flight delays
must be added for trace lengths, vias, and connectors in the system.
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Freescale Semiconductor
Serial ATA (SATA)
Figure 45 provides the AC test load for TDO and the boundary-scan outputs.
Z = 50 Ω
Output
OV /2
0
DD
R = 50 Ω
L
Figure 45. AC Test Load for the JTAG Interface
Figure 46 provides the JTAG clock input timing diagram.
JTAG
External Clock
VM
t
VM
VM
t
JTGR
JTKHKL
t
t
JTG
JTGF
VM = Midpoint Voltage (OV /2)
DD
Figure 46. JTAG Clock Input Timing Diagram
Figure 47 provides the TRST timing diagram.
TRST
VM
VM
t
TRST
VM = Midpoint Voltage (OV /2)
DD
Figure 47. TRST Timing Diagram
Figure 48 provides the boundary-scan timing diagram.
JTAG
VM
VM
External Clock
t
JTDVKH
t
JTDXKH
Boundary
Data Inputs
Input
Data Valid
t
JTKLDV
t
JTKLDX
Boundary
Data Outputs
Output Data Valid
VM = Midpoint Voltage (OV /2)
DD
Figure 48. Boundary-Scan Timing Diagram
2.16 Serial ATA (SATA)
This section describes the DC and AC electrical specifications for the serial ATA (SATA) of the MPC8536E. Note that the
external cabled applications or long backplane applications (Gen1x & Gen2x) are not supported.
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
79
Serial ATA (SATA)
2.16.1 Requirements for SATA REF_CLK
The AC requirements for the SATA reference clock are listed in Table 59.
Table 59. Reference Clock Input Requirements
Parameter
Symbol
Min
Typical
Max
Unit
Notes
SD2_REF_CLK/_B reference clock cycle time
SD2_REF_CLK/_B frequency tolerance
SD_REF_CLK/_B rise/fall time (80%-20%)
SD_REF_CLK/_B duty cycle (@50% X2VDD)
SD_REF_CLK/_B cycle to cycle clock jitter (period jitter)
SD_REF_CLK/_B phase jitter (peak-to-peak)
Note:
t
100
–350
—
—
0
150
+350
1
MHz
ppm
ns
1
—
—
—
—
2,3
CLK_REF
t
CLK_TOL
t
/t
—
50
—
—
CLK_RISE CLK_FALL
t
45
55
%
CLK_DUTY
t
t
—
100
+50
ps
CLK_CJ
–50
ps
CLK_PJ
1. Only 100/125/150 MHz have been tested, other in between values will not work correctly with the rest of the system.
2. In a frequency band from 150 kHz to 15 MHz, at BER of 10E-12.
3. Total peak-to-peak deterministic jitter “Dj” should be less than or equal to 50 ps.
T
H
Ref_CLK
T
L
Figure 49. Reference Clock Timing Waveform
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
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Serial ATA (SATA)
2.16.2 Differential Transmitter (TX) Output Characteristics
Table 60 provides the differential transmitter (TX) output characteristics for the SATA interface.
Table 60. Differential Transmitter (TX) Output Characteristics
Parameter
Channel Speed
Symbol
Min
Typical
Max
Units
Notes
—
1.5G
3.0G
t
—
1.5
3.0
—
Gbps
CH_SPEED
Unit Interval
1.5G
3.0G
—
T
666.4333
333.2167
666.4333
333.3333
670.2333
335.1167
ps
UI
DC Coupled
Common Mode
Voltage
V
200
250
450
mV
mV
3
dc_cm
TX Diff Output Voltage
1.5G
3.0G
—
V
400
400
500
—
600
700
SATA_TXDIFF
TX rise/fall time
1.5G
3.0G
—
t
100
67
—
—
273
136
ps
ps
SATA_20-80TX
TX differential skew
t
—
85
40
—
—
—
20
115
—
—
—
SATA_TXSKEW
TX Differential pair
impedance
1.5G
Z
ohm
SATA_TXDIFFIM
TX Single ended
impedance
1.5G
—
—
Z
ohm
SATA_TXSEIM
TX AC common mode
voltage (peak to peak)
1.5G
V
—
—
—
—
—
50
mV
SATA_TXCMMOD
3.0G
OOB Differential Delta
V
—
—
—
—
25
50
mV
mV
1
1
SATA_OOBvdoff
OOB Common mode
Delta
V
SATA_OOBcm
TX Rise/Fall Imbalance
TX Amplitude Imbalance
T
—
—
—
—
20
10
%
%
—
—
SATA_TXR/Fbal
T
SATA_TXampbal
TX Differential Mode
Return loss
150 MHz - 300 MHz
300 MHz - 600 MHz
600 MHz - 1.2 GHz
—
—
—
—
—
—
14
8
6
1, 2
RL
dB
SATA_TXDD11
1.2 GHz - 2.4 GHz
2.4 GHz - 3.0 GHz
3.0 GHz - 5.0 GHz
6
3
1
—
—
—
—
—
—
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
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Serial ATA (SATA)
Table 60. Differential Transmitter (TX) Output Characteristics (continued)
Parameter
Symbol
Min
Typical
Max
Units
Notes
TX Common Mode Return
loss
150 MHz - 300 MHz
300 MHz - 600 MHz
600 MHz - 1.2 GHz
—
—
—
—
—
—
5
5
2
1, 2
RL
dB
SATA_TXCC11
1.2 GHz - 2.4 GHz
2.4 GHz - 3.0 GHz
3.0 GHz - 5.0 GHz
—
—
—
—
—
—
2
1
1
TX Impedance Balance
150 MHz - 300 MHz
300 MHz - 600 MHz
600 MHz - 1.2 GHz
—
—
—
—
—
—
30
20
10
1, 2
dB
RL
SATA_TXDC11
1.2 GHz - 2.4 GHz
2.4 GHz - 3.0 GHz
3.0 GHz - 5.0 GHz
—
—
—
—
—
—
10
4
4
Deterministic jitter
1.5G
3.0G
—
—
U
—
—
—
—
0.18
0.14
UI
UI
SATA_TXDJ
Total Jitter
1.5G
3.0G
U
0.42
0.32
SATA_TXTJ
Notes:
1. Only applies when operating in 3.0Gb data rate mode.
2. The max value stated for 3.0 GHz - 5.0 GHz range only applies to Gen2i mode and not to Gen2m mode.
3. Only applies to Gen1i mode.
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Freescale Semiconductor
Serial ATA (SATA)
80%
80%
Differential
data lines
20%
20%
t
SATA_20-80TXfall
t
SATA_20-80TXrise
TX+
TX-
TX+
TX-
t
SAT_TXSKEW
t
SAT_TXSKEW
EARLY (TX+ is early)
Figure 50. Signal Rise and Fall Times and Differential Skew
LATE (TX+ is late)
2.16.3 Differential Receiver (RX) Input Characteristics
Table 61 provides the differential receiver (RX) input characteristics for the SATA interface.
Table 61. Differential Receiver (RX) Input Characteristics
Parameter
Symbol
Min
Typical
Max
Units
Notes
RX Differential Input
Voltage
1.5G
3.0G
V
1
SATA_RXDIFF
240
240
400
—
600
750
mVp-p
ps
RX rise/fall time
1.5G
3.0G
—
—
—
—
5
t
100
67
—
—
273
136
SATA_20-80RX
RX Differential skew
1.5G
3.0G
t
—
—
—
—
—
50
SATA_RXSKEW
ps
RX Differential pair
impedance
1.5G
Z
85
—
115
ohm
ohm
SATA_RXDIFFIM
RX Single-Ended
impedance
1.5G
Z
SATA_RXSEIM
40
—
—
DC Coupled
Common Mode
Voltage
V
200
250
450
mV
dc_cm
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
83
Serial ATA (SATA)
Table 61. Differential Receiver (RX) Input Characteristics (continued)
Parameter
Symbol
Min
Typical
Max
Units
Notes
RX Differential Mode
Return loss
2, 3
150 MHz - 300 MHz
300 MHz - 600 MHz
600 MHz - 1.2 GHz
—
—
—
—
—
—
18
14
10
RL
dB
SATA_RXDD11
1.2 GHz - 2.4 GHz
2.4 GHz - 3.0 GHz
3.0 GHz - 5.0 GHz
—
—
—
—
—
—
8
3
1
RX Common Mode
Return loss
2, 3, 4
150 MHz - 300 MHz
300 MHz - 600 MHz
600 MHz - 1.2 GHz
—
—
—
—
—
—
5
5
2
RL
dB
SATA_RXCC11
1.2 GHz - 2.4 GHz
2.4 GHz - 3.0 GHz
3.0 GHz - 5.0 GHz
—
—
—
—
—
—
2
2
1
RX Impedance Balance
2, 3
150 MHz - 300 MHz
300 MHz - 600 MHz
600 MHz - 1.2 GHz
—
—
—
—
—
—
30
30
20
dB
RL
SATA_RXDC11
1.2 GHz - 2.4 GHz
2.4 GHz - 3.0 GHz
3.0 GHz - 5.0 GHz
—
—
—
—
—
—
10
4
4
Deterministic jitter
1.5G
3.0G
—
—
U
—
—
—
—
0.4
0.47
UI
UI
SATA_RXDJ
SATA_RXTJ
Total Jitter
1.5G
3.0G
U
0.65
0.65
Notes:
1. The min values apply only to Gen1m, and Gen2m. the min values for Gen1i is 325 mVp-p and for Gen2i is 275 mVp-p.
2. Only applies when operating in 3.0Gb data rate mode.
3. The max value stated for 3.0 GHz - 5.0 GHz range only applies to Gen2i mode and not to Gen2m mode.
4. The max value stated for 2.4 GHz - 3.0 GHz range only applies to Gen2i mode for Gen2m the value is 1.
5. Only applies to Gen1i mode.
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Freescale Semiconductor
2
I C
2.16.4 Out-of-Band (OOB) Electrical Characteristics
Table 62 provides the Out-of-Band (OOB) electrical characteristics for the SATA interface of the MPC8536E.
Table 62. Out-of-Band (OOB) Electrical Characteristics
Parameter
Symbol
Min
Typical
Max
Units
Notes
OOB Signal Detection Threshold
—
1.5G
3.0G
V
50
75
100
125
200
200
mVp-p
ps
SATA_OOBDETE
UI During OOB Signaling
T
646.67
666.67
686.67
—
—
SATA_UIOOB
COMINIT/ COMRESET and COMWAKE
Transmit Burst Length
T
—
160
—
UI
SATA_UIOOBTXB
COMINIT/ COMRESET Transmit Gap Length T
—
SATA_UIOOBTXG
ap
—
480
—
UI
COMWAKE Transmit Gap Length
COMWAKE Gap Detection Windows
T
—
—
—
SATA_UIOOBTX
WakeGap
—
55
160
—
—
UI
ns
T
175
SATA_OOBDet
WakeGap
COMINIT/ COMRESET
Gap Detection Windows
T
175
—
525
ns
SATA_OOBDet
COMGap
2
2.17 I C
2
This section describes the DC and AC electrical characteristics for the I C interfaces of the MPC8536E.
2.17.1 I2C DC Electrical Characteristics
2
Table 63 provides the DC electrical characteristics for the I C interfaces.
2
Table 63. I C DC Electrical Characteristics
At recommended operating conditions with OVDD of 3.3 V 5%.
Parameter
Symbol
Min
Max
Unit
Notes
Supply voltage 3.3 V
Input high voltage level
Input low voltage level
Low level output voltage
OV
V
3.13
0.7 × OV
–0.3
3.47
V
V
V
V
—
—
—
1
DD
OV + 0.3
IH
DD
DD
V
0.3 × OV
IL
DD
V
0
0.2 × OV
OL
DD
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
85
2
I C
2
Table 63. I C DC Electrical Characteristics (continued)
At recommended operating conditions with OVDD of 3.3 V 5%.
Parameter
Symbol
Min
Max
Unit
Notes
Pulse width of spikes which must be suppressed by the input
filter
t
0
50
ns
2
I2KHKL
Input current each I/O pin (input voltage is between 0.1 ×
OV and 0.9 × OV (max)
I
–10
—
10
10
μA
3
I
DD
DD
Capacitance for each I/O pin
C
pF
—
I
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. See the MPC8536E PowerQUICC III Integrated Processor Reference Manual for information on the digital filter used.
3. I/O pins will obstruct the SDA and SCL lines if OV is switched off.
DD
2.17.2 I2C AC Electrical Specifications
2
Table 64 provides the AC timing parameters for the I C interfaces.
2
Table 64. I C AC Electrical Specifications
All values refer to VIH (min) and VIL (max) levels (see Table 63).
1
Parameter
Symbol
Min
Max
Unit
Notes
SCL clock frequency
f
0
400
—
kHz
μs
—
—
—
—
—
I2C
Low period of the SCL clock
High period of the SCL clock
Setup time for a repeated START condition
t
1.3
0.6
0.6
0.6
I2CL
I2CH
t
—
μs
t
t
—
μs
I2SVKH
Hold time (repeated) START condition (after this period, the first
clock pulse is generated)
t
—
μs
I2SXKL
Data setup time
100
—
ns
—
2
I2DVKH
Data hold time:
t
μs
I2DXKL
I2OVKL
CBUS compatible masters
—
0
—
—
2
I C bus devices
Data output delay time
t
—
0.6
—
0.9
—
—
μs
ns
ns
3
—
4
Set-up time for STOP condition
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
t
I2PVKH
t
300
300
I2CR
t
—
4
I2CF
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
86
2
I C
2
Table 64. I C AC Electrical Specifications (continued)
All values refer to VIH (min) and VIL (max) levels (see Table 63).
1
Parameter
Symbol
Min
Max
Unit
Notes
Bus free time between a STOP and START condition
t
1.3
—
—
μs
—
—
I2KHDX
Noise margin at the LOW level for each connected device
(including hysteresis)
V
0.1 × OV
V
NL
DD
DD
Noise margin at the HIGH level for each connected device
(including hysteresis)
V
0.2 × OV
—
V
—
NH
Note:
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state)
2
for inputs and t
for outputs. For example, t
symbolizes I C timing
(first two letters of functional block)(reference)(state)(signal)(state)
I2DVKH
(I2) with respect to the time data input signals (D) reach the valid state (V) relative to the t
clock reference (K) going to the
I2C
2
high (H) state or setup time. Also, t
(S) went invalid (X) relative to the t
symbolizes I C timing (I2) for the time that the data with respect to the start condition
clock reference (K) going to the low (L) state or hold time. Also, t
I2SXKL
2
symbolizes I C
I2C
I2PVKH
timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the t
clock
I2C
reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
2. As a transmitter, the MPC8536E provides a delay time of at least 300 ns for the SDA signal (referred to the Vihmin of the SCL
signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of Start or Stop condition.
2
When the MPC8536E acts as the I C bus master while transmitting, the MPC8536E drives both SCL and SDA. As long as the
load on SCL and SDA are balanced, the MPC8536E would not cause unintended generation of Start or Stop condition.
Therefore, the 300 ns SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time
is required for the MPC8536E as transmitter, the following setting is recommended for the FDR bit field of the I2CFDR register
2
2
to ensure both the desired I C SCL clock frequency and SDA output delay time are achieved, assuming that the desired I C
SCL clock frequency is 400 KHz and the Digital Filter Sampling Rate Register (I2CDFSRR) is programmed with its default
setting of 0x10 (decimal 16):
2
I C Source Clock Frequency
FDR Bit Setting
333 MHz 266 MHz
200 MHz
0x26
133 MHz
0x00
0x2A
896
0x05
Actual FDR Divider Selected
704
512
384
2
Actual I C SCL Frequency Generated 371 KHz
378 KHz
390 KHz
346 KHz
2
2
For details of the I C frequency calculation, refer to Determining the I C Frequency Divider Ratio for SCL (AN2919). Note that
2
the I C Source Clock Frequency is half of the CCB clock frequency for the MPC8536E.
3. The maximum t
has only to be met if the device does not stretch the LOW period (t
) of the SCL signal.
I2CL
I2DVKH
4. C = capacitance of one bus line in pF.
B
2
Figure 51 provides the AC test load for the I C.
OV /2
Output
Z = 50 Ω
DD
0
R = 50 Ω
L
2
Figure 51. I C AC Test Load
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
87
GPIO
2
Figure 52 shows the AC timing diagram for the I C bus.
SDA
t
t
t
t
I2CF
I2CF
I2DVKH
I2KHKL
t
t
t
I2CR
I2CL
I2SXKL
SCL
t
t
t
t
I2PVKH
I2SXKL
I2CH
I2SVKH
t
t
I2DXKL, I2OVKL
S
Sr
P
S
2
Figure 52. I C Bus AC Timing Diagram
2.18 GPIO
This section describes the DC and AC electrical specifications for the GPIO interface of the MPC8536E.
2.18.1 GPIO DC Electrical Characteristics
Table 65 provides the DC electrical characteristics for the GPIO interface.
Table 65. GPIO DC Electrical Characteristics
Parameter
High-level input voltage
Symbol
Min
Max
Unit
V
2
OV + 0.3
V
V
IH
DD
Low-level input voltage
V
I
– 0.3
—
0.8
5
IL
Input current
μA
IN
1
(V
= 0 V or V = V
IN
IN DD)
High-level output voltage
(OV = min, I = –2 mA)
V
2.4
—
—
V
V
OH
DD
OH
Low-level output voltage
(OV = min, I = 2 mA)
V
0.4
OL
DD
OL
Note:
1. Note that the symbol V , in this case, represents the OV symbol referenced in Table 1 and Table 2.
IN
IN
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
88
PCI
2.18.2 GPIO AC Electrical Specifications
Table 66 provides the GPIO input and output AC timing specifications.
1
Table 66. GPIO Input and Output AC Timing Specifications
2
Characteristic
GPIO inputs—minimum pulse width
Symbol
Min
Unit
Notes
t
7.5
12
ns
ns
3
PIWID
GPIO outputs—minimum pulse width
t
—
GTOWID
Notes:
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings
are measured at the pin.
2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any
external synchronous logic. GPIO inputs are required to be valid for at least t
ns to ensure proper operation.
PIWID
3. The minimum pulse width is a function of the MPX/Platform clock. The minimum pulse width must be greater than or equal
to 4 times the MPX/Platform clock period.
Figure 53 provides the AC test load for the GPIO.
OV /2
Output
Z = 50 Ω
DD
0
R = 50 Ω
L
Figure 53. GPIO AC Test Load
2.19 PCI
This section describes the DC and AC electrical specifications for the PCI bus of the MPC8536E.
2.19.1 PCI DC Electrical Characteristics
Table 67 provides the DC electrical characteristics for the PCI interface.
1
Table 67. PCI DC Electrical Characteristics
Parameter
High-level input voltage
Symbol
Min
Max
Unit
V
2
OV + 0.3
V
V
IH
DD
Low-level input voltage
V
I
–0.3
—
0.8
5
IL
Input current
μA
IN
2
(V
= 0 V or V = V
)
DD
IN
IN
High-level output voltage
(OV = min, I = –2 mA)
V
2.4
—
—
V
V
OH
DD
OH
Low-level output voltage
V
0.4
OL
(OV = min, I = 2 mA)
DD
OL
Notes:
1. Ranges listed do not meet the full range of the DC specifications of the PCI 2.2 Local Bus Specifications.
2. Note that the symbol V , in this case, represents the OV symbol referenced in Table 1 and Table 2.
IN
IN
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
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PCI
2.19.2 PCI AC Electrical Specifications
This section describes the general AC timing parameters of the PCI bus. Note that the SYSCLK signal is used as the PCI input
clock. Table 68 provides the PCI AC timing specifications at 66 MHz.
Table 68. PCI AC Timing Specifications at 66 MHz
1
Parameter
SYSCLK to output valid
Symbol
Min
Max
Unit
Notes
t
t
t
—
2.0
6.0
—
ns
ns
2, 3
2
PCKHOV
PCKHOX
PCKHOZ
Output hold from SYSCLK
SYSCLK to output high impedance
Input setup to SYSCLK
—
14
—
ns
2, 4
2, 5
2, 5
6, 7
7
t
3.0
ns
PCIVKH
PCIXKH
PCRVRH
PCRHRX
Input hold from SYSCLK
t
0
—
ns
9
REQ64 to HRESET setup time
t
t
10 × t
—
clocks
ns
SYS
HRESET to REQ64 hold time
HRESET high to first FRAME assertion
Rise time (20%–80%)
0
50
—
t
10
0.6
0.6
clocks
ns
8
PCRHFV
tPCICLK
tPCICLK
2.1
2.1
—
Failing time (20%–80%)
ns
—
Notes:
1. Note that the symbols used for timing specifications herein follow the pattern of t
(first two letters of functional
for inputs and t
for outputs. For
block)(signal)(state) (reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
example, t
symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V)
PCIVKH
relative to the SYSCLK clock, t
, reference (K) going to the high (H) state or setup time. Also, t
symbolizes
SYS
PCRHFV
PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid
(V) state.
2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.
3. All PCI signals are measured from OV /2 of the rising edge of PCI_SYNC_IN to 0.4 × OV of the signal in
DD
DD
question for 3.3-V PCI signaling levels.
4. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current
delivered through the component pin is less than or equal to the leakage current specification.
5. Input timings are measured at the pin.
6. The timing parameter t
indicates the minimum and maximum CLK cycle times for the various specified
SYS
frequencies. The system clock period must be kept within the minimum and maximum defined ranges. For values
see Section 22, “Clocking.”
7. The setup and hold time is with respect to the rising edge of HRESET.
8. The timing parameter t
Bus Specifications.
is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI 2.2 Local
PCRHFV
9. The reset assertion timing requirement for HRESET is 100 μs.
Figure 54 provides the AC test load for PCI.
Output
OV /2
DD
Z = 50 Ω
0
R = 50 Ω
L
Figure 54. PCI AC Test Load
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High-Speed Serial Interfaces
Figure 55 shows the PCI input AC timing conditions.
CLK
t
PCIVKH
t
PCIXKH
Input
Figure 55. PCI Input AC Timing Measurement Conditions
Figure 56 shows the PCI output AC timing conditions.
CLK
t
PCKHOV
Output Delay
t
PCKHOZ
High-Impedance
Output
Figure 56. PCI Output AC Timing Measurement Condition
2.20 High-Speed Serial Interfaces
The MPC8536E features two Serializer/Deserializer (SerDes) interfaces to be used for high-speed serial interconnect
applications. The SerDes1 interface is dedicated for PCI Express data transfers. The SerDes2 can be used for SGMII or SATA.
This section describes the common portion of SerDes DC electrical specifications, which is the DC requirement for SerDes
Reference Clocks. The SerDes data lane’s transmitter and receiver reference circuits are also shown.
2.20.1 Signal Terms Definition
The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms used in the description
and specification of differential signals.
Figure 57 shows how the signals are defined. For illustration purposes, only one SerDes lane is used for description. The figure
shows waveform for either a transmitter output (SDn_TX and SDn_TX) or a receiver input (SDn_RX and SDn_RX). Each
signal swings between A Volts and B Volts where A > B.
Using this waveform, the definitions are as follows. To simplify illustration, the following definitions assume that the SerDes
transmitter and receiver operate in a fully symmetrical differential signaling environment.
1. Single-Ended Swing
The transmitter output signals and the receiver input signals SDn_TX, SDn_TX, SDn_RX and SDn_RX each have a
peak-to-peak swing of A - B Volts. This is also referred as each signal wire’s Single-Ended Swing.
2. Differential Output Voltage, V (or Differential Output Swing):
OD
The Differential Output Voltage (or Swing) of the transmitter, V , is defined as the difference of the two complimentary output
OD
voltages: V
- V
The V value can be either positive or negative.
SDn_TX
SDn_TX. OD
3. Differential Input Voltage, V (or Differential Input Swing):
ID
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High-Speed Serial Interfaces
The Differential Input Voltage (or Swing) of the receiver, V , is defined as the difference of the two complimentary input
ID
voltages: V
- V
The V value can be either positive or negative.
SDn_RX
SDn_RX. ID
4. Differential Peak Voltage, V
DIFFp
The peak value of the differential transmitter output signal or the differential receiver input signal is defined as Differential Peak
Vol ta ge, V
= |A - B| Volts.
DIFFp
5. Differential Peak-to-Peak, V
DIFFp-p
Since the differential output signal of the transmitter and the differential input signal of the receiver each range from A - B to
-(A - B) Volts, the peak-to-peak value of the differential transmitter output signal or the differential
receiver input signal is defined as Differential Peak-to-Peak Voltage, V
= 2*V
=
DIFFp-p
DIFFp
2 * |(A - B)| Volts, which is twice of differential swing in amplitude, or twice of the differential
peak. For example, the output differential peak-peak voltage can also be calculated as V
TX-DIFFp-p
= 2*|V |.
OD
6. Common Mode Voltage, V
cm
The Common Mode Voltage is equal to one half of the sum of the voltages between each conductor of a balanced interchange
circuit and ground. In this example, for SerDes output, V = V + V = (A + B)
cm_out
SDn_TX
SDn_TX
/ 2, which is the arithmetic mean of the two complimentary output voltages within a differential
pair. In a system, the common mode voltage may often differ from one component’s output to the
other’s input. Sometimes, it may be even different between the receiver input and driver output
circuits within the same component. It is also referred as the DC offset in some occasion.
SDn_TX or
SDn_RX
A Volts
B Volts
V
= (A + B) / 2
cm
SDn_TX or
SDn_RX
Differential Swing, V or V = A – B
ID
OD
Differential Peak Voltage, V
= |A – B|
DIFFp
Differential Peak-Peak Voltage, V
= 2*V
(not shown)
DIFFpp
DIFFp
Figure 57. Differential Voltage Definitions for Transmitter or Receiver
To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic) transmitter that has a common
mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing that goes between 2.5V and 2.0V. Using these values,
the peak-to-peak voltage swing of each signal (TD or TD) is 500 mV p-p, which is referred as the single-ended swing for each
signal. In this example, since the differential signaling environment is fully symmetrical, the transmitter output’s differential
swing (V ) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges between 500
OD
mV and –500 mV, in other words, V is 500 mV in one phase and –500 mV in the other phase. The peak differential voltage
OD
(V
) is 500 mV. The peak-to-peak differential voltage (V
) is 1000 mV p-p.
DIFFp
DIFFp-p
2.20.2 SerDes Reference Clocks
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding
SerDes lanes. The SerDes reference clocks for PCI Express are SD1_REF_CLK and, SD1_REF_CLK. The SerDes reference
clocks for the SATA and SGMII interfaces are SD2_REF_CLK and, SD2_REF_CLK.
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High-Speed Serial Interfaces
The following sections describe the SerDes reference clock requirements and some application information.
2.20.2.1 SerDes Reference Clock Receiver Characteristics
Figure 58 shows a receiver reference diagram of the SerDes reference clocks.
•
•
The supply voltage requirements for X2V are specified in Table 2 and Table 3.
DD
SerDes Reference Clock Receiver Reference Circuit Structure
— The SDn_REF_CLK and SDn_REF_CLK are internally AC-coupled differential inputs as shown in Figure 58.
Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a 50-Ω termination to SGND (xcorevss)
followed by on-chip AC-coupling.
— The external reference clock driver must be able to drive this termination.
— The SerDes reference clock input can be either differential or single-ended. See the Differential Mode and
Single-ended Mode description below for further detailed requirements.
•
The maximum average current requirement that also determines the common mode voltage range
— When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the
maximum average current allowed for each input pin is 8mA. In this case, the exact common mode input voltage
is not critical as long as it is within the range allowed by the maximum average current of 8 mA (refer to the
following bullet for more detail), since the input is AC-coupled on-chip.
— This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V/50 = 8 mA)
while the minimum common mode input level is 0.1V above SnGND (xcorevss). For example, a clock with a
50/50 duty cycle can be produced by a clock driver with output driven by its current source from 0mA to 16mA
(0–0.8 V), such that each phase of the differential input has a single-ended swing from 0 V to 800mV with the
common mode voltage at 400mV.
— If the device driving the SDn_REF_CLK and SDn_REF_CLK inputs cannot drive 50 Ω to SnGND (xcorevss)
DC, or it exceeds the maximum input current limitations, then it must be AC-coupled off-chip.
•
The input amplitude requirement
— This requirement is described in detail in the following sections.
50 Ω
SDn_REF_CLK
Input
Amp
SDn_REF_CLK
50 Ω
Figure 58. Receiver of SerDes Reference Clocks
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High-Speed Serial Interfaces
2.20.2.2 DC Level Requirement for SerDes Reference Clocks
The DC level requirement for the MPC8536E SerDes reference clock inputs is different depending on the signaling mode used
to connect the clock driver chip and SerDes reference clock inputs as described below.
•
Differential Mode
— The input amplitude of the differential clock must be between 400mV and 1600mV differential peak-peak (or
between 200mV and 800mV differential peak). In other words, each signal wire of the differential pair must have
a single-ended swing less than 800mV and greater than 200mV. This requirement is the same for both external
DC-coupled or AC-coupled connection.
— For external DC-coupled connection, as described in section 2.20.2.1, the maximum average current
requirements sets the requirement for average voltage (common mode voltage) to be between 100 mV and 400
mV. Figure 59 shows the SerDes reference clock input requirement for DC-coupled connection scheme.
— For external AC-coupled connection, there is no common mode voltage requirement for the clock driver. Since
the external AC-coupling capacitor blocks the DC level, the clock driver and the SerDes reference clock receiver
operate in different command mode voltages. The SerDes reference clock receiver in this connection scheme has
its common mode voltage set to SnGND. Each signal wire of the differential inputs is allowed to swing below and
above the command mode voltage (SnGND). Figure 60 shows the SerDes reference clock input requirement for
AC-coupled connection scheme.
•
Single-ended Mode
— The reference clock can also be single-ended. The SDn_REF_CLK input amplitude (single-ended swing) must be
between 400mV and 800mV peak-peak (from Vmin to Vmax) with SDn_REF_CLK either left unconnected or
tied to ground.
— The SDn_REF_CLK input average voltage must be between 200 and 400 mV. Figure 61 shows the SerDes
reference clock input requirement for single-ended signaling mode.
— To meet the input amplitude requirement, the reference clock inputs might need to be DC or AC-coupled
externally. For the best noise performance, the reference of the clock could be DC or AC-coupled into the unused
phase (SDn_REF_CLK) through the same source impedance as the clock input (SDn_REF_CLK) in use.
200 mV < Input Amplitude or Differential Peak < 800 mV
SDn_REF_CLK
Vmax < 800 mV
100 mV < Vcm < 400 mV
Vmin > 0 V
SDn_REF_CLK
Figure 59. Differential Reference Clock Input DC Requirements (External DC-Coupled)
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
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High-Speed Serial Interfaces
200mV < Input Amplitude or Differential Peak < 800 mV
SDn_REF_CLK
Vmax < Vcm + 400 mV
Vcm
Vmin > Vcm – 400 mV
SDn_REF_CLK
Figure 60. Differential Reference Clock Input DC Requirements (External AC-Coupled)
400 mV < SDn_REF_CLK Input Amplitude < 800 mV
SDn_REF_CLK
0V
SDn_REF_CLK
Figure 61. Single-Ended Reference Clock Input DC Requirements
2.20.2.3 Interfacing With Other Differential Signaling Levels
With on-chip termination to SnGND (xcorevss), the differential reference clocks inputs are HCSL (High-Speed Current
Steering Logic) compatible DC-coupled.
Many other low voltage differential type outputs like LVDS (Low Voltage Differential Signaling) can be used but may need to
be AC-coupled due to the limited common mode input range allowed (100 to 400 mV) for DC-coupled connection.
LVPECL (Low Voltage Positive Emitter-Coupled Logic) outputs can produce signal with too large amplitude and may need to
be DC-biased at clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to
AC-coupling.
NOTE
Figure 62 to Figure 65 below are for conceptual reference only. Due to the fact that clock
driver chip's internal structure, output impedance and termination requirements are
different between various clock driver chip manufacturers, it is very possible that the clock
circuit reference designs provided by clock driver chip vendor are different from what is
shown below. They might also vary from one vendor to the other. Therefore, Freescale
Semiconductor can neither provide the optimal clock driver reference circuits, nor
guarantee the correctness of the following clock driver connection reference circuits. The
system designer is recommended to contact the selected clock driver chip vendor for the
optimal reference circuits with the MPC8536E SerDes reference clock receiver
requirement provided in this document.
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High-Speed Serial Interfaces
Figure 62 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It assumes that the DC
levels of the clock driver chip is compatible with MPC8536E SerDes reference clock input’s DC requirement.
HCSL CLK Driver Chip
50 Ω
SDn_REF_CLK
CLK_Out
33 Ω
SerDes Refer.
CLK Receiver
100 Ω differential PWB trace
Clock Driver
33 Ω
SDn_REF_CLK
CLK_Out
50 Ω
Clock driver vendor dependent
source termination resistor
Total 50 Ω. Assume clock driver’s
output impedance is about 16 Ω.
Figure 62. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)
Figure 63 shows the SerDes reference clock connection reference circuits for LVDS type clock driver. Since LVDS clock
driver’s common mode voltage is higher than the MPC8536E SerDes reference clock input’s allowed range (100 to 400mV),
AC-coupled connection scheme must be used. It assumes the LVDS output driver features 50-Ω termination resistor. It also
assumes that the LVDS transmitter establishes its own common mode level without relying on the receiver or other external
component.
MPC8536E
LVDS CLK Driver Chip
50 Ω
SDn_REF_CLK
10 nF
CLK_Out
SerDes Refer.
CLK Receiver
100 Ω differential PWB trace
Clock Driver
SDn_REF_CLK
CLK_Out
10 nF
50 Ω
Figure 63. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)
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High-Speed Serial Interfaces
Figure 64 shows the SerDes reference clock connection reference circuits for LVPECL type clock driver. Since LVPECL
driver’s DC levels (both common mode voltages and output swing) are incompatible with MPC8536E SerDes reference clock
input’s DC requirement, AC-coupling has to be used. Figure 64 assumes that the LVPECL clock driver’s output impedance is
50Ω. R1 is used to DC-bias the LVPECL outputs prior to AC-coupling. Its value could be ranged from 140Ω to 240Ω depending
on clock driver vendor’s requirement. R2 is used together with the SerDes reference clock receiver’s 50-Ω termination resistor
to attenuate the LVPECL output’s differential peak level such that it meets the MPC8536E SerDes reference clock’s differential
input amplitude requirement (between 200mV and 800mV differential peak). For example, if the LVPECL output’s differential
peak is 900mV and the desired SerDes reference clock input amplitude is selected as 600mV, the attenuation factor is 0.67,
which requires R2 = 25Ω. Please consult clock driver chip manufacturer to verify whether this connection scheme is compatible
with a particular clock driver chip.
LVPECL CLK
Driver Chip
MPC8536E
50 Ω
SDn_REF_CLK
SDn_REF_CLK
CLK_Out
10nF
R2
SerDes Refer.
CLK Receiver
R1
R1
100 Ω differential PWB trace
10 nF
Clock Driver
R2
CLK_Out
50 Ω
Figure 64. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)
Figure 65 shows the SerDes reference clock connection reference circuits for a single-ended clock driver. It assumes the DC
levels of the clock driver are compatible with MPC8536E SerDes reference clock input’s DC requirement.
Single-Ended
CLK Driver Chip
Total 50 Ω. Assume clock driver’s
output impedance is about 16 Ω.
50 Ω
SDn_REF_CLK
33 Ω
Clock Driver
CLK_Out
SerDes Refer.
CLK Receiver
100 Ω differential PWB trace
SDn_REF_CLK
50 Ω
50 Ω
Figure 65. Single-Ended Connection (Reference Only)
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High-Speed Serial Interfaces
2.20.2.4 AC Requirements for SerDes Reference Clocks
The clock driver selected should provide a high quality reference clock with low phase noise and cycle-to-cycle jitter. Phase
noise less than 100KHz can be tracked by the PLL and data recovery loops and is less of a problem. Phase noise above 15MHz
is filtered by the PLL. The most problematic phase noise occurs in the 1-15MHz range. The source impedance of the clock
driver should be 50 ohms to match the transmission line and reduce reflections which are a source of noise to the system.
Table 69 describes some AC parameters common to SGMII and PCI Express protocols.
Table 69. SerDes Reference Clock Common AC Parameters
At recommended operating conditions with XVDD_SRDS1 or XVDD_SRDS2 = 1.0V 5%.
Parameter
Symbol
Min
Max
Unit
Notes
Rising Edge Rate
Falling Edge Rate
Rise Edge Rate
Fall Edge Rate
1.0
1.0
+200
—
4.0
4.0
—
V/ns
V/ns
mV
mV
%
2, 3
2, 3
2
Differential Input High Voltage
Differential Input Low Voltage
V
IH
V
–200
20
2
IL
Rising edge rate (SDn_REF_CLK) to falling edge rate
(SDn_REF_CLK) matching
Rise-Fall
Matching
—
1, 4
Notes:
1. Measurement taken from single ended waveform.
2. Measurement taken from differential waveform.
3. Measured from –200 mV to +200 mV on the differential waveform (derived from SDn_REF_CLK minus SDn_REF_CLK). The
signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is
centered on the differential zero crossing. See Figure 66.
4. Matching applies to rising edge rate for SDn_REF_CLK and falling edge rate for SDn_REF_CLK. It is measured using a 200
mV window centered on the median cross point where SDn_REF_CLK rising meets SDn_REF_CLK falling. The median cross
point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge Rate
of SDn_REF_CLK should be compared to the Fall Edge Rate of SDn_REF_CLK, the maximum allowed difference should not
exceed 20% of the slowest edge rate. See Figure 67.
V
=
+200
0.0 V
IH
V
= –200 mV
IL
SDn_REF_CL
K
minus
Figure 66. Differential Measurement Points for Rise and Fall Time
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High-Speed Serial Interfaces
SDn_REF_CLK
SDn_REF_CLK
SDn_REF_CLK
SDn_REF_CLK
Figure 67. Single-Ended Measurement Points for Rise and Fall Time Matching
The other detailed AC requirements of the SerDes Reference Clocks is defined by each interface protocol based on application
usage. See the following sections for detailed information:
•
•
Section 2.9.3.2, “AC Requirements for SGMII SD2_REF_CLK and SD2_REF_CLK”
Section 2.21.2, “AC Requirements for PCI Express SerDes Clocks”
2.20.2.4.1 Spread Spectrum Clock
SD1_REF_CLK/SD1_REF_CLK were designed to work with a spread spectrum clock (+0 to -0.5% spreading at 30–33 kHz
rate is allowed), assuming both ends have same reference clock. For better results, a source without significant unintended
modulation should be used.
SD2_REF_CLK/SD2_REF_CLK are not intended to be used with, and should not be clocked by, a spread spectrum clock
source.
2.20.3 SerDes Transmitter and Receiver Reference Circuits
Figure 68 shows the reference circuits for SerDes data lane’s transmitter and receiver.
SD1_RXn or
SD2_RXn
SD1_TXn or
SD2_TXn
50 Ω
50 Ω
50 Ω
50 Ω
Receiver
Transmitter
SD1_TXn or
SD2_TXn
SD1_RXn or
SD2_RXn
Figure 68. SerDes Transmitter and Receiver Reference Circuits
The DC and AC specification of SerDes data lanes are defined in each interface protocol section below (PCI Express, SATA or
SGMII) in this document based on the application usage:
•
•
•
Section 2.9.3, “SGMII Interface Electrical Characteristics”
Section 2.21, “PCI Express”
Section 2.16, “Serial ATA (SATA)”
Please note that external AC Coupling capacitor is required for the above three serial transmission protocols with the capacitor
value defined in specification of each protocol section.
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PCI Express
2.21 PCI Express
This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8536E.
2.21.1 DC Requirements for PCI Express SD1_REF_CLK and
SD1_REF_CLK
For more information, see Section 2.20.2, “SerDes Reference Clocks.”
2.21.2 AC Requirements for PCI Express SerDes Clocks
Table 70 lists AC requirements.
Table 70. SD1_REF_CLK and SD1_REF_CLK AC Requirements
Symbol
Parameter Description
Min
Typical
Max
Units
Notes
t
REFCLK cycle time
—
—
10
—
—
ns
ps
1
REF
t
REFCLK cycle-to-cycle jitter. Difference in the period of any two
adjacent REFCLK cycles
100
—
REFCJ
t
Phase jitter. Deviation in edge location with respect to mean edge
location
–50
—
50
ps
1,2,3
REFPJ
Notes:
1. Tj at BER of 10E-6 86 ps Max.
2. Total peak-to-peak deterministic jitter “Dj” should be less than or equal to 42 ps.
3. Limits from “PCI Express CEM Rev 2.0” and measured per “PCI Express Rj, D, and Bit Error Rates”.
2.21.3 Clocking Dependencies
The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million 15 (ppm) of each other at all
times. This is specified to allow bit rate clock sources with a +/– 300 ppm tolerance.
2.21.4 Physical Layer Specifications
The following is a summary of the specifications for the physical layer of PCI Express on this device. For further details as well
as the specifications of the transport and data link layer, please use the PCI Express Base Specification. REV. 1.0a document.
2.21.4.1 Differential Transmitter (TX) Output
Table 71 defines the specifications for the differential output at all transmitters (TXs). The parameters are specified at the
component pins.
Table 71. Differential Transmitter (TX) Output Specifications
Symbol
Parameter
Unit Interval
Min
Nom
Max Units
Comments
UI
399.88 400 400.12 ps Each UI is 400 ps 300 ppm. UI does not account for
Spread Spectrum Clock dictated variations. See Note
1.
V
Differential
0.8
—
1.2
V
V
= 2*|V
– V
| See Note 2.
TX-DIFFp-p
TX-DIFFp-p
TX-D+
TX-D-
Peak-to-Peak
Output Voltage
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Table 71. Differential Transmitter (TX) Output Specifications (continued)
Symbol
Parameter
Min
Nom
Max Units
Comments
of the second and following
V
De- Emphasized
Differential Output
Voltage (Ratio)
–3.0
–3.5
–4.0
dB Ratio of the V
TX-DIFFp-p
TX-DE-RATIO
bits after a transition divided by the V
first bit after a transition. See Note 2.
of the
TX-DIFFp-p
T
Minimum TX Eye
Width
0.70
—
—
—
—
UI The maximum Transmitter jitter can be derived as
= 1 – T = 0.3 UI.
TX-EYE
T
TX-MAX-JITTER
TX-EYE
See Notes 2 and 3.
T
Maximum time
between the jitter
median and
maximum
deviation from the
median.
0.15
UI Jitter is defined as the measurement variation of the
TX-EYE-MEDIAN-to-
crossing points (V = 0 V) in relation to a
MAX-JITTER
TX-DIFFp-p
recovered TX UI. A recovered TX UI is calculated over
3500 consecutive unit intervals of sample data. Jitter
is measured using all edges of the 250 consecutive UI
in the center of the 3500 UI used for calculating the TX
UI. See Notes 2 and 3.
T
, T
D+/D- TX Output
Rise/Fall Time
0.125
—
—
—
—
UI See Notes 2 and 5
TX-RISE TX-FALL
V
RMS AC Peak
Common Mode
Output Voltage
20
mV
V
V
= RMS(|V
+V
|/2 – V
)
TX-CM-DC
TX-CM-ACp
TX-CM-ACp
TXD+
of |V
TXD-
+V
= DC
|/2
TX-CM-DC
(avg)
TX-D+
TX-D-
See Note 2
V
Absolute Delta of
DC Common
Mode Voltage
During L0 and
Electrical Idle
0
—
100
25
mV |V
– V
TX-CM-DC (during L0) TX-CM-Idle-DC (During Electrical
|<=100 mV
TX-CM-DC-ACTIVE-
IDLE-DELTA
Idle)
V
V
= DC
of |V
+V
|/2 [L0]
TX-D-
TX-CM-DC
(avg)
TX-D+
= DC
of |V
+ V
|/2
TX-CM-Idle-DC
(avg)
TX-D+
TX-D-
[Electrical Idle]
See Note 2.
V
Absolute Delta of
DC Common
Mode between D+
and D–
0
—
mV |V
– V
| <= 25 mV
TX-CM-DC-LINE-DELTA
TX-CM-DC-D+
TX-CM-DC-D-
V
V
= DC
= DC
of |V
|
TX-D+
TX-CM-DC-D+
(avg)
(avg)
of |V
|
TX-CM-DC-D-
TX-D-
See Note 2.
V
V
Electrical Idle
differential Peak
Output Voltage
0
—
—
20
mV
V
= |V
-V
| <= 20 mV
TX-IDLE-DIFFp
TX-IDLE-DIFFp
TX-IDLE-D+
TX-IDLE-D-
See Note 2.
The amount of
voltage change
allowed during
Receiver Detection
—
600
mV The total amount of voltage change that a transmitter
can apply to sense whether a low impedance
Receiver is present. See Note 6.
TX-RCV-DETECT
V
The TX DC
Common Mode
Voltage
0
—
3.6
V
The allowed DC Common Mode voltage under any
conditions. See Note 6.
TX-DC-CM
I
TX Short Circuit
Current Limit
—
—
—
90
—
mA The total current the Transmitter can provide when
shorted to its ground
TX-SHORT
T
Minimum time
spent in Electrical
Idle
50
UI Minimum time a Transmitter must be in Electrical Idle
Utilized by the Receiver to start looking for an
Electrical Idle Exit after successfully receiving an
Electrical Idle ordered set
TX-IDLE-MIN
PCI Express
Symbol
Table 71. Differential Transmitter (TX) Output Specifications (continued)
Parameter
Min
Nom
Max Units
Comments
T
Maximum time to
transition to a valid
electrical idle after
sending an
—
—
20
UI After sending an Electrical Idle ordered set, the
Transmitter must meet all Electrical Idle Specifications
within this time. This is considered a debounce time
for the Transmitter to meet Electrical Idle after
transitioning from L0.
TX-IDLE-SET-TO-IDLE
electrical Idle
ordered set
T
Maximum time to
transition to valid
TX specifications
after leaving an
electrical idle
—
—
20
UI Maximum time to meet all TX specifications when
transitioning from Electrical Idle to sending differential
data. This is considered a debounce time for the TX to
meet all TX specifications after leaving Electrical Idle
TX-IDLE-TO-DIFF-DATA
condition
RL
Differential Return
Loss
12
6
—
—
—
—
dB Measured over 50 MHz to 1.25 GHz. See Note 4
dB Measured over 50 MHz to 1.25 GHz. See Note 4
TX-DIFF
RL
Common Mode
Return Loss
TX-CM
Z
Z
DC Differential TX
Impedance
80
40
—
75
100
—
120
—
Ω
Ω
TX DC Differential mode Low Impedance
TX-DIFF-DC
TX-DC
Transmitter DC
Impedance
Required TX D+ as well as D- DC Impedance during
all states
L
Lane-to-Lane
Output Skew
—
500 +
2 UI
ps Static skew between any two Transmitter Lanes within
a single Link
TX-SKEW
C
AC Coupling
Capacitor
—
200
nF All Transmitters shall be AC coupled. The AC coupling
is required either within the media or within the
transmitting component itself. See Note 8.
TX
T
Crosslink Random
Timeout
0
—
1
ms This random timeout helps resolve conflicts in
crosslink configuration by eventually resulting in only
one Downstream and one Upstream Port. See Note 7.
crosslink
Notes:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 52 and measured over
any 250 consecutive TX UIs. (Also refer to the transmitter compliance eye diagram shown in Figure 50)
3. A T
= 0.70 UI provides for a total sum of deterministic and random jitter budget of T
= 0.30 UI for the
TX-JITTER-MAX
TX-EYE
Transmitter collected over any 250 consecutive TX UIs. The T
median is less than half of the total
TX-EYE-MEDIAN-to-MAX-JITTER
TX jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean.
The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed
to the averaged time value.
4. The Transmitter input impedance shall result in a differential return loss greater than or equal to 12 dB and a common mode
return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement
applies to all valid input levels. The reference impedance for return loss measurements is 50 ohms to ground for both the D+
and D- line (that is, as measured by a Vector Network Analyzer with 50 ohm probes—see Figure 52). Note that the series
capacitors C is optional for the return loss measurement.
TX
5. Measured between 20-80% at transmitter package pins into a test load as shown in Figure 52 for both V
6. See Section 4.3.1.8 of the PCI Express Base Specifications Rev 1.0a
and V
.
TX-D-
TX-D+
7. See Section 4.2.6.3 of the PCI Express Base Specifications Rev 1.0a
8. SerDes transmitter does not have CTX built-in. An external AC Coupling capacitor is required.
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
102
2.21.4.2 Transmitter Compliance Eye Diagrams
The TX eye diagram in Figure 69 is specified using the passive compliance/test measurement load (see Figure 71) in place of
any real PCI Express interconnect + RX component.
There are two eye diagrams that must be met for the transmitter. Both eye diagrams must be aligned in time using the jitter
median to locate the center of the eye diagram. The different eye diagrams will differ in voltage depending whether it is a
transition bit or a de-emphasized bit. The exact reduced voltage level of the de-emphasized bit will always be relative to the
transition bit.
The eye diagram must be valid for any 250 consecutive UIs.
A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is created using all edges
of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI.
NOTE
It is recommended that the recovered TX UI is calculated using all edges in the 3500
consecutive UI interval with a fit algorithm using a minimization merit function (that is,
least squares and median deviation fits).
Figure 69. Minimum Transmitter Timing and Voltage Output Compliance Specifications
PCI Express
2.21.4.3 Differential Receiver (RX) Input Specifications
Table 72 defines the specifications for the differential input at all receivers (RXs). The parameters are specified at the
component pins.
Table 72. Differential Receiver (RX) Input Specifications
Symbol
Parameter
Min
Nom
Max
Units
Comments
UI
Unit Interval
399.8
8
400
400.12
ps
Each UI is 400 ps 300 ppm. UI does not
account for Spread Spectrum Clock dictated
variations. See Note 1.
V
Differential
Peak-to-Peak
Output Voltage
0.175
0.4
—
—
1.200
—
V
V
= 2*|V
– V
|
RX-D-
RX-DIFFp-p
RX-DIFFp-p
RX-D+
See Note 2.
T
Minimum
Receiver Eye
Width
UI
The maximum interconnect media and
Transmitter jitter that can be tolerated by the
Receiver can be derived as T
RX-EYE
=
RX-MAX-JITTER
1 - T
= 0.6 UI.
RX-EYE
See Notes 2 and 3.
T
Maximum time
between the jitter
median and
maximum
deviation from
the median.
—
—
0.3
UI
Jitter is defined as the measurement variation
RX-EYE-MEDIAN-to-MAX
of the crossing points (V = 0 V) in
-JITTER
RX-DIFFp-p
relation to a recovered TX UI. A recovered TX
UI is calculated over 3500 consecutive unit
intervals of sample data. Jitter is measured
using all edges of the 250 consecutive UI in
the center of the 3500 UI used for calculating
the TX UI. See Notes 2, 3 and 7.
V
AC Peak
Common Mode
Input Voltage
—
15
—
—
150
—
mV
dB
V
V
= |V
= DC
– V
of |V
|/2 +V
RXD- RX-CM-DC
RX-CM-ACp
RX-CM-ACp
RXD+
+V
|/2
RX-CM-DC
(avg)
RX-D+
RX-D-
See Note 2
RL
Differential
Return Loss
Measured over 50 MHz to 1.25 GHz with the
D+ and D- lines biased at +300 mV and –300
mV, respectively.
RX-DIFF
See Note 4
RL
Z
Common Mode
Return Loss
6
80
—
100
50
—
120
60
dB
Ω
Measured over 50 MHz to 1.25 GHz with the
D+ and D- lines biased at 0 V. See Note 4
RX-CM
DC Differential
Input Impedance
RX DC Differential mode impedance. See
Note 5
RX-DIFF-DC
Z
Z
DC Input
Impedance
40
Ω
Required RX D+ as well as D- DC Impedance
(50 20% tolerance). See Notes 2 and 5.
RX-DC
Powered Down
DC Input
Impedance
200 k
—
—
Ω
Required RX D+ as well as D– DC
Impedance when the Receiver terminations
do not have power. See Note 6.
RX-HIGH-IMP-DC
V
Electrical Idle
Detect Threshold
65
—
—
—
175
10
mV
ms
V
= 2*|V
–V
|
RX-D-
RX-IDLE-DET-DIFFp-p
RX-IDLE-DET-DIFFp-p
RX-D+
Measured at the package pins of the Receiver
T
Unexpected
Electrical Idle
Enter Detect
Threshold
An unexpected Electrical Idle (V
V
longer than T
signal an unexpected idle condition.
<
RX-DIFFp-p
RX-IDLE-DET-DIFF-
) must be recognized no
ENTERTIME
RX-IDLE-DET-DIFFp-p
to
RX-IDLE-DET-DIFF-ENTERING
Integration Time
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
104
PCI Express
Table 72. Differential Receiver (RX) Input Specifications (continued)
Symbol
Parameter
Total Skew
Min
Nom
Max
Units
Comments
L
—
—
20
ns
Skew across all lanes on a Link. This includes
variation in the length of SKP ordered set (for
example, COM and one to five Symbols) at
the RX as well as any delay differences
arising from the interconnect itself.
TX-SKEW
Notes:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 71 should be used
as the RX device when taking measurements (also refer to the Receiver compliance eye diagram shown in Figure 70). If the
clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must
be used as a reference for the eye diagram.
3. A T
= 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the Transmitter and
RX-EYE
interconnect collected any 250 consecutive UIs. The T
specification ensures a jitter distribution in
RX-EYE-MEDIAN-to-MAX-JITTER
which the median and the maximum deviation from the median is less than half of the total. UI jitter budget collected over any
250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point
in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. If the
clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must
be used as the reference for the eye diagram.
4. The Receiver input impedance shall result in a differential return loss greater than or equal to 15 dB with the D+ line biased to
300 mV and the D- line biased to -300 mV and a common mode return loss greater than or equal to 6 dB (no bias required)
over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The
reference impedance for return loss measurements for is 50 ohms to ground for both the D+ and D- line (that is, as measured
by a Vector Network Analyzer with 50 ohm probes - see Figure 71). Note: that the series capacitors CTX is optional for the
return loss measurement.
5. Impedance during all LTSSM states. When transitioning from a Fundamental Reset to Detect (the initial state of the LTSSM)
there is a 5 ms transition time before Receiver termination values must be met on all un-configured Lanes of a Port.
6. The RX DC Common Mode Impedance that exists when no power is present or Fundamental Reset is asserted. This helps
ensure that the Receiver Detect circuit will not falsely assume a Receiver is powered on when it is not. This term must be
measured at 300 mV above the RX ground.
7. It is recommended that the recovered TX UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm
using a minimization merit function. Least squares and median deviation fits have worked well with experimental and simulated
data.
2.22
Receiver Compliance Eye Diagrams
The RX eye diagram in Figure 70 is specified using the passive compliance/test measurement load (see Figure 71) in place of
any real PCI Express RX component.
Note: In general, the minimum Receiver eye diagram measured with the compliance/test measurement load (see Figure 71) will
be larger than the minimum Receiver eye diagram measured over a range of systems at the input Receiver of any real PCI
Express component. The degraded eye diagram at the input Receiver is due to traces internal to the package as well as silicon
parasitic characteristics which cause the real PCI Express component to vary in impedance from the compliance/test
measurement load. The input Receiver eye diagram is implementation specific and is not specified. RX component designer
should provide additional margin to adequately compensate for the degraded minimum Receiver eye diagram (shown in
Figure 70) expected at the input Receiver based on some adequate combination of system simulations and the Return Loss
measured looking into the RX package and silicon. The RX eye diagram must be aligned in time using the jitter median to locate
the center of the eye diagram.
The eye diagram must be valid for any 250 consecutive UIs.
A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is created using all edges
of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI.
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
105
Clocking
NOTE
The reference impedance for return loss measurements is 50. to ground for both the D+ and
D- line (that is, as measured by a Vector Network Analyzer with 50. probes—see
Figure 71). Note that the series capacitors, CTX, are optional for the return loss
measurement.
Figure 70. Minimum Receiver Eye Timing and Voltage Compliance Specification
2.22.0.1 Compliance Test and Measurement Load
The AC timing and voltage parameters must be verified at the measurement point, as specified within 0.2 inches of the package
pins, into a test/measurement load shown in Figure 71.
NOTE
The allowance of the measurement point to be within 0.2 inches of the package pins is
meant to acknowledge that package/board routing may benefit from D+ and D– not being
exactly matched in length at the package pin boundary.
Figure 71. Compliance Test/Measurement Load
2.23 Clocking
This section describes the PLL configuration of the MPC8536E. Note that the platform clock is identical to the core complex
bus (CCB) clock.
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106
Freescale Semiconductor
Clocking
2.23.1 Clock Ranges
Table 73 provides the clocking specifications for the processor cores and Table 74 provides the clocking specifications for the
memory bus.
Table 73. Processor Core Clocking Specifications
Maximum Processor Core Frequency
Characteristic
600 MHz
Min
800 MHz
1000 MHz
1250 MHz
1333 MHZ
1500 MHz
Min Max
Unit Notes
Max Min Max Min Max Min Max
Min
Max
e500 core processor 600
frequency
600 600
800 600 1000 600 1250 600 1333 600
1500 MHz
1, 2
CCB frequency
DDR Data Rate
Notes:
400
400
400 400
400 400
400 333 400 333 500
400 400 400 400 500
333
400
533
667
333
400
500
667
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to Section 2.23.2, “CCB/SYSCLK PLL Ratio” and Section 2.23.3, “e500 Core PLL Ratio“, Section 2.23.4,
“DDR/DDRCLK PLL Ratio,” for ratio settings.
2. The processor core frequency speed bins listed also reflect the maximum platform (CCB) and DDR data rate frequency
supported by production test. Running CCB and/or DDR data rate higher than the limit shown above, although logically
possible via valid clock ratio setting in some condition, is not supported.
The DDR memory controller can run in either synchronous or asynchronous mode. When running in synchronous mode, the
memory bus is clocked relative to the platform clock frequency. When running in asynchronous mode, the memory bus is
clocked with its own dedicated PLL. Table 74 provides the clocking specifications for the memory bus.
Table 74. Memory Bus Clocking Specifications
Maximum Processor Core Frequency
Characteristic
600, 800, 1000, 1250,1333, 1500MHz
Unit
Notes
Min
Max
DDR Memory bus clock speed
200
333
MHz
1, 2, 3, 4
Notes:
1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting
SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum
operating frequencies. See Section 2.23.2, “CCB/SYSCLK PLL Ratio,” Section 2.23.3, “e500 Core PLL Ratio,” and
Section 2.23.4, “DDR/DDRCLK PLL Ratio,” for ratio settings.
2. The Memory bus clock refers to the MPC8536E memory controllers’ MCK[0:5] and MCK[0:5] output clocks, running at half of
the DDR data rate.
3. In synchronous mode, the memory bus clock speed is half the platform clock frequency. In other words, the DDR data rate is
the same as the platform (CCB) frequency. If the desired DDR data rate is higher than the platform (CCB) frequency,
asynchronous mode must be used.
4. In asynchronous mode, the memory bus clock speed is dictated by its own PLL. See Section 2.23.4, “DDR/DDRCLK PLL
Ratio.” The memory bus clock speed must be less than or equal to the CCB clock rate which in turn must be less than the DDR
data rate.
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
107
Clocking
2.23.2 CCB/SYSCLK PLL Ratio
The CCB clock is the clock that drives the e500 core complex bus (CCB), and is also called the platform clock. The frequency
of the CCB is set using the following reset signals, as shown in Table 75:
•
•
SYSCLK input signal
Binary value on LA[28:31] at power up
Note that there is no default for this PLL ratio; these signals must be pulled to the desired values.
Table 75. CCB Clock Ratio
Binary Value of
LA[28:31] Signals
Binary Value of
LA[28:31] Signals
CCB:SYSCLK Ratio
CCB:SYSCLK Ratio
0000
0001
0010
0011
0100
0101
0110
0111
16:1
Reserved
Reserved
3:1
1000
1001
1010
1011
1100
1101
1110
1111
8:1
9:1
10:1
Reserved
12:1
4:1
5:1
Reserved
Reserved
Reserved
6:1
Reserved
2.23.3 e500 Core PLL Ratio
Table 76 describes the clock ratio between the e500 core complex bus (CCB) and the e500 core clock. This ratio is determined
by the binary value of LBCTL, LALE and LGPL2 at power up, as shown in Table 76.
Table 76. e500 Core to CCB Clock Ratio
Binary Value of
LBCTL, LALE,
LGPL2 Signals
Binary Value of
LBCTL, LALE,
LGPL2 Signals
e500 core: CCB Clock Ratio
e500 core: CCB Clock Ratio
000
001
010
011
4:1
9:2
100
101
110
111
2:1
5:2
3:1
7:2
Reserved
3:2
2.23.4 DDR/DDRCLK PLL Ratio
The DDR memory controller complex can be synchronous with, or asynchronous to, the CCB, depending on configuration.
Table 77 describes the clock ratio between the DDR memory controller complex and the DDR/DDRCLK PLL reference clock,
DDRCLK, which is not the memory bus clock.
When synchronous mode is selected, the memory buses are clocked at half the CCB clock rate. The default mode of operation
is for the DDR data rate for the DDR controller to be equal to the CCB clock rate in synchronous mode, or the resulting DDR
PLL rate in asynchronous mode.
In asynchronous mode, the DDR PLL rate to DDRCLK ratios listed in Table 77 reflects the DDR data rate to DDRCLK ratio,
since the DDR PLL rate in asynchronous mode means the DDR data rate resulting from DDR PLL output.
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
108
Freescale Semiconductor
Clocking
Please note that the DDR PLL reference clock input, DDRCLK, is only required in asynchronous mode.
The DDRCLKDR configuration register in the Global Utilities block allows the DDR controller to be run in a divided down
mode where the DDR bus clock is half the speed of the default configuration. Changing of these defaults must be completed
prior to initialization of the DDR controller.
Table 77. DDR Clock Ratio
Reset Configuration
Functional Signals
Value (Binary)
DDR:DDRCLK Ratio
Name
000
001
010
011
100
101
110
111
3:1
4:1
6:1
8:1
TSEC_1588_TRIG_OUT[0:1],
TSEC1_1588_CLK_OUT
cfg_ddr_pll[0:2]
10:1
12:1
Reserved
Synchronous mode
2.23.5 PCI Clocks
The integrated PCI controller in MPC8536E supports PCI input clock frequency in the range of 33–66 MHz. The PCI input
clock can be applied from SYSCLK in synchronous mode or PCI1_CLK in asynchronous mode. For specifications on the
PCI1_CLK, refer to the PCI 2.2 Specification.
The use of PCI1_CLK is optional if SYSCLK is in the range of 33–66 MHz. If SYSCLK is outside this range then use of
PCI1_CLK is required as a separate PCI clock source, asynchronous with respect to SYSCLK.
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
109
Thermal
2.23.6 Frequency Options
2.23.6.1 SYSCLK to Platform Frequency Options
Table 78 shows the expected frequency values for the platform frequency when using a CCB clock to SYSCLK ratio in
comparison to the memory bus clock speed.
Table 78. Frequency Options of SYSCLK with Respect to Memory Bus Speeds
CCB to
SYSCLK (MHz)
SYSCLK Ratio
33.33
41.66
66.66
83
100
111
133.33
Platform /CCB Frequency (MHz)
3
4
333
444
400
533
333
415
500
400
500
5
333
400
533
6
8
333
417
500
10
12
16
333
400
533
2.23.6.2 Minimum Platform Frequency Requirements for High-speed Interfaces
Section 4.4.3.8 “SerDes1 I/O Port Selection” and Section 4.4.3.9 “SerDes2 I/O Port Selection” of the MPC8536E
PowerQUICC™ III Integrated Host Processor Family Reference Manual, describes various high-speed interface configuration
options. Note that the CCB clock frequency must be considered for proper operation of such interfaces as described below.
For proper PCI Express operation, the CCB clock frequency must be equal or greater than:
527 MHz × (PCI Express link width)
----------------------------------------------------------------------------------------------
8
See Section 18.1.3.2, “Link Width,” of the MPC8536E PowerQUICC™ III Integrated Host Processor Family Reference
Manual, for PCI Express interface width details. Note that the “PCI Express link width” in the above equation refers to the
negotiated link width as the result of PCI Express link training, which may or may not be the same as the link width POR
selection.
2.24 Thermal
This section describes the thermal specifications of the MPC8536E.
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
110
Freescale Semiconductor
Thermal
2.24.1 Thermal Characteristics
Table 79 provides the package thermal characteristics.
Table 79. Package Thermal Characteristics
Characteristic
JEDEC Board
Symbol
Value
Unit
Notes
Junction-to-ambient Natural Convection
Junction-to-ambient Natural Convection
Junction-to-ambient (@200 ft/min)
Junction-to-ambient (@200 ft/min)
Junction-to-board thermal
Single layer board (1s)
Four layer board (2s2p)
Single layer board (1s)
Four layer board (2s2p)
—
R
R
R
R
R
R
23
18
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
1, 2
1, 2
1, 2
1, 2
3
θJA
θJA
θJA
θJA
θJB
θJC
18
14
10
Junction-to-case thermal
—
< 0.1
4
Notes
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Per JEDEC JESD51-2 and JESD51-6 with the board (JESD51-9) horizontal.
3. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
4. Thermal resistance between the active surface of the die and the case top surface determined by the cold plate method
(MIL SPEC-883 Method 1012.1) with the calculated case temperature. Actual thermal resistance is less than 0.1 •C/W
Simulations with heat sinks were done with the package mounted on the 2s2p thermal test board. The thermal interface material
was a typical thermal grease such as Dow Corning 340 or Wakefield 120 grease.For system thermal modeling, the MPC8536E
thermal model without a lid is shown in Figure 72 The substrate is modeled as a block 29 x 29 x 1.2 mm with an in-plane
conductivity of 19.8 W/m•K and a through-plane conductivity of 1.13 W/m•K. The solder balls and air are modeled as a single
block 29 x 29 x 0.5 mm with an in-plane conductivity of 0.034 W/m•K and a through plane conductivity of 12.1 W/m•K. The
die is modeled as 9.6 x 9.57 mm with a thickness of 0.75 mm. The bump/underfill layer is modeled as a collapsed thermal
resistance between the die and substrate assuming a conductivity of 7.5 W/m•K in the thickness dimension of 0.07 mm. The die
is centered on the substrate. The thermal model uses approximate dimensions to reduce grid. Please refer to the case outline for
actual dimensions.
2.24.2 Recommended Thermal Model
Table 80. MPC8536E Thermal Model
Conductivity
Value
Units
Die (9.6x9.6 × 0.85 mm)
Silicon
Temperature dependent
—
Bump/Underfill (9.6 x 9.6 × 0.07 mm) Collapsed Thermal Resistance
Kz
7.5
W/m•K
Substrate (29 × 29 × 1.2 mm)
Kx
Ky
Kz
19.8
19.8
1.13
W/m•K
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
111
Thermal
Table 80. MPC8536E Thermal Model (continued)
Conductivity
Value
Units
Solder and Air (29 × 29 × 0.5 mm)
Kx
Ky
Kz
0.034
0.034
12.1
W/m•K
Bump/underfill
Die
Substrate
Solder/air
Section A-A
A
A
Top View
Figure 72. System Level Thermal Model for MPC8536E (Not to Scale)
The Flotherm library files of the parts have a dense grid to accurately capture the laminar boundary layer for flow over the part
in standard JEDEC environments, as well as the heat spreading in the board under the package. In a real system, however, the
part will require a heat sink to be mounted on it. In this case, the predominant heat flow path will be from the die to the heat
sink. Grid density lower than currently in the package library file will suffice for these simulations. The user will need to
determine the optimal grid for their specific case.
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
112
Freescale Semiconductor
Thermal
2.24.3 Thermal Management Information
This section provides thermal management information for the flip chip plastic ball grid array (FC-PBGA) package for
air-cooled applications. Proper thermal control design is primarily dependent on the system-level design—the heat sink, airflow,
and thermal interface material.
The recommended attachment method to the heat sink is illustrated in Figure 73. The heat sink should be attached to the
printed-circuit board with the spring force centered over the die. This spring force should not exceed 10 pounds force (45
Newton).
FC-PBGA Package
Heat Sink
Heat Sink
Clip
Thermal Interface Material
Die
Printed-Circuit Board
Figure 73. Package Exploded Cross-Sectional View with Several Heat Sink Options
The system board designer can choose between several types of heat sinks to place on the device. Ultimately, the final selection
of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass,
attachment method, assembly, and cost. Several heat sinks offered by Aavid Thermalloy, Advanced Thermal Solutions, Alpha
Novatech, IERC, Chip Coolers, Millennium Electronics, and Wakefield Engineering offer different heat sink-to-ambient
thermal resistances, that will allow the MPC8536E to function in various environments.
2.24.3.1 Internal Package Conduction Resistance
For the packaging technology, shown in Table 70, the intrinsic internal conduction thermal resistance paths are as follows:
•
•
The die junction-to-case thermal resistance
The die junction-to-board thermal resistance
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
113
System Clocking
Figure 74 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board.
External Resistance
Radiation
Convection
Heat Sink
Thermal Interface Material
Die/Package
Die Junction
Internal Resistance
Package/Solder Spheres
Printed-Circuit Board
Radiation
Convection
External Resistance
(Note the internal versus external package resistance)
Figure 74. Package with Heat Sink Mounted to a Printed-Circuit Board
The heat sink removes most of the heat from the device for most applications. Heat generated on the active side of the chip is
conducted through the silicon and through the heat sink attach material (or thermal interface material), and finally to the heat
sink. The junction-to-case thermal resistance is low enough that the heat sink attach material and heat sink thermal resistance
are the dominant terms.
2.24.3.2 Thermal Interface Materials
A thermal interface material is required at the package-to-heat sink interface to minimize the thermal contact resistance. The
performance of thermal interface materials improves with increased contact pressure. This performance characteristic chart is
generally provided by the thermal interface vendors.
3
Hardware Design Considerations
This section provides electrical and thermal design recommendations for successful application of the MPC8536E.
3.1
System Clocking
This device includes seven PLLs:
•
The platform PLL generates the platform clock from the externally supplied SYSCLK input. The frequency ratio
between the platform and SYSCLK is selected using the platform PLL ratio configuration bits as described in
Section 2.23.2, “CCB/SYSCLK PLL Ratio.”
•
The e500 core PLL generates the core clock as a slave to the platform clock. The frequency ratio between the e500
core clock and the platform clock is selected using the e500 PLL ratio configuration bits as described in Section 2.23.3,
“e500 Core PLL Ratio/”
•
•
•
•
•
The PCI PLL generates the clocking for the PCI bus
The local bus PLL generates the clock for the local bus.
There is a PLL for the SerDes1 block to be used for PCI Express interface
There is a PLL for the SerDes2 block to be used for SGMII and SATA interfaces.
The DDR PLL generates the DDR clock from the externally supplied DDRCLK input in asynchronous mode. The
frequency ratio between the DDR clock and DDRCLK is described in Section 2.23.4, “DDR/DDRCLK PLL Ratio.”
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
114
Freescale Semiconductor
Power Supply Design and Sequencing
3.2
Power Supply Design and Sequencing
PLL Power Supply Filtering
3.2.1
Each of the PLLs listed above is provided with power through independent power supply pins (AVDD_PLAT, AVDD_CORE,
AV DD_PCI, AVDD_LBIU, and AVDD_SRDS respectively). The AVDD level should always be equivalent to VDD, and
preferably these voltages will be derived directly from VDD through a low frequency filter scheme such as the following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to provide independent
filter circuits per PLL power supply as illustrated in Figure 75, one to each of the AVDD pins. By providing independent filters
to each PLL the opportunity to cause noise injection from one PLL to the other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz range. It should be built
with surface mount capacitors with minimum Effective Series Inductance (ESL). Consistent with the recommendations of Dr.
Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors
of equal value are recommended over a single large value capacitor.
Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled from
nearby circuits. It should be possible to route directly from the capacitors to the AVDD pin, which is on the periphery of 783
FC-PBGA the footprint, without the inductance of vias.
Figure 75 shows the PLL power supply filter Circuit.
10 Ω
V
AV
DD
DD
2.2 µF
2.2 µF
Low ESL Surface Mount Capacitors
GND
Figure 75. MPC8536E PLL Power Supply Filter Circuit
The AVDD_SRDSn signals provides power for the analog portions of the SerDes PLL. To ensure stability of the internal clock,
the power supplied to the PLL is filtered using a circuit similar to the one shown in following Figure 76. For maximum
effectiveness, the filter circuit is placed as closely as possible to the AVDD_SRDSn balls to ensure it filters out as much noise
as possible. The ground connection should be near the AVDD_SRDSn balls. The 0.003-µF capacitor is closest to the balls,
followed by the 1-µF capacitor, and finally the 1 ohm resistor to the board supply plane. The capacitors are connected from
AV DD_SRDSn to the ground plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces
should be kept short, wide and direct.
1.0 Ω
SnV
AV
SRDS
DD
DD -
1
1
0.003 µF
2.2 µF
2.2 µF
GND
1. An 0805 sized capacitor is recommended for system initial bring-up
Figure 76. SerDes PLL Power Supply Filter Circuit
Note the following:
•
•
AVDD should be a filtered version of SVDD
.
Signals on the SerDes interface are fed from the XVDD power plane.
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
115
Pin States in Deep Sleep State
3.3
Pin States in Deep Sleep State
In all low power mode by default, all input and output pads remain driven as per normal functional operation. The inputs remain
enabled.
The exception is that in Deep Sleep mode, GCR[DEEPSLEEP_Z] can be used to tristate a subset of output pads, and disable
the receivers of input pads as defined in Table 1. See the MPC8536E PowerQUICC™ III Integrated Processor Reference
Manual for details.
3.4
Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the device can generate transient power surges and high
frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching
other components in the MPC8536E system, and the device itself requires a clean, tightly regulated source of power. Therefore,
it is recommended that the system designer place at least one decoupling capacitor at each VDD, TVDD, BVDD, OVDD, GVDD
and LVDD pin of the device. These decoupling capacitors should receive their power from separate VDD,TVDD, BVDD, OVDD
,
,
GVDD, and LVDD, and GND power planes in the PCB, utilizing short low impedance traces to minimize inductance. Capacitors
must be placed directly under the device using a standard escape pattern as much as possible. If some caps are to be placed
surrounding the part it should be routed with short and large trace to minimize the inductance.
These capacitors should have a value of 0.1 µF. Only ceramic SMT (surface mount technology) capacitors should be used to
minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the VDD, TVDD
,
BVDD, OVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should
have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected
to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS
tantalum or Sanyo OSCON). However, customers should work directly with their power regulator vendor for best values types
and quantity of bulk capacitors.
3.5
SerDes Block Power Supply Decoupling Recommendations
he SerDes1 and SerDes2 blocks require a clean, tightly regulated source of power (SnVDD and XnVDD) to ensure low jitter on
transmit and reliable recovery of data in the receiver. An appropriate decoupling scheme is outlined below.
Only surface mount technology (SMT) capacitors should be used to minimize inductance. Connections from all capacitors to
power and ground should be done with multiple vias to further reduce inductance.
•
First, the board should have at least 10 x 10-nF SMT ceramic chip capacitors as close as possible to the supply balls
of the device. Where the board has blind vias, these capacitors should be placed directly below the chip supply and
ground connections. Where the board does not have blind vias, these capacitors should be placed in a ring around the
device as close to the supply and ground connections as possible.
•
•
Second, there should be a 1-µF ceramic chip capacitor from each SerDes supply (SnVDD and XnVDD) to the board
ground plane on each side of the device. This should be done for all SerDes supplies.
Third, between the device and any SerDes voltage regulator there should be a 10-µF, low equivalent series resistance
(ESR) SMT tantalum chip capacitor and a 100-µF, low ESR SMT tantalum chip capacitor. This should be done for all
SerDes supplies.
3.6
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. All unused active
low inputs should be tied to VDD,TVDD, BVDD, OVDD, GVDD, and LVDD as required. All unused active high inputs should be
connected to GND. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all
external VDD,TVDD, BVDD, OVDD, GVDD, and LVDD and GND pins of the device.
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
116
Freescale Semiconductor
Pull-Up and Pull-Down Resistor Requirements
3.7
Pull-Up and Pull-Down Resistor Requirements
The MPC8536E requires weak pull-up resistors (2–10 kΩ is recommended) on open drain type pins including I2C pins and
MPIC interrupt pins.
Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure 78.
Care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most
have asynchronous behavior and spurious assertion will give unpredictable results.
The following pins must NOT be pulled down during power-on reset: TSEC1_TXD[3], HRESET_REQ,
TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP. The UART_SOUT[0:1] and TEST_SEL pins must be set to a
proper state during POR configuration. Please refer to the pinlist table (see Table 62) of the individual device for more details.
See the PCI 2.2 specification for all pull-ups required for PCI.
3.8
Output Buffer DC Impedance
The MPC8536E drivers are characterized over process, voltage, and temperature. For all buses, the driver is a push-pull
single-ended driver type (open drain for I2C).
To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD or GND. Then, the
value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 77). The output impedance is the average of two
components, the resistances of the pull-up and pull-down devices. When data is held high, SW1 is closed (SW2 is open) and
RP is trimmed until the voltage at the pad equals OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN
are designed to be close to each other in value. Then, Z0 = (RP + RN)/2.
OV
DD
R
N
SW2
SW1
Pad
Data
R
P
OGND
Figure 77. Driver Impedance Measurement
Table 81 summarizes the signal impedance targets. The driver impedances are targeted at minimum VDD, nominal OVDD
,
105°C.
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
117
Configuration Pin Muxing
Table 81. Impedance Characteristics
Local Bus, Ethernet, DUART,
Impedance Control, Configuration, Power
Management
PCI
DDR DRAM
Symbol Unit
R
45 Target
45 Target (cfg_pci_impd=1) 18 Target (full strength mode)
25 Target (cfg_pci_impd=0) 36 Target (full strength mode)
Z
Ω
0
N
P
R
45 Target
45 Target (cfg_pci_impd=1) 18 Target (full strength mode)
25 Target (cfg_pci_impd=0) 36 Target (full strength mode)
Z
Ω
0
Note: Nominal supply voltages. See Table 1.
3.9
Configuration Pin Muxing
The MPC8536E provides the user with power-on configuration options which can be set through the use of external pull-up or
pull-down resistors of 4.7 kΩ on certain output pins (see customer visible configuration pins). These pins are generally used as
output only pins in normal operation.
While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins while HRESET is
asserted, is latched when HRESET deasserts, at which time the input receiver is disabled and the I/O circuit takes on its normal
function. Most of these sampled configuration pins are equipped with an on-chip gated resistor of approximately 20 kΩ. This
value should permit the 4.7-kΩ resistor to pull the configuration pin to a valid logic low level. The pull-up resistor is enabled
only during HRESET (and for platform /system clocks after HRESET deassertion to ensure capture of the reset value). When
the input receiver is disabled the pull-up is also, thus allowing functional operation of the pin as an output with minimal signal
quality or delay disruption. The default value for all configuration bits treated this way has been encoded such that a high voltage
level puts the device into the default state and external resistors are needed only when non-default settings are required by the
user.
Careful board layout with stubless connections to these pull-down resistors coupled with the large value of the pull-down
resistor should minimize the disruption of signal quality or speed for output pins thus configured.
The platform PLL ratio and e500 PLL ratio configuration pins are not equipped with these default pull-up devices.
3.10 JTAG Configuration Signals
Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure 78.
Care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most
have asynchronous behavior and spurious assertion will give unpredicatable results.
Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE 1149.1
specification, but it is provided on all processors built on Power Architecture technology. The device requires TRST to be
asserted during power-on reset flow to ensure that the JTAG boundary logic does not interfere with normal chip operation.
While the TAP controller can be forced to the reset state using only the TCK and TMS signals, generally systems assert TRST
during the power-on reset flow. Simply tying TRST to HRESET is not practical because the JTAG interface is also used for
accessing the common on-chip processor (COP), which implements the debug interface to the chip.
The COP function of these processors allow a remote computer system (typically, a PC with dedicated hardware and debugging
software) to access and control the internal operations of the processor. The COP interface connects primarily through the JTAG
port of the processor, with some additional status monitoring signals. The COP port requires the ability to independently assert
HRESET or TRST in order to fully control the processor. If the target system has independent reset sources, such as voltage
monitors, watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be merged into
these signals with logic.
The arrangement shown in Figure 78 allows the COP port to independently assert HRESET or TRST, while ensuring that the
target can drive HRESET as well.
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
118
Freescale Semiconductor
JTAG Configuration Signals
The COP interface has a standard header, shown in Figure 79, for connection to the target system, and is based on the 0.025"
square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a
connector key.
The COP header adds many benefits such as breakpoints, watchpoints, register and memory examination/modification, and
other standard debugger features. An inexpensive option can be to leave the COP header unpopulated until needed.
There is no standardized way to number the COP header; consequently, many different pin numbers have been observed from
emulator vendors. Some are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom, while
still others number the pins counter clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement
recommended in Figure 79 is common to all known emulators.
3.10.1 Termination of Unused Signals
If the JTAG interface and COP header will not be used, Freescale recommends the following connections:
•
TRST should be tied to HRESET through a 0 kΩ isolation resistor so that it is asserted when the system reset signal
(HRESET) is asserted, ensuring that the JTAG scan chain is initialized during the power-on reset flow. Freescale
recommends that the COP header be designed into the system as shown in Figure 78. If this is not possible, the
isolation resistor will allow future access to TRST in case a JTAG interface may need to be wired onto the system in
future debug situations.
•
No pull-up/pull-down is required for TDI, TMS, or TDO.
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
119
JTAG Configuration Signals
OV
DD
10 kΩ
10 kΩ
6
1
SRESET
SRESET
HRESET
From Target
Board Sources
(if any)
HRESET
COP_HRESET
13
11
10 kΩ
10 kΩ
10 kΩ
10 kΩ
COP_SRESET
5
1
TRST
COP_TRST
4
2
4
1
3
5
7
9
2
10 Ω
COP_VDD_SENSE
NC
6
6
3
5
8
COP_CHKSTP_OUT
CKSTP_OUT
15
10 kΩ
10
3
14
11 12
10 kΩ
KEY
13
COP_CHKSTP_IN
COP_TMS
No pin
CKSTP_IN
TMS
8
9
1
15
16
COP_TDO
COP_TDI
COP_TCK
COP Connector
Physical Pinout
TDO
3
7
TDI
TCK
NC
NC
2
10 kΩ
10
4
12
16
Notes:
1. The COP port and target board should be able to independently assert HRESET and TRST to the processor in
order to fully control the processor as shown here.
2. Populate this with a 10 Ω resistor for short-circuit/current-limiting protection.
3. The KEY location (pin 14) is not physically present on the COP header.
4. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for
improved signal integrity.
5. This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing
to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed to
position B.
6. Asserting SRESET causes a machine check interrupt to the e500 core.
Figure 78. JTAG Interface Connection
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
120
Freescale Semiconductor
Guidelines for High-Speed Interface Termination
2
4
1
3
COP_TDO
COP_TDI
NC
COP_TRST
COP_VDD_SENSE
COP_CHKSTP_IN
NC
5
7
6
8
COP_TCK
COP_TMS
COP_SRESET
9
10
12
NC
NC
11
KEY
13
15
COP_HRESET
No pin
GND
COP_CHKSTP_OUT
16
Figure 79. COP Connector Physical Pinout
3.11 Guidelines for High-Speed Interface Termination
3.11.1 SerDes1 Interface Entirely Unused
If the high-speed SerDes interface is not used at all, the unused pin should be terminated as described in this section. However,
the SerDes must always have power applied to its supply pins. See SerDes1 in Table 1 for details.
The following pins must be left unconnected (float):
•
•
•
SD1_TX[7:0]
SD1_TX[7:0]
Reserved pins T22, T23
The following pins must be connected to XGND:
•
•
•
•
SD1_RX[7:0]
SD1_RX[7:0]
SD1_REF_CLK
SD1_REF_CLK
The POR configuration pin cfg_io_ports[0:2] on TSEC3_TXD[6:3] can be used to power down SerDes 1 block for power
saving. Note that both SVDD and XVDD must remain powered.
3.11.2 SerDes 1 Interface Partly Unused
If only part of the high speed SerDes interface pins are used, the remaining high-speed serial I/O pins should be terminated as
described in this section.
The following pins must be left unconnected (float) if not used:
•
•
•
SD1_TX[7:0]
SD1_TX[7:0]
Reserved pins: T22, T23
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
121
Guidelines for High-Speed Interface Termination
The following pins must be connected to XGND if not used:
•
•
•
•
SD1_RX[7:0]
SD1_RX[7:0]
SD1_REF_CLK
SD1_REF_CLK
3.11.3 SerDes 2 Interface Entirely Unused
If the high-speed SerDes 2 interface (SGMII/ SATA) is not used at all, the unused pin should be terminated as described in this
section. See SerDes2 in Table 1 for details.
The following pins must be left unconnected (float):
•
•
•
SD2_TX[1:0]
SD2_TX[1:0]
Reserved pins L8, L9
The following pins must be connected to X2GND:
•
•
•
•
SD2_RX[1:0]
SD2_RX[1:0]
SD2_REF_CLK
SD2_REF_CLK
The POR configuration pin cfg_srds2_prtcl[0:2] on TSEC1_TXD[2], TSEC3_TXD[2], TSEC_1588_PUSLE_OUT1 can be
used to power down SerDes 2 block for power saving. Note that both S2VDD and X2VDD must remain powered.
3.11.4 SerDes 2 Interface Partly Unused
If only part of the high speed SerDes 2 (SGMII/SATA) interface pins are used, the remaining high-speed serial I/O pins should
be terminated as described in this section.
The following pins must be left unconnected (float) if not used:
•
•
•
SD2_TX[1:0]
SD2_TX[1:0]
Reserved pins: T22, T23
The following pins must be connected to X2GND if not used:
•
•
SD2_RX[1:0]
SD2_RX[1:0]
4
Ordering Information
Ordering information for the parts fully covered by this specification document is provided in Section 4.1, “Part Numbers Fully
Addressed by This Document.”
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
122
Freescale Semiconductor
Part Numbers Fully Addressed by This Document
4.1
Part Numbers Fully Addressed by This Document
Table 82. Device Nomenclature
MPC
Product
nnnn
Part
E
C
VT
AA
X
R
Security
Engine
Tiers and Temperature
Range
Processor
Frequency
DDR
Frequency
Revision
Level
1
Package
2
3
Code Identifier
MPC 8536
A = Commercial Tier
standard temperature
E = included range(0° to 90°C)
B or Blank =Industrial
Tier
VT = FC-PBGA AK = 600 MHz
G = 400 MHz
H = 500 MHz
J = 533 MHz
L = 667 MHz
—
(lead free)
PX = plastic
Standard
AN = 800 MHz
AQ = 1000 MHz
AT = 1250 MHz
AU = 1333 MHz
AV = 1500 MHz
standard temperature
range(0° to 105°C)
C = Industrial Tier
Blank = not
—
Extended temperature
included
range(–40° to 105°C)
Notes:
1. See Section 5, “Package Information,” for more information on available package types.
2. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this specification
support all core frequencies. Additionally, parts addressed by part number specifications may support other maximum core
frequencies.
3. See Table 84 for the corresponding maximum platform frequency
4.2
Part Marking
Parts are marked as in the example shown in Figure 80.
MPC853nVTnnnn
ATWLYYWW
MMMMM CCCCC
YWWLAZ
FC-PBGA
Notes:
MMMMM is the 5-digit mask number.
ATWLYYWW is the traceability code.
CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States.
Figure 80. Part Marking for FC-PBGA Device
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
123
Part Numbering
4.3
Part Numbering
Table 83 and Table 84 list all part numbers that are offered for MPC8536E.
Table 83. MPC8536 Part Numbers Commercial Tier
Standard Temp Without Security Standard Temp With Security
Core/Platform/DDR (MHz)
Notes
600/400/400
800/400/400
1000/400/400
1250/500/500
1333/533/667
1500/500/667
MPC8536AVTAKG
MPC8536AVTANG
MPC8536AVTAQG
MPC8536AVTATH
MPC8536AVTAUL
MPC8536AVTAVL
MPC8536EAVTAKG
MPC8536EAVTANG
MPC8536EAVTAQG
MPC8536EAVTATH
MPC8536EAVTAUL
MPC8536EAVTAVL
—
—
—
—
—
—
Table 84. MPC8536 Part Numbers Industrial Tier
Core/Platform/
DDR (MHz)
Standard Temp
Without Security
Standard Temp
With Security
Extended Temp
Without Security
Extended Temp
With Security
Notes
600/400/400
800/400/400
1000/400/400
1250/500/500
1333/533/667
1500/500/667
MPC8536BVTAKG
MPC8536BVTANG
MPC8536BVTAQG
MPC8536BVTATH
MPC8536BVTAUL
MPC8536BVTAVL
MPC8536EBVTAKG
MPC8536EBVTANG
MPC8536EBVTAQG
MPC8536EBVTATH
MPC8536EBVTAUL
MPC8536EBVTAVL
MPC8536CVTAKG
MPC8536CVTANG
MPC8536CVTAQG
MPC8536CVTATH
MPC8536CVTAUL
MPC8536CVTAVL
MPC8536ECVTAKG
MPC8536ECVTANG
MPC8536ECVTAQG
MPC8536ECVTATH
MPC8536ECVTAUL
MPC8536ECVTAVL
—
5
Package Information
This section details package parameters, pin assignments, and dimensions.
5.1
Package Parameters for the MPC8536E FC-PBGA
The package parameters are as provided in the following list. The package type is 29 mm × 29 mm, 783 flip chip plastic ball
grid array (FC-PBGA) without a lid.
Package outline
Interconnects
29 mm × 29 mm
783
Pitch
1 mm
Minimum module height
Maximum module height
Solder Balls
2.23 mm
2.8 mm
96.5Sn/3.5Ag
0.6 mm
Ball diameter (typical)
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
124
Mechanical Dimensions of the MPC8536E FC-PBGA
5.2
Mechanical Dimensions of the MPC8536E FC-PBGA
The mechanical dimensions and bottom surface nomenclature of the MPC8536E, 783 FC-PBGA package are shown in
Figure 81.
Figure 81. Mechanical Dimensions and Bottom Surface Nomenclature of the MPC8536E FC-PBGA
NOTES for Figure 81
1. All dimensions are in millimeters.
2. Dimensions and tolerances per ASME Y14.5M-1994.
3. Maximum solder ball diameter measured parallel to datum A
4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls.
5. Capacitors may not be present on all devices
6. Caution must be taken not to short exposed metal capacitor pads on package top.
7. All dimensions are symmetric across the package center lines, unless dimensioned otherwise.
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
125
Mechanical Dimensions of the MPC8536E FC-PBGA
6
Product Documentation
The following documents are required for a complete description of the device and are needed to design properly with the part.
•
•
MPC8536E Integrated Processor Reference Manual (document number: MPC8536ERM)
e500 PowerPC Core Reference Manual (document number: E500CORERM)
7
Document Revision History
Table 85 provides a revision history for the MPC8536E hardware specification.
Table 85. Document Revision History
Revision
Date
Substantive Change(s)
2
09/2009
• In Section 1, “Pin Assignments and Reset States,”updated the first sentence of the note to say, “The
UART_SOUT[0:1] and TEST_SEL pins must be set to a proper state during POR configuration.”
• In Table 40, “SGMII DC Receiver Electrical Characteristics,” changed LSTSAB to LSTSA and
LSTSEF to LSTSE for Note 4.
• In Table 80, “MPC8536E Thermal Model,” updated die value and bump/underfill value.
• Updated Figure 81, “Mechanical Dimensions and Bottom Surface Nomenclature of the MPC8536E
FC-PBGA,” and its notes.
1
0
09/2009
08/2009
• In Table 5, ”MPC8536E Power Dissipation 5,” changed an “—”’ to “0.”
• Initial public release.
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
126
Mechanical Dimensions of the MPC8536E FC-PBGA
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MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
127
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Document Number: MPC8536EEC
Rev. 2
09/2009
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