MPC860DT [FREESCALE]
Hardware Specifications; 硬件规格型号: | MPC860DT |
厂家: | Freescale |
描述: | Hardware Specifications |
文件: | 总80页 (文件大小:2125K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MPC860EC
Rev. 7, 09/2004
Freescale Semiconductor
Technical Data
MPC860 Family
Hardware Specifications
Contents
This hardware specification contains detailed information on
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. Maximum Tolerated Ratings . . . . . . . . . . . . . . . . . . . 5
4. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . 6
5. Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
7. Thermal Calculation and Measurement . . . . . . . . . . . 9
8. Layout Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
9. Bus Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 12
10. IEEE 1149.1 Electrical Specifications . . . . . . . . . . . 41
11. CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 43
12. UTOPIA AC Electrical Specifications . . . . . . . . . . . 67
13. FEC Electrical Characteristics . . . . . . . . . . . . . . . . . 68
14. Mechanical Data and Ordering Information . . . . . . . 71
15. Document Revision History . . . . . . . . . . . . . . . . . . . 77
power considerations, DC/AC electrical characteristics, and AC
timing specifications for the MPC860 family.
1 Overview
The MPC860 Power Quad Integrated Communications Controller
(PowerQUICC™) is a versatile one-chip integrated
microprocessor and peripheral combination designed for a variety
of controller applications. It particularly excels in
communications and networking systems. The PowerQUICC unit
is referred to as the MPC860 in this hardware specification.
The MPC860 implements the PowerPC architecture and contains
a superset of Freescale’s MC68360 Quad Integrated
™
Communications Controller (QUICC ), referred to here as the
QUICC, RISC Communications Proccessor Module (CPM). The
CPM from the MC68360 QUICC has been enhanced by the
2
addition of the inter-integrated controller (I C) channel. The
memory controller has been enhanced, enabling the MPC860 to
support any type of memory, including high-performance
memories and new types of DRAMs. A PCMCIA socket
controller supports up to two sockets. A real-time clock has also
been integrated.
Table 1 shows the functionality supported by the members of the
MPC860 family.
© Freescale Semiconductor, Inc., 2004. All rights reserved.
Features
Table 1. MPC860 Family Functionality
Cache (Kbytes) Ethernet
Part
ATM
SCC
Reference 1
Instruction
Cache
Data Cache
10T
10/100
MPC860DE
MPC860DT
MPC860DP
MPC860EN
MPC860SR
MPC860T
4
4
4
4
8
4
4
4
8
4
Up to 2
Up to 2
Up to 2
Up to 4
Up to 4
Up to 4
Up to 4
1
—
1
—
2
2
2
4
4
4
4
1
1
1
1
1
1
1
1
2
Yes
Yes
—
16
4
1
—
—
1
4
Yes
Yes
Yes
Yes
4
MPC860P
MPC855T
16
4
1
1
1
Supporting documentation for these devices refers to the following:
1. MPC860 PowerQUICC Family User’s Manual (MPC860UM, Rev. 3)
2. MPC855T User’s Manual (MPC855TUM/D, Rev. 1)
2 Features
The following list summarizes the key MPC860 features:
TM
•
Embedded single-issue, 32-bit PowerPC core (implementing the PowerPC architecture) with
thirty-two 32-bit general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch without conditional execution.
— 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table 1)
– 16-Kbyte instruction caches are four-way, set-associative with 256 sets; 4-Kbyte instruction caches
are two-way, set-associative with 128 sets.
– 8-Kbyte data caches are two-way, set-associative with 256 sets; 4-Kbyte data caches are two-way,
set-associative with 128 sets.
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache
blocks.
– Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and
are lockable on a cache block basis.
— MMUs with 32-entry TLB, fully-associative instruction, and data TLBs
— MMUs support multiple page sizes of 4-, 16-, and 512-Kbytes, and 8-Mbytes; 16 virtual address spaces
and 16 protection groups
— Advanced on-chip-emulation debug mode
Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
32 address lines
•
•
•
•
Operates at up to 80 MHz
Memory controller (eight banks)
— Contains complete dynamic RAM (DRAM) controller
MPC860 Family Hardware Specifications, Rev. 7
2
Freescale Semiconductor
Features
— Each bank can be a chip select or RAS to support a DRAM bank.
— Up to 15 wait states programmable per memory bank
— Glueless interface to DRAM, SIMMS, SRAM, EPROM, Flash EPROM, and other memory devices
— DRAM controller programmable to support most size and speed memory interfaces
— Four CAS lines, four WE lines, and one OE line
— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
— Variable block sizes (32 Kbyte to 256 Mbyte)
— Selectable write protection
— On-chip bus arbitration logic
•
•
General-purpose timers
— Four 16-bit timers or two 32-bit timers
— Gate mode can enable/disable counting
— Interrupt can be masked on reference match and event capture.
System integration unit (SIU)
— Bus monitor
— Software watchdog
— Periodic interrupt timer (PIT)
— Low-power stop mode
— Clock synthesizer
— Decrementer, time base, and real-time clock (RTC) from the PowerPC architecture
— Reset controller
— IEEE 1149.1 test access port (JTAG)
Interrupts
•
— Seven external interrupt request (IRQ) lines
— 12 port pins with interrupt capability
— 23 internal interrupt sources
— Programmable priority between SCCs
— Programmable highest priority request
•
•
10/100 Mbps Ethernet support, fully compliant with the IEEE 802.3u Standard (not available when using
ATM over UTOPIA interface)
ATM support compliant with ATM forum UNI 4.0 specification
— Cell processing up to 50–70 Mbps at 50-MHz system clock
— Cell multiplexing/demultiplexing
— Support of AAL5 and AAL0 protocols on a per-VC basis. AAL0 support enables OAM and software
implementation of other protocols.
— ATM pace control (APC) scheduler, providing direct support for constant bit rate (CBR) and
unspecified bit rate (UBR) and providing control mechanisms enabling software support of available
bit rate (ABR)
— Physical interface support for UTOPIA (10/100-Mbps is not supported with this interface) and
byte-aligned serial (for example, T1/E1/ADSL)
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
3
Features
— UTOPIA-mode ATM supports level-1 master with cell-level handshake, multi-PHY (up to four physical
layer devices), connection to 25-, 51-, or 155-Mbps framers, and UTOPIA/system clock ratios of 1/2 or
1/3.
— Serial-mode ATM connection supports transmission convergence (TC) function for T1/E1/ADSL lines,
cell delineation, cell payload scrambling/descrambling, automatic idle/unassigned cell
insertion/stripping, header error control (HEC) generation, checking, and statistics.
•
Communications processor module (CPM)
— RISC communications processor (CP)
— Communication-specific commands (for example, GRACEFUL STOP TRANSMIT, ENTER HUNT MODE, and
RESTART TRANSMIT)
— Supports continuous mode transmission and reception on all serial channels
— Up to 8 Kbytes of dual-port RAM
— 16 serial DMA (SDMA) channels
— Three parallel I/O registers with open-drain capability
Four baud-rate generators (BRGs)
•
•
— Independent (can be tied to any SCC or SMC)
— Allows changes during operation
— Autobaud support option
Four serial communications controllers (SCCs)
— Ethernet/IEEE 802.3 optional on SCC1–4, supporting full 10-Mbps operation (available only on
specially programmed devices)
— HDLC/SDLC (all channels supported at 2 Mbps)
— HDLC bus (implements an HDLC-based local area network (LAN))
— Asynchronous HDLC to support point-to-point protocol (PPP)
— AppleTalk
— Universal asynchronous receiver transmitter (UART)
— Synchronous UART
— Serial infrared (IrDA)
— Binary synchronous communication (BISYNC)
— Totally transparent (bit streams)
— Totally transparent (frame-based with optional cyclic redundancy check (CRC))
Two SMCs (serial management channels)
— UART
•
— Transparent
— General circuit interface (GCI) controller
— Can be connected to the time-division multiplexed (TDM) channels
One SPI (serial peripheral interface)
•
•
— Supports master and slave modes
— Supports multimaster operation on the same bus
2
One I C (inter-integrated circuit) port
— Supports master and slave modes
MPC860 Family Hardware Specifications, Rev. 7
4
Freescale Semiconductor
Maximum Tolerated Ratings
— Multiple-master environment support
Time-slot assigner (TSA)
•
— Allows SCCs and SMCs to run in multiplexed and/or non-multiplexed operation
— Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user defined
— 1- or 8-bit resolution
— Allows independent transmit and receive routing, frame synchronization, and clocking
— Allows dynamic changes
— Can be internally connected to six serial channels (four SCCs and two SMCs)
Parallel interface port (PIP)
•
•
— Centronics interface support
— Supports fast connection between compatible ports on the MPC860 or the MC68360
PCMCIA interface
— Master (socket) interface, release 2.1 compliant
— Supports two independent PCMCIA sockets
— Supports eight memory or I/O windows
•
Low power support
— Full on—all units fully powered
— Doze—core functional units disabled except time base decrementer, PLL, memory controller, RTC, and
CPM in low-power standby
— Sleep—all units disabled except RTC and PIT, PLL active for fast wake up
— Deep sleep—all units disabled including PLL except RTC and PIT
— Power down mode—all units powered down except PLL, RTC, PIT, time base, and decrementer
Debug interface
•
— Eight comparators: four operate on instruction address, two operate on data address, and two operate on
data
— Supports conditions: = ≠ < >
— Each watchpoint can generate a break-point internally.
3.3-V operation with 5-V TTL compatibility except EXTAL and EXTCLK
357-pin ball grid array (BGA) package
•
•
3 Maximum Tolerated Ratings
This section provides the maximum tolerated voltage and temperature ranges for the MPC860. Table 2 provides the
maximum ratings.
This device contains circuitry protecting against damage due to high-static voltage or electrical fields; however, it
is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages
to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic
voltage level (for example, either GND or V ).
dd
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
5
Thermal Characteristics
Table 2. Maximum Tolerated Ratings
(GND = 0 V)
Rating
Symbol
Value
Unit
Supply voltage 1
VDDH
VDDL
–0.3 to 4.0
–0.3 to 4.0
–0.3 to 4.0
–0.3 to 4.0
V
V
V
V
V
KAPWR
VDDSYN
Vin
Input voltage 2
GND – 0.3 to
VDDH
Temperature 3 (standard)
TA(min)
Tj(max)
TA(min)
Tj(max)
Tstg
0
95
°C
°C
°C
°C
°C
Temperature 3 (extended)
–40
95
Storage temperature range
–55 to 150
1
The power supply of the device must start its ramp from 0.0 V.
2
Functional operating conditions are provided with the DC electrical specifications in Table 6. Absolute maximum
ratings are stress ratings only; functional operation at the maxima is not guaranteed. Stress beyond those listed may
affect device reliability or cause permanent damage to the device.
Caution: All inputs that tolerate 5 V cannot be more than 2.5 V greater than the supply voltage. This restriction applies
to power-up and normal operation (that is, if the MPC860 is unpowered, voltage greater than 2.5 V must not be
applied to its inputs).
3
Minimum temperatures are guaranteed as ambient temperature, TA. Maximum temperatures are guaranteed as
junction temperature, Tj.
4 Thermal Characteristics
Table 3. Package Description
Package Designator
Package Code (Case No.)
Package Description
ZP
5050 (1103-01)
PBGA 357 25*25*0.9P1.27
PBGA 357 25*25*1.2P1.27
ZQ / VR
5058 (1103D-02)
Table 4 shows the thermal characteristics for the MPC860.
MPC860 Family Hardware Specifications, Rev. 7
6
Freescale Semiconductor
Power Dissipation
Table 4. MPC860 Thermal Resistance Data
ZP
ZQ / VR
Unit
Rating
Environment
Symbol
MPC860P MPC860P
Mold Compound Thickness
0.85
34
22
27
18
14
6
1.15
34
22
27
18
13
8
mm
1
2
Junction-to-ambient
Natural convection
Single-layer board (1s)
RθJA
°C/W
3
Four-layer board (2s2p)
Single-layer board (1s)
Four-layer board (2s2p)
RθJMA
3
Airflow (200 ft/min)
RθJMA
3
RθJMA
4
Junction-to-board
RθJB
RθJC
ΨJT
5
Junction-to-case
6
Junction-to-package top Natural convection
2
2
1
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2
3
4
Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
5
Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate
method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. For exposed pad
packages where the pad would be expected to be soldered, junction-to-case thermal resistance is a simulated value from
the junction to the exposed pad without contact resistance.
6
Thermal characterization parameter indicating the temperature difference between the package top and the junction
temperature per JEDEC JESD51-2.
5 Power Dissipation
Table 5 provides power dissipation information. The modes are 1:1, where CPU and bus speeds are equal, and 2:1,
where CPU frequency is twice the bus speed.
Table 5. Power Dissipation (PD)
1
2
Die Revision
Frequency (MHz) Typical
Maximum
Unit
D.4
50
66
66
80
656
TBD
722
851
735
TBD
762
909
mW
mW
mW
mW
(1:1 mode)
D.4
(2:1 mode)
1
2
Typical power dissipation is measured at 3.3 V.
Maximum power dissipation is measured at 3.5 V.
NOTE
-based power dissipation and do not include I/O
Values in Table 5 represent V
DDL
power dissipation over V
. I/O power dissipation varies widely by application
DDH
due to buffer current, depending on external circuitry.
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
7
DC Characteristics
6 DC Characteristics
Table 6 provides the DC electrical characteristics for the MPC860.
Table 6. DC Electrical Specifications
Symbol
Characteristic
Min
Max
Unit
Operating voltage at 40 MHz or less
VDDH, VDDL, VDDSYN
3.0
2.0
3.6
3.6
V
V
KAPWR
(power-down mode)
KAPWR
(all other operating modes)
VDDH – 0.4
3.135
VDDH
3.465
3.6
V
V
V
V
V
Operating voltage greater than 40 MHz
VDDH, VDDL, KAPWR,
VDDSYN
KAPWR
(power-down mode)
2.0
KAPWR
(all other operating modes)
VDDH – 0.4
2.0
VDDH
5.5
Input high voltage (all inputs except EXTAL and
EXTCLK)
VIH
Input low voltage 1
VIL
VIHC
Iin
GND
0.7 × (VDDH
—
0.8
VDDH + 0.3
100
V
V
EXTAL, EXTCLK input high voltage
)
Input leakage current, Vin = 5.5 V (except TMS,
TRST, DSCK, and DSDI pins)
µA
Input leakage current, Vin = 3.6 V (except TMS,
TRST, DSCK, and DSDI pins)
IIn
—
—
10
10
µA
µA
Input leakage current, Vin = 0 V (except TMS,
TRST, DSCK, and DSDI pins)
IIn
2
Input capacitance
Cin
—
20
—
pF
V
Output high voltage, IOH = –2.0 mA, VDDH = 3.0 V
(except XTAL, XFC, and open-drain pins)
VOH
2.4
Output low voltage
VOL
—
0.5
V
IOL = 2.0 mA, CLKOUT
3
IOL = 3.2 mA
IOL = 5.3 mA
4
IOL = 7.0 mA, TXD1/PA14, TXD2/PA12
IOL = 8.9 mA, TS, TA, TEA, BI, BB,
HRESET, SRESET
1
VIL(max) for the I2C interface is 0.8 V rather than the 1.5 V as specified in the I2C standard.
Input capacitance is periodically sampled.
2
MPC860 Family Hardware Specifications, Rev. 7
8
Freescale Semiconductor
Thermal Calculation and Measurement
A(0:31), TSIZ0/REG, TSIZ1, D(0:31), DP(0:3)/IRQ(3:6), RD/WR, BURST, RSV/IRQ2, IP_B(0:1)/IWP(0:1)/
3
VFLS(0:1), IP_B2/IOIS16_B/AT2, IP_B3/IWP2/VF2, IP_B4/LWP0/VF0, IP_B5/LWP1/VF1, IP_B6/DSDI/AT0,
IP_B7/PTR/AT3, RXD1 /PA15, RXD2/PA13, L1TXDB/PA11, L1RXDB/PA10, L1TXDA/PA9, L1RXDA/PA8,
TIN1/L1RCLKA/BRGO1/CLK1/PA7, BRGCLK1/TOUT1/CLK2/PA6, TIN2/L1TCLKA/BRGO2/CLK3/PA5,
TOUT2/CLK4/PA4, TIN3/BRGO3/CLK5/PA3, BRGCLK2/L1RCLKB/TOUT3/CLK6/PA2, TIN4/BRGO4/CLK7/
PA1, L1TCLKB/TOUT4/CLK8/PA0, REJCT1/SPISEL/PB31, SPICLK/PB30, SPIMOSI/PB29, BRGO4/SPIMISO/
PB28, BRGO1/I2CSDA/PB27, BRGO2/I2CSCL/PB26, SMTXD1/PB25, SMRXD1/PB24, SMSYN1/SDACK1/
PB23, SMSYN2/SDACK2/PB22, SMTXD2/L1CLKOB/PB21, SMRXD2/L1CLKOA/PB20, L1ST1/RTS1/PB19,
L1ST2/RTS2/PB18, L1ST3/L1RQB/PB17, L1ST4/L1RQA/PB16, BRGO3/PB15, RSTRT1/PB14, L1ST1/RTS1/
DREQ0/PC15, L1ST2/RTS2/DREQ1/PC14, L1ST3/L1RQB/PC13, L1ST4/L1RQA/PC12, CTS1/PC11,
TGATE1/CD1/PC10, CTS2/PC9, TGATE2/CD2/PC8, SDACK2/L1TSYNCB/PC7, L1RSYNCB/PC6, SDACK1/
L1TSYNCA/PC5, L1RSYNCA/PC4, PD15, PD14, PD13, PD12, PD11, PD10, PD9, PD8, PD5, PD6, PD7, PD4, PD3,
MII_MDC, MII_TX_ER, MII_EN, MII_MDIO, MII_TXD[0:3]
4
BDIP/GPL_B(5), BR, BG, FRZ/IRQ6, CS(0:5), CS(6)/CE(1)_B, CS(7)/CE(2)_B, WE0/BS_B0/IORD,
WE1/BS_B1/IOWR, WE2/BS_B2/PCOE, WE3/BS_B3/PCWE, BS_A(0:3), GPL_A0/GPL_B0, OE/GPL_A1/
GPL_B1, GPL_A(2:3)/GPL_B(2:3)/CS(2:3), UPWAITA/GPL_A4, UPWAITB/GPL_B4, GPL_A5, ALE_A, CE1_A,
CE2_A, ALE_B/DSCK/AT1, OP(0:1), OP2/MODCK1/STS, OP3/MODCK2/DSDO, BADDR(28:30)
7 Thermal Calculation and Measurement
For the following discussions, P = (V × I ) + PI/O, where PI/O is the power dissipation of the I/O drivers.
D
DD
DD
7.1 Estimation with Junction-to-Ambient Thermal Resistance
An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation:
T = T + (R
× P )
D
J
A
θJA
where:
T = ambient temperature (ºC)
A
R
= package junction-to-ambient thermal resistance (ºC/W)
θJA
P = power dissipation in package
D
The junction-to-ambient thermal resistance is an industry standard value which provides a quick and easy estimation
of thermal performance. However, the answer is only an estimate; test cases have demonstrated that errors of a factor
of two (in the quantity T – T ) are possible.
J
A
7.2 Estimation with Junction-to-Case Thermal Resistance
Historically, the thermal resistance has frequently been expressed as the sum of a junction-to-case thermal resistance
and a case-to-ambient thermal resistance:
R
= R
+ R
θJC θCA
θJA
where:
R
R
R
= junction-to-ambient thermal resistance (ºC/W)
= junction-to-case thermal resistance (ºC/W)
= case-to-ambient thermal resistance (ºC/W)
θJA
θJC
θCA
R
is device related and cannot be influenced by the user. The user adjusts the thermal environment to affect the
θJC
case-to-ambient thermal resistance, R
heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the
. For instance, the user can change the air flow around the device, add a
θCA
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
9
Thermal Calculation and Measurement
printed circuit board surrounding the device. This thermal model is most useful for ceramic packages with heat sinks
where some 90% of the heat flows through the case and the heat sink to the ambient environment. For most
packages, a better model is required.
7.3 Estimation with Junction-to-Board Thermal Resistance
A simple package thermal model which has demonstrated reasonable accuracy (about 20%) is a two-resistor model
consisting of a junction-to-board and a junction-to-case thermal resistance. The junction-to-case thermal resistance
covers the situation where a heat sink is used or where a substantial amount of heat is dissipated from the top of the
package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is
conducted to the printed circuit board. It has been observed that the thermal performance of most plastic packages,
especially PBGA packages, is strongly dependent on the board temperature; see Figure 1.
Board Temperature Rise Above Ambient Divided by Package Power
Figure 1. Effect of Board Temperature Rise on Thermal Behavior
If the board temperature is known, an estimate of the junction temperature in the environment can be made using
the following equation:
T = T + (R
× P )
D
J
B
θJB
where:
R
= junction-to-board thermal resistance (ºC/W)
θJB
T = board temperature (ºC)
B
P = power dissipation in package
D
If the board temperature is known and the heat loss from the package case to the air can be ignored, acceptable
predictions of junction temperature can be made. For this method to work, the board and board mounting must be
similar to the test board used to determine the junction-to-board thermal resistance, namely a 2s2p (board with a
power and a ground plane) and by attaching the thermal balls to the ground plane.
MPC860 Family Hardware Specifications, Rev. 7
10
Freescale Semiconductor
Layout Practices
7.4 Estimation Using Simulation
When the board temperature is not known, a thermal simulation of the application is needed. The simple two-resistor
model can be used with the thermal simulation of the application [2], or a more accurate and complex model of the
package can be used in the thermal simulation.
7.5 Experimental Determination
To determine the junction temperature of the device in the application after prototypes are available, the thermal
characterization parameter (Ψ ) can be used to determine the junction temperature with a measurement of the
JT
temperature at the top center of the package case using the following equation:
T = T + (Ψ × P )
J
T
JT
D
where:
Ψ
= thermal characterization parameter
JT
T = thermocouple temperature on top of package
T
P = power dissipation in package
D
The thermal characterization parameter is measured per JEDEC JESD51-2 specification using a 40 gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the
thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and
over 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to
avoid measurement errors caused by cooling effects of the thermocouple wire.
7.6 References
Semiconductor Equipment and Materials International
805 East Middlefield Rd.
(415) 964-5111
Mountain View, CA 94043
MIL-SPEC and EIA/JESD (JEDEC) Specifications
(Available from Global Engineering Documents)
800-854-7179 or
303-397-7956
JEDEC Specifications
http://www.jedec.org
1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive
Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54.
2. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its
Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212–220.
8 Layout Practices
Each VDD pin on the MPC860 should be provided with a low-impedance path to the board’s supply. Each GND pin
should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct groups of
logic on the chip. The VDD power supply should be bypassed to ground using at least four 0.1 µF-bypass capacitors
located as close as possible to the four sides of the package. The capacitor leads and associated printed circuit traces
connecting to chip VDD and GND should be kept to less than half an inch per capacitor lead. A four-layer board
employing two inner layers as VCC and GND planes is recommended.
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
11
Bus Signal Timing
All output pins on the MPC860 have fast rise and fall times. Printed circuit (PC) trace interconnection length should
be minimized in order to minimize undershoot and reflections caused by these fast output switching times. This
recommendation particularly applies to the address and data buses. Maximum PC trace lengths of 6 inches are
recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances due to the
PC traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher
capacitive loads because these loads create higher transient currents in the VCC and GND circuits. Pull up all unused
inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the
PLL supply pins.
9 Bus Signal Timing
Table 7 provides the bus operation timing for the MPC860 at 33, 40, 50, and 66 MHz.
The maximum bus speed supported by the MPC860 is 66 MHz. Higher-speed parts must be operated in half-speed
bus mode (for example, an MPC860 used at 80 MHz must be configured for a 40 MHz bus).
The timing for the MPC860 bus shown assumes a 50-pF load for maximum delays and a 0-pF load for minimum
delays.
Table 7. Bus Operation Timings
33 MHz
Min Max
30.30 30.30 25.00 30.30 20.00 30.30 15.15 30.30 ns
40 MHz
50 MHz
66 MHz
Num
Characteristic
Unit
Min Max
Min Max
Min Max
B1
CLKOUT period
B1a EXTCLK to CLKOUT phase skew
(EXTCLK > 15 MHz and MF <= 2)
–0.90 0.90 –0.90 0.90 –0.90 0.90 –0.90 0.90
–2.30 2.30 –2.30 2.30 –2.30 2.30 –2.30 2.30
–0.60 0.60 –0.60 0.60 –0.60 0.60 –0.60 0.60
–2.00 2.00 –2.00 2.00 –2.00 2.00 –2.00 2.00
ns
ns
ns
B1b EXTCLK to CLKOUT phase skew
(EXTCLK > 10 MHz and MF < 10)
B1c CLKOUT phase jitter (EXTCLK >
1
15 MHz and MF <= 2)
B1d CLKOUT phase jitter1
ns
%
%
B1e CLKOUT frequency jitter (MF < 10) 1
—
—
0.50
2.00
—
—
0.50
2.00
—
—
0.50
2.00
—
—
0.50
2.00
B1f CLKOUT frequency jitter (10 < MF
< 500) 1
B1g CLKOUT frequency jitter (MF > 500)
—
3.00
—
3.00
—
3.00
—
3.00
%
1
2
B1h Frequency jitter on EXTCLK
—
12.12
12.12
—
0.50
—
—
10.00
10.00
—
0.50
—
—
8.00
8.00
—
0.50
—
—
6.06
6.06
—
0.50
—
%
ns
ns
ns
ns
ns
B2
B3
B4
CLKOUT pulse width low
CLKOUT width high
CLKOUT rise time 3
—
—
—
—
4.00
4.00
—
4.00
4.00
—
4.00
4.00
—
4.00
4.00
—
B533 CLKOUT fall time3
—
—
—
—
B7
CLKOUT to A(0:31), BADDR(28:30), 7.58
RD/WR, BURST, D(0:31), DP(0:3)
invalid
6.25
5.00
3.80
MPC860 Family Hardware Specifications, Rev. 7
12
Freescale Semiconductor
Bus Signal Timing
Table 7. Bus Operation Timings (continued)
33 MHz 40 MHz 50 MHz
66 MHz
Num
Characteristic
Unit
Min
Max
Min
Max
Min
Max
Min
Max
B7a CLKOUT to TSIZ(0:1), REG, RSV,
AT(0:3), BDIP, PTR invalid
7.58
7.58
—
6.25
6.25
—
5.00
5.00
—
3.80
—
ns
ns
B7b CLKOUT to BR, BG, FRZ,
VFLS(0:1), VF(0:2) IWP(0:2),
—
—
—
3.80
—
4
LWP(0:1), STS invalid
B8
CLKOUT to A(0:31), BADDR(28:30) 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns
RD/WR, BURST, D(0:31), DP(0:3)
valid
B8a CLKOUT to TSIZ(0:1), REG, RSV,
AT(0:3) BDIP, PTR valid
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns
B8b CLKOUT to BR, BG, VFLS(0:1),
VF(0:2), IWP(0:2), FRZ, LWP(0:1),
STS valid 4
B9
CLKOUT to A(0:31), BADDR(28:30), 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns
RD/WR, BURST, D(0:31), DP(0:3),
TSIZ(0:1), REG, RSV, AT(0:3), PTR
High-Z
B11 CLKOUT to TS, BB assertion
7.58 13.58 6.25 12.25 5.00 11.00 3.80 11.29 ns
B11a CLKOUT to TA, BI assertion (when
driven by the memory controller or
PCMCIA interface)
2.50
9.25
2.50
9.25
2.50
9.25
2.50
9.75
ns
B12 CLKOUT to TS, BB negation
7.58 14.33 6.25 13.00 5.00 11.75 3.80
2.50 11.00 2.50 11.00 2.50 11.00 2.50
8.54
9.00
ns
ns
B12a CLKOUT to TA, BI negation (when
driven by the memory controller or
PCMCIA interface)
B13 CLKOUT to TS, BB High-Z
7.58 21.58 6.25 20.25 5.00 19.00 3.80 14.04 ns
2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns
B13a CLKOUT to TA, BI High-Z (when
driven by the memory controller or
PCMCIA interface)
B14 CLKOUT to TEA assertion
B15 CLKOUT to TEA High-Z
2.50 10.00 2.50 10.00 2.50 10.00 2.50
9.00
ns
2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns
B16 TA, BI valid to CLKOUT (setup time) 9.75
—
—
9.75
—
—
9.75
—
—
6.00
4.50
—
—
ns
ns
B16a TEA, KR, RETRY, CR valid to
CLKOUT (setup time)
10.00
10.00
10.00
B16b BB, BG, BR, valid to CLKOUT (setup 8.50
—
—
—
8.50
1.00
2.00
—
—
—
8.50
1.00
2.00
—
—
—
4.00
2.00
2.00
—
—
—
ns
ns
ns
5
time)
B17 CLKOUT to TA, TEA, BI, BB, BG, BR 1.00
valid (hold time)
B17a CLKOUT to KR, RETRY, CR valid
(hold time)
2.00
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
13
Bus Signal Timing
Table 7. Bus Operation Timings (continued)
33 MHz 40 MHz 50 MHz
66 MHz
Num
Characteristic
Unit
Min
Max
Min
Max
Min
Max
Min
Max
B18 D(0:31), DP(0:3) valid to CLKOUT
6.00
1.00
4.00
2.00
—
6.00
1.00
4.00
2.00
—
6.00
1.00
4.00
2.00
—
6.00
2.00
4.00
2.00
—
ns
ns
ns
ns
6
rising edge (setup time)
B19 CLKOUT rising edge to D(0:31),
DP(0:3) valid (hold time) 6
—
—
—
—
—
—
—
—
—
—
—
—
B20 D(0:31), DP(0:3) valid to CLKOUT
7
falling edge (setup time)
B21 CLKOUT falling edge to D(0:31),
DP(0:3) valid (hold time) 7
B22 CLKOUT rising edge to CS asserted 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns
GPCM ACS = 00
B22a CLKOUT falling edge to CS asserted
GPCM ACS = 10, TRLX = 0
—
8.00
—
8.00
—
8.00
—
8.00
ns
B22b CLKOUT falling edge to CS asserted 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns
GPCM ACS = 11, TRLX = 0,
EBDF = 0
B22c CLKOUT falling edge to CS asserted 10.86 17.99 8.88 16.00 7.00 14.13 5.18 12.31 ns
GPCM ACS = 11, TRLX = 0,
EBDF = 1
B23 CLKOUT rising edge to CS negated 2.00
GPCM read access, GPCM write
access ACS = 00, TRLX = 0, and
CSNT = 0
8.00
—
2.00
4.25
8.00
—
2.00
3.00
8.00
—
2.00
1.79
8.00
—
ns
ns
B24 A(0:31) and BADDR(28:30) to CS
asserted GPCM ACS = 10,
TRLX = 0
5.58
B24a A(0:31) and BADDR(28:30) to CS
asserted GPCM ACS = 11, TRLX = 0
13.15
—
—
10.50
—
—
8.00
—
—
5.58
—
—
ns
ns
B25 CLKOUT rising edge to OE, WE(0:3)
asserted
9.00
9.00
9.00
9.00
B26 CLKOUT rising edge to OE negated 2.00
9.00
—
2.00
9.00
—
2.00
9.00
—
2.00
9.00
—
ns
ns
B27 A(0:31) and BADDR(28:30) to CS
asserted GPCM ACS = 10, TRLX = 1
35.88
43.45
—
29.25
23.00
16.94
B27a A(0:31) and BADDR(28:30) to CS
asserted GPCM ACS = 11, TRLX = 1
—
35.50
—
—
28.00
—
—
20.73
—
—
ns
ns
B28 CLKOUT rising edge to WE(0:3)
negated GPCM write access
CSNT = 0
9.00
9.00
9.00
9.00
B28a CLKOUT falling edge to WE(0:3)
negated GPCM write access
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns
TRLX = 0, 1, CSNT = 1, EBDF = 0
MPC860 Family Hardware Specifications, Rev. 7
14
Freescale Semiconductor
Bus Signal Timing
Table 7. Bus Operation Timings (continued)
33 MHz 40 MHz 50 MHz
66 MHz
Num
Characteristic
Unit
Min
Max
Min
Max
Min
Max
Min
Max
B28b CLKOUT falling edge to CS negated
GPCM write access TRLX = 0, 1,
CSNT = 1, ACS = 10, or ACS = 11,
EBDF = 0
—
14.33
—
13.00
—
11.75
—
10.54 ns
B28c CLKOUT falling edge to WE(0:3)
negated GPCM write access
10.86 17.99 8.88 16.00 7.00 14.13 5.18 12.31 ns
TRLX = 0, 1, CSNT = 1 write access
TRLX = 0, CSNT = 1, EBDF = 1
B28d CLKOUT falling edge to CS negated
GPCM write access TRLX = 0, 1,
CSNT = 1, ACS = 10, or ACS = 11,
EBDF = 1
—
17.99
—
16.00
—
14.13
—
12.31 ns
B29 WE(0:3) negated to D(0:31), DP(0:3) 5.58
High-Z GPCM write access
—
—
—
4.25
10.5
4.25
—
—
—
3.00
8.00
3.00
—
—
—
1.79
5.58
1.79
—
—
—
ns
ns
ns
CSNT = 0, EBDF = 0
B29a WE(0:3) negated to D(0:31), DP(0:3) 13.15
High-Z GPCM write access,
TRLX = 0, CSNT = 1, EBDF = 0
B29b CS negated to D(0:31), DP(0:3),
High-Z GPCM write access,
ACS = 00, TRLX = 0, 1, and CSNT =
0
5.58
B29c CS negated to D(0:31), DP(0:3)
High-Z GPCM write access,
13.15
—
10.5
—
8.00
—
5.58
—
ns
TRLX = 0, CSNT = 1, ACS = 10, or
ACS = 11, EBDF = 0
B29d WE(0:3) negated to D(0:31), DP(0:3) 43.45
High-Z GPCM write access,
—
—
35.5
35.5
—
—
28.00
28.00
—
—
20.73
29.73
—
—
ns
ns
TRLX = 1, CSNT = 1, EBDF = 0
B29e CS negated to D(0:31), DP(0:3)
High-Z GPCM write access,
43.45
TRLX = 1, CSNT = 1, ACS = 10, or
ACS = 11, EBDF = 0
B29f WE(0:3) negated to D(0:31), DP(0:3) 8.86
High-Z GPCM write access,
—
—
6.88
6.88
—
—
5.00
5.00
—
—
3.18
3.18
—
—
ns
ns
TRLX = 0, CSNT = 1, EBDF = 1
B29g CS negated to D(0:31), DP(0:3)
High-Z GPCM write access,
8.86
TRLX = 0, CSNT = 1, ACS = 10, or
ACS = 11, EBDF = 1
B29h WE(0:3) negated to D(0:31), DP(0:3) 38.67
High-Z GPCM write access,
—
31.38
—
24.50
—
17.83
—
ns
TRLX = 1, CSNT = 1, EBDF = 1
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
15
Table 7. Bus Operation Timings (continued)
33 MHz 40 MHz 50 MHz
66 MHz
Num
Characteristic
Unit
Min
38.67
Max
Min
31.38
Max
Min
24.50
Max
Min
17.83
Max
B29i CS negated to D(0:31), DP(0:3)
High-Z GPCM write access,
—
—
—
—
ns
How to Reach Us:
TRLX = 1, CSNT = 1, ACS = 10, or
ACS = 11, EBDF = 1
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MPC860EC
Rev. 7
09/2004
Bus Signal Timing
Table 7. Bus Operation Timings (continued)
33 MHz 40 MHz 50 MHz
66 MHz
Num
Characteristic
Unit
Min
Max
Min
Max
Min
Max
Min
Max
B30 CS, WE(0:3) negated to A(0:31),
BADDR(28:30) invalid GPCM write
5.58
—
4.25
—
3.00
—
1.79
—
ns
8
access
B30a WE(0:3) negated to A(0:31),
BADDR(28:30) invalid GPCM, write
access, TRLX = 0, CSNT = 1,
13.15
—
—
10.50
—
—
8.00
—
—
5.58
—
—
ns
ns
CS negated to A(0:31) invalid GPCM
write access, TRLX = 0, CSNT =1
ACS = 10, or ACS = 11, EBDF = 0
B30b WE(0:3) negated to A(0:31),
invalid GPCM BADDR(28:30) invalid
GPCM write access, TRLX = 1,
CSNT = 1. CS negated to A(0:31),
Invalid GPCM, write access,
43.45
35.50
28.00
20.73
TRLX = 1, CSNT = 1, ACS = 10, or
ACS = 11, EBDF = 0
B30c WE(0:3) negated to A(0:31),
BADDR(28:30) invalid GPCM write
access, TRLX = 0, CSNT = 1.
8.36
38.67
1.50
—
—
6.38
31.38
1.50
—
—
4.50
24.50
1.50
—
—
2.68
17.83
1.50
—
—
ns
ns
ns
CS negated to A(0:31) invalid GPCM
write access, TRLX = 0, CSNT = 1,
ACS = 10, ACS = 11, EBDF = 1
B30d WE(0:3) negated to A(0:31),
BADDR(28:30) invalid GPCM write
access, TRLX = 1, CSNT =1.
CS negated to A(0:31) invalid GPCM
write access TRLX = 1, CSNT = 1,
ACS = 10, or ACS = 11, EBDF = 1
B31 CLKOUT falling edge to CS
valid—as requested by control bit
CST4 in the corresponding word in
UPM
6.00
6.00
6.00
6.00
B31a CLKOUT falling edge to CS
valid—as requested by control bit
CST1 in the corresponding word in
UPM
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns
B31b CLKOUT rising edge to CS valid—as 1.50
requested by control bit CST2 in the
corresponding word in UPM
8.00
1.50
8.00
1.50
8.00
1.50
8.00
ns
B31c CLKOUT rising edge to CS valid—as 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns
requested by control bit CST3 in the
corresponding word in UPM
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
17
Bus Signal Timing
Table 7. Bus Operation Timings (continued)
33 MHz 40 MHz 50 MHz
Min Max Min Max Min Max
13.26 17.99 11.28 16.00 9.40 14.13 7.58 12.31 ns
66 MHz
Min Max
Num
Characteristic
Unit
B31d CLKOUT falling edge to CS
valid—as requested by control bit
CST1 in the corresponding word in
UPM, EBDF = 1
B32 CLKOUT falling edge to BS
valid—as requested by control bit
BST4 in the corresponding word in
UPM
1.50
6.00
1.50
6.00
1.50
6.00
1.50
6.00
ns
B32a CLKOUT falling edge to BS
valid—as requested by control bit
BST1 in the corresponding word in
UPM, EBDF = 0
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns
B32b CLKOUT rising edge to BS valid—as 1.50
requested by control bit BST2 in the
corresponding word in UPM
8.00
1.50
8.00
1.50
8.00
1.50
8.00
ns
B32c CLKOUT rising edge to BS valid—as 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns
requested by control bit BST3 in the
corresponding word in UPM
B32d CLKOUT falling edge to BS
valid—as requested by control bit
BST1 in the corresponding word in
UPM, EBDF = 1
13.26 17.99 11.28 16.00 9.40 14.13 7.58 12.31 ns
B33 CLKOUT falling edge to GPL
valid—as requested by control bit
GxT4 in the corresponding word in
UPM
1.50
6.00
1.50
6.00
1.50
6.00
1.50
6.00
ns
B33a CLKOUT rising edge to GPL
valid—as requested by control bit
GxT3 in the corresponding word in
UPM
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns
B34 A(0:31), BADDR(28:30), andD(0:31) 5.58
to CS valid—as requested by control
bit CST4 in the corresponding word
in UPM
—
—
—
4.25
10.50
16.75
—
—
—
3.00
8.00
—
—
—
1.79
5.58
9.36
—
—
—
ns
ns
ns
B34a A(0:31), BADDR(28:30), andD(0:31) 13.15
to CS valid—as requested by control
bit CST1 in the corresponding word
in UPM
B34b A(0:31), BADDR(28:30), andD(0:31) 20.73
to CS valid—as requested by control
bit CST2 in the corresponding word
in UPM
13.00
MPC860 Family Hardware Specifications, Rev. 7
18
Freescale Semiconductor
Bus Signal Timing
Table 7. Bus Operation Timings (continued)
33 MHz 40 MHz 50 MHz
66 MHz
Num
Characteristic
Unit
Min
5.58
Max
Min
Max
Min
Max
Min
Max
B35 A(0:31), BADDR(28:30) to CS
valid—as requested by control bit
BST4 in the corresponding word in
UPM
—
4.25
10.50
16.75
4.25
—
3.00
8.00
—
1.79
—
ns
B35a A(0:31), BADDR(28:30), andD(0:31) 13.15
to BS valid—as requested by control
bit BST1 in the corresponding word
in UPM
—
—
—
—
—
—
—
—
—
5.58
9.36
1.79
—
—
—
ns
ns
ns
B35b A(0:31), BADDR(28:30), andD(0:31) 20.73
to BS valid—as requested by control
bit BST2 in the corresponding word
in UPM
13.00
3.00
B36 A(0:31), BADDR(28:30), andD(0:31) 5.58
to GPL valid—as requested by
control bit GxT4 in the corresponding
word in UPM
B37 UPWAIT valid to CLKOUT falling
6.00
1.00
7.00
—
—
6.00
1.00
—
—
6.00
1.00
—
—
6.00
1.00
—
—
ns
ns
9
edge
B38 CLKOUT falling edge to UPWAIT
valid 9
10
B39 AS valid to CLKOUT rising edge
—
—
7.00
7.00
—
—
7.00
7.00
—
—
7.00
7.00
—
—
ns
ns
B40 A(0:31), TSIZ(0:1), RD/WR, BURST, 7.00
valid to CLKOUT rising edge
B41 TS valid to CLKOUT rising edge
(setup time)
7.00
2.00
—
—
—
7.00
2.00
—
—
—
7.00
2.00
—
—
—
7.00
2.00
—
—
—
ns
ns
ns
B42 CLKOUT rising edge to TS valid
(hold time)
B43 AS negation to memory controller
signals negation
TBD
TBD
TBD
TBD
1
2
Phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed value.
If the rate of change of the frequency of EXTAL is slow (that is, it does not jump between the minimum and maximum
values in one cycle) or the frequency of the jitter is fast (that is, it does not stay at an extreme value for a long time)
then the maximum allowed jitter on EXTAL can be up to 2%.
3
4
The timings specified in B4 and B5 are based on full strength clock.
The timing for BR output is relevant when the MPC860 is selected to work with external bus arbiter. The timing for
BG output is relevant when the MPC860 is selected to work with internal bus arbiter.
5
6
7
The timing required for BR input is relevant when the MPC860 is selected to work with internal bus arbiter. The timing
for BG input is relevant when the MPC860 is selected to work with external bus arbiter.
The D(0:31) and DP(0:3) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA input
signal is asserted.
The D(0:31) and DP(0:3) input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is valid only
for read accesses controlled by chip-selects under control of the UPM in the memory controller, for data beats where
DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
19
Bus Signal Timing
8
The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0.
9
The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings specified
in B37 and B38 are specified to enable the freeze of the UPM output signals as described in Figure 17.
10
The AS signal is considered asynchronous to the CLKOUT. The timing B39 is specified in order to allow the behavior
specified in Figure 20.
Figure 2 is the control timing diagram.
2.0 V
2.0 V
CLKOUT
0.8 V
0.8 V
A
B
2.0 V
2.0 V
0.8 V
Outputs
0.8 V
A
B
2.0 V
2.0 V
0.8 V
Outputs
Inputs
Inputs
0.8 V
D
C
2.0 V
0.8 V
2.0 V
0.8 V
D
C
2.0 V
0.8 V
2.0 V
0.8 V
A
B
C
D
Maximum output delay specification
Minimum output hold time
Minimum input setup time specification
Minimum input hold time specification
Figure 2. Control Timing
Figure 3 provides the timing for the external clock.
MPC860 Family Hardware Specifications, Rev. 7
20
Freescale Semiconductor
Bus Signal Timing
CLKOUT
B1
B3
B1
B2
B4
B5
Figure 3. External Clock Timing
Figure 4 provides the timing for the synchronous output signals.
CLKOUT
B8
B7
B9
B9
Output
Signals
B8a
B7a
Output
Signals
B8b
B7b
Output
Signals
Figure 4. Synchronous Output Signals Timing
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
21
Bus Signal Timing
Figure 5 provides the timing for the synchronous active pull-up and open-drain output signals.
CLKOUT
B13
B11
B12
B12a
B15
TS, BB
TA, BI
TEA
B13a
B11a
B14
Figure 5. Synchronous Active Pull-Up Resistor and Open-Drain Outputs Signals Timing
Figure 6 provides the timing for the synchronous input signals.
CLKOUT
B16
B17
TA, BI
B16a
B17a
TEA, KR,
RETRY, CR
B16b
B17
BB, BG, BR
Figure 6. Synchronous Input Signals Timing
Figure 7 provides normal case timing for input data. It also applies to normal read accesses under the control of the
UPM in the memory controller.
MPC860 Family Hardware Specifications, Rev. 7
22
Freescale Semiconductor
Bus Signal Timing
CLKOUT
B16
B18
B17
B19
TA
D[0:31],
DP[0:3]
Figure 7. Input Data Timing in Normal Case
Figure 8 provides the timing for the input data controlled by the UPM for data beats where DLT3 = 1 in the UPM
RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)
CLKOUT
TA
B20
B21
D[0:31],
DP[0:3]
Figure 8. Input Data Timing when Controlled by UPM in the Memory Controller
and DLT3 = 1
Figure 9 through Figure 12 provide the timing for the external bus read controlled by various GPCM factors.
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
23
Bus Signal Timing
CLKOUT
B11
B8
B12
TS
A[0:31]
CSx
B22
B23
B25
B26
B19
OE
B28
WE[0:3]
B18
D[0:31],
DP[0:3]
Figure 9. External Bus Read Timing (GPCM Controlled—ACS = 00)
MPC860 Family Hardware Specifications, Rev. 7
24
Freescale Semiconductor
Bus Signal Timing
CLKOUT
TS
B11
B8
B12
A[0:31]
CSx
B23
B22a
B24
B25
B26
B19
OE
B18
D[0:31],
DP[0:3]
Figure 10. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 10)
CLKOUT
TS
B11
B8
B12
B22b
B22c
A[0:31]
CSx
B23
B24a
B25
B26
B19
OE
B18
D[0:31],
DP[0:3]
Figure 11. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 11)
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
25
Bus Signal Timing
CLKOUT
B11
B12
TS
A[0:31]
CSx
B8
B23
B22a
B27
B26
B19
OE
B27a
B22bB22c
B18
D[0:31],
DP[0:3]
Figure 12. External Bus Read Timing (GPCM Controlled—TRLX = 0 or 1, ACS = 10, ACS = 11)
Figure 13 through Figure 15 provide the timing for the external bus write controlled by various GPCM factors.
MPC860 Family Hardware Specifications, Rev. 7
26
Freescale Semiconductor
Bus Signal Timing
CLKOUT
TS
B11
B8
B12
B30
A[0:31]
CSx
B22
B23
B25
B28
WE[0:3]
OE
B26
B29b
B29
B8
B9
D[0:31],
DP[0:3]
Figure 13. External Bus Write Timing (GPCM Controlled—TRLX = 0 or 1, CSNT = 0)
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
27
Bus Signal Timing
CLKOUT
B11
B8
B12
TS
A[0:31]
CSx
B30aB30c
B22
B28b B28d
B25
B23
B29c B29g
WE[0:3]
OE
B26
B29a B29f
B28aB28c
B8
B9
D[0:31],
DP[0:3]
Figure 14. External Bus Write Timing (GPCM Controlled—TRLX = 0 or 1, CSNT = 1)
MPC860 Family Hardware Specifications, Rev. 7
28
Freescale Semiconductor
Bus Signal Timing
CLKOUT
TS
B11
B12
B8
B30b B30d
A[0:31]
CSx
B22
B28b B28d
B23
B25
B29eB29i
B29dB29h
WE[0:3]
OE
B26
B29b
B8
B28a B28c
B9
D[0:31],
DP[0:3]
Figure 15. External Bus Write Timing (GPCM Controlled—TRLX = 0 or 1, CSNT = 1)
Figure 16 provides the timing for the external bus controlled by the UPM.
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
29
Bus Signal Timing
CLKOUT
B8
A[0:31]
B31a
B31d
B31c
B31
B31b
CSx
B34
B34a
B34b
B32aB32d
B32c
B32
B32b
BS_A[0:3],
BS_B[0:3]
B35 B36
B35b
B35a
B33a
B33
GPL_A[0:5],
GPL_B[0:5]
Figure 16. External Bus Timing (UPM Controlled Signals)
Figure 17 provides the timing for the asynchronous asserted UPWAIT signal controlled by the UPM.
MPC860 Family Hardware Specifications, Rev. 7
30
Freescale Semiconductor
Bus Signal Timing
CLKOUT
UPWAIT
CSx
B37
B38
BS_A[0:3],
BS_B[0:3]
GPL_A[0:5],
GPL_B[0:5]
Figure 17. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing
Figure 18 provides the timing for the asynchronous negated UPWAIT signal controlled by the UPM.
CLKOUT
B37
UPWAIT
B38
CSx
BS_A[0:3],
BS_B[0:3]
GPL_A[0:5],
GPL_B[0:5]
Figure 18. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing
Figure 19 provides the timing for the synchronous external master access controlled by the GPCM.
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
31
Bus Signal Timing
CLKOUT
B41
B40
B42
TS
A[0:31],
TSIZ[0:1],
R/W, BURST
B22
CSx
Figure 19. Synchronous External Master Access Timing (GPCM Handled ACS = 00)
Figure 20 provides the timing for the asynchronous external master memory access controlled by the GPCM.
CLKOUT
B39
AS
B40
A[0:31],
TSIZ[0:1],
R/W
B22
CSx
Figure 20. Asynchronous External Master Memory Access Timing
(GPCM Controlled—ACS = 00)
Figure 21 provides the timing for the asynchronous external master control signals negation.
AS
B43
CSx, WE[0:3],
OE, GPLx,
BS[0:3]
Figure 21. Asynchronous External Master—Control Signals Negation Timing
MPC860 Family Hardware Specifications, Rev. 7
32
Freescale Semiconductor
Bus Signal Timing
Table 8 provides interrupt timing for the MPC860.
Table 8. Interrupt Timing
All Frequencies
Num
Characteristic 1
Unit
Min
Max
I39
I40
I41
I42
I43
IRQx valid to CLKOUT rising edge (setup time)
IRQx hold time after CLKOUT
IRQx pulse width low
6.00
2.00
—
—
—
—
—
ns
ns
ns
ns
—
3.00
IRQx pulse width high
3.00
IRQx edge-to-edge time
4 × TCLOCKOUT
1
The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being defined as
level-sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference
to the CLKOUT.
The timings I41, I42, and I43 are specified to allow the correct function of the IRQ lines detection circuitry and have
no direct relation with the total system interrupt latency that the MPC860 is able to support.
Figure 22 provides the interrupt detection timing for the external level-sensitive lines.
CLKOUT
I39
I40
IRQx
Figure 22. Interrupt Detection Timing for External Level Sensitive Lines
Figure 23 provides the interrupt detection timing for the external edge-sensitive lines.
CLKOUT
I41
I42
IRQx
I43
I43
Figure 23. Interrupt Detection Timing for External Edge Sensitive Lines
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
33
Bus Signal Timing
Table 9 shows the PCMCIA timing for the MPC860.
Table 9. PCMCIA Timing
33 MHz 40 MHz
50 MHz
66 MHz
Num
Characteristic
Unit
Min
20.73
Max
Min
Max
Min
Max
Min
Max
P44 A(0:31), REG valid to PCMCIA
—
16.75
—
13.00
—
9.36
—
ns
1
Strobe asserted
P45 A(0:31), REG valid to ALE negation 1 28.30
—
23.00
—
18.00
—
13.15
—
ns
ns
ns
ns
ns
ns
P46 CLKOUT to REG valid
7.58 15.58 6.25 14.25 5.00 13.00 3.79 11.84
8.58 7.25 6.00 4.84
P47 CLKOUT to REG invalid
—
—
—
—
P48 CLKOUT to CE1, CE2 asserted
P49 CLKOUT to CE1, CE2 negated
7.58 15.58 6.25 14.25 5.00 13.00 3.79 11.84
7.58 15.58 6.25 14.25 5.00 13.00 3.79 11.84
P50 CLKOUT to PCOE, IORD, PCWE,
IOWR assert time
—
11.00
11.00
—
11.00
—
11.00
P51 CLKOUT to PCOE, IORD, PCWE,
IOWR negate time
2.00 11.00 2.00 11.00 2.00 11.00 2.00 11.00
7.58 15.58 6.25 14.25 5.00 13.00 3.79 10.04
ns
P52 CLKOUT to ALE assert time
P53 CLKOUT to ALE negate time
ns
ns
ns
—
15.58
—
14.25
—
—
13.00
—
—
11.84
—
P54 PCWE, IOWR negated to D(0:31)
invalid 1
5.58
4.25
8.00
2.00
3.00
1.79
P55 WAITA and WAITB valid to CLKOUT 8.00
rising edge 1
—
—
—
—
8.00
2.00
—
—
8.00
2.00
—
—
ns
ns
P56 CLKOUT rising edge to WAITA and
WAITB invalid 1
2.00
1
PSST = 1. Otherwise add PSST times cycle time.
PSHT = 0. Otherwise add PSHT times cycle time.
These synchronous timings define when the WAITx signals are detected in order to freeze (or relieve) the
PCMCIA current cycle. The WAITx assertion will be effective only if it is detected 2 cycles before the PSL
timer expiration. See Chapter 16, “PCMCIA Interface,” in the MPC860 PowerQUICC User’s Manual.
Figure 24 provides the PCMCIA access cycle timing for the external bus read.
MPC860 Family Hardware Specifications, Rev. 7
34
Freescale Semiconductor
Bus Signal Timing
CLKOUT
TS
P44
P45
A[0:31]
REG
P46
P48
P47
P49
P51
P52
CE1/CE2
PCOE, IORD
ALE
P50
P53
P52
B18
B19
D[0:31]
Figure 24. PCMCIA Access Cycle Timing External Bus Read
Figure 25 provides the PCMCIA access cycle timing for the external bus write.
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
35
Bus Signal Timing
CLKOUT
TS
A[0:31]
P44
P45
P46
P48
P47
P49
P51
P52
B9
REG
CE1/CE2
PCWE, IOWR
ALE
P50
P53
B8
P54
P52
D[0:31]
Figure 25. PCMCIA Access Cycle Timing External Bus Write
Figure 26 provides the PCMCIA WAIT signal detection timing.
CLKOUT
P55
P56
WAITx
Figure 26. PCMCIA WAIT Signal Detection Timing
Table 10 shows the PCMCIA port timing for the MPC860.
MPC860 Family Hardware Specifications, Rev. 7
36
Freescale Semiconductor
Bus Signal Timing
Table 10. PCMCIA Port Timing
33 MHz 40 MHz
50 MHz
66 MHz
Num
Characteristic
Unit
Min
Max
Min
Max
Min
Max
Min
Max
P57 CLKOUT to OPx valid
—
19.00
—
—
19.00
—
—
19.00
—
—
19.00
—
ns
ns
ns
ns
P58 HRESET negated to OPx drive 1
25.73
21.75
5.00
1.00
18.00
5.00
1.00
14.36
5.00
1.00
P59 IP_Xx valid to CLKOUT rising edge 5.00
—
—
—
—
P60 CLKOUT rising edge to IP_Xx
invalid
1.00
—
—
—
—
1
OP2 and OP3 only
Figure 27 provides the PCMCIA output port timing for the MPC860.
CLKOUT
P57
Output
Signals
HRESET
P58
OP2, OP3
Figure 27. PCMCIA Output Port Timing
Figure 28 provides the PCMCIA output port timing for the MPC860.
CLKOUT
P59
P60
Input
Signals
Figure 28. PCMCIA Input Port Timing
Table 11 shows the debug port timing for the MPC860.
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
37
Bus Signal Timing
Table 11. Debug Port Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
P61 DSCK cycle time
3 × TCLOCKOUT
—
—
—
—
ns
ns
ns
ns
ns
P62 DSCK clock pulse width
P63 DSCK rise and fall times
P64 DSDI input data setup time
P65 DSDI data hold time
1.25 × TCLOCKOUT
0.00
8.00
5.00
0.00
0.00
3.00
—
—
P66 DSCK low to DSDO data valid
P67 DSCK low to DSDO invalid
15.00
2.00
Figure 29 provides the input timing for the debug port clock.
DSCK
D61
D62
D61
D62
D63
Figure 29. Debug Port Clock Input Timing
Figure 30 provides the timing for the debug port.
D63
DSCK
D64
D65
DSDI
D66
D67
DSDO
Figure 30. Debug Port Timings
MPC860 Family Hardware Specifications, Rev. 7
38
Freescale Semiconductor
Bus Signal Timing
Table 12 shows the reset timing for the MPC860.
Table 12. Reset Timing
33 MHz
40 MHz
50 MHz
66 MHz
Num
Characteristic
Unit
Min
Max
Min
Max
Min
Max
Min
Max
R69 CLKOUT to HRESET high
impedance
—
—
20.00
—
—
20.00
—
—
20.00
—
20.00
ns
ns
ns
R70 CLKOUT to SRESET high
impedance
20.00
—
20.00
20.00
—
—
20.00
—
R71 RSTCONF pulse width
515.1
5
425.0
0
340.0
0
257.5
8
R72
—
—
—
—
—
—
—
—
—
—
—
—
—
R73 Configuration data to HRESET rising 504.5
425.0
0
350.0
0
277.2
7
ns
ns
ns
ns
ns
ns
ns
edge setup time
5
R74 Configuration data to RSTCONF
rising edge setup time
350.0
0
—
—
350.0
0
—
—
350.0
0
—
—
350.0
0
—
—
R75 Configuration data hold time after
RSTCONF negation
0.00
0.00
—
0.00
0.00
0.00
—
0.00
0.00
—
R76 Configuration data hold time after
HRESET negation
—
0.00
—
—
—
R77 HRESET and RSTCONFasserted to
data out drive
25.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00
R78 RSTCONF negated to data out high
impedance
—
—
—
—
—
R79 CLKOUT of last rising edge before
chip three-state HRESET to data out
high impedance
—
—
—
R80 DSDI, DSCK setup
90.91
0.00
—
—
—
75.00
0.00
—
—
—
60.00
0.00
—
—
—
45.45
0.00
—
—
—
ns
ns
ns
R81 DSDI, DSCK hold time
R82 SRESET negated to CLKOUT rising 242.4
edge for DSDI and DSCK sample
200.0
0
160.0
0
121.2
1
2
Figure 31 shows the reset timing for the data bus configuration.
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
39
Bus Signal Timing
HRESET
R71
R76
RSTCONF
D[0:31] (IN)
R73
R74
R75
Figure 31. Reset Timing—Configuration from Data Bus
Figure 32 provides the reset timing for the data bus weak drive during configuration.
CLKOUT
R69
HRESET
R79
RSTCONF
R77
R78
D[0:31] (OUT)
(Weak)
Figure 32. Reset Timing—Data Bus Weak Drive During Configuration
Figure 33 provides the reset timing for the debug port configuration.
MPC860 Family Hardware Specifications, Rev. 7
40
Freescale Semiconductor
IEEE 1149.1 Electrical Specifications
CLKOUT
SRESET
R70
R81
R82
R80
R80
R81
DSCK, DSDI
Figure 33. Reset Timing—Debug Port Configuration
10 IEEE 1149.1 Electrical Specifications
Table 13 provides the JTAG timings for the MPC860 shown in Figure 34 through Figure 37.
Table 13. JTAG Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
J82
J83
J84
J85
J86
J87
J88
J89
J90
J91
J92
J93
J94
J95
J96
TCK cycle time
100.00
40.00
0.00
5.00
25.00
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCK clock pulse width measured at 1.5 V
TCK rise and fall times
10.00
—
TMS, TDI data setup time
TMS, TDI data hold time
—
TCK low to TDO data valid
27.00
—
TCK low to TDO data invalid
0.00
—
TCK low to TDO high impedance
TRST assert time
20.00
—
100.00
40.00
—
TRST setup time to TCK low
—
TCK falling edge to output valid
TCK falling edge to output valid out of high impedance
TCK falling edge to output high impedance
Boundary scan input valid to TCK rising edge
TCK rising edge to boundary scan input invalid
50.00
50.00
50.00
—
—
—
50.00
50.00
—
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
41
IEEE 1149.1 Electrical Specifications
TCK
J82
J83
J82
J83
J84
J84
Figure 34. JTAG Test Clock Input Timing
TCK
TMS, TDI
TDO
J85
J86
J87
J88
J89
Figure 35. JTAG Test Access Port Timing Diagram
TCK
J91
J90
TRST
TCK
Figure 36. JTAG TRST Timing Diagram
J92
J93
J94
Output
Signals
Output
Signals
J95
J96
Output
Signals
Figure 37. Boundary Scan (JTAG) Timing Diagram
MPC860 Family Hardware Specifications, Rev. 7
42
Freescale Semiconductor
CPM Electrical Characteristics
11 CPM Electrical Characteristics
This section provides the AC and DC electrical specifications for the communications processor module (CPM) of
the MPC860.
11.1 PIP/PIO AC Electrical Specifications
Table 14 provides the PIP/PIO AC timings as shown in Figure 38 through Figure 42.
Table 14. PIP/PIO Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
21
22
23
24
25
26
27
28
29
30
31
Data-in setup time to STBI low
0
2.5 – t3
1.5
—
—
—
—
—
—
2
ns
CLK
CLK
ns
1
Data-in hold time to STBI high
STBI pulse width
STBO pulse width
1 CLK – 5 ns
Data-out setup time to STBO low
Data-out hold time from STBO high
STBI low to STBO low (Rx interlock)
STBI low to STBO high (Tx interlock)
Data-in setup time to clock high
Data-in hold time from clock high
Clock low to data-out valid (CPU writes data, control, or direction)
2
5
CLK
CLK
CLK
CLK
ns
—
2
—
—
—
25
15
7.5
—
ns
ns
1
t3 = Specification 23.
DATA-IN
21
22
23
STBI
27
24
STBO
Figure 38. PIP Rx (Interlock Mode) Timing Diagram
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
43
CPM Electrical Characteristics
DATA-OUT
25
26
24
STBO
(Output)
28
23
STBI
(Input)
Figure 39. PIP Tx (Interlock Mode) Timing Diagram
DATA-IN
21
22
23
24
STBI
(Input)
STBO
(Output)
Figure 40. PIP Rx (Pulse Mode) Timing Diagram
DATA-OUT
25
26
24
23
STBO
(Output)
STBI
(Input)
Figure 41. PIP TX (Pulse Mode) Timing Diagram
MPC860 Family Hardware Specifications, Rev. 7
44
Freescale Semiconductor
CPM Electrical Characteristics
CLKO
DATA-IN
29
30
31
DATA-OUT
Figure 42. Parallel I/O Data-In/Data-Out Timing Diagram
11.2 Port C Interrupt AC Electrical Specifications
Table 15 provides the timings for port C interrupts.
Table 15. Port C Interrupt Timing
1
≥ 33.34 MHz
Num
Characteristic
Unit
Min
Max
35
36
Port C interrupt pulse width low (edge-triggered mode)
Port C interrupt minimum time between active edges
55
55
—
—
ns
ns
1
External bus frequency of greater than or equal to 33.34 MHz.
Figure 43 shows the port C interrupt detection timing.
36
Port C
(Input)
35
Figure 43. Port C Interrupt Detection Timing
11.3 IDMA Controller AC Electrical Specifications
Table 16 provides the IDMA controller timings as shown in Figure 44 through Figure 47.
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
45
CPM Electrical Characteristics
Table 16. IDMA Controller Timing
Characteristic
All Frequencies
Num
Unit
Min
Max
40
41
42
43
44
45
46
DREQ setup time to clock high
DREQ hold time from clock high
7
3
—
—
12
12
20
15
—
ns
ns
ns
ns
ns
ns
ns
SDACK assertion delay from clock high
SDACK negation delay from clock low
SDACK negation delay from TA low
SDACK negation delay from clock high
—
—
—
—
7
TA assertion to falling edge of the clock setup time (applies to
external TA)
CLKO
(Output)
41
40
DREQ
(Input)
Figure 44. IDMA External Requests Timing Diagram
MPC860 Family Hardware Specifications, Rev. 7
46
Freescale Semiconductor
CPM Electrical Characteristics
CLKO
(Output)
TS
(Output)
R/W
(Output)
42
43
DATA
46
TA
(Input)
SDACK
Figure 45. SDACK Timing Diagram—Peripheral Write, Externally-Generated TA
CLKO
(Output)
TS
(Output)
R/W
(Output)
42
44
DATA
TA
(Output)
SDACK
Figure 46. SDACK Timing Diagram—Peripheral Write, Internally-Generated TA
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
47
CPM Electrical Characteristics
CLKO
(Output)
TS
(Output)
R/W
(Output)
42
45
DATA
TA
(Output)
SDACK
Figure 47. SDACK Timing Diagram—Peripheral Read, Internally-Generated TA
11.4 Baud Rate Generator AC Electrical Specifications
Table 17 provides the baud rate generator timings as shown in Figure 48.
Table 17. Baud Rate Generator Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
50
51
52
BRGO rise and fall time
BRGO duty cycle
BRGO cycle
—
40
40
10
60
—
ns
%
ns
50
50
BRGOX
51
51
52
Figure 48. Baud Rate Generator Timing Diagram
MPC860 Family Hardware Specifications, Rev. 7
48
Freescale Semiconductor
CPM Electrical Characteristics
11.5 Timer AC Electrical Specifications
Table 18 provides the general-purpose timer timings as shown in Figure 49.
Table 18. Timer Timing
All Frequencies
Unit
Num
Characteristic
Min
Max
61
62
63
64
65
TIN/TGATE rise and fall time
10
1
—
—
—
—
25
ns
TIN/TGATE low time
TIN/TGATE high time
TIN/TGATE cycle time
CLKO low to TOUT valid
CLK
CLK
CLK
ns
2
3
3
CLKO
60
61
63
62
TIN/TGATE
(Input)
61
64
65
TOUT
(Output)
Figure 49. CPM General-Purpose Timers Timing Diagram
11.6 Serial Interface AC Electrical Specifications
Table 19 provides the serial interface timings as shown in Figure 50 through Figure 54.
Table 19. SI Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
70
71
L1RCLK, L1TCLK frequency (DSC = 0) 1, 2
—
SYNCCLK/2.5 MHz
L1RCLK, L1TCLK width low (DSC = 0) 2
P + 10
P + 10
—
—
—
ns
ns
ns
ns
ns
3
71a L1RCLK, L1TCLK width high (DSC = 0)
72
73
74
L1TXD, L1ST(1–4), L1RQ, L1CLKO rise/fall time
15.00
—
L1RSYNC, L1TSYNC valid to L1CLK edge (SYNC setup time)
L1CLK edge to L1RSYNC, L1TSYNC, invalid (SYNC hold time)
20.00
35.00
—
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
49
CPM Electrical Characteristics
Table 19. SI Timing (continued)
All Frequencies
Num
Characteristic
Unit
Min
Max
75
76
77
78
L1RSYNC, L1TSYNC rise/fall time
—
15.00
—
ns
ns
L1RXD valid to L1CLK edge (L1RXD setup time)
L1CLK edge to L1RXD invalid (L1RXD hold time)
17.00
13.00
10.00
10.00
10.00
10.00
10.00
0.00
—
ns
4
L1CLK edge to L1ST(1–4) valid
45.00
45.00
45.00
55.00
55.00
42.00
ns
78A L1SYNC valid to L1ST(1–4) valid
ns
79
80
L1CLK edge to L1ST(1–4) invalid
L1CLK edge to L1TXD valid
ns
ns
80A L1TSYNC valid to L1TXD valid 4
ns
81
82
L1CLK edge to L1TXD high impedance
L1RCLK, L1TCLK frequency (DSC =1)
ns
—
16.00 or
MHz
SYNCCLK/2
83
L1RCLK, L1TCLK width low (DSC =1)
P + 10
P + 10
—
—
—
ns
ns
ns
83a L1RCLK, L1TCLK width high (DSC = 1)3
84
85
L1CLK edge to L1CLKO valid (DSC = 1)
30.00
—
L1RQ valid before falling edge of L1TSYNC4
1.00
L1TCL
K
86
87
88
L1GR setup time2
L1GR hold time
42.00
42.00
—
—
—
ns
ns
ns
L1CLK edge to L1SYNC valid (FSD = 00) CNT = 0000, BYT = 0,
DSC = 0)
0.00
1
2
3
4
The ratio SYNCCLK/L1RCLK must be greater than 2.5/1.
These specs are valid for IDL mode only.
Where P = 1/CLKOUT. Thus, for a 25-MHz CLKO1 rate, P = 40 ns.
These strobes and TxD on the first bit of the frame become valid after L1CLK edge or L1SYNC, whichever comes
later.
MPC860 Family Hardware Specifications, Rev. 7
50
Freescale Semiconductor
CPM Electrical Characteristics
L1RCLK
(FE=0, CE=0)
(Input)
71
70
71a
72
L1RCLK
(FE=1, CE=1)
(Input)
RFSD=1
75
74
L1RSYNC
(Input)
73
77
L1RXD
(Input)
BIT0
76
78
79
L1ST(4-1)
(Output)
Figure 50. SI Receive Timing Diagram with Normal Clocking (DSC = 0)
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
51
CPM Electrical Characteristics
L1RCLK
(FE=1, CE=1)
(Input)
72
83a
82
L1RCLK
(FE=0, CE=0)
(Input)
RFSD=1
75
L1RSYNC
(Input)
73
74
77
L1RXD
(Input)
BIT0
76
78
79
L1ST(4-1)
(Output)
84
L1CLKO
(Output)
Figure 51. SI Receive Timing with Double-Speed Clocking (DSC = 1)
MPC860 Family Hardware Specifications, Rev. 7
52
Freescale Semiconductor
CPM Electrical Characteristics
L1TCLK
(FE=0, CE=0)
(Input)
71
70
72
L1TCLK
(FE=1, CE=1)
(Input)
73
TFSD=0
75
74
L1TSYNC
(Input)
80a
BIT0
80
81
L1TXD
(Output)
79
78
L1ST(4-1)
(Output)
Figure 52. SI Transmit Timing Diagram (DSC = 0)
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
53
CPM Electrical Characteristics
L1RCLK
(FE=0, CE=0)
(Input)
72
83a
82
L1RCLK
(FE=1, CE=1)
(Input)
TFSD=0
75
L1RSYNC
(Input)
73
74
81
L1TXD
(Output)
BIT0
80
78a
79
L1ST(4-1)
(Output)
78
84
L1CLKO
(Output)
Figure 53. SI Transmit Timing with Double Speed Clocking (DSC = 1)
MPC860 Family Hardware Specifications, Rev. 7
54
Freescale Semiconductor
CPM Electrical Characteristics
Figure 54. IDL Timing
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
55
CPM Electrical Characteristics
11.7 SCC in NMSI Mode Electrical Specifications
Table 20 provides the NMSI external clock timing.
Table 20. NMSI External Clock Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
100 RCLK1 and TCLK1 width high 1
1/SYNCCLK
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
101 RCLK1 and TCLK1 width low
1/SYNCCLK + 5
102 RCLK1 and TCLK1 rise/fall time
—
15.00
50.00
50.00
—
103 TXD1 active delay (from TCLK1 falling edge)
104 RTS1 active/inactive delay (from TCLK1 falling edge)
105 CTS1 setup time to TCLK1 rising edge
106 RXD1 setup time to RCLK1 rising edge
107 RXD1 hold time from RCLK1 rising edge 2
108 CD1 setup Time to RCLK1 rising edge
0.00
0.00
5.00
5.00
5.00
5.00
—
—
—
1
2
The ratios SYNCCLK/RCLK1 and SYNCCLK/TCLK1 must be greater than or equal to 2.25/1.
Also applies to CD and CTS hold time when they are used as external sync signals.
Table 21 provides the NMSI internal clock timing.
Table 21. NMSI Internal Clock Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
100 RCLK1 and TCLK1 frequency 1
0.00
—
SYNCCLK/3
MHz
ns
102 RCLK1 and TCLK1 rise/fall time
—
30.00
30.00
—
103 TXD1 active delay (from TCLK1 falling edge)
104 RTS1 active/inactive delay (from TCLK1 falling edge)
105 CTS1 setup time to TCLK1 rising edge
106 RXD1 setup time to RCLK1 rising edge
107 RXD1 hold time from RCLK1 rising edge 2
108 CD1 setup time to RCLK1 rising edge
0.00
0.00
40.00
40.00
0.00
40.00
ns
ns
ns
—
ns
—
ns
—
ns
1
2
The ratios SYNCCLK/RCLK1 and SYNCCLK/TCLK1 must be greater than or equal to 3/1.
Also applies to CD and CTS hold time when they are used as external sync signals.
Figure 55 through Figure 57 show the NMSI timings.
MPC860 Family Hardware Specifications, Rev. 7
56
Freescale Semiconductor
CPM Electrical Characteristics
RCLK1
102
102
101
106
100
RxD1
(Input)
107
108
CD1
(Input)
107
CD1
(SYNC Input)
Figure 55. SCC NMSI Receive Timing Diagram
TCLK1
102
102
101
100
TxD1
(Output)
103
105
RTS1
(Output)
104
104
CTS1
(Input)
107
CTS1
(SYNC Input)
Figure 56. SCC NMSI Transmit Timing Diagram
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
57
CPM Electrical Characteristics
TCLK1
102
102
101
100
TxD1
(Output)
103
RTS1
(Output)
104
107
104
105
CTS1
(Echo Input)
Figure 57. HDLC Bus Timing Diagram
11.8 Ethernet Electrical Specifications
Table 22 provides the Ethernet timings as shown in Figure 58 through Figure 62.
Table 22. Ethernet Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
120 CLSN width high
121 RCLK1 rise/fall time
122 RCLK1 width low
123 RCLK1 clock period 1
124 RXD1 setup time
125 RXD1 hold time
40
—
—
15
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
40
80
20
5
120
—
—
126 RENA active delay (from RCLK1 rising edge of the last data bit)
127 RENA width low
10
100
—
—
—
128 TCLK1 rise/fall time
15
—
129 TCLK1 width low
40
99
10
10
10
130 TCLK1 clock period1
101
50
50
50
131 TXD1 active delay (from TCLK1 rising edge)
132 TXD1 inactive delay (from TCLK1 rising edge)
133 TENA active delay (from TCLK1 rising edge)
MPC860 Family Hardware Specifications, Rev. 7
58
Freescale Semiconductor
CPM Electrical Characteristics
Table 22. Ethernet Timing (continued)
Characteristic
All Frequencies
Unit
Num
Min
Max
134 TENA inactive delay (from TCLK1 rising edge)
135 RSTRT active delay (from TCLK1 falling edge)
136 RSTRT inactive delay (from TCLK1 falling edge)
137 REJECT width low
10
10
10
1
50
50
50
—
20
20
ns
ns
ns
CLK
ns
138 CLKO1 low to SDACK asserted 2
—
—
139 CLKO1 low to SDACK negated 2
ns
1
2
The ratios SYNCCLK/RCLK1 and SYNCCLK/TCLK1 must be greater than or equal to 2/1.
SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.
CLSN(CTS1)
(Input)
120
Figure 58. Ethernet Collision Timing Diagram
RCLK1
121
121
124
123
Last Bit
RxD1
(Input)
125
126
127
RENA(CD1)
(Input)
Figure 59. Ethernet Receive Timing Diagram
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
59
CPM Electrical Characteristics
TCLK1
128
128
129
131
121
TxD1
(Output)
132
133
134
TENA(RTS1)
(Input)
RENA(CD1)
(Input)
(NOTE 2)
NOTES:
1. Transmit clock invert (TCI) bit in GSMR is set.
2. If RENA is deasserted before TENA, or RENA is not asserted at all during transmit, then the
CSL bit is set in the buffer descriptor at the end of the frame transmission.
Figure 60. Ethernet Transmit Timing Diagram
RCLK1
RxD1
(Input)
0
1
1
BIT1
125
BIT2
136
Start Frame De-
RSTRT
(Output)
Figure 61. CAM Interface Receive Start Timing Diagram
REJECT
137
Figure 62. CAM Interface REJECT Timing Diagram
MPC860 Family Hardware Specifications, Rev. 7
60
Freescale Semiconductor
CPM Electrical Characteristics
11.9 SMC Transparent AC Electrical Specifications
Table 23 provides the SMC transparent timings as shown in Figure 63.
Table 23. SMC Transparent Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
150 SMCLK clock period 1
151 SMCLK width low
151A SMCLK width high
152 SMCLK rise/fall time
100
50
50
—
10
20
5
—
—
—
15
50
—
—
ns
ns
ns
ns
ns
ns
ns
153 SMTXD active delay (from SMCLK falling edge)
154 SMRXD/SMSYNC setup time
155 RXD1/SMSYNC hold time
1
SYNCCLK must be at least twice as fast as SMCLK.
SMCLK
152
152
151
151
150
SMTXD
(Output)
NOTE
154
153
155
SMSYNC
154
155
SMRXD
(Input)
NOTE:
1. This delay is equal to an integer number of character-length clocks.
Figure 63. SMC Transparent Timing Diagram
11.10SPI Master AC Electrical Specifications
Table 24 provides the SPI master timings as shown in Figure 64 and Figure 65.
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
61
CPM Electrical Characteristics
Table 24. SPI Master Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
160 MASTER cycle time
4
2
1024
512
—
tcyc
tcyc
ns
ns
ns
ns
ns
ns
161 MASTER clock (SCK) high or low time
162 MASTER data setup time (inputs)
163 Master data hold time (inputs)
164 Master data valid (after SCK edge)
165 Master data hold time (outputs)
166 Rise time output
50
0
—
—
0
20
—
—
—
15
167 Fall time output
15
SPICLK
(CI=0)
(Output)
161
163
167
166
166
167
161
160
SPICLK
(CI=1)
(Output)
162
SPIMISO
(Input)
msb
Data
165
lsb
164
msb
167
msb
166
SPIMOSI
(Output)
Data
lsb
msb
Figure 64. SPI Master (CP = 0) Timing Diagram
MPC860 Family Hardware Specifications, Rev. 7
62
Freescale Semiconductor
CPM Electrical Characteristics
SPICLK
(CI=0)
(Output)
161
167
166
166
167
161
160
SPICLK
(CI=1)
(Output)
163
162
SPIMISO
(Input)
msb
Data
165
lsb
164
msb
msb
167
msb
166
SPIMOSI
(Output)
Data
lsb
Figure 65. SPI Master (CP = 1) Timing Diagram
11.11SPI Slave AC Electrical Specifications
Table 25 provides the SPI slave timings as shown in Figure 66 and Figure 67.
Table 25. SPI Slave Timing
All Frequencies
Unit
Num
Characteristic
Min
Max
170 Slave cycle time
2
—
—
—
—
—
—
—
50
tcyc
ns
171 Slave enable lead time
172 Slave enable lag time
15
15
1
ns
173 Slave clock (SPICLK) high or low time
174 Slave sequential transfer delay (does not require deselect)
175 Slave data setup time (inputs)
tcyc
tcyc
ns
1
20
20
—
176 Slave data hold time (inputs)
ns
177 Slave access time
ns
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
63
CPM Electrical Characteristics
SPISEL
(Input)
172
171
174
SPICLK
(CI=0)
(Input)
173
182
181
181
173
170
SPICLK
(CI=1)
(Input)
177
msb
176
182
180
Data
179
178
Undef
SPIMISO
(Output)
lsb
msb
175
181 182
lsb
SPIMOSI
(Input)
msb
Data
msb
Figure 66. SPI Slave (CP = 0) Timing Diagram
MPC860 Family Hardware Specifications, Rev. 7
64
Freescale Semiconductor
CPM Electrical Characteristics
SPISEL
(Input)
172
174
171
170
SPICLK
(CI=0)
(Input)
173
182
181
173
181
SPICLK
(CI=1)
(Input)
177
182
180
Data
179
178
SPIMISO
(Output)
msb
msb
msb
Undef
175
lsb
176
181 182
Data
Figure 67. SPI Slave (CP = 1) Timing Diagram
SPIMOSI
(Input)
msb
lsb
11.12I2C AC Electrical Specifications
2
Table 26 provides the I C (SCL < 100 kHz) timings.
Table 26. I2C Timing (SCL < 100 kHZ)
All Frequencies
Num
Characteristic
Unit
Min
Max
200 SCL clock frequency (slave)
0
100
100
—
—
—
—
—
—
—
1
kHz
kHz
µs
200 SCL clock frequency (master) 1
202 Bus free time between transmissions
203 Low period of SCL
1.5
4.7
4.7
4.0
4.7
4.0
0
µs
204 High period of SCL
µs
205 Start condition setup time
206 Start condition hold time
207 Data hold time
µs
µs
µs
208 Data setup time
250
—
ns
209 SDL/SCL rise time
µs
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
65
CPM Electrical Characteristics
Table 26. I2C Timing (SCL < 100 kHZ) (continued)
All Frequencies
Num
Characteristic
Unit
Min
Max
210 SDL/SCL fall time
—
300
—
ns
211
Stop condition setup time
4.7
µs
1
SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3 × pre_scaler × 2).
The ratio SYNCCLK/(BRGCLK / pre_scaler) must be greater than or equal to 4/1.
2
Table 27 provides the I C (SCL > 100 kHz) timings.
Table 27. . I2C Timing (SCL > 100 kHZ)
All Frequencies
Num
Characteristic
Expression
Unit
Min
Max
200 SCL clock frequency (slave)
200 SCL clock frequency (master) 1
202 Bus free time between transmissions
203 Low period of SCL
fSCL
fSCL
0
BRGCLK/48
Hz
Hz
s
BRGCLK/16512
1/(2.2 * fSCL)
1/(2.2 * fSCL)
1/(2.2 * fSCL)
1/(2.2 * fSCL)
1/(2.2 * fSCL)
0
BRGCLK/48
—
—
s
204 High period of SCL
—
s
205 Start condition setup time
206 Start condition hold time
207 Data hold time
—
s
—
s
—
—
s
208 Data setup time
1/(40 * fSCL)
—
s
209 SDL/SCL rise time
1/(10 * fSCL)
1/(33 * fSCL)
—
s
210 SDL/SCL fall time
—
s
211
Stop condition setup time
1/2(2.2 * fSCL)
s
1
SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3) × pre_scaler × 2).
The ratio SYNCCLK/(BRGCLK / pre_scaler) must be greater than or equal to 4/1.
2
Figure 68 shows the I C bus timing.
SDA
202
203
204
208
205
207
SCL
206
209
210
211
Figure 68. I2C Bus Timing Diagram
MPC860 Family Hardware Specifications, Rev. 7
66
Freescale Semiconductor
UTOPIA AC Electrical Specifications
12 UTOPIA AC Electrical Specifications
Table 28 shows the AC electrical specifications for the UTOPIA interface.
Table 28. UTOPIA AC Electrical Specifications
Num
Signal Characteristic
Direction
Min
Max
Unit
U1
UtpClk rise/fall time (Internal clock option)
Output
—
50
—
—
40
—
2
3.5
50
50
3.5
60
50
16
—
ns
%
Duty cycle
Frequency
MHz
ns
U1a UtpClk rise/fall time (external clock option)
Input
Duty cycle
Frequency
%
MHz
ns
U2
U3
U4
U5
RxEnb and TxEnb active delay
Output
Input
UTPB, SOC, Rxclav and Txclav setup time
UTPB, SOC, Rxclav and Txclav hold time
8
ns
Input
1
—
ns
UTPB, SOC active delay (and PHREQ and PHSEL active delay
in MPHY mode)
Output
2
16
ns
Figure 69 shows signal timings during UTOPIA receive operations.
U1
U1
UtpClk
U5
PHREQn
U3
U4
RxClav
RxEnb
HghZ at MPHY
U2
UTPB
SOC
U3
U4
Figure 69. UTOPIA Receive Timing
Figure 70 shows signal timings during UTOPIA transmit operations.
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
67
FEC Electrical Characteristics
U1
U1
UtpClk
U5
PHSELn
TxClav
U3
U4
Y
i
U2
TxEnb
UTPB
SOC
U5
Figure 70. UTOPIA Transmit Timing
13 FEC Electrical Characteristics
This section provides the AC electrical specifications for the Fast Ethernet controller (FEC). Note that the timing
specifications for the MII signals are independent of system clock frequency (part speed designation). Also, MII
signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.
13.1 MII Receive Signal Timing (MII_RXD[3:0], MII_RX_DV,
MII_RX_ER, MII_RX_CLK)
The receiver functions correctly up to a MII_RX_CLK maximum frequency of 25 MHz +1%. There is no minimum
frequency requirement. In addition, the processor clock frequency must exceed the MII_RX_CLK frequency – 1%.
Table 29 provides information on the MII receive signal timing.
Table 29. MII Receive Signal Timing
Num
Characteristic
Min
Max
Unit
M1
M2
M3
MII_RXD[3:0], MII_RX_DV, MII_RX_ER to MII_RX_CLK setup
MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold
MII_RX_CLK pulse width high
5
5
—
—
ns
ns
35%
65%
MII_RX_CL
K period
M4
MII_RX_CLK pulse width low
35%
65%
MII_RX_CL
K period
Figure 71 shows MII receive signal timing.
MPC860 Family Hardware Specifications, Rev. 7
68
Freescale Semiconductor
FEC Electrical Characteristics
M3
MII_RX_CLK (Input)
M4
MII_RXD[3:0] (Inputs)
MII_RX_DV
MII_RX_ER
M1
M2
Figure 71. MII Receive Signal Timing Diagram
13.2 MII Transmit Signal Timing (MII_TXD[3:0], MII_TX_EN,
MII_TX_ER, MII_TX_CLK)
The transmitter functions correctly up to a MII_TX_CLK maximum frequency of 25 MHz +1%. There is no
minimum frequency requirement. In addition, the processor clock frequency must exceed the MII_TX_CLK
frequency – 1%.
Table 30 provides information on the MII transmit signal timing.
Table 30. MII Transmit Signal Timing
Num
Characteristic
Min
Max
Unit
M5
M6
M7
MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid
MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid
MII_TX_CLK pulse width high
5
—
25
ns
—
35
65%
MII_TX_CLK
period
M8
MII_TX_CLK pulse width low
35%
65%
MII_TX_CLK
period
Figure 72 shows the MII transmit signal timing diagram.
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
69
FEC Electrical Characteristics
M7
MII_TX_CLK (Input)
M5
M8
MII_TXD[3:0] (Outputs)
MII_TX_EN
MII_TX_ER
M6
Figure 72. MII Transmit Signal Timing Diagram
13.3 MII Async Inputs Signal Timing (MII_CRS, MII_COL)
Table 31 provides information on the MII async inputs signal timing.
Table 31. MII Async Inputs Signal Timing
Num
Characteristic
Min
Max
Unit
M9
MII_CRS, MII_COL minimum pulse width
1.5
—
MII_TX_CLK
period
Figure 73 shows the MII asynchronous inputs signal timing diagram.
MII_CRS, MII_COL
M9
Figure 73. MII Async Inputs Timing Diagram
13.4 MII Serial Management Channel Timing (MII_MDIO, MII_MDC)
Table 32 provides information on the MII serial management channel signal timing. The FEC functions correctly
with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under investigation.
Table 32. MII Serial Management Channel Timing
Num
Characteristic
Min
Max
Unit
M10 MII_MDC falling edge to MII_MDIO output invalid (minimum
propagation delay)
0
—
ns
M11 MII_MDC falling edge to MII_MDIO output valid (max prop delay)
M12 MII_MDIO (input) to MII_MDC rising edge setup
—
25
—
ns
ns
10
MPC860 Family Hardware Specifications, Rev. 7
70
Freescale Semiconductor
Mechanical Data and Ordering Information
Table 32. MII Serial Management Channel Timing
Num
Characteristic
Min
Max
Unit
M13 MII_MDIO (input) to MII_MDC rising edge hold
M14 MII_MDC pulse width high
0
—
ns
40%
60%
MII_MDC
period
M15 MII_MDC pulse width low
40%
60%
MII_MDC
period
Figure 74 shows the MII serial management channel timing diagram.
M14
MM15
MII_MDC (Output)
M10
MII_MDIO (Output)
MII_MDIO (Input)
M11
M12
M13
Figure 74. MII Serial Management Channel Timing Diagram
14 Mechanical Data and Ordering Information
Table 33 provides information on the MPC860 Revision D.4 derivative devices.
Table 33. MPC860 Family Revision D.4 Derivatives
2
Number of Ethernet Support
Multichannel
HDLC Support
ATM
Support
Device
SCCs 1
(Mbps)
MPC855T
1
2
10/100
10
Yes
N/A
Yes
Yes
Yes
N/A
Yes
Yes
MPC860DE
MPC860DT
MPC860DP
10/100
10/100
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
71
Mechanical Data and Ordering Information
Table 33. MPC860 Family Revision D.4 Derivatives (continued)
2
Number of Ethernet Support
Multichannel
HDLC Support
ATM
Support
Device
SCCs 1
(Mbps)
MPC860EN
MPC860SR
MPC860T
MPC860P
4
10
N/A
Yes
Yes
Yes
N/A
Yes
Yes
Yes
10
10/100
10/100
1
2
Serial communications controller (SCC)
Up to 4 channels at 40 MHz or 2 channels at 25 MHz
Table 34 identifies the packages and operating frequencies available for the MPC860.
Table 34. MPC860 Family Package/Frequency Availability
Freq (MHz) /
Temp (Tj)
Package Type
Package
Order Number
1
Ball grid array
50
ZP/ZQ
MPC855TZQ50D4
MPC860DEZQ50D4
MPC860DTZQ50D4
MPC860ENZQ50D4
MPC860SRZQ50D4
MPC860TZQ50D4
MPC860DPZQ50D4
MPC860PZQ50D4
0° to 95°C
ZP suffix — Leaded
ZQ suffix — Leaded
VR suffix — Lead-Free are available as needed
Tape and Reel MPC855TZQ50D4R2
MPC860DEZQ50D4R2
MPC860ENZQ50D4R2
MPC860SRZQ50D4R2
MPC860TZQ50D4R2
MPC860DPZQ50D4R2
Sample
KMPC855TZQ50D4
KMPC860DEZQ50D4
KMPC860DTZQ50D4
KMPC860TZQ50D4
KMPC860SRZQ50D4
66
ZP/ZQ 1
MPC855TZQ66D4
MPC860DEZQ66D4
MPC860DTZQ66D4
MPC860ENZQ66D4
MPC860SRZQ66D4
MPC860TZQ66D4
MPC860DPZQ66D4
MPC860PZQ66D4
0° to 95°C
Tape and Reel MPC860SRZQ66D4R2
MPC860PZQ66D4R2
MPC860 Family Hardware Specifications, Rev. 7
72
Freescale Semiconductor
Mechanical Data and Ordering Information
Table 34. MPC860 Family Package/Frequency Availability (continued)
Freq (MHz) /
Temp (Tj)
Package Type
Package
Order Number
Sample
KMPC855TZQ66D4
KMPC860SRZQ66D4
KMPC860TZQ66D4
KMPC860ENZQ66D4
KMPC860PZQ66D4
80
ZP/ZQ 1
MPC855TZQ80D4
MPC860DEZQ80D4
MPC860DTZQ80D4
MPC860ENZQ80D4
MPC860SRZQ80D4
MPC860TZQ80D4
MPC860DPZQ80D4
MPC860PZQ80D4
0° to 95°C
Tape and Reel MPC860PZQ80D4R2
Sample
KMPC855TZQ80D4
KMPC860DEZQ80D4
KMPC860DTZQ80D4
KMPC860ENZQ80D4
KMPC860SRZQ80D4
KMPC860TZQ80D4
KMPC860DPZQ80D4
KMPC860PZQ80D4
Ball grid array (CZP suffix)
50
ZP/ZQ 1
MPC855TCZQ50D4
MPC860DECZQ50D4
MPC860DTCZQ50D4
MPC860ENCZQ50D4
MPC860SRCZQ50D4
MPC860TCZQ50D4
MPC860DPCZQ50D4
MPC860PCZQ50D4
–40° to 95°C
CZP suffix — Leaded
CZQ suffix — Leaded
CVR suffix — Lead-Free are available as needed
Tape and Reel MPC855TCZQ50D4R2
66
ZP/ZQ 1
MPC855TCZQ66D4
MPC860ENCZQ66D4
MPC860SRCZQ66D4
MPC860TCZQ66D4
MPC860DPCZQ66D4
MPC860PCZQ66D4
–40° to 95°C
1
The ZP package is no longer recommended for use. The ZQ package replaces the ZP package.
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
73
Mechanical Data and Ordering Information
14.1 Pin Assignments
Figure 75 shows the top view pinout of the PBGA package. For additional information, see the MPC860
PowerQUICC User’s Manual, or the MPC855T User’s Manual.
NOTE: This is the top view of the device.
W
V
U
T
PD10 PD8
PD14 PD13 PD9
PA0 PB14 PD15
PD3
IRQ7 D0
D4
D1
D2
D10
D11
D9
D3
D5
VDDL
D20
D6
D7
D29
DP1
DP2 CLKOUT IPA3
VSSSYN1
N/C
PD6 M_Tx_EN IRQ0 D13
D27
D23
D17
D14
D16
D15
D18
D19
D22
D24
D26
D31
D28
D30
DP3
DP0
PD4
PD5 IRQ1
D8
D21
IPA5 IPA4 IPA2
N/C VSSSYN
PA1
PC6
PC5 PC4 PD11
PA2 PB15 PD12
PD7 VDDH D12
VDDH
D25
IPA6 IPA0 IPA1 IPA7 XFC VDDSYN
R
VDDH
WAIT_B WAIT_A
VDDL RSTCONF
KAPWR
PORESET
SRESET
P
N
M
L
PA4 PB17 PA3 VDDL
PB19 PA5 PB18 PB16
GND
GND
XTAL
TEXP
HRESET
EXTCLK EXTAL
PA7
PC8
PA6
PC7
BADDR28
AS
MODCK2
OP0
BADDR29
VDDL
PB22 PC9
PA8 PB20
OP1 MODCK1
K
J
PC10 PA9 PB23 PB21
PC11 PB24 PA10 PB25
GND
BADDR30 IPB6 ALEA IRQ4
IPB5 IPB1 IPB2 ALEB
M_COL IRQ2 IPB0 IPB7
H
G
F
VDDL M_MDIO TDI
TCK
TRST TMS TDO PA11
PB26 PC12 PA12 VDDL
PB27 PC13 PA13 PB29
PB28 PC14 PA14 PC15
BR
VDDL
CS3
IRQ6 IPB4 IPB3
GND
GND
TS
BI
IRQ3 BURST
VDDH
VDDH
CS6
E
D
C
B
A
BG
BB
A8
A9
N/C
A12
A13
N/C
A16
A17
A15
A20
A21
A19
A24
A23
A25
A18 BSA0 GPLA0 N/C
CS2 GPLA5 BDIP TEA
PB30 PA15 PB31
A3
A6
A26 TSIZ1 BSA1 WE0 GPLA1 GPLA3 CS7
CS0
TA GPLA4
A0
19
A1
A4
A10
A22 TSIZ0 BSA3 M_CRS WE2 GPLA2 CS5 CE1A WR GPLB4
A2
18
A5
17
A7
16
A11
15
A14
14
A27
13
A29
12
A30
11
A28
10
A31 VDDL BSA2 WE1 WE3 CS4 CE2A CS1
9
8
7
6
5
4
3
2
1
Figure 75. Pinout of the PBGA Package
14.2 Mechanical Dimensions of the PBGA Package
Figure 76 shows the mechanical dimensions of the ZP PBGA package.
MPC860 Family Hardware Specifications, Rev. 7
74
Freescale Semiconductor
Mechanical Data and Ordering Information
C
0.2
4X
0.2 C
D
A
0.25 C
0.35 C
E2
E
D2
B
TOP VIEW
A2
A3
A1
A
D1
SIDE VIEW
18X e
W
V
U
T
R
P
N
M
L
K
J
E1
H
G
F
MILLIMETERS
E
D
C
B
A
DIM
A
MIN
---
0.50
0.95
0.70
0.60
MAX
2.05
0.70
1.35
0.90
0.90
A1
A2
A3
b
1
3
5
7
9
11 13 15 17 19
2
4 6 8 10 12 14 16 18
357X
b
BOTTOM VIEW
M
0.3
C A B
C
D
25.00 BSC
22.86 BSC
M
0.15
D1
D2
e
22.40
22.60
1.27 BSC
25.00 BSC
22.86 BSC
E
NOTE
E1
E2
1. Dimensions and tolerance per ASME Y14.5M, 1994
2. Dimensions in millimeters
22.40
22.60
3. Dimension b is the maximum solder ball diameter
Figure 76. Mechanical Dimensions and Bottom Surface Nomenclature
of the ZP PBGA Package
Figure 77 shows the mechanical dimensions of the ZQ PBGA package.
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
75
Mechanical Data and Ordering Information
NOTE
1. All Dimensions in millimeters
2. Dimensions and tolerance per ASME Y14.5M, 1994
3. Maximum Solder Ball Diameter measured parallel to Datum A
Figure 77. Mechanical Dimensions and Bottom Surface Nomenclature
of the ZQ PBGA Package
MPC860 Family Hardware Specifications, Rev. 7
76
Freescale Semiconductor
Document Revision History
15 Document Revision History
Table 35 lists significant changes between revisions of this hardware specification.
Table 35. Document Revision History
Revision
Date
Changes
5.1
11/2001
• Revised template format, removed references to MAC functionality, changed Table 7
B23 max value @ 66 MHz from 2ns to 8ns, added this revision history table
6
10/2002
11/2002
• Added the MPC855T. Corrected Figure 25 on page 36.
6.1
• Corrected UTOPIA RXenb* and TXenb* timing values
• Changed incorrect usage of Vcc to Vdd
• Corrected dual port RAM to 8 Kbytes
6.2
8/2003
• Changed B28a through B28d and B29d to show that TRLX can be 0 or 1
• Changed reference documentation to reflect the Rev 2 MPC860 PowerQUICC Family
Users Manual
• Nontechnical reformatting
6.3
7.0
9/2003
9/2004
• •Added Section 11.2 on the Port C interrupt pins
• •Nontechnical reformatting
• Added a tablefootnote to Table 6 DC Electrical Specifications about meeting the VIL
Max of the I2C Standard
• Replaced the thermal characteristics in Table 4 by the ZQ package
• Add the new parts to the Ordering and Availablity Chart in Table 34
• Added the mechanical spec of the ZQ package in Figure 77
• Removed all of the old revisions from Table 5
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
77
Document Revision History
THIS PAGE INTENTIONALLY LEFT BLANK
MPC860 Family Hardware Specifications, Rev. 7
78
Freescale Semiconductor
Document Revision History
THIS PAGE INTENTIONALLY LEFT BLANK
MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
79
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MPC860EC
Rev. 7
09/2004
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