MPC860DTCZQ66D4 [NXP]

MPC860DTCZQ66D4;


型号：	MPC860DTCZQ66D4
厂家：	NXP
描述：	MPC860DTCZQ66D4 PC
文件：	总2页 (文件大小：1577K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Integrated Communications Processors

MPC860

PowerQUICC^™Family

MPC860 FAMILY BLOCK DIAGRAM

Freescale Semiconductor’s PowerQUICC™

4 or 16 KB

MPC860 family is designed to deliver a

System Interface Unit

Memory Controller

I-Cache

versatile, on-chip integrated processor and

Instruction

Bus

I-MMU

peripheral combination that can be used in a

variety of controller applications—excelling

particularly in communications and networking

products. Providing functionality beyond the

MPC850 family, the MPC860 family and

MPC855T derivative are engineered to provide

higher performance in all areas of device

operation including flexibility, extensions in

capability and integration. The 860 architecture

integrates two processing blocks: the

Embedded

8xx

Core

Bus Interface Unit

System Functions

Real-Time Clock

PCMCIA Interface

Unified Bus

4 or 8 KB

D-Cache

Load/Store

Bus

D-MMU

Fast Ethernet

Controller

DMAs

FIFOs

Four

Interrupt

Dual-Port

RAM

Parallel I/O

Timers

Timer

Control

Baud Rate

Generators

Virtual IDMA

and

32-bit Controller

10/100 Base-T

Media Access

Control

and Program ROM

16 Serial DMA

Parallel

Port Pins

MII

embedded 8xx core compatible with the Power

Architecture™ technology instruction-set

architecture (ISA), and the communications

processor module (CPM). The CPM is designed

to support four serial communications

SCC1

SCC2

SCC3

SCC4

SMC1

SMC2

SPI

Serial Interface

Time Slot Assigner

controllers (SCCs), providing a total of eight

serial channels: four SCCs, two serial

Key Features

> Two SMCs, one SPI and one I²C

management controllers (SMCs), one serial

peripheral interface (SPI) and one I²C interface.

This dual-processor architecture is designed to

provide lower power consumption than

traditional architectures because the CPM

offloads peripheral tasks from the embedded

8xx core.

> Embedded 8xx core

> Additional support features, including

timers, baud rate generators, etc.

> 4 KB instruction cache and

4 KB data cache (16 KB instruction

cache and 8 KB data cache available)

in MPC860P and MPC860DP

> 8K dual-port RAM

> Available at 50, 66 and 80 MHz in a

357-pin PBGA package

> Powerful memory controller

and system functions

> Strong third-party tool support through

Freescale’s Design Alliance Program

> Efficient architecture that involves

a separate RISC processor for

handling communications

> Up to four serial communications

controllers

> Support for Ethernet, Fast Ethernet,

HDLC, asynchronous transfer mode

(ATM) and more

MPC

860

800 Series Device Number

(850, 860, etc.)

Temp. Range

None 0ºC Ta to +95ºC Tj

-40ºC Ta to +95ºC Tj

Frequency

Two Digits

Die Mask

Revision

Product Code

KXPC

XPC

MPC

Sample Pack (2-10)

Engineering Production

Fully Qualified

Part/Module Modifier

Package

VR = PB-free 357 PBGA

ZQ = 357 PBGA

Dual Channel

(Ethernet)

Dual Channel

(10/100, Multi-HDLC, ATM)

Dual Channel

(10/100, Multi-HDLC, ATM)

Four Channel

(Ethernet)

Four Channel

(Ethernet, Multi-HDLC, ATM)

Four Channel

(10/100, Multi-HDLC, ATM)

Four Channel

(10/100, Multi-HDLC, ATM)

855T 860DE 860DT 860DP 860EN 860SR

860T

860P

Serial Communications

Controllers (SCCs)

I-Cache (KB)

D-Cache (KB)

Ethernet (10T)

Ethernet (10/100)

ATM

Yes

Multichannel HDLC

Up to 32

Up to 64 Up to 64

Up to 64 Up to 64 Up to 64

Technical Specifications

> Embedded 8xx core designed to provide

106 MIPS (using Dhrystone 2.1) at 80 MHz

• 32-bit scaler RISC controller

• Two serial management controllers

• 16 serial DMA (SDMA) channels

• One I²C port

› UART

› IrDA

› Basic rate ISDN (BRI)

› Primary rate ISDN (PRI)

• Single-issue, 32-bit version of the

embedded 8xx core with 32- x 32-bit

fixed point registers

› Totally transparent mode with/

without CRC

• One serial peripheral interface

• Four general-purpose timers

• Time slot assigner

• 4 KB instruction cache and 4 KB data

cache (16 KB instruction cache and 8 KB

data cache available in 860P and 860DP)

> System integration unit

• Memory controller

• Real-time clock

• Memory management units with 32-entry

TLBs and fully associative instruction and

data TLBs

• Interrupts

• Four baud rate generators

• Protocols supported

• PCMCIA interface

• System functions

• Bus interface unit

> Advanced on-chip emulation debug mode

› Ethernet IEEE^®802.3 and Fast Ethernet

› ATM

> Data bus dynamic bus sizing for

8-, 16- and 32-bit buses

› HDLC

> Communications processor module

• 8 KB dual-port RAM

› Asynchronous HDLC

› Channelized HDLC

› Multichannel HDLC

› Appletalk

• Up to four serial communications

controllers (SCCs)

Learn More: For more information about Freescale Semiconductor products, please visit www.freescale.com.

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property

of their respective owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are

trademarks and service marks licensed by Power.org.

Document Number: MPC860FACT

REV 9

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