MPC870ZT66_技术文档

MPC875EC

Rev. 3.0, 07/2004

Freescale Semiconductor

MPC875/MPC870

Hardware Specifications

Contents

This hardware specification contains detailed information on

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

3. Maximum Tolerated Ratings . . . . . . . . . . . . . . . . . . . 7

4. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . 9

5. Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 10

7. Thermal Calculation and Measurement . . . . . . . . . . 11

8. Power Supply and Power Sequencing . . . . . . . . . . . 13

9. Mandatory Reset Configurations . . . . . . . . . . . . . . . 14

10. Layout Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

11. Bus Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 15

12. IEEE 1149.1 Electrical Specifications . . . . . . . . . . . 44

13. CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 46

14. USB Electrical Characteristics . . . . . . . . . . . . . . . . . 67

15. FEC Electrical Characteristics . . . . . . . . . . . . . . . . . 67

16. Mechanical Data and Ordering Information . . . . . . . 71

17. Document Revision History . . . . . . . . . . . . . . . . . . . 82

power considerations, DC/AC electrical characteristics, and AC

timing specifications for the MPC875/MPC870. The CPU on the

MPC875/MPC870 is a 32-bit PowerPC™ core that incorporates

memory management units (MMUs) and instruction and data

caches and that implements the PowerPC instruction set. This

hardware specification covers the following topics:

1 Overview

The MPC875/MPC870 is a versatile single-chip integrated

microprocessor and peripheral combination that can be used in a

variety of controller applications and communications and

networking systems. The MPC875/MPC870 provides enhanced

ATM functionality over that of other ATM-enabled members of

the MPC860 family.

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Features

Table 1 shows the functionality supported by the members of the MPC875/MPC870.

Table 1. MPC875/870 Devices

Cache

D Cache

Ethernet

Security

Engine

Part

SCC

SMC

USB

I Cache

10BaseT 10/100

MPC875

MPC870

8 Kbyte

1

2

1

Yes

No

—

2 Features

The MPC875/870 is comprised of three modules that each use the 32-bit internal bus: a MPC8xx core, a system

integration unit (SIU), and a communications processor module (CPM).

The following list summarizes the key MPC875/870 features:

•

Embedded MPC8xx core up to 133 MHz

Maximum frequency operation of the external bus is 80 MHz (in 1:1 mode)

— The 133-MHz core frequency supports 2:1 mode only.

— The 66-/80-MHz core frequencies support both the 1:1 and 2:1 modes.

•

Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with thirty-two 32-bit

general-purpose registers (GPRs)

— The core performs branch prediction with conditional prefetch and without conditional execution.

— 8-Kbyte data cache and 8-Kbyte instruction cache (see Table 1)

– Instruction cache is two-way, set-associative with 256 sets in 2 blocks

– Data cache is two-way, set-associative with 256 sets

– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache

blocks.

– Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and

are lockable on a cache block basis.

— MMUs with 32-entry TLB, fully associative instruction and data TLBs

— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address spaces

and 16 protection groups

— Advanced on-chip emulation debug mode

•

Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)

32 address lines

Memory controller (eight banks)

— Contains complete dynamic RAM (DRAM) controller

— Each bank can be a chip select or RAS to support a DRAM bank.

— Up to 30 wait states programmable per memory bank

— Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory devices

— DRAM controller programmable to support most size and speed memory interfaces

— Four CAS lines, four WE lines, and one OE line

MPC875/MPC870 Hardware Specifications, Rev. 3.0

2

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Freescale Semiconductor

Features

— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)

— Variable block sizes (32 Kbyte–256 Mbyte)

— Selectable write protection

— On-chip bus arbitration logic

•

General-purpose timers

— Four 16-bit timers or two 32-bit timers

— Gate mode can enable/disable counting.

— Interrupt can be masked on reference match and event capture

•

Two fast Ethernet controllers (FEC)—Two 10/100 Mbps Ethernet/IEEE 802.3 CDMA/CS that

interface through MII and/or RMII interfaces

System integration unit (SIU)

— Bus monitor

— Software watchdog

— Periodic interrupt timer (PIT)

— Clock synthesizer

— Decrementer and time base

— Reset controller

— IEEE 1149.1 test access port (JTAG)

•

Security engine is optimized to handle all the algorithms associated with IPsec, SSL/TLS, SRTP,

802.11i, and iSCSI processing. Available on the MPC875, the security engine contains a

crypto-channel, a controller, and a set of crypto hardware accelerators (CHAs). The CHAs are:

— Data encryption standard execution unit (DEU)

– DES, 3DES

– Two key (K1, K2, K1) or three key (K1, K2, K3)

– ECB and CBC modes for both DES and 3DES

— Advanced encryption standard unit (AESU)

– Implements the Rinjdael symmetric key cipher

– ECB, CBC, and counter modes

– 128-, 192-, and 256-bit key lengths

— Message digest execution unit (MDEU)

– SHA with 160- or 256-bit message digest

– MD5 with 128-bit message digest

– HMAC with either algorithm

— Master/slave logic, with DMA

– 32-bit address/32-bit data

– Operation at 8xx bus frequency

— Crypto-channel supporting multi-command descriptors

–

Integrated controller managing crypto-execution units

Buffer size of 256 bytes for each execution unit, with flow control for large data sizes

•

Interrupts

— Six external interrupt request (IRQ) lines

MPC875/MPC870 Hardware Specifications, Rev. 3.0

Freescale Semiconductor

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

3

Features

— 12 port pins with interrupt capability

— 23 internal interrupt sources

— Programmable priority between SCCs

— Programmable highest priority request

Communications processor module (CPM)

— RISC controller

•

— Communication-specific commands (for example, GRACEFUL STOP TRANSMIT, ENTER HUNT MODE, and

RESTART TRANSMIT)

— Supports continuous mode transmission and reception on all serial channels

— 8-Kbytes of dual-port RAM

— Several serial DMA (SDMA) channels to support the CPM

— Three parallel I/O registers with open-drain capability

^{On-chip 16}× 16 multiply accumulate controller (MAC)

— One operation per clock (two-clock latency, one-clock blockage)

— MAC operates concurrently with other instructions

— FIR loop—Four clocks per four multiplies

Four baud-rate generators

•

— Independent (can be connected to any SCC or SMC)

— Allows changes during operation

— Autobaud support option

SCC (serial communication controller)

— Ethernet/IEEE 802.3 optional on the SCC, supporting full 10-Mbps operation

— HDLC/SDLC

— HDLC bus (implements an HDLC-based local area network (LAN))

— Asynchronous HDLC to support point-to-point protocol (PPP)

— AppleTalk

— Universal asynchronous receiver transmitter (UART)

— Synchronous UART

— Serial infrared (IrDA)

— Binary synchronous communication (BISYNC)

— Totally transparent (bit streams)

— Totally transparent (frame based with optional cyclic redundancy check (CRC))

SMC (serial management channel)

•

— UART (low-speed operation)

— Transparent

Universal serial bus (USB)—Supports operation as a USB function endpoint, a USB host controller, or both

for testing purposes (loopback diagnostics)

— USB 2.0 full-/low-speed compatible

— The USB function mode has the following features:

– Four independent endpoints support control, bulk, interrupt, and isochronous data transfers.

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Freescale Semiconductor

Features

– CRC16 generation and checking

– CRC5 checking

– NRZI encoding/decoding with bit stuffing

– 12- or 1.5-Mbps data rate

– Flexible data buffers with multiple buffers per frame

– Automatic retransmission upon transmit error

— The USB host controller has the following features:

– Supports control, bulk, interrupt, and isochronous data transfers

– CRC16 generation and checking

– NRZI encoding/decoding with bit stuffing

– Supports both 12- and 1.5-Mbps data rates (automatic generation of preamble token and data

rate configuration). Note that low-speed operation requires an external hub.

– Flexible data buffers with multiple buffers per frame

– Supports local loopback mode for diagnostics (12 Mbps only)

Serial peripheral interface (SPI)

•

— Supports master and slave modes

— Supports multiple-master operation on the same bus

2

Inter-integrated circuit (I C) port

— Supports master and slave modes

— Supports a multiple-master environment

The MPC875 has a time-slot assigner (TSA) that supports one TDM bus (TDMb).

— Allows SCC and SMC to run in multiplexed and/or non-multiplexed operation

— Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user defined

— 1- or 8-bit resolution

— Allows independent transmit and receive routing, frame synchronization, and clocking

— Allows dynamic changes

— Can be internally connected to two serial channels (one SCC and one SMC)

PCMCIA interface

•

— Master (socket) interface, release 2.1-compliant

— Supports one independent PCMCIA socket on the MPC875/MPC870

— 8 memory or I/O windows supported

Debug interface

— Eight comparators: four operate on instruction address, two operate on data address, and two

operate on data

— Supports conditions: = ≠ < >

— Each watchpoint can generate a break point internally.

Normal high and normal low power modes to conserve power

1.8-V core and 3.3-V I/O operation with 5-V TTL compatibility

The MPC875/870 comes in a 256-pin ball grid array (PBGA) package.

•

MPC875/MPC870 Hardware Specifications, Rev. 3.0

Freescale Semiconductor

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

5

Features

The MPC875 block diagram is shown in Figure 1.

Instruction

Bus

8-Kbyte

Instruction Cache

System Interface Unit (SIU)

Unified

Bus

Memory Controller

Instruction MMU

32-Entry ITLB

Embedded

MPC8xx

Processor

Core

Internal

Bus Interface Bus Interface

Unit Unit

External

8-Kbyte

Data Cache

System Functions

Data MMU

32-Entry DTLB

Load/Store

Bus

PCMCIA-ATA Interface

Slave/Master IF

Security Engine

Fast Ethernet

Controller

Channel

AESU DEU MDEU

DMAs

FIFOs

4

Interrupt

8-Kbyte

Parallel I/O

Timers Controllers Dual-Port RAM

10/100

BaseT

Media Access

Control

4 Baud Rate

Generators

32-Bit RISC Controller

and Program

Virtual IDMA

and

Serial DMAs

ROM

Parallel Interface Port

Timers

MIII/RMII

I²C

SCC4

USB

SMC1

SPI

Time Slot Assigner

Serial Interface

Figure 1. MPC875 Block Diagram

MPC875/MPC870 Hardware Specifications, Rev. 3.0

6

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Freescale Semiconductor

Maximum Tolerated Ratings

The MPC870 block diagram is shown in Figure 2.

Instruction

Bus

8-Kbyte

Instruction Cache

System Interface Unit (SIU)

Unified

Bus

Memory Controller

Internal External

Bus Interface Bus Interface

Unit Unit

Instruction MMU

32-Entry ITLB

Embedded

MPC8xx

Processor

Core

8-Kbyte

Data Cache

System Functions

Data MMU

32-Entry DTLB

Load/Store

Bus

PCMCIA-ATA Interface

Slave/Master IF

Fast Ethernet

Controller

DMAs

FIFOs

4

Interrupt

8-Kbyte

Parallel I/O

Timers Controllers Dual-Port RAM

10/100

BaseT

Media Access

Control

4 Baud Rate

Generators

32-Bit RISC Controller

and Program

Virtual IDMA and

Serial DMAs

ROM

Parallel Interface Port

Timers

MIII / RMII

I²C

USB

SMC1

SPI

Serial Interface

Figure 2. MPC870 Block Diagram

3 Maximum Tolerated Ratings

This section provides the maximum tolerated voltage and temperature ranges for the MPC875/870. Table 2

displays the maximum tolerated ratings, and Table 3 displays the operating temperatures.

MPC875/MPC870 Hardware Specifications, Rev. 3.0

Freescale Semiconductor

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

7

Maximum Tolerated Ratings

Table 2. Maximum Tolerated Ratings

Rating

Symbol

Value

Unit

Supply voltage ¹

V_DDL(core

voltage)

–0.3 to 3.4

V

V_DDH(I/O

voltage)

–0.3 to 4

V

V_DDSYN

–0.3 to 3.4

<100

V

Difference

between

V_DDLand

V_DDSYN

mV

Input voltage ²

V_in

GND – 0.3 to

V_DDH

V

Storage temperature range

T_stg

–55 to +150

°C

¹The power supply of the device must start its ramp from 0.0 V.

²Functional operating conditions are provided with the DC electrical specifications in Table 6. Absolute maximum

ratings are stress ratings only; functional operation at the maxima is not guaranteed. Stress beyond those listed may

affect device reliability or cause permanent damage to the device.

Caution: All inputs that tolerate 5 V cannot be more than 2.5 V greater than VDDH. This restriction applies to power

up and normal operation (that is, if the MPC875/870 is unpowered, a voltage greater than 2.5 V must not be applied

to its inputs).

Table 3. Operating Temperatures

Rating

Symbol

Value

Unit

Temperature ¹(standard)

Temperature (extended)

T_A(min)

T_j(max)

T_A(min)

T_j(max)

0

°C

95

–40

100

¹Minimum temperatures are guaranteed as ambient temperature, T_A. Maximum temperatures are guaranteed as

junction temperature, T_j.

This device contains circuitry protecting against damage due to high-static voltage or electrical fields; however, it

is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages

to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic

voltage level (for example, either GND or V

).

DDH

MPC875/MPC870 Hardware Specifications, Rev. 3.0

8

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Freescale Semiconductor

Thermal Characteristics

4 Thermal Characteristics

Table 4 shows the thermal characteristics for the MPC875/870.

Table 4. MPC875/870 Thermal Resistance Data

Environment

Single-layer board (1s)

Rating

Symbol

Value

Unit

2

Junction-to-ambient ¹

Natural convection

R_θJA

43

29

36

26

20

10

2

°C/W

3

Four-layer board (2s2p)

Single-layer board (1s)

Four-layer board (2s2p)

R_θJMA

3

Airflow (200 ft/min)

R_θJMA

3

R_θJMA

Junction-to-board ⁴

R_θJB

R_θJC

Ψ_JT

5

Junction-to-case

Junction-to-package top ⁶

Natural convection

Airflow (200 ft/min)

Ψ_JT

2

¹Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal

resistance.

²Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.

³Per JEDEC JESD51-6 with the board horizontal.

⁴Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is

measured on the top surface of the board near the package.

⁵Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate

method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. For exposed

pad packages where the pad would be expected to be soldered, junction-to-case thermal resistance is a simulated

value from the junction to the exposed pad without contact resistance.

⁶Thermal characterization parameter indicating the temperature difference between the package top and the junction

temperature per JEDEC JESD51-2.

5 Power Dissipation

Table 5 provides information on power dissipation. The modes are 1:1, where CPU and bus speeds are

equal, and 2:1, where CPU frequency is twice bus speed.

Table 5. Power Dissipation (P_D)

Bus

Mode

Die Revision

Frequency

Typical ¹

Maximum ²

Unit

66 MHz

80 MHz

133 MHz

310

350

430

390

430

495

mW

1:1

2:1

0

¹Typical power dissipation is measured at V_DDL= V_DDSYN= 1.8 V, and V_DDHis at 3.3 V.

MPC875/MPC870 Hardware Specifications, Rev. 3.0

Freescale Semiconductor

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

9

DC Characteristics

²Maximum power dissipation at V_DDL= V_DDSYN= 1.9 V, and V_DDHis at 3.5 V.

NOTE

The values in Table 5 represent V

-based power dissipation and do not

DDL

include I/O power dissipation over V

. I/O power dissipation varies

DDH

widely by application due to buffer current, depending on external

circuitry.

The V

power dissipation is negligible.

DDSYN

6 DC Characteristics

Table 6 provides the DC electrical characteristics for the MPC875/870.

Table 6. DC Electrical Specifications

Characteristic

Symbol

Min

Max

Unit

Operating voltage

V_DDH(I/O)

3.135

1.7

3.465

1.9

V

V_DDL(Core)

1

V_DDSYN

1.7

1.9

V

Difference

between

V_DDLand

V_DDSYN

—

100

mV

Input high voltage (all inputs except EXTAL and EXTCLK) ²

Input low voltage ³

V_IH

V_IL

2.0

GND

3.465

0.8

V

EXTAL, EXTCLK input high voltage

V_IHC

I_in

0.7 × V_DDH

—

V_DDH

100

V

Input leakage current, Vin = 5.5 V (except TMS, TRST, DSCK and

DSDI pins) for 5-V tolerant pins ¹

µA

Input leakage current, Vin = V_DDH(except TMS, TRST, DSCK, and

DSDI)

I_In

—

10

µA

Input leakage current, Vin = 0 V (except TMS, TRST, DSCK and DSDI

pins)

I_In

Input capacitance ⁴

C_in

—

20

—

pF

V

Output high voltage, IOH = –2.0 mA, V_DDH= 3.0 V

except XTAL and open-drain pins

V_OH

2.4

Output low voltage

V_OL

—

0.5

V

IOL = 2.0 mA (CLKOUT)

IOL = 3.2 mA ⁵

IOL = 5.3 mA ⁶

IOL = 7.0 mA (TXD1/PA14, TXD2/PA12)

IOL = 8.9 mA (TS, TA, TEA, BI, BB, HRESET, SRESET)

¹The difference between V_DDLand V_DDSYNcannot be more than 100 mV.

²The signals PA[0:15], PB[14:31], PC[4:15], PD[3:15], PE(14:31), TDI, TDO, TCK, TRST, TMS, MII1_TXEN, MII_MDIO

are 5-V tolerant. The minimum voltage is still 2.0 V.

³V_IL(max) for the I²C interface is 0.8 V rather than the 1.5 V as specified in the I²C standard.

MPC875/MPC870 Hardware Specifications, Rev. 3.0

10

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Freescale Semiconductor

Thermal Calculation and Measurement

⁴Input capacitance is periodically sampled.

⁵A(0:31), TSIZ0/REG, TSIZ1, D(0:31), IRQ(2:4), IRQ6, RD/WR, BURST, IP_B(0:1), PA(0:4), PA(6:7), PA(10:11), PA15,

PB19, PB(23:31), PC(6:7), PC(10:13), PC15, PD8, PE(14:31), MII1_CRS, MII_MDIO, MII1_TXEN, MII1_COL.

⁶BDIP/GPL_B(5), BR, BG, FRZ/IRQ6, CS(0:7), WE(0:3), BS_A(0:3), GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1,

GPL_A(2:3)/GPL_B(2:3)/CS(2:3), UPWAITA/GPL_A4, UPWAITB/GPL_B4, GPL_A5, ALE_A, CE1_A, CE2_A,

OP(0:3) BADDR(28:30

7 Thermal Calculation and Measurement

For the following discussions, P = (V_DDL× I

) + P , where P is the power dissipation of the I/O

D

DDL

I/O I/O

drivers.

NOTE

power dissipation is negligible.

The V

DDSYN

7.1 Estimation with Junction-to-Ambient Thermal Resistance

An estimation of the chip junction temperature, T_J, in °C can be obtained from the following equation:

T = T + (R

× P )

D

J

A

θJA

where:

T = ambient temperature ºC

A

R

= package junction-to-ambient thermal resistance (ºC/W)

θJA

P = power dissipation in package

D

The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy

estimation of thermal performance. However, the answer is only an estimate; test cases have demonstrated

that errors of a factor of two (in the quantity T –T ) are possible.

J

A

7.2 Estimation with Junction-to-Case Thermal Resistance

Historically, thermal resistance has frequently been expressed as the sum of a junction-to-case thermal

resistance and a case-to-ambient thermal resistance:

R

= R

+ R

θJC θCA

θJA

where:

R

= junction-to-ambient thermal resistance (ºC/W)

= junction-to-case thermal resistance (ºC/W)

= case-to-ambient thermal resistance (ºC/W)

θJA

θJC

θCA

R

is device-related and cannot be influenced by the user. The user adjusts the thermal environment to

θJC

affect the case-to-ambient thermal resistance, R

. For instance, the user can change the airflow around

θCA

the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the

thermal dissipation on the printed circuit board surrounding the device. This thermal model is most useful

for ceramic packages with heat sinks where some 90% of the heat flows through the case and the heat sink

to the ambient environment. For most packages, a better model is required.

MPC875/MPC870 Hardware Specifications, Rev. 3.0

Freescale Semiconductor

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

11

Thermal Calculation and Measurement

7.3 Estimation with Junction-to-Board Thermal Resistance

A simple package thermal model that has demonstrated reasonable accuracy (about 20%) is a two-resistor model

consisting of a junction-to-board and a junction-to-case thermal resistance. The junction-to-case thermal resistance

covers the situation where a heat sink is used or where a substantial amount of heat is dissipated from the top of the

package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is

conducted to the printed circuit board. It has been observed that the thermal performance of most plastic packages

and especially PBGA packages is strongly dependent on the board temperature. If the board temperature is known,

an estimate of the junction temperature in the environment can be made using the following equation:

T = T + (R

× P )

D

J

B

θJB

where:

R

= junction-to-board thermal resistance (ºC/W)

θJB

T = board temperature ºC

B

P = power dissipation in package

D

If the board temperature is known and the heat loss from the package case to the air can be ignored, acceptable

predictions of junction temperature can be made. For this method to work, the board and board mounting must be

similar to the test board used to determine the junction-to-board thermal resistance, namely a 2s2p (board with a

power and a ground plane) and vias attaching the thermal balls to the ground plane.

7.4 Estimation Using Simulation

When the board temperature is not known, a thermal simulation of the application is needed. The simple two-resistor

model can be used with the thermal simulation of the application [2], or a more accurate and complex model of the

package can be used in the thermal simulation.

7.5 Experimental Determination

To determine the junction temperature of the device in the application after prototypes are available, the thermal

characterization parameter (Ψ ) can be used to determine the junction temperature with a measurement of the

JT

temperature at the top center of the package case using the following equation:

T = T + (Ψ × P )

J

T

JT

D

where:

Ψ

= thermal characterization parameter

JT

T = thermocouple temperature on top of package

T

P = power dissipation in package

D

The thermal characterization parameter is measured per the JESD51-2 specification published by JEDEC using a 40

gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned

so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple

junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the

package case to avoid measurement errors caused by the cooling effects of the thermocouple wire.

MPC875/MPC870 Hardware Specifications, Rev. 3.0

12

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Freescale Semiconductor

Power Supply and Power Sequencing

7.6 References

Semiconductor Equipment and Materials International

805 East Middlefield Rd

(415) 964-5111

Mountain View, CA 94043

MIL-SPEC and EIA/JESD (JEDEC) specifications

(Available from Global Engineering Documents)

800-854-7179 or

303-397-7956

JEDEC Specifications

http://www.jedec.org

1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive

Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.

2. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its

Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.

8 Power Supply and Power Sequencing

This section provides design considerations for the MPC875/870 power supply. The MPC875/870 has a

core voltage (V

) and PLL voltage (V

), which both operate at a lower voltage than the I/O voltage

DDL

DDSYN

V

. The I/O section of the MPC875/870 is supplied with 3.3 V across V

and V (GND).

DDH

DDH SS

The signals PA[0:3], PA[8:11], PB15, PB[24:25]; PB[28:31], PC[4:7], PC[12:13], PC15] PD[3:15], TDI,

TDO, TCK, TRST, TMS, MII_TXEN, and MII_MDIO are 5-V tolerant. No input can be more than 2.5 V

greater than V

. In addition, 5 V-tolerant pins cannot exceed 5.5 V, and remaining input pins cannot

DDH

exceed 3.465 V. This restriction applies to power up/down and normal operation.

One consequence of multiple power supplies is that when power is initially applied, the voltage rails ramp

up at different rates. The rates depend on the nature of the power supply, the type of load on each power

supply, and the manner in which different voltages are derived. The following restrictions apply:

•

V

must not exceed V

during power up and power down.

DDL

DDH

must not exceed 1.9 V, and V

must not exceed 3.465 V.

DDH

These cautions are necessary for the long-term reliability of the part. If they are violated, the electrostatic

discharge (ESD) protection diodes are forward-biased, and excessive current can flow through these diodes.

If the system power supply design does not control the voltage sequencing, the circuit shown in Figure 3

can be added to meet these requirements. The MUR420 Schottky diodes control the maximum potential

difference between the external bus and core power supplies on power up, and the 1N5820 diodes regulate

the maximum potential difference on power down.

MPC875/MPC870 Hardware Specifications, Rev. 3.0

Freescale Semiconductor

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

13

Mandatory Reset Configurations

V_DDH

V_DDL

MUR420

1N5820

Figure 3. Example Voltage Sequencing Circuit

9 Mandatory Reset Configurations

The MPC875/870 requires a mandatory configuration during reset.

If hardware reset configuration word (HRCW) is enabled, the HRCW[DBGC] value needs to be set to binary X1 in

the HRCW and the SIUMCR[DBGC] should be programmed with the same value in the boot code after reset. This

can be done by asserting the RSTCONF during HRESET assertion.

If HRCW is disabled, the SIUMCR[DBGC] should be programmed with binary X1 in the boot code after reset by

negating the RSTCONF during the HRESET assertion.

The MBMR[GPLB4DIS], PAPAR, PADIR, PBPAR, PBDIR, PCPAR, and PCDIR need to be configured with the

mandatory values in Table 7 in the boot code after the reset is negated.

Table 7. Mandatory Reset Configuration of MPC875/870

Value

(binary)

Register/Configuration

Field

HRCW

HRCW[DBGC]

X1

(Hardware reset configuration word)

SIUMCR

(SIU module configuration register)

SIUMCR[DBGC]

X1

0

MBMR

MBMR[GPLB4DIS}

(Machine B mode register)

PAPAR

PAPAR[5:9]

0

(Port A pin assignment register)

PAPAR[12:13]

PADIR

PADIR[5:9]

0

(Port A data direction register)

PADIR[12:13]

PBPAR

PBPAR[14:18]

PBPAR[20:22]

0

(Port B pin assignment register)

PBDIR

PBDIR[14:8]

0

(Port B data direction register)

PBDIR[20:22]

PCPAR

PCPAR[4:5]

PCPAR[8:9]

PCPAR[14]

0

(Port C pin assignment register)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

14

Freescale Semiconductor

Layout Practices

Table 7. Mandatory Reset Configuration of MPC875/870 (continued)

Register/Configuration Field

PCDIR[4:5]

Value

(binary)

PCDIR

0

(Port C data direction register)

PCDIR[8:9]

PCDIR[14]

PDPAR

PDPAR[3:7]

PDPAR[9:5]

0

(Port D pin assignment register)

PDDIR

PDDIR[3:7]

(Port D data direction register)

PDDIR[9:15]

10 Layout Practices

Each V pin on the MPC875/870 should be provided with a low-impedance path to the board’s supply. Each GND

DD

pin should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct groups

of logic on chip. The V_DDpower supply should be bypassed to ground using at least four 0.1-µF bypass capacitors

located as close as possible to the four sides of the package. Each board designed should be characterized and

additional appropriate decoupling capacitors should be used if required. The capacitor leads and associated printed

circuit traces connecting to chip V and GND should be kept to less than half an inch per capacitor lead. At a

DD

minimum, a four-layer board employing two inner layers as V and GND planes should be used.

DD

All output pins on the MPC875/870 have fast rise and fall times. Printed circuit (PC) trace interconnection length

should be minimized in order to minimize undershoot and reflections caused by these fast output switching times.

This recommendation particularly applies to the address and data buses. Maximum PC trace lengths of six inches

are recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances due to

the PC traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher

capacitive loads because these loads create higher transient currents in the V and GND circuits. Pull up all unused

DD

inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the

PLL supply pins. For more information, please refer to Section 14.4.3, “Clock Synthesizer Power (V

,

DDSYN

V

, V

),” of the MPC885 PowerQUICC Family User’s Manual.

SSSYN

SSSYN1

11 Bus Signal Timing

The maximum bus speed supported by the MPC875/870 is 80 MHz. Higher-speed parts must be operated in

half-speed bus mode (for example, an MPC875/870 used at 133 MHz must be configured for a 66 MHz bus). Table 8

shows the frequency ranges for standard part frequencies in 1:1 bus mode, and Table 9 shows the frequency ranges

for standard part frequencies in 2:1 bus mode.

Table 8. Frequency Ranges for Standard Part Frequencies (1:1 Bus Mode)

Part Frequency

66 MHz

80 MHz

Min

Max

Min

Max

Core frequency

Bus frequency

40

66.67

40

80

MPC875/MPC870 Hardware Specifications, Rev. 3.0

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

15

Freescale Semiconductor

Bus Signal Timing

Table 9. Frequency Ranges for Standard Part Frequencies (2:1 Bus Mode)

Part Frequency 66 MHz 80 MHz 133 MHz

Min

Max

Min

Max

Min

Max

Core frequency

Bus frequency

40

20

66.67

33.33

40

20

80

40

20

133

66

Table 10 provides the bus operation timing for the MPC875/870 at 33, 40, 66, and 80 MHz.

The timing for the MPC875/870 bus shown assumes a 50-pF load for maximum delays and a 0-pF load for minimum

delays. CLKOUT assumes a 100-pF load maximum delay

Table 10. Bus Operation Timings

33 MHz

40 MHz

66 MHz

80 MHz

Num

Characteristic

Unit

Min Max Min Max Min Max Min Max

B1

Bus period (CLKOUT), see Table 8

—

ns

B1a EXTCLK to CLKOUT phase skew - If

CLKOUT is an integer multiple of

–2

+2

–2

+2

–2

+2

–2

+2

EXTCLK, then the rising edge of EXTCLK

is aligned with the rising edge of CLKOUT.

For a non-integer multiple of EXTCLK, this

synchronization is lost, and the rising

edges of EXTCLK and CLKOUT have a

continuously varying phase skew.

B1b CLKOUT frequency jitter peak-to-peak

B1c Frequency jitter on EXTCLK

—

1

0.50

4

—

1

0.50

4

—

1

0.50

4

—

1

0.50

4

ns

%

B1d CLKOUT phase jitter peak-to-peak

ns

for OSCLK ≥ 15 MHz

CLKOUT phase jitter peak-to-peak

for OSCLK < 15 MHz

—

5

—

5

—

5

—

5

ns

B2

B3

CLKOUT pulse width low

(MIN = 0.4 × B1, MAX = 0.6 × B1)

12.1 18.2 10.0 15.0

6.1

9.1

5.0

7.5

CLKOUT pulse width high

(MIN = 0.4 × B1, MAX = 0.6 × B1)

B4

B5

B7

CLKOUT rise time

CLKOUT fall time

—

4.00

—

4.00

—

4.00

—

4.00

—

ns

CLKOUT to A(0:31), BADDR(28:30),

RD/WR, BURST, D(0:31) output hold

(MIN = 0.25 × B1)

7.60

6.30

3.80

3.13

B7a CLKOUT to TSIZ(0:1), REG, RSV, BDIP,

7.60

—

6.30

—

3.80

—

3.13

—

ns

PTR output hold (MIN = 0.25 × B1)

B7b CLKOUT to BR, BG, FRZ, VFLS(0:1),

VF(0:2) IWP(0:2), LWP(0:1), STS output

hold (MIN = 0.25 × B1)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

16

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Freescale Semiconductor

Bus Signal Timing

Table 10. Bus Operation Timings (continued)

33 MHz 40 MHz 66 MHz

Min Max Min Max Min Max Min Max

80 MHz

Num

Characteristic

Unit

B8

CLKOUT to A(0:31), BADDR(28:30)

RD/WR, BURST, D(0:31) valid

(MAX = 0.25 × B1 + 6.3)

—

13.80

—

12.50

—

10.00

—

9.43

ns

B8a CLKOUT to TSIZ(0:1), REG, RSV, BDIP,

—

13.80

—

12.50

—

10.00

—

9.43

ns

PTR valid (MAX = 0.25 × B1 + 6.3)

B8b CLKOUT to BR, BG, VFLS(0:1), VF(0:2),

IWP(0:2), FRZ, LWP(0:1), STS valid ²

(MAX = 0.25 × B1 + 6.3)

B9

CLKOUT to A(0:31), BADDR(28:30),

RD/WR, BURST, D(0:31), TSIZ(0:1), REG,

RSV, PTR High-Z

7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.43

ns

(MAX = 0.25 × B1 + 6.3)

B11 CLKOUT to TS, BB assertion

7.60 13.60 6.30 12.30 3.80 9.80 3.13 9.13

ns

(MAX = 0.25 × B1 + 6.0)

B11a CLKOUT to TA, BI assertion (when driven 2.50 9.30 2.50 9.30 2.50 9.80

by the memory controller or PCMCIA

2.5

9.3

interface) (MAX = 0.00 × B1 + 9.30 ¹)

B12 CLKOUT to TS, BB negation

7.60 12.30 6.30 11.00 3.80 8.50 3.13 7.92

ns

(MAX = 0.25 × B1 + 4.8)

B12a CLKOUT to TA, BI negation (when driven 2.50 9.00 2.50 9.00 2.50 9.00

by the memory controller or PCMCIA

2.5

9.00

interface) (MAX = 0.00 × B1 + 9.00)

B13 CLKOUT to TS, BB High-Z

7.60 21.60 6.30 20.30 3.80 14.00 3.13 12.93 ns

(MIN = 0.25 × B1)

B13a CLKOUT to TA, BI High-Z (when driven by 2.50 15.00 2.50 15.00 2.50 15.00 2.5 15.00 ns

the memory controller or PCMCIA

interface) (MIN = 0.00 × B1 + 2.5)

B14 CLKOUT to TEA assertion

2.50 9.00 2.50 9.00 2.50 9.00 2.50 9.00

ns

(MAX = 0.00 × B1 + 9.00)

B15 CLKOUT to TEA High-Z

2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns

(MIN = 0.00 × B1 + 2.50)

B16 TA, BI valid to CLKOUT (setup time)

6.00

4.50

—

6.00

4.50

4.00

1.00

2.00

—

6.00

4.50

4.00

2.00

—

6

—

ns

(MIN = 0.00 × B1 + 6.00)

B16a TEA, KR, RETRY, CR valid to CLKOUT

4.50

4.00

2.00

(setup time) (MIN = 0.00 × B1 + 4.5)

B16b BB, BG, BR, valid to CLKOUT (setup time) 4.00

²(4MIN = 0.00 × B1 + 0.00)

B17 CLKOUT to TA, TEA, BI, BB, BG, BR valid 1.00

(hold time) (MIN = 0.00 × B1 + 1.00 ³)

B17a CLKOUT to KR, RETRY, CR valid (hold

2.00

time) (MIN = 0.00 × B1 + 2.00)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

17

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Freescale Semiconductor

Bus Signal Timing

Table 10. Bus Operation Timings (continued)

33 MHz 40 MHz 66 MHz

Min Max Min Max Min Max Min Max

80 MHz

Num

Characteristic

Unit

B18 D(0:31) valid to CLKOUT rising edge

6.00

—

6.00

1.00

4.00

2.00

—

6.00

2.00

4.00

2.00

—

6.00

2.00

4.00

2.00

—

ns

(setup time) ⁴(MIN = 0.00 × B1 + 6.00)

B19 CLKOUT rising edge to D(0:31) valid (hold 1.00

time) ⁴(MIN = 0.00 × B1 + 1.00 ⁵)

B20 D(0:31) valid to CLKOUT falling edge

4.00

2.00

(setup time) ⁶(MIN = 0.00 × B1 + 4.00)

B21 CLKOUT falling edge to D(0:31) valid

(hold time) ⁶(MIN = 0.00 × B1 + 2.00)

B22 CLKOUT rising edge to CS asserted

7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.43

GPCM ACS = 00 (MAX = 0.25 × B1 + 6.3)

B22a CLKOUT falling edge to CS asserted

GPCM ACS = 10, TRLX = 0

—

8.00

—

8.00

—

8.00

—

8.00

(MAX = 0.00 × B1 + 8.00)

B22b CLKOUT falling edge to CS asserted

GPCM ACS = 11, TRLX = 0, EBDF = 0

(MAX = 0.25 × B1 + 6.3)

7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.43

ns

B22c CLKOUT falling edge to CS asserted

GPCM ACS = 11, TRLX = 0, EBDF = 1

(MAX = 0.375 × B1 + 6.6)

10.90 18.00 10.90 16.00 5.20 12.30 4.69 10.93 ns

B23 CLKOUT rising edge to CS negated

GPCM read access, GPCM write access

ACS = 00, TRLX = 0 & CSNT = 0

(MAX = 0.00 × B1 + 8.00)

2.00 8.00 2.00 8.00 2.00 8.00 2.00 8.00

ns

B24 A(0:31) and BADDR(28:30) to CS

asserted GPCM ACS = 10, TRLX = 0

(MIN = 0.25 × B1 – 2.00)

5.60

13.20

—

4.30

—

1.80

5.60

—

1.13

4.25

—

ns

B24a A(0:31) and BADDR(28:30) to CS

asserted GPCM ACS = 11 TRLX = 0

(MIN = 0.50 × B1 – 2.00)

10.50

B25 CLKOUT rising edge to OE,

WE(0:3)/BS_B[0:3] asserted

(MAX = 0.00 × B1 + 9.00)

9.00

B26 CLKOUT rising edge to OE negated

2.00 9.00 2.00 9.00 2.00 9.00 2.00 9.00

ns

(MAX = 0.00 × B1 + 9.00)

B27 A(0:31) and BADDR(28:30) to CS

asserted GPCM ACS = 10, TRLX = 1

(MIN = 1.25 × B1 – 2.00)

35.90

43.50

—

29.30

35.50

—

16.90

20.70

—

13.60

16.75

—

B27a A(0:31) and BADDR(28:30) to CS

asserted GPCM ACS = 11, TRLX = 1

(MIN = 1.50 × B1 – 2.00)

ns

MPC875/MPC870 Hardware Specifications, Rev. 3.0

18

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Freescale Semiconductor

Bus Signal Timing

Table 10. Bus Operation Timings (continued)

33 MHz 40 MHz 66 MHz

Min Max Min Max Min Max Min Max

9.00 9.00 9.00 9.00

80 MHz

Num

Characteristic

Unit

B28 CLKOUT rising edge to

—

ns

WE(0:3)/BS_B[0:3] negated GPCM write

access CSNT = 0

(MAX = 0.00 × B1 + 9.00)

B28a CLKOUT falling edge to

WE(0:3)/BS_B[0:3] negated GPCM write

access TRLX = 0, CSNT = 1, EBDF = 0

(MAX = 0.25 × B1 + 6.80)

7.60 14.30 6.30 13.00 3.80 10.50 3.13 9.93

ns

B28b CLKOUT falling edge to CS negated

GPCM write access TRLX = 0, CSNT = 1

ACS = 10 or ACS = 11, EBDF = 0

(MAX = 0.25 × B1 + 6.80)

—

14.30

—

13.00

—

10.50

—

9.93

11.29

B28c CLKOUT falling edge to

WE(0:3)/BS_B[0:3] negated GPCM write

access TRLX = 0, CSNT = 1 write access

TRLX = 0, CSNT = 1, EBDF = 1

(MAX = 0.375 × B1 + 6.6)

10.90 18.00 10.90 18.00 5.20 12.30 4.69

B28d CLKOUT falling edge to CS negated

GPCM write access TRLX = 0, CSNT = 1,

ACS = 10, or ACS = 11, EBDF = 1

(MAX = 0.375 × B1 + 6.6)

—

18.00

—

18.00

—

12.30

—

11.30 ns

B29 WE(0:3)/BS_B[0:3] negated to D(0:31)

High-Z GPCM write access, CSNT = 0,

EBDF = 0 (MIN = 0.25 × B1 – 2.00)

5.60

—

4.30

—

1.80

5.60

—

1.13

4.25

—

ns

B29a WE(0:3)/BS_B[0:3] negated to D(0:31)

High-Z GPCM write access, TRLX = 0,

CSNT = 1, EBDF = 0

13.20

10.50

(MIN = 0.50 × B1 – 2.00)

B29b CS negated to D(0:31) High-Z GPCM write 5.60

access, ACS = 00, TRLX = 0 & CSNT = 0

(MIN = 0.25 × B1 – 2.00)

B29c CS negated to D(0:31) High-Z GPCM write 13.20

access, TRLX = 0, CSNT = 1, ACS = 10,

or ACS = 11 EBDF = 0

—

4.30

—

1.80

5.60

—

1.13

4.25

—

ns

10.50

(MIN = 0.50 × B1 – 2.00)

B29d WE(0:3)/BS_B[0:3] negated to D(0:31)

High-Z GPCM write access, TRLX = 1,

CSNT = 1, EBDF = 0

43.50

—

35.50

—

20.70

—

16.75

—

ns

(MIN = 1.50 × B1 – 2.00)

B29e CS negated to D(0:31) High-Z GPCM write 43.50

access, TRLX = 1, CSNT = 1, ACS = 10,

or ACS = 11, EBDF = 0

(MIN = 1.50 × B1 – 2.00)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

19

Freescale Semiconductor

Bus Signal Timing

Table 10. Bus Operation Timings (continued)

33 MHz 40 MHz 66 MHz

Min Max Min Max Min Max Min Max

80 MHz

Num

Characteristic

Unit

B29f WE(0:3/BS_B[0:3]) negated to D(0:31)

High-Z GPCM write access, TRLX = 0,

CSNT = 1, EBDF = 1

5.00

—

3.00

—

0.00

—

0.00

—

ns

(MIN = 0.375 × B1 – 6.30)

B29g CS negated to D(0:31) High-Z GPCM write 5.00

access, TRLX = 0, CSNT = 1 ACS = 10 or

ACS = 11, EBDF = 1

3.00

0.00

ns

(MIN = 0.375 × B1 – 6.30)

B29h WE(0:3)/BS_B[0:3] negated to D(0:31)

High-Z GPCM write access, TRLX = 1,

CSNT = 1, EBDF = 1

38.40

31.10

17.50

13.85

(MIN = 0.375 × B1 – 3.30)

B29i CS negated to D(0:31) (0:3) High-Z GPCM 38.40

write access, TRLX = 1, CSNT = 1,

ACS = 10 or ACS = 11, EBDF = 1

(MIN = 0.375 × B1 – 3.30)

B30 CS, WE(0:3)/BS_B[0:3] negated to

A(0:31), BADDR(28:30) invalid GPCM

write access ⁷(MIN = 0.25 × B1 – 2.00)

5.60

—

4.30

—

1.80

5.60

—

1.13

4.25

—

ns

B30a WE(0:3)/BS_B[0:3] negated to A(0:31),

BADDR(28:30) invalid GPCM, write

access, TRLX = 0, CSNT = 1, CS negated

to A(0:31) invalid GPCM write access

TRLX = 0, CSNT =1 ACS = 10, or

ACS == 11, EBDF = 0

13.20

10.50

(MIN = 0.50 × B1 – 2.00)

B30b WE(0:3)/BS_B[0:3] negated to A(0:31)

Invalid GPCM BADDR(28:30) invalid

GPCM write access, TRLX = 1, CSNT = 1.

CS negated to A(0:31) invalid GPCM write

access TRLX = 1, CSNT = 1, ACS = 10, or

ACS == 11 EBDF = 0

43.50

—

35.50

—

20.70

—

16.75

—

ns

(MIN = 1.50 × B1 – 2.00)

B30c WE(0:3)/BS_B[0:3] negated to A(0:31),

BADDR(28:30) invalid GPCM write

access, TRLX = 0, CSNT = 1. CS negated

to A(0:31) invalid GPCM write access,

TRLX = 0, CSNT = 1 ACS = 10,

ACS == 11, EBDF = 1

8.40

6.40

2.70

1.70

(MIN = 0.375 × B1 – 3.00)

B30d WE(0:3)/BS_B[0:3] negated to A(0:31),

BADDR(28:30) invalidGPCM writeaccess

TRLX = 1, CSNT =1, CS negated to

38.67

31.38

17.83

14.19

A(0:31) invalid GPCM write access TRLX

= 1, CSNT = 1, ACS = 10 or 11, EBDF = 1

MPC875/MPC870 Hardware Specifications, Rev. 3.0

20

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Freescale Semiconductor

Bus Signal Timing

Table 10. Bus Operation Timings (continued)

33 MHz 40 MHz 66 MHz

80 MHz

Num

Characteristic

Unit

Min Max Min Max Min Max Min Max

B31 CLKOUT falling edge to CS valid, as

requested by control bit CST4 in the

corresponding word in the UPM

(MAX = 0.00 × B1 + 6.00)

1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00

ns

B31a CLKOUT falling edge to CS valid, as

requested by control bit CST1 in the

corresponding word in the UPM

(MAX = 0.25 × B1 + 6.80)

7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 ns

B31b CLKOUT rising edge to CS valid, as

requested by control bit CST2 in the

corresponding word in the UPM

(MAX = 0.00 × B1 + 8.00)

1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00

7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.40

ns

B31c CLKOUT rising edge to CS valid, as

requested by control bit CST3 in the

corresponding word in the UPM

(MAX = 0.25 × B1 + 6.30)

B31d CLKOUT falling edge to CS valid, as

requested by control bit CST1 in the

corresponding word in the UPM EBDF = 1

(MAX = 0.375 × B1 + 6.6)

13.30 18.00 11.30 16.00 7.60 12.30 4.69 11.30 ns

B32 CLKOUT falling edge to BS valid, as

requested by control bit BST4 in the

corresponding word in the UPM

(MAX = 0.00 × B1 + 6.00)

1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00

ns

B32a CLKOUT falling edge to BS valid, as

requested by control bit BST1 in the

corresponding word in the UPM, EBDF = 0

(MAX = 0.25 × B1 + 6.80)

7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 ns

B32b CLKOUT rising edge to BS valid, as

requested by control bit BST2 in the

corresponding word in the UPM

(MAX = 0.00 × B1 + 8.00)

1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00

ns

B32c CLKOUT rising edge to BS valid, as

requested by control bit BST3 in the

corresponding word in the UPM

(MAX = 0.25 × B1 + 6.80)

7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 ns

13.30 18.00 11.30 16.00 7.60 12.30 4.49 11.30 ns

B32d CLKOUT falling edge to BS valid, as

requested by control bit BST1 in the

corresponding word in the UPM, EBDF = 1

(MAX = 0.375 × B1 + 6.60)

B33 CLKOUT falling edge to GPL valid, as

requested by control bit GxT4 in the

corresponding word in the UPM

(MAX = 0.00 × B1 + 6.00)

1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00

ns

MPC875/MPC870 Hardware Specifications, Rev. 3.0

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

21

Freescale Semiconductor

Bus Signal Timing

Table 10. Bus Operation Timings (continued)

33 MHz 40 MHz 66 MHz

Min Max Min Max Min Max Min Max

7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 ns

80 MHz

Num

Characteristic

Unit

B33a CLKOUT rising edge to GPL valid, as

requested by control bit GxT3 in the

corresponding word in the UPM

(MAX = 0.25 × B1 + 6.80)

B34 A(0:31), BADDR(28:30), and D(0:31) to

CS valid, as requested by control bit CST4

in the corresponding word in the UPM

(MIN = 0.25 × B1 - 2.00)

5.60

13.20

20.70

5.60

—

4.30

10.50

16.70

4.30

—

1.80

5.60

9.40

1.80

5.60

9.40

1.80

—

1.13

4.25

6.80

1.13

4.25

7.40

1.13

—

ns

B34a A(0:31), BADDR(28:30), and D(0:31) to

CS valid, as requested by control bit CST1

in the corresponding word in the UPM

(MIN = 0.50 × B1 – 2.00)

B34b A(0:31), BADDR(28:30), and D(0:31) to

CS valid, as requested by CST2 in the

corresponding word in UPM

(MIN = 0.75 × B1 – 2.00)

B35 A(0:31), BADDR(28:30) to CS valid, as

requested by control bit BST4 in the

corresponding word in the UPM

(MIN = 0.25 × B1 – 2.00)

B35a A(0:31), BADDR(28:30), and D(0:31) to

BS valid, as requested by BST1 in the

corresponding word in the UPM

13.20

20.70

5.60

10.50

16.70

4.30

(MIN = 0.50 × B1 – 2.00)

B35b A(0:31), BADDR(28:30), and D(0:31) to

BS valid, as requested by control bit BST2

in the corresponding word in the UPM

(MIN = 0.75 × B1 – 2.00)

B36 A(0:31), BADDR(28:30), and D(0:31) to

GPL valid, as requested by control bit

GxT4 in the corresponding word in the

UPM (MIN = 0.25 × B1 – 2.00)

8

B37 UPWAIT valid to CLKOUT falling edge

6.00

1.00

7.00

—

6.00

1.00

7.00

—

6.00

1.00

7.00

—

6.00

1.00

7.00

—

ns

(MIN = 0.00 × B1 + 6.00)

B38 CLKOUT falling edge to UPWAIT valid ⁸

(MIN = 0.00 × B1 + 1.00)

B39 AS valid to CLKOUT rising edge ⁹

(MIN = 0.00 × B1 + 7.00)

B40 A(0:31), TSIZ(0:1), RD/WR, BURST, valid 7.00

to CLKOUT rising edge

(MIN = 0.00 × B1 + 7.00)

B41 TS valid to CLKOUT rising edge (setup

7.00

—

7.00

—

7.00

—

7.00

—

ns

time) (MIN = 0.00 × B1 + 7.00)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Bus Signal Timing

Table 10. Bus Operation Timings (continued)

33 MHz 40 MHz 66 MHz

Min Max Min Max Min Max Min Max

80 MHz

Num

Characteristic

Unit

B42 CLKOUT rising edge to TS valid (hold

2.00

—

2.00

—

2.00

—

2.00

—

ns

time) (MIN = 0.00 × B1 + 2.00)

B43 AS negation to memory controller signals

negation (MAX = TBD)

TBD

¹For part speeds above 50 MHz, use 9.80 ns for B11a.

²The timing required for BR input is relevant when the MPC875/870 is selected to work with the internal bus arbiter.

The timing for BG input is relevant when the MPC875/870 is selected to work with the external bus arbiter.

³For part speeds above 50 MHz, use 2 ns for B17.

⁴The D(0:31) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA input signal is asserted.

⁵For part speeds above 50 MHz, use 2 ns for B19.

⁶The D(0:31) input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is valid only for read

accesses controlled by chip-selects under control of the user-programmable machine (UPM) in the memory

controller, for data beats where DLT3 = 1 in the RAM words. (This is only the case where data is latched on the falling

edge of CLKOUT.)

⁷The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0.

⁸The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings specified in

B37 and B38 are specified to enable the freeze of the UPM output signals as described in Figure 19.

⁹The AS signal is considered asynchronous to the CLKOUT. The timing B39 is specified in order to allow the behavior

specified in Figure 22.

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Freescale Semiconductor

Bus Signal Timing

Figure 4 provides the control timing diagram.

.

2.0 V

CLKOUT

2.0 V

0.8 V

A

B

2.0 V

0.8 V

Outputs

0.8 V

A

B

2.0 V

0.8 V

2.0 V

0.8 V

Outputs

D

C

2.0 V

0.8 V

Inputs

0.8 V

D

C

2.0 V

0.8 V

2.0 V

0.8 V

Inputs

A

B

C

D

Maximum output delay specification

Minimum output hold time

Minimum input setup time specification

Minimum input hold time specification

Figure 4. Control Timing

Figure 5 provides the timing for the external clock.

CLKOUT

B1

B3

B2

B4

B5

Figure 5. External Clock Timing

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Freescale Semiconductor

Bus Signal Timing

Figure 6 provides the timing for the synchronous output signals.

CLKOUT

B8

B7

B9

Output

Signals

B8a

B7a

Output

Signals

B8b

B7b

Output

Signals

Figure 6. Synchronous Output Signals Timing

Figure 7 provides the timing for the synchronous active pull-up and open-drain output signals.

CLKOUT

B13

B11

B12

TS, BB

TA, BI

TEA

B13a

B12a

B11

B14

B15

Figure 7. Synchronous Active Pull-Up Resistor and Open-Drain Outputs Signals Timing

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Freescale Semiconductor

Bus Signal Timing

Figure 8 provides the timing for the synchronous input signals.

CLKOUT

B16

B17

TA, BI

B16a

B17a

TEA, KR,

RETRY, CR

B16b

B17

BB, BG, BR

Figure 8. Synchronous Input Signals Timing

Figure 9 provides normal case timing for input data. It also applies to normal read accesses under the control of the

user-programmable machine (UPM) in the memory controller.

CLKOUT

B16

B17

TA

B18

B19

D[0:31]

Figure 9. Input Data Timing in Normal Case

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Freescale Semiconductor

Bus Signal Timing

Figure 10 provides the timing for the input data controlled by the UPM for data beats where DLT3 = 1 in the UPM

RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)

CLKOUT

TA

B20

B21

D[0:31]

Figure 10. Input Data Timing when Controlled by UPM in the Memory Controller and DLT3 = 1

Figure 11 through Figure 14 provide the timing for the external bus read controlled by various GPCM factors.

CLKOUT

B11

B8

B12

TS

A[0:31]

CSx

B22

B23

B25

B26

B19

OE

B28

WE[0:3]

D[0:31]

B18

Figure 11. External Bus Read Timing (GPCM Controlled—ACS = 00)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Freescale Semiconductor

Bus Signal Timing

CLKOUT

B11

B8

B12

TS

A[0:31]

CSx

B22a

B23

B24

B25

B26

B19

OE

B18

D[0:31]

Figure 12. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 10)

CLKOUT

TS

B11

B8

B12

B22b

B22c

A[0:31]

CSx

B23

B24a

B25

B26

B19

OE

B18

D[0:31]

Figure 13. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 11)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Freescale Semiconductor

Bus Signal Timing

CLKOUT

B11

B12

TS

A[0:31]

CSx

B8

B22a

B23

B27

B26

B19

OE

B27a

B22b B22c

B18

D[0:31]

Figure 14. External Bus Read Timing (GPCM Controlled—TRLX = 1, ACS = 10, ACS = 11)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Freescale Semiconductor

Bus Signal Timing

Figure 15 through Figure 17 provide the timing for the external bus write controlled by various GPCM factors.

CLKOUT

B11

B8

B12

TS

A[0:31]

CSx

B30

B22

B23

B25

B28

WE[0:3]

B29b

B26

OE

B29

B8

B9

D[0:31]

Figure 15. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 0)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Freescale Semiconductor

Bus Signal Timing

CLKOUT

TS

B11

B8

B12

B30a B30c

A[0:31]

B28b B28d

B22

B23

CSx

B29c B29g

B25

WE[0:3]

B29a B29f

B26

OE

B28a B28c

B8

B9

D[0:31]

Figure 16. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 1)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Freescale Semiconductor

Bus Signal Timing

CLKOUT

B11

B12

TS

A[0:31]

CSx

B30b B30d

B8

B28b B28d

B22

B23

B29e B29i

B29d B29h

B25

WE[0:3]

B26

OE

B29b

B28a B28c

B8

B9

D[0:31]

Figure 17. External Bus Write Timing (GPCM Controlled—TRLX = 1, CSNT = 1)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Freescale Semiconductor

Bus Signal Timing

Figure 18 provides the timing for the external bus controlled by the UPM.

CLKOUT

B8

A[0:31]

B31a

B31d

B31c

B31b

B31

CSx

B34

B34a

B34b

B32a B32d

B32c

B32b

B32

BS_A[0:3]

B35 B36

B35a

B33a

B35b

B33

GPL_A[0:5],

GPL_B[0:5]

Figure 18. External Bus Timing (UPM Controlled Signals)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Freescale Semiconductor

Bus Signal Timing

Figure 19 provides the timing for the asynchronous asserted UPWAIT signal controlled by the UPM.

CLKOUT

B37

UPWAIT

B38

CSx

BS_A[0:3]

GPL_A[0:5],

GPL_B[0:5]

Figure 19. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing

Figure 20 provides the timing for the asynchronous negated UPWAIT signal controlled by the UPM.

CLKOUT

B37

UPWAIT

B38

CSx

BS_A[0:3]

GPL_A[0:5],

GPL_B[0:5]

Figure 20. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Freescale Semiconductor

Bus Signal Timing

Figure 21 provides the timing for the synchronous external master access controlled by the GPCM.

CLKOUT

B41

B40

B42

TS

A[0:31],

TSIZ[0:1],

R/W, BURST

B22

CSx

Figure 21. Synchronous External Master Access Timing (GPCM Handled ACS = 00)

Figure 22 provides the timing for the asynchronous external master memory access controlled by the GPCM.

CLKOUT

B39

AS

B40

A[0:31],

TSIZ[0:1],

R/W

B22

CSx

Figure 22. Asynchronous External Master Memory Access Timing (GPCM Controlled—ACS = 00)

Figure 23 provides the timing for the asynchronous external master control signals negation.

AS

B43

CSx, WE[0:3],

OE, GPLx,

BS[0:3]

Figure 23. Asynchronous External Master—Control Signals Negation Timing

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Freescale Semiconductor

Bus Signal Timing

Table 11 provides the interrupt timing for the MPC875/870.

Table 11. Interrupt Timing

All Frequencies

Min Max

Num

Characteristic ¹

Unit

I39

I40

I41

I42

I43

IRQx valid to CLKOUT rising edge (setup time)

IRQx hold time after CLKOUT

IRQx pulse width low

6.00

2.00

3.00

ns

—

IRQx pulse width high

IRQx edge-to-edge time

4xT_CLOCKOUT

¹The I39 and I40 timings describe the testing conditions under which the IRQ lines are tested when being defined as

level sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference

to the CLKOUT.

The I41, I42, and I43 timings are specified to allow correct functioning of the IRQ lines detection circuitry and have

no direct relation with the total system interrupt latency that the MPC875/870 is able to support.

Figure 24 provides the interrupt detection timing for the external level-sensitive lines.

CLKOUT

I39

I40

IRQx

Figure 24. Interrupt Detection Timing for External Level Sensitive Lines

Figure 25 provides the interrupt detection timing for the external edge-sensitive lines.

CLKOUT

I41

I42

IRQx

I43

Figure 25. Interrupt Detection Timing for External Edge-Sensitive Lines

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Freescale Semiconductor

Bus Signal Timing

Table 12 shows the PCMCIA timing for the MPC875/870.

Table 12. PCMCIA Timing

33 MHz 40 MHz

66 MHz

80 MHz

Num

Characteristic

Unit

Min

Max

Min

Max

Min

Max

Min

Max

A(0:31), REG valid to PCMCIA

20.70

—

16.70

—

9.40

—

7.40

—

ns

P44 strobe asserted ¹

(MIN = 0.75 × B1 – 2.00)

A(0:31), REG valid to ALE

28.30

—

23.00

—

13.20

—

10.50

—

ns

P45 negation¹

(MIN = 1.00 × B1 – 2.00)

CLKOUT to REG valid

(MAX = 0.25 × B1 + 8.00)

7.60 15.60 6.30 14.30 3.80 11.80 3.13 11.13

ns

P46

P47

P48

P49

CLKOUT to REG invalid

(MIN = 0.25 × B1 + 1.00)

8.60

—

7.30

—

4.80

—

4.125

—

CLKOUT to CE1, CE2 asserted

(MAX = 0.25 × B1 + 8.00)

7.60 15.60 6.30 14.30 3.80 11.80 3.13 11.13

CLKOUT to CE1, CE2 negated

(MAX = 0.25 × B1 + 8.00)

CLKOUT to PCOE, IORD, PCWE,

—

11.00

—

11.00

—

11.00

—

11.00

P50 IOWR assert time (MAX =

0.00 × B1 + 11.00)

CLKOUT to PCOE, IORD, PCWE, 2.00 11.00 2.00 11.00 2.00 11.00 2.00 11.00

ns

P51 IOWR negate time (MAX =

0.00 × B1 + 11.00)

CLKOUT to ALE assert time (MAX 7.60 13.80 6.30 12.50 3.80 10.00 3.13

= 0.25 × B1 + 6.30)

9.40

11.13

—

ns

P52

P53

P54

CLKOUT to ALE negate time (MAX

= 0.25 × B1 + 8.00)

—

15.60

—

14.30

—

11.80

—

PCWE, IOWR negated to D(0:31)

5.60

8.00

4.30

8.00

1.80

8.00

1.125

8.00

invalid¹(MIN – = 0.25 × B1 – 2.00)

WAITA and WAITB valid to

—

P55 CLKOUT rising edge¹

(MIN = 0.00 × B1 + 8.00)

CLKOUT rising edge to WAITA and 2.00

P56 WAITB invalid¹(MIN = 0.00 × B1 +

2.00)

—

2.00

—

2.00

—

2.00

—

ns

¹PSST = 1. Otherwise add PSST times cycle time.

PSHT = 0. Otherwise add PSHT times cycle time.

These synchronous timings define when the WAITA signals are detected in order to freeze (or relieve) the PCMCIA

current cycle. The WAITA assertion will be effective only if it is detected 2 cycles before the PSL timer expiration.

See Chapter 16, “PCMCIA Interface,” in the MPC885 PowerQUICC Family User’s Manual.

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Freescale Semiconductor

Bus Signal Timing

Figure 26 provides the PCMCIA access cycle timing for the external bus read.

CLKOUT

TS

P44

A[0:31]

P46

P48

P45

P47

P49

P51

P52

REG

CE1/CE2

PCOE, IORD

ALE

P50

P53

P52

B18

B19

D[0:31]

Figure 26. PCMCIA Access Cycles Timing External Bus Read

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Freescale Semiconductor

Bus Signal Timing

Figure 27 provides the PCMCIA access cycle timing for the external bus write.

CLKOUT

TS

P44

A[0:31]

P46

P48

P45

P47

P49

P51

P52

B9

REG

CE1/CE2

PCWE, IOWR

ALE

P50

P53

B8

P54

P52

D[0:31]

Figure 27. PCMCIA Access Cycles Timing External Bus Write

Figure 28 provides the PCMCIA WAIT signals detection timing.

CLKOUT

P55

P56

WAITA

Figure 28. PCMCIA WAIT Signals Detection Timing

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Freescale Semiconductor

Bus Signal Timing

Table 13 shows the PCMCIA port timing for the MPC875/870.

Table 13. PCMCIA Port Timing

33 MHz 40 MHz

Min Max Min Max Min Max Min Max

66 MHz

80 MHz

Num

Characteristic

Unit

CLKOUT to OPx valid

(MAX = 0.00 × B1 + 19.00)

—

19.00

—

19.00

—

19.00

—

19.00 ns

P57

P58

P59

P60

HRESET negated to OPx

25.70

5.00

1.00

21.70

5.00

1.00

14.40

5.00

1.00

12.40

5.00

1.00

—

ns

drive ¹(MIN = 0.75 × B1 + 3.00)

IP_Xx valid to CLKOUT rising edge

(MIN = 0.00 × B1 + 5.00)

—

CLKOUT rising edge to IP_Xx invalid

(MIN = 0.00 × B1 + 1.00)

—

¹OP2 and OP3 only.

Figure 29 provides the PCMCIA output port timing for the MPC875/870.

CLKOUT

P57

Output

Signals

HRESET

P58

OP2, OP3

Figure 29. PCMCIA Output Port Timing

Figure 30 provides the PCMCIA input port timing for the MPC875/870.

CLKOUT

P59

P60

Input

Signals

Figure 30. PCMCIA Input Port Timing

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Freescale Semiconductor

Bus Signal Timing

Table 14 shows the debug port timing for the MPC875/870.

Table 14. Debug Port Timing

All Frequencies

Min

Num

Characteristic

Unit

Max

D61 DSCK cycle time

3 × T_CLOCKOUT

—

ns

D62 DSCK clock pulse width

D63 DSCK rise and fall times

D64 DSDI input data setup time

D65 DSDI data hold time

1.25 × T_CLOCKOUT

0.00

8.00

5.00

0.00

3.00

D66 DSCK low to DSDO data valid

D67 DSCK low to DSDO invalid

15.00 ns

2.00 ns

Figure 31 provides the input timing for the debug port clock.

DSCK

D61

D62

D61

D62

D63

Figure 31. Debug Port Clock Input Timing

Figure 32 provides the timing for the debug port.

D63

DSCK

D64

D65

DSDI

D66

D67

DSDO

Figure 32. Debug Port Timings

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Freescale Semiconductor

Bus Signal Timing

Table 15 shows the reset timing for the MPC875/870.

Table 15. Reset Timing

33 MHz 40 MHz

66 MHz

80 MHz

Num

Characteristic

Unit

Min

Max

Min

Max

Min

Max

Min

Max

CLKOUT to HRESET high

—

20.00

—

20.00

—

20.00

—

20.00

ns

R69 impedance (MAX = 0.00 × B1 +

20.00)

CLKOUT to SRESET high

R70 impedance (MAX = 0.00 × B1 +

20.00)

—

20.00

—

20.00

—

20.00

—

20.00

—

ns

RSTCONF pulse width

R71

515.20

425.00

257.60

212.50

(MIN = 17.00 × B1)

R72

—

ns

Configuration data to HRESET

504.50

425.00

277.30

237.50

R73 rising edge setup time

(MIN = 15.00 × B1 + 50.00)

Configuration data to RSTCONF 350.00

R74 rising edge setup time

—

350.00

0.00

—

350.00

0.00

—

350.00

0.00

—

ns

(MIN = 0.00 × B1 + 350.00)

Configuration data hold time after 0.00

R75 RSTCONF negation

(MIN = 0.00 × B1 + 0.00)

Configuration data hold time after 0.00

R76 HRESET negation

—

(MIN = 0.00 × B1 + 0.00)

HRESET and RSTCONF

R77 asserted to data out drive

(MAX = 0.00 × B1 + 25.00)

—

25.00

RSTCONF negated to data out

R78 high impedance

—

(MAX = 0.00 × B1 + 25.00)

CLKOUT of last rising edge

before chip three-states

R79 HRESET to data out high

impedance

—

(MAX = 0.00 × B1 + 25.00)

DSDI, DSCK setup

R80

90.90

0.00

—

75.00

0.00

—

45.50

0.00

—

37.50

0.00

—

ns

(MIN = 3.00 × B1)

DSDI, DSCK hold time

R81

(MIN = 0.00 × B1 + 0.00)

SRESET negated to CLKOUT

R82 rising edge for DSDI and DSCK

sample (MIN = 8.00 × B1)

242.40

200.00

121.20

100.00

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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42

Freescale Semiconductor

Bus Signal Timing

Figure 33 shows the reset timing for the data bus configuration.

HRESET

R71

R76

RSTCONF

R73

R74

R75

D[0:31] (IN)

Figure 33. Reset Timing—Configuration from Data Bus

Figure 34 provides the reset timing for the data bus weak drive during configuration.

CLKOUT

R69

HRESET

R79

RSTCONF

R77

R78

D[0:31] (OUT)

(Weak)

Figure 34. Reset Timing—Data Bus Weak Drive During Configuration

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Freescale Semiconductor

IEEE 1149.1 Electrical Specifications

Figure 35 provides the reset timing for the debug port configuration.

CLKOUT

R70

R82

R80

SRESET

R80

R81

DSCK, DSDI

Figure 35. Reset Timing—Debug Port Configuration

12 IEEE 1149.1 Electrical Specifications

Table 16 provides the JTAG timings for the MPC875/870 shown in Figure 36 to Figure 39.

Table 16. JTAG Timing

All

Frequencies

Num

Characteristic

Unit

Min

Max

J82

J83

J84

J85

J86

J87

J88

J89

J90

J91

J92

J93

J94

J95

J96

TCK cycle time

100.00

40.00

0.00

5.00

25.00

—

ns

TCK clock pulse width measured at 1.5 V

TCK rise and fall times

10.00

—

TMS, TDI data setup time

TMS, TDI data hold time

—

TCK low to TDO data valid

27.00

—

TCK low to TDO data invalid

0.00

—

TCK low to TDO high impedance

TRST assert time

20.00

—

100.00

40.00

—

TRST setup time to TCK low

—

TCK falling edge to output valid

TCK falling edge to output valid out of high impedance

TCK falling edge to output high impedance

Boundary scan input valid to TCK rising edge

TCK rising edge to boundary scan input invalid

50.00

—

50.00

—

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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44

Freescale Semiconductor

IEEE 1149.1 Electrical Specifications

TCK

J82

J83

J82

J83

J84

Figure 36. JTAG Test Clock Input Timing

TCK

TMS, TDI

TDO

J85

J86

J87

J88

J89

Figure 37. JTAG Test Access Port Timing Diagram

TCK

J91

J90

TRST

Figure 38. JTAG TRST Timing Diagram

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Freescale Semiconductor

CPM Electrical Characteristics

TCK

J92

J93

J94

Output

Signals

Output

Signals

J95

J96

Output

Signals

Figure 39. Boundary Scan (JTAG) Timing Diagram

13 CPM Electrical Characteristics

This section provides the AC and DC electrical specifications for the communications processor module (CPM) of

the MPC875/870.

13.1 Port C Interrupt AC Electrical Specifications

Table 17 provides the timings for port C interrupts.

Table 17. Port C Interrupt Timing

33.34 MHz

Num

Characteristic

Unit

Min

Max

35

36

Port C interrupt pulse width low (edge-triggered mode)

Port C interrupt minimum time between active edges

55

—

ns

Figure 40 shows the port C interrupt detection timing.

36

Port C

(Input)

35

Figure 40. Port C Interrupt Detection Timing

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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CPM Electrical Characteristics

13.2 IDMA Controller AC Electrical Specifications

Table 18 provides the IDMA controller timings as shown in Figure 41 to Figure 44.

Table 18. IDMA Controller Timing

All

Frequencies

Num

Characteristic

Unit

Min

Max

40

41

42

43

44

45

46

DREQ setup time to clock high

DREQ hold time from clock high

7

TBD

—

12

20

15

—

ns

1

SDACK assertion delay from clock high

SDACK negation delay from clock low

—

SDACK negation delay from TA low

—

SDACK negation delay from clock high

—

TA assertion to falling edge of the clock setup time (applies to external TA)

7

¹Applies to high-to-low mode (EDM=1)

CLKO

(Output)

41

40

DREQ

(Input)

Figure 41. IDMA External Requests Timing Diagram

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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CPM Electrical Characteristics

CLKO

(Output)

TS

(Output)

R/W

(Output)

42

43

DATA

46

TA

(Input)

SDACK

Figure 42. SDACK Timing Diagram—Peripheral Write, Externally-Generated TA

CLKO

(Output)

TS

(Output)

R/W

(Output)

42

44

DATA

TA

(Output)

SDACK

Figure 43. SDACK Timing Diagram—Peripheral Write, Internally-Generated TA

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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CPM Electrical Characteristics

CLKO

(Output)

TS

(Output)

R/W

(Output)

42

45

DATA

TA

(Output)

SDACK

Figure 44. SDACK Timing Diagram—Peripheral Read, Internally-Generated TA

13.3 Baud Rate Generator AC Electrical Specifications

Table 19 provides the baud rate generator timings as shown in Figure 45.

Table 19. Baud Rate Generator Timing

All

Frequencies

Num

Characteristic

Unit

Min

Max

50

51

52

BRGO rise and fall time

BRGO duty cycle

BRGO cycle

—

40

10

60

—

ns

%

ns

50

BRGOX

51

52

51

Figure 45. Baud Rate Generator Timing Diagram

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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CPM Electrical Characteristics

13.4 Timer AC Electrical Specifications

Table 20 provides the general-purpose timer timings as shown in Figure 46.

Table 20. Timer Timing

All

Frequencies

Num

Characteristic

Unit

Min

Max

61

62

63

64

65

TIN/TGATE rise and fall time

TIN/TGATE low time

10

1

—

25

ns

clk

ns

TIN/TGATE high time

TIN/TGATE cycle time

CLKO low to TOUT valid

2

3

CLKO

60

61

63

62

TIN/TGATE

(Input)

61

64

65

TOUT

(Output)

Figure 46. CPM General-Purpose Timers Timing Diagram

13.5 Serial Interface AC Electrical Specifications

Table 21 provides the serial interface (SI) timings as shown in Figure 47 to Figure 51.

Table 21. SI Timing

All Frequencies

Num

Characteristic

Unit

Min

Max

70

71

L1RCLKB, L1TCLKB frequency (DSC = 0) ^{1, 2}

—

SYNCCLK

/2.5

MHz

L1RCLKB, L1TCLKB width low (DSC = 0) ²

P + 10

—

ns

3

71a L1RCLKB, L1TCLKB width high (DSC = 0)

72

73

L1TXDB, L1ST1 and L1ST2, L1RQ, L1CLKO rise/fall time

15.00

—

L1RSYNCB, L1TSYNCB valid to L1CLKB edge (SYNC setup time)

20.00

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CPM Electrical Characteristics

Table 21. SI Timing (continued)

Characteristic

All Frequencies

Num

Unit

Min

Max

74

75

76

77

78

L1CLKB edge to L1RSYNCB, L1TSYNCB, invalid (SYNC hold time)

L1RSYNCB, L1TSYNCB rise/fall time

35.00

—

ns

15.00

—

L1RXDB valid to L1CLKB edge (L1RXDB setup time)

L1CLKB edge to L1RXDB invalid (L1RXDB hold time)

17.00

13.00

10.00

0.00

ns

—

ns

4

L1CLKB edge to L1ST1 and L1ST2 valid

45.00

55.00

42.00

ns

78A L1SYNCB valid to L1ST1 and L1ST2 valid

ns

79

80

L1CLKB edge to L1ST1 and L1ST2 invalid

L1CLKB edge to L1TXDB valid

ns

80A L1TSYNCB valid to L1TXDB valid ⁴

ns

81

82

L1CLKB edge to L1TXDB high impedance

L1RCLKB, L1TCLKB frequency (DSC =1)

ns

—

16.00 or

SYNCCLK

/2

MHz

83

L1RCLKB, L1TCLKB width low (DSC =1)

P + 10

—

ns

83a L1RCLKB, L1TCLKB width high (DSC = 1)³

84

85

86

87

88

L1CLKB edge to L1CLKOB valid (DSC = 1)

L1RQB valid before falling edge of L1TSYNCB⁴

L1GRB setup time²

30.00

—

ns

1.00

42.00

—

L1TCLK

ns

—

L1GRB hold time

—

ns

L1CLKB edge to L1SYNCB valid (FSD = 00) CNT = 0000, BYT = 0,

DSC = 0)

0.00

ns

¹The ratio SyncCLK/L1RCLKB must be greater than 2.5/1.

²These specs are valid for IDL mode only.

³Where P = 1/CLKOUT. Thus for a 25-MHz CLKO1 rate, P = 40 ns.

⁴These strobes and TxD on the first bit of the frame become valid after the L1CLKB edge or L1SYNCB, whichever

comes later.

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CPM Electrical Characteristics

L1RCLKB

(FE=0, CE=0)

(Input)

71

70

71a

72

L1RCLKB

(FE=1, CE=1)

(Input)

RFSD=1

75

74

L1RSYNCB

(Input)

73

77

L1RXDB

(Input)

BIT0

76

78

79

L1ST(2-1)

(Output)

Figure 47. SI Receive Timing Diagram with Normal Clocking (DSC = 0)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Freescale Semiconductor

CPM Electrical Characteristics

L1RCLKB

(FE=1, CE=1)

(Input)

72

83a

82

L1RCLKB

(FE=0, CE=0)

(Input)

RFSD=1

75

L1RSYNCB

(Input)

73

74

77

L1RXDB

(Input)

BIT0

76

78

79

L1ST(2-1)

(Output)

84

L1CLKOB

(Output)

Figure 48. SI Receive Timing with Double-Speed Clocking (DSC = 1)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Freescale Semiconductor

CPM Electrical Characteristics

L1TCLKB

(FE=0, CE=0)

(Input)

71

70

72

L1TCLKB

(FE=1, CE=1)

(Input)

73

TFSD=0

75

74

L1TSYNCB

(Input)

80a

BIT0

80

81

L1TXDB

(Output)

79

78

L1ST(2-1)

(Output)

Figure 49. SI Transmit Timing Diagram (DSC = 0)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Freescale Semiconductor

CPM Electrical Characteristics

L1RCLKB

(FE=0, CE=0)

(Input)

72

83a

82

L1RCLKB

(FE=1, CE=1)

(Input)

TFSD=0

75

L1RSYNCB

(Input)

73

74

81

L1TXDB

(Output)

BIT0

80

78a

79

L1ST(2-1)

(Output)

78

84

L1CLKOB

(Output)

Figure 50. SI Transmit Timing with Double Speed Clocking (DSC = 1)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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55

Freescale Semiconductor

CPM Electrical Characteristics

Figure 51. IDL Timing

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Freescale Semiconductor

CPM Electrical Characteristics

13.6 SCC in NMSI Mode Electrical Specifications

Table 22 provides the NMSI external clock timing.

Table 22. NMSI External Clock Timing

All Frequencies

Num

Characteristic

Unit

Min

Max

100 RCLK3 and TCLK3 width high ¹

1/SYNCCLK

—

ns

101 RCLK3 and TCLK3 width low

1/SYNCCLK +5

102 RCLK3 and TCLK3 rise/fall time

—

15.00

50.00

—

103 TXD3 active delay (from TCLK3 falling edge)

104 RTS3 active/inactive delay (from TCLK3 falling edge)

105 CTS3 setup time to TCLK3 rising edge

106 RXD3 setup time to RCLK3 rising edge

107 RXD3 hold time from RCLK3 rising edge ²

108 CD3 setup time to RCLK3 rising edge

0.00

5.00

—

¹The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater than or equal to 2.25/1.

²Also applies to CD and CTS hold time when they are used as external sync signals.

Table 23 provides the NMSI internal clock timing.

Table 23. NMSI Internal Clock Timing

All Frequencies

Min Max

0.00 SYNCCLK/3 MHz

Num

Characteristic

Unit

100 RCLK3 and TCLK3 frequency ¹

102 RCLK3 and TCLK3 rise/fall time

—

30.00

—

ns

103 TXD3 active delay (from TCLK3 falling edge)

104 RTS3 active/inactive delay (from TCLK3 falling edge)

105 CTS3 setup time to TCLK3 rising edge

106 RXD3 setup time to RCLK3 rising edge

107 RXD3 hold time from RCLK3 rising edge ²

108 CD3 setup time to RCLK3 rising edge

0.00

40.00

0.00

—

40.00

—

¹The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater or equal to 3/1.

²Also applies to CD and CTS hold time when they are used as external sync signals

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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CPM Electrical Characteristics

Figure 52 through Figure 54 show the NMSI timings.

RCLK3

102

101

106

100

RxD3

(Input)

107

108

CD3

(Input)

107

CD3

SYNC Input)

Figure 52. SCC NMSI Receive Timing Diagram

TCLK3

102

101

100

TxD3

(Output)

103

105

RTS3

(Output)

104

CTS3

(Input)

107

CTS3

(SYNC Input)

Figure 53. SCC NMSI Transmit Timing Diagram

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CPM Electrical Characteristics

TCLK3

102

101

100

TxD3

(Output)

103

RTS3

(Output)

104

107

104

105

CTS3

(Echo Input)

Figure 54. HDLC Bus Timing Diagram

13.7 Ethernet Electrical Specifications

Table 24 provides the Ethernet timings as shown in Figure 55 to Figure 57.

Table 24. Ethernet Timing

All

Frequencies

Num

Characteristic

Unit

Min

Max

120 CLSN width high

121 RCLK3 rise/fall time

122 RCLK3 width low

123 RCLK3 clock period ¹

124 RXD3 setup time

125 RXD3 hold time

40

—

15

—

ns

40

80

20

5

120

—

126 RENA active delay (from RCLK3 rising edge of the last data bit)

127 RENA width low

10

100

—

128 TCLK3 rise/fall time

15

—

129 TCLK3 width low

40

99

—

130 TCLK3 clock period¹

101

50

131 TXD3 active delay (from TCLK3 rising edge)

132 TXD3 inactive delay (from TCLK3 rising edge)

6.5

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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CPM Electrical Characteristics

Table 24. Ethernet Timing (continued)

Characteristic

All

Frequencies

Num

Unit

Min

Max

133 TENA active delay (from TCLK3 rising edge)

134 TENA inactive delay (from TCLK3 rising edge)

138 CLKO1 low to SDACK asserted ²

10

—

50

20

ns

139 CLKO1 low to SDACK negated ²

¹The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater than or equal to 2/1.

²SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.

CLSN(CTS1)

(Input)

120

Figure 55. Ethernet Collision Timing Diagram

RCLK3

121

124

123

Last Bit

RxD3

(Input)

125

126

127

RENA(CD3)

(Input)

Figure 56. Ethernet Receive Timing Diagram

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Freescale Semiconductor

CPM Electrical Characteristics

TCLK3

128

129

131

121

TxD3

(Output)

132

133

134

TENA(RTS3)

(Input)

RENA(CD3)

(Input)

(NOTE 2)

NOTES:

1. Transmit clock invert (TCI) bit in GSMR is set.

2. If RENA is negated before TENA or RENA is not asserted at all during transmit, then the

CSL bit is set in the buffer descriptor at the end of the frame transmission.

Figure 57. Ethernet Transmit Timing Diagram

13.8 SMC Transparent AC Electrical Specifications

Table 25 provides the SMC transparent timings as shown in Figure 58.

Table 25. SMC Transparent Timing

All

Frequencies

Num

Characteristic

Unit

Min

Max

150 SMCLK clock period ¹

151 SMCLK width low

151A SMCLK width high

152 SMCLK rise/fall time

100

50

—

10

20

5

—

15

50

—

ns

153 SMTXD active delay (from SMCLK falling edge)

154 SMRXD/SMSYNC setup time

155 RXD1/SMSYNC hold time

1

SyncCLK must be at least twice as fast as SMCLK.

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Freescale Semiconductor

CPM Electrical Characteristics

SMCLK

152

151

150

SMTXD

(Output)

NOTE

154

153

155

SMSYNC

154

155

SMRXD

(Input)

NOTE:

1. This delay is equal to an integer number of character-length clocks.

Figure 58. SMC Transparent Timing Diagram

13.9 SPI Master AC Electrical Specifications

Table 26 provides the SPI master timings as shown in Figure 59 and Figure 60.

Table 26. SPI Master Timing

All

Frequencies

Num

Characteristic

Unit

Min

Max

160 MASTER cycle time

4

2

1024

512

—

t_cyc

ns

161 MASTER clock (SCK) high or low time

162 MASTER data setup time (inputs)

163 Master data hold time (inputs)

164 Master data valid (after SCK edge)

165 Master data hold time (outputs)

166 Rise time output

15

0

—

0

10

—

15

167 Fall time output

15

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Freescale Semiconductor

CPM Electrical Characteristics

SPICLK

(CI=0)

(Output)

161

167

166

167

160

SPICLK

(CI=1)

(Output)

163

162

SPIMISO

msb

Data

165

lsb

164

msb

(Input)

167

166

SPIMOSI

(Output)

msb

Data

lsb

Figure 59. SPI Master (CP = 0) Timing Diagram

SPICLK

(CI=0)

(Output)

161

167

166

167

160

SPICLK

(CI=1)

(Output)

163

162

166

SPIMISO

msb

Data

165

lsb

164

msb

(Input)

167

166

SPIMOSI

(Output)

msb

Data

lsb

msb

Figure 60. SPI Master (CP = 1) Timing Diagram

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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CPM Electrical Characteristics

13.10SPI Slave AC Electrical Specifications

Table 27 provides the SPI slave timings as shown in Figure 61 and Figure 62.

Table 27. SPI Slave Timing

All

Frequencies

Num

Characteristic

Unit

Min

Max

170 Slave cycle time

2

—

50

t_cyc

ns

171 Slave enable lead time

172 Slave enable lag time

15

1

ns

173 Slave clock (SPICLK) high or low time

174 Slave sequential transfer delay (does not require deselect)

175 Slave data setup time (inputs)

t_cyc

ns

1

20

—

176 Slave data hold time (inputs)

ns

177 Slave access time

ns

SPISEL

(Input)

172

171

174

SPICLK

(CI=0)

(Input)

173

182

181

182

173

170

SPICLK

(CI=1)

(Input)

177

180

Data

179

178

Undef

SPIMISO

(Output)

msb

lsb

msb

175

176

msb

181 182

lsb

SPIMOSI

(Input)

Data

msb

Figure 61. SPI Slave (CP = 0) Timing Diagram

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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CPM Electrical Characteristics

SPISEL

(Input)

172

174

171

170

SPICLK

(CI=0)

(Input)

173

182

181

173

181

SPICLK

(CI=1)

(Input)

177

182

180

178

SPIMISO

(Output)

msb

Undef

175

Data

lsb

179

176

181 182

Data

SPIMOSI

(Input)

msb

lsb

Figure 62. SPI Slave (CP = 1) Timing Diagram

13.11I²C AC Electrical Specifications

2

Table 28 provides the I C (SCL < 100 KHz) timings.

Table 28. I²C Timing (SCL < 100 KHZ)

All

Frequencies

Num

Characteristic

Unit

Min

Max

200 SCL clock frequency (slave)

0

100

—

1

KHz

µs

200 SCL clock frequency (master) ¹

1.5

4.7

4.0

4.7

4.0

0

202 Bus free time between transmissions

203 Low period of SCL

µs

204 High period of SCL

205 Start condition setup time

206 Start condition hold time

207 Data hold time

µs

208 Data setup time

250

—

ns

209 SDL/SCL rise time

µs

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Freescale Semiconductor

CPM Electrical Characteristics

Table 28. I²C Timing (SCL < 100 KHZ) (continued)

Characteristic

All

Frequencies

Num

Unit

Min

Max

210 SDL/SCL fall time

—

300

—

ns

211

Stop condition setup time

4.7

µs

¹SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3) × pre_scalar × 2).

The ratio SyncClk/(BRGCLK/pre_scalar) must be greater than or equal to 4/1.

2

Table 29 provides the I C (SCL > 100 KHz) timings.

Table 29. I²C Timing (SCL > 100 KHZ)

All Frequencies

Num

Characteristic

Expression

Unit

Min

Max

200 SCL clock frequency (slave)

200 SCL clock frequency (master) ¹

202 Bus free time between transmissions

203 Low period of SCL

fSCL

—

0

BRGCLK/48

Hz

s

BRGCLK/16512

1/(2.2 × fSCL)

0

BRGCLK/48

—

s

204 High period of SCL

—

s

205 Start condition setup time

206 Start condition hold time

207 Data hold time

—

s

—

s

—

s

208 Data setup time

—

1/(40 × fSCL)

—

s

209 SDL/SCL rise time

—

1/(10 × fSCL)

1/(33 × fSCL)

—

s

210 SDL/SCL fall time

—

s

211

Stop condition setup time

—

1/2(2.2 × fSCL)

s

¹SCL frequency is given by SCL = BrgClk_frequency / ((BRG register + 3) × pre_scalar × 2).

The ratio SyncClk/(Brg_Clk/pre_scalar) must be greater than or equal to 4/1.

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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USB Electrical Characteristics

2

Figure 63 shows the I C bus timing.

SDA

202

203

204

208

205

207

SCL

206

209

210

211

Figure 63. I²C Bus Timing Diagram

14 USB Electrical Characteristics

This section provides the AC timings for the USB interface.

14.1 USB Interface AC Timing Specifications

The USB Port uses the transmit clock on SCC1. Table 30 lists the USB interface timings.

Table 30. USB Interface AC Timing Specifications

All Frequencies

Name

Characteristic

Unit

Min

Max

US1 USBCLK frequency of operation ¹

MHz

Low speed

Full speed

6

48

US4 USBCLK duty cycle (measured at 1.5 V)

45

55

%

¹USBCLK accuracy should be ± 500 ppm or better. USBCLK may be stopped to conserve power.

15 FEC Electrical Characteristics

This section provides the AC electrical specifications for the fast Ethernet controller (FEC). Note that the timing

specifications for the MII signals are independent of system clock frequency (part speed designation). Also, MII

signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.

15.1 MII and Reduced MII Receive Signal Timing

The receiver functions correctly up to a MII_RX_CLK maximum frequency of 25 MHz +1%. The reduced MII

(RMII) receiver functions correctly up to a RMII_REFCLK maximum frequency of 50 MHz + 1%. There is no

minimum frequency requirement. In addition, the processor clock frequency must exceed the MII_RX_CLK

frequency – 1%.

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Table 31 provides information on the MII receive signal timing.

Table 31. MII Receive Signal Timing

Characteristic

Num

Min

Max

Unit

M1

M2

M3

M4

MII_RXD[3:0], MII_RX_DV, MII_RX_ER to MII_RX_CLK setup

MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold

MII_RX_CLK pulse width high

5

—

ns

35%

4

65% MII_RX_CLK period

MII_RX_CLK pulse width low

M1_R RMII_RXD[1:0], RMII_CRS_DV, RMII_RX_ERR to RMII_REFCLK

MII setup

—

ns

M2_R RMII_REFCLK to RMII_RXD[1:0], RMII_CRS_DV, RMII_RX_ERR

MII hold

2

—

ns

Figure 64 shows MII receive signal timing.

M3

MII_RX_CLK (input)

M4

MII_RXD[3:0] (inputs)

MII_RX_DV

MII_RX_ER

M1

M2

Figure 64. MII Receive Signal Timing Diagram

15.2 MII and Reduced MII Transmit Signal Timing

The transmitter functions correctly up to a MII_TX_CLK maximum frequency of 25 MHz + 1%. There is no

minimum frequency requirement. In addition, the processor clock frequency must exceed the MII_TX_CLK

frequency – 1%.

Table 32 provides information on the MII transmit signal timing.

Table 32. MII Transmit Signal Timing

Num

Characteristic

Min

Max

Unit

M5

M6

M7

M8

MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid

MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid

MII_TX_CLK pulse width high

5

—

ns

—

25

35%

65% MII_TX_CLK period

MII_TX_CLK pulse width low

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Table 32. MII Transmit Signal Timing (continued)

Num

Characteristic

Min

Max

Unit

M20_R RMII_TXD[1:0], RMII_TX_EN to RMII_REFCLK setup

MII

4

—

ns

M21_R RMII_TXD[1:0], RMII_TX_EN data hold from RMII_REFCLK rising

2

—

ns

MII

edge

Figure 65 shows the MII transmit signal timing diagram.

M7

MII_TX_CLK (input)

M5

M8

MII_TXD[3:0] (outputs)

MII_TX_EN

MII_TX_ER

M6

Figure 65. MII Transmit Signal Timing Diagram

15.3 MII Async Inputs Signal Timing (MII_CRS, MII_COL)

Table 33 provides information on the MII async inputs signal timing.

Table 33. MII Async Inputs Signal Timing

Num

Characteristic

Min

Max

Unit

M9

MII_CRS, MII_COL minimum pulse width

1.5

—

MII_TX_CLK period

Figure 66 shows the MII asynchronous inputs signal timing diagram.

MII_CRS, MII_COL

M9

Figure 66. MII Async Inputs Timing Diagram

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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FEC Electrical Characteristics

15.4 MII Serial Management Channel Timing (MII_MDIO, MII_MDC)

Table 34 provides information on the MII serial management channel signal timing. The FEC functions correctly

with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under investigation.

Table 34. MII Serial Management Channel Timing

Num

Characteristic

Min

Max

Unit

M10 MII_MDC falling edge to MII_MDIO output invalid (minimum

propagation delay)

0

—

ns

M11 MII_MDC falling edge to MII_MDIO output valid (max prop delay)

M12 MII_MDIO (input) to MII_MDC rising edge setup

M13 MII_MDIO (input) to MII_MDC rising edge hold

M14 MII_MDC pulse width high

—

10

25

—

ns

0

—

ns

40%

60%

MII_MDC period

M15 MII_MDC pulse width low

Figure 67 shows the MII serial management channel timing diagram.

M14

MM15

MII_MDC (output)

M10

MII_MDIO (output)

M11

MII_MDIO (input)

M12

M13

Figure 67. MII Serial Management Channel Timing Diagram

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Mechanical Data and Ordering Information

16 Mechanical Data and Ordering Information

Table 35 identifies the packages and operating frequencies available for the MPC875/870.

Table 35. Available MPC875/870 Packages/Frequencies

Package Type

Temperature (Tj) Frequency (MHz) Order Number

Plastic ball grid array

ZT suffix — Leaded

VR suffix — Lead-Free are available as needed

0°C to 95°C

66

KMPC875ZT66

KMPC870ZT66

MPC875ZT66

MPC870ZT66

80

KMPC875ZT80

KMPC870ZT80

MPC875ZT80

MPC870ZT80

133

66

KMPC875ZT133

KMPC870ZT133

MPC875ZT133

MPC870ZT133

Plastic ball grid array

CZT suffix — Leaded

CVR suffix — Lead-Free are available as needed

-40°C to 100°C

KMPC875CZT66

KMPC870CZT66

MPC875CZT66

MPC870CZT66

133

KMPC875CZT133

KMPC870CZT133

MPC875CZT133

MPC870CZT133

16.1 Pin Assignments

Figure 68 shows the JEDEC pinout of the PBGA package as viewed from the top surface. For additional

information, see the MPC885 PowerQUICC Family User’s Manual.

NOTE

The pin numbering starts with B2 in order to conform to the JEDEC standard for

23-mm body size using a 16 × 16 array.

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NOTE: This is the top view of the device.

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

B

C

D

E

F

MODCK2 TEXP EXTCLK MODCK1 OP0

ALEA

AS

IPB0

BURST

IRQ2

IRQ6

BB

BR

TEA

BI

CS0

CS3

CS5

N/C

RSTCONF

IPA7

SRESET BADDR29 OP1

WAITA PORESET XTAL

ALEB

TS

TA

BDIP

CS2

CE1A GPLAB3 GPLA0

IPA2

IPA5

D30

IPA4

D31

D29

EXTAL BADDR30 IPB1

BG

GPLA4 GPLA5

WR

CS4

OE

CE2A

GPLAB2

BSA0

CS7

WE0

BSA3

WE2

BSA1

TSIZ0

WE1

BSA2

A31

IPA3 VSSSYN VDDSYN HRESET BADDR28 IRQ4

IRQ3

VDDL

CS1

GPLB4

CS6

VDDL

VDDH

IPA6

IPA1 VSSSYN1

G

H

J

VDDH

D28

D7

CLKOUT

D24

D26

D25

D21

IPA0

WE3

TSIZ1

A28

A26

A30

A21

A22

A25

A20

A18

A24

A29

VDDL

GND

VDDH

VDDL

D22

D18

D6

D19

D20

A23

GND

K

L

GND

VDDL

VDDH

D5

D3

D15

D2

D16

D27

D14 VDDL

A14

A10

A19

A12

A27

A15

A17

A16

GND

VDDH

D0

VDDH

M

N

P

R

VDDH

A2

A8

A6

A3

A11

A7

A13

A9

D11

D10

D23

D9

D1

D12

D13

PE18

IRQ7

IRQ1

IRQ0

PA2

PA0

MII_MDIO

PB27

VDDL

PC6

VDDL

PE14

PB26

PC11

A1

D17

PE22

PA4

PE31

PA6

PA7

TDO

TCK

PA15

A5

A4

D4

D8

PE25

PA1

PA3

PE19

PE27

PE28

PE30

PA11 MII_COL

PA10

PB28

PC15

A0

PB29

T

PD8

PE26

N/C

PB31

PE15

PE29

PE17

PE24

PE21

PC7

PB19

PB24

PB23

TDI

TMS

PC12

GND

N/C

PB30

N/C

U

PE20

PE23 MII-TX-EN PE16

PC13 MII-CRS PC10

PB25

PA14

TRST

Figure 68. Pinout of the PBGA Package—JEDEC Standard

Table 36 contains a list of the MPC875/870 input and output signals and shows multiplexing and pin assignments.

Table 36. Pin Assignments—JEDEC Standard

Name

Pin Number

Type

Bidirectional

A[0:31]

R16, N14, M14, P15, P17, P16, N15, N16, M15, N17, L14, M16,

L15, M17, K14, L16, L17, K17, G17, K15, J16, J15, G16, J14, H17, Three-state (3.3 V only)

H16, G15, K16, H14, J17, H15, F17

TSIZ0

REG

F16

Bidirectional

Three-state (3.3 V only)

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Table 36. Pin Assignments—JEDEC Standard (continued)

Pin Number

Name

Type

Bidirectional

TSIZ1

G14

D13

B9

Three-state (3.3 V only)

RD/WR

BURST

Bidirectional

Three-state (3.3 V only)

Bidirectional

Three-state (3.3 V only)

BDIP

GPL_B5

C13

C11

C12

Output

TS

Bidirectional

Active pull-up (3.3 V only)

TA

Bidirectional

Active pull-up (3.3 V only)

TEA

BI

B12

B13

Open-drain

Bidirectional

Active pull-up (3.3 V only)

IRQ2

RSV

C9

E9

Bidirectional

Three-state (3.3 V only)

IRQ4

Bidirectional

KR

Three-state (3.3 V only)

RETRY

SPKROUT

D[0:31]

L5, N3, L3, L2, R2, K2, H3, G2, R3, M3, N2, M2, M4, N4, K5, K3, K4, Bidirectional

P3, J2, J3, J4, J5, H2, P2, H4, H5, G5, L4, G3, F2, F3, E2

Three-state (3.3 V only)

CR

E10

Input

IRQ3

FRZ

B10

Bidirectional

IRQ6

Three-state (3.3 V only)

BR

BG

BB

B11

D10

C10

Bidirectional (3.3 V only)

Bidirectional

Active pull-up (3.3 V only)

IRQ0

M6

Input (3.3 V only)

Output

IRQ1

P5

IRQ7

N5

CS[0:5]

B14, E11, C14, B15, E13, B16

F12

CS6

Output

CE1_B

CS7

D15

Output

CE2_B

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Table 36. Pin Assignments—JEDEC Standard (continued)

Pin Number

Name

Type

WE0

BS_B0

IORD

E15

D17

D16

G13

Output

WE1

BS_B1

IOWR

WE2

BS_B2

PCOE

WE3

BS_B3

PCWE

BS_A[0:3]

F14, E16, E17, F15

C17

Output

GPL_A0

GPL_B0

OE

GPL_A1

GPL_B1

F13

Output

GPL_A[2:3]

GPL_B[2:3]

CS[2–3]

E14, C16

UPWAITA

GPL_A4

D11

E12

Bidirectional (3.3 V only)

Bidirectional

UPWAITB

GPL_B4

GPL_A5

PORESET

RSTCONF

HRESET

SRESET

XTAL

D12

D5

C3

E7

Output

Input (3.3 V only)

Open-drain

Analog output

Analog input (3.3 V only)

Output

C4

D6

D7

G4

B4

EXTAL

CLKOUT

EXTCLK

TEXP

Input (3.3 V only)

Output

B3

ALE_A

B7

Output

CE1_A

C15

D14

D4

Output

CE2_A

Output

WAIT_A

Input (3.3 V only)

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Table 36. Pin Assignments—JEDEC Standard (continued)

Name

Pin Number

Type

IP_A0

IP_A1

IP_A2

G6

F5

D3

Input (3.3 V only)

IOIS16_A

IP_A3

IP_A4

IP_A5

IP_A6

IP_A7

E4

D2

E3

F4

C2

C8

Input (3.3 V only)

ALE_B

DSCK

Bidirectional

Three-state (3.3 V only)

IP_B[0:1]

IWP[0:1]

VFLS[0:1]

B8, D9

Bidirectional (3.3 V only)

OP0

OP1

B6

C6

B5

Bidirectional (3.3 V only)

Output

OP2

Bidirectional (3.3 V only)

MODCK1

STS

OP3

B2

Bidirectional (3.3 V only)

MODCK2

DSDO

BADDR[28:29]

E8, C5

D8

Output

BADDR30

REG

AS

C7

Input (3.3 V only)

Bidirectional

PA15

P14

USBRXD

PA14

USBOE

U16

R9

Bidirectional

(Optional: open-drain)

PA11

Bidirectional

RXD4

MII1-TXD0

RMII1-TXD0

(Optional: open-drain)

(5-V tolerant)

PA10

R12

Bidirectional

MII1-TXERR

TIN4

(Optional: open-drain)

(5-V tolerant)

CLK7

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Table 36. Pin Assignments—JEDEC Standard (continued)

Name

Pin Number

Type

Bidirectional

PA7

CLK1

BRGO1

TIN1

R11

PA6

CLK2

TOUT1

P11

P7

Bidirectional

PA4

CTS4

MII1-TXD1

RMII-TXD1

PA3

R5

N6

T4

P6

T5

Bidirectional

(5-V tolerant)

MII1-RXER

RMII1-RXER

BRGO3

PA2

Bidirectional

(5-V tolerant)

MII1-RXDV

RMII1-CRS_DV

TXD4

PA1

Bidirectional

(5-V tolerant)

MII1-RXD0

RMII1-RXD0

BRGO4

PA0

Bidirectional

(5-V tolerant)

MII1-RXD1

RMII1-RXD1

TOUT4

PB31

Bidirectional

SPISEL

MII1 - TXCLK

RMII1-REFCLK

(Optional: open-drain)

(5-V tolerant)

PB30

SPICLK

T17

R17

R14

N13

N12

Bidirectional

(Optional: open-drain)

(5-V tolerant)

PB29

SPIMOSI

Bidirectional

(Optional: open-drain)

(5-V tolerant)

PB28

SPIMISO

BRGO4

Bidirectional

(Optional: open-drain)

(5-V tolerant)

PB27

I2CSDA

BRGO1

Bidirectional

(Optional: open-drain)

PB26

Bidirectional

I2CSCL

BRGO2

(Optional: open-drain)

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Table 36. Pin Assignments—JEDEC Standard (continued)

Name

Pin Number

Type

Bidirectional

PB25

SMTXD1

U13

T12

U12

T11

R15

U9

(Optional: open-drain)

(5-V tolerant)

PB24

SMRXD1

Bidirectional

(Optional: open-drain)

(5-V tolerant)

PB23

SDACK1

SMSYN1

Bidirectional

(Optional: open-drain)

PB19

MII1-RXD3

RTS4

Bidirectional

(Optional: open-drain)

PC15

DREQ0

L1ST1

Bidirectional

(5-V tolerant)

PC13

Bidirectional

(5-V tolerant)

MII1-TXD3

SDACK1

PC12

MII1-TXD2

TOUT1

T15

Bidirectional

(5-V tolerant)

PC11

USBRXP

P12

U11

Bidirectional

PC10

USBRXN

TGATE1

PC7

CTS4

L1TSYNCB

USBTXP

T10

P10

T3

Bidirectional

(5-V tolerant)

PC6

CD4

L1RSYNCB

USBTXN

Bidirectional

(5-V tolerant)

PD8

RXD4

Bidirectional

(5-V tolerant)

MII-MDC

RMII-MDC

PE31

P9

Bidirectional

CLK8

(Optional: open-drain)

L1TCLKB

MII1-RXCLK

PE30

R8

Bidirectional

L1RXDB

MII1-RXD2

(Optional: open-drain)

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Mechanical Data and Ordering Information

Table 36. Pin Assignments—JEDEC Standard (continued)

Name

Pin Number

Type

Bidirectional

PE29

U7

R7

MII2-CRS

(Optional: open-drain)

PE28

Bidirectional

TOUT3

MII2-COL

(Optional: open-drain)

PE27

L1RQB

MII2-RXERR

RMII2-RXERR

T6

T2

R4

U8

U4

P4

Bidirectional

(Optional: open-drain)

PE26

Bidirectional

(Optional: open-drain)

L1CLKOB

MII2-RXDV

RMII2-CRS_DV

PE25

RXD4

MII2-RXD3

L1ST2

Bidirectional

(Optional: open-drain)

PE24

Bidirectional

(Optional: open-drain)

SMRXD1

BRGO1

MII2-RXD2

PE23

TXD4

MII2-RXCLK

L1ST1

Bidirectional

(Optional: open-drain)

PE22

Bidirectional

TOUT2

(Optional: open-drain)

MII2-RXD1

RMII2-RXD1

SDACK1

PE21

T9

Bidirectional

TOUT1

(Optional: open-drain)

MII2-RXD0

RMII2-RXD0

PE20

MII2-TXER

U3

R6

Bidirectional

(Optional: open-drain)

PE19

Bidirectional

L1TXDB

(Optional: open-drain)

MII2-TXEN

RMII2-TXEN

PE18

M5

Bidirectional

SMTXD1

MII2-TXD3

(Optional: open-drain)

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Mechanical Data and Ordering Information

Table 36. Pin Assignments—JEDEC Standard (continued)

Pin Number

Name

Type

Bidirectional

PE17

TIN3

CLK5

T8

(Optional: open-drain)

BRGO3

SMSYN1

MII2-TXD2

PE16

U6

Bidirectional

L1RCLKB

CLK6

(Optional: open-drain)

MII2-TXCLK

RMII2-REFCLK

PE15

T7

P8

Bidirectional

TGATE1

MII2-TXD1

RMII2-TXD1

PE14

MII2-TXD0

RMII2-TXD0

TMS

T14

T13

R13

U14

P13

Input

(5-V tolerant)

TDI

DSDI

Input

(5-V tolerant)

TCK

DSCK

Input

(5-V tolerant)

TRST

Input

(5-V tolerant)

TDO

Output

DSDO

(5-V tolerant)

MII1_CRS

MII_MDIO

U10

M13

Input

Bidirectional

(5-V tolerant)

MII1_TX_EN

U5

Output

RMII1_TX_EN

(5-V tolerant)

MII1_COL

V_SSSYN

V_SSSYN1

V_DDSYN

GND

R10

E5

Input

PLL analog GND

PLL analog V_DD

F6

E6

H8, H9, H10, H11, J8, J9, J10, J11, K8, K9, K10, K11, L8, L9, L10, Power

L11, U15

V_DDL

F7, F8, F9, F10, F11, H6, H13, J6, J13, K6, K13, L6, L13, N7, N8, Power

N9, N10, N11

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Table 36. Pin Assignments—JEDEC Standard (continued)

Name

Pin Number

Type

V_DDH

N/C

G7, G8, G9, G10, G11, G12, H7, H12, J7, J12, K7, K12, L7, L12, M7, Power

M8, M9, M10, M11, M12

B17, T16, U2, U17

No-connect

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16.2 Mechanical Dimensions of the PBGA Package

Figure 69 shows the mechanical dimensions of the PBGA package.

NOTES:

1. ALL DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M—1994.

3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A.

4. DATUM A, THE SEATING PLANE, IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS.

Note: Solder sphere composition is 95.5%Sn 45%Ag 0.5%Cu for MPC875/870VRXXX.

Solder sphere composition is 62%Sn 36%Pb 2%Ag for MPC875/870ZTXXX.

Figure 69. Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package

MPC875/MPC870 Hardware Specifications, Rev. 3.0

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Document Revision History

17 Document Revision History

Table 37 lists significant changes between revisions of this hardware specification.

Table 37. Document Revision History

Revision

Number

Date

Changes

0

2/2003

3/2003

5/2003

Initial release.

0.1

0.2

Took out the time-slot assigner and changed the SCC for SCC3 to SCC4.

Changed the package drawing, removed all references to Data Parity. Changed the SPI

Master Timing Specs. 162 and 164. Added the RMII and USB timing. Added the 80-MHz

timing.

0.3

0.4

5/2003

Made sure the pin types were correct. Changed the Features list to agree with the

MPC885.

Corrected the signals that had overlines on them. Made corrections on two pins that were

typos.

0.5

0.6

5/2003

Changed the pin descriptions for PD8 and PD9.

Changed a few typos. Put back the I2C. Put in the new reset configuration, corrected the

USB timing.

0.7

0.8

6/2003

8/2003

Changed the pin descriptions per the June 22 spec, removed Utopia from the pin

descriptions, changed PADIR, PBDIR, PCDIR and PDDIR to be 0 in the Mandatory

Reset Config.

Added the reference to USB 2.0 to the Features list and removed 1.1 from USB on the

block diagrams.

0.9

1.0

8/2003

9/2003

Changed the USB description to full-/low-speed compatible.

Added the DSP information in the Features list.

Put a new sentence under Mechanical Dimensions.

Fixed table formatting.

Nontechnical edits.

Released to the external web.

1.1

10/2003

Added TDMb to the MPC875 Features list, the MPC875 Block Diagram, added 13.5

Serial Interface AC Electrical Specifications, and removed TDMa from the pin

descriptions.

MPC875/MPC870 Hardware Specifications, Rev. 3.0

82

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Freescale Semiconductor

Document Revision History

Table 37. Document Revision History (continued)

Changes

Revision

Number

Date

2.0

12/2003

Changed DBGC in the Mandatory Reset Configuration to X1.

Changed the maximum operating frequency to 133 MHz.

Put the timing in the 80 MHz column.

Put in the orderable part numbers.

Rounded the timings to hundredths in the 80 MHz column.

Put the pin numbers in footnotes by the maximum currents in Table 6.

Changed 22 and 41 in the Timing.

Put TBD in the Thermal table.

3.0

1/07/2004

7/19/2004

• Added sentence to Spec B1A about EXTCLK and CLKOUT being in Alignment for

Integer Values

• Added a footnote to Spec 41 specifying that EDM = 1

• Added the thermal numbers to Table 4.

• Added RMII1_EN under M1II_EN in Table 36 Pin Assignments

• Added a tablefootnote to Table 6 DC Electrical Specifications about meeting the VIL

Max of the I2C Standard

• Put the new part numbers in the Ordering Information Section

MPC875/MPC870 Hardware Specifications, Rev. 3.0

Freescale Semiconductor

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

83

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MPC875EC

Rev. 3.0

07/2004

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE


型号：	MPC870ZT66
厂家：	Freescale
描述：	Hardware Specifications 硬件规格
文件：	总84页 (文件大小：1372K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MPC870ZT66 [FREESCALE]

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