MPC9850 [FREESCALE]
Clock Generator for PowerQUICC III; 时钟发生器为PowerQUICC III
| 型号： | MPC9850 |
| 厂家： | 
Freescale |
| 描述： | Clock Generator for PowerQUICC III |
| 文件： | 总12页 (文件大小：244K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MPC9850
Rev 5, 4/2005
Freescale Semiconductor
Technical Data
Clock Generator for PowerQUICC III
MPC9850
The MPC9850 is a PLL based clock generator specifically designed for
Freescale Microprocessor and Microcontroller applications including the
PowerQUICC III. This device generates a microprocessor input clock plus the
500 MHz Rapid I/O clock. The microprocessor clock is selectable in output
frequency to any of the commonly used microprocessor input and bus
frequencies. The Rapid I/O outputs are LVDS compatible. The device offers eight
low skew clock outputs organized into two output banks, each configurable to
support different clock frequencies. The extended temperature range of the
MPC9850 supports telecommunication and networking requirements.
MICROPROCESSOR
CLOCK GENERATOR
Features
•
•
•
•
•
8 LVCMOS outputs for processor and other circuitry
2 differential LVDS outputs for Rapid I/O interface
Crystal oscillator or external reference input
25 or 33 MHz Input reference frequency
Selectable output frequencies include = 200, 166, 133,125, 111, 100, 83, 66,
50, 33 or 16 MHz
VF SUFFIX
VM SUFFIX (PB-FREE)
100 MAPBGA PACKAGE
CASE 1462-01
•
•
•
•
•
•
•
•
Buffered reference clock output
Rapid I/O (LVDS) Output = 500, 250 or 125 MHz
Low cycle-to-cycle and period jitter
100-lead PBGA package
100-lead Pb-free Package Available
3.3V supply with 3.3V or 2.5V output LVCMOS drive
Supports computing, networking, telecommunications applications
Ambient temperature range –40°C to +85°C
Functional Description
The MPC9850 uses either a 25 or 33 MHz reference frequency to generate 8 LVCMOS output clocks, of which, the frequency
is selectable from 16 MHz to 200 MHz. The reference is applied to the input of a PLL and multiplied to 2 GHz. Output dividers,
divide this frequency by 10, 12, 15, 16, 18, 20, 24, 30, 40, 60 or 120 to produce output frequencies of 200, 166, 133, 125, 111,
100, 83 66 50 33 or 16 MHz. The single-ended LVCMOS outputs are divided into two banks of 4 low skew outputs each, for use
in driving a microprocessor or microcontroller clock input as well as other system components. The 2 GHz PLL output frequency
is also divided to produce a 125, 250 or 500 MHz clock output for Rapid I/O applications such as found on the PowerQUICC III
communications processor. The input reference, either crystal or external input is also buffered to a separate output that my be
used as the clock source for a Gigabit Ethernet PHY if desired.
The reference clock may be provided by either an external clock input of 25 MHz or 33 MHz. An internal oscillator requiring a
25 MHz crystal for frequency control may also be used. The external clock source my be applied to either of two clock inputs and
selected via the CLK_SEL control input. Both single ended LVCMOS and differential LVPECL inputs are available. The crystal
oscillator or external clock input is selected via the input pin of REF_SEL. Other than the crystal, no external components are
required for crystal oscillator operation. The REF_33MHz configuration pins is used to select between a 33 and 25 MHz input
frequency.
The MPC9850 is packaged in a 100 lead MAPBGA package to optimize both performance and board density.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
0
1
CLK
1
0
0
1
PCLK
PCLK
÷N
QA0
QA1
Ref
REF_CLK_SEL
PLL
2000 MHz
XTAL_IN
XTAL_OUT
REF_SEL
QA2
QA3
OSC
÷N
QB0
QB1
PLL_BYPASS
REF_33MHz
QB2
QB3
÷4, 8, 16, 40
QC0
QC0
CLK_A[0:5]
CLK_B[0:5]
RIO_C[0:1]
QC1
QC1
MR
REF_OUT
Figure 1. MPC9850 Logic Diagram
Function
Table 1. Pin Configurations
Pin
I/O
Input
Input
Type
Supply Active/State
CLK
PCLK, PCLK
LVCMOS PLL Reference Clock Input (pull-down)
V
DD
DD
LVPECL
PLL Reference Clock Input (PCLK - pull-down, PCLK - pull-up and
pull-down)
V
QA0, QA1, QA2, QA3 Output
QB0, QB1, QB2, QB3 Output
LVCMOS Bank A Outputs
LVCMOS Bank B Outputs
V
V
V
DDOA
DDOB
DDOC
QC0, QC1, QC0,
QC1
Output
LVDS
Bank C Outputs
REF_OUT
XTAL_IN
Output
Input
Output
Input
Input
Input
Input
Input
Input
Input
Input
LVCMOS Reference Output (25 MHz or 33 MHz)
LVCMOS Crystal Oscillator Input Pin
V
V
V
V
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
XTAL_OUT
REF_CLK_SEL
REF_SEL
REF_33MHz
MR
LVCMOS Crystal Oscillator Output Pin
LVCMOS Select between CLK and PCLK Input (pull-down)
High
High
High
Low
LVCMOS Select between External Input and Crystal Oscillator Input (pull-down) V
LVCMOS Selects 33 MHz Input (pull-down)
LVCMOS Master Reset (pull-up)
LVCMOS Select PLL or static test mode (pull-down)
LVCMOS Configures Bank A clock output frequency (pull-up)
LVCMOS Configures Bank B clock output frequency (pull-up)
LVCMOS Configures Bank C clock output frequency (pull-down)
3.3 V Supply
V
V
V
V
V
V
PLL_BYPASS
High
High
High
(1)
CLK_A[0:5]
(2)
CLK_B[0:5]
RIO_C [0:1]
V
V
V
V
V
DD
Analog Supply
DDA
Supply for Output Bank A
DDOA
DDOB
DDOC
Supply for Output Bank B
Supply for Output Bank C
GND
Ground
1. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb)
2. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb)
PowerPC bit ordering (bit 0 = msb, bit 1 = lsb)
MPC9850
Advanced Clock Drivers Devices
Freescale Semiconductor
2
Table 2. Function Table
Control
REF_CLK_SEL
REF_SEL
Default
0
CLK
1
0
0
0
0
1
PCLK
XTAL
CLK or PCLK
Normal
PLL_BYPASS
REF_33MHz
MR
Bypass
Selects 25 MHz Reference
Reset
Selects 33 MHz Reference
Normal
CLK_A, CLK_B, and RIO_C control output frequencies. See Table 3 and Table 4 for specific device configuration
Table 3. Output Configurations (Banks A & B)
CLK_x[0]
(msb)
CLK_x[5]
(lsb)
Frequency
(MHz)
(1)
CLK_x[1]
CLK_x[2]
CLK_x[3]
CLK_x[4]
N
CLK_x[0:5]
111111
111100
101000
011110
010100
001111
001100
001010
001001
001000
000111
000110
000101
000100
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
1
1
1
0
0
0
0
1
1
0
1
1
1
1
0
0
0
1
1
1
1
1
0
0
1
0
1
0
1
0
0
1
1
0
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
126
120
80
60
40
30
24
20
18
16
15
12
10
15.87
16.67
25.00
33.33
50.00
66.67
83.33
100.00
111.11
125.00
133.33
166.67
200.00
250
(2)
8
1. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb)
2. Minimum value for N
Table 4. Output Configurations (Bank C)
RIO_C[0:1]
Frequency (MHz)
50 (test output)
00
01
10
11
125
250
500
MPC9850
Advanced Clock Drivers Devices
Freescale Semiconductor
3
OPERATION INFORMATION
CLK_x[0:5]. To achieve N = 15 CLK_x[0:5] is configured to
Output Frequency Configuration
00111 or 7.
The MPC9850 was designed to provide the commonly
used frequencies in PowerQUICC, PowerPC and other
microprocessor systems. Table 3 lists the configuration
values that will generate those common frequencies. The
MPC9850 can generate numerous other frequencies that
may be useful in specific applications. The output frequency
(fout) of either Bank A or Bank B may be calculated by the
following equation.
Crystal Input Operation
TBD
Power-Up and MR Operation
Figure 2 defines the release time and the minimum pulse
length for MR pin. The MR release time is based upon the
power supply being stable and within VDD specifications. See
Table 11 for actual parameter values. The MPC9850 may be
configured after release of reset and the outputs will be stable
for use after lock indication is obtained.
fout = 2000 / N
where fout is in MHz and N = 2 * CLK_x[0:5]
This calculation is valid for all values of N from 8 to 126.
Note that N = 15 is a modified case of the configuration inputs
V
DD
MR
t
t
reset_pulse
reset_rel
Figure 2. MR Operation
Power Supply Bypassing
The MPC9850 is a mixed analog/digital product. The
architecture of the MPC9850 supports low noise signal
operation at high frequencies. In order to maintain its superior
signal quality, all VDD pins should be bypassed by
high-frequency ceramic capacitors connected to GND. If the
spectral frequencies of the internally generated switching
noise on the supply pins cross the series resonant point of an
individual bypass capacitor, its overall impedance begins to
look inductive and thus increases with increasing frequency.
The parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the noise bandwidth.
V
V
V
DD
DD
22 µF
0.1 µF
0.1 µF
MPC9850
15 Ω
DDA
Figure 3. VCC Power Supply Bypass
MPC9850
Advanced Clock Drivers Devices
Freescale Semiconductor
4
Table 5. Absolute Maximum Ratings(1)
Symbol
Characteristics
Supply Voltage (core)
Min
–0.3
–0.3
–0.3
–0.3
–0.3
Max
Unit
V
Condition
V
3.8
DD
V
Supply Voltage (Analog Supply Voltage)
Supply Voltage (LVCMOS output for Bank A or B)
DC Input Voltage
V
V
V
DDA
DD
DD
V
V
DDOx
V
V
+0.3
V
IN
DD
(2)
V
DC Output Voltage
V
+0.3
V
OUT
DDx
I
DC Input Current
±20
mA
mA
°C
IN
I
DC Output Current
Storage Temperature
±50
OUT
T
–65
125
S
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
2. V
references power supply pin associated with specific output pin.
DDx
Table 6. General Specifications
Symbol
Characteristics
Min
Typ
Max
Unit
V
Condition
V
Output Termination Voltage
ESD Protection (Human Body Model)
ESD Protection (Charged Device Model)
Latch-Up Immunity
V
DD ÷ 2
TT
HBM
CDM
LU
2000
500
V
V
100
mA
pF
pF
C
Input Capacitance
4
Inputs
Per Output
IN
PD
JA
C
Power Dissipation Capacitance
Thermal Resistance (junction-to-ambient)
Ambient Temperature
10
θ
54.5
°C/W Air flow = 0
°C
T
–40
85
A
Table 7. DC Characteristics (TA = –40°C to 85°C)
Symbol
Characteristics Min
= 3.3 V ± 5 and V = 3.3 V ± 5%
DDOB
Typ
Max
Unit
Condition
Supply Current for V = 3.3 V ± 5%, V
DD
DDOA
I
+ I
Maximum Quiescent Supply Current (Core)
200
mA
V
+ V
DD DDA
DD
DDA
pins
I
Maximum Quiescent Supply Current (Analog Supply)
Maximum Bank A and B Supply Current
15
mA
mA
V
pins
DDIN
DDA
I
I
,
175
V
V
and
pins
DDOA
DDOA
DDOB
DDOB
Supply Current for V = 3.3 V ± 5%, V
= 2.5 V ± 5% and V
= 2.5 V ± 5%
DDOB
DD
DDOA
I
+ I
Maximum Quiescent Supply Current (Core)
200
mA
V
+ V
DD DDA
DD
DDA
pins
I
Maximum Quiescent Supply Current (Analog Supply)
Maximum Bank A and B Supply Current
15
mA
mA
V
pins
DDA
DDIN
I
I
,
100
V
V
and
pins
DDOA
DDOA
DDOB
DDOB
MPC9850
Advanced Clock Drivers Devices
Freescale Semiconductor
5
Table 8. LVDS DC Characteristics (TA = –40°C to 85°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Differential LVDS Clock Outputs (QC0, QC0 and QC1, QC1) for V = 3.3 V ± 5%
DD
(1)
V
Output Differential Voltage (peak-to-peak)
Output Offset Voltage
(LVDS)
(LVDS)
100
400
mV
mV
PP
OS
V
1050
1600
1. V is the minimum differential input voltage swing required to maintain AC characteristics including t and device-to-device skew.
PP
PD
Table 9. LVPECL DC Characteristics (TA = –40°C to 85°C)(1)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Differential LVPECL Clock Inputs (CLK1, CLK1) for V = 3.3 V ± 0.5%
DD
(2)
V
Differential Voltage (peak-to-peak)
(LVPECL)
(LVPECL)
250
1.0
mV
V
PP
(3)
V
Differential Input Crosspoint Voltage
V
– 0.6
DD
CMR
1. AC characteristics are design targets and pending characterization.
2. V is the minimum differential input voltage swing required to maintain AC characteristics including t and device-to-device skew.
PP
PD
3. V
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
(AC)
CMR
CMR
range and the input swing lies within the V (AC) specification. Violation of V
(AC) or V (AC) impacts the device propagation delay,
PP
PP
CMR
device and part-to-part skew.
Table 10. LVCMOS I/O DC Characteristics (TA = –40°C to 85°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
LVCMOS for V = 3.3 V ± 5%
DD
V
Input High Voltage
Input Low Voltage
2.0
V
+ 0.3
DD
V
V
LVCMOS
LVCMOS
IH
V
I
0.8
IL
(1)
Input Current
± 200
µA
V
= V
or GND
IN
IN
DDL
LVCMOS for V = 3.3 V ±5%, V
= 3.3 V ± 5 and V
= 3.3 V ± 5%
DD
DDOA
DDOB
V
Output High Voltage
Output Low Voltage
Output Impedance
2.4
V
V
Ω
I
I
= –24 mA
= 24 mA
OH
OH
V
0.5
0.4
OL
OL
Z
14 – 17
18 – 22
OUT
LVCMOS for V = 3.3 V ±5%, V
= 2.5 V ± 5% and V = 2.5 V ± 5%
DDOB
DD
DDOA
V
Output High Voltage
Output Low Voltage
Output Impedance
1.9
V
V
Ω
I
I
= –15 mA
= 15 mA
OH
OH
V
OL
OL
Z
OUT
1. Inputs have pull-down resistors affecting the input current.
MPC9850
Advanced Clock Drivers Devices
Freescale Semiconductor
6
Table 11. AC Characteristics (VDD = 3.3 V ± 5%, VDDOA = 3.3 V ± 5%,VDDOB = 3.3 V ± 5%, TA= –40°C to +85°C)(1) (2)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Input and Output Timing Specification
f
Input Reference Frequency (25 MHz input)
Input Reference Frequency (33 MHz input)
XTAL Input
25
33
25
MHz
MHz
MHz
MHz
ref
(3)
Input Reference Frequency in PLL Bypass Mode
250
PLL bypass
PLL locked
(4)
f
VCO Frequency Range
2000
MHz
VCO
f
Output Frequency
Bank A output
Bank B output
Bank C output
15.87
15.87
50
200
200
500
MHz
MHz
MHz
MCX
f
Reference Input Pulse Width
Input Frequency Accuracy
Output Rise/Fall Time
Output Duty Cycle
2
ns
ppm
ps
refPW
f
100
500
refCcc
t , t
150
20% to 80%
r
f
DC
43
47
50
50
57
53
%
Bank A and B
Bank C
PLL Specifications
t
Maximum PLL Lock Time
MR Hold Time on Power Up
MR Hold Time
10
ms
ns
ns
LOCK
t
10
10
reset_ref
t
reset_pulse
Skew and Jitter Specifications
t
t
Output-to-Output Skew (within a bank)
50
ps
ps
sk(O)
sk(O)
Output-to-Output Skew (across banks A and B)
400
V
V
= 3.3 V
= 3.3 V
DDOA
DDOB
t
Cycle-to-Cycle Jitter
200
150
ps
ps
Bank A and B
Bank C
JIT(CC)
t
Period Jitter
200
50
ps
ps
Bank A and C
Bank A and C
JIT(PER)
t
I/O Phase Jitter
RMS (1 σ)
JIT(∅)
1. AC characteristics are design targets and pending characterization.
2. AC characteristics apply for parallel output termination of 50Ω to V
.
TT
3. In bypass mode, the MPC9850 divides the input reference clock.
4. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: f = (f
÷ M) ⋅ N.
VCO
ref
Z
= 50Ω
O
Pulse
Z
= 50Ω
O
Generator
Z = 50Ω
R = 100Ω
T
DUT MPC9850
R = 50Ω
T
V
TT
Figure 4. MPC9850 AC Test Reference (LVDS Outputs)
Z
= 50Ω
Z
= 50Ω
Pulse
O
O
Generator
Z = 50Ω
DUT MPC9850
R = 50Ω
R = 50Ω
T
T
V
V
TT
TT
Figure 5. MPC9850 AC Test Reference (LVCMOS Outputs)
MPC9850
Advanced Clock Drivers Devices
Freescale Semiconductor
7
Table 12. MPC9850 Pin Diagram (Top View)
1
2
3
4
5
6
7
8
9
10
V
V
V
V
CLKA[1] CLKA[3] CLKA[5]
CLKA[0] CLKA[2] CLKA[4]
V
QA1
QA2
V
V
V
V
A
B
C
D
E
F
DDOA
DDOA
DDOA
DD
DDOA
DDOA
DDOA
QA0
V
QA3
DDOA
DDOA
DDOA
RSVD
RSVD
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DD
REF_OUT
QC0
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
V
V
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
QC0
DDA
DDA
REF_SEL
PCLK
CLK
V
GND
DDOC
PCLK
QC1
QC1
REF_CLK_SEL REF_33MHz
XTAL_IN XTAL_OUT
PLL_BYPASS
RIO_C[1]
MR
G
H
J
V
V
V
V
DD
RIO_C[0]
DD
DD
DD
V
V
V
V
CLKB[0] CLKB[2] CLKB[4]
CLKB[1] CLKB[3] CLKB[5]
QB0
V
QB3
QB2
V
V
V
V
DDOB
DDOB
DDOB
DDOB
DDOB
DDOB
DDOB
DDOB
DDOB
V
QB1
K
DD
Table 13. MPC9850 Pin List
100 Pin
100 Pin
MAPBGA
100 Pin
MAPBGA
100 Pin
MAPBGA
100 Pin
MAPBGA
Signal
Signal
Signal
Signal
Signal
MAPBGA
(1)
V
V
A1
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
REF_SEL
CLK
E1
REF_CLK_SEL
REF_33MHz
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
V
V
J1
J2
DDOA
RSVD
RSVD
DDOB
DDOB
(1)
A2
A3
A4
A5
A6
A7
A8
A9
A10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
E2
E3
E4
E5
E6
E7
E8
E9
E10
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
DDOA
CLKA[1]
CLKA[3]
CLKA[5]
V
V
V
V
V
V
V
V
V
DD
CLKB[0]
CLKB[2]
CLKB[4]
QB0
J3
DD
DD
DD
DD
DD
DD
DD
DD
GND
GND
GND
GND
GND
GND
GND
GND
J4
J5
V
J6
DD
QA1
QA2
V
J7
DDOB
V
V
QB3
J8
DD
DD
V
V
PLL_BYPASS
MR
V
J9
DDOA
DDOA
DDOA
DDOA
DDOC
DDOB
DDOB
DDOB
DDOB
V
V
V
REF_OUT
GND
V
V
V
J10
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
V
V
PCLK
PCLK
XTAL_IN
XTAL_OUT
DDA
DDA
CLKA[0]
CLKA[2]
CLKA[4]
QA0
V
V
V
V
V
V
V
V
CLKB[1]
CLKB[3]
CLKB[5]
DD
DD
DD
DD
DD
DD
DD
DD
GND
GND
GND
GND
GND
GND
GND
GND
V
DD
V
QB1
QB2
DDOA
QA3
V
V
DD
DD
V
QC0
QC0
QC1
QC1
RIO_C[1]
RIO_C[0]
V
DDOA
DDOA
DDOB
DDOB
V
V
1. RSVD pins must be left open.
MPC9850
Advanced Clock Drivers Devices
Freescale Semiconductor
8
PACKAGE DIMENSIONS
B
C
11
A1 INDEX
AREA
K
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
3. MAXIMUM SOLDER BALL DIAMETER MEASURED
PARALLEL TO DATUM A.
11
4. DATUM A, SEATING PLANE, IS DEFINED BY THE
SPHERICAL CROWNS OF THE SOLDER BALLS.
5. PARALLELISM MEASUREMENT SHALL EXCLUDE
ANY EFFECT OF MARK ON TOP SURFACE OF
PACKAGING.
4X
0.2
TOP VIEW
SIDE VIEW
9X
1
0.5
5
0.35
A
K
J
(1.18)
H
G
F
9X
1
1.7 MAX
E
D
C
B
A
0.43
0.29
100X
SEATING
PLANE
4
A
0.12
A
0.5
0.55
0.45
3
100X
DETAIL K
ROTATED 90˚ CLOCKWISE
M
M
0.25
A B C
1
2
3
4
5
6
7
8
9
10
A1 INDEX
AREA
0.10
A
BOTTOM VIEW
VA SUFFIX
VM SUFFIX (PB-FREE)
100 MAPBGA PACKAGE
CASE 1462-01
ISSUE O
MPC9850
Advanced Clock Drivers Devices
Freescale Semiconductor
9
NOTES
MPC9850
Advanced Clock Drivers Devices
Freescale Semiconductor
10
NOTES
MPC9850
Advanced Clock Drivers Devices
Freescale Semiconductor
11
How to Reach Us:
Home Page:
www.freescale.com
E-mail:
support@freescale.com
USA/Europe or Locations Not Listed:
Freescale Semiconductor
Technical Information Center, CH370
1300 N. Alma School Road
Chandler, Arizona 85224
+1-800-521-6274 or +1-480-768-2130
support@freescale.com
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
support@freescale.com
Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
Freescale Semiconductor reserves the right to make changes without further notice to
any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor assume any liability arising out of the application or use of any
product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters that may be
provided in Freescale Semiconductor data sheets and/or specifications can and do vary
in different applications and actual performance may vary over time. All operating
parameters, including “Typicals”, must be validated for each customer application by
customer’s technical experts. Freescale Semiconductor does not convey any license
under its patent rights nor the rights of others. Freescale Semiconductor products are
not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Freescale Semiconductor product
could create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Freescale
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064
Japan
0120 191014 or +81 3 5437 9125
support.japan@freescale.com
Asia/Pacific:
Freescale Semiconductor Hong Kong Ltd.
Technical Information Center
2 Dai King Street
Tai Po Industrial Estate
Tai Po, N.T., Hong Kong
+800 2666 8080
support.asia@freescale.com
For Literature Requests Only:
Freescale Semiconductor Literature Distribution Center
P.O. Box 5405
Semiconductor was negligent regarding the design or manufacture of the part.
Denver, Colorado 80217
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
All other product or service names are the property of their respective owners.
1-800-441-2447 or 303-675-2140
Fax: 303-675-2150
© Freescale Semiconductor, Inc. 2005. All rights reserved.
LDCForFreescaleSemiconductor@hibbertgroup.com
MPC9850
Rev. 5
4/2005
相关型号：
MPC9855VM
200MHz, PROC SPECIFIC CLOCK GENERATOR, PBGA100, 11 X 11 MM, 1 MM PITCH, LEAD FREE, MAPBGA-100
NXP
MPC9855VMR2
Processor Specific Clock Generator, 200MHz, PBGA100, 11 X 11 MM, 1 MM PITCH, LEAD FREE, MAPBGA-100
IDT
©2020 ICPDF网 联系我们和版权申明