MPC9855VF [NXP]
200MHz, PROC SPECIFIC CLOCK GENERATOR, PBGA100, 11 X 11 MM, 1 MM PITCH, MAPBGA-100;
| 型号： | MPC9855VF |
| 厂家： | 
NXP |
| 描述： | 200MHz, PROC SPECIFIC CLOCK GENERATOR, PBGA100, 11 X 11 MM, 1 MM PITCH, MAPBGA-100 时钟 外围集成电路 晶体 |
| 文件： | 总12页 (文件大小：260K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MPC9855
Rev 4, 09/2005
Freescale Semiconductor
Technical Data
Clock Generator for PowerQUICC III
MPC9855
The MPC9855 is a PLL based clock generator specifically designed for
Freescale Microprocessor and Microcontroller applications including the
PowerPC and PowerQUICC. This device generates a microprocessor input
clock. The microprocessor clock is selectable in output frequency to any of the
commonly used microprocessor input and bus frequencies. The device offers
eight low skew clock outputs in two banks, each configurable to support different
clock frequencies. The extended temperature range of the MPC9855 supports
telecommunication and networking requirements.
MICROPROCESSOR
CLOCK GENERATOR
Features
•
•
•
•
8 LVCMOS outputs for processor and other circuitry
Crystal oscillator or external reference input
25 or 33 MHz Input reference frequency
Selectable output frequencies include = 200, 166, 133,125, 111, 100, 83, 66,
50, 33, or 16 MHz
•
•
•
•
•
•
•
Buffered reference clock output (2 copies)
Low cycle-to-cycle and period jitter
VF SUFFIX
VM SUFFIX (PB-FREE)
100 MAPBGA PACKAGE
CASE 1462-01
100-lead PBGA package
100-lead Pb-free Package Available
3.3 V supply with 3.3 V or 2.5 V LVCMOS output supplies
Supports computing, networking, telecommunications applications
Ambient temperature range –40°C to +85°C
Functional Description
The MPC9855 uses either a 25 or 33 MHz reference frequency to generate 8 LVCMOS output clocks, of which, the frequency
is selectable from 16 MHz to 200 MHz. The reference is applied to the input of a PLL and multiplied to 2 GHz. Output dividers,
divide this frequency by 10, 12, 15, 16, 18, 20, 24, 30, 40, 60, or 120 to produce output frequencies of 200, 166, 133, 125, 111,
100, 83, 66, 50, 33, or 16 MHz. The single-ended LVCMOS outputs provide 8 low skew outputs for use in driving a microprocessor
or microcontroller clock input as well as other system components. The input reference, either crystal or external input is also
buffered to a separate dual outputs that my be used as the clock source for a Ethernet PHY if desired.
The reference clock may be provided by either an external clock input of 25 or 33 MHz. An internal oscillator requiring a
25 MHz crystal for frequency control may also be used. The external clock source my be applied to either of two clock inputs and
selected via the CLK_SEL control input. Both single ended LVCMOS and differential LVPECL inputs are available. The crystal
oscillator or external clock input is selected via the input pin of XTAL_SEL. Other than the crystal, no external components are
required for crystal oscillator operation. The REF_33 MHz configuration pin is used to select between a 33 and 25 MHz input
frequency.
The MPC9855 is packaged in a 100 lead MAPBGA package to optimize both performance and board density.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
CLK
0
1
1
0
0
1
PCLK
PCLK
÷N
QA0
QA1
Ref
CLK_SEL
PLL
XTAL_IN
XTAL_OUT
XTAL_SEL
2000 MHz
QA2
QA3
OSC
÷N
QB0
QB1
PLL_BYPASS
REF_33 MHz
QB2
QB3
CLK_A[0:5]
CLK_B[0:5]
REF_OUT0
REF_OUT1
MR
REF_OUT1_E
Figure 1. MPC9855 Logic Diagram
MPC9855
Advanced Clock Drivers Devices
Freescale Semiconductor
2
Table 1. Pin Configurations
Pin
I/O
Type
Function
Supply
Active/State
CLK
Input
LVCMOS PLL Reference Clock Input (pull-down)
VDD
PCLK, PCLK
Input
LVPECL PLL reference clock input
V
—
—
—
—
DD
(PCLK — pull-down, PCLK — pull-up and pull-down)
QA0, QA1,
QA2, QA3
Output LVCMOS Clock Outputs
V
V
DDOA
DDOB
QB0, QB1,
QB2, QB3
Output LVCMOS Clock Outputs
REF_OUT0
REF_OUT1
Output LVCMOS Reference Output (25 MHz or 33 MHz)
V
DD
XTAL_IN
Input
LVCMOS Crystal Oscillator Input Pin
V
V
V
V
—
—
DD
DD
DD
DD
XTAL_OUT
CLK_SEL
XTAL_SEL
Output LVCMOS Crystal Oscillator Output Pin
Input
Input
LVCMOS Select between CLK and PCLK input (pull-down)
High
High
LVCMOS Select between External Input and Crystal Oscillator Input
(pull-down)
REF_33 MHz
REF_OUT1_E
MR
Input
Input
Input
Input
Input
Input
—
LVCMOS Selects 33MHz input (pull-down)
V
V
V
V
V
V
High
High
Low
High
—
DD
DD
DD
DD
DD
DD
LVCMOS Enables REF_OUT1 output (pull-down)
LVCMOS Master Reset (pull-up)
PLL_BYPASS
LVCMOS Select PLL or static test mode (pull-down)
LVCMOS Configures Bank A clock output frequency (pull-up)
LVCMOS Configures Bank B clock output frequency (pull-up)
CLK_A[0:5](1)
CLK_B[0:5](2)
—
V
—
—
—
—
—
3.3 V Supply
—
—
—
—
—
—
DD
V
V
V
—
Analog Supply
—
DDA
—
Output Supply — Bank A
Output Supply — Bank B
Ground
—
DDOA
DDOB
—
—
GND
—
—
1. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb)
2. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb)
Table 2. Function Table
Control
CLK_SEL
Default
0
1
0
0
0
0
0
1
CLK
CLKx
PCLK
XTAL
XTAL_SEL
PLL_BYPASS
REF_OUT1_E
REF_33 MHz
MR
Normal
Bypass
Disables REF_OUT1
Selects 25 MHz Reference
Reset
Enables REF_OUT1
Selects 33 MHz Reference
Normal
CLK_A and CLK_B control output frequencies. See Table 3 for specific device configuration
MPC9855
Advanced Clock Drivers Devices
Freescale Semiconductor
3
Table 3. Output Configurations (Banks A & B)
CLK_x[0]
CLK_x[5]
(lsb)
Frequency
(MHz)
CLK_x[0:5](1)
CLK_x[1]
CLK_x[2]
CLK_x[3]
CLK_x[4]
N
(msb)
111111
111100
101000
011110
010100
001111
001100
001010
001001
001000
000111
000110
000101
000100
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
1
1
1
0
0
0
0
1
1
0
1
1
1
1
0
0
0
1
1
1
1
1
0
0
1
0
1
0
1
0
0
1
1
0
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
126
120
80
60
40
30
24
20
18
16
15
12
10
15.87
16.67
25.00
33.33
50.00
66.67
83.33
100.00
111.11
125.00
133.33
166.67
200.00
250
8(2)
1. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb)
2. Minimum value for N
MPC9855
Advanced Clock Drivers Devices
Freescale Semiconductor
4
OPERATION INFORMATION
CLK_x[0:5]. To achieve N = 15 CLK_x[0:5] is configured to
Output Frequency Configuration
00111 or 7.
The MPC9855 was designed to provide the commonly
used frequencies in PowerQUICC, PowerPC and other
microprocessor systems. Table 3 lists the configuration
values that will generate those common frequencies. The
MPC9855 can generate numerous other frequencies that
may be useful in specific applications. The output frequency
(fout) of either Bank A or Bank B may be calculated by the
following equation.
Crystal Input Operation
TBD
Power-Up and MR Operation
Figure 2 defines the release time and the minimum pulse
length for MR pin. The MR release time is based upon the
power supply being stable and within VDD specifications. See
Table 9 for actual parameter values. The MPC9855 may be
configured after release of reset and the outputs will be stable
for use after lock is obtained.
fout = 2000 / N
where fout is in MHz and N = 2 * CLK_x[0:5]
This calculation is valid for all values of N from 8 to 126.
Note that N = 15 is a modified case of the configuration inputs
VDD
MR
treset_rel
treset_pulse
Figure 2. MR Operation
Power Supply Bypassing
Power Consumption Calculation
The MPC9855 is a mixed analog/digital product. The
architecture of the MPC9855 supports low noise signal
operation at high frequencies. In order to maintain its superior
signal quality, all VDD pins should be bypassed by
high-frequency ceramic capacitors connected to GND. If the
spectral frequencies of the internally generated switching
noise on the supply pins cross the series resonant point of an
individual bypass capacitor, its overall impedance begins to
look inductive and thus increases with increasing frequency.
The parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the noise bandwidth.
For unloaded outputs the power consumption of the
MPC9855 can be calculated as follows.
P = VDD * IDDBASE + nA * (VDDOA ** 2 * CPD * fA)
+ nB * (VDDOB ** 2 * CPD * fB)
where
VDD = core supply voltage
IDDBASE = base supply current
nA = number of A bank outputs (= 4)
nB = number of B bank outputs (= 4)
VDDOA = voltage supply on bank A outputs
VDDOB = voltage supply on bank B outputs
CPD = power dissipation capacitance
fA = frequency of bank A outputs
fB = frequency of bank B outputs
VDD
VDD
22 µF
15 Ω
0.1 µF
0.1 µF
MPC9855
VDDA
Figure 3. VCC Power Supply Bypass
MPC9855
Advanced Clock Drivers Devices
Freescale Semiconductor
5
Table 4. Absolute Maximum Ratings(1)
Symbol
Characteristics
Supply Voltage (core)
Min
Max
Unit
Condition
VDD
–0.3
3.8
V
VDDA
VDDOx
VIN
Supply Voltage (Analog Supply Voltage)
Supply Voltage (LVCMOS output for Bank A and B)
DC Input Voltage
–0.3
–0.3
–0.3
–0.3
VDD
VDD
V
V
VDD+0.3
VDDx+0.3
±20
V
DC Output Voltage(2)
DC Input Current
VOUT
IIN
IOUT
TS
V
mA
mA
°C
DC Output Current
±50
Storage Temperature
–65
125
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
2. VDDx references power supply pin associated with specific output pin.
Table 5. General Specifications
Symbol
VTT
Characteristics
Output Termination Voltage
Min
Typ
Max
Unit
V
Condition
VDD ÷ 2
HBM
CDM
LU
ESD Protection (Human Body Model)
ESD Protection (Charged Device Model)
Latch-Up Immunity
2000
500
V
V
100
mA
pF
pF
CIN
Input Capacitance
4
8
Inputs
Per Output
CPD
θJA
Power Dissipation Capacitance
Thermal Resistance (junction-to-ambient)
Ambient Temperature
54.5
°C/W Air flow = 0
°C
TA
–40
85
Table 6. DC Characteristics (TA = –40°C to 85°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Supply Current for VDD = 3.3 V ± 5%
IDDBASE Base Supply Current (Core)
135
170
15
mA
VDD + VDDA
pins, outputs
unloaded
IDDA
Maximum Supply Current (Analog Supply)
mA
VDDIN pins
MPC9855
Advanced Clock Drivers Devices
Freescale Semiconductor
6
Table 7. LVPECL DC Characteristics (TA = –40°C to 85°C)(1)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Differential LVPECL Clock Inputs (CLK1, CLK1) for VDD = 3.3 V ± 0.5%
Differential Voltage(2) (peak-to-peak)
Differential Input Crosspoint Voltage(3)
(LVPECL)
(LVPECL)
VPP
250
1.0
mV
V
VCMR
V
DD – 0.6
1. AC characteristics are design targets and pending characterization.
2. VPP is the minimum differential input voltage swing required to maintain AC characteristics including tPD and device-to-device skew.
3. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC)
range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay,
device and part-to-part skew.
Table 8. LVCMOS I/O DC Characteristics (TA = –40°C to 85°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
LVCMOS for VDD = 3.3 V ± 5%
VIH
VIL
IIN
Input High Voltage
Input Low Voltage
2.0
VDD + 0.3
0.8
V
V
LVCMOS
LVCMOS
IN = VDDL or GND
Input Current(1)
± 200
µA
V
LVCMOS for VDD = 3.3 V ± 5%, VDDOA = 3.3 V ± 5 and VDDOB = 3.3 V ± 5%
VOH
VOL
Output High Voltage
Output Low Voltage
Output Impedance
2.4
V
V
Ω
IOH = –24 mA
IOL = 24 mA
0.5
0.4
ZOUT
14 – 17
18 – 22
LVCMOS for VDD= 3.3 V ± 5%, VDDOA = 2.5 V ± 5% and VDDOB= 2.5 V ± 5%
VOH
VOL
Output High Voltage
Output Low Voltage
Output Impedance
1.9
V
V
Ω
IOH = –15 mA
IOL = 15 mA
ZOUT
1. Inputs have pull-down resistors affecting the input current.
MPC9855
Advanced Clock Drivers Devices
Freescale Semiconductor
7
Table 9. AC Characteristics (VDD = 3.3 V ± 5%, VDDOAB = 3.3 V ± 5%, TA= –40°C to +85°C)(1) (2)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Input and Output Timing Specification
fref
Input Reference Frequency (25 MHz input)
Input Reference Frequency (33 MHz input)
XTAL Input
Input Reference Frequency in PLL Bypass Mode(3)
VCO Frequency Range(4)
25
33
25
MHz
MHz
MHz
MHz
250
PLL bypass
PLL locked
fVCO
fMCX
2000
MHz
Output Frequency
Bank A output
Bank B output
15.87
15.87
200
200
MHz
MHz
frefPW
frefCcc
tr, tf
Reference Input Pulse Width
Input Frequency Accuracy
Output Rise/Fall Time
Output Duty Cycle
2
ns
ppm
ps
100
500
57
150
43
20% to 80%
DC
50
%
Bank A and B
PLL Specifications
tLOCK
treset_ref
treset_pulse
Maximum PLL Lock Time
10
ms
ns
ns
MR Hold Time on Power Up
MR Hold Time
10
10
Skew and Jitter Specifications
tsk(O) Output-to-Output Skew (within a bank)
tsk(O) Output-to-Output Skew (across banks A and B)
50
ps
ps
400
VDDOA = 3.3 V
VDDOB = 3.3 V
tJIT(CC)
tJIT(PER)
tJIT(∅)
tr, tf
Cycle-to-Cycle Jitter
Period Jitter
200
200
50
ps
ps
ps
ns
Bank A and B
Bank A and B
Bank A and B
20% to 80%
I/O Phase Jitter
RMS (1 σ)
Output Rise/Fall Time
TBD
1. AC characteristics are design targets and pending characterization.
2. AC characteristics apply for parallel output termination of 50Ω to VTT
3. In bypass mode, the MPC9855 divides the input reference clock.
.
4. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: fref = (fVCO ÷ M) ⋅ N.
ZO = 50Ω
ZO = 50Ω
Pulse
Generator
Z = 50Ω
DUT MPC9855
RT = 50Ω
VTT
RT = 50Ω
VTT
Figure 4. MPC9855 AC Test Reference (LVCMOS Outputs)
MPC9855
Advanced Clock Drivers Devices
Freescale Semiconductor
8
Table 10. MPC9855 Pin Diagram (Top View)
1
2
3
4
5
6
7
8
9
10
VDDOA
VDDOA
CLKA[1]
CLKA[3]
CLKA[5]
VDD
QA1
QA2
VDDOA
VDDOA
A
B
C
D
E
F
VDDOA
RSVD
VDDOA
RSVD
CLKA[0]
VDD
CLKA[2]
VDD
CLKA[4]
VDD
QA0
VDD
VDDOA
VDD
QA3
VDD
VDD
VDD
VDD
VDD
VDD
QB3
QB2
VDDOA
VDD
VDDOA
REF_OUT[0]
REF_OUT[1]
GND
VDDA
VDDA
VDD
GND
GND
GND
GND
GND
GND
VDD
GND
GND
GND
GND
VDD
RSVD
XTAL_SEL
PCLK
CLK
VDD
GND
GND
VDD
PCLK
VDD
GND
GND
RSVD
RSVD
CLK_SEL
XTAL_IN
VDDOB
REF_33MHz
XTAL_OUT
VDDOB
VDD
GND
GND
PLL_BYPASS
RSVD
MR
G
H
J
VDD
VDD
VDD
REF_OUT1E
VDDOB
CLKB[0]
CLKB[1]
CLKB[2]
CLKB[3]
CLKB[4]
CLKB[5]
QB0
VDD
VDDOB
QB1
VDDOB
VDDOB
VDDOB
VDDOB
VDDOB
K
Table 11. MPC9855 Pin List
100 Pin
100 Pin
MAPBGA
100 Pin
MAPBGA
100 Pin
MAPBGA
100 Pin
MAPBGA
Signal
Signal
Signal
Signal
Signal
MAPBGA
VDDOA
VDDOA
CLKA[1]
CLKA[3]
CLKA[5]
VDD
A1
RSVD
RSVD
VDD
C1
XTAL_SEL
CLK
E1
CLK_SEL
REF_33MHz
VDD
G1
VDDOB
VDDOB
J1
J2
A2
A3
A4
A5
A6
A7
A8
A9
A10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
C2
C3
C4
C5
C6
C7
C8
C9
C10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
E2
E3
E4
E5
E6
E7
E8
E9
E10
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
G2
G3
G4
G5
G6
G7
G8
G9
G10
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
VDD
CLKB[0]
CLKB[2]
CLKB[4]
QB0
J3
J4
VDD
GND
GND
GND
GND
VDD
GND
VDD
GND
J5
VDD
GND
J6
QA1
VDD
GND
VDDOB
QB3
J7
QA2
VDD
VDD
J8
VDDOA
VDDOA
VDDOA
VDDOA
CLKA[0]
CLKA[2]
CLKA[4]
QA0
VDD
VDD
PLL_BYPASS
MR
VDDOB
VDDOB
VDDOB
VDDOB
CLKB[1]
CLKB[3]
CLKB[5]
VDD
J9
REF_OUT[0]
VDDA
VDDA
VDD
GND
PCLK
PCLK
VDD
J10
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
XTAL_IN
XTAL_OUT
VDD
GND
GND
GND
GND
GND
VDD
VDD
GND
VDD
GND
VDD
VDDOA
QA3
GND
VDD
QB1
VDD
VDD
QB2
VDDOA
VDDOA
RSVD
REF_OUT[1]
RSVD
RSVD
RSVD
REF_OUT1E
VDDOB
VDDOB
MPC9855
Advanced Clock Drivers Devices
Freescale Semiconductor
9
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Advanced Clock Drivers Devices
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10
PACKAGE DIMENSIONS
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Advanced Clock Drivers Devices
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MPC9855
Rev. 4
09/2005
相关型号：
MPC9855VM
200MHz, PROC SPECIFIC CLOCK GENERATOR, PBGA100, 11 X 11 MM, 1 MM PITCH, LEAD FREE, MAPBGA-100
NXP
MPC9855VMR2
Processor Specific Clock Generator, 200MHz, PBGA100, 11 X 11 MM, 1 MM PITCH, LEAD FREE, MAPBGA-100
IDT
MPC9855VMR2
200MHz, PROC SPECIFIC CLOCK GENERATOR, PBGA100, 11 X 11 MM, 1 MM PITCH, LEAD FREE, MAPBGA-100
NXP
MPC9857DW
PLL Based Clock Driver, 9857 Series, 10 True Output(s), 0 Inverted Output(s), PDSO48, TSSOP-48
IDT
MPC9865VM
Clock Generator, 200MHz, PBGA100, 11 X 11 MM, 1 MM PITCH, LEAD FREE, MO-192DAC-1, MAPBGA-100
IDT
MPC9893AE
9893 SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48, 7 X 7 MM, LEAD FREE, LQFP-48
NXP
MPC9893FA
PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48, 7 X 7 MM, LQFP-48
MOTOROLA
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