PC33814AE [FREESCALE]
Two Cylinder Small Engine Control IC; 两缸小型发动机控制IC
| 型号： | PC33814AE |
| 厂家： | 
Freescale |
| 描述： | Two Cylinder Small Engine Control IC |
| 文件： | 总50页 (文件大小：2092K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MC33814
Rev. 1.0, 8/2012
Freescale Semiconductor
Product Preview
Two Cylinder Small Engine
Control IC
33814
TWO CYLINDER SMALL ENGINE
The 33814 is an engine control analog power IC intended for two cylinder
motorcycle and other small engine control applications. The IC consists of
six integrated low side drivers, three pre-drivers, a Variable Reluctance
Sensor (VRS) input circuit, a voltage pre-regulator using an external pass
transistor, and two 5 volt internal regulators, one for the microcontroller
unit (MCU) VCC supply, and one for use as a protected sensor supply.
Also included is an MCU reset control circuit with watchdog, an ISO 9141
K-Line interface for diagnostic communication and a Serial Peripheral
Interface (SPI). The six low side drivers are intended for driving two fuel
injectors, a lamp, two relays or other loads, and a tachometer. The pre-
drivers are intended to drive IGBT or MOSFET transistors to control
ignition coils, and a HEGO heater. The device is packaged in a 48 pin
LQFP-EP with an exposed pad.
CONTROL IC
98ASA00173D
AE SUFFIX (PB-FREE)
48-PIN LQFP-EP
Features:
• Operates over supply voltage range of 4.5 V VPWR 36 V
• Logic stability guaranteed down to 2.5 V
• Two fuel injector drivers - typical of 1.3 A each
Applications
• Two Ignition IGBT or general purpose gate pre-drivers
• One O2 sensor (HEGO) heater general purpose gate pre-driver
• Relay 1 driver, typically 2.0 A, can be used for fuel pump control
• Relay 2 driver, typically 1.0 A, can be used as power relay control
• Lamp driver, typically 1.0 A can also be used to drive an LED
• VPROT protected sensor supply tracks VCC +5.0 V regulator
• MCU reset generator - system integrity monitor (watchdog)
• VPP pre-regulator provides power for VCC and VPROT regulators
• Independent fault protection with all faults reported via the SPI
• ISO 9141 K-line interface for communicating diagnostic messages
• Start-up / shut-down control and power sequence logic
• Interfaces directly to MCU using a 5.0 V SPI and logic I/O
Small Engine Control for:
• Lawn Mowers
• Motor Scooters
• Small Motorcycles
• Lawn Trimmers
• Snow Blowers
• Chain Saws
• Gasoline-driven Electrical Generators
• Outboard Motors
• Differential / single-ended VRS conditioning circuit with auto/manual
selected thresholds and filter times with digital and tachometer outputs
.
MC33814
VBAT
5.0 V Sensor Supply
VBAT
Keyswitch
VBAT
KEYSW
VPROT
Relay 2
(Power)
ROUT2
MIL
VPWR
LAMPOUT
ROUT1
Relay 1
(Fuel Pump)
TACHOMETER
O2 Heater
TACHOUT
VPPREF
O2HFB
O2HOUT
MCU
VPPSENS
VCC
V
CC
+5.0 V
O2HSENSP
RESETB
RESETB
O2HSENSN
INJOUT1
VBAT
4
SPI
SPI
MRX
MTX
BATSW
RIN1
RIN2
IGNIN1
IGNIN2
INJIN1
INJIN2
VRSOUT
O2HIN
VRSP
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
Injectors
VBAT
INJOUT2
ISO9141
ISO9141
IGNFB1
IGNOUT1
IGNFB2
IGNOUT2
IGNSENSP
IGNSENSN
VBAT
VRSN
GND
Crankshaft VRS
Figure 1. 33814 Simplified Application Diagram
*This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2012. All rights reserved.
1
Orderable Parts
Table 1. Orderable Part Variations
Part Number (1)
Temperature (T )
Notes
Package
A
PC33814AE
-40 to 125 °C
48 LQFP-EP
Notes
1. To Order parts in Tape & Reel, add the R2 suffix to the part number.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
2
Table of Contents
1
2
3
Orderable Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2 Static Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3 Dynamic Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.4 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.5 Typical Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
General IC Functional Description and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1 Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2 MCU SPI Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.3 Functional Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.1 Package Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4
5
6
7
8
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Analog Integrated Circuit Device Data
Freescale Semiconductor
3
2
Internal Block Diagram
POR,
Over-voltage
Under-voltage
VPWR
Pre-
RESETB
PROT
VCC
VPP
Regulator
VPPREF
VPPSENS
+5.0 V
Tracking
Regulator
VCC
V
VCC
LOGIC CONTROL
+5.0 V
CSB
SI
SCLK
SO
Watchdog
Regulator
SPI INTERFACE
& REGISTERS
INJOUT1
Typical of all 6 Driver Outputs
O2HIN
INJIN1
INJOUT2
ROUT1
Gate Control
VClamp
75 µA
Current Limit
Temperature Limit
Short/Open
ROUT2
lLimit
INJIN2
IGNIN1
+
–
(1 of 6 shown)
LAMPOUT
RS
TACHOUT
INJGND1
INJGND2
SPI Control
Parallel Control
PARALLEL
CONTROL
RGND1
RGND2
IGNIN2
RIN1
VPWR
VAnalog
VLogic
V10.0 Analog
V2.5 Logic
RIN2
MRX
VCC
ISO9141
ISO9141
CONTROLLER
Bandgap
Bias
MTX
Pre-drivers
KEYSW
SLEEP/RUN
START LOGIC
IGNFB1
To ROUT2
Driver
Ignition 1
Ignition 2
IGNOUT1
BATSW
IGNFB2
IGNOUT2
Oscillator
lLimit
IGNSENSP
IGNSENSN
To Logic
Control
+
–
O2HFB
O2HOUT
O2 Heater
Divider
(SPI CONTROL)
V
CC
O2HSENSP
O2HSENSN
lLimit
+
–
To Logic
Control
(SPI)
Divide by “N”
N=1-32
+
–
VRSP
VRSN
To TACHOUT Driver
VRS CIRCUIT
VRSOUT
Note: All current sinks and sources
~50µA except where indicated
GND
Figure 2. Simplified Internal Block Diagram
33814
Analog Integrated Circuit Device Data
Freescale Semiconductor
4
3
Pin Connections
3.1
Pinout Diagram
Transparent Top View
48 47 46 45 44 43 42 41 40 39 38 37
1
36
35
34
33
32
31
30
29
28
27
26
25
O2HFB
O2HOUT
IGNSENSP
IGNSENSN
O2HSENSN
O2HSENSP
VRSOUT
VRSP
RIN1
2
RIN2
3
O2HIN
IGNIN1
IGNIN2
INJIN1
INJIN2
BATSW
MTX
4
5
6
7
8
9
VRSN
10
11
12
CSB
MRX
VPWR
TACHOUT
NC
SCLK
13 14 15 16 17 18 19 20 21 22 23 24
Figure 3. 33814 Pin Connections
3.2
Pin Definitions
Table 2. 33814 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 20.
Pin
Function
Pin
Pin Name
Formal Name
Description
Voltage feedback from drain of O2 Sensor Heater driver FET
1
O2HFB
Input
O2 Sensor Heater
Feedback Input
Pre-driver output for O2 Sensor Heater driven by SPI input or O2HIN pin
2
3
O2HOUT
Output
Input
O2 Sensor Heater
Output
Positive input to the ignition current sense differential amplifier
IGNSENSP
Ignition Current
Sense Input Positive Used to measure current in IGBT emitter resistor for IGNOUT1 and
IGNOUT2, if used.
Negative input to the ignition current sense differential amplifier
4
5
IGNSENSN
O2HSENSN
Input
Input
Ignition Current
Sense Input Negative Used to measure current in IGBT emitter resistor for IGNOUT1 and
IGNOUT2, if used
Negative input to the O2 heater current sense differential amplifier
O2 Heater Current
Sense Input Negative Used to measure current in of O2 heater driver MOSFET source resistor, if
used.
33814
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
Table 2. 33814 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 20.
Pin
Function
Pin
Pin Name
Formal Name
Description
Positive input to the O2 heater current sense differential amplifier
6
O2HSENSP
Input
O2 Heater Current
Sense Input Positive Used to measure current in of O2 heater driver MOSFET source resistor, if
used.
5.0 V Logic Level Output from conditioned VRS differential inputs VRSP,
VRSN
7
8
9
VRSOUT
VRSP
Output
Input
VRS Conditioned
Output
The VRSP and VRSN form a differential input for the Variable Reluctance
Sensor attached to the crankshaft toothed wheel.
Variable Reluctance
Sensor Positive Input
The VRSP and VRSN form a differential input for the Variable Reluctance
Sensor attached to the crankshaft toothed wheel.
VRSN
Input
Variable Reluctance
Sensor Negative
Input
The Chip Select input pin is an active low signal sent by the MCU to indicate
that the device is being addressed.
10
11
CSB
Input
SPI Chip Select
VPWR is the main voltage supply input for the device. Connected to a 12 Volt
battery (Should have reverse battery protection and adequate transient
protection.)
VPWR
Supply Input Main Voltage Supply
Input
The SCLK input pin is used to clock in and out the serial data on the SI and
SO pins while being addressed by the CSB.
12
SCLK
Input
SPI Clock Input
The SI input pin is used to receive serial data into the device from the MCU.
Base drive for external PNP pass transistor
13
14
SI
Input
SPI Data Input
VPPREF
Output
VPP Reference Base
Drive
Ground pin, return for all voltage supplies
15
16
17
GND
SO
Ground
Output
Supply
Ground
The SO output pin is used to transmit serial data from the device to the MCU.
SPI Data Output
5.0 Volt supply output for MCU VCC. This output supplies the VCC voltage for
5.0 Volt MCUs. It is short-circuit and over-current protected.
VCC
VCC Supply
Protected Output
Feedback to internal VPP 6.5 Volt regulator from external pass transistor
18
19
20
VPPSENS
RESETB
VPROT
Input
Output
Output
Voltage Sense from
VPP
5.0 V Logic level reset signal used to reset the MCU during under and over-
voltage conditions and for initial power-up, down and watchdog timeouts
RESETB Output to
MCU
The VPROT Output is a protected 5.0 Volt output that tracks the VCC voltage
but isolates the VCC output against shorts to ground and to battery. It is
intended to supply sensors which are located off of the ECU board.
Sensor Supply
Protected Output
Low side driver output for MIL (warning lamp) driven by SPI input command
21
22
LAMPOUT
RGND2
Output
WarningLampOutput
Ground connection for ROUT 2 low side driver. Must be tied to VPWR
Ground.
Ground
ROUT2 Power
Ground
Low side relay driver output # 2 driven by SPI input command or RIN2 logic
input
23
ROUT2
Output
Relay Driver 2 Output
For future expansion
For future expansion
24
25
26
N.C.
N.C.
No Connect
No Connect
Output
Unused pin
Unused pin
This pin provides the low side drive for a tachometer gauge or alternatively as
a SPI controlled low side driver, or oscillator output.
TACHOUT
Tachometer output
Output 5.0 V logic level ISO9141 data to the MCU from the ISO9141 IN/OUT
pin
27
28
MRX
MTX
Output
Input
Low Side Driver
Output
Input 5.0 V logic level ISO9141 data from the MCU to the ISO9141 IN/OUT
pin
ISO9141 MCU Data
Input
33814
Analog Integrated Circuit Device Data
Freescale Semiconductor
6
Table 2. 33814 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 20.
Pin
Function
Pin
Pin Name
Formal Name
Description
This output is a 5.0 V logic level that is high when KEYSW is high. It is only
low when KEYSW is low. It can also be controlled via the SPI. The BATSW
output may not be present in a different package but it’s function can be read
by the SPI.
29
BATSW
Output
Battery Switch
5.0 V logic level input from the MCU to control the injector 2 driver output.
(Can also be controlled via the SPI)
30
31
32
33
34
INJIN2
INJIN1
IGNIN2
IGNIN1
O2HIN
Input
Input
Input
Input
Input
Injector Driver Input 2
Injector Driver Input 1
Ignition Input 2
5.0 V logic level input from the MCU to control the injector 1 driver output.
(Can also be controlled via the SPI)
5.0 V logic level input from MCU controlling the ignition coil # 2 current flow
and spark. (Can also be controlled via the SPI)
5.0 V logic level input from MCU controlling the ignition coil # 1 current flow
and spark. (Can also be controlled via the SPI)
Ignition Input 1
5.0 V logic level input used to turn on and off the O2HOUT driver. The
O2HOUT driver can also be turned on and off via the SPI if this pin is not
present in a different package.
O2 Sensor Heater
Input
5.0 V logic level input from the MCU to control the relay 2 driver output
ROUT2. The ROUT2 driver can also be turned on and off via the SPI if this
pin is not present in a different package.
35
36
37
RIN2
RIN1
Input
Input
Input
Relay Driver Input 2
Relay Driver Input 1
Key Switch Input
5.0 V logic level input from the MCU to control the relay 1 driver output
ROUT1. The ROUT1 driver can also be turned on and off via the SPI if this
pin is not present in a different package.
The Key Switch Input is a VPWR level signal that indicates that the Key is
inserted and turned to the ON/OFF position. In the ON position the
(KEYSW = VBAT) the IC is enabled and BATSW = HIGH (Relay 2 ON if
programmed in the SPI). In the OFF position the IC is in Sleep mode, only
when the PWREN bit in the SPI register is also low.
KEYSW
Ground connection for injector 2 low side driver. Must be tied to VPWR
ground.
38
39
40
41
42
43
44
INJGND2
INJOUT2
RGND1
Ground
Output
Injector Driver 2
Ground
Low side driver output for injector 2 driven by the SPI input or by parallel input
INJIN2
Injector Driver 2
Output
Ground connection for ROUT 1 low side driver. Must be tied to VPWR ground.
Ground
Output
ROUT1 Power
Ground
Low side relay driver output # 1 driven by the SPI input command or RIN1
logic input
ROUT1
Relay Driver 1 Output
Ground connection for injector 1 low side driver. Must be tied to VPWR
ground.
INJGND1
INJOUT1
ISO9141
Ground
Output
Injector Driver 1
Ground
Low side driver output for injector 1 driven by the SPI input or by parallel input
INJIN1
Injector Driver 1
Output
ISO9141 pin is VPWR level IN/OUT signal which is connected to an external
ECU tester that uses the ISO9141 protocol.The output is open drain and the
Input is a ratiometric VPWR level threshold comparator.
Input/Output
ISO9141 K-Line
Bidirectional Serial
Data Signal
Voltage feedback from collector of ignition # 1 driver IGBT through 10:1
voltage divider (9R:1R)
45
IGNFB1
Input
Feedback from
Collector 1
Output to gate of IGBT or GPGD for ignition # 1
46
47
IGNOUT1
IGNFB2
Output
Input
Ignition Output 1
Voltage feedback from collector of ignition # 2 driver IGBT through 10:1
voltage divider (9R:1R)
Feedback from
Collector 2
Output to gate of IGBT or GPGD for ignition # 2
48
IGNOUT2
Output
Ignition Output 2
33814
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
4
General Product Characteristics
4.1
Maximum Ratings
Table 3. MAXIMUM RATINGS
All voltages are with respect to ground, unless mentioned otherwise. Exceeding these ratings may cause malfunction or
permanent device damage.
Parameter
Symbol
Min.
Max.
Unit
ELECTRICAL RATINGS
Supply Voltage
V
V
-0.3
-0.3
-0.3
-0.3
45
V
PWR
PWR
DC
VPP Supply Voltage (If supplied externally and not using internal VPP regulator)
VPROT Regulator
VPP_Ext
VPROT
10.0
VPWR
V
V
V
DC
DC
DC
SPI Interface and Logic Input Voltage (VSI, VSCLK, VCSB, VRIN1, VRIN2, VINJIN1
INJIN2, VIGNIN1, VIGNIN2, VO2HIN, VMTX
,
VIL, VIH
V
CC
V
)
SPI Interface and Logic Output Voltage (VSO, VBATSW, VMRX,VVRSOUT
)
VIL, VIH
VOUTX
-0.3
-0.3
V
V
V
CC
DC
DC
All Low Side Drivers Drain Voltage (VINJOUT1, VINJOUT2, VROUT1, VROUT2, VLAMPOUT,
VCLAMP
VTACHOUT
)
All Pre-drivers Output Voltage (VIGNOUT1, VIGNOUT2, VO2HOUT
)
VGDX
VGDFB
VISENS
-0.3
-1.5
-0.3
10
60
V
V
V
DC
DC
DC
All Pre-driver Feedback Inputs Voltage (VIGNFB1, VIGNFB2, VO2HFB
All Pre-driver Current Sense Inputs Voltage
)
1.0
(VIGNSENSN, VIGNSENSP, VO2HSENSN,VO2HSENSP
KEYSW Input Voltage (VKEYSW
RESETB Output Voltage (VRESETB
ISO9141 Input/Output Voltage (VISO9141
)
)
VKEYSW
VRESETB
VISO9141
IOC_INJX
-18
-0.3
-18
VPWR
V
V
V
DC
DC
DC
)
V
CC
)
VPWR
Output Continuous Current (INJOUT1, INJOUT2)
• TJUNCTION = 150 °C
A
–
–
–
–
–
1.3
Output Continuous Current (ROUT1)
• TJUNCTION = 150 °C
IOC_R1
A
2.0
1.0
1.0
50
Output Continuous Current (ROUT2)
• TJUNCTION = 150 °C
IOC_R2
A
Output Continuous Current (LAMPOUT)
• TJUNCTION = 150 °C
IOC_LAMP
A
Output Continuous Current (TACHOUT)
• TJUNCTION = 150 °C
IOC_TACH
mA
Maximum Voltage for VRSN and VRSP inputs to ground
VVRS_IN
IVRSX_IN
-0.5
–
6.0
15
V
DC
Maximum Current for VRSN and VRSP inputs (internal diodes limit voltage)
mA
Output Clamp Energy (INJOUT1, INJOUT2, ROUT1)(Single Pulse)
• TJUNCTION = 150 °C, IOUT = 1.0 A
E
mJ
CLAMP
TBD
TBD
100
Output Clamp Energy (INJOUT1, INJOUT2)(Continuous Pulse)
E
mJ
CLAMP
• TJUNCTION = 125 °C, IOUT = 1.0 A, TBD kHz (Max Injector frequency is 70 Hz)
TBD
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Analog Integrated Circuit Device Data
Freescale Semiconductor
8
Table 3. MAXIMUM RATINGS
All voltages are with respect to ground, unless mentioned otherwise. Exceeding these ratings may cause malfunction or
permanent device damage.
Parameter
Symbol
Min.
Max.
Unit
THERMAL RATINGS
Operating Temperature (Automotive grade version)
C
• Ambient
• Junction
• Case
TA
TJ
-40
-40
-40
125
150
125
TC
Storage Temperature
T
-55
–
150
3.0
C
W
STG
Power Dissipation (T 25 C)
P
D
A
Peak Package Reflow Temperature During Reflow (2) (3)
,
TPPRT
–
Note 3
C
Notes
2. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
3. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts (i.e. MC33xxxD enter 33xxx), and review parametrics.
33814
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
4.2
Static Electrical Characteristics
Table 4. Power Input Static Electrical Characteristics
Characteristics noted under conditions of 6.0 V VPWR 18 V, -40 C TC 125 C, and Calibrated Timers, unless otherwise
noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 14 V, TA = 25 C.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUT (VPWR)
Supply Voltage (measured at VPWR pin)(4)
• Logic Stable Range
V
VPWR(
VPWR(
VPWR(
2.5
4.5
6.0
–
–
–
45
36
18
FO
)
)
• Full Operational Range
FO
• Full Parameter Specification Range
FP)
Supply Current
IVPWR(
mA
ON)
• All Outputs Disabled (Normal Mode), excludes base current to the external
pnp
–
–
10.0
10
14.0
20
Sleep State Supply Current (Must have PWREN & KEYSW 0.8 V for sleep
state),
IVPWR(SS)
A
• VPWR = 18 V
VPWR Over-voltage Shutdown Threshold Voltage (OV Reset)(5)
VPWR Over-voltage Shutdown Hysteresis Voltage
VPWR(OV)
37.5
0.5
39
42
V
V
VPWR
1.5
3.0
(OV-HYS)
VCC Power On Reset Voltage Threshold (POR Power On Reset), rising VT
VCC Under-voltage Shutdown Threshold Voltage (UV Reset)(6), falling VT
VCC POR and Under-voltage Shutdown Hysteresis Voltage
VCC POR and Under-voltage Non-overlap (POR-UV)
VCC(POR)
VCC(UV)
3.9
2.9
100
0.8
–
–
4.9
3.9
–
V
V
VCC(UV/POR-HYS)
–
mV
V
VCC,
1.0
1.2
NONOVERLAP
VOLTAGE PRE-REGULATOR OUTPUT (VPPREF, VPPSENS)
VPPREF Output Voltage
VPPREF
IVPPREF
5.85
–
6.5
-5.0
-15
–
7.15
–
V
VPPREF Output Current (includes external PNP current)
VPPREF Current Limit
mA
mA
F
IVPPCL
-5
2.2
–
-20
25
3
Output Capacitance External (ceramic)
VPPSENS Input Current
VOCE
IVPPSENS
REGLINE_VPP
–
mA
mV
Line Regulation IVCC = 100 mA, IVPROT = 50 mA 9.0 V < VPWR < 18 V and Diodes
Inc. FZT753TA PNP
–
2.0
25
Dropout Voltage (Minimal Input/Output Voltage, tracks input below)
VDROPOUT_PP
–
1.05
1.4
V
I
VCC = 100 mA, IVPROT = 50 mA and Diodes Inc. FZT753TA PNP
Notes
4. This parameter is guaranteed by design but is not production tested.
5. Over-voltage thresholds minimum and maximum include hysteresis.
6. Under-voltage thresholds minimum and maximum include hysteresis
33814
Analog Integrated Circuit Device Data
Freescale Semiconductor
10
Table 4. Power Input Static Electrical Characteristics
Characteristics noted under conditions of 6.0 V VPWR 18 V, -40 C TC 125 C, and Calibrated Timers, unless otherwise
noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 14 V, TA = 25 C.
Characteristic
VOLTAGE REGULATOR OUTPUTS (VCC, VPROT)
VCC Output Voltage 0 IVCC IVCC_C
Symbol
Min
Typ
Max
Unit
VCC
IVCC_C
4.9
–
5.0
–
5.1
200
20
V
VCC Output Current Continuous
mA
mV
VPROT Output Voltage (tracks VCC)
IVCC-VPROT
|
–
–
IVCC = 100 mA, IVPROT = 50 mA 9.0 V < VPWR < 18 V
VPROT Output Current Continuous
IVPROT_C
IVCC_CL
IVPROT_CL
VOCE
–
–
–
100
500
260
47
mA
mA
mA
F
VCC Output Current Limiting
200
110
2.2
–
VPROT Output Current Limiting
–
Output Capacitance External (VCC and VPROT) without reverse protection diode
–
Line Regulation (Both VCC and VPROT
IVCC =100 mA, IPROT = 50 mA, 9.0 V< VPWR < 18 V
)
REGLINE_VB
REGLOAD_VB
VDROPOUT
2.0
25
mV
Load Regulation (Both VCC and VPROT) measured from 10% - 90% of IVCC_C
&
–
–
2.0
25
mV
V
I
PROT_C, VPWR = 13 V
Dropout Voltage (Both VCC and VPROT) (Minimal Input/Output Voltage at full load,
tracks input below)
1.05
1.4
ALL LOW SIDE DRIVERS (INJ1, INJ2, ROUT1, ROUT2, LAMPOUT, TACHOUT)
Output Fault Detection Voltage Threshold(7)
Outputs programmed OFF (Open Load)
Outputs programmed ON (Short to Battery)
VOUT(FLT-TH)
V
2.0
2.5
3.0
Output OFF Open Load Detection Current (INJ1, INJ2, RELAY1, RELAY2 &
LAMP)
I(OFF)OCO
A
40
10
–
75
–
115
30
• VDRAIN = 18 V, Outputs Programmed OFF
Output OFF Open Load Detection Current TachOut
Output Leakage Current
A
A
IOUT(LKG)
• VDRAIN = 24 V, Open Load Detection Disabled and Output commanded
OFF
–
20
Over-temperature Shutdown (OT) (8)
TLIM
TLIM(HYS)
VOC
155
5.0
–
185
15
C
C
V
Over-temperature Shutdown Hysteresis(9)
10
Output Clamp Voltage
• ID = 20 mA
48
53
60
INJOUT1, INJOUT2
Drain-to-Source ON Resistance
• IOUT = 1.0 A TJ = 125 °C, VPWR = 13 V
• IOUT = 1.0 A TJ = 25 °C, VPWR = 13 V
• IOUT = 1.0 A TJ = -40 °C, VPWR = 13 V
RDS(ON)_INJx
RDS(ON)_INJx
RDS(ON)_INJx
–
–
–
–
0.4
–
0.6
–
–
Continuous Current (not to exceed)
Output Self Limiting Current
Notes
IOUT(CC)_INJx
IOUT(LIM)_INJx
–
–
–
1.3
3.0
A
A
1.6
7. These parameters are guaranteed by design. Production test equipment uses 1.0 MHz, 5.0 V SPI interface.
8. This parameter is guaranteed by design, however it is not production tested.
9. Programmable via SPI but variable with magnitude input frequency
33814
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
Table 4. Power Input Static Electrical Characteristics
Characteristics noted under conditions of 6.0 V VPWR 18 V, -40 C TC 125 C, and Calibrated Timers, unless otherwise
noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 14 V, TA = 25 C.
Characteristic
Symbol
Min
Typ
Max
Unit
ROUT1
Driver Drain-to-Source ON Resistance
RDS(ON)_R1
• IOUT = 700 mA, TJ = 150 C, VPWR = 13 V
–
0.3
0.4
Continuous Current (not to exceed)
Output Self-limiting Current (Has inrush current timer)
ROUT2
IOUT(CC)_R1
IOUT(LIM)_R1
–
–
–
2.0
6.0
A
A
3.0
Driver Drain-to-Source ON Resistance
• IOUT = 350 mA, TJ = 150 C, VPWR = 13 V
RDS(ON)_R2
–
–
1.5
Continuous Current (not to exceed)
Output Self-limiting Current
LAMPOUT
IOUT(CC)_R2
IOUT(LIM)_R2
–
–
–
1.0
2.4
1.2
Driver Drain-to-Source ON Resistance
RDS(ON)_LAMP
• IOUT = 1.0 A, TJ = 150 C, VPWR = 13 V
–
–
1.5
Continuous Current
IOUT(CC)_LAMP
–
-
1.0
2.4
A
A
Output Self-limiting Current (Has inrush current timer)
IOUT(LIM)_
1.2
–
LAMP
TACHOUT
Driver Drain-to-Source ON Resistance
RDS(ON)_TACH
• IOUT = 50 mA, TJ = 150 C, VPWR = 13 V
–
–
20
Continuous Current (not to exceed)
Output Current Shutdown
IOUT(CC)_TACH
–
–
–
50
mA
mA
IOUT(SHUTDOWN)
60
110
_TACH
ALL PRE-DRIVERS (IGNOUT1, IGNOUT2, AND O2HOUT)
Pre-driver Output Voltage, VPWR = 13 V
• IGD = 500 A
V
VGS(ON)
7.0
0.0
8.0
9.0
0.5
VGS(OFF)
0.375
• IGD = -500 A
IGNOUTx Output Source Current (IGNOUT1 and IGNOUT2 by default)
• 1.0 VGD 3.0, VPWR = 13 V
IIGN_GD_H
I(OFF)OCO
10
–
–
mA
Output OFF Open Load Detection Current
• VDRAIN = 18 V, Outputs Programmed OFF
A
40
10
75
–
115
–
GPGD Output Source Current (O2HOUT by default) at 1.0 VGD 3.0,
IGPGD_GD_H
mA
VPWR = 13 V
Pre-driver Output Voltage
• IGD = 500 A
VIGNFB(FLT-TH)
VGPGD(FLT_TH)
100
1.0
250
2.5
400
4.0
mV
V
• IGD = -500 A
Output Clamp Voltage
VCLAMP
48
53
60
V
Over-current Voltage Threshold
• VO2HSENSN to VO2HSENSP
VSENS-TH
180
200
220
mV
33814
Analog Integrated Circuit Device Data
Freescale Semiconductor
12
Table 4. Power Input Static Electrical Characteristics
Characteristics noted under conditions of 6.0 V VPWR 18 V, -40 C TC 125 C, and Calibrated Timers, unless otherwise
noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 14 V, TA = 25 C.
Characteristic
Symbol
Min
Typ
Max
Unit
ALL PRE-DRIVERS (IGNOUT1, IGNOUT2, AND O2HOUT) (CONTINUED)
Over-current Voltage Threshold
• VIGNSENSN to VIGNSENSP) (IGNIN1 or IGNIN2 = 1
• VIGNSENSN to VIGNSENSP) (IGNIN1 and IGNIN2 = 1
VSENS-TH
VSENS-TH
180
360
200
400
220
440
mV
Current Sense Input Offset Current (IGNSENSP,IGNSENSN, O2H
Current Sense Input Bias Current
ISENS-OFFSET
ISENS-BIAS
–
–
–
–
15
15
A
A
ISO-9141 TRANSCEIVER PARAMETERS (8.0 V < VPWR < 18 V)
Input Low Voltage at ISO I/O pin
VIL_ISO
VIH_ISO
–
–
–
–
–
–
0.3x
VPWR
V
V
V
V
V
Input High Voltage at ISO I/O pin
Input Hysteresis at ISO I/O pin
0.7*
VPWR
–
VHYST_ISO
VOL_ISO
VOH_ISO
0.15x
VPWR
–
Output Low-voltage at ISO I/O pin
Output High-voltage at ISO I/O pin
Output current limit at ISO I/O pin (MTX = 0)
–
0.2x
VPWR
0.8x
VPWR
–
ILIM_ISO
CL_ISO
50
100
3.0
150
10
mA
nF
Load capacitance at ISO I/O pin(10)
VRS CONDITIONER INPUT
Comparator Thresholds
0.01
VVRS_THRESH
–
–
See Table variable via
SPI or dynamically
mV
%
Threshold Accuracy
Steady State Condition ( + 20% only valid for VRS DAC thresholds 110 mV and
higher.All other thresholds guaranteed monotonic only.)
AccuTHRESH
–
20
Input Bias Current VRSP and VRSN (2.5 V common mode must be off)
VRS Positive Clamp Voltage at ICLAMP = 10 mA
IBIASRSX
VCLAMP_P
VCLAMP_N
-5.0
5.5
5.0
5.8
µA
V
–
–
VRS Negative Clamp Voltage at ICLAMP = 10 mA
-0.44
-0.22
V
DIGITAL INTERFACE (MRX, MTX,CSB, SI, SCLK, SO, RINX,O2HIN, INJINX, IGNINX, BATSW, VRSOUT, RESETB)
Input Logic High-voltage Thresholds
Input Logic Low-voltage Thresholds
Input Logic Voltage Hysteresis
Input Logic Capacitance
VIH
VIL
0.7 x VCC
GND - 0.3
500
–
–
–
–
VCC + 0.3
V
V
0.2 x VCC
VHYS
CIN
–
mV
pF
A
–
20
Sleep Mode Input Logic Current (10)
• KEYSW = 0 V
ILOGIC_SS
-10
30
–
10
Input Logic Pull-down Current (10) INJIN1, INJIN2, RIN1, RIN2, SI, SCLK,IGNIN1,
IGNIN2, O2HIN
ILOGIC_PD
A
50
100
• 0.8 V to 5.0 V
Notes
10. This parameter is guaranteed by design, however it is not production tested.
33814
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
Table 4. Power Input Static Electrical Characteristics
Characteristics noted under conditions of 6.0 V VPWR 18 V, -40 C TC 125 C, and Calibrated Timers, unless otherwise
noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 14 V, TA = 25 C.
Characteristic
Symbol
Min
Typ
Max
Unit
DIGITAL INTERFACE (MRX, MTX,CSB, SI, SCLK, SO, RINX,O2HIN, INJINX, IGNINX, BATSW, VRSOUT, RESETB) (CONTINUED)
SO Tri-state Output (in tri-state mode, CSB = 1)
• 0 V to 5.0 V
ITRISO
A
A
-10
-10
–
–
10
10
CSB Input Current
• CSB = VCC
ICSB
Input Logic Pull-up Current - CSB and MTX
• 0.0 to 4.2 V
ILOGIC_PU
A
A
V
-20
–
-50
–
-90
10
–
CSB Leakage Current to VCC
• CSB = 5.0 V, KEYSW = 0.0 V
ICSB(LKG)
SO, MRX High-state Output Voltage (CSB =0 for SO)
• ISO-HIGH = -1.0 mA
VSO_HIGH
VMRX_HIGH
VCC - 0.4
–
SO, MRX Low-state Output Voltage (CSB =0 for SO)
• ISO-LOW = 1.0 mA
VSO_LOW
V
V
V
VMRX_HIGH
–
VCC - 1.0
–
–
–
–
0.4
–
BATSW High-state Output Voltage
• ISO-HIGH = -10 mA
VBATSW_HIGH
BATSW Low-state Output Voltage
• ISO-LOW = 10 mA
VBATSW_LOW
1.0
KEYSW High-state Input Voltage
KEYSW Low-state Input Voltage
KEYSW Hysteresis
VKEYSW_HIGH
VKEYSW_LOW
VKEYSW_HYS
VVRSOUT_LOW
4.5
-0.3
100
–
–
–
–
–
VPWR
2.5
–
V
V
mV
V
VRS Low-state Output Voltage
IVRS-LOW = 1.0 mA
0.4
VRS Low-state Output Voltage
IVRS-LOW = 1.0 mA
VVRSOUT_HIGH VCC -0.4
–
–
–
5.0
0.4
25
V
V
RESET Low-state Output Voltage
IRESET-LOW = 1.0 mA
–
VRESET_LOW
RESET High-state Leakage Voltage
10
A
IRESET_
LEAKAGE_HIGH
RESET Pull-down Resistor
300
–
400
k
RRESET_
PULDOWN
33814
Analog Integrated Circuit Device Data
Freescale Semiconductor
14
4.3
Dynamic Electrical Characteristics
(12)
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions of 6.0 V VPWR 18 V, -40 C TC 125 C, and Calibrated Timers, unless otherwise
noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 14 V, TA = 25 C.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUT
Required Low State Duration on VCC for Power On Reset
t
s
s
RESET
t(POR)
• VCC 0.2 V
1.0
–
-
–
-
Power on RESET pulse width
100
WATCHDOG TIMER
Maximum Time Value Watchdog can be loaded with (default time)
Minimum Time Value Watchdog can be loaded with
Reset Pulse Width when Watchdog times out
VRS CONDITIONING INPUT
WDMAX
WDMIN
–
–
–
–
10
–
sec.
ms
s
1.0
100
WDRESET
–
Output Blanking Time Programming Range
OUTPUTBLANK
0
–
50
%
(% of previous out pulse 0 to 15/32 in 1/32 steps, 15/32 = 46.9%)
Output Deglitch Filter Time (1/128 of the previous output pulse)
OUTPUTDEGLITCH
DELAYTHRESH
DELAYOBT
–
–
–
1.0
–
–
%
s
s
Delay from CSB to Change in VRS Comparator Threshold (11)
Delay from CSB to Change in VRS Output Blank Time (11)
ISO9141 TRANSCEIVER
10
10
–
Typical ISO9141 Data Rate
ISOBR
tTXDF
–
–
–
–
–
10
–
–
kbps
s
Turn OFF Delay MTX Input to ISO Output
2.0
1.0
1.0
1.0
Turn ON/OFF Delay ISO Input to MRX Output
Rise and Fall Time MRX Output (measured from 10% to 90%)
Maximum Rise and Fall Time MTX Input (measured from 10% to 90%)
tRXDF, tRXDR
tRXR, tRXF
tTXR, tTXF
–
s
–
s
–
s
ALL LOW SIDE DRIVERS
Output ON Current Limit Fault Filter Timer
Output Retry Timer
t
30
7.0
60
10
90
13
µs
ms
ms
µs
SC1
t
REF
tINRUSH
t(OFF)OC
7.0(11)
100
10(11)
–
13(11)
400
Inrush Current Delay Timer
Output OFF Open-circuit Fault Filter Timer
Output Slew Rate, INJOUT1,INJOUT2,ROUT1,ROUT2, and LAMPOUT
t
V/s
SR(RISE)
• R
= 500 VLOAD = 14 V
1.0
1.0
–
5.0
5.0
1.0
10
10
LOAD
Output Slew Rate, INJOUT1,INJOUT2,ROUT1,ROUT2, and LAMPOUT
• R = 500 VLOAD = 14 V
t
V/s
SR(FALL)
tPHL
LOAD
Propagation Delay (Input Rising Edge OR CSB to Output Falling Edge)
µs
• Input at 50% VDD to Output voltage 90% of VLOAD (INJ1, INJ2,
ROUT1, ROUT2, LAMP)
5.0
Propagation Delay (Input Rising Edge OR CSB to Output Falling Edge)
• Input at 50% VDD to Output voltage 90% of VLOAD (TACHOMETER)
tPHL
µs
–
1.0
6.0
Notes
11. Guaranteed by Design
12. PWM frequencies, watchdog time periods, and tachometer driver oscillator mode timings and frequencies, are all derived from the
trimmed, internal oscillator of 4.0 MHz
33814
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
(12)
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions of 6.0 V VPWR 18 V, -40 C TC 125 C, and Calibrated Timers, unless otherwise
noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 14 V, TA = 25 C.
Characteristic
Symbol
Min
Typ
Max
Unit
ALL LOW SIDE DRIVERS (CONTINUED)
Propagation Delay (Input Falling Edge OR CSB to Output Rising Edge)
tPLH
µs
• Input at 50% VDD to Output voltage 10% of VLOAD (INJ1, INJ2,
ROUT1, ROUT2, LAMP)
–
1.0
5.0
Propagation Delay (Input Falling Edge OR CSB to Output Rising Edge)
• Input at 50% VDD to Output voltage 10% of VLOAD (TACHOMETER)
tPLH
µs
–
1.0
–
6.0
14
Output Slew Rate, Tachout
t
V/s
SR(FALL)
• R
= 500 VLOAD = 14 V
6.0
LOAD
ALL GATE PRE-DRIVER (IGN1, IGN2, AND O2H)
Output OFF Open-circuit Fault Filter Timer
t(OFF)OC
µs
µs
µs
100
30
–
–
–
400
90
Over-current (short-circuit) Fault Filter Timer
tSC
Propagation Delay (Input Rising Edge OR CSB to Output Rising Edge)
• Input at 50% VDD to Output voltage 10% of VGS(ON)
tPLH
1.0
5.0
Propagation Delay (Input Falling Edge OR CSB to Output Falling Edge)
• Input at 50% VDD to Output voltage 90% of VGS(ON)
tPHL
µs
–
1.0
5.0
SPI DIGITAL INTERFACE TIMING (13)
Falling Edge of CSB to Rising Edge of SCLK
• Required Setup Time
tLEAD
ns
ns
ns
ns
100
50
–
–
–
–
–
–
Falling Edge of SCLK to Rising Edge of CSB
• Required Setup Time
tLAG
SI to Rising Edge of SCLK
• Required Setup Time
t
SI(SU)
16
Rising Edge of SCLK to SI
• Required Hold Time
t
SI(HOLD)
20
–
–
5.0
5.0
–
–
–
SI, CSB, SCLK Signal Rise Time (14)
t
ns
ns
ns
ns
ns
µs
R(SI)
SI, CSB, SCLK Signal Fall Time (14)
tF
–
–
(SI)
Time from Falling Edge of CSB to SO Low-impedance (15)
Time from Rising Edge of CSB to SO High-impedance
Time from Falling Edge of SCLK to SO Data Valid (16)
t
–
55
55
55
SO(EN)
t
–
–
SO(DIS)
tVALID
–
25
Sequential Transfer Rate (13)
tSTR
• Time required between data transfers
–
–
1.0
Notes
13. These parameters are guaranteed by design. Production test equipment uses 1.0 MHz, 5.0 V SPI interface.
14. Rise and Fall time of incoming SI, CSB, and SCLK signals suggested for design consideration to prevent the occurrence of double
pulsing.
15. Time required for output states data to be terminated at SO pin.
16. Time required to obtain valid data out from SO following the fall of SCLK with 200 pF load.
33814
Analog Integrated Circuit Device Data
Freescale Semiconductor
16
4.4
Timing Diagrams
CSB
0.2 V
DD
t
t
LAG
LEAD
0.7 V
0.2 V
DD
SCLK
DD
t
t
SI(HOLD)
SI(SU)
0.7 V
0.2 V
DD
DD
SI
MSB in
t
SO(EN)
t
t
SO(DIS)
VALID
0.7 V
0.2 V
DD
DD
MSB out
SO
LSB out
Figure 4. Timing Diagram
33814
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
4.5
Typical Electrical Characteristics
Gate Pre‐Drive VolvsVpwr @ 25 degC
Gate Pre‐Drive VohvsVpwr @ 25 degC
Iload
Vpwr (V)
Figure 5. Typical Electrical Specifications
33814
Analog Integrated Circuit Device Data
Freescale Semiconductor
18
VprotvsVpwr @ 25 degC
Vcc vs Vpwr @ 25 degC
)
V
(
t
o
Iload
r
p
V
Vpwr (V)
)
s
m
h
o
(
n
o
s
d
R
Vpwr (V)
Figure 6. Typical Electrical Specifications (continued)
33814
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
5
General IC Functional Description and Application
Information
5.1
Functional Pin Description
5.1.1 VPWR Supply Input
The VPWR pin is the battery input to the 33814 IC. The VPWR pin requires external reverse battery and adequate transient
voltage protection. All IC analog current and internal logic current is provided from the VPWR pin.
An over-voltage comparator monitors this pin and when an over-voltage condition is present all outputs and voltage regulators
are shut off for protection. The VPWR pin should be bypassed to ground, as close to the IC as possible, with a 0.1 µF ceramic
capacitor.
5.1.2 VPPREF Output
The VPPREF output pin is used to drive the base of an external regulator PNP pass transistor. The output of this VPP regulator
supplies the input voltage to the two internal 5.0 Volt regulators. The VPP regulator is a low drop-out (LDO) regulator that provides
a regulated output voltage when the input is greater than its specified voltage level, and follows the input voltage when it is below
its specified voltage level. It is not recommended that this voltage be brought off of the module PC board, because it may not
have adequate protection to prevent damage to the PNP pass transistor under short-to-ground or short-to-battery conditions.
5.1.3 VPPSENS Input
The VPPSENS pin is used to monitor the VPP pre-regulator output voltage from the external pass transistor’s collector, and to
supply the input voltage to the VCC and VPROT regulators.
The VPPSENS pin should be bypassed to ground, as close to the IC as possible, with a 0.1 µF ceramic capacitor and a higher
value electrolytic capacitor in parallel.
5.1.4 VCC Output (5.0 V Supply)
The VCC regulator obtains its input voltage from the VPP pre-regulator. The VCC output supplies 5.0 V power to the system MCU
and other on-board peripherals.
A Power On Reset (POR) circuit monitors the VCC output voltage level. When the VCC voltage exceeds the VCC(POR) threshold,
the RESETB line is held low for an additional delay time, t(POR), and then brought to a logic one level.
An under-voltage (UV) circuit monitors the output of the VCC regulator and when the voltage goes below the VCC(UV) threshold
for more than the VCC filter time, t(VCC-UV), the RESETB line is asserted to a logic zero state and remains there until the POR
condition is met.
5.1.5 VPROT Output (5.0 V Protected Supply)
The VPROT regulator obtains its input voltage from the VPP pre-regulator and its reference voltage from the VCC output. VPROT
tracks VCC and is protected against shorts to ground, shorts to battery, over-current and over-temperature.The VPROT output
supplies 5.0 V power to any external sensors and other off-board peripherals. The VPROT regulator on/off state can be controlled
via a bit in the SPI Control Registers. The VPROT output should be protected against ESD by means of a 0.1 µF ceramic
capacitor on the output and a higher value electrolytic capacitor in parallel.
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Freescale Semiconductor
20
5.1.6 GND
The GND pin provides the ground reference for the VPWR, VPP, VPROT, and VCC supplies. The GND pin is used as a return for
both the power supplies as well as power ground for some of the lower current output drivers. The higher current output drivers
have their own ground pins. All ground pins (INJGND1, INJGND2, RGND1, and RGND2) and the exposed pad must be directly
connected to this pin and the negative battery terminal. There is no separate ground pin associated with the LAMPOUT driver,
it shares a ground with ROUT2.
5.1.7 SCLK Input
The serial clock (SCLK) pin clocks the internal SPI shift register of the 33814. The SI data is latched into the input shift register
on the rising edge of SCLK signal. The SO pin shifts status bits out on the falling edge of SCLK. The SO data is available for the
MCU to read on the rising edge of SCLK. With CSB in a logic high state, signals on the SCLK and SI pins will be ignored and the
SO pin will be in a high-impedance state.The SCLK signal consists of a 50% duty cycle with CMOS logic levels referenced to
VCC. All SPI transfers consist of exactly16 SCLK pulses. If any more or less than 16 clock pulses are received within one frame
of CSB going low and then high, a SPI error is reported in the SPI Status Register. The SPI error bit will also be set whenever
an invalid SPI message is received, even though it may contain 16-bits.
5.1.8 CSB Input
The system MCU selects which slave is to receive SPI communication using separate chip select (CSB) pins. With the CSB in a
logic low state, SPI words may be sent to the 33814 via the serial input (SI) pin, and status information is received by the MCU
via the serial output (SO) pin. The falling edge of CSB enables the SO output and transfers status information into the SO buffer.
The rising edge of the CSB initiates the following operation:
1. Disables the SO driver (high-impedance)
2. Activates the received command word, allowing the 33814 to activate/deactivate output drivers.
To avoid any spurious data, it is essential that the high-to-low and low-to-high transitions of the CSB signal occur only when SCLK
is in a logic low state. Internal to the 33814 device is an active pull-up to VCC on CSB. In cases where voltage exists on CSB
without the application of VCC, no current will flow from CSB to the VCC pin.This input requires CMOS logic levels referenced to
VCC and has an internal active pull-up current source.
5.1.9 SI Input
The SI pin is used for serial instruction data input. SI information is latched into the input register on the rising edge of SCLK and
the input data transitions on the falling edge of SCLK. A logic high state present on SI will program a one in the command word
on the rising edge of the CSB signal. To program a complete word, 16 bits of information must be entered into the device.This
input requires CMOS logic levels referenced to VCC
.
5.1.10 SO Output
The SO pin is the output from the SPI shift register. The SO pin remains high-impedance until the CSB pin transitions to a logic
low state. All normal operating drivers are reported as zero, all faulted drivers are reported as one. The negative transition of CSB
enables the SO driver.
The SI/SO shifting of the data follows a first-in-first-out protocol, with both input and output words transferring the most significant
bit (MSB) first.
The serial output data is available to be latched by the MCU on the rising edge of SCLK. The SO data transitions on falling edge
of the SCLK. This output provides CMOS logic levels referenced to VCC.
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5.1.11 KEYSW Input
KEYSW is the input from the vehicle ignition keyswitch. This signal is at VBAT (12 V) when the key is inserted and turned to the
ON position. When the key is in the OFF position and/or removed from the keyswitch, this input is pulled to ground by an internal
pull-down resistor. When this signal is low, and the PWREN SPI Control register bit is also low, the 33814 is in the Sleep mode.
If the PWREN SPI control register bit is logic one, when the KEYSW goes low, only the outputs are turned off (except ROUT2 if
the Shut Down Disable bit is set). When the PWREN SPI Control register bit also goes to zero, the entire circuit enters Sleep
mode. When KEYSW signal goes high, it wakes up the IC, turns on the VPP regulator and a Power On Reset signal is generated.
This pin is internally protected against a reverse battery condition by an internal diode.
The state of the KEYSW input is also available as a bit in the SPI Status Register.
5.1.12 PWREN SPI Control Register BIT
The PWREN signal is a bit in the SPI Control Register that, along with KEYSW, BATSW, and the ROUT2 output can provide the
power start-up logic of the vehicle.
The purpose of the PWREN signal is allow the MCU to control the shutdown of power to itself when the user turns off the KEYSW.
This may be necessary to allow the MCU the time required to perform its pre-shutdown routines.
When the MCU wants to shutdown the power supplies in the 33814, it must write a logic zero (0) to the PWREN bit in the SPI
Control register. Only the state of the PWREN bit in the SPI Control register will control the shutdown of the 33814 power
supplies.
5.1.13 BATSW Output
The BATSW output pin is a 5.0 V logic level output that by default is an indication of the state of the KEYSW input. When KEYSW
is at VBAT (12 V) level the BATSW output is a logic 1 (5.0 V), and when KEYSW is at ground (0 V) level, BATSW is at a logic 0.
The BATSW output may be used to inform the MCU that the user is trying to shutdown the vehicle.
The BATSW output can also be used to control an LS driver, such as the Relay 2 driver, by connecting the BATSW output to the
RIN2 input.
In certain packaged options of the 33814, the BATSW signal is not brought out to a pin. In this case, the BATSW signal can still
be determined by the MCU by reading the state of BATSW bit in the SPI Status register. The MCU can then control the ROUT2
(Relay 2 output) by setting the “RIN2” bit in the SPI Control register.
If the BATSW signal is not needed by the MCU or to control the Relay 2 output, it can also be configured as a low current LED
high side driver controlled through the SPI interface. As a high side driver, BATSW can also be PWM’d to allow an LED to be
dimmed. A bit in the SPI Battery Switch Logic Output Configuration register called “HSD”, controls whether the BATSW output
will be a simple high side driver, or will be controlled by KEYSW as indicated above.
MC33814
OffꢁBoard
300 ꢀ
BATSW
.01ꢁμF
LED
GND
Figure 7. Recommended Circuit to Use BATSW as an LED Driver
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If the BATSW output is used to control an LED, the LED cathode should be tied to ground and the LED anode should be
connected to the BATSW pin through an external resistor. The value of the external resistor should be 340 ohms or greater. Care
must be taken if the BATSW output is sent off-board due to the chance of shorts to the battery or shorts to ground, for which the
output is not protected. At a minimum, this output should be protected by a diode, the current limit resistor, and an ESD capacitor
(.01 µF ceramic).
5.1.14 Using ROUT2 as a Power RelAY
The ROUT2 (Relay 2 Output) can be used to drive a power relay. The RIN2 input or the RIN2 bit in the SPI Control register can
be used to turn the ROUT2 output on or off as desired. The BATSW output can be connected to the RIN2 input to control the
power relay, or the MCU can chose to control the RIN2 bit in the SPI Control register to actuate the power relay.
The ROUT2 output is unique in that it can be kept turned on even after KEYSW is turned off (as long as the PWREN bit is still
set to a one) by setting the shut down disable (SDD) bit in the ROUT2 Configuration register.
5.1.15 ISO9141 Transceiver (MTX, MRX, ISO9141)
These three pins are used to provide an ISO914, K-line communication link for the MCU to provide diagnostic support for the
system. MRX is the 5.0 V logic level serial output line to the MCU. MTX is the 5.0 V logic level serial input to the IC from the MCU.
The ISO9141 pin is a bi-directional line, consistent with the ISO9141 specification for signalling to and from the MCU. There is
only one bit in the SPI Status register to indicate an over-temperature fault from the ISO9141 functional block. There are no
Configuration or Control registers associated with this functional block.
5.1.16 Tachometer (TACHOUT)
The TACHOUT pin is a low side driver, that can used to drive a tachometer meter movement. TACHOUT can be programmed
via the SPI to:
1. Output the same signal as VRSOUT divided by a 1 to 32 programmable divider,
2. Output a PWM signal with a frequency and duty cycle programmable via the SPI, or
3. Output one of 8 fixed frequencies as indicated in Table 6.
If a tachometer is not required the TACHOUT output can also be used as a low current, SPI controlled, low side driver to drive a
LED or other low current load. The SPI Configuration register for the Tachometer is used to determine which mode this output
will be used in. The TACHOUT output handles over-current (OC) differently than the other low side drivers. When an over-current
limit is reached the TACHOUT output does not enter a current limiting state but rather shuts the output off to protect the output
device. The retry option works similarly to the other low side drivers.
In the LSD mode bit 4 of the SPI Configuration register controls the turn on or turn off of the Open Load detect current sink.
Table 6. TACHOUT SPI Configuration Register
SPI Configuration
TACHOUT Mode
Register 4 Bits 6,5
00 (default)
VRSOUT divided by ‘N’ where ‘N’ is defined by bits 0 thru 4 of SPI
Configuration Register 4 (1 - 32)
00001 = 1 (default)
.
11111 = 31
00000=32
01
10
11
Oscillator Output
Low Side Driver (LSD)
Same as 10 above
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Table 7. TACHOUT SPI Configuration Register
SPI Configuration
Oscillator Frequencies
Register Bits 2,1,0
000 (default)
001
10 Hz
100 Hz
010
1.0 kHz
011
5.0 kHz
100
10 kHz
101
20 kHz
40 kHz
110
111
100 kHz (not recommended for use)
Table 8. TACHOUT SPI CONFIGURATION REGISTER
7
6
5
4
3
2
1
0
Retry
VRSOUT
LSD
/
VRSOUT
Osc.
/
OL Current In-Rush
Output
Freq. 2
Output/
PWM
Output/
PWM
Enable
Sink Enable
Delay
mode
Freq. 1
Freq. 0
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(1)
N16
N8
N4
N2
N1
5.1.17 INJIN1, INJIN2 Inputs
The INJIN1and INJIN2 pins are the parallel inputs that control the Injector outputs, INJOUT1 and INJOUT2 respectively. The
INJIN1 and INJIN2 pins are logic level inputs with built-in pull-downs to ground to prevent accidental actuation of an injector if
the connection to the pin is lost. As a default, INJIN1 and INJIN2 inputs are OR’d with the injector control bits in the SPI ON/OFF
control word. This is to allow the INJOUT’s to be controlled by either the INJIN’s (parallel inputs) or via the SPI when either Injector
driver is being used for purposes other than injector drive.
5.1.18 INJOUT1, INJOUT2 Driver Outputs
These output pins are the injector driver outputs for the two Injectors that the IC supports. If two injectors are not needed, one
INJOUT can be used as a general purpose low side driver for relays, motors, lamps, gauges, etc. The injector driver outputs can
be controlled by the parallel input (INJINx) or the appropriate bit in the SPI Injector Command register. The Injector outputs can
also be PWM’d via the SPI for use as variable speed motor drivers, LED/lamp dimming drivers, or as a fuel pump driver. Injector
outputs are forced off during all RESET events.
5.1.19 RIN1, RIN2 Inputs
The RIN1and RIN2 pins are the parallel inputs that control the relay outputs, ROUT1 and ROUT2 respectively. The RIN1 and
RIN2 pins are 5.0 V logic level inputs with built-in pull-downs to ground to prevent accidental actuation of a relay if the connection
to the pin is lost. As a default, RIN1 and RIN2 inputs are OR’d with the Relay control bits in the SPI ON/OFF control word. This
is to allow the ROUT’s to be controlled by either the RIN’s (parallel inputs) or via the SPI when either relay driver is being used
for purposes other than relay drive.
5.1.20 ROUT1, ROUT2 Driver Outputs
These are output pins for ROUT1 and ROUT2 low side drivers. These outputs have different current ratings and can be used to
drive relays or other inductive loads. Each output is controlled via the SPI or via the RINx logic inputs. Each output has a pull-
down current sink that can be enabled via the SPI to provide open load diagnostics. The open load detect current sink can be
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disabled via the SPI to allow the outputs to be used as LED drivers. The ROUTx outputs can also be PWM’d via the SPI for use
as variable speed motor drivers, LED/lamp dimming drivers, or as a fuel pump driver (ROUT1). All control and configuration for
the ROUT’s is via the SPI ROUT1 and ROUT2 ON/OFF word in the SPI Control register and the individual ROUT1 and ROUT2
words in the SPI Control register.
The ROUT2 relay output can be configured in SPI to drive a power relay controlled by the BATSW signal.
5.1.21 LAMPOUT Driver Output
The Lamp driver output, LAMPOUT is a low side driver capable of driving an incandescent lamp. The current limit contains a
programmable delay to allow the driver to handle the inrush current of a cold lamp filament. A pull-down current sink is provided
to allow the IC to detect when the bulb is burned out (open filament). The turn on and off of the LAMP is via the SPI ON/OFF
Control register word and it also has the ability to be PWM’d for advanced diagnostic (dimming) purposes via the SPI Lamp
Control register. The output can also be used to drive a LED if the open load detect current sink is commanded off via SPI, to
prevent “ghosting”. The LAMPOUT SPI Configuration Register contains the following bits.
Table 9. LAMPOUT SPI Configuration Register
7
6
5
4
3
2
1
0
Retry
x
x
OL Current In-Rush
x
PWM
PWM
Enable
Sink
Delay
Freq. 1
Freq. 0
Enable
(0)
(0)
(0)
(1)
(1)
(0)
(0)
(0)
The Retry Enable bit, bit 7, when set will allow the output to turn on for a short period and off for a long period when an over
current condition is present. The open load (OL) current sink disable allows the current sink to be turned off when using the driver
as an LED driver to prevent ghosting, where the LEDS appears to be partially on due to the OL current sink. It can also be turned
off to measure the output device leakage. The Inrush delay bit, when set (by default for the Lamp driver) waits an additional time
before annunciating an over-current condition. This is done to allow for the inrush current of an incandescent lamp. The internal
PWM duty cycles (D/C) are controlled by the lower 7 bits in the corresponding SPI Control Register. The external duty cycles are
provided by the MCU on the input pin of the corresponding output driver.
Bits 1, 0
PWM Frequency
PWM D/C
00
01
10
11
None or on ext. pin
100 Hz
None or on ext. pin
Internal
1 KHz
Internal
On ext pin 100
Internal
5.1.22 VRSP, VRSN Inputs, VRSOUT Output
The 33814 contains a VRS input conditioning circuit that employs a differential input. VRSP and VRSN are the positive and
negative inputs from the VRS (See Figure 8). Internal zener diode clamps to ground and VCC limit the input voltage to within the
safe operating range of the circuit. It is important to provide external 15 k current limiting resistors to prevent damage to the VRSP
and VRSN inputs (See Figure 8). The VRS circuit conditions and digitizes the input from the crankshaft mounted toothed wheel
to provide an angle clock and RPM data to the MCU. This circuit provides a comparator with multiple thresholds, which are
programmed via the SPI to allow the VRS circuit to handle different sensors and the wide dynamic range of the VRS output at
engine speeds from crank to running. The output of this circuit is provided on the VRSOUT pin, which is a 5.0 Volt logic level
signal to the MCU. The comparator threshold values can also be controlled automatically based on the input signal amplitude.The
output of the comparator contains a programmable one shot, noise blanking circuit. The time value of this blanking pulse can be
selected via the SPI as a percentage of the last input high (or low) pulse.The VRSOUT output can also be divided and sent to
the TACHOUT pin to drive a tachometer.
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VCC
External
Circuitry
VCC
15Kꢀ
1 nF
VRSP
VRSN
+
DEGLITCH
FILTER
1% of previous
output pulse up
time or Zero
BLANKING FILTER
Variable
SET
CLR
Threshold
Comparator
_
VRSOUT
S
R
Q
Q
15Kꢀ
SPI VRS
Threshold
value
Threshold
DAC
(4 Bits)
OUTPUT PULSE UP-
TIME COUNTER
4 MHz
VCC
_
DEGLITCH
FILTER
1% of previous
output pulse up
time or Zero
Zero
BLANKING
COUNTER (N/32)
(4 Bits)
SPI VRS
Blanking
value
Threshold
Comparator
+
BLANKING FILTER
Figure 8. VRS Schematic
Table 10. SPI VRS Manual Configuration Register
SPI VRS Manual Parameters
Configuration Register Bits 7, 6, 5, 4
Threshold Values (nominal)
0000
0.01 - 28 mV
(Tolerance not specified below 110 mV threshold. Only specified for monotonicity.)
0001
0010
0011
0.01 - 36 mV
(Tolerance not specified below 110 mV threshold. Only specified for monotonicity.)
3.0 - 36 mV
(Tolerance not specified below 110 mV threshold. Only specified for monotonicity.)
8.0 - 48 mV
(Tolerance not specified below 110 mV threshold. Only specified for monotonicity.)
0100
0101 (default)
0110
23 - 55 mV
(Tolerance not specified below 110 mV threshold. Only specified for monotonicity.)
35-75 mV
(Tolerance not specified below 110 mV threshold. Only specified for monotonicity.)
74 mV
(Tolerance not specified below 110 mV threshold. Only specified for monotonicity.)
0111
1000
1001
1010
1011
1100
1101
1110
1111
110 mV + 20%
150 mV + 20%
215 mV + 20%
300 mV + 20%
425 mV + 20%
600 mV + 20%
850 mV + 20%
1.210 V + 20%
1.715 V + 20%
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5.1.23 Controls for the VRSN and VRSP Inputs
The VRS can be connected to the 33814 in either a differential or single-ended fashion. The use of differential filtering capacitor,
and grounded capacitors of at least 100 nF are also advisable. In some applications, a damping resistor of approximately
5.0 kOhm directly across the pickup coil is also useful to minimize high frequency ringing.
5.1.24 GND VRSN Bit
To use the VRS inputs in a single-ended configuration the “GND VRSN” bit in the SPI Configuration register must be set to
indicate to the 33814 that this mode is being used. The VRS is then connected between the VRSP input and ground. The default
for this bit is zero (0) indicating that the differential mode is selected.
5.1.25 2.5 Volt Reference Disconnect Bit
The disconnect 2.5 Volt reference bit in the SPI VRS configuration register is used to disconnect the internal 2.5 Volt reference
signal from the VRSN and VRSP inputs, so that an external reference voltage can be employed. The default state of this bit is
zero (0), indicating that the internal 2.5 Volt reference voltage is connected to the VRSN and VRSP inputs.
5.1.26 Selecting the Input Threshold and Blanking Time
Two different SPI registers are provided to control the VRS circuit values in the manual mode. The SPI VRS configuration register
is used to set the “engine running” values for the threshold and blanking filter and the SPI VRS control register is used to provide
the “engine cranking “threshold and blanking filter values. Once the engine is running, the MCU clears the SPI VRS control
register and the 33814 will use the values found in the SPI VRS configuration register.
5.1.27 Input Comparator Threshold Values
The threshold voltage for the input comparator is produced by a 4-bit D/A converter. The control of the D/A output value is by
means of the upper four bits of the SPI VRS configuration register or the upper four bits of the SPI VRS control register. When
the contents of the SPI VRS control register contains all zeros, the binary value for the D/A threshold is taken from the value in
the SPI VRS configuration register. When the contents of the SPI VRS control register is non-zero, then the value in the upper
four bits of the SPI VRS control register is used to set the D/A output. The values outputted by this D/A, using either the SPI VRS
control register or the SPI VRS Configuration register, are listed in Table 10 in the threshold values table. The blanking one-shot
time is also set via the lower 4 bits of the SPI VRS configuration register or the SPI VRS control register using the same condition,
as described previously for the threshold D/A.
5.1.28 Blanking Time Definitions
The values for the one shot blanking, as a percentage of the last high output pulse period is shown in Table 11.
Table 11. SPI VRS Manual Configuration Register
SPI VRS Configuration/Control
Register Bits 3,2,1,0
Blanking Time in%
(of last pulse high period)
0000 (default)
0001
0.0
3.12
0010
6.25
0011
9.37
0100
12.5
0101
15.62
18.75
21.87
0110
0111
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Table 11. SPI VRS Manual Configuration Register
SPI VRS Configuration/Control
Blanking Time in%
Register Bits 3,2,1,0
(of last pulse high period)
1000
1001
1010
1011
1100
1101
1110
1111
25
28.1
31.3
34.4
37.5
40.6
43.8
46.9
5.1.29 Manual and Automatic Modes
The SPI VRS miscellaneous configuration register has a bit to enable the automatic selection of the comparator threshold (bit 7).
At this time, the operation of automatic mode remains TBD.
5.1.30 VRS Peak Detector
The VRS peak detector determines the magnitude of the positive peak of the VRS input signal and digitizes it. The value of the
VRS peak voltage is reported in the VRS SPI status register bits 7, 6, 5, and 4. The MCU can read the value of peak voltage after
the zero crossing time of the input pulse, and uses this information to set the threshold and blanking parameters for subsequent
input pulses. Status bits reflect the last detected peak and only read 0000 after a POR or SPI reset command.
Table 12. Peak Detector Output in SPI VRS Status Register
SPI VRS Status Register
Peak Values (nominal)
Bits 7,6,5,4
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
10 mV
14 mV
20 mV
28 mV
40 mV
56 mV
80 mV
113 mV
159 mV
225 mV
318 mV
450 mV
636 mV
900 mV
1.273 V
1.800 V
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5.1.31 VRS Deglitching Filters
The VRS input circuit has additional filters on the rising and falling edges of the input waveforms to reduce the effect of short
transitions that may occur during those noise sensitive times. The deglitching filters are approximately 1% of the last positive
pulse period. The deglitch filters are enabled by setting the deglitch bit (bit 3) in the SPI VRS miscellaneous parameters
configuration register. This bit is, by default, zero (0), meaning that the deglitch filters are disabled.
5.1.32 High/Low Reference Bit
The High/Low reference bit in the SPI VRS miscellaneous configuration register is used to change the use of the input high pulse
timing to input low pulse timing, in cases where an elongated tooth wheel is being used rather than the missing tooth wheel. The
default for this bit is zero (0), indicating the use of a crankshaft wheel with a missing tooth (or teeth).
5.1.33 Disable VRS bit
The disable VRS bit in the SPI VRS miscellaneous configuration register is used to disable the VRS input circuitry when there is
no need for a VRS input conditioning circuit. This would be the case, for example, if the crankshaft wheel sensor was a hall effect
device whose output could be directly input to the MCU. The default for this bit is zero (0) indicating that the VRS input
conditioning circuitry is active.
5.1.34 Clamp Active Status bits
There are two clamp active status bits in the SPI VRS status register. One is for the low pulse clamp and the other is for the high
pulse clamp. When either of these bits are a one (1), it indicates that the peak voltage for that part of the input waveform has
exceeded the clamp voltage and is being clamped to the high or low voltage limit. These status bits can be used to indicate that
the engine has attained the speed necessary to switch from “cranking” values for the threshold and blanking (in the SPI VRS
control register) to the “running” values. (in the SPI VRS configuration register).
5.1.35 Pre-driver Operation
There are three identical pre-drivers in the 33814. Each pre-driver can be configured as either an ignition (IGBT) pre-driver or a
general purpose gate driver (GPGD). By default, one pre-driver is configured as a GPGD (O2HOUT) and two pre-drivers are
configured as ignition (IGNOUT1, IGNOUT2) pre-drivers.
A bit in each of the SPI Configuration registers, for each pre-driver, defines whether the pre-driver behaves as an ignition or a
GPGD pre-driver.
It should be noted that there are only two current measurement circuits, ISGNSENSP/N and O2SENSP/N. When all three pre-
drivers are used as GPGD, then IGNSENSP/N is associated with the IGNOUT1 pre-driver only, and the O2SENSP/N is
associated with the O2OUT pre-driver. The IGNOUT2 pre-driver will not have an associated current sense circuit and will rely on
Short to Battery (drain voltage sense) protection only. When all three pre-drivers are used as ignition predrivers, then IGNOUT1
and IGNOUT2 will share the IGNSENSP/N current measurement circuit, and IGNOUT3 (O2HOUT) will have its own current
sense circuit, O2SENSP/N.
5.1.36 O2HIN Input
The O2HIN pin is the parallel input that controls the O2HOUT pre-driver output. The O2HIN pin is a 5.0 V logic level input with
a built-in pull-down to ground to prevent accidental actuation of the pre-driver output if the connection to the pin is lost. As a
default, the O2HIN input is ORed with the O2HOUT control bit in the SPI ON/OFF control word. This is to allow the O2HOUT to
be controlled by either the O2HIN (parallel input) or via the SPI.
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5.1.37 O2HOUT Pre-driver Output with Drain Feedback Input O2HFB
The O2HOUT output is a pre-driver output that controls the gate of a MOSFET to drive a heater on an O2 (Lamda) sensor. The
pre-driver is capable of driving most power MOSFETs. The O2HOUT output and associated drain feedback pin O2HFB provide
short to battery, over-current protection for the external driver MOSFET. More accurate current control can be provided by placing
a current sense resistor between the O2SENSP and O2SENSN pins.
Output-off open circuit (OL) and output-on over-current (OC) faults are detected and annunciated via the SPI.
5.1.38 IGNIN1 and IGNIN2 Inputs
The IGNIN1 and IGNIN2 pins are the parallel inputs that control the IGNOUT1 and IGNOUT2 pre-driver outputs, respectively.
The IGNIN1 and IGNIN2 pins are 5.0 V logic level inputs with built-in pull-downs to ground to prevent accidental actuation of a
pre-driver output if the connection to the pin is lost. As a default, IGNIN1 and IGNIN2 inputs are ORed with the IGNOUT1 and
IGNOUT2 control bits in the SPI ON/OFF control word. This is to allow the IGNOUTs to be controlled by either the IGNINs
(parallel inputs) or via the SPI.
5.1.39 IGNOUT1 and IGNOUT2 Pre-driver Outputs, with Feedback IGNFB1
and IGNFB2, and Current Sense Inputs
The IGNOUT1 and IGNOUT2 outputs are pre-driver outputs that drive an IGBT that controls the ignition coil current to produce
a spark. The IGNOUTx outputs and their associated feedback pins IGNFBx provide short to battery and one shared current sense
resistor provides over-current protection for the external driver transistors. When used as an IGBT driver, a 10:1 voltage divider
(9R:1R) must be used on the feedback pins to prevent the 400 Volt flyback from damaging the IC.
If two Ignition pre-drivers are not required, they can be reconfigured, via the SPI, as general purpose gate drivers (GPGDs) used
to drive ordinary MOSFETs.
More accurate current control can be provided by placing a current sense resistor between the IGNSENSP and IGNSENSN pins.
When both pre-drivers are used as ignition (IGBT) pre-drivers, the both pre-drivers can share one current sense resistor. The
input controls will determine the value of the current sense threshold voltage across the current sense resistor. When either one
of the inputs is ON, the threshold voltage will be VSENS-TH, but when both inputs are ON simultaneously, the threshold will be
raised to 2VSENS-TH to compensate for both pre-drivers being ON.
When one pre-driver is used as an ignition pre-driver and the other pre-driver is used as a GPGD, the current sense circuit is
connected ONLY to the ignition driver channel. When both pre-drivers are designated as GPGD pre-drivers, only pre-driver #1
will have use of the current sense circuit, the other pre-driver, #2, will only have short to battery protection via the drain sense
voltage comparator.
5.1.40 RESETB
The RESETB pin is a 5.0 volt logic, low level output that is used to reset the MCU.The RESETB pin is an open drain output.
Without power on the 33814 circuit, the RESETB pin is held low by an internal pull-down resistor. In a typical application, the
RESETB pin must be pulled up externally by a pull-up resistor to VCCWhen power is applied to the circuit and the voltage on
the VCC pin reaches the lower voltage threshold, the RESETB pin will remain at a low level (open drain FET turned on) for a
period of time equal to the time value WDRESET. After this time period, the RESETB pin will go high and stay high until a reset
pulse is generated due to any of the following events:
1. A watchdog timer timeout event occurs,
2. An under-voltage event on VCC occurs, or
3. An over-voltage event on VPWR occurs.
A Power On Reset (POR) is always provided upon power ON (i.e. anytime the IC goes from sleep state to active state).
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5.1.41 Disabling the Watchdog Timer
Since a watchdog reset occurs, by default 10 seconds after the POR, if the MCU needs to programmed in-circuit, a means of
disabling the watchdog must be provided to avoid interrupting the MCU programming procedure. This disable mechanism can
be a jumper between the RESETB pin of the 33814 and the MCU’s Reset input pin, or via an isolation resistor placed between
the RESETB pin on the 33814 and the MCU’s reset input pin that allows the MCU’s reset pin to be pulled high independently of
the 33814 RESETB. The watchdog can also be disabled via a bit in the SPI WD configuration register.
5.1.42 Internal Reset
There is a bit in the SPI control register that is labelled “Reset”. When this bit is set to a one (1) by the MCU, it will instruct the
33814 to perform an internal reset. This reset will NOT toggle the RESETB output pin, but will cause all internal registers to be
initialized back to their default values, including clearing the reset bit in the SPI control register.
5.2
MCU SPI Interface Description
The 33814 device directly interfaces to a 5.0 V micro controller unit (MCU) using a16-bit serial peripheral interface (SPI) protocol.
SPI serial clock frequencies up to 8.0 MHz may be used when programming and reading output status information (production
tested at 1.0 MHz). Figure 9 illustrates the SPI configuration between an MCU and one 33814.
Data is sent to the 33814 device through the SI input pin. As data is being clocked into the SI pin, other data is being clocked out
of the device by the SO output pin. The response data received by the MCU during SPI communication depends on the previous
SPI message sent to the device. The SPI can be used to read or write data to the configuration and control registers and to read
or write the data contained in the status registers.
The MCU is only allowed to read or clear bits (write zeros) in the status register unless the Power ON Self-test (POST) enable
bit in the control register is set. When the POST enable bit is set the MCU can read and write zeros or ones to the status register.
Note that the MCU must clear the POST enable bit before operation is resumed or the status register will not be updated with
fault indications.
5.2.1 SPI Integrity Check
One SPI word is reserved as a SPI check message. When bits 12 through15 are all zero, then the SPI will echo the remaining
12-bit SPI word sent and will flip bits 12 through14, bit 15 will remain a 0. This allows the MCU to poll the SPI and compare the
received message to confirm the integrity of the SPI communication channel to the 33814. There is a SPI error bit in the SPI
status register that indicates if an incorrect SPI message has been received. The SPI error bit in the SPI status register is set
whenever any SPI message error is detected.
Important A SCLK pulse count strategy has been implemented to ensure integrity of SPI communications. Only SPI messages
consisting of 16 SCLK pulses will be acknowledged. SPI messages consisting of other than 16 SCLK pulses will be ignored by
the device and reported as a SPI error. Invalid SPI messages, that contain invalid commands or addresses will also be flagged
as a SPI error.
33814
Micro controller
MOSI
MISO
SI
Shift Register
16-Bit Shift Register
SO
SCLK
Receive
Buffer
To Logic
CSB
Parallel
Ports
Figure 9. SPI Interface with Microprocessor
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Two or more 33814 devices may be used in a module system. Multiple ICs may be SPI configured in parallel only. Figure 10
demonstrates the configuration.
Micro controller
33814
MOSI
SI
Shift Register
MISO
SO
SCLK
SCLK
CSB
Parallel
Ports
33879A
SI
SO
SCLK
CSB
Figure 10. SPI Parallel Interface (Only) with Microprocessor
5.3
Functional Device Operation
5.3.1 Power Supply
The 33814 is designed to operate from VPWRMIN to VPWRMAX on the VPWR pin. The VPWR pin supplies power to all internal
regulators, and analog and logic circuit blocks.
5.3.1.1
V
Pre-regulator
PP
The VPP pre-regulator supplies the input voltage to the VCC and VPROT regulators. It uses an external PNP transistor as a pass
element. This allows the user to choose the PNP’s size and package considerations to meet the system requirements. The
amount of power that the external PNP transistor will have to dissipate depends on the maximum voltage the system can be
expected to run at and the maximum expected current drawn from the VCC and VPROT regulators. The VPPSENS pin is used to
feedback the value of the VPP voltage for regulation. Since the VPP regulator is not intended to supply off-the-board loads, there
is no short to ground or short to battery protection on the output of the external PNP.
5.3.1.2
V
Regulator
CC
The VCC regulator output is used for supplying 5.0 Volts to the MCU, and for setting communication threshold levels via the
internal SPI SO driver. The VCC regulator contains an internal pass transistor which is protected against over-current.
5.3.1.3
V
Regulator
PROT
The protected output VPROT is a tracking regulator that uses the VCC output as a reference. Since it is expected that the VPROT
regulator will supply 5.0 Volts to external sensors in the vehicle, it is well protected against shorts to battery, shorts to ground and
over-current. The VPROT supply is enabled at power-on but can be disabled via the SPI control register.
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5.3.2 Power ON Reset (POR)
Applying VPWR and bringing KEYSW high (VBAT) will generate a Power On Reset (POR) and place the device in the Normal
operating state. The Power On Reset circuit incorporates a timer to prevent high frequency transients from causing an erroneous
POR.
Upon enabling the device (KEYSW High), outputs will be activated based on the initial state of the control register or parallel
input. All three supplies, VPP, VCC, and VPROT, are enabled when KEYSW is brought high.
VPWR_OV=1 ||
VCC_UV=1||
VCC_POR=1
RESET
(Resets ASIC & MCU)
VPWR_UV=1
RESETB=0
from any state
BATSW=1
SLEEP
(Engine/Key is off)
RESETB=0
NORMAL
(SPI Bus Usable)
RESETB=1
KEYSW=0 &&
PWREN=0
BATSW=0
BATSW=1
KEYSW=0
PREPARE TO
SHUTDOWN
(SPI Bus Usable)
RESETB=1
PWREN=1
OV –
Over-voltage
SPI_RESET
(Resets ASIC Only)
RESETB=1
UV –
Under-voltage
BATSW=0
WD =
Watchdog
TD = Time Delay
POR = Power On Reset
&& = logic AND
BATSW=1
|| = logic OR
Passive State
Active States
Figure 11. 33814 Functional State Diagram
Table 13. Operational States
PWREN SPI Bit
Input
KEYSW Input
BATSWB Output
All Supplies
STATE
L
H
H
L
L
L
L
H
H
L
OFF
ON
ON
ON
Sleep
NORMAL
H
H
NORMAL
Prepare to shutdown
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5.3.3 SLEEP State
Sleep State is entered when the VBAT level signal is removed from the KEYSW pin and the PWREN SPI bit is a logic low. In
Sleep state all outputs and current sources and sinks are off and the device consumes less than IVPWR(SS) µA. Applying a VBAT
level to the KEYSW pin will force the device to exit the Sleep state and generates a POR.
5.3.4 NORMAL State
The default NORMAL state is entered when power is applied to the VPWR and the KEYSW pin.
Note that the device is designed to have VPWR present before KEYSW is brought high. It is acceptable to bring VPWR and
KEYSW high simultaneously, however it is not recommended to bring KEYSW high while VPWR is low.
SPI register settings from Power-ON Reset (POR) are as follows:
• All outputs turned off.
• Off State open load detection enabled (LSD)
• Default values in the SPI Configuration, Control and Status registers.
5.3.5 Power On Self-test (POST)
At power on, after a POR, it may be desired to go through an initial Power On Self-test routine to ensure that the SPI is working
correctly and the status registers in the 33814 are viable. After a POR, all the registers in the 33814 contain their “default” values,
as indicated in the SPI register tables later in this document. The watchdog is also set to its default timeout value of 10 seconds,
so any POST routine must be accomplished within this time frame or a WD reset may occur. To perform a POST routine, the
MCU should first send a SPI message to set the POST enable bit in the SPI control register 1, bit 6. Once this bit is set, the status
registers are disconnected from the analog and logic portions of the 33814, and are connected only to the SPI circuitry. The
POST can then write various data patterns to the status registers and verify that none of the bits are “stuck” or otherwise
unworking. Note that bits in the status register labelled “x” are not implemented and when testing these bits may result in
erroneous data. After testing all the status registers and confirming that they are viable, the status registers can be set back to
their default values by clearing the POST Enable bit back to 0. The POST enable bit allows the MCU to write ones (1s) to the
Status registers.
Normally, the status register can only be cleared to zeros by the MCU and written ones by the 33814 internal logic. This was
designed to prevent the MCU from missing any reported fault bits, and for the 33814, to prevent system status errors that could
result from the MCU erroneously writing a one (1) to a fault bit.
Once the POST enable bit is set back to a zero (0) by the MCU, the status register returns to the condition where the 33814 can
only write ones(1s) to it and the MCU can only write zeros (0s) to it.
Again, it is important to note that any POST routine should be designed to take less than 10 seconds to avoid a watchdog reset
from occurring and truncating the POST routine because the WD reset will clear the POST Enable bit as well.
The 33814 IC has two modes of operation, Normal mode, and Sleep mode.
5.3.6 Watchdog (WD)
5.3.6.1
Watchdog Normal Operation
The watchdog is a programmable timer that is used to monitor the operation of the MCU. When the MCU is executing code
properly, it’s program code should contain instructions to periodically send a SPI message to the watchdog SPI control register
to refresh the watchdog. The watchdog timer, once refreshed, will reload the time interval value stored in the SPI watchdog
configuration register and begin counting time again. Under normal operating conditions this sequence will continue until the
MCU shuts down, typically, when the KEYSW is turned off.
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5.3.6.2
Watchdog Fault Operation
In the event that something goes wrong during the MCU program execution, such as an unexpected breakpoint or other program
hang-up such as the execution of a HALT instruction, the watchdog may not be refreshed. When the WD time interval value
programmed in the SPI Configuration register elapses, the watchdog will issue a RESETB pulse. This RESETB pulse will cause
the MCU to restart it’s program and correct operation should be restored.
After any RESETB (power-on or other), the watchdog SPI configuration register will contain the default value for the refresh time,
10 seconds. The watchdog is also enabled by default.
The MCU, in it’s initialization (start-up) code, can choose to change this default value and/or disable the watchdog by sending a
SPI command to write new information in the watchdog SPI configuration register.
5.3.6.3
Watchdog SPI Configuration Register
There are seven bits in the watchdog SPI configuration register which define the time value that is loaded into the watchdog timer.
Bits 3, 2, 1, 0 are a Binary coded decimal (BCD) value from 1 to 10. (11 to 16 are mapped to 10 and 0 is mapped to 1) The
remaining three bits, 6, 5, and 4 are the time multiplier values. There are three time multiplier values so only one bit, 6, 5, or 4
may be set at one time. Setting more than one bit will result in the highest multiplier value getting precedence.
Bit 7 is the watchdog enable(1) or disable(0) bit.
The time multipliers are as follows:
Bit 6 = x1 seconds (s)
Bit 5 = x 100 milliseconds (ms)
Bit 4 = x 10 milliseconds (ms)
The register in Table 14 shows the watchdog enabled and the time value of 10 seconds. Using this technique, time values from
1.0 ms. to 10 seconds can be programmed into the watchdog.
Table 14. Watchdog SPI Configuration Register
Enable/
x1 sec.
x100 ms.
x10 ms.
8
4
2
1
Disable
1
1
0
0
1
0
1
0
5.3.6.4
Watchdog SPI Control Register
The watchdog relies on Bit 7 of the watchdog SPI control register being written as a one (1) to refresh the watchdog timer. (i.e.
reload the time value from the watchdog SPI configuration register) The watchdog SPI control register can also be loaded with
a time value to temporarily set a different value in the watchdog timer for the next cycle.
Table 15. Watchdog SPI Control Register
Refresh
x1 sec.
x100 ms.
x10 ms.
8
4
2
1
1
0
0
0
0
0
0
0
When Bits 6 thru 0 in the watchdog SPI control register are zero, the value stored in the watchdog SPI configuration register will
be loaded into the watchdog timer. If there is a temporary time value written into the watchdog SPI control register then that value
will be loaded into the watchdog. Since the watchdog SPI control register is automatically cleared to zero when the watchdog
timer is loaded, the next watchdog timer load will be from the value stored in the watchdog SPI configuration register, unless a
new temporary time value is again written to the watchdog SPI Control Register.
Example:
To enable and set the watchdog for a timeout value of 200 ms, the MCU will write the following byte into the watchdog SPI
configuration register:
Table 16.
Enable/
x1 sec.
x100 ms.
x10 ms.
8
4
2
1
Disable
1
0
1
0
0
0
1
0
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In the main loop of the MCU’s program there will be a call to a routine to write the following byte into the watchdog SPI Control
Register to refresh the watchdog periodically (must be < 200 ms).
Table 17.
WD
x1 sec.
x100 ms.
x10 ms.
8
4
2
1
Refresh
1
0
0
0
0
0
0
0
5.3.7 Low Side Drivers (LSD)
The six open drain low side drivers (LSDs) are designed to control various automotive loads such as injectors, fuel pumps,
solenoids, lamps, and relays, etc. Each driver includes off-state open load detection, on-state short to ground detection, short-
circuit to battery protection, over-current protection, over-temperature protection, and diagnostic fault reporting via the SPI. The
LSDs are individually controlled through the parallel input pins or/and via the SPI. All outputs except ROUT2 are disabled when
the KEYSW input pin is brought low regardless of the state of the input pins. All outputs, including ROUT2 are disabled when the
RESETB pin is low.
5.3.7.1
LSD Input Logic Control
The LSDs (and the pre-drivers) are controlled individually using a combination of the external pin input (if one exists) and/or a
SPI On/Off Control bit. The logic can be made to turn the outputs on or off by means of a logical combination of the external pin
ORed with the SPI Control On/Off Bit or a logical combination of the external pin ANDed with the SPI Control On/Off Bit. A
separate OR/AND select bit is found in the SPI configuration registers to accomplish this selection.
5.3.7.2
Pulse Width Modulation Mode
Besides just turning the outputs ON or OFF, the outputs can be Pulse Width Modulated (PWM’d) to control the outputs with a
variable 0 to 100% duty cycle at a selection of different frequencies. There are two built-in PWM frequencies (100 HZ and
1.0 kHz) and the external input pin can also be used as either an external PWM frequency input (divided by 100) or a total PWM
(frequency and duty cycle) input. Two bits (Bits 1, 0) in the SPI configuration register control which mode of input control is
selected.
The internal PWM duty cycles (D/C) are controlled by the lower 7 bits in the corresponding SPI control register. The duty cycle
for the internal PWM is in 1% increments and is specified in the SPI control register as a 7 bit binary word which provides 128
different binary combinations. The binary values of 0000000 to 1100100 represent 0% to 100% and the binary values 1100100
to 1111111 (100 to 127) all map to 100%.
The external PWM duty cycles (D/C) are provided by the MCU on the input pin of the corresponding output driver.
Table 18.
Bits 1, 0
PWM Frequency
PWM D/C
00
01
10
11
None or on ext. pin
100 Hz
None or on ext. pin
Internal
1.0 kHz
Internal
On ext pin 100
Internal
5.3.7.3
LSD Output Protection
Output protection consists of a dual strategy which utilizes over-current and/or over-temperature sensing to detect a fault and
then automatically control the output to protect the output device from damage.
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5.3.7.4
Over-current (OC) Protection
The first protection scheme works by sensing an over-current condition by monitoring the voltage on the individual output device
drain.
When the SPI configuration retry enable bit is set to a one (1), the default state, during an over-current event the device enters
current limit and will remain in current limit for a fixed time period. At the end of this time period the output device will turn off and
wait a delay time roughly 100 times greater than the on time. The output will try to turn on again after this off time. If the short is
still present, the process will start again. This on/off cycling will continue until the output is commanded off or the over-temperature
(OT) on the output device is reached.
If the SPI configuration register retry enable bit is set to a zero (0), this on/off cycling will not occur and the output will turn off if
the over-current threshold is reached. The output will not turn on again until the output is commanded off and then on again.
The Inrush Delay bit, in the SPI Configuration Register for each output, when set to a one(1), will prevent the over-current fault
bit from being set and the over-current protection from shutting off the output for tINRUSH time rather than tSC
.
Table 19. Inrush Delay Bit
Inrush Delay Bit
Timer Value
0
1
tSC
tINRUSH
5.3.7.5
Temperature Limit (OT) Protection
The second protection scheme works by sensing the local temperature of the individual output device. During an over-current
event, the device enters current limit and will remain in current limit until the output driver maximum temperature limit is exceeded
(OT). At this point, the device will shutdown automatically, regardless of the input state. The output will try to turn on again only
when the junction temperature falls below the maximum temperature minus the TLIM hysteresis temperature value and the input
state is commanding the output to be on. The TLIM hysteresis value is specified in the static parameter table.
The temperature limit (TLIM) protection is independent of the over-current protection and is not controlled by the SPI. TLIM is
always enabled and is always a retry operation.
Outputs may be used in parallel to drive higher current loads provided the turn-off energy of the load does not exceed the energy
rating of a single output driver.
5.3.7.6
Output Driver Diagnostics.
Over-current (OC), temperature limit (OT) exceeded, short to ground (SG), and open load (OL) conditions are reported through
the status register for each driver (no SG for the tachometer). Only open load and over-current are reported for pre-drivers. There
is also a bit in the SPI status register to indicate when any of the LSDs or pre-drivers are reporting a fault and when a particular
output has any of the four possible fault conditions present. This makes it easy for the MCU to poll for fault conditions by looking
for a single bit in one register to detect the presence of any fault in the circuit.
5.3.7.7
Open Load Pull-down Current Enable/Disable Bit
An open load condition is detected by the voltage level on the drain of the MOSFET in the off state. Internal to the device is a
pull-down current sink. This current sink may be disabled by clearing the appropriate bit in the in the LSD configuration register.
When the current sink is disabled, the off-state open load fault status bit will be forced to a logic 0.
5.3.7.8
Open Load and Short to Battery Strategy
The injectors, lamps, relays, and tachometer low side outputs are capable of detecting an open load in the off state and short to
battery condition in the on state. All faults are reported through the SPI status register communication. For open load detection,
a current source is placed between the MOSFET drain pin and ground of the IC. An open load fault is reported when the drain
voltage is less than the listed threshold. Open load fault detect threshold is set internally to the listed threshold and may not be
programmed. A shorted load fault is reported when the drain pin voltage is greater than the programmed short threshold voltage
when the device is in the on state.
The open load and short to battery fault threshold voltage is fixed and cannot be modified via the SPI.
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5.3.7.9
Short to Ground Strategy
The Injectors, Lamps, and Relays (but not the Tachometer) low side driver outputs are capable of detecting a short to ground by
measuring the current flow in the output device and comparing it to a known current value. If a short to ground is detected it is
annunciated via a bit in the appropriate SPI status register.
5.3.8 SPI REGISTER DEFINITIONS
There are three basic SPI register types:
Configuration Registers - used to set the operating modes and parameters for the 33814 functional blocks. Each output can
be configured by setting the individual bits in the configuration register for that output according to the descriptions in the previous
functional descriptions for each particular output.
Control Registers - used to turn outputs on and off and set the PWM duty cycle for outputs that are used as PWM outputs. Also
used to set the temporary operating parameters for the watchdog timer and the VRS circuit.
Status Registers - used to annunciate faults and other values that the MCU may need to act upon. Each output and functional
block has a status register associated with it and the individual fault bits for each of the faults monitored are contained in these
registers. An “Any Fault” bit, bit 7, is the OR of all the individual fault bits in the register and indicates that one or more of the fault
bits is set. There is a system-wide “Any Fault” bit in the power supply and Any Fault Status register 13, (Bit 7) whose state is the
OR of all the other “Any Fault” bits in the other status registers. The MCU can monitor this system-wide Any Fault bit to discover
if any of the outputs has a fault condition present. Once the MCU detects the system-wide Any Fault bit =1, then it must interrogate
the all the other status registers to determine the actual fault(s) that are present.
Once a fault bit in any status register is set, by the 33814 circuit, it can only be cleared by the MCU or by any of the reset actions
including a software reset.
Non-fault bits in the status register can be set and cleared by the 33814 circuit. All existing bits in the status register, bits not
marked as “x” can only be cleared by the MCU when the POST bit is zero (0). When the POST bit is one (1), the MCU can read
or write any existing bit in the status register. Non-existing bits, marked with an “x” in the table cannot be changed from the default
zero (0) value.
5.3.8.1
Existing and Non-existing Bits in the SPI Registers
Entries in the following SPI Registers marked with an “x” are non-existent bits. They are set to zero (0) by default and cannot be
changed by reading or writing to them. They should be ignored when testing registers during POST.
System On/Off Indicators
One of the registers in the status register contains the On/Off status indication of the six LSDs and three pre-driver outputs. (The
TACHOUT output is the only output not annunciated in this register). The output is considered to be On (1) whenever all of the
following conditions are true:
1. The output is commanded on via the Input pin or/and SPI bit, subject to the OR/AND logic condition selected.
2. There are no over-current (OC), short to battery (SB), or over-temperature (OT) faults present.
3. If PWM is enabled, the PWM control is set to a value greater than 0%.
4. There is no reset condition present. (OV, UV, WD, SW)
5. The 33814 is in the Normal state. (i.e. KEYSW=1)
Note: For ROUT2, the 33814 can be in either the Normal state or the Pre-shutdown state if the shutdown disable (SDD) bit is set
and PWREN=1.
If all of the five conditions above are true, the System On/Off bit for that output will be on (1).
If any of the five conditions above are false, the System On/Off bit for that output will be off (0).
5.3.8.2
Model Code and Revision Number
One status register is reserved for reporting the model code and revision of the 33814 circuits. The model code for the 33814 is
001. The revision code is the current version number for the circuit. This register is read-only.
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5.3.9 SPI Command Summary
The SPI commands are defined as 16 bits with 4 address control bits and 12 command data bits. There are 7 separate commands
that are used to set the operational parameters of device. The operational parameters are stored internally in 8-bit registers. Write
commands write the data contained in the present SPI word whereas read commands have to wait until the next SPI command
is sent to read the data requested.
Table 17 defines the commands and default state of the internal registers at POR. SPI commands may be sent to the device at
any time while the device is in the Normal state.
Messages sent are acted upon on the rising edge of the CSB input.
Bit value returned equals bit value sent for this command
Table 20. SPI Command Messages
Command
Control Address Bits
Data Bits
hex
0
15
0
14
0
13
0
12
0
11
X*
10
X*
9
8
7
6
5
4
3
2
1
0
SPI Check
X*
X*
X*
0/1
X*
0/1
X*
0/1
X*
0/1
X*
0/1
X*
0/1
X*
0/1
X*
0/1
Read Configuration
Register
1
0
0
0
1
<0000>
Internal Register Address
Write Configuration
Register
2
3
4
5
6
7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
<0000>
Internal Register Address
0/1
0/1
0/1
0/1
0/1
X*
0/1
0/1
0/1
0/1
0/1
X*
0/1
0/1
0/1
0/1
0/1
X*
0/1
0/1
0/1
0/1
0/1
X*
0/1
0/1
0/1
0/1
0/1
X*
0/1
0/1
0/1
0/1
0/1
X*
0/1
0/1
0/1
0/1
0/1
X*
0/1
0/1
0/1
0/1
0/1
X*
Read Status Register
Write Status Register
Read Control Register
Write Control Register
SPI Check Response
<0000>
Internal Register Address
<0000>
Internal Register Address
<0000>
Internal Register Address
<0000>
Internal Register Address
X*
X*
X*
X*
5.3.9.1
SPI Commands
There are seven SPI commands that can be issued by the MCU to:
• Do a SPI Check verification
• Read the contents of the SPI configuration registers
• Write the contents of the SPI configuration registers
• Read the contents of the SPI status registers
• Write the contents of the SPI status registers
• Read the contents of the SPI control registers
• Write the contents of the SPI control registers
5.3.9.2
SPI Registers
The SPI interface consists of three blocks of four, 8-bit read/write registers.
There are three types of SPI registers:
• Configuration Registers - These registers allow the MCU to configure the various parameters and options for the various
functional blocks.
• Control Registers - These registers are used to command the outputs on and off and set the PWM duty cycle values.
• Status Registers - These registers report back faults and other conditions of the various functional blocks.
The following acronyms are use in the SPI table:
• OC = over-current, could be short to battery (SB)
• OV = over-voltage
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• OT = over-temperature
• OL = open load
• SG = short to ground
• PWM = pulse width modulation
• DC = duty cycle
The following conventions are used in the SPI register tables:
• All default selections are in BOLD fonts
• Non-default selections are in normal font
• The first selection listed is the default selection
• The binary values shown, (0 or 1) are the default values after a reset has occurred.
Table 21. SPI Configuration Registers
Reg #
Hex
7
6
5
4
3
2
1
0
Injector 1 Driver
Injector 2 Driver
0
0
Retry
x
x
OL Current In-Rush
OR/AND
PWM
PWM
Delay
Enable
Sink
Freq. 1
Freq. 0
Enable
(0)
(0)
(0)
(1)
(0)
(0)
(0)
(0)
1
1
Retry
x
x
OL Current In-Rush
OR/AND
PWM
PWM
Delay
Enable
Sink
Freq. 1
Freq. 0
Enable
(0)
(0)
(0)
(1)
(0)
(0)
(0)
(0)
Relay 1 Driver
2
3
4
2
3
4
Retry
Enable
x
x
OL Current
Sink
Enable
In-Rush
Delay
OR/AND
PWM
PWM
Freq. 1
Freq. 0
(0)
(0)
(0)
(1)
(1)
(0)
(0)
(0)
Relay 2 Driver
Retry
Enable
Shutdown
DisableSD
D
x
OL Current
Sink
Enable
In-Rush
Delay
OR/AND
PWM
PWM
Freq. 1
Freq. 0
(0)
(0)
(0)
(1)
(0)
(0)
(0)
(0)
Tachometer Driver
Retry
Enable
Vrsout/LSD Vrsout/
OL Current
Sink
In-Rush
Delay
Output
Freq. 2
Output/
PWM
Output/
PWM
Osc. mode
Enable
Freq. 1
Freq. 0
(0)
(0)
(0)
(0) N16
(0) N9
(0) N4
(0) N2
(1) N1
Lamp Driver
5
5
Retry
Enable
x
x
OL Current
Sink
Enable
In-Rush
Delay
x
PWM
PWM
Freq. 1
Freq. 0
(0)
(0)
(0)
(1)
(1)
(0)
(0)
(0)
Battery Switch
Logic Output
6
7
8
6
7
8
HSD Mode
X
x
x
x
x
PWM
PWM
Freq.1
Freq. 0
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
O2 Heater
Pre-Driver
IGN/GPGD
Select
Retry
Enable
x
OL Current
Sink
x
OR/AND
PWM
PWM
Freq. 1
Freq. 0
(0)
(0)
(0)
(1)
(0)
(0)
(0)
(0)
Ignition 1 Pre-Driver
IGN/GPGD
Select
Retry
Enable
x
OL Current
Sink
x
OR/AND
PWM
PWM
Freq. 1
Freq. 0
(1)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
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Table 21. SPI Configuration Registers
Reg #
Hex
7
6
5
4
3
2
1
0
Ignition 2 Pre-Driver
9
9
IGN/GPGD
Select
Retry
Enable
x
OL Current
Sink
x
OR/AND
PWM
PWM
Freq. 1
Freq. 0
(1)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Watchdog
Parameters
10
11
A
B
Enable/
Disable
Load Time Load Time Load Time Load Time 8 Load Time 4 Load Time 2 Load Time
x1 sec
x100 ms
x10 ms
(1)
(1)
(0)
(0)
(1)
(0)
(1)
(0)
VRS Manual
Parameters
Threshold Threshold Threshold Threshold Filter Time Filter Time Filter Time Filter Time
3
2
1
0
3
2
1
0
(0)
(1)
(0)
(1)
(0)
(0)
(1)
(1)
VRS Automatic
Parameters
12
13
C
D
mantiss 8 mantiss 4 mantiss 2 mantiss 1 exponent 8 exponent 4 exponent 2 exponent 1
(0)
(1)
(1)
(1)
(0)
(0)
(1)
(1)
VRS Miscellaneous
Parameters
Man./Auto
Disable
VRS
x
High/ Low De-glitch Gnd VRSN Inv Inputs
Disable
2.5 V CM
Ref
(0)(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Table 22. SPI Control Registers
Reg #
Hex
7
6
5
4
3
2
1
0
Main OFF/ON
Control
0
0
INJ1
(0/1)
INJ2
REL1
(0/1)
X
REL2
(0/1)
LAMP
(0/1)
X
IGN1
(0/1)
IGN2
(0/1)
Tach
O2H
(0/1)
(0/1)
Other OFF/ON
Control
1
1
Pwren
POST
Enable
OFF/ON
VProt
Batsw
RESET
internal
only
OFF/ON
(0)
X
ON/OFF
(1)
OFF/ON
(0)
OFF/ON
(1)
(0)
PWM6
(0)
(0)
PWM5
(0)
(0)
PWM3
(0)
(0)
PWM0
(0)
Injector 1 Driver
Injector 2 Driver
Relay 1 Driver
Relay 2 Driver
Tachometer Driver
Lamp Driver
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
PWM4
(0)
PWM2
(0)
PWM1
(0)
(0)
X
PWM6
(0)
PWM5
(0)
PWM4
(0)
PWM3
(0)
PWM2
(0)
PWM1
(0)
PWM0
(0)
(0)
X
PWM6
(0)
PWM5
(0)
PWM4
(0)
PWM3
(0)
PWM2
(0)
PWM1
(0)
PWM0
(0)
(0)
X
PWM6
(0)
PWM5
(0)
PWM4
(0)
PWM3
(0)
PWM2
(0)
PWM1
(0)
PWM0
(0)
(0)
X
PWM6
(0)
PWM5
(0)
PWM4
(0)
PWM3
(0)
PWM2
(0)
PWM1
(0)
PWM0
(0)
(0)
X
PWM6
(0)
PWM5
(0)
PWM4
(0)
PWM3
(0)
PWM2
(0)
PWM1
(0)
PWM0
(0)
(0)
X
Batsw
PWM6
(0)
PWM5
(0)
PWM4
(0)
PWM3
(0)
PWM2
(0)
PWM1
(0)
PWM0
(0)
(0)
X
O2 Heater Pre-
Driver
PWM6
(0)
PWM5
(0)
PWM4
(0)
PWM3
(0)
PWM2
(0)
PWM1
(0)
PWM0
(0)
(0)
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Table 22. SPI Control Registers
Reg #
Hex
7
6
5
4
3
2
1
0
Ignition 1 Pre-Driver
Ignition 2 Pre-Driver
Watchdog
10
A
X
(0)
X
PWM6
(0)
PWM5
(0)
PWM4
(0)
PWM3
(0)
PWM2
(0)
PWM1
(0)
PWM0
(0)
11
12
B
C
PWM6
(0)
PWM5
(0)
PWM4
(0)
PWM3
(0)
PWM2
(0)
PWM1
(0)
PWM0
(0)
(0)
WDRFSH Load Time Load Time Load Time Load Time Load Time Load Time Load Time
x1 sec
x100 ms
x10 ms
8
4
2
1
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
VRS Conditioner
13
D
Threshold Threshold Threshold Threshold Filter Time Filter Time Filter Time Filter Time
3
2
1
0
3
2
1
0
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Table 23. SPI Status Registers
Reg #
Hex
7
6
5
4
3
2
1
0
Injector 1 Driver
Faults
0
0
Faults
x
x
x
Open Load
OL
Over -
current OC
Over-temp Short Gnd
OT
SG
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Injector 2 Driver
Faults
1
2
1
2
3
4
5
7
8
9
A
Faults
x
x
x
Open Load
OL
Over-
current OC
Over-temp Short Gnd
OT
SG
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Relay 1 Driver
Faults
Faults
x
x
x
Open Load
OL
Over-
current OC
Over-temp Short Gnd
OT
SG
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Relay 2 Driver
Faults
3
Faults
x
x
x
Open Load
OL
Over-
current OC
Over-temp Short Gnd
OT
SG
(0)
x
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Tachometer Driver
Faults
4
Faults
x
x
x
Open Load
OL
Over-
current OC
Over-temp
OT
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Lamp Driver Faults
5
Faults
x
x
x
Open Load
OL
Over-
current OC
Over-temp Short Gnd
OT
(0)
x
SG
(0)
x
(0)
(0)
(0)
(0)
(0)
(0)
O2 Heater Pre-
Driver Faults
7
Faults
x
x
x
Open Load
OL
Over-
current OC
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Ignition 1 Pre-driver
Faults
8
Faults
x
x
x
Open Load
OL
Over-
current OC
x
x
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Ignition 2 Pre-driver
Faults
9
Faults
x
x
x
Open Load
OL
Over-
current OC
x
x
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Watchdog State
10
Enable/
Disable
WD timer
bit 6
WD timer
bit 5
WD timer
bit 4
WD timer
bit 3
WD timer
bit 2
WD timer
bit 1
WD timer
bit 0
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Table 23. SPI Status Registers
VRS Conditioner
and ISO9141 Faults
11
B
Peak 8
Peak 4
Peak 2
Peak 1
x
Clamp-
active
Clamp-
active
ISO Over-
temp OT
VRSP
VRSN
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Power Supply and
Any System Faults
13
D
Any
System
Faults
Keysw
Pwren
Batsw
SPI Error
VPROT
Short to
Battery
VPROT
Over-temp
OT
VPROT
Short to
Ground
(0)
(1/0)
(0/1)
(0/1)
(0/1)
(0/1)
(0/1)
(0/1)
System On/Off
Indicators
14
15
E
F
INJ1
Off/On
INJ2
Off/On
REL1
Off/On
REL2
Off/On
LAMP
Off/On
IGN1
Off/On
IGN2
Off/On
O2H
Off/On
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Model Code/
Model
Model
Model
Rev #
Rev #
Rev #
Rev #
Rev #
Revision Number*
*Read Only except
for POST Enable
Code 2
Code 1
Code 0
(0)
(0)
(1)
(0)
(0)
(0)
(0)
(0)
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6
Typical Applications
6.0.1 Output OFF Open Load Fault
An Output OFF Open Load Fault is the detection and reporting of an open load when the corresponding output is disabled (input
bit programmed to a logic low state). The Output OFF Open Load Fault is detected by comparing the drain-to-source voltage of
the specific MOSFET output to an internally generated reference. Each output has one dedicated comparator for this purpose.
Each output has an internal pull-down current source or resistor. The pull-down current sources are enabled on power-up and
must be enabled for Open Load Detect to function. In cases were the Open Load Detect current is disabled, the status bit will
always respond with logic 0. The device will only shut down the pull-down current in Sleep mode or when disabled via the SPI.
During output switching, especially with capacitive loads, a false Output OFF Open Load Fault may be triggered. To prevent this
false fault from being reported, an internal fault filter of 100 to 450 µs is incorporated. The duration for which a false fault may be
reported is a function of the load impedance, RDS(ON), COUT of the MOSFET, as well as the supply voltage, VPWR. The rising edge
of CSB triggers the built-in fault delay timer. The timer must time out before the fault comparator is enabled to detect a faulted
threshold. Once the condition causing the Open Load Fault is removed, the device resumes normal operation. The Open Load
Fault, however, will be latched in the output SO Response register for the MCU to read.
6.0.2 Low Voltage Operation
Low voltage condition (6.5 V< VPWR <9.0 V) will operate per the command word, however parameter tables may be out of
specification and status reported on SO pin is not guaranteed.
6.0.3 Low Side Injector Driver Voltage Clamp
Each Injector output of the 33814 incorporates an internal voltage clamp to provide fast turn-OFF and transient protection. Each
clamp independently limits the drain-to-source voltage to VCL. The total energy clamped (EJ) can be calculated by multiplying the
current area under the current curve (IA) times the clamp voltage (VCL) (see Figure 12).
Characterization of the output clamps, using a repetitive pulse method at 1.0 A, indicates the maximum energy to be 100 mJ at
125 C junction temperature per output.
Drain-to-Source Clamp
Drain Voltage
Voltage (VCL = 50 V)
Clamp Energy
Drain Current
(ID= 0.3 A)
(EJ = IA x V
)
CL
Drain-to-Source ON
Voltage (VDS(ON)
)
Current
Area (I )
A
Time
GND
Figure 12. Output Voltage Clamping
6.0.4 Reverse Battery Protection
The 33814 device requires external reverse battery protection on the VPWR pin.
All outputs consist of a power MOSFET with an integral substrate diode. During a reverse battery condition, current will flow
through the load via the substrate diode. Under this condition load devices will turn on. If load reverse battery protection is
desired, a diode must be placed in series with the load.
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7
Packaging
7.1
Package Mechanical Dimensions
Package dimensions are provided in package drawings. To find the most current package outline drawing, go to
www.freescale.com and perform a keyword search for the drawing’s document number.
Table 24. 98A Reference Documents
Package
Suffix
Package Outline Drawing Number
98ASA00173D
48-Pin LQFP-EP
AE
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45
Dimensions shown are provided for reference ONLY
(For Layout and Design, refer to the Package Outline Drawing listed in the 98A Reference Documents table)
AE SUFFIX
48-PIN LQFP-EP
98ASA00173D
ISSUE A
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AE SUFFIX
48-PIN LQFP-EP
98ASA00173D
ISSUE A
33814
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AE SUFFIX
48-PIN LQFP-EP
98ASA00173D
ISSUE A
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8
Revision History
REVISION
DATE
DESCRIPTION OF CHANGES
•
•
Initial release
8/2012
1.0
Removed Freescale Confidential Proprietary on page 1
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49
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© 2012 Freescale Semiconductor, Inc.
Document Number: MC33814
Rev. 1.0
8/2012
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