PC34709VK_技术文档

Document Number: MC34709

Rev. 1.0, 8/2012

Freescale Semiconductor

Product Preview

Power Management Integrated

Circuit (PMIC) for i.MX50/53

Families

34709

The 34709 is the Power Management Integrated Circuit (PMIC)

designed primarily for use with the Freescale i.MX50 and i.MX53

families. It offers a lower cost alternative to the MC34708, targeting

embedded applications that do not require a battery charger. However,

it can be easily combined with an external charger, allowing flexibility

for either single or multi-cell Li-Ion battery configurations. It supports

both consumer and industrial applications with a single 130-pin 8x8

MAPBGA 0.5 mm pitch package that is easily routable in low cost

board designs.

POWER MANAGEMENT

VK SUFFIX (PB-FREE)

98ASA00333D

130 MAPBGA

8.0 X 8.0 (0.5 MM PITCH)

Features

• Five buck converters configurable to provide up to six independent

outputs for direct supply of the processor core, memory, and

peripherals.

Applications

Tablets

• Boost regulator for USB PHY domain on i.MX processors.

• Seven LDO regulators with internal and external pass devices for

thermal budget optimization

Smart Mobile Devices

Patient Monitors

• One low current, high accuracy, voltage reference for DDR memory

• 10-bit ADC for monitoring battery and other inputs

• Real time clock and crystal oscillator circuitry with a coin cell

backup/charger

Digital Signage

Human Machine Interfaces (HMI)

• SPI/I²C bus for control and register interface

• Four general purpose low-voltage I/Os with interrupt capability

• Two PWM outputs

ꢅꢆꢇꢈꢉꢊꢋꢌ

ꢀꢁꢂꢃꢄꢁ

ꢓꢓꢔ

ꢓꢊꢋꢌꢋꢜ

ꢂꢜꢑꢇꢖꢉꢋꢈꢝꢋꢌꢖ

ꢍꢏꢐꢑꢒ

ꢓꢀ

ꢑꢔꢋꢕ

ꢍꢖꢖꢗꢇꢎꢄꢒꢘꢃꢗꢗꢒꢄ

ꢅꢕꢖꢉꢗꢈꢘ

ꢒꢕꢢꢏꢔꢟꢉꢑꢊ

ꢍꢎ

ꢍꢏꢐ

ꢓꢊꢋꢌꢋꢜ

ꢞꢋꢈꢇꢉꢞꢜꢟꢋꢖ

ꢙꢜꢠꢋꢌ

ꢓꢙꢔꢚꢔꢛꢀ

ꢃꢬꢊꢋꢌꢟꢈꢗ

ꢀꢞꢈꢌꢭꢋꢌ

ꢙꢜꢠꢋꢌ

ꢁꢇꢈꢉꢊꢋꢌ

ꢎꢀꢙꢚꢛꢜꢝ

ꢎꢋꢓꢀ

ꢂꢕꢏꢔꢜꢟꢏꢡꢈꢊꢊꢋꢌꢘ

ꢍꢜꢑꢢꢞ

ꢓꢢꢌꢋꢋꢟ

ꢀꢜꢕꢟꢏꢀꢋꢗꢗ

ꢡꢈꢊꢊꢋꢌꢘ

ꢣꢛ

ꢀꢁꢂꢃꢄꢅꢁꢆ

ꢣ

ꢣꢣ

ꢧ

ꢛ

ꢣꢪ

ꢥ

ꢦ

ꢫ

ꢨ

ꢩ

ꢤ

ꢆꢍꢀ

Figure 1. Simplified Application Diagram

*This document contains certain information on a new product.

Specifications and information herein are subject to change without notice.

Table of Contents

1

2

Orderable Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Part Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 Format and Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.3 Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.1 Simplified Internal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4.1 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4.2 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3

4

5

5.2.1

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.3.1

5.3.2

General PMIC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6

7

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.1 Start-up Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.2 Bias and References Block Description and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.3 Clocking and Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.3.1

7.3.2

7.3.3

Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

SRTC Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Coin Cell Battery Backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.4 Interrupt Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.4.1

7.4.2

Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Interrupt Bit Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.5 Power Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.5.1

7.5.2

7.5.3

7.5.4

7.5.5

7.5.6

Power Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Power Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Buck Switching Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Boost Switching Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Linear Regulators (LDOs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

7.6 Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

7.6.1

7.6.2

7.6.3

7.6.4

7.6.5

Input Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Dedicated Readings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Touch Screen Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

ADC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

7.7 Auxiliary Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

7.7.1

7.7.2

General Purpose I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

PWM Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

7.8 Serial Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

7.8.1

7.8.2

7.8.3

SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

SPI/I2C Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

2

7.9 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

7.9.1

7.9.2

7.9.3

7.9.4

Register Set structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Specific Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

SPI/I2C Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SPI Register’s Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

8

Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

8.1 Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

8.2 Bill of Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

8.3 34709 Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

8.3.1

8.3.2

8.3.3

8.3.4

General board recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

General Routing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Parallel Routing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Switching Regulator Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

8.4 Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

8.4.1

8.4.2

Rating Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Estimation of Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

9

Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

9.1 Package Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

10 Reference Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

11 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

34709

Analog Integrated Circuit Device Data

3

Freescale Semiconductor

Orderable Parts

1

Orderable Parts

This section describes the part numbers available to be purchased, along with their differences. Valid orderable part numbers

are provided on the web. To determine the orderable part numbers for this device, go to http://www.freescale.com and perform

a part number search for the following device numbers.

Table 1. Orderable Part Variations

Part Number ⁽¹⁾

Temperature (T )

Package

A

PC34709VK

Notes

-40 to 85 °C

130 MAPBGA - 8.0 x 8.0 mm - 0.5 mm Pitch

1. To Order parts in Tape & Reel, add the R2 suffix to the part number.

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

4

Part Identification

2

Part Identification

This section provides an explanation of the part numbers and their alpha numeric breakdown.

2.1

Description

Part numbers for the chips have fields that identify the specific part configuration. You can use the values of these fields to

determine the specific part you have received.

2.2

Format and Examples

Part numbers for a given device have the following format, followed by a device example:

Table 2 - Part Numbering - Analog:

PC tt xxx r v PPP RR - PC34709VKR2

2.3

Fields

These tables list the possible values for each field in the part number (not all combinations are valid).

Table 2: Part Numbering - Analog

FIELD

PC

DESCRIPTION

VALUES

• MC- Qualified Standard

• PC- Prototype Device

Product Category

• 33 = -40 °C to > 105 °C

• 34 = -40 °C to  105 °C

• 35 = -55 °C to  125 °C

tt

Temperature Range

xxx

r

Product Number

Revision

• Assigned by Marketing

• (default blank)

v

Variation

• (default blank)

PPP

RR

Package Identifier

Tape and Reel Indicator

• Varies by package

• R2 = 13 inch reel hub size

34709

Analog Integrated Circuit Device Data

5

Freescale Semiconductor

Internal Block Diagram

3

Internal Block Diagram

3.1

Simplified Internal Diagram

SW1IN

SW1ALX

GNDSW1A

SW1FB

O/P

Drive

SW1

Dual Phase

GP

2000 mA

Buck

SW1CFG

SW1VSSSNS

GNDADC

SW1BLX

O/P

10 Bit GP

ADC

Drive

GNDSW1B

A/D Result

DVS

CONTROL

ADIN9

SW1PWGD

ADIN10

ADIN11

A/D

Control

SW2IN

SW2LX

GNDSW2

SW2FB

SW2PWGD

MUX

O/P

Drive

SW2

ADIN12/TSX1

ADIN13/TSX2

ADIN14/TSY1

LP

`

1000 mA

Buck

Touch

Screen

ADIN15/TSY2

TSREF

Interface

Die Temp &

Thermal Warning

Detection

SW3IN

To Interrupt

Section

SW3

INT MEM

500 mA

Buck

O/P

Drive

SW3LX

GNDSW3

SW3FB

SW4AIN

SW4ALX

GNDSW4A

SW4FBA

O/P

Drive

SW4

Dual Phase

DDR

SW4CFG

1000 mA

Buck

Package Pin Legend

SW4BIN

SW4BLX

GNDSW4B

SW4BFB

O/P

Drive

Output Pin

Input Pin

SPIVCC

Shift Register

Bi-directional Pin

CS

SPI

Interface

+

Muxed

I2C

Optional

Interface

SW5IN

CLK

SW5

I/O

1000 mA

Buck

O/P

Drive

SW5LX

GNDSW5

SW5FB

SPI

MOSI

MISO

To Enables & Control

Registers

GNDSPI

Shift Register

SWBSTIN

SWBSTLX

SWBSTFB

O/P

Drive

SWBST

380 mA

Boost

GNDSWBST

VCORE

VCOREDIG

VDDLP

Reference

Generation

VINREFDDR

VHALF

VCOREREF

VREFDDR

10mA

GNDCORE

GNDREF

VREFDDR

BP

VINPLL

VPLL

50 mA

Pass

FET

VUSB2DRV

VUSB2

Pass

FET

VUSB2

250mA

VDACDRV

VDAC

250mA

To

Trimmed

Circuits

SPI

Trim-In-Package

Control

Logic

VINGEN1

VGEN1

250mA

Pass

FET

Startup

Sequencer

Decode

Trim

Control

Logic

VGEN2DRV

VGEN2

PUMSx

PLL

Switchers

Pass

FET

VGEN2

250mA

VINUSB

Monitor

Timer

VUSB

Regulator

VUSB

RTC +

Calibration

32 KHz

Internal

Osc

LDOVDD

GNDUSB

SPI Result

Registers

Interrupt

Inputs

Enables &

Control

32 KHz

Buffers

Best

of

Supply

GNDREG1

GNDREG2

GNDREF1

GNDREF2

BP

LCELL

Switch

LICELL

PWM

Outputs

32 KHz

Crystal

Osc

GPIO Control

Li Cell

Charger

Core Control Logic, Timers, & Interrupts

Digital Core

VSRTC

Figure 2. Simplified Internal Block Diagram

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

6

Pin Connections

4

Pin Connections

4.1

Pinout Diagram

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

A

B

C

D

E

F

MISO

CS

GNDSPI

MOSI

SPIVCC

INT

GLBRST

RESETB

PWRON1

GNDCTRL

PWM2

PWM1

ICTEST

GPIOLV2

GNDGPIO

SW2LX

GNDSW2

SW2FB

GNDREF2

SW2PWGD

SW3FB

NC_2

CLK

GNDUSB

VINUSB

XTAL1

GPIOLV1

GPIOLV0

SW2IN

NC_3

GPIOVDD

VUSB

RESETBMCU

PWRON2

PUMS4

SDWNB

PUMS5

PUMS3

PUMS1

ADIN9

GNDSW3

SW3IN

SW3LX

CLK32K

SUBSPWR1

SUBSGND

SUBSREF

GPIOLV3

SUBSANA2

SUBSPWR3

SUBSLDO

SUBSPWR2

GNDRTC

XTAL2

CLK32KVCC

CLK32KMCU

SUBSPWR1

SUBSPWR

GNDSWBST

SWBSTLX

VINGEN1

VINREFDDR

VPLL

SWBSTIN

G

H

J

PUMS2

GNDCORE

VCOREDIG

VCOREREF

VDDLP

VSRTC

VCORE

GNDADC

ADIN10

VGEN1

GNDREG2

SUBSANA1

SW1CFG

SWBSTFB

VHALF

ADIN11

TSREF

TSY1

K

L

WDI

TSX1

SW1PWGD

VREFDDR

VINPLL

TSY2

TSX2

VGEN2DRV

GNDREG1

VDACDRV

VUSB2DRV

VUSB2

M

N

P

R

GNDREF

BP

LICELL

SW4AFB

SW4BFB

SW4CFG

SW5FB

VGEN2

GNDREF1

GNDSW1A

SW1ALX

LDOVDD

VDAC

STANDBY

NC_1

GNDSW4A

SW4ALX

SW4AIN

SW4BIN

GNDSW4B

SW4BLX

SW5IN

GNDSW5

SW5LX

SW1IN

GNDSW1B

SW1FB

SW1BLX

SW1VSSSNS

Figure 3. Top View Ballmap

34709

Analog Integrated Circuit Device Data

7

Freescale Semiconductor

Pin Connections

4.2

Pin Definitions

Table 3. Pin Definitions

Function

Rating

[V]

Pin Number

Supply

N1

Pin Name

# Balls

Definition

1. Application supply point

BP

I

5.5

3.6

1

2. Input supply to the IC core circuitry

Indication of imminent system shutdown

D6

IC Core

J2

SDWNB

O

Regulated supply for the IC analog core circuitry

Regulated supply for the IC digital core circuitry

Main bandgap reference

VCORE

VCOREDIG

VCOREREF

VDDLP

O

-

1

J1

K1

O

VDDLP reference

L1

O

Ground for the IC core circuitry

H1

GNDCORE

GNDREF

GND

Ground reference for IC core circuitry

M1

Switching Regulators

P10

Regulator 1 input

SW1IN

I

5.5

2

P11

R9

Regulator 1A switch node connection

Regulator 1 feedback

SW1ALX

SW1FB

O

5.5

3.6

-

1

P13

P9

I

Ground for Regulator 1A

Regulator 1 sense

GNDSW1A

SW1VSSSNS

SW1PWGD

SW1BLX

GNDSW1B

SW1CFG

SW2IN

GND

R13

K10

R11

P12

L12

B11

A10

A12

B10

A13

E14

D15

B13

D14

B12

P4

GND

-

Power good signal for SW1

Regulator 1B switch node connection

Ground for Regulator 1B

Regulator 1A/B mode configuration

Regulator 2 input

O

3.6

5.5

-

O

GND

I

3.6

5.5

3.6

-

I

Regulator 2 switch node connection

Regulator 2 feedback

SW2LX

O

SW2FB

I

Ground for Regulator 2

GNDSW2

SW2PWGD

SW3IN

GND

Power good signal for SW2

Regulator 3 input

O

3.6

5.5

3.6

-

I

Regulator 3 switch node connection

Regulator 3 feedback

SW3LX

O

SW3FB

I

Ground for Regulator 3

GNDSW3

GNDREF2

SW4AIN

GND

Ground reference for Regulators

Regulator 4A input

GND

-

I

O

I

5.5

3.6

Regulator 4A switch node connection

Regulator 4A feedback

R3

SW4ALX

SW4AFB

N2

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

8

Pin Connections

Table 3. Pin Definitions (continued)

Rating

[V]

Pin Number

Pin Name

# Balls

Definition

Function

Ground for Regulator 4A

Regulator 4B input

P3

GNDSW4A

SW4BIN

GND

-

1

P5

I

5.5

3.6

-

Regulator 4B switch node connection

Regulator 4B feedback

R6

SW4BLX

SW4BFB

GNDSW4B

SW4CFG

SW5IN

O

P2

I

Ground for Regulator 4B

Regulator 4A/B mode configuration

Regulator 5 input

P6

GND

M6

I

3.6

5.5

3.6

-

P7

I

Regulator 5 output

R8

SW5LX

O

Regulator 5 feedback

M8

SW5FB

I

GND

I

Ground for Regulator 5

P8

GNDSW5

GNDREF1

SWBSTIN

SWBSTLX

SWBSTFB

GNDSWBST

Ground reference for regulators

Boost Regulator BP supply

SWBST switch node connection

Boost Regulator feedback

Ground for regulator boost

N9

-

F15

5.5

7.5

5.5

-

G14

O

H15

I

F14

GND

LDO Regulators

VREFDDR input supply

J14

K15

J15

L15

K14

N14

P15

N15

D2

VINREFDDR

VREFDDR

VHALF

I

3.6

1.5

5.5

2.5

5.5

3.6

5.5

3.6

5.5

-

1

VREFDDR regulator output

O

Half supply reference for VREFDDR

VPLL input supply

O

VINPLL

I

VPLL regulator output

VPLL

O

Drive output for VDAC regulator using an external PNP device

VDAC regulator output

VDACDRV

VDAC

O

Supply pin for VUSB2, VDAC, and VGEN2

USB transceiver regulator output

VUSB input supply

LDOVDD

VUSB

I

O

D1

VINUSB

GNDUSB

I

Ground for VUSB LDO

C1

GND

1. VUSB2 input using internal PMOS FET

2. Drive output for VUSB2 regulator using an external PNP device

VUSB2 regulator output

I

O

P14

VUSB2DRV

5.5

1

R14

H14

H12

VUSB2

VINGEN1

VGEN1

O

3.6

2.5

1

VGEN1 input supply

I

VGEN1 regulator output

O

1. VGEN2 input using internal PMOS FET

2. Drive output for VGEN2 regulator using an external PNP device

VGEN2 regulator output

I

L14

VGEN2DRV

5.5

1

O

M15

H2

VGEN2

VSRTC

O

3.6

2.5

-

1

Output regulator for SRTC module on processor

Ground for Regulator 1

O

M14

GNDREG1

GND

34709

Analog Integrated Circuit Device Data

9

Freescale Semiconductor

Pin Connections

Table 3. Pin Definitions (continued)

Rating

[V]

Pin Number

Pin Name

# Balls

Definition

Function

Ground for Regulator 2

Supply for GPIOLV pins

J12

C8

C7

B7

GNDREG2

GPIOVDD

GPIOLV0

GPIOLV1

GPIOLV2

GPIOLV3

PWM1

GND

I

-

1

2.5

-

General purpose input/output 1

General purpose input/output 2

General purpose input/output 3

General purpose input/output 4

PWM output 1

I/O

O

B9

E10

A8

PWM output 2

A7

PWM2

O

GPIO ground

C9

GNDGPIO

GND

Clock/RTC/Coin Cell

1. Coin cell supply input

I

M2

LICELL

3.6

1

2. Coin cell charger output

O

32.768 kHz Oscillator crystal connection 1

32.768 kHz Oscillator crystal connection 2

Ground for the RTC block

E1

XTAL1

XTAL2

I

2.5

-

1

G1

I

GND

I

F1

GNDRTC

CLK32KVCC

CLK32K

Supply voltage for 32 k buffer

F3

3.6

32 kHz Clock output for peripherals

32 kHz Clock output for processor

E3

O

G3

CLK32KMCU

O

Control Logic

Reset output for peripherals

Reset output for processor

Watchdog input

B5

D5

K3

P1

B4

A6

E5

A5

G6

G5

F6

F5

E6

A9

B6

A4

B2

B1

RESETB

RESETBMCU

WDI

O

3.6

-

1

O

I

Standby input signal from processor

Interrupt to processor

STANDBY

INT

I

O

Power on/off button connection 1

Power on/off button connection 2

Global Reset

PWRON1

PWRON2

GLBRST

PUMS1

PUMS2

PUMS3

PUMS4

PUMS5

ICTEST

GNDCTRL

SPIVCC

CS

I

Power up mode supply setting 1

Power up mode supply setting 2

Power up mode supply setting 3

Power up mode supply setting 4

Power up mode supply setting 5

Normal mode, test mode selection, & anti-fuse bias

Ground for control logic

I

GND

Supply for SPI bus

I

3.6

Primary SPI select input

Primary SPI clock input

CLK

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

10

Pin Connections

Table 3. Pin Definitions (continued)

Rating

[V]

Pin Number

Pin Name

# Balls

Definition

Function

Primary SPI write input

Primary SPI read output

Ground for SPI interface

B3

MOSI

MISO

I

3.6

-

1

A2

O

A3

GNDSPI

GND

A to D Converter

ADC generic input channel 9

H6

J5

ADIN9

ADIN10

ADIN11

TSX1

I

4.8

-

1

ADC generic input channel 10

I

ADC generic input channel 11

J6

I

Touch Screen Interface X1 or ADC generic input channel 12

Touch Screen Interface X2 or ADC generic input channel 13

Touch Screen Interface Y1 or ADC generic input channel 14

Touch Screen Interface Y2 or ADC generic input channel 15

Touch screen reference

K5

L4

L6

L3

K6

H5

I

TSX2

I

TSY1

I

TSY2

TSREF

GNDADC

O

Ground for A to D circuitry

GND

Substrate Grounds

Substrate ground connection

K8

K9

SUBSREF

GND

-

1

SUBSPWR

E8

F8

F9

G8

G9

H8

H9

J9

Substrate ground connection

SUBSPWR1

GND

-

8

Substrate ground connection

E11

G10

SUBSPWR2

SUBSPWR3

SUBSLDO

GND

-

1

H10

K12

SUBSANA1

SUBSANA2

SUBSGND

F10

J8

No connects

A14

B15

R1

Do not connect

NC

-

3

34709

Analog Integrated Circuit Device Data

11

Freescale Semiconductor

General Product Characteristics

5

General Product Characteristics

5.1

Maximum Ratings

Table 4. Maximum Ratings

All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent

damage to the device.

Symbol

Description (Rating)

Min.

Max.

Unit

Notes

ELECTRICAL RATINGS

-

ICTEST Pin Voltage

V

V_ICTEST

V_BP

1.8

4.5

3.6

BP Voltage

Coin Cell Voltage

V_LICELL

ESD Ratings

(2)

-

• Human Body Model All pins

• Charge Device Model All pins

V_ESD

2000

500

Notes

2. ESD testing is performed in accordance with the Human Body Model (HBM) (C_ZAP= 100 pF, R_ZAP= 1500 ), and the Charge Device

Model (CDM), Robotic (C_ZAP= 4.0 pF).

5.2

Thermal Characteristics

Table 5. Thermal Ratings

All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent

damage to the device.

Symbol

Description (Rating)

Min.

Max.

Unit

Notes

THERMAL RATINGS

Ambient Operating Temperature Range

Operating Junction Temperature Range

-

°C

T_A

T_J

-40 to 85

-40 to 125

-65 to 150

Note 3

Storage Temperature Range

°C

T_ST

(3), (4)

Peak Package Reflow Temperature During Reflow

T_PPRT

THERMAL RESISTANCE AND PACKAGE DISSIPATION RATINGS

(5), (6)

(5), (7)

Junction to Ambient Natural Convection

R_θJA

-

93

53

80

49

°C/W

• Single layer board (1s)

Junction to Ambient Natural Convection

R_θJMA

• Four layer board (2s2p)

Junction to Ambient (@200 ft/min.)

R_θJMA

• Single layer board (1s)

Junction to Ambient (@200 ft/min.)

R_θJMA

• Four layer board (2s2p)

(8)

(9)

Junction to Board

R_θJB

-

34

25

°C/W

Junction to Case

R_θJC

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

12

General Product Characteristics

Table 5. Thermal Ratings (continued)

All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent

damage to the device.

Symbol

Description (Rating)

Min.

Max.

Unit

Notes

THERMAL RESISTANCE AND PACKAGE DISSIPATION RATINGS (CONTINUED)

(10)

Junction to Package Top

-

JT

6.0

°C/W

• Natural Convection

Notes

3. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may

cause a malfunction or permanent damage to the device.

4. Freescale's Package Reflow capability meets the Pb-free requirements for JEDEC standard J-STD-020C, for Peak Package Reflow

Temperature and Moisture Sensitivity Levels (MSL).

5. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient

temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

6. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.

7. Per JEDEC JESD51-6 with the board horizontal.

8. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top

surface of the board near the package.

9. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).

10. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per

JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

5.2.1

Power Dissipation

During operation, the temperature of the die should not exceed the maximum junction temperature. To optimize the thermal

management scheme and avoid overheating, the 34709 PMIC provides a thermal management system. The thermal protection

is based on a circuit with a voltage output that is proportional to the absolute temperature. This voltage can be read out via the

ADC for specific temperature readouts, see Serial Interfaces.

This voltage is monitored by an integrated comparator. Interrupts THERM110, THERM120, THERM125, and THERM130 will be

generated when respectively crossing in either direction of the thresholds specified in Table 6. The temperature range can be

determined by reading the THERMxxxS bits.

Thermal protection is integrated to power off the 34709 PMIC, in case of over dissipation. This thermal protection will act above

the maximum junction temperature to avoid any unwanted power downs. The protection is debounced for 8.0 ms in order to

suppress any (thermal) noise. This protection should be considered as a fail-safe mechanism and therefore the application

design should be dimensioned such that this protection is not tripped under normal conditions. The temperature thresholds and

the sense bit assignment are listed in Table 6.

Table 6. Thermal Protection Thresholds

Parameter

Thermal 110 °C threshold (THERM110)

Min

Typ

Max

Units

Notes

105

115

120

125

2.0

110

120

125

130

-

115

125

130

135

4.0

°C

Thermal 120 °C threshold (THERM120)

Thermal 125 °C threshold (THERM125)

Thermal 130 °C threshold (THERM130)

Thermal warning hysteresis

(11)

Thermal protection threshold

130

140

150

Notes

11. Equivalent to approx. 30 mW min, 60 mW max

34709

Analog Integrated Circuit Device Data

13

Freescale Semiconductor

General Product Characteristics

5.3

Electrical Characteristics

General PMIC Specifications

5.3.1

Table 7. General Electrical Characteristic

Internal

Pin Name

Max ⁽¹⁹⁾

Parameter

Load Condition

Min

Unit

Notes

Termination ⁽¹⁶⁾

(13)

(18)

Input Low

Input High

47 kOhm

1.0 MOhm

-

0.0

0.3

VCOREDIG

0.3

V

PWRON1, PWRON2,

GLBRST

Pull-up

1.0

Input Low

0.0

STANDBY, WDI

CLK32K

Weak Pull-down

CMOS

Input High

Output Low

Output High

Output Low

Output High

Output Low

-

0.9

3.6

-100 A

100 A

-100 A

100 A

-2.0 mA

0.0

CLK32KVCC - 0.2

0.0

0.2

CLK32KVCC

0.2

CLK32KMCU

CMOS

VSRTC - 0.2

0.0

VSRTC

0.4

(17)

RESETB,

Open-drain

RESETBMCU,

SDWNB, SW1PWGD,

SW2PWGD

Output High

Open-drain

-

3.6

V

Off /Coin cell mode

1.15

1.28

PUMS[4 :0] =

(0110, 0111, 1000,

1001)

1.2 V setting

1.3 V setting

1.15

1.25

1.35

V

VSRTC

Voltage Output

PUMS[4 :0] =

(0110, 0111, 1000,

1001)

Input Low

-

0.0

0.3 * GPIOVDD

GPIOVDD + 0.3

0.2

V

Input High

Output Low

Output High

Output Low

Output High

Output Low

Output High

Input Low

-

0.7 * GPIOVDD

CMOS

-

0.0

GPIOLV1,2,3,4

-

GPIOVDD - 0.2

GPIOVDD

0.4

-2.0 mA

0.0

Open-drain

CMOS

Open-drain

-

GPIOVDD + 0.3

0.2

-

0.0

PWM1, PWM2

CLK, MOSI

CS

GPIOVDD - 0.2

GPIOVDD

0.3 * SPIVCC

SPIVCC + 0.3

0.4

(12)

0.0

Input High

Input Low

0.7 * SPIVCC

0.0

Weak Pull-down

Input High

Input Low

1.1

0.0

SPIVCC + 0.3

0.3 * VCOREDIG

VCOREDIG

(12) (20)

,

Weak Pull-down

on CS

CS, MOSI (at Booting

for SPI / I²C decoding)

(12) (20)

Input High

0.7 * VCOREDIG

,

MISO

Output Low

Output High

-100 A

100 A

0.0

0.2

V

(12) (21)

MISO, INT

CMOS

MISO

SPIVCC - 0.2

SPIVCC

(12) (21)

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

14

General Product Characteristics

Table 7. General Electrical Characteristic

Internal

Pin Name

Max ⁽¹⁹⁾

0.3

Parameter

Input Low

Load Condition

Min

0.0

1.0

Unit

V

Notes

Termination ⁽¹⁶⁾

(14)

-

PUMSxS = 0

PUMS1,2,3,4,5

ICTEST

Input High

PUMSxS = 1

(14)

VCOREDIG

V

(15)

Input Low

Input High

Input Low

Input Mid

Input High

-

0.0

1.1

0.0

1.3

2.5

0.3

1.7

0.3

2.0

3.1

V

SW1CFG, SW4CFG

ADIN8,9,10

Input must not

exceed

-

BP

V

TSX1,TSX2, TSY1,

TSY2

Input must not

exceed

BP or VCORE

Notes

12. SPIVCC is typically connected to the output of buck regulator SW5 and set to 1.800 V

13. Input has internal pull-up to VCOREDIG equivalent to 200 kOhm

14. Input state is latched in first phase of cold start, refer to Serial Interfaces for a description of the PUMS configuration

15. Input state is not latched

16. A weak pull-down represents a nominal internal pull-down of 100 nA, unless otherwise noted

17. RESETB, RESETBMCU, SDWNB, SW1PWGD, SW2PWGD have open-drain outputs, external pull-ups are required

18. SPIVCC needs to remain enabled for proper detection of WDI High to avoid involuntary shutdown

19. The maximum should never exceed the maximum rating of the pin as given in Pin Connections

20. The weak pull-down on CS is disabled if a VIH is detected at start-up to avoid extra consumption in I²C mode

21. The output drive strength is programmable

34709

Analog Integrated Circuit Device Data

15

Freescale Semiconductor

General Product Characteristics

5.3.2

Current Consumption

The current consumption of the individual blocks is described in detail throughout this specification. For convenience, a summary

table follows for standard use cases.

Table 8. Current Consumption Summary ⁽²⁴⁾

Characteristics noted under conditions BP = 3.6 V, -40 C  T_A 85 C, unless otherwise noted. Typical values at BP = 3.6 V

and T_A= 25 °C under nominal conditions, unless otherwise noted.

Mode

Description

Typ

Max

Unit

Notes

All blocks disabled, BP=0, coin cell is attached to LICELL 

(at 25 °C only)

• RTC Logic

RTC / Power

cut

• VCORE Module

• VSRTC

4.0

7.0

A

• 32 k Oscillator

• Clk32KMCU buffer active(10 pF load)

All blocks disabled, BP>3.0 V(at 25 °C only)

• Digital Core

• RTC Logic

• VCORE Module

OFF (good

battery)

20

55

A

• VSRTC

• 32 k Oscillator

• CLK32KMCU buffer active (10 pF load)

• COINCHEN = 0

Low-power Mode (Standby pin asserted and ON_STBY_LP=1)

• Digital core

• RTC logic

• VCORE module

• VSRTC

• CLK32KMCU/CLK32K active (10 pF load)

ON Standby

260

650

A

• 32 k oscillator

• I_REF

• SW1, SW2, SW3, SW4A, SW4B, SW5 in PFM ^(23),(27)

• VDDREF, VPLL, VGEN1, VGEN2, VUSB2, VDAC

in low-power mode ^(22),(25)

• Digital core

• RTC logic

• VCORE module

• VSRTC

• CLK32KMCU/CLK32K active (10 pF load)

• 32 k oscillator

• Digital

ON Standby

370

750

A

• I_REF

• SW1, SW2, SW3, SW4A, SW4B, SW5 in PFM ^(23),(27)

• VDDREF, VPLL, VGEN1, VGEN2, VUSB2, VDAC on 

in low-power mode ^(23),(25)

• PLL

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

16

General Product Characteristics

Table 8. Current Consumption Summary ⁽²⁴⁾

Characteristics noted under conditions BP = 3.6 V, -40 C  T_A 85 C, unless otherwise noted. Typical values at BP = 3.6 V

and T_A= 25 °C under nominal conditions, unless otherwise noted.

Mode

Description

Typ

Max

Unit

Notes

Typical use case

• Digital core

• RTC logic

• VCORE module

• VSRTC CLK32KMCU/CLK32K active (10 pF)

• 32 k oscillator

• I_REF

ON

1600

3000

A

• SW1, SW2, SW3, SW4A, SW4B, SW5 in APS SWBST ^{(23),(26),(27)}

• VDDREF, VPLL, VGEN1, VGEN2, VUSB2, VDAC on 

in low-power mode ^(22),(25)

• Digital

• PLL

Notes

22. Equivalent to approx. 30 mW min, 60 mW max

23. Current in RTC Mode is from LICELL=2.5 V; in all other modes from BP = 3.6 V.

24. External loads are not included

25. VUSB2, VGEN2 external pass PNPs

26. SWBST in auto mode

27. SW4A output 2.5 V

34709

Analog Integrated Circuit Device Data

17

Freescale Semiconductor

General Description

6

General Description

The 34709 is the PMIC designed specifically for use with the Freescale i.MX50 and i.MX53 families. As the companion PMIC on

several i.MX reference designs, it is a proven solution, which enables a faster time to market with fewer resources.

6.1

Features

Power Generation

• Five buck switching regulators

• Two single/dual phase buck regulators

• Three single phase buck regulators

• Up to six independent outputs

• PFM/Auto pulse skip/PWM operation mode

• Dynamic voltage scaling

• 5 V boost regulator

• Support for USB physical layer on i.MX processor (USB PHY)

• Seven LDO regulators

• Two with selectable internal or external pass devices

• Four with embedded pass devices

• One with an external PNP device

• One voltage reference for DDR memory with internal PMOS device

Analog to Digital Converter

• Seven general purpose channels

• Eight dedicated channels for monitoring the charger

• Resistive touchscreen interface

Auxiliary Circuits

• General purpose I/Os

• PWM outputs

Clocking and Oscillators

• Real time clock

• Time and day counters

• Time of day alarm

• 32.768 kHz crystal oscillator

• Coin cell battery backup

• Coin cell charger

Serial Interface

• SPI

• I²C

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

18

General Description

6.2

Block Diagram

FIVE BUCK

REGULATORS

Processor Core

Split Power Domains

DDR Memory

I/O

10 BIT ADC CORE

General Purpose

Resistive Touch

Screen Interface

SEVEN LDO

REGULATORS

Peripherals

5.0 V BOOST

REGULATOR

CONTROL

INTERFACE

SPI/I²C

POWER CONTROL

LOGIC

PC34709

State Machine

BIAS &

REFERENCES

Trimmed Bandgap

DDR Memory Voltage

Reference

32.768 kHz CRYSTAL OSCILLATOR

Real Time Clock

GENERAL PURPOSE

I/O & PWM OUTPUTS

SRTC Support

Coin Cell charger

Figure 4. Functional Block Diagram

6.3

Functional Description

The 34709 Power Management Integrated Circuit (PMIC) represents a complete system power solution in a single package.

Designed primarily for use with the Freescale i.MX50/53 families. The 34709 integrates five multi-mode buck regulators and

seven LDO regulators and one voltage reference for direct supply of the processor core, memory, and peripherals.

The 34709 also integrates a real time clock, coin cell charger, a 16-channel 10-bit ADC, 5.0 V USB boost regulator, two PWM

outputs, touch-screen interface, status LED drivers, and four GPIOs.

34709

Analog Integrated Circuit Device Data

19

Freescale Semiconductor

Functional Block Description

7

Functional Block Description

7.1

Start-up Requirements

At power-up, switching and linear regulators are sequentially enabled in time slots of 2.0 ms steps, to limit the inrush current after

an initial delay of 8.0 ms, in which the core circuitry gets enabled. To ensure a proper power-up sequence, the outputs of the

switching regulators that are not enabled, are discharged at the beginning of the Cold start with weak pull-downs on the output.

For that same reason, an 8.0 ms delay allows the outputs of the linear regulators to be fully discharged as well, through the built

in discharge path. The peak inrush current per event is limited. Any under-voltage detection at BP is masked while the power-up

sequencer is running. When the switching regulator is enabled, it will start in PWM mode for 3.0 ms. Then it will switch over to

the mode that it is programmed to in the SPI.

The Power-up Mode Select pins PUMSx (x = 1,2,3,4,5) are used to configure the start-up characteristics of the regulators. Supply

enabling and output level options are selected by hardwiring the PUMSx pins for the desired configuration. The recommended

power-up strategy for end products is to bring up as little of the system as possible at booting, essentially sequestering just the

bare essentials to allow processor start-up and software to run. With such a strategy, the start-up transients are controlled at

lower levels, and the rest of the system power tree can be brought up by software. This allows optimization of supply ordering,

where specific sequences may be required, as well as supply default values. Software code can load up all of the required

programmable options, to avoid sneak paths, under/over-voltage issues, start-up surges, etc, without any change in hardware.

The state of the PUMSx pins are latched in before any of the switching or linear regulators are enabled, with the exception of

VCORE. PUMSx options and start-up configurations will be robust to a PCUT event, whether occurring during normal operation

or during the 8.0 ms of pre-sequencer initialization, i.e., the system will not end up in an unexpected / undesirable consumption

state.

Table 9 shows the initial setup for the voltage level of the switching and linear regulators, and whether they get enabled.

Table 9. Power-up Defaults

53

LPM

53

DDR2

53

DDR3

53

LVDDR3

53

LVDDR2

i.MX

Reserved

50

PUMS[4:1]

0000-0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

PUMS5=0

VUSB2

VGEN2

Ext PNP Ext PNP Ext PNP

Ext PNP

Ext PNP Ext PNP Ext PNP Ext PNP Ext PNP Ext PNP

Reserved

PUMS5=1

VUSB2

VGEN2

Internal

PMOS

Internal

PMOS

Internal

PMOS

SW1A

(VDDGP)

Reserved

1.1

1.3

1.8

1.1

1.3

1.2

1.5

1.1

1.3

1.2

1.1

1.2

1.8

1.1

1.2

1.1

1.2

3.15

1.2

1.1

1.2

3.15

1.8

SW1B

(VDDGP)

(28)

SW2

1.225

1.2

1.3

1.2

(VCC)

(28)

SW3

1.2

(VDDA)

(28)

SW4A

1.5

1.35

3.15

1.2

3.15

1.8

(DDR/SYS)

(28)

SW4B

1.5

(DDR/SYS)

(28)

SW5

Reserved

1.8

Off

1.8

Off

1.8

Off

1.8

Off

1.8

Off

1.8

Off

1.8

Off

1.8

Off

1.8

Off

1.8

Off

1.8

Off

(I/O)

SWBST

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

20

Functional Block Description

Table 9. Power-up Defaults

53

LPM

53

DDR2

53

DDR3

53

LVDDR3

53

LVDDR2

i.MX

Reserved

50

(29)

VUSB

VUSB2

VSRTC

VPLL

Reserved

3.3

2.5

3.3

2.5

3.3

2.5

3.3

2.5

3.3

2.5

3.3

2.5

1.2

1.8

On

2.5

1.2

3.1

3.3

2.5

1.2

1.8

On

2.5

1.2

3.1

3.3

2.5

1.2

1.8

On

2.5

1.2

3.1

3.3

2.5

1.2

1.8

On

2.5

1.2

3.1

3.3

2.5

1.2

1.8

On

2.5

1.2

2.5

3.3

2.5

1.2

1.8

On

2.5

1.2

2.5

1.2

1.3

1.8

VREFDDR

VDAC

On

2.775

1.2

2.775

1.3

2.775

1.3

2.775

1.3

2.775

1.3

VGEN1

VGEN2

Notes

2.5

28. The SWx node are activated in APS mode when enabled by the start-up sequencer.

29. VUSB is supplied by SWBST.

The power-up sequence is shown in Tables 10 and 11. VCOREDIG, VSRTC, and VCORE, are brought up in the pre-sequencer

start-up.

Table 10. Power-up Sequence i.MX53

Tap x 2.0 ms

PUMS [4:1] = [0101,0110,0111,1000,1001] (i.MX53)

0

1

2

3

4

5

6

7

8

9

SW2 (VCC)

VPLL (NVCC_CKIH = 1.8 V)

VGEN2 (VDD_REG= 2.5 V, external PNP

SW3 (VDDA)

SW1A/B (VDDGP)

SW4A/B, VREFDDR (DDR/SYS)

SW5 (I/O), VGEN1

VUSB, VUSB2

VDAC

Table 11. Power-up Sequence i.MX50

Tap x 2.0 ms PUMS [4:1] = [0100, 1011, 1100, 1101, 1110, 1111] (i.MX50/I.MX53)

0

1

2

3

4

5

6

7

8

9

SW2

SW3

SW1A/B

VDAC

SW4A/B, VREFDDR

SW5

VGEN2, VUSB2

VPLL

VGEN1

VUSB

34709

Analog Integrated Circuit Device Data

21

Freescale Semiconductor

Functional Block Description

7.2

Bias and References Block Description and Application

Information

All regulators use the main bandgap as the reference. The main bandgap is bypassed with a capacitor at REFCORE. The

bandgap and the rest of the core circuitry is supplied from VCORE. The performance of the regulators is directly dependent on

the performance of VCOREDIG and the bandgap. No external DC loading is allowed on VCOREDIG or REFCORE. VCOREDIG

is kept powered as long as there is a valid supply and/or coin cell. Table 12 shows the main characteristics of the core circuitry.

Table 12. Core Voltages Electrical Specifications

Characteristics noted under conditions BP = 3.6 V, -40 C  T_A 85 C, unless otherwise noted. Typical values at BP = 3.6 V

and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

VCOREDIG (DIGITAL CORE SUPPLY)

Output voltage

V

• ON mode

V_COREDIG

-

1.5

0.0

-

(30)

• OFF with good battery and RTC mode

V_COREDIGbypass capacitor

C_COREDIG

-

1.0

-

F

VDDLP (DIGITAL CORE SUPPLY - LOWER POWER)

Output voltage

V

• ON mode with good battery

-

1.5

1.2

-

V_DDLP

(31)

• OFF mode with good battery

• RTC mode

(32)

V_DDLPbypass capacitor

C_DDLP

-

100

-

pF

VCORE (ANALOG CORE SUPPLY)

Output voltage

V

• ON mode and charging

V_CORE

-

2.775

0.0

-

(30)

• OFF and RTC mode

V_COREbypass capacitor

C_CORE

-

1.0

-

F

VREFCORE (BANDGAP / REGULATOR REFERENCE)

(30)

Output voltage

V_REFCORE

-

1.2

0.5

-

V

Absolute accuracy

Temperature drift

%

0.25

100

V_REFCOREbypass capacitor

C_REFCORE

Notes

nF

30. 3.0 V < BP < 4.5 V, no external loading on VCOREDIG, VDDLP, VCORE, or REFCORE. Extended operation down to UVDET, but no

system malfunction.

31. Powered by VCOREDIG

32. Maximum capacitance on V_DDLPshould not exceed 1000 pF, including the board capacitance.

7.3

Clocking and Oscillators

Clock Generation

7.3.1

A system clock is generated for internal digital circuitry as well as for external applications utilizing the clock output pins. A crystal

oscillator is used for the 32.768 kHz time base and generation of related derivative clocks. If the crystal oscillator is not running

(for example, if the crystal is not present), an internal 32 kHz oscillator will be used instead.

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

22

Functional Block Description

Support is also provided for an external Secure Real Time Clock (SRTC), which may be integrated on a companion system

processor IC. For media protection in compliance with Digital Rights Management (DRM) system requirements, the

CLK32KMCU can be provided as a reference to the SRTC module where tamper protection is implemented.

7.3.1.1

Clocking Scheme

The internal 32 kHz oscillator is an integrated backup for the crystal oscillator, and provides a 32.768 kHz nominal frequency at

60% accuracy, if running. The internal oscillator only runs if a valid supply is available at BP, and would not be used as long as

the crystal oscillator is active. In absence of a valid supply at the BP supply node (for instance due to a dead battery), the crystal

oscillator continues running supplied from the coin cell battery. All control functions will run off the crystal derived frequency,

occasionally referred to as “32 kHz” for brevity’s sake.

During the switchover between the two clock sources (such as when the crystal oscillator is starting up), the output clock is

maintained at a stable active low or high phase of the internal 32 kHz clock to avoid any clocking glitches. If the XLTAL clock

source suddenly disappears during operation, the IC will revert back to the internal clock source. Given the unpredictable nature

of the event and the start-up times involved, the clock may be absent long enough for the application to shut down during this

transition, such as a sag in the regulator output voltage or absence of a signal on the clock output pins.

A status bit, CLKS, is available to indicate to the processor which clock is currently selected: CLKS=0 when the internal RC is

used and CLKS=1 if the crystal source is used. The CLKI interrupt bit will be set whenever a change in the clock source occurs,

and an interrupt will be generated if the corresponding CLKM mask bit is cleared.

7.3.1.2

Oscillator Specifications

The crystal oscillator has been optimized for use in conjunction with the Micro Crystal CC7V-T1A32.768 kHz-9.0 pF-30 ppm or

equivalent (such as Micro Crystal CC5V-T1A or Epson FC135) and is capable of handling its parametric variations.

The electrical characteristics of the 32 kHz Crystal oscillator are given in the following table, taking into account the crystal

characteristics noted above. The oscillator accuracy depends largely on the temperature characteristics of the used crystal.

Application circuits can be optimized for required accuracy by adapting the external crystal oscillator network (via component

accuracy and/or tuning). Additionally, a clock calibration system is provided to adjust the 32,768 cycle counter that generates the

1.0 Hz timer and RTC registers; see SRTC Support for more detail.

Table 13. Oscillator and Clock Main Electrical Specifications

Characteristics noted under conditions BP = 3.6 V, -40 C  T_A 85 C, unless otherwise noted. Typical values at BP = 3.6 V

and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

OSCILLATOR AND CLOCK OUTPUT

Operating Voltage

• Oscillator and RTC Block from BP

V_INRTC

1.8

-

4.5

3.6

V

• Oscillator and RTC Block from LICELL

Operating Current Crystal Oscillator and RTC Module

I_INRTC

A

• All blocks disabled, no main battery attached, coin cell is attached

to LICELL

-

2.0

-

5.0

1.0

RTC oscillator start-up time

• Upon application of power

t_START-RTC

sec

Output Low

• CLK32K Output sink 100 A

• CLK32KMCU Output source 50 A

V_RTCLO

V

0.0

-

0.2

Output High

• CLK32K Output source 100 A

-

CLK32K

VCC -0.2

CLK32K

VCC

V_RTCHI

• CLK32KMCU Output sink 50 A

VSRTC-0.2

VSRTC

34709

Analog Integrated Circuit Device Data

23

Freescale Semiconductor

Functional Block Description

Table 13. Oscillator and Clock Main Electrical Specifications

Characteristics noted under conditions BP = 3.6 V, -40 C  T_A 85 C, unless otherwise noted. Typical values at BP = 3.6 V

and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

OSCILLATOR AND CLOCK OUTPUT (CONTINUED)

CLK32K Rise and Fall Time, CL = 50 pF

• CLK32KDRV [1:0] = 00

-

6.0

2.5

3.0

2.0

-

• CLK32KDRV [1:0] = 01 (default)

• CLK32KDRV [1:0] = 10

t_CLK32KET

ns

• CLK32KDRV [1:0] = 11

CLK32KMCU Rise and Fall Time

• CL = 12 pF

t_CKL32K

ns

%

-

45

-

22

-

MCUET

CLK32K_DC/

CLK32K

MCU_DC

CLK32K and CLK32KMCU Output Duty Cycle

• Crystal on XTAL1, XTAL2 pins

55

30

RMS Output Jitter

ns

RMS

• 1 Sigma for Gaussian distribution

-

7.3.2

SRTC Support

When configured for DRM mode (SPI bit DRM = 1), the CLK32KMCU driver will be kept enabled through all operational states

to ensure that the SRTC module always has its reference clock. If DRM = 0, the CLK32KMCU driver will not be maintained in the

Off state.

It is also necessary to provide a means for the processor to do an RTC initiated wake-up of the system if it has been programmed

for such capability. This can be accomplished by connecting an open-drain NMOS driver to the PWRON pin of the 34709 PMIC,

so that it is in effect, a parallel path for the power key. The 34709 PMIC will not be able to discern the turn on event from a normal

power key initiated turn on, but the processor should have the knowledge, since the RTC initiated turn on is generated locally.

Open Drain output for RTC wake-up

32 kHz

SPIVCC=1.8 V

GP Domain=1.1 V

LP Domain=1.2 V

34709

Processor

I/O

Core Supply

SOG Supply

VCOREDIG

PWRONx

Vcoredig

ON

Detect

SRTC

Best Of

Suppy

On/Off

Button

HP-RTC

VSRTC = 1.2 V

CKIL: VSRTC

Vsrtc &

Detect

32 kHz for

DSM timing

LP-RTC

CLK32KMCU

0.1 u

Main

Battery

Coin Cell

Battery

Figure 5. SRTC Block Diagram

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

24

Functional Block Description

7.3.2.1

VSRTC

The VSRTC regulator provides the CLK32KMCU output level. Additionally, it is used to bias the Low-power SRTC domain of the

SRTC module integrated on certain FSL processors. The VSRTC regulator is enabled as soon as the RTCPORB is detected.

The VSRTC cannot be disabled.

Depending on the configuration of the PUMS[4:0] pins, the VSRTC voltage will be set to 1.3 or 1.2 V. With PUMS[4:0] = (0110,

0111, 1000, or 1001) VSRTC will be set to 1.3 V in on mode (on, on standby and on standby low-power modes). In off and coin

cell modes the VSRTC voltage will drop to 1.2 V with the PUMS[4:0] = (0110, 0111, 1000, or 1001). With PUMS[4:0] = (0110,

0111, 1000, or 1001), VSRTC will be set to 1.2 V for all modes (on, on standby, on standby low-power mode, off, and coin cell).

Table 14. VSRTC Electrical Specifications

Characteristics noted under conditions BP = 3.6 V, -40 C  T_A 85 C, unless otherwise noted. Typical values at BP = 3.6 V

and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

GENERAL

Operating Input Voltage Range

• Valid Coin Cell range

• Valid BP

V_SRTCIN

1.8

-

3.6

4.5

V

Operating Current Load Range

Bypass Capacitor Value

I_SRTC

0.0

-

50

-

A

F

CO_SRTC

0.1

VSRTC - ACTIVE MODE - DC

Output Voltage

• V_SRTCINMIN< V_STRCIN< V_SRTCINMAX

V_SRTC

V

• I_SRTCMIN< I_SRTC< I_SRTCMAX

• Off and coin cell mode

1.15

1.20

1.28

1.25

VSRTC - ACTIVE MODE - DC (CONTINUED)

Output Voltage

• V_SRTCINMIN< V_STRCIN< V_SRTCINMAX

• I_SRTCMIN< I_SRTC< I_SRTCMAX

V_SRTC

1.2

• PUMS[4:0] ≠ (0110, 0111, 1000, 1001)

• On, Standby, and Standby LPM modes

Output Voltage

• V_SRTCINMIN< V_STRCIN< V_SRTCINMAX

• I_SRTCMIN< I_SRTC< I_SRTCMAX

V_SRTC

V

1.25

1.3

0.8

1.35

• PUMS[4:0] = (0110, 0111, 1000, 1001)

• On, Standby, and Standby LPM modes

Active Mode Quiescent Current

• V_SRTCINMIN< V_STRCIN< V_SRTCINMAX

• I_SRTC= 0

I_SRTCQ

A

-

7.3.2.2

Real Time Clock

A Real Time Clock (RTC) is provided with time and day counters as well as an alarm function. The RTC utilizes the 32.768 kHz

crystal oscillator for the time base and is powered by the coin cell backup supply when BP has dropped below operational range.

In configurations where the SRTC is used, the RTC can be disabled to conserve current drain by setting the RTCDIS bit to a 1

(defaults on at power up).

Time and Day Counters

34709

Analog Integrated Circuit Device Data

25

Freescale Semiconductor

Functional Block Description

The 32.768 kHz clock is divided into a 1.0 Hz time tick which drives a 17-bit Time Of Day (TOD) counter. The TOD counter counts

the seconds during a 24 hour period from 0 to 86,399 and will then roll over to 0. When the roll over occurs, it increments the

15-bit DAY counter. The DAY counter can count up to 32767 days. The 1.0 Hz time tick can be used to generate a 1HZI interrupt

if unmasked.

Time Of Day Alarm

A Time Of Day Alarm (TODA) function can be used to turn on the application and alert the processor. If the application is already

on, the processor will be interrupted. The TODA and DAYA registers are used to set the alarm time. When the TOD counter is

equal to the value in TODA and the DAY counter is equal to the value in DAYA, the TODAI interrupt will be generated.

Timer Reset

As long as the supply at BP is valid, the real time clock will be supplied from VCOREDIG. If BP is not valid, the real time clock

can be backed up from a coin cell via the LICELL pin. When the VSRTC voltage drops to the range of 0.9 to 0.8 V, the RTCPORB

reset signal is generated and the contents of the RTC will be reset. Additional registers backed up by coin cell will also reset with

RTCPORB. To inform the processor that the contents of the RTC are no longer valid due to the reset, a timer reset interrupt

function is implemented with the RTCRSTI bit.

RTC Timer Calibration

A clock calibration system is provided to adjust the 32,768 cycle counter that generates the 1.0 Hz timer for RTC timing registers.

The general implementation relies on the system processor to measure the 32.768 kHz crystal oscillator against a higher

frequency and more accurate system clock, such as a TCXO. If the RTC timer needs a correction, a 5-bit 2’s complement

calibration word can be sent via the SPI, to compensate the RTC for inaccuracy in its reference oscillator.

Table 15. RTC calibration Settings

Code in RTCCAL[4:0]

Correction in Counts per 32768 Relative correction in ppm

01111

00011

00001

00000

11111

11101

10001

10000

+15

+3

+1

0

+458

+92

+31

0

-1

-31

-3

-92

-15

-16

-458

-488

The available correction range should be sufficient to ensure drift accuracy in compliance with standards for DRM time keeping.

Note that the 32.768 kHz oscillator is not affected by RTCCAL settings; calibration is only applied to the RTC time base counter.

Therefore, the frequency at the clock output CLK32K is not affected.

The RTC system calibration is enabled by programming the RTCCALMODE[1:0] for desired behavior by operational mode.

Table 16. RTC Calibration Enabling

RTCCALMODE

Function

RTC Calibration disabled (default)

00

01

10

11

RTC Calibration enabled in all modes except coin cell only

Reserved for future use. Do not use.

RTC Calibration enabled in all modes

The RTC Calibration circuitry can be automatically disabled when main battery contact is lost or if it is so deeply discharged that

RTC power draw is switched to the coin cell (configured with RTCCALMODE=01).

Because of the low RTC consumption, RTC accuracy can be maintained through long periods of the application being shut down,

even after the main battery has discharged. However, it is noted that the calibration can only be as good as the RTCCAL data

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Functional Block Description

that has been provided, so occasional refreshing is recommended to ensure that any drift influencing environmental factors have

not skewed the clock beyond desired tolerances.

7.3.3

Coin Cell Battery Backup

The LICELL pin provides a connection for a coin cell backup battery or supercap. If the main battery is deeply discharged,

removed, or contact-bounced (i.e., during a power cut), the RTC system and coin cell maintained logic will switch over to the

LICELL for backup power. This switch over occurs for a BP below 1.8 V threshold with LICELL greater than BP. A small capacitor

should be placed from LICELL to ground under all circumstances.

Upon initial insertion of the coin cell, it is not immediately connected to the on chip circuitry. The cell gets connected when the IC

powers on, or after enabling the coin cell charger when the IC was already on.

The coin cell charger circuit will function as a current-limited voltage source, resulting in the CC/CV taper characteristic typically

used for rechargeable Lithium-Ion batteries. The coin cell charger is enabled via the COINCHEN bit. The coin cell voltage is

programmable through the VCOIN[2:0] bits. The coin cell charger voltage is programmable in the ON state where the charge

current is fixed at ICOINHI.

If COINCHEN=1 when the system goes into an Off or User Off state, the coin cell charger will continue to charge to the predefined

voltage setting, but at a lower maximum current ICOINLO. This compensates for self discharge of the coin cell and ensures that

if/when the main cell gets depleted, that the coin cell will be topped off for maximum RTC retention. The coin cell charging will

be stopped for the BP below UVDET. The bit COINCHEN itself is only cleared when an RTCPORB occurs.

Table 17. Coin Cell Voltage Specifications

VCOIN[2:0]

Output Voltage

000

001

010

011

100

101

110

111

2.50

2.70

2.80

2.90

3.00

3.10

3.20

3.30

Table 18. Coin Cell Electrical Specifications

Characteristics noted under conditions BP = 3.6 V, -40 C  T_A 85 C, unless otherwise noted. Typical values at BP = 3.6 V

and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

COIN CELL CHARGER

Voltage Accuracy

V_LICELLACC

-

100

60

-

mV

Coin Cell Charge Current in On and Watchdog modes ICOINHI

I_LICELLON

A

Coin Cell Charge Current in Off, cold start/warm start, and Low-power Off

modes (User Off / Memory Hold) ICOINLO

I_LICELLOFF

-

10

-

A

Current Accuracy

I_LICELACC

CO_LICELL

-

30

100

4.7

-

%

nF

F

LICELL Bypass Capacitor

LICELL Bypass Capacitor as coin cell replacement

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Functional Block Description

7.4

Interrupt Management

Control

7.4.1

The system is informed about important events, based on interrupts. Unmasked interrupt events are signaled to the processor

by driving the INT pin high; this is true whether the communication interface is configured for SPI or I²C.

Each interrupt is latched so that even if the interrupt source becomes inactive, the interrupt will remain set until cleared. Each

interrupt can be cleared by writing a 1 to the appropriate bit in the Interrupt Status register, which will also cause the interrupt line

to go low. If a new interrupt occurs while the processor clears an existing interrupt bit, the interrupt line will remain high.

Each interrupt can be masked by setting the corresponding mask bit to a 1. As a result, when a masked interrupt bit goes high,

the interrupt line will not go high. A masked interrupt can still be read from the Interrupt Status register. This gives the processor

the option of polling for status from the IC. The IC powers up with all interrupts masked, so the processor must initially poll the

device to determine if any interrupts are active. Alternatively, the processor can unmask the interrupt bits of interest. If a masked

interrupt bit was already high, the interrupt line will go high after unmasking.

The sense registers contain status and input sense bits, so the system processor can poll the current state of interrupt sources.

They are read only, and not latched or clearable.

Interrupts generated by external events are debounced. Therefore, the event needs to be stable throughout the debounce period

before an interrupt is generated. Nominal debounce periods for each event are documented in the INT summary table following

later in this section. Due to the asynchronous nature of the debounce timer, the effective debounce time can vary slightly.

7.4.2

Interrupt Bit Summary

Table 19 summarizes all interrupt, mask, and sense bits associated with INT control. For more detailed behavioral descriptions,

refer to the related chapters.

Table 19. Interrupt, Mask and Sense Bits

Debounce

Time

Interrupt

Mask

Sense

Purpose

Trigger

ADCDONEI

TSDONEI

ADCDONEM

TSDONEM

-

ADC has finished requested conversions L2H

0.0

Touch screen has finished conversion

Touch screen pen detect

L2H

TSPENDET

TSPENDETM

Dual

1.0 ms

Low battery detect

Programmable

VBATTDB

LOWBATT

SCPI

LOWBATTM

SCPM

-

H2L

Sense is 1 if below LOWBAT threshold

min. 4.0 ms

max 8.0 ms

Regulator short-circuit protection tripped L2H

1HZI

1HZM

-

1.0 Hz time tick

L2H

H2L

L2H

H2L

L2H

0.0

TODAI

TODAM

Time of day alarm

0.0

30 ms ⁽³³⁾

30 ms

30 ms ⁽³³⁾

30 ms

0.0

Power on button 1 event

PWRON1I

PWRON2I

PWRON1M

PWRON2M

PWRON1S

PWRON2S

Sense is 1 if PWRON1 is high.

Power on button 2 event

Sense is 1 if PWRON2 is high.

SYSRSTI

WDIRESETI

PCI

SYSRSTM

WDIRESETM

PCM

-

System reset through PWRONx pins

WDI silent system restart

Power cut event

0.0

WARMI

WARMM

Warm Start event

0.0

MEMHLDI

MEMHLDM

Memory Hold event

0.0

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Functional Block Description

Table 19. Interrupt, Mask and Sense Bits

Debounce

Time

Interrupt

Mask

Sense

Purpose

Trigger

32 kHz clock source change

Sense is 1 if source is XTAL

CLKI

CLKM

CLKS

-

Dual

0.0

RTCRSTI

RTCRSTM

RTC reset has occurred

L2H

0.0

Thermal 110 °C threshold

THERM110

THERM110M

THERM110S

THERM120S

THERM125S

Dual

30 ms

Sense is 1 if above threshold

Thermal 120 °C threshold

THERM120

THERM125

THERM130

THERM120M

THERM125M

Dual

30 ms

Sense is 1 if above threshold

Thermal 125 °C threshold

Sense is 1 if above threshold

Thermal 130 °C threshold

THERM130M

GPIOLVxM

THERM130S

GPIOLVxS

Sense is 1 if above threshold

GPIOLVxI

Notes

General Purpose input interrupt

Programmable Programmable

33. Debounce timing for the falling edge can be extended with PWRONxDBNC[1:0]; refer to Serial Interfaces for details.

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Functional Block Description

7.5

Power Generation

The 34709 PMIC provides reference and supply voltages for the application processor as well as peripheral device.

Six buck (step down) converters and one boost (step up) converters are included. One of the buck regulators can be configured

in multiphase, single phase mode, or operate as separate independent outputs (in this case, there are six buck converters). The

buck converters provide the supply to processor cores and to other low-voltage circuits such as IO and memory. Dynamic voltage

scaling is provided to allow controlled supply rail adjustments for the processor cores and/or other circuitry. The boost converter

supplies the VUSB regulator for the USB PHY on the processor. The VUSB regulator is powered from the boost to ensure

sufficient headroom for the LDO through the normal discharge range of the main battery.

Linear regulators are directly supplied from the battery or from the switching regulator, and include supplies for IO and

peripherals, such as audio, camera, Bluetooth, Wireless LAN, etc. Naming conventions are suggestive of typical or possible use

case applications, but the switching and linear regulators may be utilized for other system power requirements within the

guidelines of specified capabilities. Four general purpose I/Os are available, which can be configured as inputs/outputs. As inputs

they can be configured as interrupts.

7.5.1

Power Tree

Refer to the representative tables and text specifying each supply for information on performance metrics and operating ranges.

Table 20 summarizes the available power supplies.

Table 20. Power Tree Summary

Supply

Purpose (typical application)

Buck regulator for processor VDDGP domain

Buck regulator for processor VCC domain

Buck regulator for processor VDD domain and peripherals

Buck regulator for DDR memory and peripherals

Buck regulator for I/O domain

Output Voltage (in V)

Load Capability (in mA)

SW1

SW2

0.650 – 1.4375

2000

1000

500

1000

380

0.05

50

SW3

0.650 – 1.425

SW4A

SW4B

SW5

1.200 – 1.85: 2.5/3.15

1.200 – 1.85

Boost regulator for USB PHY support

Secure Real Time Clock supply

SWBST

VSRTC

VPLL

5.00/5.05/5.10/5.15

1.2

Quiet Analog supply

1.2/1.25/1.5/1.8

DDR Ref supply

VREFDDR

VDAC

0.6 – 0.9

10

TV DAC supply, external PNP

2.5/2.6/2.7/2.775

2.5/2.6/2.75/3.0

250

65

VUSB/peripherals supply, internal PMOS

VUSB/peripherals external PNP

VUSB2

VGEN1

VGEN2

VUSB

2.5/2.6/2.75/3.0

350

250

50

General peripherals supply #1

1.2/1.25/1.3/1.35/1.4/1.45/1.5/1.55

2.5/2.7/2.8/2.9/3.0/3.1/3.15/3.3

3.3

General peripherals supply #2, internal PMOS

General peripherals supply #2, external PNP

USB Transceiver supply

250

100

7.5.2

Modes of Operation

The 34709 PMIC is fully programmable via the SPI interface and associated register map. Additional communication is provided

by direct logic interfacing, including interrupt, watchdog, and reset. Default start-up of the device is selectable by hardwiring the

Power-up Mode Select (PUMS) pins.

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Functional Block Description

Power cycling of the application is driven by the 34709 PMIC. It has the interfaces for the power buttons and dedicated signaling

interfacing with the processor. It also ensures the supply of the Real Time Clock (RTC), critical internal logic, and other circuits

from the coin cell, in case of brief interruptions from the main battery. A charger for the coin cell is included to ensure that it is

kept topped off until needed.

The 34709 PMIC provides the timekeeping, based on an integrated low-power oscillator running with a standard watch crystal.

This oscillator is used for internal clocking, the control logic, and as a reference for the Regulator PLL. The timekeeping includes

time of day, calendar, and alarm, and is backed up by coin cell. The clock is driven to the processor for reference and deep sleep

mode clocking.

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Functional Block Description

Coin cell

BP < UVDET

BP > UVDET

From Any Mode: Loss of Power with PCEN=0,

Thermal Protection Trip, or System Reset

PCT[7:0] Expired

Off

Unqual’d

Turn On

WDI Low,

WDIRESET=0

WDI Low,

WDIRESET=1

and

Unqual’d

Turn On

Turn On Event

PCMAXCNT is

exceeded

Start Up Modes

Reset Timer

Expired

Reset Timer

Expired

Warm

Start

Cold

Start

WDI Low,

WDIRESET=1 and

PCMAXCNT not

exceeded

Watchdog

Timer Expired

On

Turn On Event

(Warm Boot)

Turn On Event

(Warm Start)

Processor Request

for User Off:

USEROFFSPI=1

Low Power

Off Modes

Warm Start

Not

Enabled

Warm Start

Enabled

User

Off

Memory

Hold

User Off

Wait

PCUT Timer

PCT[7:0]

Expired

PCUTEXPB

cleared to 0

WARMEN=0

WARMEN=1

Application of Power

before PCUT Timer

PCT[7:0] expiration

(PCEN=1 and

PCMAXCNT not

exceeded)

From Any Mode: Loss of

Power with Power Cuts

enabled (PCEN=1) and

PCMAXCNT not exceeded

Internal

MemHold

Power Cut

Figure 6. Power Control State Machine Flow Diagram

The following are text descriptions of the power states of the system for additional details of the state machine to complement

the drawing in Figure 6. Note that the SPI control is only possible in the Watchdog, On and User Off Wait states, and that the

interrupt line INT is kept low in all states except for Watchdog and On.

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Functional Block Description

7.5.2.1

Coin Cell

The RTC module is powered from either the battery or the coin cell, due to insufficient voltage at BP, and the IC is not in a Power

Cut. No Turn On event is accepted in the Coin Cell state. Transition out (to the Off state) requires BP restoration with a threshold

above UVDET. RESETB, and RESETBMCU are held low in this mode.

The RTC module remains active (32 kHz oscillator + RTC timers), along with BP level detection to qualify exit to the Off state.

VCOREDIG is off and the VDDLP regulator is on, the rest of the system is put into its lowest power configuration.

If the coin cell is depleted (VSTRC drops to 0.9 V to 0.8 V while in the Coin Cell state), a complete system reset will occur. At

next power application / Turn On event, the system will start-up reinitialized with all SPI bits including those that reset on

RTCPORB restored to their default states.

7.5.2.2

Off (with good battery)

If the supply VALWAYS is above the UVDET threshold, only the IC core circuitry at VCOREDIG and the RTC module are

powered, all other supplies are inactive. To exit the Off mode, a valid turn on event is required. No specific timer is running in this

mode. RESETB and RESETBMCU are held low in this mode.

If BP is below the UVDET threshold, no turn on events are accepted. If a valid coin cell is present, the core gets powered from

LICELL. The only active circuitry is the RTC module and the detection VCORE module powering VCOREDIG at 1.5 V.

To exit the OFF mode, a valid turn ON event is required.

7.5.2.3

Cold Start

Cold Start is entered upon a Turn On event from Off, Warm Boot, successful PCUT, or a Silent System Restart. The first 8.0 ms

is used for initialization which includes bias generation, PUMSx configuration latching, and qualification of the input supply level

BP. The switching and linear regulators are then powered up sequentially to limit the inrush current; see the Power-up section

for sequencing and default level details. The reset signals RESETB and RESETBMCU are kept low. The Reset timer starts

running when entering Cold Start. The Cold Start state is exited for the Watchdog state and both RESETB and RESETBMCU

become high (open-drain output with external pull-ups) when the reset timer is expired. The input control pins WDI, and

STANDBY are ignored.

7.5.2.4

Watchdog

The system is fully powered and under SPI control. RESETB and RESETBMCU are high. The Watchdog timer starts running

when entering the Watchdog state. When expired, the system transitions to the On state, where WDI will be checked and

monitored. The input control pins WDI and STANDBY are ignored while in the Watchdog state.

7.5.2.5

On Mode

The system is fully powered and under SPI control. RESETB and RESETBMCU are high. The WDI pin must be high to stay in

this mode. The WDI IO supply voltage is referenced to SPIVCC (normally connected to SW5 = 1.8 V); SPIVCC must therefore

remain enabled to allow for proper WDI detection. If WDI goes low, the system will transition to the Off state or Cold Start

(depending on the configuration; refer to the section on Silent System Restart with WDI Event for details).

7.5.2.6

User Off Wait

The system is fully powered and under SPI control. The WDI pin no longer has control over the part. The Wait mode is entered

by a processor request for user off by setting the USEROFFSPI bit high. This is normally initiated by the end user via the power

key; upon receiving the corresponding interrupt, the system will determine if the product has been configured for User Off or

Memory Hold states (both of which first require passing through User Off Wait) or just transition to Off.

The Wait timer starts running when entering User Off Wait mode. This leaves the processor time to suspend or terminate its tasks.

When expired, the Wait mode is exited for User Off mode or Memory Hold mode depending on warm starts being enabled or not

via the WARMEN bit. The USEROFFSPI bit is being reset at this point by RESETB going low.

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Functional Block Description

7.5.2.7

Memory Hold and User Off (Low-power Off states)

As noted in the User Off Wait description, the system is directed into low-power Off states based on a SPI command in response

to an intentional turn off by the end user. The only exit then will be a turn on event. To an end user, the Memory Hold and User

Off states look like the product has been shut down completely. However, a faster start-up is facilitated by maintaining external

memory in self-refresh mode (Memory Hold and User Off mode) as well as powering portions of the processor core for state

retention (User Off only). The Switching regulator mode control bits allow selective powering of the buck regulators for optimizing

the supply behavior in the low-power Off modes. Linear regulators and most functional blocks are disabled (the RTC module,

SPI bits resetting with RTCPORB, and Turn On event detection are maintained).

By way of example, the following descriptions assume the typical use case where SW1 supplies the processor core(s), SW2 is

applied to the processor’s VCC domain, SW3 supplies the processors internal memory/peripherals, SW4 supplies the external

memory, and SW5 supplies the I/O rail. The buck regulators are intended for direct connection to the aforementioned loads.

7.5.2.8

Memory Hold

RESETB and RESETBMCU are low, and both CLK32K and CLK32KMCU are disabled (CLK32KMCU active if DRM is set). To

ensure that SW1, SW2, SW3, and SW5 shut off in Memory Hold, appropriate mode settings should be used such as

SW1MHMODE, = SW2MHMODE, = SW3MHMODE, = SW5MHMODE set to = 0 (refer to the mode control description later in

this section). Since SW4 should be powered in PFM mode, SW4MHMODE could be set to 1.

Upon a Turn On event, the Cold Start state is entered, the default power-up values are loaded, and the MEMHLDI interrupt bit

is set. A Cold Start out of the Memory Hold state will result in shorter boot times compared to starting out of the Off state, since

software does not have to be loaded and expanded from flash. The start-up out of Memory Hold is also referred to as Warm Boot.

No specific timer is running in this mode.

Buck regulators that are configured to stay on in MEMHOLD mode by their SWxMHMODE settings will not be turned off when

coming out of MEMHOLD and entering a Warm Boot. The switching regulators will be reconfigured for their default settings as

selected by the PUMSx pins in the normal time slot that would affect them.

7.5.2.9

User Off

RESETB is low and RESETBMCU is kept high. The 32 kHz peripheral clock driver CLK32K is disabled; CLK32KMCU (connected

to the processor’s CKIL input) is maintained in this mode if the CLK32KMCUEN and USEROFFCLK bits are both set, or if DRM

is set.

The memory domain is held up by setting SW4UOMODE = 1. Similarly, the SW1 and/or SW2 and/or SW3 supply domains can

be configured for SWxUOMODE=1 to keep them powered through the User Off event. If one of the switching regulators can be

shut down on in User Off, its mode bits would typically be set to 0.

Since power is maintained for the core (which is put into its lowest power state), and since MCU RESETBMCU does not trip, the

processor’s state may be quickly recovered when exiting USEROFF upon a turn on event. The CLK32KMCU clock can be used

for very low frequency / low-power idling of the core(s), minimizing battery drain, while allowing a rapid recovery from where the

system left off before the USEROFF command.

Upon a turn on event, Warm Start state is entered, and the default power-up values are loaded. A Warm Start out of User Off will

result in an almost instantaneous start-up of the system, since the internal states of the processor were preserved along with

external memory. No specific timer is running in this mode.

7.5.2.10 Warm Start

Entered upon a Turn On event from User Off. The first 8.0 ms is used for initialization, which includes bias generation, PUMSx

latching, and qualification of the input supply level BP. The switching and linear regulators are then powered up sequentially to

limit the inrush current; see Start-up Requirements for sequencing and default level details. If SW1, SW2, SW3, SW4, and/or

SW5, were configured to stay on in User Off mode by their SWxUOMODE settings, they will not be turned off when coming out

of User Off and entering a Warm Start. The buck regulators will be reconfigured for their default settings as selected by the

PUMSx pins in the respective time slot defined in the sequencer selection.

RESETB is kept low and RESETBMCU is kept high. CLK32KMCU is kept active if CLK32KMCU was set. The reset timer starts

running when entering Warm Start. When expired, the Warm Start state is exited for the Watchdog state, a WARMI interrupt is

generated, and RESETB will go high.

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Functional Block Description

7.5.2.11 Internal MemHold Power Cut

As described in the Power Cut Description, a momentary power interruption will put the system into the Internal MemHold Power

Cut state if PCUTs are enabled. The backup coin cell will now supply the 34709 core along with the 32 k crystal oscillator, the

RTC system, and coin cell backed up registers. All regulators will be shut down to preserve the coin cell and RTC as long as

possible.

Both RESETB and RESETBMCU are tripped, bringing the entire system down along with the supplies and external clock drivers,

so the only recovery out of a Power Cut state is to reestablish power and initiate a Cold Start.

If the PCT timer expires before power is re-established, the system transitions to the Off state and awaits a sufficient supply

recovery.

7.5.3

Power Control Logic

Power Cut Description

7.5.3.1

When the BP drops below the UVDET threshold, due to battery bounce or battery removal, the Internal MemHold Power Cut

mode is entered and a Power Cut (PCUT) timer starts running. The backup coin cell will now supply the RTC as well as the on

chip memory registers and some other power control related bits. All other supplies will be disabled.

The maximum duration of a power cut is determined by the PCUT timer PCT [7:0] preset via the SPI. When a PCUT occurs, the

PCUT timer will be started. The contents of PCT [7:0] does not reflect the actual count down value, but will keep the programmed

value, and therefore does not have to be reprogrammed after each power cut.

If power is not re-established above the 3.0 V threshold before the PCUT timer expires, the state machine transitions to the Off

mode at expiration of the counter, and clears the PCUTEXB bit by setting it to 0. This transition is referred to as an “unsuccessful”

PCUT. In addition the PMIC will bring the SDWNB pin low for one 32 kHz clock cycle before powering down.

Upon re-application of power before expiration (a “successful PCUT”, defined as BP first rising above the UVDET threshold and

then battery above the 3.0 V threshold before the PCUT timer expires), a Cold Start is engaged after the UVTIMER has expired.

In order to distinguish a non-PCUT initiated Cold Start from a Cold Start after a PCUT, the PCI interrupt should be checked by

software. The PCI interrupt is cleared by software or when cycling through the Off state.

Because the PCUT system quickly disables the entire power tree, the battery voltage may recover to a level with the appearance

of a valid supply once the battery is unloaded. However, upon a restart of the IC and power sequencer, the surge of current

through the battery and trace impedances can once again cause the BP node to droop below UVDET. This chain of cyclic power

down / power-up sequences is referred to as “ambulance mode”, and the power control system includes strategies to minimize

the chance of a product falling into and getting stuck in ambulance mode.

First, the successful recovery out of a PCUT requires the BP node to rise above LOBATT threshold, providing hysteretic margin

from the LOBATT (H to L) threshold. Secondly, the number of times the PCUT mode is entered is counted with the counter

PCCOUNT [3:0], and the allowed count is limited to PCMAXCNT [3:0] set through the SPI. When the contents of both become

equal, then the next PCUT will not be supported and the system will go to Off mode, after the PCUT time expires.

After a successful power-up after a PCUT (i.e., valid power is reestablished, the system comes out of reset, and the processor

reassumes control), software should clear the PCCOUNT [3:0] counter. Counting of PCUT events is enabled via the

PCCOUNTEN bit. This mode is only supported if the power cut mode feature is enabled by setting the PCEN bit. When not

enabled, then in case of a power failure, the state machine will transition to the Off state. SPI control is not possible during a

PCUT event and the interrupt line is kept low. SPI configuration for PCUT support should also include setting the PCUTEXPB = 1

(See Silent Restart from PCUT Event).

7.5.3.2

Silent Restart from PCUT Event

If a short duration power cut event occurs (such as from a battery bounce, for example), it may be desirable to perform a silent

restart, so the system is reinitialized without alerting the user. This can be facilitated by setting the PCUTEXPB bit to “1” at booting

or after a Cold Start. This bit resets on RTCPORB, therefore any subsequent Cold Start can first check the status of PCUTEXPB

and the PCI bit. The PCUTEXPB is cleared to “0” when transitioning from PCUT to Off. If there was a PCUT interrupt and

PCUTEXPB is still “1”, then the state machine has not transitioned through Off, which confirms that the PCT timer has not expired

during the PCUT event (i.e., a successful power cut). In this case, a silent restart may be appropriate.

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If PCUTEXPB is found to be “0” after the Cold Start where PCI is found to be “1”, then it is inferred that the PCT timer has expired

before power was reestablished, flagging an unsuccessful power cut or first power-up, so the start-up user greeting may be

desirable for playback.

7.5.3.3

Silent System Restart with WDI Event

A mechanism is provided for recovery if the system software somehow gets into an abnormal state which requires a system reset,

but it is desired to make the reset a silent event so as to happen without end user awareness. The default response to WDI going

low is for the state machine to transition to the Off state (when WDIRESET = 0). However, if WDIRESET = 1, the state machine

will go to Cold Start without passing through Off mode (i.e., does not generate an OFFB signal).

A WDIRESET event will generate a maskable WDIRESETI interrupt and also increment the PCCOUNT counter. This function is

unrelated to PCUTs, but it shares the PCUT counter so that the number of silent system restarts can be limited by the

programmable PCMAXCNT counter.

When PCUT support is used, the software should set the PCUTEXPB bit to “1”. Since this bit resets with RTCPORB, it will not

be reset to “0” if a WDI falls and the state machine goes straight to the Cold Start state. Therefore, upon a restart, software can

discern a silent system restart if there is a WDIRESETI interrupt and PCUTEXPB = 1. The application may then determine that

an inconspicuous restart without fanfare may be more appropriate than launching into the welcoming routine.

A PCUT event does not trip the WDIRESETI bit.

Note that the system response to WDI is gated by the Watchdog timer—once the timer has expired, then the system will respond

as programmed by WDIRESET and described above.

7.5.3.4

Turn On Events

When in Off mode, the circuit can be powered on via a Turn On event. The Turn On events are listed by the following. To indicate

to the processor what event caused the system to power on, an interrupt bit is associated with each of the Turn On events.

Masking the interrupts related to the turn on events will not prevent the part to turn on except for the time of day alarm. If the part

was already on at the time of the turn on event, the interrupt is still generated.

• Power Button Press: PWRON1, or PWRON2 pulled low with corresponding interrupts and sense bits PWRON1I or

PWRON2I, and PWRON1S or PWRON2S. A power on/off button is connected from PWRONx to ground. The PWRONx can

be hardware debounced through a programmable debouncer PWRONxDBNC [1:0] to avoid a response upon a very short (i.e.,

unintentional) key press. BP should be above UVDET to allow a power-up. The PWRONxI interrupt is generated for both the

falling and the rising edge of the PWRONx pin. By default, a 30 ms interrupt debounce is applied to both falling and rising

edges. The falling edge debounce timing can be extended with PWRONxDBNC[1:0] as defined in the following table. The

PWRONxI interrupt is cleared by software or when cycling through the Off mode.

Table 21. PWRONx Hardware Debounce Bit Settings⁽³⁴⁾

Turn On

Debounce (ms)

Falling Edge INT Rising Edge INT

Bits

State

Debounce (ms)

00

01

10

11

0.0

31.25

125

31.25

125

31.25

PWRONxDBNC[1:0]

750

Notes

34. The sense bit PWRONxS is not debounced and follows the state of the PWRONx pin.

• Battery Attach: This occurs when BP crosses the 3.0V threshold and the UVDET rising threshold which is equivalent to

attaching a charged battery or supply to the product.

• RTC Alarm: TOD and DAY become equal to the alarm setting programmed. This allows powering up a product at a preset

time. BP should be above 3.0V, and BP should have crossed the UVDET rising threshold and not transitioned below the

UVDET falling threshold.

• System Restart: System restart which may occur after a system reset as described earlier in this section. This is an optional

function, see Turn Off Events. BP should be above 3.0 V and BP should have crossed the UVDET rising threshold and not

transitioned below the UVDET falling threshold.

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Functional Block Description

• Global System Reset: The global reset feature powers down the part, disables the charger, resets the SPI registers to their

default value including all the RTCPORB registers (except the DRM bit, and the RTC registers), and then powers back on. To

enable a global reset, the GLBRST pin needs to be pulled low for greater than GLBRSTTMR [1:0] seconds and then pulled

back high (defaults to 12 s). BP should be above 3.0 V.

Table 22. Global Reset Time Settings

Bits

State

Time (s)

00

01

Invalid

4.0

GLBRSTTMR[1:0]

10

8.0

11 (default)

12

7.5.3.5

Turn Off Events

• Power Button Press (via WDI): User shut down of a product is typically done by pressing the power button connected to the

PWRONx pin. This will generate an interrupt (PWRONxI), but will not directly power off the part. The product is powered off

by the processor’s response to this interrupt, which will be to pull WDI low. Pressing the power button is therefore under normal

circumstances not considered as a turn off event for the state machine. However, since the button press power down is the

most common turn off method for end products, it is described in this section as the product implementation for a WDI initiated

Turn Off event. Note that the software can configure a user initiated power down, via a power button press for transition to a

Low-power Off mode (Memory Hold or User Off) for a quicker restart than the default transition into the Off state.

• Power Button System Reset: A secondary application of the PWRONx pins is the option to generate a system reset. This is

recognized as a Turn Off event. By default, the system reset function is disabled but can be enabled by setting the

PWRONxRSTEN bits. When enabled, a four second long press on the power button will cause the device to go to the Off

mode, and as a result, the entire application will power down. An interrupt SYSRSTI is generated upon the next power-up.

Alternatively, the system can be configured to restart automatically by setting the RESTARTEN bit.

• Thermal Protection: If the die gets overheated, the thermal protection will power off the part to avoid damage. A Turn On

event will not be accepted while the thermal protection is still being tripped. The part will remain in Off mode until cooling

sufficiently to accept a Turn On event. There are no specific interrupts related to this other than the warning interrupts.

• Under-voltage Detection: When the voltage at BP drops below the under-voltage detection threshold UVDET, the state

machine will transition to Off mode if PCUT is not enabled, or if the PCT timer expires when PCUT is enabled. The SDWNB

pin is used to notify that the processor that the PMIC is going to immediately shut down. The PMIC will bring the SDWNB pin

low for one 32 kHz clock cycle before powering down. This signal will then be brought back high in the power Off state.

7.5.3.6

Timers

The different timers as used by the state machine are listed by the following. This listing does not include RTC timers for

timekeeping. A synchronization error of up to one clock period may occur with respect to the occurrence of an asynchronous

event, the duration listed below is therefore the effective minimum time period.

Table 23. Timer Main Characteristics

Timer

Duration

Clock

Under-voltage Timer

Reset Timer

4.0 ms

40 ms

32 k/32

Watchdog Timer

128 ms

Programmable 0 to 8 seconds

in 31.25 ms steps

Power Cut Timer

32 k/1024

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Functional Block Description

7.5.3.6.1

Timing Diagrams

A Turn On event timing diagrams shown in Figure 7.

ow

Turn On Event

WDI Pulled Low

Sequencer time slots

System Core Active

Turn On Verification

Power Up Sequencer

UV Masking

RESETB

INT

WDI

8 ms

20 ms

12 ms

128 ms

1- Off

2- Cold Start

3- Watchdog

4- On

3- Watchdog

1- Off

Power up of the system upon a Turn On Event followed by a transition to the On state if WDI is pulled high

Turn on Event is based on PWRON being pulled low

... or transition to Off state if WDI remains low

= Indeterminate State

Figure 7. Power-up Timing Diagram

7.5.3.7

Power Monitoring

The voltage at BP are monitored by detectors as summarized in Table 24.

Table 24. LOWBATT Detection Thresholds

Threshold

Power on

Voltage (V)

3.0

Low input supply warning

• BP (H to L)⁽³⁵⁾

2.9

UVDET rising⁽³⁶⁾

3.0

UVDT Falling⁽³⁶⁾

2.65

Notes

35. 50 mV hysteresis is applied.

36. ± 4.0 % tolerance

The UVDET and Power on thresholds are related to the power on/off events as described earlier in this chapter. In order for the

IC to power on, BP must rise above the UVDET rising threshold, and the power on threshold (3.0 V) threshold. When the BP

node decreases below the 2.9 V threshold, a low input supply warning will be sent to the processor via the LOWBATTI interrupt.

The LOWBATTI detection threshold is debounced by the VBATTDB[2:0] SPI bits shown in Table 25.

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Functional Block Description

Table 25. VBATTDB Debounce Times

VATTDB[1:0]

Debounce Time (ms)

00

01

0.1

1.0

2.5

3.9

10

11 (default)

7.5.3.8

Power Saving

System Standby

7.5.3.8.1

A product may be designed to enter DSM after periods of inactivity, the STANDBY pin is provided for board level control of timing

in and out of such deep sleep modes.

When a product is in DSM, it may be able to reduce the overall platform current by lowering the regulator output voltage, changing

the operating mode of the switching regulators, or disabling some regulators. This can be obtained by controlling the STANDBY

pin. The configuration of the regulators in standby is pre-programmed through the SPI.

A lower power standby mode can be obtained by setting the ON_STBY_LP SPI bit to a one. With the ON_STBY_LP SPI bit set

and the STANDBY pin asserted, a lower power standby will be entered. In the on Standby Low-power mode, the switching

Regulators should all be programmed into PFM mode, and the LDO's should be configured to Low-power mode when the

STANDBY pin is asserted. The PLL is disabled in this mode

Note that the STANDBY pin is programmable for Active High or Active Low polarity, and the decoding of a Standby event will

take into account the programmed input polarity associated with each pin. For simplicity, Standby will generally be referred to as

active high throughout this document, but as defined in Table 26, active low operation can be accommodated. Finally, since the

STANDBY pin activity is driven asynchronously to the system, a finite time is required for the internal logic to qualify and respond

to the pin level changes.

Table 26. Standby Pin and Polarity Control

STANDBY (Pin)

STANDBYINV (SPI bit)

STANDBY Control⁽³⁷⁾

0

1

0

1

0

1

0

1

0

Notes

37. STANDBY = 0: System is not in Standby STANDBY = 1: System is in Standby

The state of the STANDBY pin only has influence in On mode, and are therefore it is ignored during start-up and in the Watchdog

phase. This allows the system to power-up without concern of the required Standby polarities since software can make

adjustments accordingly as soon as it is running.

A command to transition to one of the low-power Off states (User Off or Memory Hold, initiated with USE-ROFFSPI=1) redefines

the power tree configuration based on SWxMODE programming, and has priority over Standby (which also influences the power

tree configuration).

7.5.3.8.2

Standby Delay

A provision to delay the Standby response is included. This allows the processor and peripherals, some time after a Standby

instruction has been received, to terminate processes to facilitate seamless Standby exiting and re-entrance into Normal

operating mode.

A programmable delay is provided to hold off the system response to a Standby event. When enabled (STBYDLY = 01, 10, or

11), STBYDLY will delay the STANDBY initiated response for the entire IC until the STBYDLY counter expires.

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Functional Block Description

Note that this delay is applied only when going into Standby, and no delay is applied when coming out of Standby. Also, an

allowance should be accounted for synchronization of the asynchronous Standby event and the internal clocking edges (up to a

full 32 k cycle of additional delay).

Table 27. Delay of STANDBY- Initiated Response

STBYDLY[1:0]

Function

No Delay

00

One 32 k period (default)

Two 32 k periods

01

10

11

Three 32 k periods

7.5.4

Buck Switching Regulators

Six buck switching regulators are provided with integrated power switches and synchronous rectification. In a typical application,

SW1 and SW2 are used for supplying the application processor core power domains. Split power domains allow independent

DVS control for processor power optimization, or to support technologies with a mix of device types with different voltage ratings.

SW3 is used for powering internal processor memory as well as low-voltage peripheral devices and interfaces which can run at

the same voltage level. SW4A/B is used for powering external DDR memory as well as low-voltage peripheral devices and

interfaces, which can run at the same voltage level. SW5 is used to supply the I/O domain for the system.

The buck regulators are supplied from the system supply BP, which is drawn from the main battery

The switching regulators can operate in different modes depending on the load conditions. These modes can be set through the

SPI and include a PFM mode, PWM Pulse Skip, an Automatic Pulse Skipping mode, and a PWM mode.

Table 28. Buck Operating Modes

Mode

Description

The regulator is switched off and the output voltage is discharged

OFF

The regulator is switched on and set to PFM mode operation. In this mode, the regulator is always running in

PFM mode. Useful at light loads for optimized efficiency.

PFM

APS

The regulator is switched on and set to Automatic Pulse Skipping. In this mode the regulator moves automatically

between pulse skipping and full PWM mode depending on load conditions.

The regulator is switched on and set to PWM mode. In this mode the regulator is always in full PWM mode

operation regardless of load conditions.

PWM

The regulator is alternating between pulse skipping and PWM modes, depending on the load conditions.

PWMPS

Buck modes of operation are programmable for explicitly defined or load-dependent control.

When initially activated, regulators outputs will apply controlled stepping to the programmed value. The soft start feature limits

the inrush current at start-up. During soft start, the regulator will be forced to PWM mode for 3.0 ms and then default to the APS

mode A built in current limiter ensures that during normal operation the maximum current through the coil is not exceeded.

Point of Load feedback is intended for minimizing errors due to board level IR drops.

7.5.4.1

General Control

Operational modes of the Buck regulators can be controlled by direct SPI programming, altered by the state of the STANDBY

pin, by direct state machine influence (i.e., entering Off or low-power Off states, for example), or by load current magnitude when

so configured (Auto Pulse skip mode). Available modes include PWM with No Pulse Skipping (PWM), PWM with Pulse Skipping

(PWMPS), Pulse Frequency Mode (PFM), Automatic Pulse Skip (APS), and Off. The transition between the two modes PWMPS

and PWM can occur automatically, based on the load current (auto pulse skip mode). For light loading, the regulators should be

put into PFM mode to optimize efficiency.

SW1A/B, SW2, SW3, SW4A/B, and SW5, can be configured for mode switching with STANDBY or autonomously, based on load

current Auto pulse skip mode. Additionally, provisions are made for maintaining PFM operation in User off and Memhold modes,

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Functional Block Description

to support state retention for faster start-up from the Low-power Off modes for Warm Start or Warm Boot. SWxMODE[3:0] bits

will be reset to their default values defined by PUMSx settings by the start-up sequencer.

Table 29 summarizes the Buck regulators programmability for Normal and Standby modes.

Table 29. Switching regulator Mode Control for Normal and Standby Operation

SWxMODE[3:0]

Normal Mode

Standby Mode

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Off

PWM

PWMPS

PFM

Off

APS

Off

PWM

Off

PWM

APS

Off

APS

PWMPS

APS

PFM

PWM

PWMPS

APS

PWM

PWMPS

PFM

In addition to controlling the operating mode in Standby, the voltage setting can be changed. The transition in voltage is handled

in a controlled slope manner, see Serial Interfaces for details. Each regulator has an associated set of SPI bits for Standby mode

set points. By default, the Standby settings are identical to the non-standby settings which are initially defined by PUMSx

programming.

The actual operating mode of the Switching regulators as a function of the STANDBY pin is not reflected through the SPI. In other

words, the SPI will read back what is programmed in SWxMODE[3:0], not the actual state that may be altered as described

previously.

Two tables follow for mode control in the low-power Off states. Note that a low-power Off activated SWx should use the Standby

set point as programmed by SWxSTBY[4:0]. The activated regulator(s) will maintain settings for mode and voltage until the next

start-up event. When the respective time slot of the start-up sequencer is reached for a given regulator, its mode and voltage

settings will be updated the same as if starting out of the Off state (except that switching regulators active through a low-power

Off mode will not be off when the start-up sequencer is started).

Table 30. Switching regulator Control In Memory Hold

Memory Hold Operational Mode

SWxMHMODE

(38)

0

1

Off

PFM

Notes:

38. For Memory Hold mode, an activated SWx should use the

Standby set point as programmed by SWxSTBY[4:0].

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Functional Block Description

Table 31. Switching regulator Control In User Off

SWxUOMODE

User Off Operational Mode ⁽³⁹⁾

0

1

Off

PFM

Notes:

39. For User Off mode, an activated SWx should use the

Standby set point as programmed by SWxSTBY[4:0].

In normal steady state operating mode, the SW1xPWGD pin is high. When the buck charger set point is changed to a higher or

lower set point, the SW1xPWGD pin will go low and will go high again when the higher/lower set point is reached.

7.5.4.2

Switching Frequency

A PLL generates the Switching system clocking from the 32.768 kHz crystal oscillator reference. The switching frequency can

be programmed to 2.0 MHz or 4.0 MHz by setting the PLLX SPI bit as shown in Table 32.

Table 32. Buck Regulator Frequency

PLLX

Switching Frequency (Hz)

0

1

2 000 000

4 000 000

The clocking system provides a near instantaneous activation when the Switching regulators are enabled or when exiting PFM

operation for PWM mode. The PLL can be configured for continuous operation with PLLEN = 1.

7.5.4.3

SW1

SW1 is fully integrated synchronous Buck PWM voltage mode control DC/DC regulator. It can be operated in single phase/dual

phase mode. The operating mode of the Switching regulators is configured by the SW1CFG pin. The SW1CFG pin is sampled

at start-up.

Table 33. SW1 Configuration

SW1CFG

VCOREDIG

Ground

SW1A/B Configuration Mode

Single Phase Mode

Dual Phase Mode

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Functional Block Description

BP

SW1IN

SW1AMODE

SW1FAULT

I_SENSE

C_{INSW 1A}

Controller

SW1

SW1ALX

Driver

L_{SW 1A}

D_SW1

C_OSW1A

GNDSW1A

SW1FB

Internal

Compensation

SPI

Z2

SPI

Interface

Z1

V_REF

EA

DAC

BP

SW1BIN

SW1BMODE

I_SENSE

C_{IN SW 1B}

Controller

SW1BLX

Driver

SW1BFAULT

GNDSW1B

VCOREDIG

SW1CFG

Figure 8. SW1 Single Phase Output Mode Block Diagram

BP

SW1IN

SW1AMODE

I_SENSE

C_INSW1A

Controller

SW1

SW1ALX

Driver

L_SW1A

C_OSW1A

D_SW1A

SW1FAULT

GNDSW1A

Internal

Compensation

SPI

Z2

SPI

Interface

SW1FB

Z1

V_REF

EA

DAC

BP

SW1BIN

SW1BLX

SW1BMODE

I_SENSE

C_INSW1B

Controller

Driver

L_{SW 1B}

C_{OSW 1B}

D_SW1B

SW1BFAULT

GNDSW1B

SW1CFG

Figure 9. SW1 Dual Phase Output Mode Block Diagram

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The peak current is sensed internally for over-current protection purposes. If an over-current condition is detected the regulator

will limit the current through cycle by cycle operation and alert the system through the SW1FAULT SPI bit and issue an SCPI

interrupt via the INT pin.

SW1A/B output voltage is SPI configurable in step sizes of 12.5 mV as shown in the table below. The SPI bits SW1A[5:0] set the

output voltage for both the SW1A and SW1B.

Table 34. SW1A/B Output Voltage Programmability

SW1A/B

Output (V)

SW1A/B

Output (V)

Set Point SW1A[5:0]

0

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

010000

010001

010010

010011

010100

010101

010110

010111

011000

011001

011010

011011

011100

011101

011110

011111

0.6500

0.6625

0.6750

0.6875

0.7000

0.7125

0.7250

0.7375

0.7500

0.7625

0.7750

0.7875

0.8000

0.8125

0.8250

0.8375

0.8500

0.8625

0.8750

0.8875

0.9000

0.9125

0.9250

0.9375

0.9500

0.9625

0.9750

0.9875

1.0000

1.0125

1.0250

1.0375

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

100000

100001

100010

100011

100100

100101

100110

100111

101000

101001

101010

101011

101100

101101

101110

101111

110000

110001

110010

110011

110100

110101

110110

110111

111000

111001

111010

111011

111100

111101

111110

111111

1.0500

1.0625

1.0750

1.0875

1.1000

1.1125

1.1250

1.1375

1.1500

1.1625

1.1750

1.1875

1.2000

1.2125

1.2250

1.2375

1.2500

1.2625

1.2750

1.2875

1.3000

1.3125

1.3250

1.3375

1.3500

1.3625

1.3750

1.3875

1.4000

1.4125

1.4250

1.4375

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

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Functional Block Description

Table 35. SW1A/B Electrical Specification

Characteristics noted under conditions BP = 3.6 V, -40 C  T_A 85 C, unless otherwise noted. Typical values at BP = 3.6 V

and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

SW1A/B BUCK REGULATOR

Operating Input Voltage

• PWM operation, 0 < IL < I_MAX

• PFM operation, 0 < IL < IL_MAX

V_SW1IN

3.0

2.8

-

4.5

V

Output Voltage Accuracy

(40)

• PWM mode including ripple, load regulation, and transients

• PFM Mode, including ripple, load regulation, and transients

V_SW1ACC

Nom-25

Nom

Nom+25

mV

Continuous Output Load Current, V_INMIN< BP < 4.5 V

• PWM mode single/dual phase (parallel)

• SW1 in PFM mode

I_SW1

-

2000

-

mA

A

50

Current Limiter Peak Current Detection

• V_IN= 3.6 V, Current through Inductor

I_SW1PEAK

-

4.0

-

Transient Load Change

• 100 mA/µs

I_SW1

A

-

1.0

25

TRANSIENT

V_SW1OS-

Start-up Overshoot, IL = 0

mV

µs

START

Turn-on Time

t_ON-SW1

• Enable to 90% of end value IL = 0

-

500

Switching Frequency

• PLLX = 0

f_SW1

-

2.0

4.0

-

MHz

µA

• PLLX = 1

Quiescent Current Consumption

• PWMPS or APS Mode, IL=0 mA; device not switching

• PFM Mode, IL=0 mA

I_SW1Q

-

160

15

-

Efficiency,

• PFM, 0.9 V, 1.0 mA

-

54

75

81

76

-

(41)

• PWM Pulse skipping, 1.1 V, 200 mA

• PWM Pulse skipping, 1.1 V, 800 mA

• PWM, 1.1 V, 1600 mA

%

Notes:

40. Transient loading for load steps of ILMAX/2.

41. Efficiency numbers at V_IN= 3.6 V, excludes the quiescent current

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7.5.4.4

SW2

SW2 is fully integrated synchronous Buck PWM voltage-mode control DC/DC regulator.

BP

SW2IN

SW2MODE

I_SENSE

C

INSW 3

Controller

SW2

SW2LX

Driver

L_SW2

D_{SW 2}

C_OSW2

SW2FAULT

SPI

Interface

GNDSW2

Internal

Compensation

SPI

Z2

SW2FB

Z1

V_REF

EA

DAC

Figure 10. SW2 Block Diagram

The peak current is sensed internally for over-current protection purposes. If an over-current condition is detected, the regulator

will limit the current through cycle by cycle operation, alert the system through the SW2FAULT SPI bit, and issue an SCPI

interrupt via the INT pin.

SW2 can be programmed in step sizes of 12.5 mV as shown in Table 36.

Table 36. SW2 Output Voltage Programmability

SW2x

Output (V)

SW2 Output

(V)

Set Point SW2[5:0]

0

1

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

010000

0.6500

0.6625

0.6750

0.6875

0.7000

0.7125

0.7250

0.7375

0.7500

0.7625

0.7750

0.7875

0.8000

0.8125

0.8250

0.8375

0.8500

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

100000

100001

100010

100011

100100

100101

100110

100111

101000

101001

101010

101011

101100

101101

101110

101111

110000

1.0500

1.0625

1.0750

1.0875

1.1000

1.1125

1.1250

1.1375

1.1500

1.1625

1.1750

1.1875

1.2000

1.2125

1.2250

1.2375

1.2500

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

46

Functional Block Description

Table 36. SW2 Output Voltage Programmability

SW2x

SW2 Output

(V)

Set Point SW2[5:0]

Output (V)

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

010001

010010

010011

010100

010101

010110

010111

011000

011001

011010

011011

011100

011101

011110

011111

0.8625

0.8750

0.8875

0.9000

0.9125

0.9250

0.9375

0.9500

0.9625

0.9750

0.9875

1.0000

1.0125

1.0250

1.0375

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

110001

110010

110011

110100

110101

110110

110111

111000

111001

111010

111011

111100

111101

111110

111111

1.2625

1.2750

1.2875

1.3000

1.3125

1.3250

1.3375

1.3500

1.3625

1.3750

1.3875

1.4000

1.4125

1.4250

1.4375

Table 37. SW2 Electrical Specifications

Characteristics noted under conditions BP = 3.6 V, -40 C  T_A 85 C, unless otherwise noted. Typical values at BP = 3.6 V

and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

SW2 BUCK REGULATOR

Operating Input Voltage

• PWM operation, 0 < IL < I_MAX

• PFM operation, 0 < IL < IL_MAX

V_SW2IN

3.0

2.8

-

4.5

V

Output Voltage Accuracy

(42)

• PWM mode including ripple, load regulation, and transients

• PFM Mode, including ripple, load regulation, and transients

V_SW2ACC

Nom-25

Nom

Nom+25

mV

Continuous Output Load Current, V_INMIN< BP < 4.5 V

• PWM mode

• PFM mode

I_SW2

-

1000

-

mA

A

50

Current Limiter Peak Current Detection

• V_IN= 3.6 V Current through Inductor

I_SW2PEAK

-

2.0

-

Transient Load Change

• 100 mA/µs

I_SW2

A

-

0.500

25

TRANSIENT

V_SW2OS-

Start-up Overshoot, IL = 0

mV

µs

START

Turn-on Time

t_ON-SW2

• Enable to 90% of end value IL = 0

-

500

34709

Analog Integrated Circuit Device Data

47

Freescale Semiconductor

Functional Block Description

Table 37. SW2 Electrical Specifications

Characteristics noted under conditions BP = 3.6 V, -40 C  T_A 85 C, unless otherwise noted. Typical values at BP = 3.6 V

and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

SW2 BUCK REGULATOR (CONTINUED)

Switching Frequency

-

• PLLX = 0

• PLLX = 1

f_SW2

-

2.0

4.0

MHz

µA

Quiescent Current Consumption

• PWMPS or APS Mode, IL=0 mA; device not switching

• PFM Mode, IL = 0 mA; device not switching

I_SW2Q

-

160

15

-

Efficiency

• PFM, 0.9 V, 1.0 mA

-

54

75

83

78

-

(43)

• PWM Pulse skipping, 1.2 V, 120 mA

• PWM Pulse skipping, 1.2 V, 500 mA

• PWM, 1.2 V, 1000 mA

%

Notes:

42. Transient loading for load steps of ILMAX/2.

43. Efficiency numbers at V_IN= 3.6 V, excludes the quiescent current.

7.5.4.5

SW3

SW3 is fully integrated synchronous Buck PWM voltage mode control DC/DC regulator.

BP

SW3IN

SW3MODE

I_SENSE

C

INSW 3

Controller

SW3

SW3LX

Driver

L_SW3

D_SW3

C_OSW3

SW3FAULT

SPI

Interface

GNDSW3

Internal

Compensation

SPI

Z2

SW3FB

Z1

V_REF

EA

DAC

Figure 11. SW3 Block Diagram

The peak current is sensed internally for over-current protection purposes. If an over-current condition is detected the regulator

will limit the current through cycle by cycle operation and alert the system through the SW3FAULT SPI bit and issue an SCPI

interrupt via the INT pin.

SW3 can be programmed in step sizes of 25 mV as shown in Table 38.

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

48

Functional Block Description

Table 38. SW3 Output Voltage Programmability

Set Point

SW3[4:0]

SW3 Output (V)

Set Point

SW3[4:0]

SW3 Output (V)

0

1

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

0.6500

0.6750

0.7000

0.7250

0.7500

0.7750

0.8000

0.8250

0.8500

0.8750

0.9000

0.9250

0.9500

0.9750

1.0000

1.0250

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

1.0500

1.0750

1.1000

1.1250

1.1500

1.1750

1.2000

1.2250

1.2500

1.2750

1.3000

1.3250

1.3500

1.3750

1.4000

1.4250

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Table 39. SW3 Electrical Specification

Characteristics noted under conditions BP = 3.6 V, -40 C  T_A 85 C, unless otherwise noted. Typical values at BP = 3.6 V

and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

SW3 BUCK REGULATOR

Operating Input Voltage

• PWM operation, 0 < IL < I_MAX

• PFM operation, 0 < IL < IL_MAX

V_SW3IN

3.0

2.8

-

4.5

V

Output Voltage Accuracy

(44)

• PWM mode including ripple, load regulation, and transients

• PFM Mode, including ripple, load regulation, and transients

V_SW3ACC

Nom-3%

Nom

Nom+3%

mV

Continuous Output Load Current, V_INMIN< BP < 4.5 V

• PWM mode

• PFM mode

I_SW3

-

500

-

mA

A

50

Current Limiter Peak Current Detection

• V_IN= 3.6 V Current through Inductor

I_SW3PEAK

-

1.0

-

Transient Load Change

• 100 mA/µs

I_SW3

250

mA

mV

µs

TRANSIENT

V_SW3OS-

Start-up Overshoot, IL = 100 mA/µs

-

25

START

Turn-on Time

t_ON-SW3

• Enable to 90% of end value IL = 0

500

34709

Analog Integrated Circuit Device Data

49

Freescale Semiconductor

Functional Block Description

Table 39. SW3 Electrical Specification

Characteristics noted under conditions BP = 3.6 V, -40 C  T_A 85 C, unless otherwise noted. Typical values at BP = 3.6 V

and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

SW3 BUCK REGULATOR (CONTINUED)

Switching Frequency

• PLLX = 0

• PLLX = 1

f_SW3

-

2.0

4.0

-

MHz

µA

Quiescent Current Consumption

• PWMPS or APS Mode, IL=0 mA; device not switching

• PFM Mode, IL = 0 mA; device not switching

I_SW3Q

-

160

15

-

Efficiency

• PFM, 1.2 V, 1.0 mA

-

71

79

82

81

-

(45)

• PWM Pulse skipping, 1.2 V, 120 mA

• PWM Pulse skipping, 1.2 V, 250 mA

• PWM, 1.2 V, 500 mA

%

Notes:

44. Transient loading for load steps of ILMAX/2

45. Efficiency numbers at VIN=3.6 V, Excludes the quiescent current,

7.5.4.6

SW4

SW4A/B is fully integrated synchronous Buck PWM voltage mode control DC/DC regulator. It can be operated in (single phase/

dual phase mode) or as separate independent outputs. The operating mode of the Switching regulator is configured by the

SW4CFG pin. The SW4CFG pin is sampled at start-up.

Table 40. SW4A/B Configuration

SW4CFG

Ground

SW4A/B Configuration Mode

Separate independent output

Single phase

VCOREDIG

VCORE

Dual phase

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

50

Functional Block Description

BP

SW4IN

SW4AMODE

I_SENSE

C_{INSW 4A}

Controller

SW4A

SW4ALX

Driver

L_SW4A

C_OSW4A

D_{SW 4A}

SW4AFAULT

GNDSW4A

SW4AFB

Internal

Compensation

SPI

Z2

Z1

V_REF

EA

DAC

SPI

Interface

BP

SW4BIN

SW4BLX

SW4BMODE

I_SENSE

C_{INSW 4B}

Controller

SW4B

Driver

L_SW4B

C_{OSW 4B}

D_SW4B

SW4BFAULT

GNDSW4B

Internal

Compensation

SPI

Z2

SW4BFB

SW4CFG

Z1

V_REF

EA

DAC

Figure 12. SW4A/B Separate Output Mode Block Diagram

34709

Analog Integrated Circuit Device Data

51

Freescale Semiconductor

Functional Block Description

BP

SW4IN

SW4AMODE

SW4AFAULT

I_SENSE

C_INSW4A

Controller

SW4

SW4ALX

Driver

L_SW4A

C_OSW4a

D_SW4

GNDSW4A

Internal

Compensation

SPI

Z2

SW4AFB

Z1

V_REF

EA

DAC

SPI

Interface

BP

SW4BIN

SW4BMODE

I_SENSE

C_INSW4B

Controller

SW4BLX

Driver

SW4BFAULT

GNDSW4B

Internal

SPI

Compensation

Z2

SW4BFB

SW4CFG

Z1

V_REF

EA

DAC

VCOREDIG

Figure 13. SW4 Single Phase Output Mode Block Diagram

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

52

Functional Block Description

BP

SW4IN

SW4AMODE

SW4AFAULT

I_SENSE

C_INSW4A

Controller

SW4

SW4ALX

Driver

L_SW4A

C_OSW4A

D_SW4A

GNDSW4A

Internal

Compensation

SPI

Z2

SW4AFB

Z1

V_REF

EA

DAC

SPI

Interface

BP

SW4BIN

SW4BMODE

I_SENSE

C_INSW4B

Controller

SW4BLX

D_SW4B

Driver

L_SW4B

C_OSW4B

SW4BFAULT

GNDSW4B

Internal

SPI

Compensation

Z2

SW4BFB

SW4CFG

Z1

V_REF

EA

DAC

VCORE

Figure 14. SW4 Dual Phase Output Mode Block Diagram

The peak current is sensed internally for over-current protection purposes. If an over-current condition is detected, the regulator

will limit the current through cycle by cycle operation, alert the system through the SW4xFAULT SPI bit, and issue an SCPI

interrupt via the INT pin.

SW4A/B has a high output range (2.5 V or 3.15 V) and a low output range (1.2 V to1.85 V). The SW4A/B output range is set by

the PUMS configuration at startup and cannot be changed dynamically by software. This means that If the PUMS are set to allow

SW4A to come up in the high output voltage range, the output can only be changed between 2.5 V or 3.15 V. It cannot be

programmed in the low output range. If software sets the SW4AHI[1:0]= 00, when the PUMS is set to come up into the high

voltage range, the output voltage will only go as low as the lowest setting in the high range which is 2.5 V. If the PUMS are set

to start up in the low output voltage range, the voltage is controlled through the SW4x[4:0] bits by software. It cannot be

programmed into the high voltage range. When changing the voltage in either the high or low voltage range, the switcher should

be forced into PWM mode to change the voltage.

Table 41. SW4A/B Output Voltage Select

SW4xHI[1:0]

Set point selected by

Output Voltage

00

01

10

SW4x[4:0]

SW4xHI[1:0]

See Table 42

2.5 V

3.15 V

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

53

Functional Block Description

Table 42. SW4A/B Output Voltage Programmability

SW4x

Output (V)

Set Point SW4x[4:0]

Output (V)

0

1

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

1.2000

1.2250

1.2500

1.2750

1.3000

1.3250

1.3500

1.3750

1.4000

1.4250

1.4500

1.4750

1.5000

1.5250

1.5500

1.5750

16

17

18

19

20

21

22

23

24

25

26

-

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

-

1.6000

1.6250

1.6500

1.6750

1.7000

1.7250

1.7500

1.7750

1.8000

1.8250

1.8500

-

2

3

4

5

6

7

8

9

10

11

12

13

14

15

-

Table 43. SW4A/B Electrical Specifications

Characteristics noted under conditions BP = 3.6 V, -40 C  T_A 85 C, unless otherwise noted. Typical values at BP = 3.6 V

and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

SW4A/B Buck Regulator

(47)

Operating Input Voltage

• PWM operation, 0 < IL < I_MAX

• PFM operation, 0 < IL < IL_MAX

V_SW4IN

3.0

2.8

-

4.5

V

Output Voltage Accuracy

(46)

• PWM mode including ripple, load regulation, and transients

• PFM Mode, including ripple, load regulation, and transients

V_SW4ACC

Nom-3%

Nom

Nom+3%

mV

Continuous Output Load Current, V_INMIN< BP < 4.5 V

• PWM mode (separate)

-

500

1000

-

I_SW4

mA

A

• PWM mode single/dual phase

• PFM mode

50

Current Limiter Peak Current Detection

• V_IN= 3.6 V Current through Inductor (separate)

• Current through Inductor

I_SW4PEAK

-

1.0

2.0

-

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

54

Functional Block Description

Table 43. SW4A/B Electrical Specifications

Characteristics noted under conditions BP = 3.6 V, -40 C  T_A 85 C, unless otherwise noted. Typical values at BP = 3.6 V

and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

SW4A/B Buck Regulator (CONTINUED)

Transient Load Change

• Single/Dual Phase

• Separate

i_SW4

-

500

250

mA

TRANSIENT

• 100 mA/µs

V_SW4OS-

Start-up Overshoot, IL = 100 mA/µs

-

25

mV

µs

START

Turn-on Time

t_ON-SW4

• Enable to 90% of end value IL = 0

500

Switching Frequency

• PLLX = 0

f_SW4

-

2.0

4.0

-

MHz

µA

• PLLX = 1

Quiescent Current Consumption

• PWMPS or APS Mode, IL=0 mA; device not switching

• PFM Mode, IL = 0 mA; device not switching

I_SW4Q

-

160

15

-

Efficiency

-

79

93

92

82

72

71

81

78

-

• PFM, 3.15 V, 10 mA (A)

• PWM Pulse skipping, 3.15 V, 50 mA (A)

• PWM Pulse skipping, 3.15 V, 250 mA (A)

• PWM, 3.15 V, 500 mA (A)

(48)

%

• PFM, 1.2 V, 10 mA (B)

• PWM Pulse skipping, 1.2 V, 50 mA (B)

• PWM Pulse skipping, 1.2 V, 250 mA (B)

• PWM 1.2 V, 500 mA (B)

Notes:

46. Transient loading for load steps of IL_MAX/ 2.

47. When SW4A/B is set to 3.0 V and above the regulator may drop out of regulation when BP nears the output voltage.

48. Efficiency numbers at V_IN= 3.6 V, excludes the quiescent current.

34709

Analog Integrated Circuit Device Data

55

Freescale Semiconductor

Functional Block Description

7.5.4.7

SW5

SW5 is fully integrated synchronous Buck PWM voltage mode control DC/DC regulator.

BP

SW5IN

SW5MODE

I_SENSE

C_INSW5

Controller

SW5

SW5LX

Driver

L_SW5

C_OSW5

D_SW5

SW5FAULT

SPI

GNDSW5

Interface

Internal

Compensation

SPI

Z2

SW5FB

Z1

V_REF

EA

DAC

Figure 15. SW5 Block Diagram

The peak current is sensed internally for over-current protection purposes. If an over-current condition is detected the regulator

will limit the current through cycle by cycle operation and alert the system through the SW5FAULT SPI bit and issue an SCPI

interrupt via the INT pin.

SW5 can be programmed in step sizes of 25 mV as shown in Table 44. If the software wants to change the output voltage, after

power-up the regulator should be forced into PWM mode to change the voltage.

Table 44. SW5 Output Voltage Programmability

SW5

Output (V)

SW5

Output (V)

Set Point SW5[4:0]

0

1

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

1.2000

1.2250

1.2500

1.2750

1.3000

1.3250

1.3500

1.3750

1.4000

1.4250

1.4500

1.4750

1.5000

1.5250

1.5500

1.5750

16

17

18

19

20

21

22

23

24

25

26

-

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

-

1.6000

1.6250

1.6500

1.6750

1.7000

1.7250

1.7500

1.7750

1.8000

1.8250

1.8500

-

2

3

4

5

6

7

8

9

10

11

12

13

14

15

-

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

56

Functional Block Description

Table 45. SW5 Electrical Specifications

Characteristics noted under conditions BP = 3.6 V, -40 C  T_A 85 C, unless otherwise noted. Typical values at BP = 3.6 V

and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

SW5 BUCK REGULATOR

Operating Input Voltage

• PWM operation, 0 < IL < I_MAX

• PFM operation, 0 < IL < IL_MAX

V_SW5IN

3.0

2.8

-

4.5

V

Output Voltage Accuracy

(49)

• PWM mode including ripple, load regulation, and transients

• PFM Mode, including ripple, load regulation, and transients

V_SW5ACC

Nom-3%

Nom

Nom+3%

mV

Continuous Output Load Current, V_INMIN< BP < 4.5 V

• PWM mode

• PFM mode

I_SW5

-

1000

-

mA

A

50

Current Limiter Peak Current Detection

• V_IN= 3.6 V Current through Inductor

I_SW5PEAK

-

2.0

-

Transient Load Change

• 100 mA/µs

I_SW5

mA

mV

µs

-

500

25

TRANSIENT

V_SW5

Start-up Overshoot, IL = 0

OS-START

Turn-on Time

t_ON-SW5

• Enable to 90% of end value IL = 0

-

500

Switching Frequency

• PLLX = 0

f_SW5

-

2.0

4.0

-

MHz

µA

• PLLX = 1

Quiescent Current Consumption

• PWMPS or APS Mode, IL=0 mA; device not switching

• PFM Mode, IL = 0 mA; device not switching

I_SW5Q

-

160

15

-

Efficiency

• PFM, 1.8 V, 1.0 mA

-

80

79

86

82

-

(50)

• PWM Pulse skipping, 1.8 V, 50 mA

• PWM Pulse skipping, 1.8 V, 500 mA

• PWM, 1.8 V, 1000 mA

%

Notes

49. Transient Loading for load Steps of ILMAX/2

50. Efficiency numbers at VIN=3.6 V, Excludes the quiescent current.

34709

Analog Integrated Circuit Device Data

57

Freescale Semiconductor

Functional Block Description

7.5.4.8

Dynamic Voltage Scaling

To reduce overall power consumption, processor core voltages can be varied depending on the mode or activity level of the

processor. SW1A/B and SW2 allow for two different set points with controlled transitions to avoid sudden output voltage changes,

which could cause logic disruptions on their loads.

Preset operating points for SW1A/B and SW2 can be set up for:

• Normal operation: output value selected by SPI bits SWx[5:0]. Voltage transitions initiated by SPI writes to SWx[5:0] are

governed by the DVS stepping rate shown in the following tables.

• Standby (Deep Sleep): can be higher or lower than normal operation, but is typically selected to be the lowest state retention

voltage of a given process. Set by SPI bits SWxSTBY[5:0] and controlled by a Standby event. Voltage transitions initiated by

Standby are governed by the SWxDVSSPEED[1:0] SPI bits shown in Table 46.

The following table summarizes the set point control and DVS time stepping applied to SW1A/B and SW2.

Table 46. DVS Control Logic Table for SW1A/B and SW2

STANDBY

Set Point Selected by

0

1

SWx[4:0]

SWxSTBY[4:0]

Table 47. DVS Speed Selection

SWxDVSSPEED[1:0]

Function

00

01 (default)

10

12.5 mV step each 2.0 s

12.5 mV step each 4.0 s

12.5 mV step each 8.0 s

12.5 mV step each 16.0 s

11

The regulator has a strong sourcing and sinking capability in the PWM mode. Therefore, the rising/falling slope is determined by

the regulator in PWM mode. However, if the regulators are programmed in PFM, PWMPS, or APS mode during a DVS transition,

the falling slope can be influenced by the load. Additionally, as the current capability in PFM mode is reduced, controlled DVS

transitions in PFM mode could be affected. Critically timed DVS transitions are best assured with PWM mode operation.

Voltage transitions programmed through SPI(SWx[4:0]) on SW3 and SW5 will step in increments of 25 mV per 4.0 s, SW4A/B

will step in increments of 25 mV per 8.0 s when SW4xHI[1:0]=00, and SW4A/B will step in increments of 25 mV per 16 s when

SW4xHI[1:0]≠00. Additionally, SW3, SW4/B, and SW5 include standby mode set point programmability.

The following diagram shows the general behavior for the switching regulators when initiated with SPI programming or standby

control.

SW1 and SW2 also contain Power Good (outputs from the 34709 to the application processor). The power good signal is an

active high signal. When SWxPWRGDB is high, it means that the regulators output has reached its programmed voltage. The

SWxPWRGDB voltage outputs will be low during the DVS period and if the current limit is reached on the switching regulator.

The SWxPWRGD will be low from a low to high or a high to low transition of the regulator output voltage. During the DVS period,

the over-current condition on the switching regulator should be masked. If the current limit is reached outside of a DVS period,

the SWxPWRGD pin will stay low until the current limit condition is removed.

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Functional Block Description

Requested

Set Point

Output Voltage

with light Load

Internally

Controlled Steps

Example

Actual Output

Voltage

Output

Voltage

Init ial

Set Point

Actual

Output Voltage

Internally

Possible

Output Voltage

Window

Controlled Steps

Request for

Higher Voltage

Request for

Lower Voltage

Voltage

Change

Request

Initiated by SPI Programming, Standby Control

SWxPWGD

Figure 16. Voltage Stepping with DVS

7.5.5

Boost Switching Regulator

SWBST is a boost switching regulator with a programmable output, which defaults to 5.0 V on power-up, operating at 2.0 MHz.

SWBST supplies the VUSB regulator for the USB PHY. Note that the parasitic leakage path for a boost regulator will cause the

output voltage SWBSTOUT and SWBSTFB to sit at a Schottky voltage drop below the battery voltage whenever SWBST is

disabled. The switching NMOS transistor is integrated on-chip. An external fly back Schottky diode, inductor, and capacitor are

required.

BP

4.7u

SWBSTIN

SWBST

SPI

Registers

2.2uH

SPI

Boosted Output

Voltage SWBST

SWBSTIN

SWBSTLX

Output

Drive

Switcher

Core

32 kHz

Control

22uF

SWBSTFB

GNDSWBST

= Package Pin

Figure 17. Boost Regulator Architecture

SWBST output voltage programmable via the SWBST[1:0] SPI bits as shown in Table 48.

Table 48. SWBST Voltage Programming

Parameter

Voltage

SWBST Output Voltage

00

01

10

11

5.000 (default)

5.050

SWBST[1:0]

5.100

5.150

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Functional Block Description

SWBST can be controlled by SPI programming in PFM, PWM, and Auto mode. Auto mode transitions between PFM and PWM

mode based on the load current. By default SWBST is powered up in Auto mode.

Table 49. SWBST Mode Control

Parameter

Voltage

SWBST Mode

00

01

10

11

Off

PFM

SWBSTMODE[1:0]

SWBSTSTBYMODE[1:0]

Auto (default)

PWM

Table 50. SWBST Electrical Specifications

Characteristics noted under conditions BP = 3.6 V, -40 C  T  85 C, unless otherwise noted. Typical values at BP = 3.6 V

A

and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

SWITCH MODE SUPPLY SWBST

(51)

Average Output Voltage

V_SWBST

V

• 3.0 V < V_IN< 4.5 V, 0 < IL < IL_MAX

Nom-4%

-

V_NOM

Nom+3%

120 mV

Output Ripple

V_SWBSTACC

• 3.0 V < V_IN< 4.5 V 0 < IL < IL_MAX, excluding reverse recovery of

Schottky diode

Vp-p

-

Average Load Regulation

SWBST_ACC

mV/mA

mV

• V_IN= 3.6 V, 0 < IL < IL_MAX

-

0.5

50

-

Average Line Regulation

V_SWBST

• 3.0 V < V_IN< 4.5 V IL = IL_MAX

LINEAREG

Continuous Load Current

I_SWBST

mA

• 3.0 V < V_IN< 4.5 V, V_OUT= 5.0 V

380

Peak Current Limit

I_SWBSTPEAK

mA

mV

• At SWBSTIN, V_IN= 3.6 V

-

1800

-

V_SWBSTOS-

Start-up Overshoot, IL = 0 mA

500

START

Turn-on Time

t_ON-SWBST

f_SWBST

ms

MHz

mV

• Enable to 90% of V_OUTIL = 0

-

2.0

-

Switching Frequency

2.0

Transient Load Response, IL from 1.0 to 100 mA in 1.0 µs steps

• Maximum transient Amplitude

V_SWBS

-

300

500

TRANSIENT

Transient Load Response, IL from 100 to 1.0 mA in 1.0 µs steps

• Maximum transient Amplitude

V_SWBS

mV

µs

TRANSIENT

Transient Load Response, IL from 1.0 to 100 mA in 1.0 µs steps

• Time to settle 80% of transient

V_SWBS

TRANSIENT

Transient Load Response, IL from 100 to 1.0 mA in 1.0 µs steps

• Time to settle 80% of transient

V_SWBS

ms

%

-

20

-

TRANSIENT

Efficiency, IL = IL_MAX

65

80

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Functional Block Description

Table 50. SWBST Electrical Specifications

Characteristics noted under conditions BP = 3.6 V, -40 C  T  85 C, unless otherwise noted. Typical values at BP = 3.6 V

A

and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

SWITCH MODE SUPPLY SWBST (CONTINUED)

Bias Current Consumption

I_SWBSTBIAS

µA

• PFM or Auto mode

-

35

-

NMOS Off Leakage

I_LEAK-SWBST

• SWBSTIN = 4.5 V, SWBSTMODE [1:0] = 0

1.0

6.0

Notes:

51. V_INis the low side of the inductor that is connected to BP.

7.5.6

Linear Regulators (LDOs)

This section describes the linear regulators provided. For convenience, these regulators are named to indicate their typical or

possible applications, but the supplies are not limited to these uses and may be applied to any loads within the specified regulator

capabilities.

A low-power standby mode controlled by STANDBY is provided for the regulators with an external pass device in which the bias

current is aggressively reduced. This mode is useful for deep sleep operation, where certain supplies cannot be disabled, but

active regulation can be tolerated with lesser parametric requirements. The output drive capability and performance are limited

in this mode.

All regulators use the main bandgap as reference. The main bandgap is bypassed with a capacitor at REFCORE. The bandgap

and the rest of the core circuitry are supplied from VCORE. The performance of the regulators is directly dependent on the

performance of VCOREDIG and the bandgap. No external DC loading is allowed on VCOREDIG or REFCORE. VCOREDIG is

kept powered as long as there is a valid supply and/or coin cell.

7.5.6.1

General Features

The following applies to all linear regulators, unless otherwise specified.

•

Advised bypass capacitor is the Murata GRM155R60G225ME95, which comes in a 0402 case.

In general, parametric performance specifications assume the use of low ESR X5R/X7R ceramic capacitors with 20%

accuracy and 15% temperature spread, for a worst case stack up of 35% from the nominal value. Use of other types with wider

temperature variation may require a larger room temperature nominal capacitance value to meet performance specs over

temperature. In addition, capacitor derating as a function of DC bias voltage requires special attention. Finally, minimum

bypass capacitor guidelines are provided for stability and transient performance. Larger values may be applied; performance

metrics may be altered and generally improved, but should be confirmed in system applications.

Regulators which require a minimum output capacitor ESR (those with external PNPs) can avoid an external resistor if ESR

is assured with capacitor specifications or board level trace resistance.

The output voltage tolerance specified for each of the linear regulators include process variation, temperature range, static

line regulation, and static load regulation.

In the Low-power mode, the output performance is degraded. Only those parameters listed in the Low-power mode section

are guaranteed. In this mode, the output current is limited to much lower currents than in the active mode.

When a regulator gets disabled, the output will be pulled towards ground by an internal pull-down. The pull-down is also

activated when RESETB goes low.

•

7.5.6.2

LDO Regulator Control

The regulators with embedded pass devices (VPLL, VGEN1, and VUSB) have an adaptive biasing scheme thus, there are no

distinct operating modes such as a Normal mode and a Low-power mode. Therefore, no specific control is required to put these

regulators in a Low-power mode.

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Functional Block Description

The external pass regulator (VDAC) can also operate in a normal and low-power mode. However, since a load current detection

cannot be performed for this regulator, the transition between both modes is not automatic and is controlled by setting the

corresponding mode bits for the operational behavior desired.

The regulators VUSB2, and VGEN2 can be configured for using the internal pass device or external pass device as explained in

Supplies. For both configurations, the transition between both modes is controlled by setting the VxMODE bit for the specific

regulator. Therefore, depending on the configuration selected, the automatic Low-power mode determines availability.

The regulators can be disabled and the general purpose outputs can be forced low when going into Standby (note that the

Standby response timing can be altered with the STBYDLY function, as described in the previous section). Each regulator has

an associated SPI bit for this. When the bit is not set, STANDBY is of no influence. The actual operating mode of the regulators

as a function of STANDBY is not reflected through SPI. In other words, the SPI will read back what is programmed, not the actual

state.

Table 51. LDO Regulator Control (external pass device LDOs)

VxEN

VxMODE

VxSTBY STANDBY⁽⁵²⁾

Regulator Vx

0

1

X

0

1

X

0

1

X

0

1

X

0

1

Off

On

Low-power

On

Off

Low-power

Notes

52. STANDBY refers to a Standby event as described earlier

For regulators with internal pass devices, the previous table can be simplified by elimination of the VxMODE column.

Table 52. LDO Regulator Control (internal pass device LDOs)

VxEN

VxSTBY

STANDBY ⁽⁵³⁾

Regulator Vx

0

1

X

0

1

X

0

1

Off

On

Off

Notes

53. STANDBY refers to a Standby event as described earlier

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62

Functional Block Description

7.5.6.3

Transient Response Waveforms

The transient load and line response are specified with the waveforms as depicted in Figure 18. Note that where the transient

load response refers to the overshoot only, so excluding the DC shift itself, the transient line response refers to the sum of both

overshoot and DC shift. This is also valid for the mode transition response.

V

_NOM+ 0.8V

I_MAX

I_L

V_IN

V_NOM+ 0.3V

0 mA

10us

1us

V_INStimulus for Transient Line Response

I_LStimulus for Transient Load Response

I_L= 0 mA

I_L= IL_MAX

Overshoot

V_OUT

Overshoot

V_OUTfor Transient Load Response

Active Mode

Low Power Mode

Active Mode

Overshoot

V_OUT

Mode Transition

Time

Overshoot

I_L< IL_MAX

I_L< IL_MAXLP

I_L< IL_MAX

V_OUTfor Mode Transition Response

Figure 18. Transient Waveforms

7.5.6.4

Short-circuit Protection

The higher current LDOs, and those most accessible in product applications, include short-circuit detection and protection

(VDAC, VUSB, VUSB2, VGEN1, and VGEN2). The short-circuit protection (SCP) system includes debounced fault condition

detection, regulator shutdown, and processor interrupt generation, to contain failures and minimize the chance of product

damage. If a short-circuit condition is detected, the LDO will be disabled by resetting its VxEN bit, while at the same time, an

interrupt SCPI will be generated to flag the fault to the system processor. The SCPI interrupt is maskable through the SCPM

mask bit.

The SCP feature is enabled by setting the REGSCPEN bit. If this bit is not set, then not only is no interrupt generated, but also

the regulators will not automatically be disabled upon a short-circuit detection. However, the built-in current limiter will continue

to limit the output current of the regulator. Note that by default, the REGSCPEN bit is not set, so at start-up, none of the regulators

in an overload condition are disabled.

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Functional Block Description

7.5.6.5

VPLL

VPLL is provided for isolated biasing of the application processors PLLs for clock generation in support of protocol and peripheral

needs. Depending on the application and power requirements, this supply may be considered for sharing with other loads, but

noise injection must be avoided and filtering added, if necessary to ensure suitable PLL performance. The VPLL regulator has a

dedicated input supply pin.

VINPLL can be connected to either BP or a 1.8 V switched mode power supply rail such as from SW5 for the two lower set points

of each regulator VPLL[1:0] = [00], [01]. In addition, when the two upper set points (VPLL[1:0] = [10],[11]) are used, the VINPLL

inputs can be connected to either BP or a 2.2 V nominal external switched mode power supply rail, to improve power dissipation.

Table 53. VPLL Voltage Control

Parameter Value

Function

ILoad max

Input Supply

00

output = 1.2 V

50 mA

BP or 1.8 V

01 output = 1.25 V

10 output = 1.50 V

VPLL[1:0]

BP or External switch

11

output = 1.8 V

Table 54. VPLL Electrical Specification

Characteristics noted under conditions BP = 3.6 V, -40 C  T  85 C, unless otherwise noted. Typical values at BP = 3.6 V

A

and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

GENERAL

Operating Input Voltage Range

• VPLL all settings, BP biased

UVDET

1.75

-

4.5

V_INPLL

V

• VPLL [1:0] = 00, 01 (SW5 = 1.8 V)

• VPLL, [1:0] = 10, 11, External Switch

1.8

2.2

2.15

Operating current Load range

I_PLL

-

50

mA

VPLL ACTIVE MODE – DC

Output Voltage V_OUT

V_PLL

V

V_NOM

– 0.05

V_NOM

+ 0.05

• V_INMIN< V_IN< V_INMAXIL_MIN< IL < IL_MAX

V_NOM

Load Regulation

V_PLL-LOPP

V_PLL-LIPP

I_PLL-Q

mV/mA

mV

• 1.0 mA < IL < IL_MAXFor any V_INMIN< V_IN< V_INMAX

-

0.35

5.0

8.0

75

-

Line Regulation

• V_INMIN< V_IN< V_INMAXFor any IL_MIN< IL < IL_MAX

Quiescent Current

µA

• V_INMIN< V_IN< V_INMAXIL = 0

Current Limit

I_PLLLIM

mA

• V_INMIN< V_IN< V_INMAX

VPLL ACTIVE MODE – AC

PSRR, IL = 75% of IL_MAX, 20 Hz to 20 kHz

• V_IN= UVDET

VPLL_PSRR

35

50

40

60

-

dB

• V_IN= V_NOM+ 1.0 V, > UVDET

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Functional Block Description

Table 54. VPLL Electrical Specification

Characteristics noted under conditions BP = 3.6 V, -40 C  T  85 C, unless otherwise noted. Typical values at BP = 3.6 V

A

and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

Output Noise Density, V_IN= V_INMINIL = 75% of IL_MAX

• 100 Hz – 1.0 kHz

VPLL_NOISE

-

20

-

dB/dec

• > 1.0 kHz – 1.0 MHz

2.5

V/Hz

VPLL ACTIVE MODE – AC (CONTINUED)

Turn-on Time

t_ON-VPLL

µs

ms

%

• Enable to 90% of end value V_IN= V_INMIN, V_INMAXIL = 0

-

140

10

Turn-off Time

• Disable to 10% of initial value V_IN= V_INMIN, V_INMAX, IL = 0

t_OFF-VPLL

0.05

-

Start-up Overshoot

VPLL_OS-

• V_IN= V_INMIN, V_INMAXIL = 0

-

1.0

50

5.0

2.0

70

START

Transient Load Response

• V_IN= V_INMIN, V_INMAX

V_PLL-LO

mV

TRANSIENT

Transient Line Response

• IL = 75% of IL_MAX

V_PLL-LI

8.0

TRANSIENT

7.5.6.6

VREFDDR

VREFDDR is an internal PMOS half supply Voltage Follower. The output voltage is at one half the input voltage. It’s typical

application is as the V for DDR memories. A filtered resistor divider is utilized to create a low frequency pole. This divider then

REF

utilizes a voltage follower to drive the load.

Table 55. VREFDDR Electrical Specification

Characteristics noted under conditions BP = 3.6 V, -40 C  T  85 C, unless otherwise noted. Typical values at BP = 3.6 V

A

and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

GENERAL

V_REFFDDRIN

I_REFDDR

Operating Input Voltage Range V_INMINto V_INMAX

Operating Current Load Range IL_MINto IL_MAX

1.2

0.0

-

1.8

10

V

mA

VREFDDR ACTIVE MODE – DC

Output Voltage V_OUT

V_REFDDR

V

• V_INMIN< V_IN< V_INMAXIL_MIN< IL < IL_MAX

0.6

V_IN/2

0.9

1.0

(54)

Output Voltage tolerance

• V_INMIN< V_IN< V_INMAX

• 0.6 mA < IL < 10 mA

V_REFDDRTOL

%

-1.0

-

Load Regulation

V_REFDDR

mV/mA

µA

• 1.0 mA < IL < IL_MAXFor any V_INMIN< V_IN< V_INMAX

-

5.0

8.0

36

-

LOPP

Quiescent Current

I_REFDDRQ

• V_INMIN< V_IN< V_INMAXIL = 0

Current Limit

I_REFDDRLIM

mA

• V_INMIN< V_IN< V_INMAX

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Functional Block Description

Table 55. VREFDDR Electrical Specification

Characteristics noted under conditions BP = 3.6 V, -40 C  T  85 C, unless otherwise noted. Typical values at BP = 3.6 V

A

and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

VREFDDR ACTIVE MODE – AC

Turn-on Time

t_ON-VREFDDR

µs

• Enable to 90% of end value V_IN= V_INMIN, V_INMAXIL = 0

-

100

10

Turn-off Time

• Disable to 10% of initial value V_IN= V_INMIN, V_INMAX, IL = 0

t_OFF-

ms

0.05

VREFDDR

VREFDDR ACTIVE MODE – AC (CONTINUED)

Start-up Overshoot

V_REFDDROS

%

• V_IN= V_INMIN, V_INMAXIL = 0

-

1.0

5.0

2.0

-

Transient Load Response

V_REFDDRL

mV

• V_IN= V_INMIN, V_INMAX

TRANSIENT

Notes

54. guaranteed at 25 °C only

7.5.6.7

VUSB

The VUSB regulator is used to supply 3.3 V to the external USB PHY, it is powered from the SWBST boost supply to ensure

current sourcing compliance through the normal discharge range of the battery/supply input. VUSB has an internal PMOS pass

FET which will support loads up to 100 mA.

Table 56. VUSB Electrical Characteristics

Characteristics noted under conditions BP = 3.6 V, -40 C  T  85 C, unless otherwise noted. Typical values at BP = 3.6 V

A

and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

VUSB REGULATOR

Operating Input Voltage Range V_INMINto V_INMAX

• Supplied by SWBST

V_USBIN

V

V_SWBST

4%

-

V_SWBST+3

%

-

Operating Current Load Range IL_MINto IL_MAX

I_USB

0.0

100

mA

VUSB ACTIVE MODE - DC

Output Voltage V_OUT

V_USB

V

mV/mA

mV

• V_INMIN< V_IN< V_INMAXIL_MIN< IL < IL_MA

V_NOM- 4%

3.3

1.0

-

V_NOM+ 4%

Load Regulation

V_USBLOPP

V_USBLIPP

V_USBSOCP

I_USBLIM

• 0 < IL < IL_MAXfrom DM / DP, For any V_INMIN< V_IN< V_INMAX

-

20

-

Line Regulation

• V_INMIN< V_IN< V_INMAX, For any IL_MIN< IL < IL_MAX

-

Over-current Protection threshold

mA

• V_INMIN< V_IN< V_INMAX, Short-circuit V_OUTto ground

I_MAX+20%

-

Current Limit

mA

• V_INMIN< V_IN< V_INMAX

-

180

-

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Functional Block Description

Table 56. VUSB Electrical Characteristics

Characteristics noted under conditions BP = 3.6 V, -40 C  T  85 C, unless otherwise noted. Typical values at BP = 3.6 V

A

and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

VUSB ACTIVE MODE - AC

PSRR - IL = 75% of IL_MAX20 Hz to 20 kHz

• V_IN= V_INMIN+ 100 mV

VUSB_PSRR

VUSB_NOISE

dB

35

40

-

Output Noise - V_IN= V_INMINIL = 75% of IL_MAX

• 100 Hz – 50 kHz

-

1.0

0.2

V/Hz

• > 50 kHz – 1.0 MHz

7.5.6.8

VUSB2

VUSB2 has an internal PMOS pass FET which will support loads up to 65 mA. To support load currents an external PNP is

provided. The external PNP configuration is offered to avoid excess on-chip power dissipation at high loads and large differentials

between BP and output settings. For lower current requirements, an integrated PMOS pass FET is included. The input pin for

the integrated PMOS option is shared with the base current drive pin for the PNP option. The external PNP configuration must

be committed as a hardwired board level implementation. The recommended PNP device is the ON Semiconductor™

NSS12100XV6T1G, which is capable of handling up to 250 mW of continuous dissipation, at minimum footprint and 75 °C of

ambient. For use cases where up to 500 mW of dissipation is required, the recommended PNP device is the ON Semiconductor

NSS12100UW3TCG. For stability reasons, a small minimum ESR may be required.

A short-circuit condition will shut down the VUSB2 regulator and generate an interrupt for SCPI.

The nominal output voltage of this regulator is SPI configurable, and can be 2.5 V, 2.6 V, 2.75 V, or 3.0 V. The output current

when working with the internal pass FET is 65 mA, and could be up to 350 mA when working with an external PNP.

Table 57. VUSB2 Voltage Control

ILoad max

Output

Voltage

Parameter Value

VUSB2CONFIG=0 VUSB2CONFIG=1

Internal Pass FET

External PNP

00

01

10

11

2.5 V

2.6 V

65 mA

350 mA

VUSB2[1:0]

2.75 V

3.00 V

Table 58. VUSB2 Electrical Specification

Characteristics noted under conditions BP = 3.6 V, -40 C  T  85 C, unless otherwise noted. Typical values at BP = 3.6 V

A

and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

GENERAL

V_NOM

0.25

+

Operating Input Voltage Range V_INMINto V_INMAX

V_USB2IN

-

4.5

V

Operating Current Load Range IL_MINto IL_MAX

• Internal pass FET

I_USB2

0.0

-

65

mA

• External PNP Not exceeding PNP max power

350

Extended Input Voltage Range

V_USB2IN

V

• Performance may be out of specification

UVDET

-

4.5

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Functional Block Description

Table 58. VUSB2 Electrical Specification

Characteristics noted under conditions BP = 3.6 V, -40 C  T  85 C, unless otherwise noted. Typical values at BP = 3.6 V

A

and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

VUSB2 ACTIVE MODE - DC

Output Voltage V_OUT

V_USB2

V

• V_INMIN< V_IN< V_INMAXIL_MIN< IL < IL_MAX

V_NOM- 3%

V_NOM

0.25

8.0

V_NOM+ 3%

Load Regulation

V_USB2LOPP

mV/mA

mV

• 1.0 mA < IL < IL_MAXFor any V_INMIN< V_IN< V_INMAX

-

Line Regulation

V_USB2LIPP

• V_INMIN< V_IN< V_INMAXFor any IL_MIN< IL < IL_MAX

Over-current Protection threshold

VUSB2_OCP

mA

µA

IL_MAX

+20%

• V_INMIN< V_IN< V_INMAXShort-circuit V_OUTto GND

-

Active Mode Quiescent Current, V_INMIN< V_IN< V_INMAX

• IL = 0, Internal PMOS configuration

I_USB2Q

-

25

30

-

• V_INMIN< V_IN< V_INMAXIL = 0, External PNP configuration

Current Limit

• External PNP mode only

• V_INMIN< V_IN< V_INMAX

I_USB2LIM

-

4.62*

-

mA

• Current on VUSB2DRV multiplied by  of external PNP transistor

(I_USB2DRVwhen VSUSB2DRV is forced to LDOVDD)

VUSB2 LOW-POWER MODE - DC

Output Voltage V_OUT

V_USB2

V

• V_INMIN< V_IN< V_INMAXIL_MINLP< IL < IL_MAXLP

V_NOM- 3%

0.0

V_NOM

-

V_NOM+ 3%

3.0

Current Load Range IL_MINLPto IL_MAXLP

I_USB2

mA

µA

Low-power Mode Quiescent Current

• V_INMIN< V_IN< V_INMAXIL = 0

I_USB2Q

-

8.0

-

VUSB2 ACTIVE MODE - AC

PSRR, IL = 75% of IL_MAX20 Hz to 20 kHz

• V_IN= V_INMIN+ 100 mV

• V_IN= V_NOM+ 1.0 V

VUSB2_PSRR

35

50

40

60

-

dB

Output Noise Density, V_IN= V_INMINIL = 75% of IL_MAX

• 100 Hz – 1.0 kHz

VUSB

2_NOISE

-

20

-

dB/dec

• > 1.0 kHz – 1.0 MHz

1.0

V/Hz

Turn-on Time

t_ON-VUSB2

ms

%

• Enable to 90% of end value V_IN= V_INMIN, V_INMAXIL = 0

-

0.05

-

1.0

10

Turn-off Time

t_OFF-VUSB2

• Disable to 10% of initial value V_IN= V_INMIN, V_INMAXIL = 0

Start-up Overshoot

VUSB2_OS-

• V_IN= V_INMIN, V_INMAXIL = 0

1.0

2.0

START

Transient Load Response, V_IN= V_INMIN, V_INMAX

• VUSB2=01, 10, 11

x

VUSB2_LO

-

1.0

50

2.0

70

%

TRANSIENT

• VUSB2=00

mV

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Functional Block Description

Table 58. VUSB2 Electrical Specification

Characteristics noted under conditions BP = 3.6 V, -40 C  T  85 C, unless otherwise noted. Typical values at BP = 3.6 V

A

and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

Transient Line Response

• IL = 75% of IL_MAX

VUSB2_LI

mV

-

5.0

8.0

TRANSIENT

Mode Transition Time

t_MOD-VUSB2

• From low-power to active and from active to low-power

_IN= V_INMIN, V_INMAXIL = IL_MAXLP

µs

%

-

100

2.0

V

Mode Transition Response

VUSB_MODE

• From low-power to active and from active to low-power

1.0

RES

V_IN= V_INMIN, V_INMAXIL = IL_MAXLP

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Functional Block Description

7.5.6.9

VDAC

The primary applications of this power supply is the TV-DAC. However, these supplies could also be used for other peripherals

if one of these functions is not required. Low-power modes and programmable standby options can be used to optimize power

efficiency during deep sleep modes.

An external PNP is utilized for VDAC to avoid excess on-chip power dissipation at high loads and large differentials between BP

and output settings. For stability reasons, a small minimum ESR may be required. In the Low-power mode for VDAC, an internal

bypass path is used instead of the external PNP. External PNP devices must always be connected to the BP line in the

application. The recommended PNP device is the ON Semiconductor NSS12100XV6T1G, which is capable of handling up to

250 mW of continuous dissipation at minimum footprint and 75 °C of ambient. For use cases where up to 500 mW of dissipation

is required, the recommended PNP device is the ON Semiconductor NSS12100UW3TCG. For stability reasons, a small minimum

ESR may be required.

A short-circuit condition will shut down the VDAC regulator and generate an interrupt for SCPI.

The nominal output voltage of this regulator is SPI configurable, and can be 2.5 V, 2.6 V, 2.7 V, or 2.775 V. The maximum output

current along with an external PNP, is 250 mA.

Table 59. VDAC Voltage Control

Parameter

Value

Output Voltage

ILoad max

00

01

10

11

2.500 V

2.600 V

2.700 V

2.775 V

250 mA

VDAC

Table 60. VDAC Electrical Specification

Characteristics noted under conditions BP = 3.6 V, -40 C  T  85 C, unless otherwise noted. Typical values at BP = 3.6 V

A

and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

GENERAL

V_NOM

0.25

+

Operating Input Voltage Range V_INMINto V_INMAX

V_DACIN

-

4.5

V

Operating Current Load Range IL_MINto IL_MAX

• Not exceeding PNP max power

I_DAC

mA

0.0

-

250

4.5

Extended Input Voltage Range

V_DACIN

V

• Performance may be out of specification

UVDET

VDAC ACTIVE MODE – DC

Output Voltage V_OUT

V_DAC

V

• V_INMIN< V_IN< V_INMAXIL_MIN< IL < IL_MAX

V_NOM– 3%

V_NOM

0.20

5.0

V_NOM+ 3%

Load Regulation

V_DACLOPP

mV/mA

mV

• 1.0 mA < IL < IL_MAXFor any V_INMIN< V_IN< V_INMAX

-

Line Regulation

V_DACLIPP

• V_INMIN< V_IN< V_INMAXFor any IL_MIN< IL < IL_MAX

Over-current Protection threshold

VDAC_OCP

mA

µA

IL_MAX

+20%

• V_INMIN< V_IN< V_INMAXShort-circuit V_OUTto GND

-

Active Mode Quiescent Current

• V_INMIN< V_IN< V_INMAXIL = 0

I_DACQ

-

30

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Functional Block Description

Table 60. VDAC Electrical Specification

Characteristics noted under conditions BP = 3.6 V, -40 C  T  85 C, unless otherwise noted. Typical values at BP = 3.6 V

A

and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

Current Limit

• External PNP mode only

• V_INMIN< V_IN< V_INMAX

I_DACLIM

-

3.2*

-

mA

• Current on VDACDRV multiplied by  of external PNP transistor

(I_DACDRVwhen VDACDRV is forced to LDOVDD)

VDAC LOW-POWER MODE – DC - VDACMODE=1

Output Voltage V_OUT

V_DAC

V

• V_INMIN< V_IN< V_INMAXIL_MINLP< IL < IL_MAXLP

V_NOM– 3%

0.0

V_NOM

-

V_NOM+ 3%

3.0

Current Load Range IL_MINLPto IL_MAXLP

I_DAC

mA

µA

Low-power Mode Quiescent Current

• V_INMIN< V_IN< V_INMAXIL = 0

I_DACQ

-

8.0

-

VDAC ACTIVE MODE – AC

PSRR - IL = 75% of IL_MAX20 Hz to 20 kHz

• V_IN= V_INMIN+ 100 mV

• V_IN= V_NOM+ 1.0 V

VDAC_PSRR

35

50

40

60

-

dB

Output Noise Density, V_IN= V_INMINIL = 75% of IL_MAX

• 100 Hz – 1.0 kHz

-

-115

-126

-132

VDAC_NOISE

V/Hz

• > 1.0 kHz – 10 kHz

• > 10 kHz – 1.0 MHz

Spurs

VDAC_SPURS

dB

ms

%

• 32.768 kHz and harmonics

-

-120

1.0

10

Turn-on Time

t_ON-VDAC

• Enable to 90% of end value V_IN= V_INMIN, V_INMAXIL = 0

-

Turn-off Time

t_OFF-VDAC

• Disable to 10% of initial value V_IN= V_INMIN, V_INMAX, IL = 0

0.05

-

Start-up Overshoot

VDAC_OS-

• V_IN= V_INMIN, V_INMAXIL = 0

-

1.0

5.0

-

2.0

8.0

100

START

Transient Load Response

• V_IN= V_INMIN, V_INMAX

VDAC_LO

%

TRANSIENT

Transient Line Response

• IL = 75% of IL_MAX

V_DACLI

mV

µs

TRANSIENT

Mode Transition Time

t_MODE-VDAC

• From low-power to active V_IN= V_INMIN, V_INMAXIL = IL_MAXLP

Mode Transition Response

VDAC_MODE

• From low-power to active and from active to low-power

%

-

1.0

2.0

RES

V_IN= V_INMIN, V_INMAXIL = IL_MAXLP

7.5.6.10 VGEN1, VGEN2

General purpose LDOs, VGEN1, and VGEN2, are provided for expansion of the power tree to support peripheral devices, which

could include EMMC cards, WLAN, BT, GPS, or other functional modules. These regulators include programmable set points for

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Functional Block Description

system flexibility. VGEN1 has an internal PMOS pass FET, and is powered from the SW5 buck for an efficiency advantage and

reduced power dissipation in the pass devices. VGEN2 is powered directly from the battery.

VGEN2 has an internal PMOS pass FET, which will support loads up to 50 mA. For higher current capability, drive for an external

PNP is provided. The external PNP is offered to avoid excess on-chip power dissipation at high loads and large differentials

between BP and output settings. The input pin for the integrated PMOS option is shared with the base current drive pin for the

PNP option. The external PNP device is always connected to the BP line in the application. The recommended PNP device is

the ON Semiconductor NSS12100XV6T1G which is capable of handling up to 250 mW of continuous dissipation at minimum

footprint and 75 °C of ambient. For use cases where up to 500 mW of dissipation is required, the recommended PNP device is

the ON Semiconductor NSS12100UW3TCG. For stability, a small minimum ESR may be required.

A short-circuit condition will shut down the VGEN1 and VGEN2 regulators, and generate an interrupt for SCPI.

The nominal output voltage of both VGEN1 and VGEN2 are SPI configurable with the VGENx[2:0] bits as shown in Table 61 and

Table 62.

Table 61. VGEN1 Control Register Bit Assignments

Parameter

Value

Output Voltage

ILoad max

000

001

010

011

100

101

110

111

1.2000

1.2500

1.3000

1.3500

1.4000

1.4500

1.5000

1.5500

250 mA

VGEN1[2:0]

Table 62. VGEN2 Control Register Bit Assignments

ILoad max

Output

Voltage

Parameter Value

VGEN2CONFIG=0 VGEN2CONFIG=1

Internal Pass FET

External PNP

000

001

010

011

100

101

110

111

2.50

2.70

2.80

2.90

3.00

3.10

3.15

3.30

50 mA

250 mA

VGEN2[2:0]

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Functional Block Description

Table 63. VGEN1 Electrical Specification

Characteristics noted under conditions BP = 3.6 V, -40 C  T  85 C, unless otherwise noted. Typical values at BP = 3.6 V

A

and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

GENERAL

Operating Input Voltage Range V_INMINto V_INMAX

• All settings

V_GEN1IN

V

1.75

0.0

1.8

-

1.85

250

Operating Current Load Range IL_MINto IL_MAX

• Not exceeding PNP max power

I_GEN1

mA

VGEN1 ACTIVE MODE – DC

Output Voltage V_OUT

V_GEN1

V

• V_INMIN< V_IN< V_INMAXIL_MIN< IL < IL_MAX

V_NOM– 3%

V_NOM

0.25

5.0

V_NOM+ 3%

Load Regulation

V_GEN1LOPP

mV/mA

mV

• 1.0 mA < IL < IL_MAXFor any V_INMIN< V_IN< V_INMAX

-

Line Regulation

V_GEN1LIPP

• V_INMIN< V_IN< V_INMAXFor any IL_MIN< IL < IL_MAX

Over-current Protection threshold

VGEN1_OCP

mA

IL_MAX

+20%

• V_INMIN< V_IN< V_INMAXShort-circuit V_OUTto GND

-

Active Mode Quiescent Current

• V_INMIN< V_IN< V_INMAXIL = 0

I_GEN1Q

µA

-

12

-

Current Limit

I_GEN1LIM

mA

• V_INMIN< V_IN< V_INMAX

375

VGEN1 ACTIVE MODE - AC

PSRR

• IL = 75% of IL_MAX20 Hz to 20 kHz VGEN1[2:0] = 000-101

VGEN1_PSRR

50

37

60

-

dB

• IL = 75% of ILMAX 20 Hz to 20 kHz VGEN1[2:0] = 110-111

Output Noise Density, V_IN= V_INMINIL = 75% of IL_MAX

• 100 Hz – 1.0 kHz

-

-115

-126

-132

VGEN

1_NOISE

V/Hz

• > 1.0 kHz – 10 kHz

• > 10 kHz – 1.0 MHz

Spurs

VGEN

1_SPURS

dB

ms

%

• 32.768 kHz and harmonics

-

-100

1.0

10

Turn-on Time

t_ON-VGEN1

• Enable to 90% of end value V_IN= V_INMIN, V_INMAX, IL = 0

-

Turn-off Time

t_OFF-VGEN1

• Disable to 10% of initial value V_IN= V_INMIN, V_INMAX, IL = 0

0.01

-

Start-up Overshoot

VGEN1_OS-

• V_IN= V_INMIN, V_INMAX, IL = 0

-

1.0

5.0

2.0

8.0

START

Transient Load Response

• V_IN= V_INMIN, V_INMAX

VGEN1_LO

%

TRANSIENT

Transient Line Response

• IL = 75% of IL_MAX

V_GEN1LI

mV

TRANSIENT

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Functional Block Description

Table 63. VGEN1 Electrical Specification

Characteristics noted under conditions BP = 3.6 V, -40 C  T  85 C, unless otherwise noted. Typical values at BP = 3.6 V

A

and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

VGEN1 ACTIVE MODE - AC (CONTINUED)

Mode Transition Time

t_MODE-VGEN1

• From low-power to active and from active to low-power

V_IN= V_INMIN, V_INMAXIL = IL_MAXLP

µs

%

-

100

2.0

Mode Transition Response

VGEN

1_MODERES

• From low-power to active and from active to low-power

1.0

V_IN= V_INMIN, V_INMAXIL = IL_MAXLP

Table 64. VGEN2 Electrical Specification

Characteristics noted under conditions BP = 3.6 V, -40 C  T  85 C, unless otherwise noted. Typical values at BP = 3.6 V

A

and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

VGEN2

Characteristic

Min

Typ

Max

Unit Notes

Operating Input Voltage Range V_INMINto V_INMAX

• All settings, BP biased

V_GEN2IN

V

V_NOM

+0.25

-

4.5

Operating Current Load Range IL_MIto IL_MAX

• Internal Pass FET

I_GEN2

mA

0.0

-

50

Operating Current Load Range IL_MINto IL_MAX

• External PNP, Not exceeding PNP max power

I_GEN2

250

Extended Input Voltage Range

V_GEN2IN

mV/mA

• BP Biased, Performance may out of specification for output levels

VGEN2 [2:0] = 010 to 111

UVDET

-

4.5

VGEN2 ACTIVE MODE - DC

Output Voltage V_OUT

V_GEN2

V

• V_INMIN< V_IN< V_INMAXIL_MIN< IL < IL_MAX

V_NOM- 3%

V_NOM

0.20

8.0

V_NOM+ 3%

Load Regulation

V_GEN2LOPP

mV/mA

mV

• 1.0 mA < IL < IL_MAX, For any V_INMIN< V_IN< V_INMAX

-

Line Regulation

V_GEN2LIPP

• V_INMIN< V_IN< V_INMAXFor any IL_MIN< IL < IL_MAX

Over-current Protection threshold

VGEN2_OCP

mA

µA

ILmax

+20%

• V_INMIN< V_IN< V_INMAXShort-circuit V_OUTto GND

-

Active Mode Quiescent Current

• V_INMIN< V_IN< V_INMAXIL = 0

I_GEN2Q

-

30

Current Limit

• External PNP mode only

• V_INMIN< V_IN< V_INMAX

I_GEN2LIM

3.4*

-

mA

• Current on VGEN2DRV multiplied by  of external PNP transistor

(I_GEN2DRVwhen VGEN2DRV is forced to LDOVDD)

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Functional Block Description

Table 64. VGEN2 Electrical Specification

Characteristics noted under conditions BP = 3.6 V, -40 C  T  85 C, unless otherwise noted. Typical values at BP = 3.6 V

A

and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

VGEN2 LOW-POWER MODE - DC - VGEN2MODE=1

Output Voltage V_OUT

V_GEN2

V

• V_INMIN< V_IN< V_INMAXIL_MINLP< IL < IL_MAXLP

V_NOM- 3%

0.0

V_NOM

-

V_NOM+ 3%

3.0

Current Load Range IL_MINLPto IL_MAXLP

I_GEN2

mA

µA

Low-power Mode Quiescent Current

• V_INMIN< V_IN< V_INMAXIL = 0

I_GEN2Q

-

8.0

-

VGEN2 ACTIVE MODE - AC

PSRR - IL = 75% of ILmax, 20 Hz to 20 kHz

• V_IN= V_INMIN+ 100 mV

• V_IN= V_NOM+ 1.0 V

VGEN2_PSRR

35

55

40

60

-

dB

Output Noise Density - V_IN= V_INMINIL = 75% of IL_MAX

• 100 Hz – 1.0 kHz

-

-115

-126

-132

VGEN

2_NOISE

V/Hz

• > 1.0 kHz – 10 kHz

• > 10 kHz – 1.0 MHz

Turn-on Time

t_ON-VGEN22

ms

• Enable to 90% of end value V_IN= V_INMIN, V_INMAX, IL = 0

-

1.0

VGEN2 ACTIVE MODE - AC (CONTINUED)

Turn-off Time

t_OFF-VGEN2

ms

%

• Disable to 10% of initial value V_IN= V_INMIN, V_INMAX, IL = 0

0.05

-

10

2.0

8.0

100

Start-up Overshoot

VGEN2_OS-

• V_IN= V_INMIN, V_INMAXIL = 0

-

1.0

5.0

-

START

Transient Load Response

• V_IN= V_INMIN, V_INMAX

VGEN2_LO

%

TRANSIENT

Transient Line Response

• IL = 75% of IL_MAX

V_GEN2LI

mV

µs

TRANSIENT

Mode Transition Time

t_MODE-VGEN2

• From low-power to active V_IN= V_INMIN, V_INMAX, IL = IL_MAXLP

Mode Transition Response

VGEN

2_MODERES

• From low-power to active and from active to low-power

%

-

1.0

2.0

V_IN= V_INMIN, V_INMAX, IL = IL_MAXLP

34709

Analog Integrated Circuit Device Data

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Functional Block Description

7.6

Analog to Digital Converter

The ADC core is a 10 bit converter. The ADC core and logic run at an internally generated frequency of approximately 1.33 MHz.

The ADC is supplied from VCORE. The ADC core has an integrated auto calibration circuit which reduces the offset and gain

errors.

7.6.1

Input Selector

The ADC has 16 input channels. Table 65 gives an overview of the characteristics of each of these channels.

Table 65. ADC Inputs

Channel ADSELx[3:0]

Signal read

Input Level

Scaling

Scaled Version

Reserved

0

1

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Reserved

-40 – 150 °C

Reserved

0 – 3.6 V

0 – 2.4 V

Reserved

2

Reserved

Die temperature

Reserved

3

1.2 – 2.4 V

4

Reserved

X2/3

Reserved

5

Reserved

6

Reserved

7

Reserved

Coin cell Voltage

ADIN9

8

0 – 2.4 V

9

x1

0 – 2.4 V

ADIN10

10

11

12

13

14

15

x1

0 – 2.4 V

ADIN11

x1

0 – 2.4 V

ADIN12/TSX1

ADIN13/TSX2

ADIN14/TSY1

ADIN15/TSY2

x1/x2

0 – 2.4 V / 0 -1.2 V

x1/x2

Some of the internal signals are first scaled to adapt the signal range to the input range of the ADC. For details on scaling, see

Dedicated Readings.

Table 66. ADC Input Specification

Parameter

Condition

Min Typ Max Units

No bypass capacitor at input

Bypass capacitor at input 10 nF

-

5.0

30

kOhm

Source Impedance

When considerately exceeding the maximum input of the ADC at the scaled or unscaled inputs, the reading result will return a

full scale. It has to be noted however, that this full scale does not necessarily yield a 1022 DEC reading due to the offsets and

calibration applied. The same applies for when going below the minimum input where the corresponding 0000 DEC reading may

not be returned.

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Functional Block Description

7.6.2

Control

The ADC parameters are programmed by the processor via the SPI. When a reading sequence is finished, an interrupt

ADCDONEI is generated. The interrupt can be masked with the ADCDONEM bit.

The ADC is enabled by setting ADEN bit high. The ADC can start a series of conversions through SPI programming by setting

the ADSTART bit. If the ADEN bit is low, the ADC will be disabled and in low-power mode. The ADC is automatically calibrated

every time PMIC is powered.

The conversions will begin after a small analog synchronization of up to 30 microseconds, plus a programmable delay from 0

(default) up to 600 S, by programming the bits ADDLY1[3:0]. The ADDLY2[3:0] controls the delay between each of the

conversions from 0 to 600 S. ADDLY3[3:0] controls the delay after the final conversion, and is only valid when ADCONT is high.

ADDLY1, 2, and 3 are set to 0 by default.

Table 67. ADDLYx[3:0]

ADDLYx[3:0]

Delay in s

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0.0

40

80

120

160

200

240

280

320

360

400

440

480

520

560

600

There is a max of 8 conversions that will take place when the ADC is started. The register ADSELx[3:0] selects the channel which

the ADC will read and store in the ADRESULTx register. The ADC will always start at the channel indicated in ADSEL0, and read

up to and including the channel set by the ADSTOP[2:0] bits. For example, when ADSTOP[2:0] = 010, it will request the ADC to

read channels indicated in ADSEL0, ADSEL1, and ADSEL2. When ADSTOP[2:0] = 111, all eight channels programmed by the

value in ADSEL0-7 will be read. When the ADCONT bit is set high, it allows the ADC to continuously loop and read the channels

from address 0 to the stop address programmed in ADSTOP. By default, the ADCONT is set low (disabled). In the continuous

mode, the ADHOLD bit will allow the software to hold the ADC sequencer from updating the results register while the ADC results

are read. Once the sequence of A/D conversions is complete, the ADRESULTx results are stored in 4 SPI registers (ADC 4 -

ADC 7).

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Functional Block Description

7.6.3

Dedicated Readings

Channel 0 to 2 Reserve

7.6.3.1

Channel 0 to Channel 2 are reserved.

7.6.3.2

Channel 3 Die Temperature

The relation between the read out code and temperature is given in Table 68.

Table 68. Die Temperature Voltage Reading

Parameter

Die temperature read out code at 25 °C

Slope temperature change per LSB

Slope error

Min

Typ

Max

Unit

-

680

+0.426

-

Decimal

°C/LSB

%

5.0

The Actual Die Temperature is obtained as follows: Die Temp = 25 + 0.426 * (ADC Code - 680)

7.6.3.3

Channel 4 to 7 Reserved

Channel 4 to Channel 7 are reserved.

7.6.3.4

Channel 8 Coin Cell Voltage

The voltage of the coin cell connected to the LICELL pin can be read on channel 8. Since the voltage range of the coin cell

exceeds the input voltage range of the ADC, the LICELL voltage is scaled as V(LICELL)*2/3. In case the voltage at LICELL drops

below the coin cell disconnect threshold, the voltage at LICELL can still be read through the ADC.

Table 69. Coin Cell Voltage Reading Coding

Conversion Code

Voltage at ADC input (V) Voltage at LICELL (V)

ADRESULTx[9:0]

1 111 111 110

1 000 000 000

0 000 000 000

2.400

1.200

0.000

3.6

1.8

0

7.6.3.5

Channel 9-11 ADIN9-ADIN11

There are 3 general purpose analog input channels that can be measured through the ADIN9-ADIN11 pins.

7.6.3.6

Channel 12-15 ADIN12-ADIN15

If the touch screen is not used, the inputs TSX1, TSX2, TSY1, and TSY2 can be used as general purpose inputs. They are

respectively mapped on ADC channels 12, 13, 14, and 15.

7.6.4

Touch Screen Interface

The touch screen interface provides all circuitry required for the readout of a four-wire resistive touch screen. The touch screen

X plate is connected to TSX1 and TSX2, while the Y plate is connected to TSY1 and TSY2. A local supply TSREF will serve as

a reference. Several readout possibilities are offered.

If the touchscreen is not used, the inputs TSX1, TSX2, TSY1, and TSY2 can be used as general purpose inputs. They are

respectively mapped on ADC channels 12, 13, 14, and 15.

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

78

Functional Block Description

Touch Screen Pen detection bias can be enabled via the TSPENDETEN bit in the AD0 register. When this bit is enabled and a

pen touch is detected, the TSPENDET bit in the Interrupt Status 0 register is set and the INT pin is asserted - unless the interrupt

is masked. Pen detection is only active when TSEN is low.

The reference for the touch screen (Touch Bias) is TSREF and is powered from VCORE. During touch screen operation, TSREF

is a dedicated regulator. No loads other than the touch screen should be connected here. When the ADC performs non touch

screen conversions, the ADC does not rely on TSREF and the reference is disabled.

The readouts are designed such that the on chip switch resistances are of no influence on the overall readout. The readout

scheme does not account for contact resistances, as present in the touch screen connectors. The touch screen readings will

have to be calibrated by the user or the factory, where one has to point with a stylus to the opposite corners of the screen. When

reading the X-coordinate, the 10-bit ADC reading represents a 10-bit coordinate, with ‘0’ for a coordinate equal to X-, and full

scale ‘1023’ when equal to X+. When reading the Y-coordinate, the 10-bit ADC reading represents a 10-bit coordinate, with ‘0’

for a coordinate equal to Y-, and full scale ‘1023’ when equal to Y+. When reading contact resistance, the 10-bit ADC reading

represents the voltage drop over the contact resistance created by the known current source, multiplied by 2.

The X-coordinate is determined by applying TSREF over the TSX1 and TSX2 pins, while performing a high-impedance reading

on the Y-plate through TSY1. The Y-coordinate is determined by applying TSREF between TSY1 and TSY2, while reading the

TSX1 pin. The contact resistance is measured by applying a known current into the TSY1 pin of the touch screen and through

the TSX2 pin, which is grounded. The voltage difference between the two remaining terminals TSY2 and TSX1 is measured by

the ADC, and equals the voltage across the contact resistance. Measuring the contact resistance helps determine if the touch

screen is touched with a finger or a stylus.

The TSSELx[1:0] allows the application processor to select its own reading sequence. The TSSELx[1:0] determines what is read

during the touch screen reading sequence, as shown in Table 70. The touch screen will always start at TSSEL0 and read up to

and including the channel set by TSSEL at the TSSTOP[2:0] bits. For example when TSSTOP[2:0] = 010, it will request the ADC

to read channels indicated in TSSEL0, TSSEL1, and TSSEL2. When TSSTOP[2:0] = 111, all eight addresses will be read.

Table 70. Touch Screen Action Select

TSSELx[1:0]

Signals Sampled

00

01

10

11

Dummy to discharge TSREF cap

X - plate

Y - plate

Contact

The touch screen readings can be repeated, as in the following example readout sequence, to reduce the interrupt rate and to

allow for easier noise rejection. The dummy conversion inserted between the different readings allows the references in the

system to be pre-biased for the change in touch screen plate polarity. It will read out as ‘0’.

A touch screen reading will take precedence over an ADC sequence. If an ADC reading is triggered during a touch screen event,

the ADC sequence will be overwritten by the touch screen data.

The first touch screen conversion can be delayed from 0 (default) to 600 s by programming the TSDLY1[3:0] bits. The

TSDLY2[3:0] controls the delay between each of the touch screen conversions from 0 to 600 s. TSDLY[2:0] sets the delay after

the last address is converted. TSDLY1, 2, and 3 are set to 0 by default.

Table 71. TSDLYx[3:0]

TSDLYx[3:0]

Delay in uS

0000

0001

0010

0011

0100

0101

0110

0

40

80

120

160

200

240

34709

Analog Integrated Circuit Device Data

79

Freescale Semiconductor

Functional Block Description

Table 71. TSDLYx[3:0]

TSDLYx[3:0]

Delay in uS

0111

1000

1001

1010

1011

1100

1101

1110

1111

280

320

360

400

440

480

520

560

600

To perform a touch screen reading, the processor must do the following:

1. Enable the touch screen with TSEN

2. Select the touch screen sequence by programming the TSSEL0-TSSEL7 SPI bits.

3. Program the TSSTOP[2:0]

4. Program the delay between the conversion via the TSDLY1 and TSDLY2 settings.

5. Trigger the ADC via the TSSTART SPI bit

6. Wait for an interrupt indicating the conversion is done TSDONEI

7. And then read out the data in the ADRESULTx registers

7.6.5

ADC Specifications

Table 72. ADC Electrical Specifications

Characteristics noted under conditions BP = 3.6 V, -40 C  T  85 C, unless otherwise noted. Typical values at BP = 3.6 V

A

and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

ADC

Characteristic

Min

Typ

Max

Unit Notes

Conversion Current

-

1.0

-

mA

V

Converter Core Input Range

• Single-ended voltage readings

• Differential readings

V_ADCIN

0.0

-

2.4

1.2

-1.2

Conversion Time per channel

Integral Non-linearity

t_CONVERT

-

10

3

s

LSB

s

Differential Non-linearity

Zero Scale Error (Offset)

Full Scale Error (Gain)

Drift Over-temperature

Turn On/Off Time

1

5

10

1

t_ON-OFF-ADC

31

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

80

Functional Block Description

7.7

Auxiliary Circuits

7.7.1

General Purpose I/Os

The 34709 contains four configurable GPIO input/outputs for general purpose use. When configured as outputs, they can be

configured as open-drain (OD) or CMOS (push-pull outputs). These GPIOs are low-voltage capable (1.2 or 1.8 V). In open-drain

configuration these outputs can only be pulled up to 2.5 V maximum.

Each individual GPIO has a dedicated 16-bit control register. Table 73 provides detailed bit descriptions.

Table 73. GPIOLVx Control ⁽⁵⁵⁾

SPI Bit

Description

GPIOLVx direction

0: Input (default)

1: Output

DIR

Input state of the GPIOLVx pin

0: Input low

DIN

DOUT

HYS

1: Input High

Output state of GPIOLVx pin

0: Output Low

1: Output High

Hysteresis

0: CMOS in

1: Hysteresis (default)

GPIOLVx input debounce time

00: no debounce (default)

01: 10 ms debounce

DBNC[1:0]

INT[1:0]

10: 20 ms debounce

11: 30 mS debounce

GPIOLVx interrupt control

00: None (default)

01: Falling edge

10: Rising edge

11: Both edges

Pad keep enable

0: Off (default)

1: On

PKE

ODE

DSE

PUE

Open-drain enable

0: CMOS (default)

1: OD

Drive strength enable

0: 4.0 mA (default)

1: 8.0 mA

Pull-up/down enable

0: pull-up/down off

1: pull-up/down on (default)

Pull-up/Pull-down enable

00: 10 K active pull-down

01: 10 K active pull-up

PUS[1:0]

10: 100 K active pull-down

11: 100 K active pull-up (default)

34709

Analog Integrated Circuit Device Data

81

Freescale Semiconductor

Functional Block Description

Table 73. GPIOLVx Control ⁽⁵⁵⁾

SPI Bit

Description

Slew rate enable

00: slow (default)

01: normal

SRE[1:0]

10: fast

11: very fast

Notes

55. x= 0, 1, 2, or 3 depending of the GPIO channel it is being

used

7.7.2

PWM Outputs

There are two PWM outputs on the 34709 PWM1 and PWM2 and which are controlled by the PWMxDUTY and PWMxCLKDIV

registers shown in Table 74.The base clock will be the 2.0 MHz divided by 32.

Table 74. PWMx Duty Cycle Programming

PWMxDC[5:0](⁽⁵⁶⁾

)

Duty Cycle

000000

000001

…

0/32, Off (default)

1/32

…

010000

…

16/32

…

31/32

011111

1xxxxx

32/32, Continuously On

Notes

56. “x” represent 1 and 2

32.768 kHz Crystal Oscillator RTC Block Description and Application Information

Table 75. PWMx Clock Divider Programming

PWMxCLKDIV[5:0](⁽⁵⁷⁾

)

Duty Cycle

000000

000001

…

Base Clock

Base Clock / 2

…

001111

…

Base Clock / 16

…

111111

Notes

Base Clock / 64

57. “x” represent 1 and 2

7.8

Serial Interfaces

The IC contains a number of programmable registers for control and communication. The majority of registers are accessed

2

through a SPI interface in a typical application. The same register set may alternatively be accessed with an I C interface that is

2

muxed on SPI pins. Table 76 describes the muxed pin options for the SPI and I C interfaces; further details for each interface

mode follow.

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

82

Functional Block Description

Table 76. SPI / I²C Bus Configuration

Pin Name

SPI Mode Functionality

I²C Mode Functionality

Configuration ⁽⁵⁹⁾

CS

Configuration ⁽⁵⁸⁾, Chip Select

SPI Clock

CLK

SCL: I²C bus clock

MISO

MOSI

Notes

Master In, Slave Out (data output)

Master Out, Slave In (data input)

SDA: Bi-directional serial data line

A0 Address selection ⁽⁶⁰⁾

58. CS held low at Cold Start, configures the interface for SPI mode; once activated, CS functions as the SPI Chip Select.

59. CS tied to VCOREDIG at Cold Start, configures the interface for I²C mode; the pin is not used in I²C mode, other than for configuration.

60. In I²C mode, the MOSI pin is hardwired to ground, or VCOREDIG is used to select between two possible addresses.

7.8.1

SPI Interface

The IC contains a SPI interface port which allows access by a processor to the register set. Via these registers the resources of

the IC can be controlled. The registers also provide status information about how the IC is operating, as well as information on

external signals.

2

Because the SPI interface pins can be reconfigured for reuse as an I C interface, a configuration protocol mandates that the CS

pin is held low during a turn on event for the IC (a weak pull-down is integrated on the CS pin). The state of CS is latched in during

2

the initialization phase of a Cold Start sequence, ensuring that the I C bus is configured before the interface is activated. With

the CS pin held low during start-up (as would be the case if connected to the CS driver of an unpowered processor due to the

integrated pull-down), then the bus configuration will be latched for SPI mode.

The SPI port utilizes 32-bit serial data words comprised of 1 write/read_b bit, 6 address bits, 1 null bit, and 24 data bits. The

addressable register map spans 64 registers of 24 data bits each. The map is not fully populated, but it follows the legacy

conventions for bit positions corresponding to common functionality with previous generation FSL products.

7.8.1.1

SPI Interface Description

For a SPI read, the first bit sent to the IC must be a zero indicating a SPI read cycle. Next, the six bit address is sent MSB first.

This is followed by one dead bit to allow for more address decode time. The 34709 will clock the above bits in on the rising edge

of the SPI clock. Then the 24 data bits are driven out on the MISO pin on the falling edge of the SPI clock so the master can clock

them in on the rising edge of the SPI clock.

For each MOSI SPI transfer, first a one is written to the write/read_b bit if this SPI transfer is to be a write. A zero is written to the

write/read_b bit if this is to be a read command. If a zero is written, then any data sent after the address bits are ignored and the

internal contents of the field addressed do not change when the 32nd CLK is sent.

For a SPI write the first bit sent to the 34709 must be a one indicating a SPI write cycle. Next the six bit address is sent MSB first.

This is followed by one dead bit to allow for more address decode time. Then the data is sent MSB first. The SPI data is written

to the SPI register whose address was sent at the start of the SPI cycle on the falling edge of the 32nd SPI clock. Additionally,

whenever a SPI write cycle is taking place the SPI read data is shifted out for the same address as for the write cycle. Next the

6-bit address is written, MSB first. Finally, data bits are written, MSB first. Once all the data bits are written then the data is

transferred into the actual registers on the falling edge of the 32nd CLK.

The CS polarity is active high. The CS line must remain high during the entire SPI transfer. For a write sequence it is possible for

the written data to be corrupted, if after the falling edge of the 32nd clock the CS goes low before it's required time. CS can go

low before this point and the SPI transaction will be ignored, but after that point the write process is started and cannot be stopped

because the write strobe pulse is already being generated and CS going low may cause a runt pulse that may or may not be wide

enough to clock all 24 data bits properly. To start a new SPI transfer, the CS line must be toggled low and then pulled high again.

The MISO line will be tri-stated while CS is low.

The register map includes bits that are read/write, read only, read/write “1” to clear (i.e., Interrupts), and clear on read, reserved,

and unused. Refer to the SPI/I2C Register Map and the individual subcircuit descriptions to determine the read/write capability

of each bit. All unused SPI bits in each register must be written to as zeroes. A SPI read back of the address field and unused

bits are returned as zeroes. To read a field of data, the MISO pin will output the data field pointed to by the 6 address bits loaded

at the beginning of the SPI sequence.

34709

Analog Integrated Circuit Device Data

83

Freescale Semiconductor

Functional Block Description

CS

CLK

MOSI

Write_En

Address5

Addr ess 4

Address3

Address2

Address 1

Address 0

“Dead Bit”

Data 23

Data 22

Data 1

Data 0

MISO

Figure 19. SPI Transfer Protocol Single Read/Write Access

CS

Preamble

First Address

Preamble Another Address

24 Bits Data

MOSI

MISO

24 Bits Data

Figure 20. SPI Transfer Protocol Multiple Read/Write Access

7.8.1.2

SPI Timing Requirements

Figure 21 and Table 77 summarize the SPI timing requirements. The SPI input and output levels are set via the SPIVCC pin, by

connecting it to the desired supply. This would typically be tied to SW5 and programmed for 1.80 V. The strength of the MISO

driver is programmable through the SPIDRV [1:0] bits. See Thermal Protection Thresholds for detailed SPI electrical

characteristics.

t_CLKPER

t_CLKHIGH

CS

t_SELHLD

t_SELLOW

t_SELSU

t_CLKLOW

CLK

t_WRTSU

t_WRTLHD

MOSI

MISO

t_RDDIS

t_RDEN

t_RDSU

t_RDHLD

Figure 21. SPI Interface Timing Diagram

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

84

Functional Block Description

Table 77. SPI Interface Timing Specifications⁽⁶¹⁾

Parameter

Description

t _MIN(ns)

Time CS has to be high before the first rising edge of CLK

Time CS has to remain high after the last falling edge of CLK

Time CS has to remain low between two transfers

t_SELSU

t_SELHLD

t_SELLOW

t_CLKPER

t_CLKHIGH

t_CLKLOW

t_WRTSU

t_WRTHLD

t_RDSU

15

Clock period of CLK

38

Part of the clock period where CLK has to remain high

Part of the clock period where CLK has to remain low

Time MOSI has to be stable before the next rising edge of CLK

Time MOSI has to remain stable after the rising edge of CLK

Time MISO will be stable before the next rising edge of CLK

Time MISO will remain stable after the falling edge of CLK

Time MISO needs to become active after the rising edge of CS

Time MISO needs to become inactive after the falling edge of CS

15

4.0

t_RDHLD

t_RDEN

t_RDDIS

Notes

61. This table reflects a maximum SPI clock frequency of 26 MHz.

7.8.2

I²C Interface

2

7.8.2.1

I C Configuration

2

When configured for I C mode, the interface may be used to access the complete register map previously described for SPI

access. Since SPI configuration is more typical, references within this document will generally refer to the common register set

2

as a “SPI map” and bits as “SPI bits”; however, it should be understood that access reverts to I C mode when configured as such.

2

The SPI pins CLK and MISO are reused for the SCL and SDA lines respectively. Selection of I C mode for the interface is

configured by hard-wiring the CS pin to VCOREDIG on the application board. The state of CS is latched in during the initialization

2

phase of a Cold Start sequence, so the I CS bit is defined for bus configuration before the interface is activated. The pull-down

2

on CS will be deactivated if the high state is detected (indicating I C mode).

2

In I C mode, the MISO pin is connected to the bus as an open-drain driver, and the logic level is set by an external pull-up. The

2

part can function only as an I C slave device, not as a host.

2

7.8.2.2

I C Device ID

2

I C interface protocol requires a device ID for addressing the target IC on a multi-device bus. To allow flexibility in addressing for

bus conflict avoidance, pin programmable selection is provided to allow configuration for the address LSB(s). This product

supports 7-bit addressing only; support is not provided for 10-bit or general Call addressing.

2

Because the MOSI pin is not utilized for I C communication, it is reassigned for pin programmable address selection by

2

hardwiring to VCOREDIG or GND at the board level when configured for I C mode. MOSI will act as Bit 0 of the address. The

2

I C address assigned to FSL PM ICs (shared amongst our portfolio) is given as follows:

00010-A1-A0, the A1 and A0 bits are allowed to be configured for either 1 or 0. The A1 address bit is internally hardwired as a

“0”, leaving the LSB A0 for board level configuration. The designated address then is defined as: 000100-A0.

34709

Analog Integrated Circuit Device Data

85

Freescale Semiconductor

Functional Block Description

2

7.8.2.3

I C Operation

2

The I C mode of the interface is implemented generally following the Fast Mode definition which supports up to 400 kbits/s

operation. (Exceptions to the standard are noted to be 7-bit only addressing, and no support for general Call addressing) Timing

diagrams, electrical specifications, and further details on this bus standard, is available on the internet, by typing 

2

“I C specification” in the web search string field.

2

Standard I C protocol utilizes bytes of eight bits, with an acknowledge bit (ACK) required between each byte. However, the

number of bytes per transfer is unrestricted. The register map is organized in 24-bit registers which corresponds to the 24-bit

2

words supported by the SPI protocol of this product. To ensure that I C operation mimics SPI transactions in behavior of a

complete 24-bit word being written in one transaction, software is expected to perform write transactions to the device in 3-byte

sequences, beginning with the MSB. Internally, data latching will be gated by the acknowledge at the completion of writing the

third consecutive byte.

2

Failure to complete a 3-byte write sequence will abort the I C transaction and the register will retain its previous value. This could

be due to a premature STOP command from the master, for example.

2

I C read operations are also performed in byte increments separated by an ACK. Read operations also begin with the MSB and

3-bytes will be sent out unless a STOP command or NACK is received prior to completion.

The following examples show how to write and read data to the IC. The host initiates and terminates all communication. The host

sends a master command packet after driving the start condition. The device will respond to the host if the master command

packet contains the corresponding slave address. In the following examples, the device is shown always responding with an ACK

to transmissions from the host. If at any time a NAK is received, the host should terminate the current transaction and retry the

transaction.

Packet

Type

Device

Address

Register Address

7

0

7

0

Host SDA

(to MISO)

Continuation

START

0

R / W

A

C

K

A

C

K

Slave SDA

(from MISO)

Host can

also drive

another

Start instead

of Stop

Packet

Type

Master Driven Data

( byte 2 )

Master Driven Data

( byte 1)

Master Driven Data

( byte 0 )

23

16

15

8

7

0

Host SDA

(to MISO)

STOP

A

C

K

A

C

K

A

C

K

Slave SDA

(from MISO)

Figure 22. I²C 3-byte Write Example

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

86

Functional Block Description

Packet

Type

Device

Address

Register Address

Device Address

23

16

0

15

0

8

7

0

Host SDA

(to MISO)

Continuation

START

0

START

1

R /W

A

C

K

A

C

K

A

C

K

Slave SDA

(from MISO)

Host can also

drive another

Start instead of

Stop

Device Data

( byte 2)

Device Data

AP Lite Driven Data

( byte 1 )

Device Data

APLite Driven Data

( byte 0)

AP Lite Driven Data

Packet

Type

A

C

K

A

C

K

Host SDA

(to MISO)

NA

CK

STOP

23

16

15

8

7

0

Slave SDA

(from MISO)

Figure 23. I²C 3-byte Read Example

7.8.3

SPI/I²C Specification

Table 78. SPI/I²C Electrical Characteristics

Characteristics noted under conditions BP = 3.6 V, -40 C  T  85 C, unless otherwise noted. Typical values at BP = 3.6 V

A

and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

SPI Interface Logic IO

Input Low CS

V_INCSLO

V_INCSHI

V_INMOSILO

0.0

1.1

-

0.4

V

Input High CS

SPIVCC+0.3

/

Input Low, MOSI, CLK

0.0

-

0.3*SPIVCC

SPIVCC+0.3

V

V_INCLKLO

V_INMOSIHI

/

Input High, MOSI, CLK

0.7*SPIVCC

V_INCLKHI

Output Low MISO, INT

V_MISOLO

V_INTLO

/

V

• Output sink 100 A

0.0

SPIVCC-0.2

1.75

-

0.2

SPIVCC

3.6

Output High MISO, INT

V_MISOHI

/

V

V_INTHI

• Output source 100 A

SPIVCC Operating Range

V_CC-SPI

MISO Rise and Fall Time, CL = 50 pF, SPIVCC = 1.8 V

• SPIDRV [1:0] = 00

-

6.0

2.5

3.0

2.0

-

• SPIDRV [1:0] = 01 (default)

• SPIDRV [1:0] = 10

t_MISOET

ns

• SPIDRV [1:0] = 11

34709

Analog Integrated Circuit Device Data

87

Freescale Semiconductor

Functional Block Description

7.9

Configuration Registers

Register Set structure

7.9.1

The general structure of the register set is given in Table 79. Expanded bit descriptions are included in the following functional

sections for application guidance. For brevity’s sake, references are occasionally made herein to the register set as the “SPI map”

2

or “SPI bits”, but note that bit access is also possible through the I C interface option so such references are implied as

generically applicable to the register set accessible by either interface.

Table 79. Register Set

Register

0

1

Interrupt Status 0

Interrupt Mask 0

Interrupt Sense 0

Interrupt Status 1

Interrupt Mask 1

Interrupt Sense 1

Power Up Mode Sense

Identification

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Memory A

Memory B

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

Regulator Mode 0

GPIOLV0 Control

GPIOLV1 Control

GPIOLV2 Control

GPIOLV3 Control

Reserved

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

ADC5

ADC6

2

Memory C

ADC7

3

Memory D

Reserved

Supply Debounce

Reserved

PWM Control

Unused

4

RTC Time

5

RTC Alarm

6

RTC Day

Reserved

7

RTC Day Alarm

Regulator 1 A/B Voltage

Regulator 2 & 3 Voltage

Regulator 4 A/B Voltage

Regulator 5 Voltage

Regulator 1 & 2 Mode

Regulator 3, 4 and 5 Mode

Regulator Setting 0

SWBST Control

Reserved

8

Regulator Fault Sense

Reserved

9

Unused

10

11

12

13

14

15

Reserved

Unused

Reserved

ADC 0

Unused

ADC 1

Unused

Power Control 0

Power Control 1

Power Control 2

ADC 2

Unused

ADC 3

Unused

ADC4

Unused

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

88

Functional Block Description

7.9.2

Specific Registers

7.9.2.1

IC and Version Identification

The IC and other version details can be read via the identification bits. These are hardwired on the chip and described in Table 80.

Table 80. IC Revision Bit Assignment

Identifier

Value

Purpose

Represents the full mask revision

FULL_LAYER_REV[2:0]

XXX

Pass 1.0 = 001

Represents the full Metal revision

Pass 1.0 = 000

METAL_LAYER_REV[2:0]

FIN[2:0]

XXX

000

Options within same Reticle

Pass 1.0 = 000

Wafer manufacturing facility

Pass 1.0 = 000

FAB[2:0]

7.9.2.2

Embedded Memory

There are four register banks of general purpose embedded memory to store critical data. The data written to MEMA[23:0],

MEMB[23:0], MEMC[23:0], and MEMD[23:0] is maintained by the coin cell when the main battery is deeply discharged, removed,

or contact-bounced (i.e., during a power cut). The contents of the embedded memory are reset by RTCPORB. A known pattern

can be maintained in these registers to validate confidence in the RTC contents when power is restored after a power cut event.

Alternatively, the banks can be used for any system need for bit retention with coin cell backup.

34709

Analog Integrated Circuit Device Data

89

Freescale Semiconductor

Functional Block Description

7.9.3

SPI/I²C Register Map

The complete SPI bitmap is given in Table 81.

Table 81. SPI/I²C Register Map

Register Types

Read / Write

Register Values

Reset

R/W

0 = low

Bits Loaded at Cold Start based on PUMS Value

Bits Reset by POR or Global Reset

R/WM

W1C

RO

Read / Write Modify

Write One to Clear

Read Only

1 = High

X = Variable

RESETB / Green Reset Bits Reset by POR or Global or Green Reset

Bits Reset by RTCPORB or Global Reset

Bits Reset by POR or OFFB

NU

Not Used

Bits Reset by RTCPORB Only

Register

Name

Address

Type

Default

34709 SPI Register Map Rev 0.1

23

-

22

-

21

20

19

18

17

16

-

Interrupt

Status 0

15

-

14

-

13

12

11

10

9

8

0x00

W1C h00_00_00

LOWBATT

-

Table 82

7

6

5

4

3

2

1

0

-

TSPENDET

TSDONEI

ADCDONEI

23

-

22

-

21

20

19

18

17

16

-

Interrupt

Mask 0

15

-

14

-

13

12

11

10

9

8

0x01

0x02

0x03

0x04

R/W h00_20_07

LOWBATTM

-

Table 83

7

6

5

4

3

2

1

0

-

TSPENDETM

TSDONEM

ADCDONEM

23

-

22

-

21

20

19

18

17

16

-

Interrupt

Sense 0

15

-

14

-

13

12

11

10

9

8

NU

h00_00_00

-

0

Table 84

7

6

5

4

3

2

1

-

23

22

21

20

GPIOLV3I

12

19

GPIOLV2I

11

18

17

16

-

BATTDETBI

-

GPIOLV1I

GPIOLV0I

SCPI

8

Interrupt

Status 1

15

14

13

10

9

WARMI

1

W1C h40_80_80

CLKI

THERM130

THERM125

THERM120

4

THERM110

3

MEMHLDI

PCI

0

Table 85

7

6

SYSRSTI

22

5

2

RTCRSTI

WDIRESTI

PWRON2I

20

PWRON1I

19

-

TODAI

17

1HZI

16

23

21

-

18

-

15

BATTDETBIM

14

GPIOLV3M

12

GPIOLV2M

11

GPIOLV1M

GPIOLV0M

9

SCPM

8

Interrupt

Mask 1

13

10

R/W h5F_FF_FB

CLKM

7

THERM130M

6

THERM125M THERM120M THERM110M

MEMHLDM

WARMM

1

PCM

0

Table 86

5

4

3

2

RTCRSTM

SYSRSTM

WDIRESTM

PWRON2M

PWRON1M

-

TODAM

1HZM

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

90

Functional Block Description

23

22

21

20

19

18

17

16

-

GPIOLV3S

GPIOLV2S

GPIOLV1S

GPIOLV0S

-

Interrupt

Sense 1

15

14

13

12

11

10

9

8

0x05

0x06

0x07

0x08

RO hXX_XX_XX

CLKS

THERM130S

THERM125S

THERM120S

THERM110S

-

Table 87

7

-

6

-

5

4

3

2

1

0

-

PWRON2S

PWRON1S

-

23

-

22

-

21

20

19

18

17

16

-

Power Up

Mode Sense

15

-

14

-

13

12

11

10

9

8

RO

h00_00_XX

-

Table 88

7

6

5

4

PUMS4S

20

3

PUMS3S

19

2

1

0

-

PUMS5S

PUMS2S

PUMS1S

ICTESTS

23

22

21

18

17

-

16

PAGE[4:0]

-

15

-

14

-

13

-

12

-

11

3

10

FAB[2:0]

2

9

8

FIN[2]

0

Identification

Table 89

RO h00_0X_XX

7

6

5

4

1

FIN[1:0]

FULL_LAYER_REV[2:0]

METAL_LAYER_REV[2:0]

23

22

21

20

-

19

-

18

-

17

-

16

REGSCPEN

-

Regulator

Fault Sense

15

14

13

12

11

10

9

8

R0

h00_XX_XX

-

VGEN2FAULT VGEN1FAULT

VDACFAULT

VUSB2FAULT

VUSBFAULT

Table 90

7

6

5

4

3

2

1

0

SWBSTFAULT

SW5FAULT

SW4BFAULT

SW4AFAULT

SW3FAULT

SW2FAULT

RSVD

SW1FAULT

23

22

-

21

20

-

19

18

17

16

-

15

14

-

13

12

-

11

10

9

8

0x09

To

0x0C

Unused

NU

h00_00_00

-

7

6

5

4

3

2

1

0

-

23

22

21

20

19

18

17

16

COINCHEN

VCOIN[2:0]

-

Power

Control 0

15

-

14

-

13

-

12

-

11

10

9

8

0x0D

0x0E

0x0F

R/W h00_00_40

R/W h00_00_00

R/W h42_23_00

-

PCUTEXPB

-

Table 93

7

6

5

4

3

2

1

0

-

CLK32KMCUEN USEROFFCLK

DRM

20

-

USEROFFSPI

WARMEN

PCCOUNTEN

PCEN

23

-

22

21

-

19

-

18

-

17

-

16

-

Power

Control 1

15

14

13

12

11

10

9

8

PCMAXCNT[3:0]

PCCOUNT[3:0]

Table 94

7

6

5

4

3

2

1

0

PCT[7:0]

23

22

21

20

19

-

18

17

16

-

STBYDLY[1:0]

ON_STBY_LP

-

CLKDRV[1:0]

Power

Control 2

15

-

14

13

12

WDIRESET

4

11

-

10

9

8

SPIDRV[1:0]

STANDBYINV

2

GLBRSTTMR[1:0]

Table 95

7

6

5

3

1

0

PWRON2DBNC[1:0]

PWRON1BDBNC[1:0]

-

PWRON2RSTEN PWRON1RSTEN RESTARTEN

34709

Analog Integrated Circuit Device Data

91

Freescale Semiconductor

Functional Block Description

23

15

7

22

14

6

21

13

5

20

12

4

19

MEMA[23:16]

18

10

2

17

9

16

8

11

Memory A

Table 96

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

R/W h00_00_00

R/W h0X_XX_XX

R/W h01_FF_FF

R/W h00_XX_XX

R/W h00_7F_FF

MEMA[15:8]

MEMA[7:0]

3

1

0

23

15

7

22

14

6

21

13

5

20

12

4

19

18

10

2

17

9

16

8

MEMB[23:16]

11

Memory B

Table 97

MEMB[15:8]

3

1

0

MEMB[7:0]

23

15

7

22

14

6

21

13

5

20

12

4

19

18

10

2

17

9

16

8

MEMC[23:16]

11

Memory C

Table 98

MEMC[15:8]

3

1

0

MEMC[7:0]

23

15

7

22

14

6

21

13

5

20

12

4

19

18

10

2

17

9

16

8

MEMD[23:16]

11

Memory D

Table 99

MEMD[15:8]

3

1

0

MEMD[7:0]

23

22

21

13

5

20

12

4

19

18

10

2

17

9

16

TOD[16]

8

RTCCALMODE[1:0]

RTCCAL[4:0]

15

7

14

11

RTC Time

Table 100

TOD[15:8]

6

3

1

0

TOD[7:0]

23

RTCDIS

15

22

SPARE

14

21

SPARE

13

20

SPARE

12

19

18

SPARE

10

17

SPARE

9

16

TODA[16]

8

SPARE

11

RTC Alarm

Table 101

TODA[15:8]

7

6

5

4

3

2

1

0

TODA[7:0]

23

-

22

-

21

-

20

-

19

18

-

17

-

16

-

15

-

14

13

12

11

10

9

8

RTC Day

Table 102

DAY[14:8]

7

6

5

4

3

2

1

0

DAY[7:0]

23

-

22

-

21

-

20

-

19

-

18

-

17

-

16

-

RTC Day

Alarm

15

-

14

13

12

11

10

9

8

DAYA[14:8]

Table 103

7

6

5

4

3

2

1

0

DAYA[7:0]

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

92

Functional Block Description

23

15

7

22

14

6

21

13

5

20

12

4

19

11

3

18

10

2

17

9

16

8

RSVD[5:0]

RSVD[5:4]

Regulator

1A/B Voltage

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

R/WM hXX_XX_XX

R/WM h00_XX_XX

R/WM h52_80_48

R/WM h52_08_48

R/WM h00_XX_XX

R/WM h00_00_0X

RSVD[3:0]

SW1ASTBY[5:2]

Table 104

1

0

SW1ASTBY[1:0]

SW1A[5:0]

23

-

22

14

6

21

13

5

20

19

11

3

18

10

2

17

-

16

SW3[4]

8

SW3STBY[4:0]

Regulator

2&3 Voltage

15

12

9

SW3[3:0]

SW2STBY[5:2]

Table 105

7

4

20

12

4

1

17

9

0

SW2STBY[1:0]

SW2[5:0]

23

15

7

22

14

6

21

13

5

19

18

10

16

SW4BHI[1:0]

SW4BSTBY[4:0]

SW4B[4]

Regulator 4

Voltage

11

8

SW4B[3:0]

SW4AHI[1:0]

SW4ASTBY[4:3]

Table 106

3

2

1

0

SW4ASTBY[2:0]

SW4A[4:0]

23

22

-

21

-

20

19

-

18

-

17

-

16

-

15

-

Regulator 5

Voltage

14

13

12

11

10

9

-

8

-

SW5TBY[4:0]

Table 107

7

6

-

5

-

4

3

2

1

0

-

SW5[4:0]

18

23

PLLX

15

22

21

20

19

17

16

PLLEN

14

SW2DVSSPEED[1:0]

SW2UOMODE SW2MHMODE

SW2MODE[3:2]

Regulator

1, 2 Mode

13

-

12

-

11

-

10

-

9

-

8

-

SW2MODE[1:0]

Table 108

7

6

5

4

3

2

1

0

SW1DVSSPEED[1:0]

23 22

SW5UOMODE SW5MHMODE

SW1AUOMODESW1AMHMODE

SW1AMODE[3:0]

17

21

20

12

4

19

18

16

SW5MODE[3:0]

11

SW4BUOMODE SW4BMHMODE

Regulator

3, 4, 5 Mode

15

14

13

10

9

8

0

SW4BMODE[3:0]

SW4AUOMODE SW4AMHMODE

SW4AMODE[3:2]

Table 109

7

6

5

3

2

1

SW4AMODE[1:0]

SW3UOMODE SW3MHMODE

SW3MODE[3:0]

23

-

22

-

21

-

20

-

19

-

18

-

17

-

16

-

Regulator

Setting 0

15

-

14

-

13

-

12

11

10

9

8

VGEN2[2]

0

VUSB2[1:0]

VPLL[1:0]

Table 110

7

6

5

4

3

-

2

1

VGEN2[1:0]

VDAC[1:0]

VGEN1[2:0]

23

-

22

-

21

-

20

-

19

-

18

-

17

-

16

-

SWBST

Control

15

-

14

-

13

-

12

-

11

-

10

-

9

-

8

-

Table 111

7

6

5

4

3

2

1

0

SPARE

SWBSTSTBYMODE[1:0]

SPARE

SWBSTMODE[1:0]

SWBST[1:0]

34709

Analog Integrated Circuit Device Data

93

Freescale Semiconductor

Functional Block Description

23

22

-

21

-

20

VUSB2MODE VUSB2STBY

12 11

19

18

VUSB2EN

10

17

16

-

VUSB2CONFIG

VPLLSTBY

Regulator

Mode 0

15

14

13

9

8

0x20

0x21

0x22

0x23

0x24

R/WM h0X_XX_XX

R/W h00_38_0X

VPLLEN

VGEN2MODE VGEN2STBY

VGEN2EN VGEN2CONFIG VREFDDREN

-

Table 112

7

6

5

4

3

2

1

0

-

VDACMODE

VDACSTBY

VDACEN

VUSBEN

-

VGEN1STBY

VGEN1EN

23

22

21

20

19

18

17

16

-

SPARE

GPIOLV0

Control

15

14

13

12

11

10

9

8

SRE1

SRE0

PUS1

PUS0

PUE

DSE

ODE

PKE

Table 113

7

6

5

4

3

2

1

0

INT1

INT0

DBNC1

DBNC0

HYS

DOUT

DIN

DIR

23

22

21

20

19

18

17

16

-

SPARE

GPIOLV1

Control

15

14

13

12

11

10

9

8

SRE1

SRE0

PUS1

PUS0

PUE

DSE

ODE

PKE

Table 114

7

6

5

4

3

2

1

0

INT1

INT0

DBNC1

DBNC0

HYS

DOUT

DIN

DIR

23

22

21

20

19

18

17

16

-

SPARE

GPIOLV2

Control

15

14

13

12

11

10

9

8

SRE1

SRE0

PUS1

PUS0

PUE

DSE

ODE

PKE

Table 115

7

6

5

4

3

2

1

0

INT1

INT0

DBNC1

DBNC0

HYS

DOUT

DIN

DIR

23

22

21

20

19

18

17

16

-

SPARE

GPIOLV3

Control

15

14

13

12

11

10

9

8

PKE

0

SRE1

SRE0

PUS1

PUS0

PUE

DSE

ODE

Table 116

7

6

5

4

3

2

1

INT1

INT0

DBNC1

DBNC0

HYS

DOUT

DIN

DIR

16

-

23

22

21

20

19

18

-

17

-

15

14

13

12

11

10

-

9

8

0x25

to

0x2A

Unused

NU

h00_00_00

-

7

6

5

4

3

2

1

0

-

23

-

22

-

19

-

21

20

18

17

16

SPARE

15

SPARE

14

SPARE

TSPENDETEN

SPARE

11

TSSTOP[2:0]

13

TSSTART

5

12

TSEN

4

10

SPARE

2

9

SPARE

1

8

THERM

0

ADC 0

0x2B

R/W h00_00_00

Table 119

TSHOLD

7

TSCONT

6

SPARE

3

SPARE

23

ADSTOP[2:0]

21

ADHOLD

19

ADCONT

18

ADSTART

17

ADEN

16

22

20

12

4

TSDLY3[3:0]

TSDLY2[3:0]

15

7

14

13

11

3

10

9

1

8

0

ADC 1

0x2C

R/W h00_00_00

Table 120

TSDLY1[3:0]

ADDLY3[3:0]

6

5

2

ADDLY2[3:0]

ADDLY1[3:0]

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

94

Functional Block Description

23

15

7

22

ADSEL5[3:0]

14

ADSEL3[3:0]

21

13

5

20

12

4

19

11

3

18

10

2

17

9

16

8

ADSEL4[3:0]

ADSEL2[3:0]

ADSEL0[3:0]

ADC 2

0x2D

0x2E

0x2F

0x30

0x31

0x32

0x33

0x34

R/W h00_00_00

Table 121

6

1

0

ADSEL1[3:0]

23

15

7

22

14

6

21

13

5

20

12

4

19

11

3

18

10

2

17

9

16

8

TSSEL7[1:0]

TSSEL3[1:0]

TSSEL6[1:0]

TSSEL2[1:0]

TSSEL5[1:0]

TSSEL1[1:0]

TSSEL4[1:0]

TSSEL0[1:0]

ADC 3

R/W h00_00_00

Table 122

1

0

ADSEL7[3:0]

ADSEL6[3:0]

23

15

22

21

20

19

18

10

2

17

9

16

8

ADRESULT1[9:2]

14

13

-

12

11

3

ADC 4

Table 123

ADRESULT1[1:0]

-

ADRESULT0[9:6]

7

6

5

4

1

0

-

ADRESULT0[5:0]

-

23

15

7

22

14

21

20

19

18

10

2

17

16

ADRESULT3[9:2]

13

-

12

11

3

9

8

ADC 5

Table 124

ADRESULT3[1:0]

-

ADRESULT2[9:6]

6

5

4

1

0

-

ADRESULT2[5:0]

-

23

15

22

14

6

21

20

19

18

10

2

17

16

ADRESULT5[9:2]

13

-

12

11

3

9

8

ADC 6

Table 125

ADRESULT5[1:0]

-

ADRESULT4[9:6]

7

23

15

7

5

4

1

0

-

ADRESULT4[5:2]

-

22

14

21

20

19

18

10

2

17

16

ADRESULT7[9:2]

13

-

12

11

3

9

8

ADC 7

Table 126

ADRESULT7[9:2]

-

ADRESULT6[9:6]

6

5

4

1

0

-

ADRESULT6[5:0]

-

23

-

22

-

21

-

20

19

-

18

-

17

16

-

12

-

9

-

15

-

14

-

13

-

11

-

10

-

8

-

Unused

NU

h00_00_00

7

6

5

4

3

2

1

-

0

-

23

-

22

-

21

-

20

-

19

-

18

-

17

16

DIE_TEMP_DB[1:0]

Supply

Debounce

15

-

14

-

13

-

12

-

11

-

10

-

9

-

8

-

R/W h03_00_00

Table 128

7

6

5

4

3

2

1

-

0

-

VBATTDB[1:0]

34709

Analog Integrated Circuit Device Data

95

Freescale Semiconductor

Functional Block Description

23

-

22

-

21

-

20

-

19

-

18

-

17

-

16

-

15

-

14

-

13

-

12

-

11

-

10

-

9

8

0x35

to

0x36

Unused

NU

h00_00_00

-

7

6

5

4

3

2

1

0

-

23

22

21

20

19

18

17

16

PWM2CLKDIV[5:0]

PWM2DUTY[5:4]

15

7

14

13

12

4

11

3

10

9

8

0

PWM Control

Table 130

0x37

R/W h00_00_00

PWM2DUTY[3:0]

PWM1CLKDIV[5:2]

6

5

2

1

PWM1CLKDIV[1:0]

PWM1DUTY[5:0]

23

-

22

21

-

20

-

19

-

18

-

17

-

16

-

14

-

15

-

13

-

12

-

11

-

10

-

9

-

8

-

0x38

to

Unused

NU

h00_00_00

0x3F

7

6

5

4

3

2

1

-

0

-

7.9.4

SPI Register’s Bit Description

Table 82. Register 0, Interrupt Status 0

Name

Bit # R/W

Reset

Default

Description

ADCDONEI

TSDONEI

TSPENDET

Reserved

LOWBATT

Reserved

0

1

RW1C

RESETB

0

-

ADC has finished requested conversions

Touchscreen has finished requested conversions

Touch screen pen detection

For Future Use

RW1C

RESETB

2

RW1C

RESETB

3

R

-

4

-

For Future Use

5

-

For Future Use

6

-

For Future Use

7

-

For Future Use

8

-

For Future Use

9

-

For Future Use

10

11

12

-

For Future Use

-

For Future Use

-

For Future Use

13 RW1C

RESETB

0

-

Low battery threshold warning

For Future Use

14

15

16

17

18

19

R

-

For Future Use

-

For Future Use

-

For Future Use

-

For Future Use

-

For Future Use

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

96

Functional Block Description

Table 82. Register 0, Interrupt Status 0

Name

Bit # R/W

Reset

Default

Description

Reserved

20

21

22

23

R

-

For Future Use

Back to SPI/I2C Register Map

Table 83. Register 1, Interrupt Mask 0

Name

Bit # R/W Reset Default

Description

ADCDONEM

TSDONEM

TSPENDETM

Reserved

LOWBATTM

Reserved

0

1

R/W RESETB

1

-

ADCDONEI mask bit

TSDONEI mask bit

Touch screen pen detect mask bit

For Future Use

2

3

R

-

4

-

For Future Use

5

-

For Future Use

6

-

For Future Use

7

-

For Future Use

8

-

For Future Use

9

-

For Future Use

10

11

12

-

For Future Use

-

For Future Use

-

For Future Use

13 R/W RESETB

1

-

LOBATLI mask bit

For Future Use

14

15

16

17

18

19

20

21

22

23

R

-

For Future Use

-

For Future Use

-

For Future Use

-

For Future Use

-

For Future Use

-

For Future Use

-

For Future Use

-

For Future Use

-

For Future Use

Back to SPI/I2C Register Map

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

97

Functional Block Description

Table 84. Register 2, Interrupt Sense 0

Name

Bit # R/W

Reset

Default

Description

Unused

0

1

R

-

0

-

Not available

For Future Use

Not available

For Future Use

Not available

For Future Use

Not available

Unused

2

Reserved

Unused

3

4

-

5

-

6

-

7

0

-

Reserved

Unused

8

9

-

10

11

12

13

14

15

16

17

18

19

20

21

22

23

0

-

Unused

Reserved

Unused

-

0

Unused

Back to SPI/I2C Register Map

Table 85. Register 3, Interrupt Status 1

Name

Bit # R/W

Reset

Default

Description

1HZI

TODAI

0

1

2

3

4

5

6

7

8

9

RW1C RTCPORB

R

0

1

0

1.0 Hz time tick

Time of day alarm

Unused

PWRON1I

PWRON2I

WDIRESETI

SYSRSTI

RTCRSTI

PCI

RW1C

OFFB

PWRON1 event

PWRON2 event

RW1C RTCPORB

WDI system reset event

PWRON system reset event

RTC reset event

RW1C

OFFB

Power cut event

WARMI

RW1C RTCPORB

Warm start event

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

98

Functional Block Description

Table 85. Register 3, Interrupt Status 1

Name

Bit # R/W

Reset

Default

Description

MEMHLDI

THERM110

THERM120

THERM125

THERM130

CLKI

10 RW1C RTCPORB

11 RW1C RESETB

12 RW1C RESETB

13 RW1C RESETB

14 RW1C RESETB

15 RW1C RESETB

16 RW1C RESETB

17 RW1C RESETB

18 RW1C RESETB

19 RW1C RESETB

20 RW1C RESETB

0

-

Memory hold event

110 °C thermal threshold

120 °C thermal threshold

125 °C thermal threshold

130 °C thermal threshold

Clock source change

Short-circuit protection trip detection

GPIOLV1 interrupt

SCPI

GPIOLV1I

GPIOLV2I

GPIOLV3I

GPIOLV4I

Unused

GPIOLV2 interrupt

GPIOLV3 interrupt

GPIOLV4 interrupt

21

22

23

R

-

Not available

Reserved

Unused

-

For future use

RESETB

0

Not available

Back to SPI/I2C Register Map

Table 86. Register 4, Interrupt Mask 1

Name

Bit # R/W

Reset

Default

Description

1HZM

TODAM

0

1

2

3

4

5

6

7

8

9

R/W RTCPORB

R

1

1HZI mask bit

TODAI mask bit

Unused

PWRON1M

PWRON2M

WDIRESETM

SYSRSTM

RTCRSTM

PCM

R/W

OFFB

PWRON1 mask bit

PWRON2 mask bit

R/W RTCPORB

WDIRESETI mask bit

SYSRSTI mask bit

RTCRSTI mask bit

R/W

OFFB

PCI mask bit

WARMM

R/W RTCPORB

WARMI mask bit

MEMHLDM

10 R/W RTCPORB

MEMHLDI mask bit

THERM110M 11 R/W

THERM120M 12 R/W

THERM125M 13 R/W

THERM130M 14 R/W

RESETB

THERM110 mask bit

THERM120 mask bit

THERM125 mask bit

THERM130 mask bit

CLKI mask bit

CLKM

15 R/W

16 R/W

17 R/W

18 R/W

19 R/W

SCPM

Short-circuit protection trip mask bit

GPIOLV1 interrupt mask bit

GPIOLV2 interrupt mask bit

GPIOLV3 interrupt mask bit

GPIOLV1M

GPIOLV2M

GPIOLV3M

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

99

Functional Block Description

Table 86. Register 4, Interrupt Mask 1

Name

Bit # R/W

Reset

Default

Description

GPIOLV4M

Unused

20 R/W

RESETB

1

0

-

GPIOLV4 interrupt mask bit

Not available

21

22

23

R

Reserved

Unused

-

For Future use

1

Not available

Back to SPI/I2C Register Map

Table 87. Register 5, Interrupt Sense 1

Name

Bit # R/W Reset Default

Description

Unused

0

1

R

0

S

0

S

0

-

Not available

Unused

2

Not available

PWRON1S

PWRON2S

Unused

3

NONE

PWRON1I sense bit

PWRON2I sense bit

Not available

4

5

Unused

6

Not available

Unused

7

Not available

Unused

8

Not available

Unused

9

Not available

Unused

10

11

12

13

14

15

16

17

18

19

20

21

22

23

Not available

THERM110S

THERM120S

THERM125S

THERM130S

CLKS

NONE

THERM110 sense bit

THERM120 sense bit

THERM125 sense bit

THERM130 sense bit

CLKI sense bit

Not available

Unused

Not available

Unused

Not available

Unused

Not available

Unused

Not available

Unused

Not available

Reserved

Unused

-

For Future Use

Not available

NONE

0

Back to SPI/I2C Register Map

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

100

Functional Block Description

Table 88. Register 6, Power-up Mode Sense

Name

Bit #

R/W

Reset

Default

Description

ICTESTS

PUMS1S

PUMS2S

PUMS3S

PUMS4S

PUMS5S

Unused

Reserved

Unused

0

1

R

NONE

S

L

0

-

ICTEST sense state

PUMS1 state

PUMS2 state

PUMS3 state

PUMS4 state

PUMS5 state

Not available

For future use

Not available

2

3

4

5

6

7

8

9

-

10

11

12

13

14

15

16

17

18

19

20

21

22

23

0

Back to SPI/I2C Register Map

Table 89. Register 7, Identification

Name

Bit # R/W

Reset

Default

Description

METAL_LAYER_REV0

METAL_LAYER_REV1

METAL_LAYER_REV2

FULL_LAYER_REV0

FULL_LAYER REV1

FULL_LAYER REV2

FIN0

0

1

2

3

4

5

6

7

8

R

NONE

X

Metal Layer version

Pass 1.0 = 000

Full Layer version

Pass 1.0 = 001

FIN version

FIN1

Pass 1.0 = 000

FIN2

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

101

Functional Block Description

Table 89. Register 7, Identification

Name

Bit # R/W

Reset

Default

Description

FAB0

FAB1

9

R

NONE

X

0

FAB version

10

11

12

13

14

15

16

17

18

19

20

21

22

23

Pass 1.0 = 000

FAB2

Unused

Not available

Unused

PAGE0

R/W DIGRESETB

PAGE1

PAGE2

SPI Page

PAGE3

PAGE4

Back to SPI/I2C Register Map

Table 90. Register 8, Regulator Fault Sense

Name

Bit #

R/W

Reset

Default

Description

SW1FAULT

Reserved

0

1

R

NONE

-

S

-

SW1 fault detection

For future use

SW2FAULT

SW3FAULT

SW4AFAULT

SW4BFAULT

SW5FAULT

SWBSTFAULT

VUSBFAULT

VUSB2FAULT

VDACFAULT

VGEN1FAULT

VGEN2FAULT

Unused

2

NONE

S

0

SW2 fault detection

SW3 fault detection

SW4A fault detection

SW4B fault detection

SW5 fault detection

SWBST fault detection

VUSB fault detection

VUSB2 fault detection

VDAC fault detection

VGEN1 fault detection

VGEN2 fault detection

Not available

3

4

5

6

7

8

9

10

11

12

13-22

23

RESCGPEN

R/W RESETB

0

Regulator short-circuit protect enable

Back to SPI/I2C Register Map

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

102

Functional Block Description

Table 91. Register 9, Reserved

Name

Bit #

R/W

Reset

Default

Description

Reserved

23-0

R

-

For future use

Table 92. Register 10 to 12, Unused

Name

Bit # R/W

23-0

Reset

Default

Description

Reserved

R

-

For future use

Table 93. Register 13, Power Control 0

Name

Bit #

R/W

Reset

Default

Description

PCEN

PCCOUNTEN

WARMEN

0

1

2

3

4

5

6

7

8

R/W

R

RTCPORB

RESETB

0

1

0

Power cut enable

Power cut counter enable

Warm start enable

USEROFFSPI

DRM

SPI command for entering user off modes

Keeps VSRTC and CLK32KMCU on for all states

Keeps the CLK32KMCU active during user off

Enables the CLK32KMCU

RTCPORB ⁽⁶²⁾

RTCPORB

USEROFFCLK

CLK32KMCUEN

Unused

RTCPORB

Not available

Unused

R

Not available

PCUTEXPB=1 at a start-up event indicates that PCUT timer did not

expire (assuming it was set to 1 after booting)

PCUTEXPB

9

R/W

RTCPORB

0

Unused

Reserved

VCOIN0

VCOIN1

VCOIN2

COINCHEN

10

11

12

13

14

15

16

17

18

19

20

21

22

23

R

0

-

Not available

For Future Use

R

-

R/W

RTCPORB

0

Coin cell charger voltage setting

Coin cell charger enable

Notes:

62. Reset by RTCPORB but not during a GLBRST (global reset)

Back to SPI/I2C Register Map

34709

Analog Integrated Circuit Device Data

103

Freescale Semiconductor

Functional Block Description

Table 94. Register 14, Power Control 1

Name

Bit # R/W

Reset

Default

Description

PCT0

PCT1

0

1

R/W

R

RTCPORB

0

PCT2

2

PCT3

3

Power cut timer

PCT4

4

PCT5

5

PCT6

6

PCT7

7

PCCOUNT0

PCCOUNT1

PCCOUNT2

PCCOUNT3

PCMAXCNT0

PCMAXCNT1

PCMAXCNT2

PCMAXCNT3

Unused

8

9

Power cut counter

10

11

12

13

14

15

16

17

18

19

20

21

22

23

Maximum allowed number of power cuts

Not available

Unused

R

Unused

R

Unused

R

Unused

R

Unused

R

Unused

R

Unused

R

Back to SPI/I2C Register Map

Table 95. Register 15, Power Control 2

Name

Bit #

R/W

Reset

Default

Description

RESTARTEN

PWRON1RSTEN

PWRON2RSTEN

Unused

0

1

2

3

4

5

6

7

8

9

R/W

R

RTCPORB

0

1

Enables automatic restart after a system reset

Enables system reset on PWRON1 pin

Enables system reset on PWRON2 pin

Not available

PWRON1DBNC0

PWRON1DBNC1

PWRON2DBNC0

PWRON2DBNC1

GLBRSTTMR0

GLBRSTTMR1

R/W

RTCPORB

Sets debounce time on PWRON1 pin

Sets debounce time on PWRON2 pin

Sets Global reset time

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

104

Functional Block Description

Table 95. Register 15, Power Control 2

Name

Bit #

R/W

Reset

Default

Description

STANDBYINV

Unused

10

11

12

13

14

15

16

17

18

19

20

R/W

R

RTCPORB

0

1

0

1

0

If set then STANDBY is interpreted as active low

Not available

WDIRESET

SPIDRV0

SPIDRV1

Unused

R/W

R

RESETB

RTCPORB

Enables system reset through WDI

SPI drive strength

Not available

Unused

R

CLK32KDRV0

CLK32KDRV1

Unused

R/W

R

RTCPORB

CLK32K and CLK32KMCU drive strength (master control bits)

Not available

Unused

R

On Standby Low-power Mode

0 = Low-power mode disabled

1 =Low-power mode enabled

ON_STBY_LP

21

R/W

RESETB

0

STBYDLY0

STBYDLY1

22

23

R/W

RESETB

1

0

Standby delay control

Back to SPI/I2C Register Map

Table 96. Register 16, Memory A

Name

Bit # R/W

Reset

Default

Description

MEMA0

MEMA1

MEMA2

MEMA3

MEMA4

MEMA5

MEMA6

MEMA7

MEMA8

MEMA9

MEMA10

MEMA11

MEMA12

MEMA13

MEMA14

MEMA15

MEMA16

MEMA17

MEMA18

0

1

R/W

RTCPORB

0

2

3

4

5

6

7

8

9

Backup memory A

10

11

12

13

14

15

16

17

18

34709

Analog Integrated Circuit Device Data

105

Freescale Semiconductor

Functional Block Description

Table 96. Register 16, Memory A

Name

Bit # R/W

Reset

Default

Description

MEMA19

MEMA20

MEMA21

MEMA22

MEMA23

19

20

21

22

23

R/W

RTCPORB

0

Backup memory A

Back to SPI/I2C Register Map

Table 97. Register 17, Memory B

Name

Bit #

R/W

Reset

Default

Description

MEMB0

MEMB1

MEMB2

MEMB3

MEMB4

MEMB5

MEMB6

MEMB7

MEMB8

MEMB9

MEMB10

MEMB11

MEMB12

MEMB13

MEMB14

MEMB15

MEMB16

MEMB17

MEMB18

MEMB19

MEMB20

MEMB21

MEMB22

MEMB23

0

1

R/W

RTCPORB

0

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

Backup memory B

Back to SPI/I2C Register Map

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

106

Functional Block Description

Table 98. Register 18, Memory C

Name

Bit # R/W

Reset

Default

Description

MEMC0

MEMC1

MEMC2

MEMC3

MEMC4

MEMC5

MEMC6

MEMC7

MEMC8

MEMC9

MEMC10

MEMC11

MEMC12

MEMC13

MEMC14

MEMC15

MEMC16

MEMC17

MEMC18

MEMC19

MEMC20

MEMC21

MEMC22

MEMC23

0

1

R/W

RTCPORB

0

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

Backup memory C

Back to SPI/I2C Register Map

Table 99. Register 19, Memory D

Name

Bit #

R/W

Reset

Default

Description

MEMD0

MEMD1

MEMD2

MEMD3

MEMD4

MEMD5

MEMD6

MEMD7

MEMD8

MEMD9

0

1

2

3

4

5

6

7

8

9

R/W

RTCPORB

0

Backup memory D

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

107

Functional Block Description

Table 99. Register 19, Memory D

Name

Bit #

R/W

Reset

Default

Description

MEMD10

MEMD11

MEMD12

MEMD13

MEMD14

MEMD15

MEMD16

MEMD17

MEMD18

MEMD19

MEMD20

MEMD21

MEMD22

MEMD23

10

11

12

13

14

15

16

17

18

19

20

21

22

23

R/W

RTCPORB

0

Backup memory D

Back to SPI/I2C Register Map

Table 100. Register 20, RTC Time

Name

Bit # R/W

Reset

Default

Description

TOD0

TOD1

TOD2

TOD3

TOD4

TOD5

TOD6

TOD7

TOD8

TOD9

TOD10

TOD11

TOD12

TOD13

TOD14

TOD15

TOD16

0

1

R/W

RTCPORB ⁽⁶³⁾

0

2

3

4

5

6

7

8

Time of day counter

9

10

11

12

13

14

15

16

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

108

Functional Block Description

Table 100. Register 20, RTC Time

Name

Bit # R/W

Reset

Default

Description

RTCCAL0

RTCCAL1

17

18

19

20

21

22

23

R/W

RTCPORB ⁽⁶³⁾

0

RTCCAL2

RTC calibration count

RTCCAL3

RTCCAL4

RTCCALMODE0

RTCCALMODE1

RTC calibration mode

Notes

63. Reset by RTCPORB but not during a GLBRST (global reset)

Back to SPI/I2C Register Map

Table 101. Register 21, RTC Alarm

Name

Bit #

R/W

Reset

Default

Description

TODA0

TODA1

TODA2

TODA3

TODA4

TODA5

TODA6

TODA7

TODA8

TODA9

TODA10

TODA11

TODA12

TODA13

TODA14

TODA15

TODA16

Unused

RTCDIS

0

1

R/W

R

RTCPORB ⁽⁶⁴⁾

1

0

2

3

4

5

6

7

8

Time of day alarm

9

10

11

12

13

14

15

16

17- 22

23

Not available

Disable RTC

R/W

RTCPORB ⁽⁶⁴⁾

Notes

64. Reset by RTCPORB but not during a GLBRST (global reset)

Back to SPI/I2C Register Map

34709

Analog Integrated Circuit Device Data

109

Freescale Semiconductor

Functional Block Description

Table 102. Register 22, RTC Day

Name

Bit #

R/W

Reset

Default

Description

DAY0

DAY1

DAY2

DAY3

DAY4

DAY5

DAY6

DAY7

DAY8

DAY9

DAY10

DAY11

DAY12

DAY13

DAY14

Unused

0

R/W

R

RTCPORB ⁽⁶⁵⁾

0

1

2

3

4

5

6

7

Day counter

8

9

10

11

12

13

14

15 - 23

Not available

Notes

65. Reset by RTCPORB but not during a GLBRST (global reset)

Back to SPI/I2C Register Map

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

110

Functional Block Description

Table 103. Register 23, RTC Day Alarm

Name

Bit #

R/W

Reset

Default

Description

DAYA0

DAYA1

DAYA2

DAYA3

DAYA4

DAYA5

DAYA6

DAYA7

DAYA8

DAYA9

DAYA10

DAYA11

DAYA12

DAYA13

DAYA14

Unused

0

R/W

R

RTCPORB ⁽⁶⁶⁾

1

0

1

2

3

4

5

6

7

Day alarm

8

9

10

11

12

13

14

15 - 23

Not available

Notes

66. Reset by RTCPORB but not during a GLBRST (global reset)

Back to SPI/I2C Register Map

Table 104. Register 24, Regulator 1A/B Voltage

Name

Bit #

R/W

Reset

Default

Description

SW1A0

SW1A1

0

R/WM NONE

*

-

1

SW1A2

2

SW1 setting in normal mode

SW1A3

3

SW1A4

4

SW1A5

5

SW1ASTBY0

SW1ASTBY1

SW1ASTBY2

SW1ASTBY3

SW1ASTBY4

SW1ASTBY5

Reserved

6

7

8

SW1 setting in Standby mode

9

10

11

12 - 23

R

-

For future use

Back to SPI/I2C Register Map

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

111

Functional Block Description

Table 105. Register 25, Regulator 2 & 3 Voltage

Name

Bit #

R/W

Reset

Default

Description

SW20

SW21

0

1

R/WM

R

NONE

*

0

*

0

SW22

2

SW2 setting in normal mode

SW23

3

SW24

4

SW25

5

SW2STBY0

SW2STBY1

SW2STBY2

SW2STBY3

SW2STBY4

SW2STBY5

SW30

6

7

8

SW2 setting in Standby mode

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

SW31

SW32

SW3 setting in normal mode

Not available

SW33

SW34

Unused

SW3STBY0

SW3STBY1

SW3STBY2

SW3STBY3

SW3STBY4

Unused

R/WM

R

NONE

SW3 setting in standby mode

Not available

Back to SPI/I2C Register Map

Table 106. Register 26, REgulator 4A/B

Name

Bit #

R/W

Reset

Default

Description

SW4A0

SW4A1

0

1

2

3

4

5

6

7

8

9

R/WM

NONE

*

SW4A2

SW4A setting in normal mode

SW4A3

SW4A4

SW4ASTBY0

SW4ASTBY1

SW4ASTBY2

SW4ASTBY3

SW4ASTBY4

SW4A setting in Standby mode

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

112

Functional Block Description

Table 106. Register 26, REgulator 4A/B

Name

Bit #

R/W

Reset

Default

Description

SW4AHI0

SW4AHI1

SW4B0

10

11

12

13

14

15

16

17

18

19

20

21

22

23

R/WM

NONE

*

SW4A high setting

SW4B1

SW4B2

SW4B setting in normal mode

SW4B3

SW4B4

R/WM RESETB

SW4BSTBY0

SW4BSTBY1

SW4BSTBY2

SW4BSTBY3

SW4BSTBY4

SW4BHI0

SW4BHI1

SW4B setting in Standby mode

SW4B high setting

Back to SPI/I2C Register Map

Table 107. Register 27, REgulator 5 Voltage

Name

Bit #

R/W

Reset

Default

Description

SW50

SW51

0

1

R/WM NONE

R

*

0

SW52

2

SW4 setting in normal mode

Not available

SW53

3

SW54

4

Unused

5 - 9

10

SW5STBY0

SW5STBY1

SW5STBY2

SW5STBY3

SW5STBY4

Unused

R/WM NONE

R

11

12

SW5 setting in Standby mode

Not available

13

14

15 - 23

Back to SPI/I2C Register Map

Table 108. Register 28, Regulators 1 & 2 Operating Mode

Name

Bit #

R/W

Reset

Default

Description

SW1AMODE0

SW1AMODE1

SW1AMODE2

SW1AMODE3

0

1

2

3

R/W

RESETB

0

1

SW1A operating mode

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

113

Functional Block Description

Table 108. Register 28, Regulators 1 & 2 Operating Mode

Name

Bit #

R/W

Reset

Default

Description

SW1AMHMODE

SW1AUOMODE

SW1DVSSPEED0

SW1DVSSPEED1

Unused

4

5

R/W

R

OFFB

0

1

0

1

0

1

0

1

0

SW1A Memory Hold mode

SW1A User Off mode

6

RESETB

SW1 DVS1 speed

7

8 - 13

14

15

16

17

18

19

20

21

22

23

Not available

SW2MODE0⁽⁶⁷⁾

SW2MODE1⁽⁶⁷⁾

SW2MODE2⁽⁶⁷⁾

SW2MODE3⁽⁶⁷⁾

SW2MHMODE

SW2UOMODE

SW2DVSSPEED0

SW2DVSSPEED1

PLLEN

R/W

RESETB

OFFB

SW2 operating mode

SW2 Memory Hold mode

SW2 User Off mode

OFFB

RESETB

SW2 DVS1 speed

PLL enable

PLLX

PLL multiplication factor

Notes

67. SWxMODE[3:0] bits will be reset to their default values by the start-up sequencer, based on PUMS settings. An enabled switch will

default to APS mode for both Normal and Standby operation.

Back to SPI/I2C Register Map

Table 109. Register 29, Regulators 3, 4, and 5 Operating Mode

Name

Bit #

R/W

Reset

Default

Description

SW3MODE0

SW3MODE1

0

1

R/W

RESETB

OFFB

0

1

0

1

0

1

0

SW3 operating mode

SW3MODE2

2

SW3MODE3

3

SW3MHMODE

SW3UOMODE

SW4AMODE0

SW4AMODE1

SW4AMODE2

SW4AMODE3

SW4AMHMODE

SW4AUOMODE

SW4BMODE0

SW4BMODE1

SW4BMODE2

SW4BMODE3

SW4BMHMODE

4

SW3 Memory Hold mode

SW3 User Off mode

5

OFFB

6

RESETB

OFFB

7

SW4A operating mode

8

9

10

11

12

13

14

15

16

SW4A Memory Hold mode

SW4A User Off mode

OFFB

RESETB

OFFB

SW4B operating mode

SW4B Memory Hold mode

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

114

Functional Block Description

Table 109. Register 29, Regulators 3, 4, and 5 Operating Mode

SW4BUOMODE

SW5MODE0⁽⁶⁸⁾

SW5MODE1⁽⁶⁸⁾

SW5MODE2⁽⁶⁸⁾

SW5MODE3⁽⁶⁸⁾

SW5MHMODE

SW5UOMODE

17

18

19

20

21

22

23

R/W

OFFB

RESETB

OFFB

0

1

0

SW4B User Off mode

SW5 operating mode

SW5 Memory Hold mode

SW5 User Off mode

OFFB

Notes

68. SWxMODE[3:0] bits will be reset to their default values by the start-up sequencer, based on PUMS settings. An enabled regulator will

default to APS mode for both Normal and Standby operation.

Back to SPI/I2C Register Map

Table 110. Register 30, Regulator Setting 0

Name

Bit #

R/W

Reset

Default

Description

VGEN10

VGEN11

VGEN12

Unused

VDAC0

VDAC1

VGEN20

VGEN21

VGEN22

VPLL0

0

R/WM

R

RESETB

*

0

*

0

1

VGEN1 setting

2

3

Not available

VDAC setting

4

R/WM

R

RESETB

5

6

7

VGEN2 setting

VPLL setting

8

9

VPLL1

10

11

12

13 -23

VUSB20

VUSB21

Unused

VUSB2 setting

Not available

Back to SPI/I2C Register Map

Table 111. Register 31, SWBST Control

Name

Bit #

R/W

Reset

Default

Description

SWBST0

SWBST1

0

1

2

3

4

5

6

R/W

NONE

*

SWBST setting

*

SWBSTMODE0

SWBSTMODE1

Spare

RESETB

0

1

0

1

SWBST mode

Not available

SWBSTSTBYMODE0

SWBSTSTBYMODE1

SWBST standby mode

34709

Analog Integrated Circuit Device Data

115

Freescale Semiconductor

Functional Block Description

Table 111. Register 31, SWBST Control

Name

Bit #

R/W

Reset

Default

Description

Spare

Unused

7

R/W

R

RESETB

0

Not available

8 - 23

Back to SPI/I2C Register Map

Table 112. Register 32, Regulator Mode 0

Name

Bit #

R/W

Reset

Default

Description

VGEN1EN

VGEN1STBY

Unused

0

1

R/W

R

NONE

*

0

1

*

VGEN1 enable

VGEN1 controlled by standby

Not available

RESETB

2

VUSBEN

3

R/W

R

RESETB

NONE

VUSB enable (PUMS4:1=[0100]).

VDAC enable

VDACEN

4

VDACSTBY

VDACMODE

Unused

5

RESETB

0

*

VDAC controlled by standby

VDAC operating mode

Not available

6

7

Unused

8

R

Not available

Unused

9

R

Not available

VREFDDREN

10

R/W

NONE

VREFDDR enable

PUMS5 Tied to ground = 0: VGEN2 with external PNP

PUMS5 Tied to VCROREDIG =1:VGEN2 internal PMOS

VGEN2CONFIG

11

R/W

*

VGEN2EN

VGEN2STBY

VGEN2MODE

VPLLEN

12

13

14

15

16

R/W

NONE

RESETB

NONE

*

0

*

VGEN2 enable

VGEN2 controlled by standby

VGEN2 operating mode

VPLL enable

VPLLSTBY

RESETB

0

VPLL controlled by standby

PUMS5 Tied to ground = 0: VUSB2 with external PNP

PUMS5 Tied to VCROREDIG =1:VUSB2 internal PMOS

VUSB2CONFIG

17

R/W

NONE

*

VUSB2EN

VUSB2STBY

VUSB2MODE

Unused

18

19

20

21

22

23

R/W

R

NONE

*

VUSB2 enable

VUSB2 controlled by standby

VUSB2 operating mode

Not available

RESETB

0

Unused

R

Not available

Unused

R

Not available

Back to SPI/I2C Register Map

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

116

Functional Block Description

Table 113. Register 33, GPIOLV0 Control

Name

Bit #

R/W

Reset

Default

Description

GPIOLV0 direction

0: Input

DIR

0

R/W RESETB

0

1: Output

Input state of GPIOLV0 pin

0: Input low

DIN

1

2

0

1: Input High

Output state of GPIOLV0 pin

0: Output Low

DOUT

1: Output High

Hysteresis

0: CMOS in

1: Hysteresis

HYS

3

4

R/W RESETB

1

0

DBNC0

GPIOLV0 input debounce time

00: no debounce

01: 10 ms debounce

10: 20 ms debounce

11: 30 mS debounce

DBNC1

5

R/W RESETB

0

INT0

INT1

6

7

R/W RESETB

0

GPIOLV0 interrupt control

00: None

01: Falling edge

10: Rising edge

11: Both edges

Pad keep enable

0: Off

PKE

ODE

DSE

PUE

8

9

R/W RESETB

0

1

1: On

Open-drain enable

0: CMOS

1: OD

Drive strength enable

0: 4.0 mA

10

11

1: 8.0 mA

Pull-up/down enable

0: pull-up/down off

1: pull-up/down on (default)

Pull-up/Pull-down select

00: 10 K pull-down

01: 100 K pull-down

10: 10 K pull-up

PUS0

PUS1

12

13

R/W RESETB

1

11: 100 K pull-up

(1.0 default 10)

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

117

Functional Block Description

Table 113. Register 33, GPIOLV0 Control

Name

Bit #

R/W

Reset

Default

Description

SRE0

14

R/W RESETB

R

0

Slew rate enable

00: slow (default)

01: normal

SRE1

15

0

10: fast

11: very fast

Unused 16 - 23

Not available

Back to SPI/I2C Register Map

Table 114. Register 34, GPIOLV1 Control

Name

Bit #

R/W

Reset

Default

Description

GPIOLV1directon

0: Input

DIR

0

R/W

RESETB

0

1: Output

Input state of GPIOLV1 pin

0: Input low

DIN

1

2

R/W

RESETB

0

1: Input High

Output state of GPIOLV1 pin

0: Output Low

DOUT

1: Output High

Hysteresis

0: CMOS in

1: Hysteresis

HYS

3

4

R/W

RESETB

1

0

DBNC0

GPIOLV1 input debounce time

00: no debounce

01: 10 ms debounce

10: 20 ms debounce

11: 30 mS debounce

DBNC1

5

R/W

RESETB

0

INT0

INT1

6

7

R/W

RESETB

0

GPIOLV1 interrupt control

00: None

01: Falling edge

10: Rising edge

11: Both edges

Pad keep enable

0: Off

PKE

ODE

DSE

8

9

R/W

RESETB

0

1: On

Open-drain enable

0: CMOS

1: OD

Drive strength enable

0: 4.0 mA

10

1: 8.0 mA

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

118

Functional Block Description

Table 114. Register 34, GPIOLV1 Control

Name

Bit #

R/W

Reset

Default

Description

Pull-up/down enable

0: pull-up/down off

PUE

11

R/W

RESETB

1

1: pull-up/down on (default)

Pull-up/Pull-down select

00: 10 K pull-down

01: 100 K pull-down

10: 10 K pull-up

PUS0

12

R/W

RESETB

1

11: 100 K pull-up

PUS1

SRE0

13

14

R/W

RESETB

1

0

(1.0 default 10)

Slew rate enable

00: slow (default)

01: normal

SRE1

15

R/W

RESETB

0

10: fast

11: very fast

Unused 16 - 23

R

Not available

Back to SPI/I2C Register Map

Table 115. Register 35, GPIOLV2 Control

Name

Bit #

R/W

Reset

Default

Description

GPIOLV2 direction

0: Input

DIR

0

R/W

RESETB

0

1: Output

Input state of GPIOLV2 pin

0: Input low

DIN

1

2

R/W

RESETB

0

1: Input High

Output state of GPIOLV2 pin

0: Output Low

DOUT

1: Output High

Hysteresis

0: CMOS in

1: Hysteresis

HYS

3

4

R/W

RESETB

1

0

DBNC0

GPIOLV2 input debounce time

00: no debounce

01: 10 ms debounce

10: 20 ms debounce

11: 30 mS debounce

DBNC1

5

R/W

RESETB

0

INT0

INT1

6

7

R/W

RESETB

0

GPIOLV2 interrupt control

00: None

01: Falling edge

10: Rising edge

11: Both edges

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

119

Functional Block Description

Table 115. Register 35, GPIOLV2 Control

Name

Bit #

R/W

Reset

Default

Description

Pad keep enable

0: Off

PKE

8

R/W

RESETB

0

1: On

Open-drain enable

0: CMOS

ODE

DSE

PUE

9

R/W

RESETB

0

1

1: OD

Drive strength enable

0: 4.0 mA

10

11

1: 8.0 mA

Pull-up/down enable

0: pull-up/down off

1: pull-up/down on (default)

Pull-up/Pull-down select

00: 10 K pull-down

01: 100 K pull-down

10: 10 K pull-up

PUS0

12

R/W

RESETB

1

11: 100 K pull-up

PUS1

SRE0

13

14

R/W

RESETB

1

0

(1.0 default = 10)

Slew rate enable

00: slow (default)

01: normal

SRE1

15

R/W

R

RESETB

0

10: fast

11: very fast

Unused 16 - 23

Not available

Back to SPI/I2C Register Map

Table 116. Register 36, GPIOLV3 Control

Name

Bit #

R/W

Reset

Default

Description

GPIOLV3 direction

0: Input

DIR

0

R/W

RESETB

0

1: Output

Input state of GPIOLV3 pin

0: Input low

DIN

1

2

R/W

RESETB

0

1: Input High

Output state of GPIOLV3 pin

0: Output Low

DOUT

1: Output High

Hysteresis

0: CMOS in

1: Hysteresis

HYS

3

4

R/W

RESETB

1

0

DBNC0

GPIOLV3 input debounce time

34709

Analog Integrated Circuit Device Data

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120

Functional Block Description

Table 116. Register 36, GPIOLV3 Control

Name

Bit #

R/W

Reset

Default

Description

00: no debounce

01: 10 ms debounce

10: 20 ms debounce

11: 30 mS debounce

DBNC1

5

R/W

RESETB

0

INT0

INT1

6

7

R/W

RESETB

0

GPIOLV3 interrupt control

00: None

01: Falling edge

10: Rising edge

11: Both edges

Pad keep enable

0: Off

PKE

ODE

DSE

8

9

R/W

RESETB

0

1: On

Open-drain enable

0: CMOS

1: OD

Drive strength enable

0: 4.0 mA

10

1: 8.0 mA

Pull-up/down enable

0: pull-up/down off

PUE

11

12

R/W

RESETB

1

1: pull-up/down on (default)

PUS0

Pull-up/Pull-down select

00: 10 K pull-down

01: 100 K pull-down

10: 10 K pull-up

PUS1

13

R/W

RESETB

1

11: 100 K pull-up

(1.0 default = 10)

SRE0

SRE1

14

15

R/W

R

RESETB

0

Slew rate enable

00: slow (default)

01: normal

10: fast

11: very fast

Unused 16 - 23

Not available

Back to SPI/I2C Register Map

Table 117. Register 37 - 40, Reserved

Name

Bit # R/W

0 - 23

Reset

Default

Description

Unused

R

0

Not available

Table 118. Register 41 - 42, Unused

Name

Bit #

R/W

Reset

Default

Description

Unused

0-23

R

0

Not available

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

121

Functional Block Description

Table 119. Register 43, ADC 0

Name

Bit #

R/W

Reset

Default

Description

ADEN

0

1

R/W

DIGRESETB

0

Enables ADC from the low-power mode

ADSTART

Request a start of the ADC Reading Sequencer

Run ADC reads continuously when high or one time when low. Note that the

TSSTART request will have higher priority

ADCONT

2

R/W

DIGRESETB

0

ADHOLD

ADSTOP0

ADSTOP1

ADSTOP2

Spare

3

4

5

6

7

R/W

DIGRESETB

0

Hold the ADC reading Sequencer while saved ADC results are read from SPI

Channel Selection to stop when complete. Always start at 000 and read up to and

including this channel value.

Not available

0: NTCREF not forced on

1: Force NTCREF on

THERM

8

R/W

DIGRESETB

0

Spare

9

R/W

DIGRESETB

0

Not available

10

11

12

13

14

Spare

Not available

TSEN

Enable the touch screen from low-power mode.

Request a start of the ADC Reading Sequencer for touch screen readings.

Run ADC reads of touch screen continuously when high or one time when low.

TSSTART

TSCONT

Hold the ADC reading Sequencer while saved touch screen results are read from

SPI

TSHOLD

15

R/W

DIGRESETB

0

TSSTOP0

TSSTOP1

TSSTOP2

Spare

16

17

18

19

R/W

DIGRESETB

0

Just like the ADSTOP above, but for the touch screen read programming. This will

allow independent code for ADC Sequence readings and touch screen ADC

Sequence readings.

Not available

TSPENDET

EN

Enable the touch screen Pen Detection. Note that TSEN must be off for Pen

Detection.

20

R/W

DIGRESETB

0

Spare

21

22

23

R/W

DIGRESETB

0

Not available

Back to SPI/I2C Register Map

Table 120. Register 44, ADC 1

Name

Bit #

R/W

Reset

Default

Description

ADDLY10

ADDLY11

ADDLY12

ADDLY13

0

1

2

3

R/W DIGRESETB

0

This will allow delay before the ADC readings.

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

122

Functional Block Description

Table 120. Register 44, ADC 1

Name

Bit #

R/W

Reset

Default

Description

ADDLY20

ADDLY21

ADDLY22

ADDLY23

ADDLY30

ADDLY31

ADDLY32

ADDLY33

TSDLY10

TSDLY11

TSDLY12

TSDLY13

TSDLY20

TSDLY21

TSDLY23

TSDLY30

TSDLY31

TSDLY33

4

R/W DIGRESETB

0

5

This will allow delay between each of ADC readings in a set.

6

7

8

9

This will allow delay after the set of ADC readings. This delay is only valid between

subsequent wrap around reading sequences with ADCONT

10

11

12

13

14

15

16

17

18

19

20

21

22

23

This will allow delay before the ADC touch screen readings. This is like the ADDLY1,

but allows independent programming of touch screen readings from general purpose

ADC readings to prevent code replacement in the system.

This will allow delay between each of ADC touch screen readings in a set. This is like

the ADDLY2, but allows independent programming of touch screen readings from

general purpose ADC readings to prevent code replacement in the system.

This will allow delay after the set of ADC touch screen readings. This delay is only

valid between subsequent wrap around reading sequences with TSCONT mode.

This is like the ADDLY3, but allows independent programming of touch screen

readings from general purpose ADC readings to prevent code replacement in the

system.

Back to SPI/I2C Register Map

Table 121. Register 45, ADC 2

Name

Bit #

R/W

Reset

Default

Description

ADSEL00

ADSEL01

ADSEL02

ADSEL03

ADSEL10

ADSEL11

ADSEL12

ADSEL13

ADSEL20

ADSEL21

ADSEL22

ADSEL23

0

1

R/W

DIGRESETB

0

Channel Selection to place in ADRESULT0

2

3

4

5

Channel Selection to place in ADRESULT1

Channel Selection to place in ADRESULT2

6

7

8

9

10

11

34709

Analog Integrated Circuit Device Data

123

Freescale Semiconductor

Functional Block Description

Table 121. Register 45, ADC 2

Name

Bit #

R/W

Reset

Default

Description

ADSEL30

ADSEL31

ADSEL32

ADSEL33

ADSEL40

ADSEL41

ADSEL42

ADSEL43

ADSEL50

ADSEL51

ADSEL52

ADSEL53

12

13

14

15

16

17

18

19

20

21

22

23

R/W

DIGRESETB

0

Channel Selection to place in ADRESULT3

Channel Selection to place in ADRESULT4

Channel Selection to place in ADRESULT5

Back to SPI/I2C Register Map

Table 122. Register 46, ADC 3

Name

Bit # R/W

Reset

Default

Description

ADSEL60

ADSEL61

ADSEL62

ADSEL63

ADSEL70

ADSEL71

ADSEL72

ADSEL73

TSSEL00

0

1

2

3

4

5

6

7

8

R/W DIGRESETB

0

Channel Selection to place in ADRESULT6

Channel Selection to place in ADRESULT7

Touch screen Selection to place in ADRESULT0.

Select the action for the Touch screen; 00 = dummy to discharge TSREF capacitance,

01 = to read X-plate, 10 = to read Y-plate, and 11 = to read Contact.

TSSEL01

9

R/W DIGRESETB

0

TSSEL10

TSSEL11

TSSEL20

TSSEL21

TSSEL30

TSSEL31

TSSEL40

TSSEL41

TSSEL50

TSSEL51

TSSEL60

TSSEL61

10

11

12

13

14

15

16

17

18

19

20

21

R/W DIGRESETB

0

Touch screen Selection to place in ADRESULT1.

See TSSEL0 for modes.

Touch screen Selection to place in ADRESULT2.

See TSSEL0 for modes.

Touch screen Selection to place in ADRESULT3.

See TSSEL0 for modes.

Touch screen Selection to place in ADRESULT4.

See TSSEL0 for modes.

Touch screen Selection to place in ADRESULT5.

See TSSEL0 for modes.

Touch screen Selection to place in ADRESULT6.

See TSSEL0 for modes.

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

124

Functional Block Description

Table 122. Register 46, ADC 3

Name

Bit # R/W

Reset

Default

Description

TSSEL70

TSSEL71

22

23

R/W DIGRESETB

0

Touch screen Selection to place in ADRESULT7.

See TSSEL0 for modes.

Back to SPI/I2C Register Map

Table 123. Register 47, ADC 4

Name

Bit # R/W

Reset

Default

Description

Unused

0

1

R

0

Not available

Unused

ADRESULT00

ADRESULT01

ADRESULT02

ADRESULT03

ADRESULT04

ADRESULT05

ADRESULT06

ADRESULT07

ADRESULT08

ADRESULT09

Unused

2

DIGRESETB

3

4

5

6

ADC Result for ADSEL0

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

Not available

Unused

ADRESULT10

ADRESULT11

ADRESULT12

ADRESULT13

ADRESULT14

ADRESULT15

ADRESULT16

ADRESULT17

ADRESULT18

ADRESULT19

DIGRESETB

ADC Result for ADSEL1

Back to SPI/I2C Register Map

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

125

Functional Block Description

Table 124. Register 48, ADC5

Name

Bit # R/W

Reset

Default

Description

Unused

0

1

R

0

Not available

Unused

ADRESULT20

ADRESULT21

ADRESULT22

ADRESULT23

ADRESULT24

ADRESULT25

ADRESULT26

ADRESULT27

ADRESULT28

ADRESULT29

Unused

2

DIGRESETB

3

4

5

6

ADC Result for ADSEL2

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

Not available

Unused

ADRESULT30

ADRESULT31

ADRESULT32

ADRESULT33

ADRESULT34

ADRESULT35

ADRESULT36

ADRESULT37

ADRESULT38

ADRESULT39

DIGRESETB

ADC Result for ADSEL3

Back to SPI/I2C Register Map

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

126

Functional Block Description

Table 125. Register 49, ADC6

Name

Bit # R/W

Reset

Default

Description

Unused

0

1

R

0

Not available

Unused

ADRESULT40

ADRESULT41

ADRESULT42

ADRESULT43

ADRESULT44

ADRESULT45

ADRESULT46

ADRESULT47

ADRESULT48

ADRESULT49

Unused

2

DIGRESETB

3

4

5

6

ADC Result for ADSEL4

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

Not available

Unused

ADRESULT50

ADRESULT51

ADRESULT52

ADRESULT53

ADRESULT54

ADRESULT55

ADRESULT56

ADRESULT57

ADRESULT58

ADRESULT59

DIGRESETB

ADC Result for ADSEL5

Back to SPI/I2C Register Map

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

127

Functional Block Description

Table 126. Register 50, ADC7

Name

Bit # R/W

Reset

Default

Description

Unused

0

1

R

0

Not available

Unused

ADRESULT60

ADRESULT61

ADRESULT62

ADRESULT63

ADRESULT64

ADRESULT65

ADRESULT66

ADRESULT67

ADRESULT68

ADRESULT69

Unused

2

DIGRESETB

3

4

5

6

ADC Result for ADSEL6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

Not available

Unused

ADRESULT70

ADRESULT71

ADRESULT72

ADRESULT73

ADRESULT74

ADRESULT75

ADRESULT76

ADRESULT77

ADRESULT78

ADRESULT79

DIGRESETB

ADC Result for ADSEL7

Back to SPI/I2C Register Map

Table 127. Register 51, Reserved

Name

Bit # R/W

0 - 23

Reset

Default

Description

Unused

R

0

Not Available

Table 128. Register 52, Supply Debounce

Name

Bit # R/W

Reset

Default

Description

Reserved

0

R

-

For Future use

1

2

VBATTDB0

VBATTDB1

Reserved

R/W RESETB

1

-

Low input warning (BP) debounce

For Future use

3

4 - 23

R

-

Back to SPI/I2C Register Map

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

128

Functional Block Description

Table 129. Register 53 - 54, Reserved

Name

Bit # R/W

0 - 23

Reset

Default

Description

Unused

R

0

Not Available

Table 130. Register 55, PWM Control

Name

Bit # R/W

Reset

Default

Description

PWM1DUTY0

PWM1DUTY1

PWM1DUTY2

PWM1DUTY3

PWM1DUTY4

PWM1DUTY5

PWMCLKDIV0

PWM1CLKDIV1

PWM1CLKDIV2

PWM1CLKDIV3

PWM1CLKDIV4

PWM1CLKDIV5

PWM2DUTY0

PWM2DUTY1

PWM2DUTY2

PWM2DUTY3

PWM2DUTY4

PWM2DUTY5

PWM2CLKDIV0

PWM2CLKDIV1

PWM2CLKDIV2

PWM2CLKDIV3

PWM2CLKDIV4

PWM2CLKDIV5

0

1

2

3

4

5

6

7

8

9

R/W RESETB

0

PWM1 Duty Cycle

PWM1 Clock Divide Setting

10 R/W RESETB

11 R/W RESETB

12 R/W RESETB

13 R/W RESETB

14 R/W RESETB

15 R/W RESETB

16 R/W RESETB

17 R/W RESETB

18 R/W RESETB

19 R/W RESETB

20 R/W RESETB

21 R/W RESETB

22 R/W RESETB

23 R/W RESETB

PWM2 Duty Cycle

PWM2 Clock Divide Setting

Back to SPI/I2C Register Map

Table 131. Register 56 - 63, Unused

Name

Bit #

R/W

Reset

Default

Description

Unused

0-23

R

0

Not available

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

129

Typical Applications

8

Typical Applications

Figure 24 gives a typical application diagram of the 34709 PMIC together with its functional components. For details on

component references and additional components such as filters, refer to the individual sections.

8.1

Application Diagram

SW1 Output

2 x22u

C2

4.7u

L1A

1.0u

BP

SW1IN

SW1ALX

GNDSW1A

SW1FB

O/P

Drive

C3/C4

SW1

Dual Phase

GP

2000 mA

Buck

SW1CFG

SW1VSSSNS

VCOREDIG

To AP

D1

GNDADC

SW1BLX

GNDSW1B

O/P

Drive

R18

100K

10 Bit GP

ADC

A/D Result

ADIN9

DVS

SW1PWGD

General Purpose

CONTROL

ADC Inputs:

i.e., PA thermistor,

Light Sensor, Etc.

ADIN10

SW2 Output

C6

C5

4.7u

BP

L2

A/D

Control

ADIN11

1.0u

SW2IN

SW2LX

GNDSW2

SW2FB

22u

MUX

O/P

Drive

SW2

ADIN12/TSX1

ADIN13/TSX2

ADIN14/TSY1

D2

R19

100K

LP

Touch

Screen

Interface

`

1000 mA

SW2PWGD

To AP

BP

Buck

Touch

Screen

Interface

SW3 Output

C8 10u

C7

4.7u

L3

1.0u

ADIN15/TSY2

TSREF

SW3IN

C34

SW3

INT MEM

500 mA

Buck

O/P

Drive

SW3LX

GNDSW3

SW3FB

D3

2.2u

C9

4.7u

SW4A Output

L4A

1.0u

BP

SW4AIN

C10

10u

SW4ALX

GNDSW4A

SW4FBA

O/P

Drive

D4

SW4

Dual Phase

DDR

SW4CFG

1000 mA

Buck

SW4B Output

C12 10u

C11

4.7u

L4B

1.0u

Package Pin Legend

BP

SW4BIN

SW4BLX

GNDSW4B

SW4BFB

O/P

Drive

Output Pin

Input Pin

D5

SPIVCC

Shift Register

Bi-directional Pin

SW5

SW5 Output

C14 22u

C13

4.7u

L5

1.0u

CS

SPI

SW5IN

Interface

+

Muxed

I2C

CLK

SW5

I/O

1000 mA

Buck

O/P

Drive

SW5LX

GNDSW5

SW5FB

SPI

D6

SPI

MOSI

MISO

To Enables & Control

Registers

BP

C15

4.7u

Optional

Interface

GNDSPI

Shift Register

L6

2.2u

SWBSTIN

SWBSTLX

SWBSTFB

SWBST

Output

(Boost)

BP

D7

O/P

Drive

SWBST

380 mA

Boost

GNDSWBST

C16

10u

C33

VCORE

MC34709

1u

C32

VCOREDIG

VDDLP

Reference

Generation

1u

SW4B

C17

100n

C31

VINREFDDR

VHALF

C18

100n

C30

VCOREREF

100pF

VREFDDR

10mA

GNDCORE

GNDREF

100n

VREFDDR

1u

C19

Main input Supply - BP

C20

2.2u

BP

VINPLL

VPLL

BP

VPLL

50 mA

Pass

FET

C1

10u

BP

VUSB2DRV

VUSB2

Q1

Pass

FET

VUSB2

350mA

C21

2.2u

BP

VDACDRV

VDAC

250mA

Q2

C22

2.2u

To

Trimmed

Circuits

SPI

Trim-In-Package

Control

Logic

C23

SW5

VINGEN1

VGEN1

250mA

Pass

FET

2.2u

BP

Startup

Sequencer

Decode

Trim?

VINUSB

SWBST

Control

Logic

VGEN2DRV

VGEN2

PUMSx

Q3

VUSB

Regulator

PLL

Switchers

C29

VUSB

Pass

FET

VGEN2

250mA

Monitor

Timer

GNDUSB

2.2u

C24

2.2u

RTC

Calibration

+

32 KHz

Internal

Osc

LDOVDD

BP

SPI Result

Registers

Interrupt

Inputs

Enables &

Control

32 KHz

Buffers

Best

of

Supply

Coin Cell

Battery

GNDREG1

GNDREG2

GNDREF1

GNDREF2

BP

LCELL

Switch

LICELL

C28

100n

PWM

Outputs

32 KHz

Crystal

Osc

GPIO Control

Li Cell

Charger

Core Control Logic, Timers, & Interrupts

Digital Core

VSRTC

R4

R20 R3

C25

0.1u

To/From

AP

To AP

To Peripherals

To GND, or

VCOREDIG

18p

C27

18p

C26

Y1

32.768 KHz

Crystal

On/Off

Button

Reset

button

Figure 24. Typical Application Schematic

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

130

Typical Applications

8.2

Bill of Material

Table 132 provides a complete list of the recommended components on a full featured system using the 34709 Device. Critical

components such as inductors, transistors, and diodes are provided with a recommended part number, but equivalent

components may be used.

Table 132. 34709 Bill of Material ⁽⁶⁹⁾

Item Reference Quantity

Description

Vendor

Comments

34709

Freescale

PMIC

1

U1

Battery/supply input

C1

Miscellaneous

1

10 F

TDK

Battery Filter

2

100 nF

1.0 F

100 pF

100 nF

2.2 F

100 nF

VSRTC

3

4

C25

C33

1

2

1

VCORE

VCOREDIG

VDDLP

5

C32

6

C31

VCOREREF

TSREF

7

C30

8

C34

Coin cell

Oscillator

9

C28

Crystal 32.768 kHz CC7

10

11

12

13

Boost

14

15

16

17

SW1

Y1

18 pF

100 k

Oscillator load capacitors

RESETB, RESETBMCU Pull-ups

SDWNB Pull-up

C26, C27

R3, R4

R20

2.2 H LPS3015-222ML

Diode BAS52

10 F 16 V

Coilcraft

Infineon

Boost Inductor

L6

D7

1

Boost diode

Boost Output Capacitor

Boost Input Capacitor

C16

C15

4.7 F

Buck 1 Inductor (I_MAX< 1.6 Amps)

Alternate part numbers:

• 1.0 H VLS252010ET-1R0N (TDK)

• 1.0 H BRL3225T1ROM (Taiyo Yuden)

• 1.0 uH LPS4012-102NL (Coilcraft)

1.0 H VLS201612ET-1R0N TDK

18

L1A, L1B

2

22 F

Buck 1 Output Capacitor

Buck 1 Input Capacitor

SW1LX diode

19

20

21

C3, C4

C2

2

1

4.7 F

Diode BAS3010-03LRH

Infineon

D1

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

131

Typical Applications

Table 132. 34709 Bill of Material ⁽⁶⁹⁾

Item Reference Quantity

Description

Vendor

Comments

SW2

1.0 H VLS252010ET-1R0N TDK

Buck 2 Inductor

22

23

L2

C6

C5

D2

1

22 F

Buck 2 Output Capacitor

Buck 2 Input Capacitor

SW2LX diode

4.7 F

24

Diode BAS3010-03LRH

Infineon

25

SW3

26

1.0 H VLS201612ET-1R0N TDK

Buck 3 Inductor

L3

C8

C7

D3

1

10 F

Buck 3 Output Capacitor

Buck 3 Input Capacitor

SW3LX diode

27

4.7 F

28

Diode BAS3010-03LRH

Infineon

29

SW4A

Buck 4A Inductor

1.0 H VLS201612ET-1R0N TDK

Alternate Part number:

30

L4A

1

1.0 H VLS252010ET-1R0N (TDK)

10 F

Buck 4A Output Capacitor

Buck 4A Input Capacitor

SW4ALX diode

31

32

C10

C9

1

4.7 F

Diode BAS3010-03LRH

Infineon

33

D4

SW4B

Buck 4B Inductor

1.0 H VLS201612ET-1R0N TDK

Alternate Part numbers:

1.0 H VLS252010ET-1R0N (TDK)

34

L4B

1

10 F

Buck 4B Output Capacitor

Buck 4B Input Capacitor

SW4BLX diode

35

36

C12

C11

D5

1

4.7 F

Diode BAS3010-03LRH

Infineon

37

SW5

38

1.0 H VLS252010ET-1R0N TDK

Buck 5 Inductor

L5

C14

C13

D6

1

22 F

Buck 5 Output Capacitor

Buck 5 Input Capacitor

SW5LX diode

39

4.7 F

40

Diode BAS3010-03LRH

Infineon

41

VPLL

42

2.2 F

VPLL output Capacitor

C20

1

VREFDDR

43

100 nF

1.0 F

100 nF

VHALF 0.1 uF caps

C18

C19

C17

1

VREFDDR output Capacitor

VREFDDR input Capacitor

44

45

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

132

Typical Applications

Table 132. 34709 Bill of Material ⁽⁶⁹⁾

Item Reference Quantity

Description

Vendor

Comments

VDAC

PNP NSS12100UW3TCG

PNP NSS12100XV6T1G

VDAC PNP - 500 W dissipation

On Semi

46

Q2

1

VDAC PNP - 250 W dissipation - Alternate

2.2 F

VDAC output Capacitor

47

C22

VUSB2

PNP NSS12100UW3TCG

PNP NSS12100XV6T1G

VUSB2 PNP - 500 W dissipation

On Semi

48

Q1

1

VUSB2 PNP - 250 W dissipation - Alternate

2.2 F

VUSB2 output Capacitor

VUSB output Capacitor

VGEN1 output Capacitor

49

C21

VUSB

50

C29

C23

1

VGEN1

51

VGEN2

PNP NSS12100UW3TCG

PNP NSS12100XV6T1G

VGEN2 PNP - 500 W dissipation

On Semi

52

Q3

1

VGEN2 PNP - 250 W dissipation - Alternate

2.2 F

VGEN2 output Capacitor

53

C24

Notes

69. Freescale does not assume liability, endorse, or warrant components from external manufacturers that are referenced in circuit

drawings or tables. While Freescale offers component recommendations in this configuration, it is the customer’s responsibility to

validate their application.

8.3

34709 Layout Guidelines

8.3.1

General board recommendations

1. It is recommended to use an 4 layer board stack-up arranged as follows:

•

High-current signal

GND

Signal

High-current signal

2. Allocate TOP and BOTTOM PCB Layers for POWER ROUTING (high-current signals), copper-pour the unused area.

3. Add one GND inner layer to reduce Current loops to the maximum between layers.

8.3.2

General Routing Requirements

1. Some recommended things to keep in mind for manufacturability:

•

Via in pads require a 4.5 mil Minimum annular ring. Pad must be 9.0 mils larger than the hole

Max copper thickness for lines less than 5.0 mils wide is 0.6 oz copper

Minimum allowed spacing between line and hole pad is 3.5 mils

Minimum allowed spacing between line and line is 3.0 mils

2. Care must be taken with SWxFB pins traces. These signals are susceptible to noise and must be routed far away from

power, clock, or high-power signals, like the ones on the SWxIN, SWx, SWxLX, SWBSTIN, SWBST, and SWBSTLX pins.

34709

Analog Integrated Circuit Device Data

133

Freescale Semiconductor

Typical Applications

3. Shield feedback traces of the switching regulators and keep them as short as possible (trace them on the bottom so the

ground and power planes shield these traces).

4. Avoid coupling trace between important signal/low noise supplies (like VREFCORE, VCORE, VCOREDIG) from any

switching node (i.e. SW1ALXx, SW2LX, SW3LX, SW4ALX, SW4BLX, SW5LX, and SWBSTLX).

5. Make sure that all components related to an specific block are referenced to the corresponding ground, e.g. all

components related to the SW1 converter must referenced to GNDSW1A1 and GNDSW1A2.

8.3.3

Parallel Routing Requirements

2

1. SPI/I C signal routing:

•

CLK is the fastest signal of the system, so it must be given special care. Here are some tips for routing the communication

signals:

•

To avoid contamination of these delicate signals by nearby high-power or high-frequency signals, it is a good practice to

shield them with ground planes placed on adjacent layers. Make sure the ground plane is uniform throughout the whole

signal trace length.

Figure 25. Recommended Shielding for Critical Signals.

•

These signals can be placed on an outer layer of the board to reduce their capacitance in respect to the ground plane.

The crystal connected to the XTAL1 and XTAL2 pins must not have a ground plane directly below.

The following are clock signals: CLK, CLK32K, CLK32KMCU, XTAL1, and XTAL2. These signals must not run parallel to

each other, or in the same routing layer. If it is necessary to run clock signals parallel to each other, or parallel to any other

signal, then follow a MAX PARALLEL rule as follows:

• Up to one inch parallel length – 25 mil minimum separation

• Up to two inches parallel length – 50 mil minimum separation

• Up to three inches parallel length – 100 mil minimum separation

• Up to four inches parallel length – 250 mil minimum separation

•

Care must be taken with these signals not to contaminate analog signals, as they are high-frequency signals. Another good

practice is to trace them perpendicularly on different layers, so there is a minimum area of proximity between signals.

8.3.4

Switching Regulator Layout Recommendations

1. Per design, the 34709 is designed to operate with only one input bulk capacitor. However, it is recommended to add a

high-frequency filter input capacitor (CIN_hf), to filter out any noise at the regulator input. This capacitor should be in the

range of 100 nF and should be placed right next to or under the IC, closest to the IC pins.

2. Make high-current ripple traces low inductance (short, high W/L ratio).

3. Make high-current traces wide or copper islands.

4. Make high-current traces SYMETRICAL for dual–phase regulators (SW1, SW4).

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

134

Typical Applications

V_BP

SWxVIN

C_{IN_HF}

C_IN

SWx

SWxLX

Diver Controller

L

C_OUT

D

GNDSWx

SWxFB

Compensation

Figure 26. Generic Buck Regulator Architecture

Figure 27. Recommended Layout for Switching Regulators.

8.4

Thermal Considerations

8.4.1

Rating Data

The thermal rating data of the packages has been simulated with the results listed in Table 5.

Junction to Ambient Thermal Resistance Nomenclature: the JEDEC specification reserves the symbol R

strictly for junction-to-ambient thermal resistance on a 1s test board in natural convection environment. R

or θJA (Theta-JA)

or θJMA 

θJA

θJMA

(Theta-JMA) will be used for both junction-to-ambient on a 2s2p test board in natural convection and for junction-to-ambient with

34709

Analog Integrated Circuit Device Data

135

Freescale Semiconductor

Typical Applications

forced convection on both 1s and 2s2p test boards. It is anticipated that the generic name, Theta-JA, will continue to be commonly

used.

The JEDEC standards can be consulted at http://www.jedec.org/

8.4.2

Estimation of Junction Temperature

An estimation of the chip junction temperature TJ can be obtained from the equation

T = T + (R

x P )

D

J

A

θJA

with

T = Ambient temperature for the package in °C

A

R_= Junction to ambient thermal resistance in °C/W

JA

P

= Power dissipation in the package in W

D

The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal

performance. Unfortunately, there are two values in common usage: the value determined on a single layer board R and the

θJA

value obtained on a four layer board R

. Actual application PCBs show a performance close to the simulated four layer board

θJMA

value although this may be somewhat degraded in case of significant power dissipated by other components placed close to the

device.

At a known board temperature, the junction temperature T is estimated using the following equation

J

T = T + (R

x P ) with

D

J

B

θJB

T = Board temperature at the package perimeter in °C

B

R

= Junction to board thermal resistance in °C/W

θJB

P

= Power dissipation in the package in W

D

When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made.

See Functional Block Description for more details on thermal management.

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

136

Packaging

9

Packaging

The 34709 is offered in an 130 balls, 8.0x8.0 mm, 0.5 mm pitch MAPBGA package.

9.1

Package Mechanical Dimensions

Package dimensions are provided in package drawings. To find the most current package outline drawing, go to

www.freescale.com and perform a keyword search for the drawing’s document number.

Table 133. Package Drawing Information

Package

Suffix

Package Outline Drawing Number

98ASA00333D

130-pin MAPBGA (8 x 8), 0.5 mm

VK

Dimensions shown are provided for reference ONLY (For Layout and Design, refer to the Package Outline Drawing listed in the

following figures).

34709

Analog Integrated Circuit Device Data

137

Freescale Semiconductor

Packaging

VK SUFFIX

130-PIN

98ASA00333D

REVISION 0

Figure 28. 8 x 8 Package Mechanical Dimension

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

138

Packaging

VK SUFFIX

130-PIN

98ASA00333D

REVISION 0

Figure 29. 8 x 8 Package Mechanical Dimension

34709

Analog Integrated Circuit Device Data

139

Freescale Semiconductor

Reference Section

10 Reference Section

Table 134. MC34709 Reference Documents

Reference

Description

34709FS

34709ER

Freescale Fact Sheet

Freescale Errata

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

140

Revision History

11 Revision History

REVISION

DATE

DESCRIPTION OF CHANGES

•

Initial release

Corrected doc number to MC34709, corrected part number PC34709VK

Removed Freescale Confidential Proprietary on page 1

1.0

8/2012

34709

Analog Integrated Circuit Device Data

Freescale Semiconductor

141

Information in this document is provided solely to enable system and software

implementers to use Freescale products. There are no express or implied copyright

licenses granted hereunder to design or fabricate any integrated circuits on the

information in this document.

How to Reach Us:

Home Page:

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Freescale reserves the right to make changes without further notice to any products

herein. Freescale makes no warranty, representation, or guarantee regarding the

suitability of its products for any particular purpose, nor does Freescale assume any

liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation consequential or incidental

damages. “Typical” parameters that may be provided in Freescale data sheets and/or

specifications can and do vary in different applications, and actual performance may

vary over time. All operating parameters, including “typicals,” must be validated for

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Freescale, the Freescale logo, AltiVec, C-5, CodeTest, CodeWarrior, ColdFire, C-Ware,

Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, Qorivva, StarCore, and

Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. 

Airfast, BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, MagniV, MXC, Platform in a

Package, Processor expert, QorIQ Qonverge, QUICC Engine, Ready Play,

SMARTMOS, TurboLink, Vybrid, and Xtrinsic are trademarks of Freescale

Semiconductor, Inc. All other product or service names are the property of their

respective owners.

Document Number: MC34709

Rev. 1.0

8/2012


型号：	PC34709VK
厂家：	Freescale
描述：	Power Management Integrated Circuit (PMIC) for i.MX50/53 Families 功率管理集成电路（PMIC ），用于i.MX50 / 53族集成电源管理电路
文件：	总142页 (文件大小：5056K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PC34709VK [FREESCALE]

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