FTK20NS65PD [FS]

20Amps, 650Volts N-Channel Super Juction MOS-FET;


型号：	FTK20NS65PD
厂家：	First Silicon Co., Ltd
描述：	20Amps, 650Volts N-Channel Super Juction MOS-FET
文件：	总7页 (文件大小：889K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SEMICONDUCTOR

FTK20NS65P/F/DD

TECHNICAL DATA

20Amps, 650Volts N-Channel Super Juction MOS-FET

Product Summary

VDS @ Tj,max

R^DS(on),max

I^DM

650V

0.15Ω

60A

P :

Q^g,typ

39nC

TO-220

DESCRIPTION

F :

FTK20NS65 Power MOS FET is fabricated using

advanced super junction technology. The resulting

device has extremely low on resistance, making it

especially suitable for applications which require

superior power density and outstanding efficiency.

TO-220F

DD :

FEATURES

TO-263

�

Ultra fast body diode

Ultra low RDS(on)

Ultra low gate charge (typ. Qg = 39nC)

100% UIS tested

RoHS compliant

Applications

SYMBOL

�

Power faction correction (PFC).

2.Drain

�

Switched mode power supplies (SMPS).

Uninterruptible power supply (UPS).

1.Gate

3.Source

ORDERING INFORMATION

Pin Assignment

Order Number

Package

Packing

FTK20NS65P

FTK20NS65F

FTK20NS65DD

TO-220

TO-220F

TO-263

Tube

Reel & Taping

Note: Pin Assignmen:

G: Gate

D: Drain

S: Source

2017. 07. 05

Revision No : 1

1/7

FTK20NS65P/F/DD

Absolute Maximum Ratings

Parameter

Symbol

Value

650

Unit

Drain - Source Voltage

V_DSS

I_D

Continuous drain current

( TC = 25°C )

( TC = 100°C )

Pulsed drain current ¹⁾

Gate - Source voltage

I_DM

V_GSS

± 30

Avalanche energy, single pulse ²⁾

E_AS

600

Avalanche energy, repetitive ³⁾

Avalanche current, repetitive ³⁾

E_AR

I_AR

0.4

Power Dissipation

( TC = 25°C )

P_D

205

- Derate above 25°C

1.64

W/°C

°C

Operating and Storage Temperature Range

Continuous diode forward current

Diode pulse current

T_J, T_STG

I_S

-55 to +150

I_S,pulse

Thermal CharacteristicsTO-220/TO-263

Parameter

Symbol

Value

0.61

Unit

°C/W

Thermal Resistance, Junction-to-Case

Thermal Resistance, Junction-to-Ambient

R_θJC

R_θJA

Thermal Characteristics TO-220F

Parameter

Symbol

Value

3.7

Unit

°C/W

Thermal Resistance, Junction-to-Case

Thermal Resistance, Junction-to-Ambient

R_θJC

R_θJA

2017. 07. 05

Revision No : 1

2/7

FTK20NS65P/F/DD

Electrical Characteristics T_c= 25°C unless otherwise noted

Parameter

Static characteristics

Drain-source breakdown voltage

Gate threshold voltage

Symbol

Test Condition

Min.

Typ.

Max.

Unit

BV_DSS

V_GS(th)

I_DSS

V_GS=0 V, I_D=0.25 mA

V_DS=V_GS, I_D=0.25mA

V_DS=650 V, V_GS=0 V,

T_j= 25°C

650

2.5

3.5

4.5

Drain cut-off current

μA

T_j= 125°C

Gate leakage current, Forward

I_GSSF

V_GS=30 V, V_DS=0 V

Gate leakage current, Reverse

Drain-source on-state resistance

I_GSSR

V_GS=-30 V, V_DS=0 V

V_GS=10 V, I_D=10 A

T_j= 25°C

-50

R_DS(on)

0.15

0.4

0.18

T_j= 150°C

Gate resistance

R_G

f=1 MHz, open drain

4.5

Dynamic characteristics

Input capacitance

C_iss

C_oss

C_rss

t_d(on)

t_r

V_DS= 25 V, V_GS= 0 V,

f = 1 MHz

2637

1250

Output capacitance

Reverse transfer capacitance

Turn-on delay time

Rise time

V_DD= 380V, I_D= 10A

R_G= 4.7Ω, V_GS=10V

Turn-off delay time

t_d(off)

t_f

113

Fall time

Gate charge characteristics

Gate to source charge

Gate to drain charge

Q_gs

V_DD=480 V, I_D=10A,

V_GS=0 to 10 V

10.3

13.7

Q_gd

Gate charge total

Q_g

Gate plateau voltage

V_plateau

5.5

Reverse diode characteristics

Diode forward voltage

Reverse recovery time

Reverse recovery charge

Peak reverse recovery current

V_SD

t_rr

V_GS=0 V, I_F=10A

V_R=50 V, I_F=20A,

dI_F/dt=100 A/μs

1.0

513

7.5

μC

Q_rr

I_rrm

Notes:

1. Limited by maximum junction temperature, maximum duty cycle is 0.75.

2. I_AS= 5A, V_DD=60V, Starting T_j= 25°C.

3. Repetitive Rating: Pulse width limited by maximum junction temperature.

2017. 07. 05

Revision No : 1

3/7

FTK20NS65P/F/DD

Typical Characteristics

Electrical Characteristics Diagrams

Figure 1. On-Region Characteristics

Figure 2. Transfer Characteristics

V_GS=10V

Common Source

T_c= 25°C

V_GS=7V

Pulse test

V_DS=20 V

Pulse test

V_GS=6.5V

V_GS=6V

V_GS=5.5V

Drain−source voltage _DV_S(V)

Gate−source voltageV_GS(V)

Figure 3. On-Resistance Variation vs. Drain Current

Figure 4. Threshold Voltage vs. Temperature

V_GS= 10V

T_c= 25°C

Pulse test

I_DS=0.25 mA

Pulse test

Junction temperature T_j(°C)

Drain current I_D(A)

Figure 5. Breakdown Voltage vs. Temperature

Figure 6. On-Resistance vs. Temperature

V_GS=0 V

I_DS=0.25 mA

Pulse test

V_GS=10 V

I_DS=10 A

Pulse test

Junction temperature T_j(°C)

2017. 07. 05

Revision No : 1

4/7

FTK20S65P/F/DD

Figure 7. Capacitance Characteristics

Figure 8. Gate Charge Characterist

C_iss= C_gs+ C_gd(C_ds= shorted)

C_oss= C_ds+ C_gd

= C

C_iss

C_oss

I_D= 10A

C_rss

Notes:

f = 1 MHz

V_GS=0 V

Total Gate Charge Q_G(nC)

Drain-Source Voltage V_DS(V)

Figure 9.1 Maximum Safe Operating Area

TO-220F

Figure 9.2 Maximum Safe Operating Area

TO-220/TO-263

Drain-Source Voltage V_DS(V)

Figure 10.1 Power Dissipation vs. Temperature

TO-220F

Figure 10.2 Power Dissipation vs. Temperature

TO-220/TO-263

Case temperature T_c(°C)

Revision No : 0

5/7

2017. 07. 05

FTK20NS65P/F/DD

D.U.T.

V_DS

R_G

Driver

V_DD

* dv/dt controlled by R

* I_SDcontrolled by pulse period

* D.U.T.-Device Under Test

Same Type

as D.U.T.

V_GS

Fig. 1A Peak Diode Recovery dv/dt Test Circuit

Period

P. W.

V_GS

(Driver)

P.W.

Period

10V

V_GS

_FM, Body Diode Forward Current

I_SD

(D.U.T.)

di/dt

I_RM

Body Diode Reverse Current

Body Diode Recovery dv/dt

V_DS

(D.U.T.)

V_DD

Body Diode

Forward Voltage Drop

Fig. 1B Peak Diode Recovery dv/dt Waveforms

2017. 07. 05

Revision No : 1

6/7

FTK20NS65P/F/DD

TEST CIRCUITS AND WAVEFORMS (Cont.)

R_L

V_DS

90%

V_DD

V_GS

R_G

10%

V_GS

D.U.T.

10V

t_D(ON)

t_D(OFF)

Pulse Width ≤ 1μs

Duty Factor ≤ 0 1%

t_F

t_R

Fig. 2A Switching Test Circuit

Fig. 2B Switching Waveforms

Same Type

as D.U.T.

50kΩ

Q_G

12V

10V

0 3μF

0.2μF

V_DS

Q_GS

Q_GD

V_GS

DUT

V_G

3mA

Charge

Fig. 3A Gate Charge Test Circuit

Fig. 3B Gate Charge Waveform

V_DS

BV_DSS

R_D

V_DD

10V

D.U.T.

t_p

I_AS

Time

t_p

Fig. 4A Unclamped Inductive Switching Test Circuit

Fig. 4B Unclamped Inductive Switching Waveforms

2017. 07. 05

Revision No : 1

7/7

相关型号：