FT2232C_技术文档

FT2232C Dual USB UART / FIFO I.C.

1.0 Introduction

The FT2232C is the 3^rdgeneration of FTDI’s popular USB UART / FIFO I.C. family. This device features two Multi-

Purpose UART / FIFO controllers which can be conﬁgured individually in several different modes. As well as a UART

interface, FIFO interface and Bit-Bang IO modes of the 2^ndgeneration FT232BM and FT245BM devices, the FT2232C

offers a variety of additional new modes of operation, including a Multi-Protocol Synchronous Serial Engine interface

which is designed speciﬁcally for synchronous serial protocols such as JTAG and SPI bus.

1.1 Features Summary

HARDWARE FEATURES

•

Integrated Power-On-Reset circuit, with optional

Reset input and Reset Output pins

5V and 3.3V logic IO Interfacing with independent

level conversion on each channel

•

Single Chip USB ó Dual Channel Serial / Parallel

Ports with a variety of conﬁgurations

Entire USB protocol handled on the chip...no USB-

speciﬁc ﬁrmware programming required

FT232BM-style UART interface option with full

Handshaking & Modem interface signals

UART Interface supports 7 / 8 bit data, 1 / 2 stop

bits, and Odd / Even / Mark / Space / No Parity

Transfer Data Rate 300 to 1 Mega Baud (RS232)

Transfer Data Rate 300 to 3 Mega Baud (TTL and

RS422 / RS485)

•

Integrated 3.3V LDO Regulator for USB IO

Integrated 6MHz – 48Mhz clock multiplier PLL

USB Bulk or Isochronous data transfer modes

4.35V to 5.25V single supply operating voltage

range

•

UHCI / OHCI / EHCI host controller compatible

USB 2.0 Full Speed (12 Mbits / Second)

compatible

•

Compact 48-LD LQFP package

•

Auto Transmit Enable control for RS485 serial

applications using TXDEN pin

VIRTUAL COM PORT (VCP) DRIVERS for

•

Windows 98 / 98 SE / 2000 / ME / XP

Linux 2.40 and greater

Windows CE **

FT245BM-style FIFO interface option with bi-

directional data bus and simple 4 wire handshake

interface

MAC OS-8 and OS-9**

MAC OS-X**

•

Transfer Data Rate up to 1 MegaByte / Second

Enhanced Bit-Bang Mode interface option

New Synchronous Bit-Bang Mode interface option

New CPU-Style FIFO Interface Mode option

New Multi-Protocol Synchronous Serial Engine

(MPSSE) interface option

D2XX (USB Direct Drivers + DLL S/W Interface)

Windows 98 / 98 SE / 2000 / ME / XP

APPLICATION AREAS

•

USB óDual Port RS232 Converters

USB ó Dual Port RS422 / RS485 Converters

Upgrading Legacy Peripheral Designs to USB

USB Instrumentation

•

New MCU Host Bus Emulation Mode option

New Fast Opto-Isolated Serial Interface Mode

option

USB JTAG Programming

•

Interface mode and USB Description strings

conﬁgurable in external EEPROM

USB to SPI Bus Interfaces

USB Industrial Control

•

EEPROM Conﬁgurable on board via USB

Support for USB Suspend and Resume conditions

via PWREN#, and SI / WU pins

Field Upgradable USB Products

Galvanically Isolated Products with USB Interface

•

Support for bus powered, self powered, and high-

power bus powered USB conﬁgurations

[ ** = In planning or under development ]

DS2232C Version 1.2

Page 1 of 54

FT2232C Dual USB UART / FIFO I.C.

1.2 General Description

The FT2232C is a USB interface which incorporates the functionallity of two of FTDI’s second generation BM chips

into a single device. A single downstream USB port is converted to two IO channels which can each be individually

conﬁgured as a FT232BM-style UART interface, or a FT245BM-style FIFO interface, without the need to add a

USB hub. There are also several new special modes which are either enabled in the external EEPROM, or by using

driver commands. These include Synchronous Bit-Bang Mode, a CPU-Style FIFO Interface Mode, a Multi-Protocol

Synchronous Serial Engine Interface Mode, MCU Host Bus Emulation Mode, and Fast Opto-Isolated Serial Interface

Mode. In addition a new high drive level option means that the device UART / FIFO IO pins will drive out at around

three times the normal power level, meaning that the bus can be shared by several devices. Classic BM-style

Asynchronous Bit-Bang Mode is also supported, but has been enhanced to give the user access to the device’s

internal RD# and WR# strobes.

FTDI provide a royalty free Virtual Com Port (V.C.P) driver that makes the peripheral ports look like a standard COM

port to the PC. Most existing software applications should be able interface with the Virtual Com Port simply by

reconﬁguring them to use the new ports created by the driver. Using the VCP drivers an application programmer would

communicate with the device in exactly the same way as they would a regular PC COM port - using the Windows

VCOMM API calls or a COM port library. The FT2232C driver also incorporates the functions deﬁned for FTDI’s D2XX

drivers, allowing applications programmers to interface software directly to the device using a Windows DLL. Details of

the driver and the programming interface can be found on FTDI’s website at www.ftdichip.com.

DS2232C Version 1.2

Page 2 of 54

FT2232C Dual USB UART / FIFO I.C.

2.0 Features and Enhancements

The FT2232C incorporates all of the enhancements introduced for the second generation FT232BM and FT245BM

chips. These are summarised as follows :-

•

Two Individually Conﬁgurable IO Channels

Each of the FT2232C’s Channels (A and B) can be

individually conﬁgured as a FT232BM-style UART

interface, or as a FT245BM-style FIFO interface. In

addition these channel can be conﬁgured in a number

of special IO modes.

is also retained. This will make the device gently

pull down on the FIFO / UART IO lines when the

power is shut off (PWREN# is high). In this mode any

residual voltage on external circuitry is bled to GND

when power is removed, thus ensuring that external

circuitry controlled by PWREN# resets reliably when

power is restored.

•

Integrated Power-On-Reset (POR) circuit

The device incorporates an internal POR function.

A RESET# pin is available to allow external logic to

reset the device where required, however for most

applications this pin can simply be hardwired to Vcc.

A RSTOUT# pin is provided in order to allow the new

POR circuit to provide a stable reset to external MCU

and other devices.

•

Support for Isochronous USB Transfers

Whilst USB Bulk transfer is usually the best choice

for data transfer, the scheduling time of the data is

not guaranteed. For applications where scheduling

latency takes priority over data integrity such as

transferring audio and low bandwidth video data,

the FT2232C offers the option of USB Isochronous

transfer via conﬁguration of bit in the EEPROM.

•

Integrated RCCLK circuit

Used to ensure that the oscillator and clock multiplier

PLL frequency are stable prior to USB enumeration.

•

Send Immediate / Wake Up Signal Pin on each

channel

There is a Send Immediate / Wake Up (SI/WU) signal

pins on each of the chips channels. These combine

two functions on one pin. If USB is in suspend mode

(and remote wakeup is enabled in the EEPROM),

strobing this pin low will cause the device to request

a resume from suspend (WakeUp) on the USB Bus.

Normally, this can be used to wake up the Host PC.

During normal operation, if this pin is strobed low

any data in the device RX buffer will be sent out over

USB on the next Bulk-IN request from the drivers

regardless of the packet size. This can be used to

optimise USB transfer speed for some applications.

Integrated level converter on UART / FIFO

interface and control signals

Each channel of the FT2232C has its own

independent VCCIO pin that can be supplied by

between 3V to 5V. This allows each channel’s output

voltage drive level to be individually conﬁgured. Thus

allowing, for example 3.3V logic to be interfaced

to the device without the need for external level

converter I.C.’s.

•

Improved power management control for high-

power USB Bus Powered devices

The PWREN# pin will become active when the

device is enumerated by USB, and be deactivated

when the device is in USB suspend. This can be

used to directly drive a transistor or P-Channel

MOSFET in applications where power switching

of external circuitry is required. The BM pull down

enable feature (conﬁgured in the external EEPROM)

•

Low suspend current

The suspend current of the FT2232C is typically

under 100 μA (excluding the 1.5K pull up resistor on

USBDP) in USB suspend mode. This allows greater

margin for peripherals to meet the USB Suspend

current limit of 500uA.

DS2232C Version 1.2

Page 3 of 54

FT2232C Dual USB UART / FIFO I.C.

•

Programmable Receive Buffer Timeout

The TX buffer timeout is programmable over USB in

1ms increments from 1ms to 255ms, thus allowing

the device to be better optimised for protocols

requiring faster response times from short data

packets.

•

Extended EEPROM Support

The FT2232C supports 93C46 (64 x 16 bit), 93C56

(128 x 16 bit), and 93C66 (256 x 16 bit) EEPROMs.

The extra space is not used by the device, however

it is available for use by other external MCU / logic

whilst the FT2232C is being held in reset. There is

now an adiitional 64 words of space available (128

bytes total) in the user area when a 93C56 or 93C66

is used.

•

Relaxed VCC Decoupling

The improved level of Vcc decoupling that was

incorporated into BM devices has also been

implemented in the FT2232C device.

•

USB 2.0 (full speed option)

An EEPROM based option allows the FT2232C to

return a USB 2.0 device descriptor as opposed to

USB 1.1. Note : The device would be a USB 2.0 Full

Speed device (12Mb/s) as opposed to a USB 2.0

High Speed device (480Mb/s).

Baud Rate Pre-Scaler Divisors

The FT2232C (UART mode) baud rate pre-scaler

supports division by (n+0), (n+0.125), (n+0.25),

(n+0.375), (n+0.5), (n+0.625), (n+0.75) and (n+0.875)

where n is an integer between 2 and 16,384 (2¹⁴).

DS2232C Version 1.2

Page 4 of 54

FT2232C Dual USB UART / FIFO I.C.

In addition to the BM chip features, the FT2232C incorporates the following new features and interface modes :-

•

Enhanced Asynchronous Bit-Bang Interface

The FT2232C supports FTDI’s BM chip Bit Bang

mode. In Bit Bang mode, the eight FIFO data lines

can be switched between FIFO interface mode and

an 8-bit Parallel IO port. Data packets can be sent

to the device and they will be sequentially sent to

the interface at a rate controlled by an internal timer

(equivalent to the baud rate prescaler). With the

FT2232C device this mode has been enhanced

so that the internal RD# and WR# strobes are now

brought out of the device which can be used to allow

external logic to be clocked by accesses to the Bit-

Bang IO bus.

can be conﬁgured for different industry standards, or

proprietary bus protocols. For instance, it is possible

to connect one of the FT2232C’s channels to an

SRAM conﬁgurable FPGA as supplied by vendors

such as Altera and Xilinx. The FPGA device would

normally be un-conﬁgured (i.e. have no deﬁned

function) at power-up. Application software on the PC

could use the MPSSE to download conﬁguration data

to the FPGA over USB. This data would deﬁne the

hardware’s function on power up. The other FT2232

channel would be available for other devices.

This approach would allow a customer to create a

“generic” USB peripheral, who’s hardware function

can be deﬁned under control of the application

software. The FPGA based hardware could be easily

upgraded or totally changed simply by changing the

FPGA conﬁguration data ﬁle. (See FTDI’s MORPH-

IC development module for a practicle example,

www.morph-ic.com)

•

Synchronous Bit-Bang Interface

Synchronous Bit-Bang Mode differs from

Asynchronous Bit-Bang mode in that the device

is only read when it is written to. Thus making it

easier for the controlling program to measure the

response to an output stimulus as the data returned

is synchronous to the output data.

•

MCU Host Bus Emulation

This new mode combines the ‘A’ and ‘B’ bus interface

to make the FT2232C interface emulate a standard

8048 / 8051 style MCU bus. This allows peripheral

devices for these MCU families to be directly

attached to the FT2232C with IO being performed

over USB with the help of MPSSE interface

technology.

High Output Drive Level Capabillity

The IO interface pins can be made to drive out at

three times the standard drive level thus allowing

multiple devices, or devices that require a greater

drive strength to be interfaced to the FT2232C. This

option is conﬁgured in the external EEPROM, ad can

be set individually for each channel.

•

Fast Opto-Isolated Serial Interface

CPU-Style FIFO Interface

A new proprietary FTDI protocol is designed to

allow galvanically isolated devices to communicate

sychronously with the FT2232C using just 4 signal

wires (over two dual opto-isolators), and two power

lines. The peripheral circuitry controls the data

transfer rate in both directions, whilst maintaining

full data integrity. Maximum USB full speed data

rates can be acheived. Both ‘A’ and ‘B’ channels

can communicate over the same 4 wire interface if

desired.

The CPU style FIFO interface is essentially the same

function as the classic FT245 interface, however the

bus signals have been redeﬁned to make them easier

to interface to a CPU bus.

•

Multi-Protocol Synchronous Serial Engine

Interface (M.P.S.S.E.)

The Multi-Protocol Synchronous Serial Engine

(MPSSE) interface is a new option designed to

interface efﬁciently with synchronous serial protocols

such as JTAG and SPI Bus. It is very ﬂexible in that it

DS2232C Version 1.2

Page 5 of 54

FT2232C Dual USB UART / FIFO I.C.

3.0 Simpliﬁed Block Diagram

PWREN#

ADBUS0

Baud Rate

Generator

48MHz

Channel A

ADBUS1

ADBUS2

VCC

PWRCTL

ADBUS3

ADBUS4

Dual Port TX

Buffer

128 bytes

ADBUS5

ADBUS6

ADBUS7

Multi-

Purpose

UART / FIFO

Controller

3.3 Volt

LDO

Regulator

3V3OUT

Dual Port RX

Buffer

ACBUS0

ACBUS1

384 Bytes

ACBUS2

ACBUS3

USBDP

USBDM

SI/WUA

Serial Interface

Engine

USB

Transceiver

USB

Protocol Engine

( SIE )

BDBUS0

BDBUS1

BDBUS2

Channel B

Dual Port TX

Buffer

128 bytes

BDBUS3

BDBUS4

Multi-

Purpose

UART / FIFO

Controller

BDBUS5

BDBUS6

BDBUS7

USB DPLL

Dual Port RX

Buffer

384 Bytes

BCBUS0

BCBUS1

BCBUS2

BCBUS3

XTOUT

XTIN

48MHz

12MHz

Baud Rate

Generator

6MHZ

Oscillator

x8 Clock

Multiplier

48MHz

SI/WUB

3V3OUT

TEST

GND

EECS

EESK

EEPROM

Interface

RESET

GENERATOR

RSTOUT#

RESET#

EEDATA

Figure 1 - FT2232C Simpliﬁed Block Diagram

3.1 Functional Block Descriptions

•

USB Transceiver

•

3.3V LDO Regulator

The USB Transceiver Cell provides the USB 1.1 /

USB 2.0 full-speed physical interface to the USB

cable. The output drivers provide 3.3 volt level slew

rate control signalling, whilst a differential receiver

and two single ended receivers provide USB data

in, SEO and USB Reset condition detection.

The 3.3V LDO Regulator generates the 3.3 volt

reference voltage for driving the USB transceiver

cell output buffers. It requires an external

decoupling capacitor to be attached to the 3V3OUT

regulator output pin. It also provides 3.3V power to

the RSTOUT# pin. The main function of this block

is to power the USB Transceiver and the Reset

Generator Cells rather than to power external logic.

However, external circuitry requiring 3.3V nominal

at a current of not greater than 5mA could also

draw its power from the 3V3OUT pin if required.

•

USB DPLL

The USB DPLL cell locks on to the incoming NRZI

USB data and provides separate recovered clock

and data signals to the SIE block.

DS2232C Version 1.2

Page 6 of 54

FT2232C Dual USB UART / FIFO I.C.

•

6MHz Oscillator

and receive registers. When conﬁgured as a

UART it performs asynchronous 7 / 8 bit Parallel

to Serial and Serial to Parallel conversion of the

data on the RS232 (RS422 and RS485) interface.

Control signals supported by UART mode include

RTS, CTS, DSR , DTR, DCD and RI. There

are also transmitter enable control signal pins

(TXDEN) provided to assist with interfacing to

RS485 transceivers. RTS/CTS, DSR/DTR and

Xon/Xoff handshaking options are also supported.

Handshaking, where required, is handled in

hardware to ensure fast response times. The

UART’s also supports the RS232 BREAK setting

and detection conditions.

The 6MHz Oscillator cell generates a 6MHz

reference clock input to the x8 Clock multiplier from

an external 6MHz crystal or ceramic resonator.

x8 Clock Multiplier

The x8 Clock Multiplier takes the 6MHz input

from the Oscillator cell and generates a 48MHz

reference clock for the USB DPPL and the Baud

Rate Generator blocks.

•

Serial Interface Engine (SIE)

The Serial Interface Engine (SIE) block performs

the Parallel to Serial and Serial to Parallel

conversion of the USB data. In accordance to the

USB 2.0 speciﬁcation, it performs bit stufﬁng / un-

stufﬁng and CRC5 / CRC16 generation / checking

on the USB data stream.

•

Baud Rate Generator

The Baud Rate Generator provides a x16 clock

input to the UART’s from the 48MHz reference

clock and consists of a 14 bit prescaler and 3

register bits which provide ﬁne tuning of the baud

rate (used to divide by a number plus a fraction).

This determines the Baud Rate of the UART which

is programmable from 183 baud to 3 million baud.

•

USB Protocol Engine

The USB Protocol Engine manages the data

stream from the device USB control endpoint. It

handles the low level USB protocol (Chapter 9)

requests generated by the USB host controller

and the commands for controlling the functional

parameters of the UART / FIFO controller blocks.

•

RESET Generator

The Reset Generator Cell provides a reliable

power-on reset to the device internal circuitry

on power up. An additional RESET# input and

RSTOUT# output are provided to allow other

devices to reset the FT2232C, or the FT2232C

to reset other devices respectively. During reset,

RSTOUT# is driven low, otherwise it drives out

at the 3.3V provided by the onboard regulator.

RSTOUT# can be used to control the 1.5K

pull-up on USBDP directly where delayed USB

enumeration is required. It can also be used to

reset other devices. RSTOUT# will stay high-

impedance for approximately 5ms after VCC

has risen above 3.5V AND the device oscillator is

running AND RESET# is high. RESET# should

be tied to VCC unless it is a requirement to reset

the device from external logic or an external reset

generator I.C.

•

Dual Port TX Buffers (128 bytes)

Data from the USB data out endpoint is stored

in the Dual Port TX buffer and removed from the

buffer to the transmit register under control of the

UART FIFO controller.

Dual Port RX Buffers (384 bytes)

Data from the UART / FIFO controller receive

register is stored in the Dual Port RX buffer prior

to being removed by the SIE on a USB request for

data from the device data in endpoint.

Multi-Purpose UART / FIFO Controllers

The Multi-purpose UART / FIFO controllers handle

the transfer of data between the Dual Port RX

and TX buffers and the UART / FIFO transmit

DS2232C Version 1.2

Page 7 of 54

FT2232C Dual USB UART / FIFO I.C.

•

EEPROM Interface

Power-Off and USB 2.0 descriptor modes.

The EEPROM should be a 16 bit wide

When used without an external EEPROM the

FT2232C be conﬁgured as a USB to dual serial

port device. Adding an external 93C46 (93C56

or 93C66) EEPROM allows each of the chip’s

channels to be independently conﬁgured as a

serial UART (232 mode), or a parallel FIFO (245

mode). The external EEPROM is used to enable

the CPU-style FIFO interface, and Fast Opto-

Isolated Serial interface modes. The external

EEPROM can also be used to customise the USB

VID, PID, Serial Number, Product Description

Strings and Power Descriptor value of the

FT2232C for OEM applications. Other parameters

controlled by the EEPROM include Remote Wake

Up, Isochronous Transfer Mode, Soft Pull Down on

conﬁguration such as a MicroChip 93LC46B or

equivalent capable of a 1Mb/s clock rate at VCC =

4.35V to 5.25V. The EEPROM is programmable-

on board over USB using a utility program available

from FTDI’s web site (www.ftdichip.com). This

allows a blank part to be soldered onto the PCB

and programmed as part of the manufacturing and

test process.

If no EEPROM is connected (or the EEPROM

is blank), the FT2232C will default to dual serial

ports. The device use its built-in default VID, PID

Product Description and Power Descriptor Value.

In this case, the device will not have a serial

number as part of the USB descriptor.

DS2232C Version 1.2

Page 8 of 54

FT2232C Dual USB UART / FIFO I.C.

4.0 Device Pin-Out

24

V

C

V

C

V

C

I

O

A

V

C

I

O

B

A

V

C

ADBUS0

ADBUS1

ADBUS2

ADBUS3

ADBUS4

ADBUS5

ADBUS6

ADBUS7

23

22

21

20

19

17

16

6

8

7

3V3OUT

USBDM

USBDP

15

13

12

11

10

48

37

36

ACBUS0

ACBUS1

ACBUS2

ACBUS3

SI/WUA

BDBUS4

BDBUS5

GND

EESK

EEDATA

VCC

1

5

4

RSTOUT#

RESET#

BDBUS6

BDBUS7

RESET#

RSTOUT#

3V3OUT

USBDP

FTDI

FT2232C

XXYY

40

39

38

37

36

35

33

32

VCCIOB

BCBUS0

BCBUS1

BDBUS0

BDBUS1

BDBUS2

BDBUS3

BDBUS4

BDBUS5

BDBUS6

BDBUS7

43

XTIN

USBDM

GND

SI/WUA

ACBUS3

ACBUS2

BCBUS2

BCBUS3

SI/WUB

GND

44

48

1

XTOUT

EECS

12

25

24

13

30

29

28

27

26

EESK

BCBUS0

BCBUS1

BCBUS2

BCBUS3

SI/WUB

2

EEDATA

TEST

47

A

G

N

D

G

N

D

G

N

D

G G

N N

D D

41

PWREN#

Figure 2

Pin-Out

Figure 3

Pin-Out

(LQFP-48 Package )

(Schematic Symbol )

DS2232C Version 1.2

Page 9 of 54

FT2232C Dual USB UART / FIFO I.C.

5.0 Pin Deﬁnitions

This section decribes the operation of the FT2232C pins. Common pins are deﬁned in the ﬁrst section, then the I/O

pins are deﬁned, by chip mode. More detailed descriptions of the operation of the I/O pins are provided in section 9.

5.1 Common Pins

The operation of the following FT2232C pins stay the same, regardless of the chip mode :-

USB INTERFACE GROUP

Pin#

Signal

Type

I/O

Description

7

8

USBDP

USBDM

USB Data Signal Plus ( Requires 1.5K pull-up to 3V3OUT or RSTOUT# )

USB Data Signal Minus

I/O

EEPROM INTERFACE GROUP

Pin#

48

1

Signal

EECS

Type

Description

I/O

EEPROM – Chip Select. Tri-State during device reset. **Note 1

EESK

OUTPUT Clock signal to EEPROM. Tri-State during device reset, else drives out. **Note 1

2

EEDATA

I/O

EEPROM – Data I/O Connect directly to Data-In of the EEPROM and to Data-

Out of the EEPROM via a 2.2K resistor. Also, pull Data-Out of the EEPROM

to VCC via a 10K resistor for correct operation. Tri-State during device reset.

**Note 1

MISCELLANEOUS SIGNAL GROUP

Pin#

4

Signal

Type

Description

RESET#

INPUT

Can be used by an external device to reset the FT2232C. If not required, tie to

VCC. **Note 1

5

RSTOUT#

OUTPUT Output of the internal Reset Generator. Drives low for 5.6 ms after VCC > 3.5V

and the internal clock starts up, then clamps it’s output to the 3.3V output of the

internal regulator. Taking RESET# low will also force RSTOUT# to drive low.

RSTOUT# is NOT affected by a USB Bus Reset.

47

41

TEST

INPUT

Puts device into I.C. test mode – must be tied to GND for normal operation.

PWREN#

OUTPUT Goes Low after the device is conﬁgured via USB, then high during USB suspend.

Can be used to control power to external logic using a P-Channel Logic Level

MOSFET switch. Enable the Interface Pull-Down Option in EEPROM when using

the PWREN# pin in this way.

43

44

XTIN

INPUT

Input to 6MHz Crystal Oscillator Cell. This pin can also be driven by an external

6MHz clock if required. Note : Switching threshold of this pin is VCC/2, so if

driving from an external source, the source must be driving at 5V CMOS level or

a.c. coupled to centre around VCC/2.

XTOUT

OUTPUT Output from 6MHz Crystal Oscillator Cell. XTOUT stops oscillating during USB

suspend, so take care if using this signal to clock external logic.

**Note 1 - During device reset, these pins are tri-state but pulled up to VCC via internal 200K resistors.

DS2232C Version 1.2

Page 10 of 54

FT2232C Dual USB UART / FIFO I.C.

POWER AND GND GROUP

Pin#

6

Signal

Type

Description

3V3OUT

OUTPUT 3.3 volt Output from the integrated L.D.O. regulator This pin should be

decoupled to GND using a 33nF ceramic capacitor in close proximity to the

device pin. It’s prime purpose is to provide the internal 3.3V supply to the

USB transceiver cell and the RSTOUT# pin. A small amount of current (<=

5mA) can be drawn from this pin to power external 3.3V logic if required.

3, 42

14

VCC

PWR

+4.35 volt to +5.25 volt VCC to the device core, LDO and non-UART / FIFO

controller interface pins.

VCCIOA

PWR

+3.0 volt to +5.25 volt VCC to the UART / FIFO A Channel interface pins

10..13, 15..17 and 19..24. When interfacing with 3.3V external logic in a bus

powered design connect VCCIO to a 3.3V supply generated from the USB

bus. When interfacing with 3.3V external logic in a self powered design

connect VCCIO to the 3.3V supply of the external logic. Otherwise connect

to VCC to drive out at 5V CMOS level.

31

VCCIOB

PWR

+3.0 volt to +5.25 volt VCC to the UART / FIFO B Channel interface pins

26..30, 32..33 and 35..40. When interfacing with 3.3V external logic in a bus

powered design connect VCCIO to a 3.3V supply generated from the USB

bus. When interfacing with 3.3V external logic in a self powered design

connect VCCIO to the 3.3V supply of the external logic. Otherwise connect

to VCC to drive out at 5V CMOS level.

9,18, 25, 34 GND

PWR

Device - Ground Supply Pins

46

AVCC

Device - Analog Power Supply for the internal x8 clock multiplier. A low pass

ﬁlter consisting of a 470 Ohm series resistor and a 100 nF to GND should be

used on the supply to this pin.

45

AGND

PWR

Device - Analog Ground Supply for the internal x8 clock multiplier

DS2232C Version 1.2

Page 11 of 54

FT2232C Dual USB UART / FIFO I.C.

5.2 IO Pin Deﬁnitions by Chip Mode

The FT2232C will default to dual serial mode (232 UART mode on both channel A and B, if no external EEPROM is

used, or the external EEPROM is blank. The deﬁnition of the following pins vary according to the chip’s mode :-

Channel A

Pin Deﬁnitions by Chip Mode **Note 2

Enhanced

Fast

Opto-

Host Bus Isolated

Emulation Serial

Generic

Name

232 UART 245 FIFO CPU FIFO Asynchronous

MPSSE

**Note 4

MCU

Pin#

Mode

Interface

Mode

and

Synchronous

Bit-Bang Modes

Mode

**Note 5

24

23

22

21

20

19

17

16

15

13

12

11

10

ADBUS0 TXD

D0

TCK/SK

TDI/D0

AD0

**Note 3

ADBUS1 RXD

ADBUS2 RTS#

ADBUS3 CTS#

ADBUS4 DTR#

ADBUS5 DSR#

ADBUS6 DCD#

ADBUS7 RI#

D1

AD1

D2

TDO/DI

TMS/CS

GPIOL0

GPIOL1

GPIOL2

GPIOL3

GPIOH0

GPIOH1

GPIOH2

GPIOH3

**Note 8

AD2

D3

AD3

D4

AD4

D5

AD5

D6

AD6

D7

AD7

ACBUS0 TXDEN

ACBUS1 SLEEP#

ACBUS2 RXLED#

ACBUS3 TXLED#

RXF#

TXE#

RD#

WR

SI/WUA

CS#

A0

WR# **Note 6

RD# **Note 6

WR# **Note 7

RD# **Note 7

SI/WUA

I/O0

I/O1

RD#

WR#

**Note 8

IORDY

OSC

**Note 8

SI/WUA

**Note 2 : 232 UART, 245 FIFO, CPU FIFO Interface, and Fast Opto-Isolated modes are enabled in the external

EEPROM. Enhanced Asynchronous and Synchronous Bit-Bang modes, MPSSE, and MCU Host Bus Emulation

modes are enabled using the driver command set bit mode. See Section 5.2 for details.

**Note 3 : Channel A can be conﬁgured in another IO mode if channel B is in Fast Opto-Isolated Serial Mode. If both

Channel A and Channel B are in Fast Opto-Isolated Serial Mode all of the IO will be on Channel B.

**Note 4 : MPSSE is Channel A only.

**Note 5 : MCU Host Bus Emulation requires both Channels.

**Note 6 : The Bit-Bang Mode (synchronous and asynchronous) WR# and RD# strobes are on these pins when the

main Channel mode is 245 FIFO, CPU FIFO interface, or Fast Opto-Isolated Serial Modes.

**Note 7 : The Bit-Bang Mode (synchronous and asynchronous) WR# and RD# strobes are on these pins when the

main Channel mode is 232 UART Mode.

**Note 8 : SI/WU is not available in these modes.

DS2232C Version 1.2

Page 12 of 54

FT2232C Dual USB UART / FIFO I.C.

Channel B

Pin Deﬁnitions by Chip Mode **Note 2

Enhanced

Fast

Opto-

Host Bus Isolated

Emulation Serial

Generic

Name

232 UART 245 FIFO CPU FIFO Asynchronous

MPSSE

**Note 4

MCU

Pin#

Mode

Interface

Mode

and

Synchronous

Bit-Bang Modes

Mode

**Note 5

40

39

38

37

36

35

33

32

30

29

28

27

26

BDBUS0 TXD

D0

AD8

FSDI

BDBUS1 RXD

BDBUS2 RTS#

BDBUS3 CTS#

BDBUS4 DTR#

BDBUS5 DSR#

BDBUS6 DCD#

BDBUS7 RI#

D1

AD9

FSCLK

FSDO

D2

AD10

AD11

AD12

AD13

AD14

AD15

CS#

D3

FSCTS

**Note 3

D4

D5

D6

D7

BCBUS0 TXDEN

BCBUS1 SLEEP#

BCBUS2 RXLED#

BCBUS3 TXLED#

RXF#

TXE#

RD#

WR

SI/WUB

CS#

A0

WR# **Note 9

RD# **Note 9

WR# **Note 7

RD# **Note 7

SI/WUB

ALE

RD#

WR#

**Note 8

RD#

WR#

**Note 8

SI/WUB

**Note 8

SI/WUB

**Note 2 : 232 UART, 245 FIFO, CPU FIFO Interface, and Fast Opto-Isolated modes are enabled in the external

EEPROM. Enhanced Asynchronous and Synchronous Bit-Bang modes, MPSSE, and MCU Host Bus Emulation

modes are enabled using the driver command set bit mode. See Section 5.2 for details.

**Note 3 : Channel A can be conﬁgured in another IO mode if channel B is in Fast Opto-Isolated Serial Mode. If both

Channel A and Channel B are in Fast Opto-Isolated Serial Mode all of the IO will be on Channel B.

**Note 4 : MPSSE is Channel A only.

**Note 5 : MCU Host Bus Emulation requires both Channels.

**Note 6 : The Bit-Bang Mode (synchronous and asynchronous) WR# and RD# strobes are on these pins when the

main Channel mode is 245 FIFO, CPU FIFO interface, or Fast Opto-Isolated Serial Modes.

**Note 7 : The Bit-Bang Mode (synchronous and asynchronous) WR# and RD# strobes are on these pins when the

main Channel mode is 232 UART Mode.

**Note 8 : SI/WU is not available in these modes.

**Note 9 : The Bit-Bang Mode (synchronous and asynchronous) WR# and RD# strobes are on these pins when the

main Channel mode is 245 FIFO, CPU FIFO interface. Bit-Bang mode is not available on Channel B when Fast Opto-

Isolated Serial Mode is enabled.

DS2232C Version 1.2

Page 13 of 54

FT2232C Dual USB UART / FIFO I.C.

5.3 IO Mode Command Hex Values

Enhanced Asynchronous and Synchronous Bit-Bang modes, MPSSE, and MCU Host Bus Emulation modes are

enabled using the D2XX driver command FT_SetBitMode. The hex values used with this command to enable these

modes are as follows-

Mode

Value (hex)

Reset the IO bit Mode

Asynchronous Bit Bang Mode

MPSSE

0

1

2

Synchronous Bit bang Mode

MCU Host bus Emulation

Fast Opto-Isolated Serial Mode

4

8

10

See application note AN2232C-02 “Bit Mode Functions for the FT2232C” for more details and examples.

Note that all other device modes can be enabled in the external EEPROM, and do not require these values to be

conﬁgured.

In the case of Fast Opto-Isolated Serial mode sending a value of 10 will hold this device mode in reset, and sending a

value of 0 will release this mode from reset.

DS2232C Version 1.2

Page 14 of 54

FT2232C Dual USB UART / FIFO I.C.

6.0 Package Outline

Figure 4 - 48 LD LQFP Package Dimensions

9

7

PIN# 48

Pin# 1

FTDI

FT2232C

7

9

XXYY

0.22+/- 0.05

0.5

1.0

0.24 +/- 0.07

12^o+/- 1^o

0.09 Min

0.16 Max

0.09 Min

0.2 Max

0.25

0.22 +/- 0.05

0.05 Min

0.15 Max

0.2 Min

0.6 +/- 0.15

The FT2232C is supplied in a 48 LD LQFP package as standard. This package has a 7mm x 7mm body (9mm x 9mm

including leads) with leads on a 0.5mm pitch.

The above drawing shows the LQFP-48 package – all dimensions are in millimetres.

XXYY = Date Code ( XX = 1 or 2 digit year number, YY = 2 digit week number.

DS2232C Version 1.2

Page 15 of 54

FT2232C Dual USB UART / FIFO I.C.

7.0 Absolute Maximum Ratings

These are the absolute maximum ratings for the FT2232C device in accordance with the Absolute Maximum Rating System

(IEC 60134). Exceeding these may cause permanent damage to the device.

•

Storage Temperature …………………………………………………….............................. –65^oC to + 150^oC

Floor Life (Out of Bag) at Factory Ambient (30^oC/60% Relative Humidity)........................192 Hours **Note 10

(Level 3 Compliant)

•

Ambient Temperature (Power Applied)……………………….............................................. 0^oC to + 70^oC

VCC Supply Voltage ……………………………………………….................................….... -0.5V to +6.00V

DC Input Voltage - Inputs ………………………………………………................................. -0.5V to VCC + 0.5V

DC Input Voltage - High Impedance Bidirectionals …………………….............................. -0.5V to VCC + 0.5V

DC Output Current – Outputs ……………………………………………............................... 24mA

DC Output Current – Low Impedance Bidirectionals …………………................................ 24mA

Power Dissipation (VCC = 5.25V) .……………………………………...............................… 500mW

Electrostatic Discharge Voltage (Human Body Model) (I < 1μA) …………......................… +/- 3000V

Latch Up Current (Vi = +/- 10V maximum, for 10 ms) ……………………........................... +/-200mA

**Note 10 – If devices are stored out of the packaging beyond this time limit the devices should be baked before use.

The devices should be ramped up to a temperature of 110^oC and baked for 8 to 10 hours.

DS2232C Version 1.2

Page 16 of 54

FT2232C Dual USB UART / FIFO I.C.

7.1 D.C. Characteristics

DC Characteristics ( Ambient Temperature = 0 to 70^oC )

Operating Voltage and Current

Parameter Description

Min

4.35

3.0

-

Typ

5.0

-

Max

5.25

-

Units

V

Conditions

Vcc1

Vcc2

Icc1

Icc2

VCC Operating Supply Voltage

VCCIO Operating Supply Voltage

Operating Supply Current

V

30

mA

μA

Normal Operation

Operating Supply Current

-

100

200

USB Suspend **Note 11

**Note 11 – Supply current excludes the 200μA nominal drawn by the external pull-up resistor on USBDP.

IO Pin Characteristics ( VCCIO = 5.0V, Standard Drive Level ) **Note 12

Parameter Description

Min

3.2

0.3

1.3

50

Typ

4.1

0.4

1.6

55

Max

4.9

0.6

1.9

60

Units

V

Conditions

Voh

Vol

Output Voltage High

I source = 2mA

I sink = 2mA

Output Voltage Low

V

Vin

Input Switching Threshold

Input Switching Hysteresis

V

VHys

mV

IO Pin Characteristics ( VCCIO = 3.0 - 3.6V, Standard Drive Level ) **Note 12

Parameter Description

Min

2.2

0.3

1.0

20

Typ

2.7

0.4

1.2

25

Max

3.2

0.5

1.5

30

Units

V

Conditions

Voh

Vol

Output Voltage High

I source = 1 mA

I sink = 2 mA

Output Voltage Low

V

Vin

Input Switching Threshold

Input Switching Hysteresis

V

VHys

mV

IO Pin Characteristics ( VCCIO = 5.0V, High Drive Level ) **Note 12, **Note 13

Parameter Description

Min

3.2

0.3

1.3

50

Typ

4.1

0.4

1.6

55

Max

4.9

0.6

1.9

60

Units

V

Conditions

Voh

Vol

Output Voltage High

I source = 6 mA

I sink = 6 mA

Output Voltage Low

V

Vin

Input Switching Threshold

Input Switching Hysteresis

V

VHys

mV

IO Pin Characteristics ( VCCIO = 3.0 - 3.6V, High Drive Level ) **Note 12, **Note 13

Parameter Description

Min

2.2

0.3

1.0

20

Typ

2.8

0.4

1.2

25

Max

3.2

0.6

1.5

30

Units

V

Conditions

Voh

Vol

Output Voltage High

I source = 3mA

I sink = 8 mA

Output Voltage Low

V

Vin

Input Switching Threshold

Input Switching Hysteresis

V

VHys

mV

**Note 12 : Inputs have an internal 200K pull-up resistor to VCCIO, which can alternativly be programmed to pull

down using a conﬁguration bit in the external EEPROM.

**Note 12 : The high output drive level is conﬁgured in the external EEPROM. Each channel can be conﬁgured

individually.

DS2232C Version 1.2

Page 17 of 54

FT2232C Dual USB UART / FIFO I.C.

XTIN / XTOUT Pin Characteristics

Parameter Description

Min

4.0

0.1

1.8

Typ

Max

5.0

1.0

3.2

Units

Conditions

Fosc = 6MHz

Voh

Vol

Vin

Output Voltage High

Output Voltage Low

-

V

Input Switching Threshold

2.5

RESET#, TEST, EECS, EESK, EEDATA Pin Characteristics **Note 14

Parameter Description

Min

3.2

0.3

1.3

50

Typ

4.1

0.4

1.6

55

Max

4.9

0.6

1.9

60

Units

V

Conditions

Voh

Vol

Output Voltage High

I source = 2mA

I sink = 2 mA

Output Voltage Low

V

Vin

Input Switching Threshold

Input Switching Hysteresis

V

VHys

mV

**Note 14 – EECS, EESK, EEDATA and RESET# pins have an internal 200K pull-up resistor to VCC

RSTOUT# Pin Characteristics

Parameter Description

Min

3.0

0.3

Typ

Max

3.6

Units

Conditions

Voh

Vol

Output Voltage High

Output Voltage Low

-

V

I source = 2mA

I sink = 2mA

0.6

USB IO Pin Characteristics **Note 15

Parameter Description

Min

Typ

Max

Units Conditions

UVoh

IO Pins Static Output ( High)

2.8

3.6

V

RI = 1.5K to 3V3Out ( D+ )

RI = 15K to GND ( D- )

-

UVol

IO Pins Static Output ( Low )

0

0.3

V

RI = 1.5K to 3V3Out ( D+ )

RI = 15K to GND ( D- )

-

UVse

Single Ended Rx Threshold

Differential Common Mode

Differential Input Sensitivity

Driver Output Impedance

0.8

0.2

29

2.0

2.5

V

-

UCom

UVDif

UDrvZ

V

-

44

Ohm

**Note 15 – Driver Output Impedance includes the external 27R series resistors on USBDP and USBDM pins.

DS2232C Version 1.2

Page 18 of 54

FT2232C Dual USB UART / FIFO I.C.

8.0 Standard Device Conﬁguration Examples

8.1 Oscillator Conﬁgurations

FT2232C

27pF

43

XTIN

3-Pin Resonator

6MHz

2 - Pin Resonator

or Crystal

1M

6MHz

27pF

44

XTOUT

Figure 5

Figure 6

3-Pin Ceramic Resonator Conﬁguration

Crystal or 2-Pin Ceramic Resonator

Conﬁguration

Figure 5 illustrates how to use the FT2232C with a 3-Pin Ceramic Resonator. A suitable part would be a ceramic

resonator from Murata’s CERALOCK range. (Murata Part Number CSTCR6M00G15), or equivalent. 3-Pin ceramic

resonators have the load capacitors built into the resonator so no external loading capacitors are required. This makes

for an economical conﬁguration. The accuracy of this Murata ceramic resonator is +/- 0.25% and it is speciﬁcally

designed for USB full speed applications. A 1 MegaOhm loading resistor across XTIN and XTOUT is recommended in

order to guarantee this level of accuracy.

Other ceramic resonators with a lesser degree of accuracy (typically +/- 0.5%) are technically out-with the USB

speciﬁcation, but it has been calculated that using such a device will work satisfactorily in practice with a FT2232C

design. An example of such a device is Murata’s CSTLSM00G53.

Figure 6 illustrates how to use the FT2232C with a 6MHz Crystal or 2-Pin Ceramic Resonator. In this case, these

devices do not have in-built loading capacitors so these have to be added between XTIN, XTOUT and GND as

shown. A value of 27pF is shown as the capacitor in the example – this will be good for many crystals and some

resonators but do select the value based on the manufacturers recommendations wherever possible. If using a crystal,

use a parallel cut type. If using a resonator, see the previous note on frequency accuracy.

It is also possible to use a 6 MHz Oscillator with the FT2232C. In this case the output of the oscillator would be

connected to XTIN, and XTOUT should be left unconnected. The oscillator must have a CMOS output.

DS2232C Version 1.2

Page 19 of 54

FT2232C Dual USB UART / FIFO I.C.

8.2 EEPROM Conﬁguration

Figure 7 illustrates how to connect the FT2232C to the

93C46 (93C56 or 93C66) EEPROM. EECS (pin 48) is directly

connected to the chip select (CS) pin of the EEPROM. EESK

(pin 1) is directly connected to the clock (SK) pin of the

EEPROM. EEDATA (pin 2) is directly connected to the Data

In (Din) pin of the EEPROM. There is a potential condition

whereby both the Data Output (Dout) of the EEPROM can drive

out at the same time as the EEDATA pin of the FT2232C. To

prevent potential data clash in this situation, the Dout of the

EEPROM is connected to EEDATA of the FT2232C via a 2.2K

resistor.

FT2232C

48

1

EECS

EESK

2

EEDATA

VCC

EEPROM - 93C46 / 56 / 66

Following a power-on reset or a USB reset, the FT2232C will

scan the EEPROM to ﬁnd out (a) if an EEPROM is attached to

the Device and (b) if the data in the device is valid. If both of

these are the case, then the FT2232C will use the data in the

EEPROM, otherwise it will use its built-in default values and

conﬁguration. The default port conﬁguration of the FT2232C

puts both Channel A and Channel B into serial UART mode.

1

8

7

6

5

CS

VCC

NC

2

3

SK

2.2K

DIN

DOUT

NC

4

GND

When a valid command is issued to the EEPROM from the

FT2232C, the EEPROM will acknowledge the command by

pulling its Dout pin low. In order to check for this condition,

it is necessary to pull Dout high using a 10K resistor. If the

command acknowledge doesn’t happen then EEDATA will be

pulled high by the 10K resistor during this part of the cycle

and the device will detect an invalid command or no EEPROM

present.

VCC

10K

Figure 7

EEPROM Conﬁguration

There are two varieties of 93C46/56/66 EEPROM’s on the market – one is conﬁgured as being 16 bits wide, the other

is conﬁgured as being 8 bits wide. These are available from many sources such as Microchip, STMicro, ISSI etc. The

FT2232C requires EEPROM’s with a 16-bit wide conﬁguration such as the Microchip 93LC46B device. The EEPROM

must be capable of reading data at a 1Mb clock rate at a supply voltage of 4.35V to 5.25V. Most available parts are

capable of this. Check the manufacturers data sheet to ﬁnd out how to connect pins 6 and 7 of the EEPROM. Some

devices specify these as no-connect, others use them for selecting 8 / 16 bit mode or for test functions. Some other

parts have their pinout rotated by 90^oso please select the required part and its options carefully.

It is possible to “share” the EEPROM between the FT2232C and another external device such as an MCU. However,

this can only be done when the FT2232C is in its reset condition as it tri-states its EEPROM interface at that time. A

typical conﬁguration would use four bits of an MCU IO Port. One bit would be used to hold the FT2232C reset (using

RESET#) on power-up, the other three would connect to the EECS, EESK and EEDATA pins of the FT2232C in

order to read / write data to the EEPROM at this time. Once the MCU has read / written the EEPROM, it would take

RESET# high to allow the FT2232C to conﬁgure itself and enumerate over USB.

The external EEPROM can be programmed over USB using utility software provided by FTDI. The external EEPROM

is used to enable 245 FIFO, CPU-Style FIFO, and Fast Opto-Isolated Serial interface modes on each channel.

DS2232C Version 1.2

Page 20 of 54

FT2232C Dual USB UART / FIFO I.C.

8.3 USB Bus Powered and Self Powered Conﬁguration

Figure 8 - USB Bus Powered Conﬁguration

Ferrite Bead

470R

USB "B"

Connector

VCC

1

27R

0.1uF

2

3

42

14 31

46

V

C

V

C

A

V

C

V

C

I

V

27R

4

C

I

6

5

10nF

3v3OUT

O

A

O

A

33nF

8

7

USB DM

USB DP

1.5K

FT2232C

RSTOUT#

5

43

XTIN

6MHz

44

XTOUT

VCC

4

27pF

10K

27pF

RESET#

48

EECS

1

2

EESK

VCC

EEDATA

A

G

N

D

47

G

N

D

G

N

D

G

N

D

G

N

D

+

TEST

0.1uF

10uF

45

9

18 25 34

Decoupling Capacitors

Figure 8 illustrates the FT2232C in a typical USB bus powered conﬁguration. A USB Bus Powered device gets its

power from the USB bus. Basic rules for USB Bus power devices are as follows –

a) On plug-in, the device must draw no more than 100mA

b) On USB Suspend the device must draw no more than 500μA.

c) A High Power USB Bus Powered Device (one that draws more than 100mA) should use the PWREN# pin to keep

the current below 100mA on plug-in and 500μA on USB suspend.

d) A device that consumes more than 100mA can not be plugged into a USB Bus Powered Hub

e) No device can draw more that 500mA from the USB Bus.

The power descriptor in the EEPROM should be programmed to match the current draw required by the device.

A Ferrite Bead is connected in series with USB power to prevent noise from the device and associated circuitry (EMI)

being radiated down the USB cable to the Host. The value of the Ferrite Bead depends on the total current required

by the circuit – a suitable range of Ferrite Beads is available from Steward (www.steward.com) for example Steward

Part # MI0805K400R-00 also available from DigiKey, Part # 240-1035-1.

DS2232C Version 1.2

Page 21 of 54

FT2232C Dual USB UART / FIFO I.C.

Figure 9 - USB Self Powered Conﬁguration

470R

USB "B"

VCC

Connector

1

27R

0.1uF

46

2

3

42

14 31

V

C

V

C

V

C

I

V

A

V

C

27R

4

C

I

6

3v3OUT

O

A

O

B

33nF

4.7K

10K

8

7

USB DM

USB DP

FT2232C

1.5K

5

RSTOUT#

RESET#

VCC

4

A

47

G

N

D

G

N

D

G

N

D

G

N

D

G

N

D

TEST

+

0.1uF

10uF

45

9 18 25 34

Decoupling Capacitors

Figure 9 illustrates the FT2232C in a typical USB self powered conﬁguration. A USB Self Powered device gets its

power from its own POWER SUPPLY and does not draw current from the USB bus. The basic rules for USB Self

power devices are as follows –

a) A Self-Powered device should not force current down the USB bus when the USB Host or Hub Controller is

powered down.

b) A Self Powered Device can take as much current as it likes during normal operation and USB suspend as it has its

own POWER SUPPLY.

c) A Self Powered Device can be used with any USB Host and both Bus and Self Powered USB Hubs.

The USB power descriptor option in the EEPROM should be programmed to a value of zero (self powered).

To meet requirement a) the 1.5K pull-up resistor on USBDP is connected to RSTOUT# as per the bus-power circuit.

However, the USB Bus Power is used to control the RESET# Pin of the FT2232C device. When the USB Host or

Hub is powered up RSTOUT# will pull the 1.5K resistor on USBDP to 3.3V, thus identifying the device as a full speed

device to USB. When the USB Host or Hub power is off, RESET# will go low and the device will be held in reset. As

RESET# is low, RSTOUT# will also be low, so no current will be forced down USBDP via the 1.5K pull-up resistor

when the host or hub is powered down. Failure to do this may cause some USB host or hub controllers to power up

erratically.

Note : When the FT2232C is in reset, the I/O interface pins all go tri-state. These pins have internal 200K pull-up

resistors to VCCIO, so they will gently pull high unless driven by some external logic.

DS2232C Version 1.2

Page 22 of 54

FT2232C Dual USB UART / FIFO I.C.

8.4 Interfacing to 3.3V Logic

Figure 10 - Bus Powered Circuit with 3.3V logic drive and IO supply voltage

3.3V LDO

Regulator

VCC3V3

3.3V Power to

External Logic

In

Out

Gnd

0.1uF

Ferrite Bead

27R

470R

VCC

1

2

3

4

42

31

14

3

46

0.1uF

USB "B"

V

C

V

C

V

C

I

A

27R

Connector

C

I

V

C

33nF

6

VCC3V3

10nF

3v3OUT

O

A

O

B

8

7

USB DM

USB DP

10

SI/WUA

VCC

FT2232C

1.5K

VCC3V3

+

5

RSTOUT#

0.1uF

10uF

VCC

26

SI/WUB

Decoupling

Capacitors

4

RESET#

A

G

N

D

G

N

D

G

N

D

G

N

D

G

N

47

TEST

D

45

9

18 25 34

Figure 10 shows how to conﬁgure the FT2232C to interface with a 3.3V logic devices. In this example, a discrete 3.3V

regulator is used to supply the 3.3V logic from the USB supply. VCCIOA and VCCIOB are connected to the output of

the 3.3V regulator, which in turn will cause the device interface IO pins on both channels to drive out at 3.3V level. It is

also possible to have one IO interface channel driving out at 5V level, and the other at 3.3V level. In this case one of

the VCCIO pins would be connected to 5V, and the other connected to 3.3V.

For USB bus powered circuits some considerations have to be taken into account when selecting the regulator –

a) The regulator must be capable of sustaining its output voltage with an input voltage of 4.35 volts. A Low Drop Out

(LDO) regulator must be selected.

b) The quiescent current of the regulator must be low in order to meet the USB suspend total current requirement of

<= 500μA during USB suspend.

An example of a regulator family that meets these requirements is the MicroChip (Telcom) TC55 Series. These

devices can supply up to 250mA current and have a quiescent current of under 1μA.

DS2232C Version 1.2

Page 23 of 54

FT2232C Dual USB UART / FIFO I.C.

In some cases, where only a small amount of current is required (< 5mA) , it may be possible to use the in-built

regulator of the FT2232C to supply the 3.3V without any other components being required. In this case, connect

VCCIOA or VCCIOB to the 3V3OUT pin of the FT2232C.

Note : It should be emphasised that the 3.3V supply for VCCIO in a bus powered design with a 3.3V logic interface

should come from an LDO which is supplied by the USB bus, or from the 3V3OUT pin of the FT232BM, and not from

any other source. Please also note that if the SI/WU pins are not being used they should be pulled up to the same

supply as their respective VCCIO pin.

Figure 11 - Self Powered Circuit with 3.3V logic drive and IO supply voltage

VCC3V3

470R

VCC5V

USB "B"

Connector

1

27R

0.1uF

3

42 14 31

V

2

3

4

46

V

C

A

V

C

V

C

I

27R

C

I

C

6

VCC3V3

O

B

O

A

3v3OUT

33nF

10

SI/WUA

4.7K

8

7

USB DM

USB DP

FT2232C

10K

1.5K

VCC3V3

5

RSTOUT#

RESET#

VCC5V

26

SI/WUB

4

A

47

G

N

D

G

N

D

G

N

D

G

N

D

G

N

D

TEST

+

0.1uF

10uF

25 34

9 18

45

Decoupling Capacitors

Figure 11 is an example of a FT2232C USB self powered design with 3.3V interface. In this case the VCCIOA and

VCCIOB pins are supplied by an external 3.3V supply in order to make both of the device’s IO channels drive out at

3.3V logic level, thus allowing them to be connected to a 3.3V MCU or other external logic. It is also possible to have

one IO interface channel driving out at 5V level, and the other at 3.3V level. In this case one of the VCCIO pins would

be connected to 5V, and the other connected to 3.3V.

DS2232C Version 1.2

Page 24 of 54

FT2232C Dual USB UART / FIFO I.C.

A USB self powered design uses its own power supplies, and does not draw any of its power from the USB bus. In

such cases, no special care need be taken to meet the USB suspend current (0.5 mA) as the device does not get its

power from the USB port.

As with bus powered 3.3V interface designs, in some cases, where only a small amount of current is required (<5mA),

it may be possible to use the in-built regulator of the FT2232C to supply the 3.3V without any other components being

required. In this case, connect VCCIOA or VCCIOB to the 3V3OUT pin of the FT2232C.

Note that if the SI/WU pins are not being used they should be pulled up to the same supply as their respective VCCIO

pin.

DS2232C Version 1.2

Page 25 of 54

FT2232C Dual USB UART / FIFO I.C.

8.5 Power Switching

Figure 12 - Bus Powered Circuit with Power Control

P-Channel Power

MOSFET

Switched 5V Power to

External Logic

s

d

0.1uF

g

0.1uF

Soft Start

Circuit

1K

Ferrite Bead

27R

470R

USB "B"

Connector

VCC

1

2

3

4

0.1uF

46

3

42 14 31

V

C

V

C

V

C

I

V

C

I

A

27R

V

C

6

10nF

3V3OUT

O

A

O

B

33nF

FT2232C

8

7

USB DM

USB DP

VCC

41

PWREN#

+

1.5K

0.1uF

10uF

5

4

RSTOUT#

RESET#

Decoupling Capacitors

VCC

USB Bus powered circuits need to be able to power down in USB suspend mode in order to meet the <= 500μA total

suspend current requirement (including external logic). Some external logic can power itself down into a low current

state by monitoring the PWREN# pin. For external logic that cannot power itself down in that way, the FT2232C

provides a simple but effective way of turning off power to external circuitry during USB suspend.

Figure 12 shows how to use a discrete P-Channel Logic Level MOSFET to control the power to external logic circuits.

A suitable device would be an International Rectiﬁer (www.irf.com) IRLML6402, or equivalent. It is recommended that

a “soft start” circuit consisting of a 1K series resistor and a 0.1 μF capacitor are used to limit the current surge when

the MOSFET turns on. Without the soft start circuit there is a danger that the transient power surge of the MOSFET

turning on will reset the FT2232C, or the USB host / hub controller. The values used here allow attached circuitry to

power up with a slew rate of ~12.5 V per millisecond, in other words the output voltage will transition from GND to 5V

in approximately 400 microseconds.

DS2232C Version 1.2

Page 26 of 54

FT2232C Dual USB UART / FIFO I.C.

Alternatively, a dedicated power switch I.C. with inbuilt “soft-start” can be used instead of a MOSFET. A suitable

power switch I.C. for such an application would be a Micrel (www.micrel.com) MIC2025-2BM or equivalent.

Please note the following points in connection with power controlled designs –

a) The logic to be controlled must have its own reset circuitry so that it will automatically reset itself when power is re-

applied on coming out of suspend.

b) Set the Pull-down on Suspend option in the FT2232C’s EEPROM.

c) For USB high-power bus powered device (one that consumes greater than 100 mA, and up to 500 mA of current

from the USB bus), the power consumption of the device should be set in the max power ﬁeld in the EEPROM.

A high-power bus powered device must use this descriptor in the EEPROM to inform the system of its power

requirements.

d) For 3.3V power controlled circuits the VCCIO pins must not be powered down with the external circuitry. Either

connect the power switch between the output of the 3.3V regulator and the external 3.3V logic, or if appropriate

power the VCCIO pin from the 3V3OUT pin of the FT2232C.

Figure 13 - Bus Powered Circuit with Power Control and 3.3V Logic Drive / IO Supply

Voltage

3.3V LDO

Regulator

Switched 3.3V Power

to External Logic

P-Channel Power

MOSFET

VCC3V3

s

d

IN

OUT

GND

0.1uF

g

0.1uF

Soft Start

1K

Circuit

Ferrite

Bead

470R

USB "B"

VCC5V

Connector

1

2

3

4

27R

0.1uF

3

V

C

42 14 31

46

V

C

V

C

I

V

C

I

A

V

C

6

10nF

3V3OUT

VCC3V3

O

A

O

B

33nF

FT2232

10

26

SI/WUA

SI/WUB

8

7

USB DM

USB DP

VCC5V

+

1.5K

0.1uF

10uF

5

4

RSTOUT#

RESET#

Decoupling Capacitors

VCC5V

41

PWREN#

Figure 13 is a FT2232C design example which effectively combines the circuits shown in Figures 13 and 14 to give a

USB bus powered design with power switching and 3.3V logic drive level on both channels. Once again a P-Channel

Power MOSFET and soft start circuit are used to control the power to external logic devices. A 3.3V LDO regulator

which is supplied by the USB bus is used to provide the 3.3V supply for the VCCIO pins, as well as the external logic.

If the SI/WU pins are not being used they should be pulled up to 3.3V.

DS2232C Version 1.2

Page 27 of 54

FT2232C Dual USB UART / FIFO I.C.

9.0 Signal Descriptions By IO Mode and Interface Channel Conﬁgurations

9.1 232 UART Interface Mode Signal Descriptions and Interface Conﬁgurations

When either Channel A or Channel B are in 232 UART mode the IO signal lines are conﬁgured as follows:-

Pin#

Signal

Type

Description

Channel A Channel B

24

23

22

21

20

19

17

16

40

39

38

37

36

35

33

32

TXD

OUTPUT Transmit Asynchronous Data Output

INPUT Receive Asynchronous Data Input **Note 16

OUTPUT Request To Send Control Output / Handshake signal

INPUT Clear To Send Control Input / Handshake signal **Note 16

OUTPUT Data Terminal Ready Control Output / Handshake signal

RXD

RTS#

CTS#

DTR#

DSR#

DCD#

RI#

INPUT

Data Set Ready Control Input / Handshake signal **Note 16

Data Carrier Detect Control Input **Note 16

Ring Indicator Control Input. When the Remote Wake up option

is enabled in the EEPROM, taking RI# low can be used to

resume the PC USB Host controller from suspend. **Note 16

15

13

30

29

TXDEN OUTPUT Enable Transmit Data for RS485

SLEEP# OUTPUT Goes low during USB Suspend Mode. Typically used to power-

down an external TTL to RS232 level converter I.C. in USB to

RS232 converter designs.

12

11

10

28

27

26

RXLED# O.C.

TXLED# O.C

LED Drive - Pulses Low when Transmitting Data via USB.

LED Drive - Pulses Low when Receiving Data via USB.

SI/WU

INPUT

The Send Immediate / WakeUp signal combines two functions

on a single pin. If USB is in suspend mode (PWREN# = 1) and

remote wakeup is enabled in the EEPROM , strobing this pin

low will cause the device to request a resume on the USB Bus.

Normally, this can be used to wake up the Host PC.

During normal operation (PWREN# = 0), if this pin is strobed low

any data in the device TX buffer will be sent out over USB on the

next Bulk-IN request from the drivers regardless of the pending

packet size. This can be used to optimise USB transfer speed for

some applications. Tie this pin to VCCIO if not used.

**Note 16 : These pins are pulled to up VCCIO via internal 200K resistors during Reset and USB Suspend mode.

These can be programmed to gently pull low during USB suspend ( PWREN# = “1” ) by setting this option in the

EEPROM.

DS2232C Version 1.2

Page 28 of 54

FT2232C Dual USB UART / FIFO I.C.

Figure 14 - USB <=> Dual Port RS232 Converter Conﬁguration

VCC

Figure 14 illustrates how to connect the

FT2232C, when both channels A and B are

conﬁgured as 232-style UART interfaces, to

two TTL – RS232 Level Converter I.C.’s to

make a USB <=> Dual Port RS232 converter

using the popular “213” series of TTL to

RS232 level converters. These devices

have 4 transmitters and 5 receivers in a 28-

LD SSOP package and feature an in-built

voltage converter to convert the 5V (nominal)

VCC to the +/- 9 volts required by RS232.

An important feature of these devices is

the SHDN# pin which can power down the

device to a low quiescent current during USB

suspend mode.

SP213EHCA

FT2232C

SLEEP# (ACBUS1)

DB9-M

13

24

23

22

21

20

19

17

16

15

25

7

11

2

RS232 Channel A

SHDN#

VCC

T1Out

R4In

3

TXD (ADBUS0)

RXD (ADBUS1)

RTS# (ADBUS2)

RTS# (ADBUS3)

DTR# (ADBUS4)

DSR# (ADBUS5)

DCD# (ADBUS6)

RI# (ADBUS7)

T1In

TXD_A

22

20

8

2

23

1

R4Out

T3In

RXD_A

7

T3Out

R1In

RTS_A

9

8

R1Out

T2In

CTS_A

3

4

6

T2Out

R2In

DTR_A

5

4

6

R2Out

R3Out

R5Out

DSR_A

27

18

28

1

26

19

R3In

DCD_A

9

R5In

RI_A

21

12

5

TXDEN (ACBUS0)

GND

T4In

C1+

T4Out

C2+

15

0.1uF

14

17

0.1uF

16

C1-

C2-

V+

G

N

D

V

C

13

V-

0.1uF

VCC

11

10

The device used in the example above

is a Sipex SP213EHCA which is capable

of RS232 communication at up to 500K

baud. If a lower baud rate is acceptable,

then several pin compatible alternatives

are available such as the Sipex SP213ECA

, the Maxim MAX213CAI and the Analog

Devices ADM213E, which are all good for

communication at up to 115,200 baud. If a

higher baud rate is desired, use a Maxim

MAX3245CAI part which is capable of RS232

communication at rates of up to 1M baud.

The MAX3245 is not pin compatible with

the 213 series devices, also its SHDN pin is

active high, so connect it to PWREN# instead

of SLEEP#. Dual RS232 level converters

such as the Maxim MAX3187 may also be a

suitable alternative.

0.1uF

VCC

SP213EHCA

DB9-M

29

40

39

38

37

36

35

33

32

30

25

7

11

2

SLEEP# (BCBUS1)

TXD (BDBUS0)

RXD (BDBUS1)

RTS# (BDBUS2)

CTS# (BDBUS3)

DTR# (BDBUS4)

DSR# (BDBUS5)

DCD# (BDBUS6)

RI# (BDBUS7)

SHDN#

T1In

VCC

T1Out

R4In

RS232 Channel B

3

TXD_B

22

20

8

2

23

1

R4Out

T3In

RXD_B

7

RTS_B

T3Out

R1In

9

8

R1Out

T2In

CTS_B

3

6

4

T2Out

R2In

DTR_B

5

4

6

DSR_B

R2Out

R3Out

R5Out

27

18

28

1

26

19

DCD_B

R3In

9

RI_B

R5In

5

21

12

TXDEN (BCBUS0)

GND

T4In

C1+

T4Out

C2+

15

41

PWREN#

0.1uF

14

17

16

C1-

G

C2-

V+

V

C

13

V-

N

D

0.1uF

VCC

11

10

0.1uF

VCC

DS2232C Version 1.2

Page 29 of 54

FT2232C Dual USB UART / FIFO I.C.

Figure 15 - USB <=> RS422 Converter Conﬁguration

VCC

14 SP491

FT2232C

DB9-M

RS422 Channel A

41

13

4

PWREN#

10

9

TXDM_A

5

3

2

SLEEP# (ACBUS1)

D

TXDP_A

RXDP_A

24

23

22

21

20

19

17

16

15

TXD (ADBUS0)

RXD (ADBUS1)

RTS# (ADBUS2)

CTS# (ADBUS3)

DTR# (ADBUS4)

DSR# (ADBUS5)

DCD# (ADBUS6)

RI# (ADBUS7)

11

12

120R

R

RXDM_A

6

7

VCC

14 SP491

GND

4

10

9

RTSM_A

5

3

2

D

RTSP_A

CTSP_A

11

120R

R

12

CTSM_A

6

7

TXDEN (ACBUS0)

VCC

14 SP491

DB9-M

RS422 Channel B

4

29

40

39

38

37

36

35

33

32

30

SLEEP# (BCBUS1)

TXD (BDBUS0)

RXD (BDBUS1)

RTS# (BDBUS2)

CTS# (BDBUS3)

DTR# (BDBUS4)

DSR# (BDBUS5)

DCD# (BDBUS6)

RI# (BDBUS7)

10

9

TXDM_B

5

3

2

D

TXDP_B

RXDP_B

11

120R

R

12

RXDM_B

6

7

VCC

14 SP491

GND

4

10

9

RTSM_B

5

3

2

D

RTSP_B

CTSP_B

11

120R

R

12

TXDEN (BCBUS0)

CTSM_B

6

7

Figure 15 illustrates how to connect the UART interfaces of the FT2232C to two TTL – RS422 Level Converter I.C.’s

to make a USB to dual port RS422 converter. There are many such level converter devices available – this example

uses two Sipex SP491 devices which have enables on both their transmitters and receivers. Because the transmitter

enables are active high, they are connected to the SLEEP# pins. The receiver enables are active low and are both

connected to the PWREN# pin. This ensures that both the transmitters and receivers are enabled when the device

is active, and disabled when the device is in USB suspend mode. If the design is USB BUS powered, it may be

necessary to use a P-Channel logic level MOSFET (controlled by PWREN#) in the VCC line of the SP491 devices to

ensure that the USB standby current of 500μA is met.

The SP491 is good for sending and receiving data at a rate of up to 5M Baud – in this case the maximum rate is

limited to 3M Baud by the FT2232C.

DS2232C Version 1.2

Page 30 of 54

FT2232C Dual USB UART / FIFO I.C.

Figure 16 - USB <=> RS485 Converter Conﬁguration

DB9-M

RS485 Channel A

FT2232C

41

13

VCC

SP481

PWREN#

8

3

SLEEP# (ACBUS1)

7

6

DM_A

DPA

24

23

22

21

20

19

17

16

15

4

2

1

TXD (ADBUS0)

RXD (ADBUS1)

RTS# (ADBUS2)

CTS# (ADBUS3)

DTR# (ADBUS4)

DSR# (ADBUS5)

DCD# (ADBUS6)

RI# (ADBUS7)

D

R

GND

5

120R

LINK

TXDEN (ACBUS0)

DB9-M

RS485 Channel B

VCC

SP481

8

29

40

39

38

37

36

35

33

32

30

3

SLEEP# (BCBUS1)

TXD (BDBUS0)

RXD (BDBUS1)

RTS# (BDBUS2)

CTS# (BDBUS3)

DTR# (BDBUS4)

DSR# (BDBUS5)

DCD# (BDBUS6)

RI# (BDBUS7)

7

DM_B

DP_B

GND

4

2

1

D

6

R

5

120R

LINK

TXDEN (BCBUS0)

Figure 16 illustrates how to connect the UART interfaces of the FT2232C to two TTL – RS485 Level Converter I.C.’s

to make a USB to dual port RS485 converter. This example uses two Sipex SP491 devices but there are similar parts

available from Maxim and Analog Devices amongst others. The SP491 is a RS485 device in a compact 8 pin SOP

package. It has separate enables on both the transmitter and receiver. With RS485, the transmitter is only enabled

when a character is being transmitted from the UART. The TXDEN pins on the FT2232C are provided for exactly that

purpose, and so the transmitter enables are wired to the TXDEN’s. The receiver enable is active low, so it is wired to

the PWREN# pin to disable the receiver when in USB suspend mode.

RS485 is a multi-drop network – i.e. many devices can communicate with each other over a single two wire cable

connection. The RS485 cable requires to be terminated at each end of the cable. Links are provided to allow the cable

to be terminated if the device is physically positioned at either end of the cable.

In this example the data transmitted by the FT2232C is also received by the device that is transmitting. This is a

common feature of RS485 and requires the application software to remove the transmitted data from the received

data stream. With the FT2232C it is possible to do this entirely in hardware – simply modify the schematic so that RXD

of the FT2232C is the logical OR of the SP481 receiver output with TXDEN using an HC32 or similar logic gate.

DS2232C Version 1.2

Page 31 of 54

FT2232C Dual USB UART / FIFO I.C.

9.2 232 UART Mode LED Interface

VCCIO

LED

TX

RX

220R

FT2232C

TXLED#

RXLED#

TXLED#

RXLED#

Figure 17

Dual LED Conﬁguration

Figure 18

Single LED Conﬁguration

When conﬁgured in UART mode the FT2232C has two IO pins on each channel dedicated to controlling LED

status indicators, one for transmitted data the other for received data. When data is being transmitted / received

the respective pins drive from tri-state to low in order to provide indication on the LED’s of data transfer. A digital

one-shot timer is used so that even a small percentage of data transfer is visible to the end user. Figure 17 shows

a conﬁguration using two individual LED’s – one for transmitted data the other for received data. In Figure 18, the

transmit and receive LED indicators are wire-OR’ed together to give a single LED indicator which indicates any

transmit or receive data activity.

Another possibility (not shown here) is to use a 3 pin common anode tri-color LED based on the circuit in Figure 18 to

have a single LED that can display activity in a variety of colors depending on the ratio of transmit activity compared to

receive activity.

Note that the LED’s are connected to the same supply as VCCIO.

DS2232C Version 1.2

Page 32 of 54

FT2232C Dual USB UART / FIFO I.C.

9.3 245 FIFO Interface Mode Signal Descriptions and Conﬁguration

When either Channel A or Channel B are in 245 FIFO mode the IO signal lines are conﬁgured as follows.

FIFO DATA BUS GROUP **Note 17

Pin#

Signal

Type

Description

Channel A Channel B

24

23

22

21

20

19

17

16

40

39

38

37

36

35

33

32

D0

D1

D2

D3

D4

D5

D6

D7

I/O

FIFO Data Bus Bit 0

FIFO Data Bus Bit 1

FIFO Data Bus Bit 2

FIFO Data Bus Bit 3

FIFO Data Bus Bit 4

FIFO Data Bus Bit 5

FIFO Data Bus Bit 6

FIFO Data Bus Bit 7

FIFO CONTROL INTERFACE GROUP

Pin#

Signal

Type

Description

Channel A Channel B

15

30

RXF#

OUTPUT When high, do not read data from the FIFO. When low, there is

data available in the FIFO which can be read by strobing RD#

low then high again ** Note 18

13

12

29

28

TXE#

RD#

OUTPUT When high, do not write data into the FIFO. When low, data can

be written into the FIFO by strobing WR high then low. ** Note 18

INPUT

Enables Current FIFO Data Byte on D0..D7 when low. Fetches

the next FIFO Data Byte (if available) from the Receive FIFO

Buffer when RD# goes from low to high. ** Note 17

11

10

27

26

WR

INPUT

Writes the Data Byte on the D0..D7 into the Transmit FIFO Buffer

when WR goes from high to low. ** Note 17

SI/WU

The Send Immediate / WakeUp signal combines two functions

on a single pin. If USB is in suspend mode (PWREN# = 1) and

remote wakeup is enabled in the EEPROM , strobing this pin

low will cause the device to request a resume on the USB Bus.

Normally, this can be used to wake up the Host PC.

During normal operation (PWREN# = 0), if this pin is strobed low

any data in the device TX buffer will be sent out over USB on the

next Bulk-IN request from the drivers regardless of the pending

packet size. This can be used to optimise USB transfer speed for

some applications. Tie this pin to VCCIO if not used.

**Note 17 : In Input Mode, these pins are pulled to VCCIO via internal 200K resistors. These can be programmed to

gently pull low during USB suspend ( PWREN# = “1” ) by setting this option in the EEPROM.

**Note 18 : During device reset, these pins are tri-state but pulled up to VCCIO via internal 200K resistors.

DS2232C Version 1.2

Page 33 of 54

245 FIFO Mode TIMING DIAGRAMS

Figure 19 - FIFO READ Cycle

FT2232C Dual USB UART / FIFO I.C.

T6

T5

RXF#

RD#

T2

T1

T4

T3

Valid Data

D[7...0]

Time

T1

Description

Min

Max

Unit

ns

RD# Active Pulse Width

RD# to RD Pre-Charge Time

RD# Active to Valid Data **Note 19

50

T2

50 + T6

T3

20

0

50

25

T4

Valid Data Hold Time from RD# Inactive **Note 19

RD# Inactive to RXF#

T5

0

T6

RXF# inactive after RD# cycle

80

** Note 19 : Load 30 pF at standard drive level. These times will also vary if the high output drive level is enabled.

Figure 20 - FIFO Write Cycle

T12

T11

TXE#

T8

T7

WR

T9

T10

Valid Data

D[7...0]

Time

T7

Description

Min

50

20

0

Max

Unit

ns

WR Active Pulse Width

T8

WR to WR Pre-Charge Time

Data Setup Time before WR inactive

Data Hold Time from WR inactive

WR Inactive to TXE#

T9

T10

T11

T12

5

25

TXE inactive after WR cycle

80

DS2232C Version 1.2

Page 34 of 54

FT2232C Dual USB UART / FIFO I.C.

Figure 21 - Microprocessor Interface Example

FT2232C

Microcontroller

Channel A

D0

IO10

IO11

IO12

IO13

IO14

IO15

IO16

IO17

or B

D1

D2

D3

D4

D5

D6

D7

RD#

WR

IO20

IO21

IO22

IO23

TXE#

RXF#

SI / WU

IO24

IO25

( Optional )

41

PWREN#

( Optional )

Figure 21 illustrates a typical interface between one of the channels of the FT2232C, conﬁgured in 245-style FIFO

interface mode, and a MicroController (MCU). Either channel A or B, or both can be conﬁgured in this mode. This

examples uses two IO Ports of the MCU, one port (8 bits) to transfer data to one of the and the other port (4 / 5

bits) to monitor the TXE# and RXF# status bits and generate the RD# and WR strobes to the FT2232C as required.

Optionally, SI / WU can be connected to another IO pin if either of the functions of this pin are required. If the SI / WU

function is not required, tie this pin to VCCIO. If the MCU is handling power management functions, then PWREN#

should also be connected to an IO pin of the MCU.

The 8 data bits on IO Port 1 can be shared with other peripherals when the MCU is not accessing the FT2232C.

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FT2232C Dual USB UART / FIFO I.C.

9.4 CPU FIFO Interface Mode Signal Descriptions and Conﬁguration Examples

CPU-style FIFO interface mode is designed to allow a CPU to interface to USB via the FT2232C. This mode is

enabled in the external EEPROM. The interface is achieved using a chip select bit (CS#) and address bit (A0).

When either Channel A or Channel B are in CPU FIFO Interface mode the IO signal lines are conﬁgured as follows:-

FIFO DATA BUS GROUP **Note 20

Pin#

Signal

Type

Description

Channel A Channel B

24

23

22

21

20

19

17

16

40

39

38

37

36

35

33

32

D0

D1

D2

D3

D4

D5

D6

D7

I/O

FIFO Data Bus Bit 0

FIFO Data Bus Bit 1

FIFO Data Bus Bit 2

FIFO Data Bus Bit 3

FIFO Data Bus Bit 4

FIFO Data Bus Bit 5

FIFO Data Bus Bit 6

FIFO Data Bus Bit 7

FIFO CONTROL INTERFACE GROUP

Pin#

Signal

Type

Description

Channel A Channel B

15

13

12

11

30

29

28

27

CS#

A0

INPUT

Chip Select Bit ** Note 20

Address Bit ** Note 20

RD#

WR#

Negative read input ** Note 20

Negative write input ** Note 20

**Note 20 : In Input Mode, these pins are pulled to VCCIO via internal 200K resistors. These can be programmed to

gently pull low during USB suspend ( PWREN# = “1” ) by setting this option in the EEPROM.

Chip Select bit and Address bit truth table

CS#

A0

X

RD#

X

WR#

X

1

0

Read Data Pipe

Read Status

Write Data Pipe

Send Immediate **Note 21

1

Key : X = Not Used; 1 = Signal off; 0 = Signal off

**Note 21 : Has to be clocked by USB clock.

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FT2232C Dual USB UART / FIFO I.C.

Status Data bits

Data Bit

Data

1

Status

bit 0

Data Available (=RXF)

bit 1

1

Space Available (=TXE)

bit 2

1

Suspend

bit 3

1

Conﬁgured

bit 4 **Note 22

bit 5 **Note 22

bit 6 **Note 22

bit 7 **Note 22

X

Key : X = Not Used; 1 = Signal off; 0 = Signal off

**Note 22 : bits 4 to 7 will have arbitrary values when the status is read.

Figure 22 - CPU FIFO Interface Mode - Signal Timing

A0

CS#

WR#

Valid

t3

t1

t4

t6

RD#

D7..0

Valid

t2

t5

t7

Time

Description

Min

15

20

5

Max

Unit

ns

t1

t2

t3

t4

t5

t6

t7

t8

t9

A0 / CS Setup to WR#

Data setup to WR#

WR# Pulse width

-

A0/CS Hold from WR#

Data hold from WR#

A0/CS Setup to RD#

-

5

-

15

5

-

Data delay from RD# **Note 23

A0/CS hold from RD#

50

-

Data hold time from RD# **Note 23

0

30

**Note 23 : For standard output drive level Times may vary if high drive level is enabled.

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FT2232C Dual USB UART / FIFO I.C.

Figure 23 - CPU FIFO Single Channel Interface Example 1

Decoder

FT2232C

CPU

Channel A

15

13

12

11

CS# (ACBUS0)

Address Bus

A0 (ACBUS1)

RD# (ACBUS2)

WR# (ACBUS3)

RD#

WR#

Data Bus

Data

D[0...7] (ADBUS[0...7])

Figure 23 shows an example where channel A of the FT2232C is used in CPU FIFO mode to interface with a CPU. To

read or write data to or from the CPU to the FT2232C, the FT2232C’s Chip Select (CS#) would be set to 0. In order

to read the status of the device the Address bit would then be set to 1, and RD# would be strobed causing the status

data to be driven onto D0...D7. If data is available (D0 = 1) then it can be read by setting A0 to 0, and strobing RD#. If

space is available (D1=1) then data can be written to the FT2232C by setting A0 to 0 and strobing WR#.

When CS# is set to 0 and A0 is set to 1, strobing WR# causes any data in the FT2232C’s TX buffer to be sent out over

USB on the next Bulk-In request, regardless of the pending packet size.

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FT2232C Dual USB UART / FIFO I.C.

Figure 24 - CPU FIFO Dual Channel Interface Example 2

Decoder

FT2232C

CPU

Channel A

15

CS#_A (ACBUS0)

Address Bus

13

12

11

A0_A (ACBUS1)

RD#_A (ACBUS2)

WR#_A (ACBUS3)

RD#

WR#

Data Bus

Data

D[0...7]A (ADBUS[0...7])

Channel B

30

CS#_B (BCBUS0)

A0_B (BCBUS1)

RD#_B (BCBUS2)

WR#B (BCBUS3)

29

28

27

D[0...7]B (BDBUS[0...7])

Figure 24 shows an example where both channels A and B of the FT2232C are used in CPU FIFO mode to interface

with a CPU. This conﬁguration gives the CPU access to both of the FT2232C’s data pipes.

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FT2232C Dual USB UART / FIFO I.C.

9.5 Enhanced Asynchronous and Synchronous Bit-Bang Modes - Signal Description and

Interface Conﬁguration

Bit-bang mode is a special FT2232C device mode that changes the 8 IO lines on either (or both) channels into an 8

bit bi-directional data bus. The are two types of bit bang mode for the FT2232C - Enhanced Asynchronous Bit-Bang

Mode, which is virtually the same as FTDI BM chip-style Bit-Bang mode, with the addition of Read and Write strobes;

and Synchronous Bit-Bang mode, where data is only read from the device when the device is written to. Bit-Bang

mode is enabled by driver command. When either Channel A or Channel B (or both) have Enhanced Asynchronous

Bit-Bang mode, or Synchronous Bit-Bang mode enabled the IO signal lines are conﬁgured as follows :-

BIT-BANG DATA BUS GROUP **Note 24

Pin#

Signal

Type

Description

Channel A Channel B

24

23

22

21

20

19

17

16

40

39

38

37

36

35

33

32

D0

D1

D2

D3

D4

D5

D6

D7

I or O

Bit-Bang Data Bus Bit 0

Bit-Bang Data Bus Bit 1

Bit-Bang Data Bus Bit 2

Bit-Bang Data Bus Bit 3

Bit-Bang Data Bus Bit 4

Bit-Bang Data Bus Bit 5

Bit-Bang Data Bus Bit 6

Bit-Bang Data Bus Bit 7

BIT-BANG CONTROL INTERFACE GROUP

Pin#

Signal

Type

Description

Channel A Channel B

15

13

12

11

10

30

29

28

27

26

WR#

RD#

OUTPUT **Note 25

OUTPUT **Note 26

WR#

RD#

SI/WU

INPUT

The Send Immediate / WakeUp signal combines two functions

on a single pin. If USB is in suspend mode (PWREN# = 1) and

remote wakeup is enabled in the EEPROM , strobing this pin

low will cause the device to request a resume on the USB Bus.

Normally, this can be used to wake up the Host PC.

During normal operation (PWREN# = 0), if this pin is strobed low

any data in the device TX buffer will be sent out over USB on the

next Bulk-IN request from the drivers regardless of the pending

packet size. This can be used to optimise USB transfer speed for

some applications. Tie this pin to VCCIO if not used.

**Note 24 : In Input Mode, these pins are pulled to VCCIO via internal 200K resistors. These can be programmed to

gently pull low during USB suspend ( PWREN# = “1” ) by setting this option in the EEPROM.

**Note 25 : The Bit-Bang Mode (synchronous and asynchronous) WR# and RD# strobes are on these pins when

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FT2232C Dual USB UART / FIFO I.C.

the main Channel mode is 245 FIFO, CPU FIFO interface, or Fast Opto-Isolated Serial Mode. Bit-Bang mode is not

available on Channel B when Fast Opto-Isolated Serial Mode is enabled.

**Note 26 : The Bit-Bang Mode (synchronous and asynchronous) WR# and RD# strobes are on these pins when the

main Channel mode is set to 232 UART Mode.

Enhanced Asynchronous Bit-Bang Mode

Enhanced Asynchronous Bit-Bang mode is the same as BM-style Bit-Bang mode, except that the internal RD# and

WR# strobes are now brought out of the device to allow external logic to be clocked by accesses to the bit-bang IO

bus.

On either or both channels any data written to the device in the normal manner will be self clocked onto the data pins

(those which have been conﬁgured as outputs). Each pin can be independently set as an input or an output. The rate

that the data is clocked out at is controlled by the baud rate generator.

For the data to change there has to be new data written, and the baud rate clock has to tick. If no new data is written

to the channel, the pins will hold the last value written.

To allow time for the data to be setup and held around the WR# strobe, the baud rate should be less than 1

MegaBaud.

See the application note AN232B-01, “FT232BM/FT245BM Bit Bang Mode” for more details and a sample

application.

Enabling

Asynchronous Bit-Bang mode is enabled using Set Bit Bang Mode driver command. A hex value of 1 will enable it, and

a hex value of 0 will reset the device. See application note AN2232C-02, “Bit Mode Functions for the FT2232C” for

more details and examples of this.

Synchronous Bit-Bang Mode

With Synchronous Bit-Bang mode data will only be sent out by the FT2232C if there is space in the device for data to

be read from the pins. This Synchronous Bit-Bang mode will read the data bus pins ﬁrst, before it sends out the byte

that has just been transmitted. It is therefore 1 byte behind the output, and so to read the inputs for the byte that you

have just sent, another byte must be sent.

For example :-

(1) Pins start at 0xFF

Send 0x55,0xAA

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FT2232C Dual USB UART / FIFO I.C.

Pins go to 0x55 and then to 0xAA

Data read = 0xFF,0x55

(2) Pins start at 0xFF

Send 0x55,0xAA,0xAA

(repeat the last byte sent)

Pins go to 0x55 and then to 0xAA

Data read = 0xFF,0x55,0xAA

Enabling

Synchronous Bit-Bang mode is enabled using Set Bit Bang Mode driver command. A hex value of 4 will enable it, and

a hex value of 0 will reset the device. See application note AN2232C-02, “Bit Mode Functions for the FT2232C” for

more details and examples.

Figure 25 - Synchronous Bit Bang Mode Signal Timing

t3

t1

t2

t4

t5

t6

Clk Time

D7..0

Current Data

New Data

WR#

RD#

Time

t1

Description

Current pin state is read

RD# is set inactive

t2

t3

RD# is set active again, and any pins that are output will change to the new data.

t4

Clock state for data setup

WR# goes active

t5

t6

WR# goes inactive

The internal RD# and WR# strobes are brought out of the device to allow external logic to be clocked by accesses to

the bit-bang IO bus.

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FT2232C Dual USB UART / FIFO I.C.

9.6 Multi-Protocol Synchronous Serial Engine (MPSSE) Mode Signal Descriptions and

Interface Conﬁgurations

MPSSE Mode is designed to allow the FT2232C to interface efﬁciently with synchronous serial protocols such

as JTAG and SPI Bus. It can also be used to program SRAM based FPGA’s over USB. The MPSSE interface is

designed to be ﬂexible so that it can be conﬁgured to allow any synchronous serial protocol (industry standard or

proprietary) to be interfaced to the FT2232C. MPSSE is available on channel A only.

MPSSE is fully conﬁgurable, and is programmed by sending commands down the data pipe. These can be sent

individually, or more efﬁciently in packets. MPSSE is capable of a maximum sustained data rate of 5.6 Mega bits / s.

When Channel A is conﬁgured in MPSSE mode the IO signal lines are conﬁgured as follows :-

Pin#

Signal

Type

Description

(Channel A Only)

24

23

22

21

20

19

17

TCK/SK OUTPUT Clock signal Output

TDI/D0 OUTPUT Serial Data Out

TDO/DI INPUT Serial Data In **Note 27

TMS/CS OUTPUT Select Signal Out

GPIOL0 I/O

GPIOL1 I/O

GPIOL2 I/O

GPIOL3 I/O

GPIOH0 I/O

GPIOH1 I/O

GPIOH2 I/O

GPIOH3 I/O

General Pupose input / Output **Note 27

16

15

13

12

11

**Note 27 : In Input Mode, these pins are pulled to VCCIO via internal 200K resistors. These can be programmed to

gently pull low during USB suspend ( PWREN# = “1” ) by setting this option in the EEPROM.

Enabling

MPSSE mode is enabled using Set Bit Bang Mode driver command. A hex value of 2 will enable it, and a hex value of

0 will reset the device. See application note AN2232C-02, “Bit Mode Functions for the FT2232C” for more details

and examples.

The MPSSE command set is fully described in application note AN2232C-01 - “Command Processor For MPSSE

and MCU Host Bus Emulation Modes”.

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FT2232C Dual USB UART / FIFO I.C.

9.7 MCU Host Bus Emulation Mode Signal Descriptions and Interface Conﬁguration

MCU host bus emulation mode uses both of the FT2232C’s A and B channel interfaces to make the chip emulate a

standard 8048 / 8051 MCU host bus. This allows peripheral devices for these MCU families to be directly connected to

USB via the FT2232C.

The lower 8 bits (AD7 to AD0) is a multiplexed Address / Data bus. A8 to A15 provide upper (extended) addresses.

There are 4 basic operations :-

1) Read (does not change A15 to A8)

2) Read Extended (changes A15 to A8)

3) Write (does not change A15 to A8)

4) Write Extended (changes A15 to A8)

Enabling

MCU Host Bus Emulation mode is enabled using Set Bit Bang Mode driver command. A hex value of 8 will enable

it, and a hex value of 0 will reset the device. See application note AN2232C-02, “Bit Mode Functions for the

FT2232C” for more details and examples.

The MCU Host Bus Emulation Mode command set is fully described in application note AN2232C-01 - “Command

Processor For MPSSE and MCU Host Bus Emulation Modes”.

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FT2232C Dual USB UART / FIFO I.C.

When MCU Host Bus Emulation mode is enabled the IO signal lines on both channels work together and the pins are

conﬁgured as follows :-

Pin#

Signal

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

I/O0

Type

I/O

Description

24

23

22

21

20

19

17

16

15

Address / Data Bus Bit 0 **Note 28

Address / Data Bus Bit 1 **Note 28

Address / Data Bus Bit 2 **Note 28

Address / Data Bus Bit 3 **Note 28

Address / Data Bus Bit 4 **Note 28

Address / Data Bus Bit 5 **Note 28

Address / Data Bus Bit 6 **Note 28

Address / Data Bus Bit 7 **Note 28

MPSSE mode instructions to set / clear or read the high byte of

data can be used with this pin. **Note 28, **Note 29

13

I/O1

I/O

MPSSE mode instructions to set / clear or read the high byte of

data can be used with this pin. In addition this pin has instructions

which will make the controller wait until it is high, or wait until it is

low. This can be used to connect to an IRQ pin of a peripheral chip.

The FT2232C will wait for the interrupt, and then read the device,

and pass the answer back to the host PC. I/O1 must be held in

input mode if this option is used. **Note 28, **Note 29

12

IORDY

INPUT

Extends the time taken to perform a Read or Write operation if

pulled low. Pull up to Vcc if not being used.

11

40

39

38

37

36

35

33

32

30

29

28

27

OSC

A8

OUTPUT Shows the clock signal that the circuit is using.

OUTPUT Extended Address Bus Bit 8

A9

OUTPUT Extended Address Bus Bit 9

A10

A11

A12

A13

A14

A15

CS#

ALE

RD#

WR#

OUTPUT Extended Address Bus Bit 10

OUTPUT Extended Address Bus Bit 12

OUTPUT Extended Address Bus Bit 13

OUTPUT Extended Address Bus Bit 14

OUTPUT Extended Address Bus Bit 15

OUTPUT Extended Address Bus Bit 16

OUTPUT Negative pulse to select device during Read or Write.

OUTPUT Positive pulse to latch the address.

OUTPUT Negative Read Output.

OUTPUT Negative Write Output. (Data is setup before WR# goes low, and is

held after WR# goes high)

**Note 28 : In Input Mode, these pins are pulled to VCCIO via internal 200K resistors. These can be programmed to

gently pull low during USB suspend ( PWREN# = “1” ) by setting this option in the EEPROM.

**Note 29 : These instrucions are fully described in the application note AN2232C-01 - “Command Processor For

MPSSE and MCU Host Bus Emulation Modes”.

DS2232C Version 1.2

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FT2232C Dual USB UART / FIFO I.C.

Figure 29 - MCU Host Bus Emulation Mode Signal Timing - Write Cycle

t3

t8 t9 t10 t11

t1

t2

t4

t5

t6

t7

OSC

High Address

Low Address

A15..A8

Data

AD7..0

ALE

CS#

WR#

IORDY

Time

t1

Description

High address byte is placed on the bus if the extended write is used.

Low address byte is put out.

t2

t3

1 clock period for address is set up.

t4

ALE goes high to enable latch. This will extend to 2 clocks wide if IORDY is low.

ALE goes low to latch address and CS# is set active low.

Data driven onto the bus.

t5

t6

t7

1 clock period for data setup.

t8

WR# is driven active low. This will extend to 6 clocks wide if IORDY is low.

WR# is driven inactive high.

t9

t10

t11

CS# is driven inactive, 1/2 a clock period after WR# goes inactive

Data is held until this point, and may now change

DS2232C Version 1.2

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FT2232C Dual USB UART / FIFO I.C.

Figure 30 - MCU Host Bus Emulation Mode Signal Timing - Read Cycle

t3

t1

t2

t4

t5

t6

t7

t8 t9

OSC

High Address

Low Address

A15..A8

Hi-Z

AD7..0

ALE

CS#

RD#

IORDY

Time

t1

Description

High address byte is placed on the bus if the extended read is used - otherwise t1 will not occur.

Low address byte is put out.

t2

t3

1 clock period for address set up.

t4

ALE goes high to enable address latch. This will extend to 2 clocks wide if IORDY is low.

t5

ALE goes low to latch address, and CS# is set active low. This will extend to 3 clocks if IORDY is sampled

low. CS# will always drop 1 clock after ALE has gone high no matter the state of IORDY.

t6

t7

t8

t9

Data is set as input (Hi-Z), and RD# is driven active low.

1 clock period for data setup. This will extend to 5 clocks wide if IORDY# is sampled low.

RD# is driven inactive high.

CS# is driven inactive 1/2 a clock period after RD# goes inactive, and the data bus is set back to output.

Figure 31 - MCU Host Bus Emulation Mode Signal Timing - Clock (OSC) Signal

t

high

OSC

t

period

t

low

Time

tperiod

thigh

Description

Minimum

41.6

Typical Value

83.3

Maximum

125.0

62.5

Unit

ns

Clock Period

Clock signal high time

Clock signal low time

20.8

41.6

ns

20.8

41.6

62.5

ns

tlow

DS2232C Version 1.2

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FT2232C Dual USB UART / FIFO I.C.

Figure 32 - MCU Host Bus Emulation Example - USB <=> CAN Bus Interface

FT2232C

SJA1000

CANBus

Controller

30

29

28

27

CS# (BCBUS0)

CS#

Tx

Rx

CANBus

Transeiver

ALE (BCBUS1)

ALE/AS

RD#

RD# (BCBUS2)

WR# (BCBUS3)

WR#

AD[0...7]

(ADBUS[0...7])

AD[0...7]

ADDRESS / DATA BUS

CAN

Bus

Vcc

12

15

13

IORDY# (ACBUS2)

I/O0 (ACBUS0)

I/O1 (ACBUS1)

MODE

INT#

Figure 32 shows an example where the FT2232C is used to interface a Philips SJA1000 CAN Bus Controller to a PC

over USB. In this example IORDY is not used and so is pulled up to Vcc. I/O1 is used to monitor the Interrupt output

(INT) of the SJA1000. The MODE pin on the SJA1000 is pulled high to select Intel mode. See the semiconductors

section of the Philips website (www.philips.com) for more details on the SJA1000, and suitable CAN Bus transceiver

devices.

DS2232C Version 1.2

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FT2232C Dual USB UART / FIFO I.C.

9.8 Fast Opto-Isolated Serial Interface Mode Signal Description and Conﬁguration

Fast Opto-Isolated Serial Interface Mode provides a method of communicating with an external device over USB using

4 wires that can have opto-isolators in their path, thus providing galvanic isolation between systems. If either channel

A or channel B are enabled in fast opto-isolated serial mode then the pins on channel B are switched to the fast serial

interface conﬁguration. The I/O interface for fast serial mode is always on channel B, even if both channels are being

used in this mode. An address bit is used to determine the source or destination channel of the data. It therefore

makes sense to always use at least channel B or both for fast serial mode, but not A own its own.

When either Channel B or Both Channel A and B are conﬁgured in Fast Opto-Isolated Serial Interface mode following

IO signal lines are conﬁgured as follows :-

Pin#

Signal

FSDI

Type

Description

40

39

INPUT

Fast serial data input **Note 30

FSCLK

Clock input to FT2232C chip to clock data in or out. The external

device has to provide a clock signal or nothing will change on

the interface pins. This gives the external device full control over

the interface. It is designed to be half duplex so that data is only

transferred in one direction at a time. **Note 30

38

FSDO

OUTPUT Fast serial data output. Driven low to indicate that the chip is ready

to send data.

37

26

FSCTS OUTPUT Clear To Send control signal output

SI/WU

INPUT

The Send Immediate / WakeUp signal combines two functions on

a single pin. If USB is in suspend mode (PWREN# = 1) and remote

wakeup is enabled in the EEPROM , strobing this pin low will cause

the device to request a resume on the USB Bus. Normally, this can

be used to wake up the Host PC.

During normal operation (PWREN# = 0), if this pin is strobed low

any data in the device TX buffer will be sent out over USB on the

next Bulk-IN request from the drivers regardless of the pending

packet size. This can be used to optimise USB transfer speed for

some applications. Tie this pin to VCCIO if not used.

**Note 30 : Pulled up to VCCIO via internal 200K resistors. These pins can be programmed to gently pull low during

USB suspend ( PWREN# = “1” ) by setting this option in the EEPROM.

Fast Opto-Isolated serial interface mode is enabled in the external EEPROM.

DS2232C Version 1.2

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FT2232C Dual USB UART / FIFO I.C.

Figure 33 - Fast Opto-Isolated Serial Signal Timing Diagram

FSCLK

t1

t5

t6

t2

FSDO / FSCTS

FSDI

t7

t3

t4

Time

t1

Description

Min

Max

Unit

ns

FSDO / FSCTS hold time

FSDO / FSCTS setup time

FSDI hold time

5

-

t2

5

t3

5

t4

FSDI setup time

FSCLK low

10

20

t5

t6

FSCLK high

t7

FSCLK Period

Outgoing Fast Serial Data

To send fast serial data out of the chip, the external device must clock. If the chip has data ready to send, it will drive

FSDO low to indicate the start bit. It will not do this if it is currently receiving data from the external device.

Figure 34 - Fast Opto-Isolated Serial Data Format - Data output from the FT2232C

FSCLK

0

Start

Bit

D0

D1

D2

D3

D4

D5

D6

D7

SRCE

Source

Bit

FSDO

Data Bits - LSB first

Notes :-

(i) Start Bit is always 0.

(ii) Data is sent LSB ﬁrst.

(iii) The source bit (SRCE) indicates which channel the data has come from. A ‘0’ means that it has come from Chan-

nel A, a ‘1’ means that it has come from Channel B.

(iv) If the target device is unable to accept the data when it detects the start bit, it should stop the FSCLK until it can

accept the data.

DS2232C Version 1.2

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FT2232C Dual USB UART / FIFO I.C.

Incoming Fast Serial Data

The external device is allowed to send data into the chip if FSCTS is high. On receipt of a Zero start bit on FSDI, the

chip will drop FSCTS on the next positive clock edge. The data from bits 0 to 7 is then clocked in (LSB ﬁrst). The

next bit determines where the data will be written to. It can go to either channel A or to channel B. A ‘0’ will send it to

channel A, providing channel A is enabled for fast serial mode, otherwise it will go to channel B. A ‘1’ will send it to

channel B, providing channel B is enabled for fast serial mode, otherwise it will go to channel A. ( Either channel A, or

channel B, or both must be enabled as fast serial mode or the circuit is disabled).

Figure 35 - Fast Opto-Isolated Serial Data Format - Data input to the FT2232C

FSCTS

FSCLK

0

D0

D1

D2

D3

D4

D5

D6

D7

DEST

Destination

Bit

FSDI

Start

Bit

Data Bits - LSB first

Notes :-

(i) Start Bit is always 0.

(ii) Data is sent LSB ﬁrst.

(iii) The destination bit (DEST) indicates which channel the data should go to. A ‘0’ means that it should go to channel

A, a ‘1’ means that it should go to channel B.

(iv) The target device should check CTS is high before it sends data. CTS goes low after data bit 0 (D0) and stays low

until the chip can accept more data.

Contention

There is a possibility that contention may occur, where the interface goes from being completely idle to both sending

and receiving at the same clock instance. In this case the chip backs off, and allows the data from the external device

to be received.

Data Format

The data format for either direction is :-

1) Zero Start Bit

2) Data bit 0

3) Data bit 1

4) Data bit 2

5) Data bit 3

6) Data bit 4

7) Data bit 5

8) Data bit 6

9) Data bit 7

10) Source/Destination (‘0’ indicates channel A; ‘1’ indicates channel B)

DS2232C Version 1.2

Page 51 of 54

FT2232C Dual USB UART / FIFO I.C.

Reset / Enable

Fast serial mode is enabled by setting the appropriate bits in the external EEPROM. The fast serial mode can be

held in reset by setting a bit value of 10 using the Set Bit Bang Mode command. While this bit is set the device is held

reset - data can be sent to the device, but it will not be sent out by the device until the device is enabled again. This

is done by sending a bit value of 0 using the set bit mode command. See application note AN2232C-02, “Bit Mode

Functions for the FT2232C” for more details and examples.

Figure 36 - Fast Opto-Isolated Serial Interface Example

VCC5V

Cable

VCCE

FT2232C

8

HCPL-2430

1

2

1K

7

40

39

470R

FSDI (BDBUS0)

DI

3

6

5

CLK

FSCLK (BDBUS1)

4

VCCE

VCC5V

8

1

HCPL-2430

1K

7

470R

38

37

2

3

FSDO (BDBUS2)

FSCTS (BDBUS0)

DO

6

5

CTS

4

In the example shown in ﬁgure 12 two Agilent HCPL-2430 (see the semiconductor section at www.agilent.com) high

speed opto-couplers are used to optically isolate an external device which interfaced to USB using the FT2232C. In

this example VCC5V is the supply for the FT2232C (bus or self powered), and VCCE is the supply to the external

device.

Care must be taken with the voltage used to power the photoLED’s. It should be the same supply that the I/Os are

driving to, or the LED’s may be permanently on. Limiting resistors should be ﬁtted in the lines that drive the diodes.

The outputs of the opto-couplers are open-collector and so need a pullup resistor.

Testing

Fast serial mode has been tested using an Scenix (Ubicom), SX28 microcontroller (see www.ubicom.com) which

was conﬁgured in loopback mode. This was done both with, and without HP HCPL-2430 opto-isolators in place. The

isolators add a considerable delay to the turnaround time seen by the micro. This was close to 100 nS with the high

speed HCPL-2430 device. This is the combined delay of the clock signal from the microcontroller going through

an opto-coupler to the chip, and the data from the FT2232C chip going through the other opto-coupler back to the

microcontroller.

DS2232C Version 1.2

Page 52 of 54

FT2232C Dual USB UART / FIFO I.C.

10.0 Document Revision History

DS2232C Version 1.0 – Initial document created January 2004.

DS2232C Version 1.1 – Updated February 2004.

•

Grammar Corrections

Section 4.0 Device Pin Out Figure 2 corrected.

Section 5.1 TEST pin number corrected.

Section 5.1 VCCIOA and VCCIOB pin descriptions updated.

Section 9.1 Figure 14 SP214EHCA pin numbers corrected.

Section 12.0 Company contact information updated.

DS2232C Version 1.2 – Updated April 2004.

•

Section 1.0 Linux now supported.

Section 2.0 Extended EEPROM Support corrected.

Section 2.0 Synchronous Bit-Bang Mode description clariﬁed.

Section 4.0 Figure 3 Pin 46 AVCC name corrected.

Section 5.2 Note 2 modiﬁed.

Section 5.3 IO Mode Command Hex Values added.

Section 8.1 Additional Murata part number added.

Section 8.3 TEST pin number added to ﬁgure 8.

Section 8.3 TEST pin number and missing GND added to ﬁgure 9.

Section 8.4 SI/WU pin numbers added to ﬁgure 10.

Section 8.4 TEST pin number added to ﬁgure 11.

Section 9.3 FIFO Write Cycle timings ameded. Figure 19 amended.

Section 9.5 Synchronous Bit-Bang Mode description ameded.

Sections 9.5, 9.6, 9.7, and 9.8 Enabling IO Bit Mode clariﬁed.

Section 12.0 Email Addresses Updated.

DS2232C Version 1.2

Page 53 of 54

FT2232C Dual USB UART / FIFO I.C.

11.0 Disclaimer

Neither the whole nor any part of the information contained in, or the product described in this manual, may be

adapted or reproduced in any material or electronic form without the prior written consent of the copyright holder.

This product and its documentation are supplied on an as-is basis and no warranty as to their suitability for any

particular purpose is either made or implied.

Future Technology Devices International Ltd. will not accept any claim for damages howsoever arising as a result of

use or failure of this product. Your statutory rights are not affected.

This product or any variant of it is not intended for use in any medical appliance, device or system in which the failure

of the product might reasonably be expected to result in personal injury.

This document provides preliminary information that may be subject to change without notice.

12.0 Contact Information

Future Technology Devices International. Limited

373 Scotland Street,

Glasgow G5 8QB,

United Kingdom.

Tel : +44 ( 0 )141 429 2777

Fax : +44 ( 0 )141 429 2758

E-Mail ( Sales ) : sales1@ftdichip.com

E-Mail ( Support ) : support1@ftdichip.com

E-Mail ( General Enquiries ) : admin1@ftdichip.com

Web Site URL : http://www.ftdichip.com

Agents and Sales Representatives

At the time of writing our Sales Network covers over 40 different countries world-wide. Please visit the Sales Network

page of our Web site for the contact details our distributor(s) in your country.

DS2232C Version 1.2

Page 54 of 54


型号：	FT2232C
厂家：	FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD.
描述：	Dual USB UART / FIFO I.C. 双USB UART / FIFO I.C. 先进先出芯片 PC
文件：	总54页 (文件大小：1025K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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