EDC4BV7282B-60JG-S [FUJITSU]
Memory IC, 4MX72, CMOS, PDMA168;
| 型号： | EDC4BV7282B-60JG-S |
| 厂家： | 
FUJITSU |
| 描述： | Memory IC, 4MX72, CMOS, PDMA168 光电二极管 |
| 文件： | 总8页 (文件大小：114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 1997
data sheet
Revision 1.0
EDC4BV7282B-60(J/T)G-S
32MByte (4M x 72) CMOS
EDO DRAM Module - 3.3V (ECC), Buffered
General Description
The EDC4BV7282B-60(J/T)G-S is a high performance, EDO (Extended Data Out) 32-megabyte dynamic RAM module organized
as 4M words by 72 bits, in a 168-pins, dual-in-line (DIMM) memory module with ECC.
The module utilizes eighteen, Fujitsu MB81V17805B-60(PJ/FN) CMOS 2Mx8 EDO dynamic RAMs in a surface mount package
on an epoxy laminate substrate. Each device is accompanied by a decoupling capacitor for improved noise immunity.
Control lines provided are such that Dword control is possible. All signals are buffered (74ABT16244 or equivalent) except RAS,
data, and IDs.
Features
• High Density: 32MByte
• Fast Access Time of 60ns (max.)
• Low Power:
3.7 W (max.) -Active (60ns)
165mW (max.) - Standby (LVTTL)
100mW (max.) - Standby (CMOS)
• LVTTL-compatible inputs and outputs
• Separate power and ground planes to improve noise immunity
• Single power supply of 3.3V±0.3V
• Height: 1.000 inch
• 2K Refresh Cycles
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Ratings
-0.5 to +4.6
20
Unit
V
Voltage on any pin relative to V
V
P
SS
T
Power Dissipation
W
T
T
Operating Temperature
Storage Temperate
0 to +70
-55 to +125
-50 to +50
°C
°C
mA
opr
T
I
stg
Short Circuit Output Current
OS
RECOMMENDED DC OPERATING CONDITIONS
(TA = 0 to +70 °C)
Symbol
Parameter
Supply Voltage
Min
3.0
0
Typ
Max
3.6
0
Unit
V
V
V
V
3.3
V
V
V
V
CC
SS
IH
Ground
0
-
V
+0.3
Input High voltage
Input Low voltage
2.0
-0.3
CC
-
0.8
IL
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
1
July 1997
Revision 1.0
EDC4BV7282B-60(J/T)G-S
Functional Diagram
RAS0*
RAS2*
2M x 16
EDO
DRAM
BLOCK
2M x 16
EDO
DRAM
BLOCK
2M x 16
EDO
DRAM
BLOCK
2M x 16
EDO
DRAM
BLOCK
CAS0*
WE0*
OE0*
A0
CAS4*
WE2*
OE2*
B0
2M x 8
EDO
DRAM
RAS1*
CAS1*
RAS3*
CAS5*
2M x 16
EDO
DRAM
BLOCK
2M x 16
EDO
DRAM
BLOCK
2M x 16
EDO
DRAM
BLOCK
2M x 16
EDO
DRAM
BLOCK
2M x 8
EDO
DRAM
DQ0~DQ15
DQ16~DQ31
DQ32~DQ39
DQ40~DQ55
DQ56~DQ71
DQ0~DQ71
Notes:
1. All signals inclusing PDs (with the exception of RAS*, data and IDs)
are buffered.
V
V
SS
CC
2. “*” signifies active low signal.
Decoupling capacitors
to all devices
3. Addresses A1 ~ A10 are connected to all devices.
4. Each 2Mx16 block comprises two 2Mx8 EDO devices.
All specifications of this device are subject to change without notice.
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
2
July 1997
Revision 1.0
EDC4BV7282B-60(J/T)G-S
Pin Name
A0~A10,B0
A0~A9, B0
DQ0~DQ71
WE0*, WE2*
RAS0*~ RAS3*
OE0*, OE2*
Row Address
VSS
NC
PDE*
PD1~PD8
Ground
Column Address
Data Inputs/Outputs
Write Enable
Row Address Strobes
Output Enable
No Connection
Presence Detect Enable
Presence Detect
PD
60ns
NC
CAS0*, CAS1*, CAS4*, CAS5* Column Address Strobes
VCC
PD6
PD7
NC
Power Supply
Pin No.
Pin Designation
Pin No.
43
Pin Designation
Pin No.
85
Pin Designation
Pin No.
Pin Designation
V
SS
V
V
V
1
2
3
4
5
6
127
128
129
130
131
132
SS
SS
SS
DQ0
DQ1
DQ2
DQ3
44
45
46
47
OE2*
RAS2*
CAS4*
NC
†
†
†
86
87
88
89
DQ36
DQ37
DQ38
DQ39
NC
RAS3*
CAS5*
NC
†
V
V
48
WE2*
90
PDE*
CC
CC
V
V
7
8
9
DQ4
DQ5
DQ6
DQ7
DQ8
49
50
51
52
53
54
55
56
57
58
59
91
92
93
94
95
DQ40
DQ41
DQ42
DQ43
DQ44
133
134
135
136
137
138
139
140
141
142
143
CC
CC
NC
NC
DQ18
DQ19
V
NC
NC
DQ54
DQ55
10
11
12
13
14
15
16
17
V
V
V
96
SS
SS
SS
SS
DQ9
DQ20
DQ21
DQ22
DQ23
97
98
99
100
101
DQ45
DQ46
DQ47
DQ48
DQ49
DQ56
DQ57
DQ58
DQ59
DQ10
DQ11
DQ12
DQ13
V
V
CC
CC
V
V
18
19
20
21
22
23
24
25
26
27
28
29
30
31
60
61
62
63
64
65
66
67
68
69
70
71
72
73
DQ24
NC
NC
NC
NC
102
103
104
105
106
107
108
109
110
111
112
113
114
115
144
145
146
147
148
149
150
151
152
153
154
155
156
157
DQ60
NC
NC
NC
NC
CC
CC
DQ14
DQ15
D216
D217
DQ50
DQ51
DQ52
DQ53
V
V
DQ25
DQ26
DQ27
DQ61
DQ62
DQ63
SS
SS
NC
NC
V
NC
NC
V
V
V
CC
SS
CC
SS
WE0*
CAS0*
NC
RAS0*
OE0*
†
†
DQ28
DQ29
DQ30
DQ31
NC
CAS1*
NC
RAS1*
NC
DQ64
DQ65
DQ66
DQ67
†
V
V
†
CC
CC
V
V
32
33
34
35
36
74
75
76
77
78
DQ32
DQ33
DQ34
DQ35
116
117
118
119
120
158
159
160
161
162
DQ68
DQ69
DQ70
DQ71
SS
SS
A0
A2
A4
A6
†
†
†
†
A1
A3
A5
A7
†
†
†
†
V
V
SS
SS
PD1(V
)
)
†
†
37
38
39
40
41
42
A8
†
†
79
80
81
82
83
84
121
122
123
124
125
126
A9
†
163
164
165
166
167
168
PD2(NC)
PD4(NC)
PD6
OL
PD3(V
A10
NC
NC
NC
OL
PD5(NC)
PD7
†
†
V
V
PD8(V
ID1(V
)
SS
†
CC
CC
ID0(V
)
)
NC
NC
NC
B0
SS
SS
V
V
CC
†
CC
Notes:
1. PDE* (Pin 132): PD Enable.
2. SIgnals marked with “†” are buffered.
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
3
July 1997
Revision 1.0
EDC4BV7282B-60(J/T)G-S
DC CHARACTERISTICS
(VCC = 3.3V±0.3V, VSS = 0V, TA = 0 to +70 °C)
60
Parameter
Operating Current
Symbol
Test Condition
Unit
Note
Min.
Max.
I
RAS*, CAS* cycling; t = min.
-
1018
mA
1, 2
CC1
RC
LVTTL Interface
RAS*, CAS* ³ V
-
-
46
28
mA
mA
IH
D
= High-Z
out
I
Standby current
CC2
CMOS Interface
RAS*, CAS* ³ V - 0.2V
cc
D
= High-Z
out
CAS* ³ V ; RAS*, Address
RAS* -only Refresh
Current
IH
I
-
-
1018
1018
mA
mA
2
CC3
cycling @ t = min
RC
RAS*, CAS* cycling @
CAS*-before-RAS*
Refresh Current
I
CC4
t
= min.
RC
RAS* £ V CAS*, Address
Hyper Page Mode
Current
IL
I
-
838
90
mA
mA
mA
1, 3
CC5
cycling @ t = min
PC
I
0V £ Vin £ V +0.3V
Input Leakage Current
Output Leakage Current
-90
-20
LI
CC
0V £ Vout £ V
CC
I
20
LO
D
= Disable
out
V
High I = -2mA
Output High Voltage
Output Low Voltage
2.4
-
-
V
V
OH
out
V
Low I = 2 mA
0.4
OL
out
Notes:
1. Values depend on output load condition when the device is selected. Maximum Values are specified at the output open condition.
2. Address can be changed once or less while RAS* = V .
IL
3. Address can be changed once or less while CAS* = V
.
IH
CAPACITANCE
(TA =+25°C, VCC = 3.3V±0.3V)
Parameter
Symbol
Max.
10
Unit
pF
Note
1
C
Input Capacitance (Address, CAS*, WE*, OE*)
Input Capacitance (RAS0*, RAS1*)
I1
C
40
pF
1
I2
C
Input Capacitance (RAS2*, RAS3*)
33
pF
1
I3
C
Input/Output Capacitance (DQ0~DQ71)
20
pF
1, 2
I/O
Notes:
1. Capacitance is measured with Boonton Meter or effective capacitance method.
2. CAS* = V to disable D
.
out
IH
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
4
July 1997
Revision 1.0
EDC4BV7282B-60(J/T)G-S
AC CHARACTERISTICS
(TA = 0 to +70°C, VCC = 3.3V±0.3V, VSS = 0V)
60
Parameter
Symbol
Unit
Notes
Min
110
-
Max
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Random read/write cycle time
Access time from RAS*
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
RC
60
3,4
3,4,5
3, 10
2
RAC
CAC
AA
Access time from CAS*
-
20
Access time from column address
Transition time (rise and fall)
RAS* precharge time
-
35
2
50
T
40
60
20
50
10
20
15
10
5
-
RP
RAS* pulse width
10000
RAS
RSH
CSH
CAS
RCD
RAD
CRP
ASR
RAH
ASC
CAH
RAL
RCS
RCH
RRH
WCH
WP
RAS* hold time
-
CAS* hold time
-
CAS* pulse width
10000
RAS* to CAS* delay time
RAS* to column address delay time
CAS* to RAS* precharge time
Row address set-up time
Row address hold time
40
4
25
10
-
-
10
0
-
Column address set-up time
Column address hold time
Column address to RAS* lead time
Read command set-up time
Read command hold time to CAS*
Read command hold time to RAS*
Write command hold time
Write command pulse width
Write command to RAS* lead time
Write command to CAS* lead time
Data-in set-up time
-
10
35
3
-
-
-
0
-
8
0
-
10
10
20
10
0
-
-
-
RWL
CWL
DS
-
-
9
9
Data-in hold time
15
-
-
DH
Refresh period
32
REF
WCS
CSR
CHR
RPC
CPA
HPC
CP
Write command set-up time
CAS* set-up time (CBR refresh)
CAS* hold time (CBR refresh)
RAS* precharge to CAS* hold time
Access time from CAS* precharge
Hyper page mode cycle time
CAS* precharge time (Hyper page)
RAS* pulse width (Hyper page)
0
-
7
1
1
15
10
5
-
-
-
-
40
3, 11
12
25
10
60
-
-
100000
RASP
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
5
July 1997
Revision 1.0
EDC4BV7282B-60(J/T)G-S
Notes:
1. An initial pulse of at least 200ms is required after power-up followed by a minimum of eight RAS* cycles before device operation
is achieved.
2.
V
(min.) and V (max.) are reference levels for measuring timing of input signals. Transition times are measured between V
IH IL
IH
(min.) and V (max.) and are assumed to be 5 ns for all inputs.
IL
3. Measure with a load equivalent of 2 TTL loads and 100pF.
4. Operation within the t (max.) limit ensures that t (max.) limit can be met; t (max.) is specified as a reference point
RCD
RCD
RAC
only. If t
is greater than the specified t
(max) limit, then access time is controlled exclusively by t
.
RCD
RCD
CAC
5. Assumes that t
³ t
(max.).
RACD
RCD
6. This parameter defines the time at which the output achieves open circuit condition and is not referenced to V or V
.
OH
OL
7.
t
t
is a non restrictive operating parameter. It is included in the data sheet as an electrical characteristic only. If t
(min.) the cycle is an early write cycle and the data out pin will remain at high impedance for the duration of the cycle.
Š
WCS
WCS
WCS
8. Either t
or t must be satisfied for a read cycle.
RCH
RRH
9. These parameters are referenced to the CAS* leading edge in early write cycles.
10. Operation within the t (max.) limit ensures that t (max.) limit can be met. t (max.) is specified as a reference point only.
RAD
RAD
RAC
If t
is greater than the specified t
(max.) limit, then access time is controlled by t
.
RAD
RAD
AA
11. Access time is determined by the longer of t , t
, or t
.
AA CAC
ACP
12.
t
defines RAS* pulse width in fast page mode cycles.
RASC
Physical Dimensions
168-pin (84x2) 3.3V DIMM
5.250
Note 3
5.171
5.014
0.158
1
11
40
41
84
Æ0.118
2.150
0.450
1.450
0.250
0.250
1.700
2.507
0.050
±0.004
4.550 (Ref.)
5.014
0.350
Front View
Notes:
1. All dimensions are in inches.
2. Pin 85 is behind pin 1 on the back side.
3. Thickness = 0.280 for TSOP DRAMs
= 0.350 for SOJ DRAMs
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
6
July 1997
Revision 1.0
EDC4BV7282B-60(J/T)G-S
Ordering Information
E D C 4 B V 72 82 B - 60 J G - S
(1) (2) (3) (4) (5) (6)
(7)
(8) (9) (10)
(11) (12) (13)
(14) (15)
(1) Memory Type
(9) Module Revision *1
F : Fast Page Mode (FPM)
E : Extended Data Out (EDO)
Blank : Rev. 0
A
B
:
:
Rev. 1
Rev. 2 (etc.)
(2) Module Shape
S : SIMM
*1 When DRAM device or PCB is
revised, the revision is changed
D : DIMM
O : Small Outline DIMM
(10) Power consumption
(3) Module Pin Count
A : 72-pin
Blank : Standard
L
:
Low Power
B : 144-pin
C : 168-pin
(11) Speed
D : 200-pin
50
60
70
:
50ns
60ns
70ns
:
:
(4) Word Depth
1 : 1M
2 : 2M
4 : 4M, etc.
(12) Package of Component
J
T
:
:
SOJ
TSOP
(5) Buffer Type
B : Buffered
(13) Module Lead Finish
U : Unbuffered
R : Registered
S
:
:
Solder Plate
Gold Plate
G
(6) Operating Voltage
N : 5V
(14) Private Brand Name *2
Blank : Common Products
V : 3,3V
G
:
FMG Brand
(7) Data Width
*2 This column is applicable to
custom modules, NOT applicable
to JEDEC standard commodity
products
(ex. 8=x8, 32=x32, 72=x72 etc.)
(8) Device Configuration / Refresh
41 : 1Mx4, 1K Refresh Cycle
42 : 4Mx4, 2K Refresh Cycle
44 : 4Mx4, 4K Refresh Cycle
82 : 2Mx8, 2K Refresh Cycle
14 : 1Mx16, 4K Refresh Cycle
11 : 1Mx16, 1K Refresh Cycle
(15) Assembly & Test Site
S
:
Smart Modular Technologies
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
7
July 1997
Revision 1.0
EDC4BV7282B-60(J/T)G-S
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Memory Marketing Dept.
4-1-1, Kamikodanaka Nakahara-ku,
Kawasaki 211-88, Japan
Tel: +81-44-754-3767
Fax: +81-44-754-3343
Internet: http://www.fujitsu.co.jp/
North and South America
FUJITSU MICROELECTRONICS, INC.
3545 North First Street
San Jose, CA 95134-1804, USA.
Tel: +1-408-922-9000
Fax: +1-408-922-9179
Customer Response Center (Mon-Fri: 7am-5pm (PST))
Tel: +1-800-866-8608
All Rights Reserved.
Fax: +1-408-922-9179
Circuit diagrams utilizing Fujitsu products are included
as a means of illustrating typical semiconductor appli-
cations. Complete information sufficient for construc-
tion purposes is not necessarily given.
Internet: http://www.fujitsumicro.com/
Europe
The information given in this document have been
carefully checked and is believed to be reliable. How-
ever, Fujitsu assumes no responsibility for inaccura-
cies.
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
63303 Dreieich–Buchschlag
Germany
Tel: +49-6103-690-0
Fax: +49-6103-690-122
The information contained in this document does not
convey any licence under the copyrights, patent rights
or trademarks claimed and owned by Fujitsu.
Internet: http://www.fujitsu-ede.com/
Fujitsu reserves the right to change products or specifi-
cations without notice.
Asia
No part of this publication may be copied or reproduced
in any form or by any means, or transferred to any third
party without prior written consent of Fujitsu.
FUJITSU MICROELECTRONICS ASIA PTE LIMITED
#05-08, 151 Lorong Chuan
NewTechPark
Singapore 556741
Tel: +65-281-0770
Fax: +65-281-0220
The information contained in this document are not
intended for use with equipments which require
extremely high reliability such as aerospace equip-
ments, undersea repeaters, nuclear control systems or
medical equipments for life support.
Internet: http://www.fsl.com.sg/
ã FUJITSU LIMITED 1997
PrintedinGermany
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
8
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