MB15E07LPFV1 [FUJITSU]
Single Serial Input PLL Frequency Synthesizer On-Chip 2.5 GHz Prescaler; 单串行输入锁相环频率合成片2.5 GHz的预分频器
| 型号： | MB15E07LPFV1 |
| 厂家： | 
FUJITSU |
| 描述： | Single Serial Input PLL Frequency Synthesizer On-Chip 2.5 GHz Prescaler |
| 文件： | 总23页 (文件大小：185K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-21355-1E
ASSP
Single Serial Input
PLL Frequency Synthesizer
On-Chip 2.5 GHz prescaler
MB15E07L
■ DESCRIPTION
The Fujitsu MB15E07L is serial input Phase Locked Loop (PLL) frequency synthesizer with a 2.5 GHz prescaler.
A 32/33 or a 64/65 can be selected for the prescaler that enables pulse swallow operation.
The latest BiCMOS process technology is used, resuItantly a supply current is limited as low as 4.5 mA typ. This
operates with a supply voltage of 3.0 V (typ.)
Furthermore, a super charger circuit is included to get a fast tuning as well as low noise performance. As a result
of this, MB15E07L is ideally suitable for digital mobile communications, such as GSM (Global System for Mobile
Communications).
■ FEATURES
• High frequency operation:2.5 GHz max. (@ P = 64/65)
2.0 GHz max. (@ P = 32/33)
• Low power supply voltage: VCC = 2.7 to 3.6 V
• Very Low power supply current: ICC = 4.5 mA typ. (VCC = 3 V)
• Power saving function: IPS = 0.1 µA typ. (VCC = 3 V)
• Pulse swallow function: 32/33 or 64/65
• Serial input 14-bit programmable reference divider: R = 5 to 16,383
• Serial input 18-bit programmable divider consisting of:
- Binary 7-bit swallow counter: 0 to 127
- Binary 11-bit programmable counter: 5 to 2,047
• Wide operating temperature: Ta = –40 to +85°C
• Plastic 16-pin SSOP package (FPT-16P-M05) and 16-pads BCC package (LCC-16P-M02)
■ PACKAGES
16-pin, plastic SSOP
16-pads, plastic BCC
(FPT-16P-M05)
(LCC-16P-M02)
MB15E07L
■ PIN ASSIGNMENTS
SSOP-16 pin
φR
OSCIN
OSCOUT
VP
1
2
3
16
15
14
φP
LD/fout
VCC
4
5
6
7
13
12
11
10
Top
View
ZC
PS
LE
DO
GND
Xfin
fin
Data
Clock
8
9
(FPT-16P-M05)
BCC-16 pads
OSCIN φR
16
15
view
8
OSCOUT
φP
1
2
3
14
13
12
VP
LD/fout
ZC
VCC
Top
7
DO
GND
Xfin
4
5
6
11
10
9
PS
LE
Data
fin Clock
(LCC-16P-M02)
2
MB15E07L
■ PIN DESCRIPTIONS
Pin no.
Pin
name
I/O
Descriptions
SSOP-16 BCC-16
Programmable reference divider input.
Oscillator input.
Connection for an crystal or a TCXO.
1
16
OSCIN
I
TCXO should be connected with a coupling capacitor.
Oscillator output.
Connection for an external crystal.
2
1
OSCOUT
O
3
4
2
3
VP
–
–
Power supply voltage input for the charge pump.
Power supply voltage input.
VCC
Charge pump output.
Phase of the charge pump can be reversed by FC bit.
5
6
7
4
5
6
DO
GND
Xfin
O
–
I
Ground.
Prescaler complementary input, and should be grounded via a
capacitor.
Prescaler input.
8
9
7
8
fin
I
I
Connection with an external VCO should be done with AC coupling.
Clock input for the 19-bit shift register.
Data is shifted into the shift register on the rising edge of the clock.
(Open is prohibited.)
Clock
Serial data input using binary code.
The last bit of the data is a control bit. (Open is prohibited.)
Control bit = “H” ; Data is transmitted to the programmable reference
counter.
10
9
Data
I
Control bit = “L” ; Data is transmitted to the programmable counter.
Load enable signal input (Open is prohibited.)
When LE is high, the data in the shift register is transferred to a latch,
according to the control bit in the serial data.
11
12
10
11
LE
PS
I
I
Power saving mode control. This pin must be set at “L” at Power-ON.
(Open is prohibited.)
PS = “H” ; Normal mode
PS = “L” ; Power saving mode
Forced high-impedance control for the charge pump (with internal pull
up resistor.)
ZC = “H” ; Normal DO output.
13
14
12
13
ZC
I
ZC = “L” ; DO becomes high impedance.
Lock detect signal output (LD)/phase comparator monitoring output
(fout).
The output signal is selected by LDS bit in the serial data.
LDS = “H” ; outputs fout (fr/fp monitoring output)
LDS = “L” ; outputs LD (“H” at locking, ”L” at unlocking.)
LD/fout
O
Phase comparator output for an external charge pump. Nch open
drain output.
15
16
14
15
φP
φR
O
O
Phase comparator output for an external charge pump. CMOS
output.
3
MB15E07L
■ BLOCK DIAGRAM
1
OSCIN
fr
Crystal
oscillator
circuit
φR
φP
16
15
fp
Phase
comparator
Programmable
reference divider
OSCOUT 2
LD
Binary 14-bit
reference counter
fr
Lock
detector
Intermittent
mode control
(power save)
SW
LDS
FC
12
11
PS
LE
17-bit latch
LD/fr/fp
selector
3-bit latch
14-bit latch
LE
14 LD/fout
fp
1-bit
control
latch
19-bit shift register
19-bit shift register
13
3
C
N
T
ZC
VP
10
9
Data
Super
charger
Clock
5
DO
18-bit latch
LE
11-bit latch
7-bit latch
SW
Programmable divider
Prescaler
32/33,
64/65
7
8
Xfin
fin
Binary 7-bit
swallow
counter
Binary 11-bit
programmable
counter
fp
GND
VCC
6
4
Control circuit
MD
Note: SSOP-16 pin
4
MB15E07L
■ ABSOLUTE MAXIMUM RATINGS
Rating
Parameter
Symbol
Unit
Remark
Min.
–0.5
VCC
–0.5
–0.5
–10
–25
–55
Max.
+4.0
+6.0
VCC
VP
VI
V
V
Power supply voltage
Input voltage
VCC +0.5
VCC +0.5
+10
V
Output voltage
VO
IO
V
mA
mA
°C
Except DO output
DO output
Output current
Ido
+25
Storage temperature
Tstg
+125
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Unit
Remark
Min.
2.7
Typ.
3.0
–
Max.
3.6
VCC
VP
VI
V
V
Power supply voltage
VCC
GND
–40
6.0
Input voltage
–
VCC
+85
V
Operating temperature
Ta
–
°C
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All
the device’s electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside
these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.
HandIing Precautions
• This device should be transported and stores in anti-static containers.
• This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are
properly grounded. Cover workbenches with grounded conductive mats.
• Always turn the power supply off before inserting or removing the device from its socket.
• Protect leads with a conductive sheet when handling or transporting PC boards with devices.
5
MB15E07L
■ ELECTRICAL CHARACTERISTICS
(VCC = 2.7 to 3.6 V, Ta = –40 to +85°C)
Value
Unit
Parameter
Symbol
Condition
Min.
Typ.
Max.
fin = 2500 MHz,
fosc = 12 MHz, P = 64/65
Power supply current*1
Power saving current
ICC*1
Ips*2
–
4.5
–
mA
ZC = “H” or open
P = 32/33
–
–
–
–
10
µA
100
100
2000
2500
Operating frequency
fin
MHz
MHz
P = 64/65
Crystal oscillator operating fre-
quency
fOSC
Vfin
min. 500 mVP-P
3
–
–
40
+2
50 Ω system
(Refer to the test circuit.)
fin*3
–10
dBm
VP-P
Input sensitivity
OSCIN*3
VOSC
VIH
–
0.5
VCC × 0.7
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
VCC
–
–
Data, Clock,
Input voltage
V
LE, PS, ZC
VIL
–
VCC × 0.3
+1.0
+1.0
+1.0
0
IIH*4
IIL*4
IIH*4
IIL*4
–
–1.0
–1.0
–1.0
–100
0
Data, Clock,
LE, PS
µA
µA
–
–
Input current
ZC
Pull up input
–
IIH
+100
0
OSCIN
µA
V
IIL*4
–
–100
–
φP
VOL
VOH
VOL
VDOH
VDOL
Open drain output
VCC = 3 V, IOH = –1 mA
VCC = 3 V, IOL = 1 mA
VCC = 3 V, IOH = –1 mA
VCC = 3 V, IOL = 1 mA
0.4
VCC – 0.4
–
–
φR,
V
LD/fout
Output voltage
0.4
VP – 0.4
–
–
DO
V
0.4
High impedance
cutoff current
VCC = 3 V, VP = 6 V
VOOP = GND to 6 V
DO
IOFF
–
–
3.0
nA
φP
IOL
IOH*4
IOL
Open drain output
1.0
–1.0
–
–
–
–
–
–
mA
–
–
φR,
LD/fout
mA
1.0
Output current
VCC = 3 V, VP = 3 V,
VDOH = 2.0 V, Ta = +25°C
IDOH*4, 5
IDOL*4
–11
8
–
–
–6
15
DO
mA
VCC = 3 V, VP = 3 V
VDOL = 1.0 V, Ta = +25°C
*1: Conditions; VCC = 3.0 V, Ta = +25°C, in locking state.
*2: VCC = 3.0 V, fosc = 12.8 MHz, Ta = +25°C, in power saving mode.
*3: AC coupling with a 1000 pF capacitor connected.
*4: The symbol “–” (minus) means direction of current flow.
*5: Ta = +25°C
6
MB15E07L
■ FUNCTION DESCRIPTIONS
1. Pulse Swallow Function
The divide ratio can be calculated using the following equation:
fVCO = [(M × N) + A] × fOSC ÷ R (A < N)
fVCO : Output frequency of external voltage controlled oscillator (VCO)
N
A
: Preset divide ratio of binary 11-bit programmable counter (5 to 2,047)
: Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127)
fOSC : Output frequency of the reference frequency oscillator
R
M
: Preset divide ratio of binary 14-bit programmable reference counter (5 to 16,383)
: Preset divide ratio of modules prescaler (32 or 64)
2. Serial Data Input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference
divider and the programmable divider separately.
Binary serial data is entered through the Data pin.
One bit of data is shifted into the shift register on the rising edge of the clock. When the load enable pin is high,
stored data is latched according to the control bit data as follows:
Table.1 Control Bit
Control bit (CNT)
Destination of serial data
17 bit latch (for the programmable reference divider)
18 bit latch (for the programmable divider)
H
L
(1) Shift register configuration
Programmable reference counter
MSB
Data flow
LSB
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
C
N
T
R
1
R
2
R
3
R
4
R
5
R
6
R
7
R
8
R
9
R
R
R
R
R
10 11 12 13 14 SW FC LDS
CNT
: Control bit
[Table. 1]
[Table. 2]
[Table. 5]
[Table. 7]
[Table. 6]
R1 to R14 : Divide ratio setting bit for the programmable reference counter (5 to 16,383)
SW
FC
: Divide ratio setting bit for the prescaler (32/33 or 64/65)
: Phase control bit for the phase comparator
: LD/fout signal select bit
LDS
Note: Start data input with MSB first
7
MB15E07L
Programmable reference counter
MSB
N
Data flow
LSB
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
C
N
T
A
1
A
2
A
3
A
A
5
A
6
A
7
N
1
N
2
N
3
N
4
N
5
N
6
N
7
N
8
N
9
N
4
10 11
CNT
: Control bit
[Table. 1]
[Table. 3]
[Table. 4]
N1 to N11 : Divide ratio setting bits for the programmable counter (5 to 2,047)
A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127)
Note: Start data input with MSB first
Table.2 Binary 14-bit Programmable Reference Counter Data Setting
Divide
R
R
R
R
R
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
ratio
(R)
14
13
12
11
10
5
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note: • Divide ratio less than 5 is prohibited.
Table.3 Binary 11-bit Programmable Counter Data Setting
Divide
N
N
N
9
N
8
N
7
N
6
N
5
N
4
N
3
N
2
N
1
ratio
(N)
11
10
5
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
2047
1
1
1
1
1
1
1
1
1
1
1
Note: • Divide ratio less than 5 is prohibited.
8
MB15E07L
Table.4 Binary 7-bit Swallow Counter Data Setting
Divide
A
7
A
6
A
5
A
4
A
3
A
2
A
1
ratio
(A)
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
127
1
1
1
1
1
1
1
Table.5 Prescaler Data Setting
SW
H
Prescaler divide ratio
32/33
64/65
L
Table.6 LD/fout Output Select Data Setting
LDS
LD/fout output signal
H
L
fout signal
LD signal
(2) Relation between the FC input and phase characteristics
The FC bit changes the phase characteristics of the phase comparator. Both the internal charge pump output
level (DO) and the phase comparator output (φR, φP) are reversed according to the FC bit. Also, the monitor
pin (fout) output is controlled by the FC bit. The relationship between the FC bit and each of DO, φR, and φP is
shown below.
Table.7 FC Bit Data Setting (LDS = “H”)
FC = High
FC = Low
φR
DO
H
φR
φP
L
LD/fout
fout = fr
DO
L
φP
Z*
L
LD/fout
fout = fp
fr > fp
fr < fp
fr = fp
L
H
L
H
L
L
L
Z*
Z*
H
Z*
Z*
Z*
* : High impedance
9
MB15E07L
When designing a synthesizer, the FC pin setting depends on the VCO and LPF characteristics.
(1)
:
:
When the LPF and VCO characteristics are
similar to (1), set FC bit high.
When the VCO characteristics are similar to
(2), set FC bit low.
VCO
output
frequency
PLL
LPF
VCO
(2)
LPF input voltage
Table.8 PS Pin Setting
Table.9 ZC Pin Setting
PS pin
Status
H
L
Normal mode
Power saving mode
ZC pin
DO output
H
L
Normal output
High impedance
10
MB15E07L
3. Power Saving Mode (Intermittent Mode Control Circuit)
Setting a PS pin to Low, the IC enters into power saving mode resultatly current consumption can be limited to
10 µA (max.). Setting PS pin to High, power saving mode is released so that the IC works normally.
In addition, the intermittent operation control circuit is included which helps smooth start up from the power
saving mode.In general, the power consumption can be saved by the intermittent operation that powering down
or waking up the synthesizer. Such case, if the PLL is powered up uncontrolled, the resulting phase comparator
output signal is unpredictable due to an undefined phase relation between reference frequency (fr) and
comparison frequency (fp) and may in the worst case take longer time for lock up of the loop.
Topreventthis, theintermittentoperationcontrolcircuitenforcesalimitederrorsignaloutputofthephasedetector
during power up, thus keeping the loop locked.
During the power saving mode, the corresponding section except for indispensable circuit for the power saving
function stops working, then current consumption is reduced to 10 µA (max.).
Note: • While the power saving mode is executed, ZC pin should be set at “H” or open. If ZC is set at “L”
during power saving mode, approximately 10 µA current flows.
• PS pin must be set “L” at Power-ON.
• The power saving mode can be released (PS : L → H) 1µs later after power supply remains stable.
• During the power saving mode, it is possible to input the serial data.
ON
VCC
Clock
Data
LE
PS
(1)
(2)
(3)
(1) PS = L (power saving mode) at Power-ON
(2) Set serial data after power supply remains stable.
(3) Relase power saving mode (PS : L → H) after setting serial data.
11
MB15E07L
4. Serial Data Input Timing
1st. data
2nd. data
Control bit Invalid data
LSB
~
Data
MSB
~
~
Clock
t1
t3
t2
t6
t7
LE
~
t4
t5
On rising edge of the clock, one bit of the data is transferred into the shift register.
Parameter
Min.
Typ. Max.
Unit
Parameter
Min.
Typ. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
t1
t2
t3
t4
20
20
30
30
–
–
–
–
–
–
–
–
t5
t6
t7
100
20
–
–
–
–
–
–
100
12
MB15E07L
■ PHASE COMPARATOR OUTPUT WAVEFORM
fr
fp
tWU
tWL
LD
[ FC = “H” ]
φP
φR
H
DO
Z
L
[ FC = “L” ]
φP
φR
H
DO
Z
L
Notes: 1. Phase error detection range: –2π to +2π
2. Pulses on DO output signal during locked state are output to prevent dead zone.
3. LD output becomes low when phase is tWU or more. LD output becomes high when phase error is tWL
or less and continues to be so for three cycles or more.
4. tWU and tWL depend on OSCIN input frequency.
tWU > 4/fosc (e. g. tWU > 312.5 ns, foscin = 12.8 MHz)
tWL < 8/fosc (e. g. tWL < 625.0 ns, foscin = 12.8 MHz)
5. LD becomes high during the power saving mode (PS = “L”.)
13
MB15E07L
■ TYPICAL CHARACTERISTICS
1. fin Input Sensitivity
Input frequency vs. Input sensitivity (Prescaler = 64/65)
(dBm)
+10
Ta = +25°C
0
–10
–20
–30
SPEC
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
–40
0
1000
2000
3000 (MHz)
Input frequency (fin)
Input frequency vs. Input sensitivity (Prescaler = 32/33)
(dBm)
+10
Ta = +25°C
0
–10
–20
–30
SPEC
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
–40
0
1000
2000
3000 (MHz)
Input frequency (fin)
14
MB15E07L
2. OSCIN Input Sensitivity
Input frequency vs. Input sensitivity
(dBm)
+10
SPEC
Ta = +25°C
0
–10
–20
–30
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
–40
0
50
100
150 (MHz)
Input frequency (fosc)
15
MB15E07L
3. DO Output Current
IOH vs. VOH
(V)
5.000
Ta = +25°C
VCC = 3.0 V
VP = 3.0 V, 5.0 V
.5000
/div
.0000
.0000
IDO
2.500/div
(mA)
–25.00
IOH
IOL vs. VOL
(V)
5.000
Ta = +25°C
VCC = 3.0 V
VP = 3.0 V, 5.0 V
.5000
/div
.0000
.0000
IDO
2.500/div
(mA)
–25.00
IOL
16
MB15E07L
4. fin Input Impedance
1; 10.715 Ω
–50.275 Ω
1 GHz
2; 11.118 Ω
–10.846 Ω
1.5 GHz
4
3
3; 16.718 Ω
20.081 Ω
2 GHz
4; 43.439 Ω
38.307 Ω
2.5 GHz
2
1
5. OSCIN Input Impedance
1; 4.656 kΩ
–19.064 kΩ
3 MHz
2; 704.75 Ω
–5.3735 kΩ
10 MHz
3; 388.25 Ω
–2.775 kΩ
20 MHz
4
3
4; 136.38 Ω
–1.5275 kΩ
40 MHz
17
MB15E07L
■ TEST CIRCUIT (FOR MEASURING INPUT SENSITIVITY fin/OSCIN)
VCC VP
0.1 µF
1000 pF
1000 pF
S • G
S • G
0.1 µF
1000 pF
50 Ω
50 Ω
8
7
6
5
4
3
2
1
9 10 11 12 13 14 15 16
Oscilloscope
Controller
(setting divide ratio)
VCC
Note: SSOP-16 pin
18
MB15E07L
■ APPLICATION EXAMPLE
Output
LPF
VCO
VP
10 kΩ
12 kΩ
12 kΩ
Lock detect.
10 kΩ
From
a controller
φR
φP
LD/fout ZC
PS
LE
Data
Clock
16
15
14
13
12
11
10
9
MB15E07L
1
2
3
4
5
6
7
8
OSCIN OSCOUT VP
VCC
DO
GND
Xfin
1000 pF
fin
1000 pF
X’ tal
C2
C1
0.1 µF
0.1 µF
C1, C2: Depend on the crystal parameters
VP: 6V max.
Note: SSOP-16 pin
19
MB15E07L
■ ORDERING INFORMATION
Part number
Package
Remarks
16-pin, plastic SSOP
(FPT-16P-M05)
MB15E07LPFV1
16-pads, plastic BCC
(LCC-16P-M02)
MB15E07LPV
20
MB15E07L
■ PACKAGE DIMENSIONS
* : These dimensions do not include resin protrusion.
16-pin, plastic SSOP
(FPT-16P-M05)
+0.20
*
5.00±0.10(.197±.004)
1.25–0.10
(Mounting height)
.049+–..000048
0.10(.004)
INDEX
*
4.40±0.10
6.40±0.20
5.40(.213)
NOM
(.173±.004) (.252±.008)
"A"
0.15+–00..0025
+0.10
Details of "A" part
0.65±0.12
(.0256±.0047)
0.22–0.05
+.004
+.002
.009–.002
.006–.001
0.10±0.10(.004±.004)
(STAND OFF)
0
10°
0.50±0.20
(.020±.008)
4.55(.179)REF
Dimensions in mm (inches
)
C
1994 FUJITSU LIMITED F16013S-2C-4
(Continued)
21
MB15E07L
(Continued)
16-pins, plastic BCC
(LCC-16P-M02)
* : These dimensions do not include resin protrusion.
4.55±0.10
(.179±.004)
0.80(.032)MAX
3.40(.134)TYP
0.65(.026)TYP
(Mouting height)
14
9
9
14
0.40±0.10
(.016±.004)
2.45(.096)
TYP
3.40±0.10
(.1339±.0039)
45˚
"A"
1.15(.045)TYP
"B"
0.80(.032)
TYP
E-MARK
0.40(.016)
0.325±0.10
(.013±.004)
1.725(.068)
TYP
1
6
6
1
0.085±0.04
(.003±.002)
(STAND OFF)
Details of "A" part
Details of "B" part
0.75±0.10
(.030±.004)
0.60±0.10
(.024±.004)
0.05(.002)
0.40±0.10
(.016±.004)
0.60±0.10
(.024±.004)
Dimensions in mm (inches
)
C
1996 FUJITSU LIMITED C16013S-1C-1
22
MB15E07L
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
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Tel: (044) 754-3753
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The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
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http://www.fujitsu.co.jp/
The information and circuit diagrams in this document presented
as examples of semiconductor device applications, and are not
intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the
use of this information or circuit diagrams.
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, U.S.A.
Tel: (408) 922-9000
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
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Tel: (800) 866-8608
Fax: (408) 922-9179
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FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Any semiconductor devices have inherently a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
Fax: (06103) 690-122
http:.//www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LIMITED
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281 0770
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required
for export of those products from Japan.
Fax: (65) 281 0220
http://www.fmap.com.sg/
F9710
FUJITSU LIMITED Printed in Japan
23
相关型号：
MB15E07SLWQN
PLL Frequency Synthesizer, BICMOS, PQCC16, 4 X 4 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, PLASTIC, QFN-16
FUJITSU
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