MB15F73SPPFT [FUJITSU]
Dual Serial Input PLL Frequency Synthesizer; 双串行输入锁相环频率合成器
| 型号： | MB15F73SPPFT |
| 厂家： | 
FUJITSU |
| 描述： | Dual Serial Input PLL Frequency Synthesizer |
| 文件： | 总27页 (文件大小：257K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-21365-1E
ASSP
Dual Serial Input
PLL Frequency Synthesizer
MB15F73SP
■ DESCRIPTION
The Fujitsu MB15F73SP is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2000 MHz pres-
caler and a 600 MHz prescaler. A 64/65 or a 128/129 for the 2000 MHz prescaler, and a 8/9 or a 16/17 for the 600
MHz prescaler can be selected for the prescaler that enables pulse swallow operation.
MB15F73SP has the same configuration with MB15F03 or MB15F03L. The BiCMOS process is used , as a result
a supply current is typically 3.5 mA at 2.7 V. The supply voltage range is from 2.4 V to 3.6 V. A refined charge
pump supplies well-balanced output current with 1.5 mA and 6 mA selectable by serial data.
The new package (BCC20) decreases an area of MB15F73SP more than 30 % comparing with the former BCC16
(for dual PLL).
MB15F73SP is ideally suited for wireless mobile communications, such as PDC.
■ FEATURES
• High frequency operation
: RF synthesizer : 2000 MHz max
: IF synthesizer : 600 MHz max
: VCC = 2.4 to 3.6 V
• Low power supply voltage
• Ultra Low power supply current : ICC = 3.5 mA typ.
(VCC = Vp = 2.7 V, Ta = +25°C, SWIF = SWRF = 0 in IF/RF locking state)
(Continued)
■ PACKAGES
20-pin plastic TSSOP
20-pad plastic BCC
(FPT-20P-M06)
(LCC-20P-M04)
MB15F73SP
(Continued)
• Direct power saving function: Power supply current in power saving mode
Typ. 0.1 µA (VCC = Vp = 2.7 V, Ta = +25°C)
Max. 10 µA (VCC = Vp = 2.7 V)
• Software selectable charge pump current: 1.5 mA/6.0 mA typ.
• Dual modulus prescaler: 2000 MHz prescaler (64/65 or128/129 )/600 MHz prescaler (8/9 or 16/17)
• 23 bit shift register
• Serial input binary 14-bit programmable reference divider: R = 3 to 16,383
• Serial input programmable divider consisting of:
- Binary 7-bit swallow counter: 0 to 127
- Binary 11-bit programmable counter: 3 to 2,047
• Built-in high-speed tuning, low-noise phase comparator, current-switching type constant current circuit
• On–chip phase control for phase comparator
• Built-in digital locking detector circuit to detect PLL locking and unlocking
• Operating temperature: Ta = –40 to +85°C
• Sireal data format compatible with MB15F02SL
■ PIN ASSIGNMENTS
(TSSOP-20)
TOP VIEW
(BCC-20)
TOP VIEW
OSCIN Data
GND Clock
OSCIN
GND
finIF
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
Clock
Data
finIF
1
16
LE
20 19 18 17
LE
XfinIF
GNDIF
VCCIF
PSIF
2
3
4
5
15
14
13
12
finRF
XfinIF
GNDIF
VCCIF
PSIF
finRF
XfinRF
GNDRF
VCCRF
XfinRF
GNDRF
VCCRF
PSRF
VpRF
DoRF
VpIF
7
8
9 10
11
VpIF
6
PSRF
DoIF
DoIF
DoRF
LD/fout 10
LD/fout VpRF
(LCC-20P-M04)
(FPT-20P-M06)
2
MB15F73SP
■ PIN DESCRIPTION
Pin no.
Pin
I/O
Descriptions
name
TSSOP BCC
The programmable reference divider input. TCXO should be connected with a AC
coupling capacitor.
1
2
3
19
20
1
OSCIN
GND
finIF
I
Ground for OSC input buffer and the shift register circuit.
Prescaler input pin for the IF-PLL.
Connection to an external VCO should be AC coupling.
I
I
Prescaler complimentary input for the IF-PLL section.
This pin should be grounded via a capacitor.
4
5
6
2
3
4
XfinIF
GNDIF
VCCIF
Ground for the IF-PLL section.
Power supply voltage input pin for the IF-PLL section (except for the charge
pump circuit), the shift register and the oscillator input buffer.
Power saving mode control for the IF-PLL section. This pin must be set at "L"
Power-On. (Open is prohibited.)
7
5
PSIF
I
PSIF = "H" ; Normal mode / PSIF = "L" ; Power saving mode
8
9
6
7
VpIF
Power supply voltage input pin for the IF-PLL charge pump.
Charge pump output for the IF-PLL section.
DoIF
O
O
O
Look detect signal output (LD)/ phase comparator monitoring output (fout). The
output signal is selected by a LDS bit in a serial data.
LDS bit = "H" ; outputs fout signal / LDS bit = "L" ; outputs LD signal
10
8
LD/fout
11
12
9
DoRF
Charge pump output for the RF-PLL section.
10
VpRF
Power supply voltage input pin for the RF-PLL charge pump.
Power saving mode control for the RF-PLL section. This pin must be set at "L"
Power-ON. (Open is prohibited. )
13
11
PSRF
I
PSRF = "H" ; Normal mode / PSRF = "L" ; Power saving mode
Power supply voltage input pin for the RF-PLL section (except for the charge
pump circuit).
14
15
16
12
13
14
VCCRF
GNDRF
XfinRF
Ground for the RF-PLL section.
Prescaler complimentary input for the RF-PLL section.
This pin should be grounded via a capacitor.
I
I
Prescaler input pin for the RF-PLL.
Connection to an external VCO should be AC coupling.
17
18
15
16
finRF
Load enable signal input (with the schmitt trigger circuit.)
When LE is set "H", data in the shift register is transferred to the corresponding
latch according to the control bit in a serial data.
LE
I
Serial data input (with the schmitt trigger circuit.)
19
20
17
18
Data
I
I
A data is transferred to the corresponding latch (IF-ref. counter, IF-prog. counter,
RF-ref. counter, RF-prog. counter) according to the control bit in a serial data.
Clock input for the 23-bit shift register (with the schmitt trigger circuit.)
One bit data is shifted into the shift register on a rising edge of the clock.
Clock
3
MB15F73SP
■ BLOCK DIAGRAM
VpIF
8
VCCIF
GNDIF
5
(
)
(
)
( )
6
4
6
3
Intermittent
mode control
(IF-PLL)
11 bit latch
7 bit latch
3 bit latch
PSIF
7
5
(
)
fpIF
Binary 7-bit
swallow counter
(IF-PLL)
Binary 11-bit
programable
counter (IF-PLL)
Phase
comp.
(IF-PLL)
Current
Switch
Charge
pump
(IF-PLL)
9
7
DoIF
LDS SWIF FCIF
(
)
finIF
3
1
Prescaler
(IF-PLL)
(8/9, 16/17)
Lock Det.
(IF-PLL)
(
)
)
XfinIF
4
2
(
1 bit latch
2 bit latch
14 bit latch
LDIF
Binary 14-bit pro-
grammable ref.
counter(IF-PLL)
C/P setting
counter
T1
T2
frIF
OSCIN
1
( )
19
Selector
AND
frRF
LD
frIF
frRF
fpIF
fpRF
Binary 14-bit pro-
grammable ref.
counter(RF-PLL)
C/Psetting
counter
T1
T2
10
LD/
OR
(
)
fout
8
2 bit latch
14 bit latch
1 bit latch
(
)
)
15
Prescaler
(RF-PLL)
(64/65, 128/129)
finRF 17
Lock Det.
(RF-PLL)
XfinRF 16
(
14
Phase
comp.
(RF-PLL)
Charge
pump
(RF-PLL)
Binary 11-bit
programmable
counter(RF-PLL)
Binary 7-bit
swallow counter
(RF-PLL)
Current
Switch
11
DoRF
LDS SWRF
FCRF
Intermittent
mode control
(RF-PLL)
(
)
9
PSRF 13
fpRF
11 bit latch
( )
11
7 bit latch
3 bit latch
Schmitt
circuit
LE 18
Latch selector
(
)
)
16
(
17
Schmitt
circuit
C
N
1
C
N
2
Data 19
23-bit shift register
Schmitt
circuit
Clock 20
(
)
18
2
(
)
(
12
)
14
15
(
13
)
12
(
10
)
20
VpRF
VCCRF
GND
GNDRF
O -- TSSOP
( ) -- BCC
4
MB15F73SP
■ ABSOLUTE MAXIMUM RATINGS
Rating
Parameter
Symbol
Unit
Min.
−0.5
VCC
Max.
4.0
VCC
Vp
V
V
Power supply voltage
Input voltage
4.0
VI
−0.5
GND
GND
−55
VCC + 0.5
VCC
V
V
LD/fout
Do
VO
Output voltage
VDO
Tstg
Vp
V
Storage temperature
+125
°C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Unit
Min.
2.4
Typ.
2.7
Max.
3.6
VCC
Vp
VI
V
V
Power supply voltage
VCC
2.7
3.6
Input voltage
GND
−40
VCC
+85
V
Operating temperature
Ta
°C
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
5
MB15F73SP
*
■ ELECTRICAL CHARACTERISTICS
(VCC = 2.4 V to 3.6 V, Ta = −40 °C to +85 °C)
Value
Unit
Parameter
Power supply current
Power saving current
Symbol
Condition
Min.
Typ.
Max.
*1
ICCIF
IF PLL
1.3
mA
mA
*2
ICCRF
RF PLL
2.2
IPSIF
IPSRF
finIF
PSIF = PSRF = “L”
PSIF = PSRF = “L”
IF PLL
0.1*8
0.1*8
10
10
µA
µA
*3
finIF
50
100
3
600
2000
40
MHz
MHz
MHz
dBm
dBm
VP−P
*3
Operating frequency
finRF
finRF
fOSC
RF PLL
OSCIN
finIF
PfinIF
IF PLL, 50 Ω system
−15
−15
0.5
+2
Input sensitivity
finRF
PfinRF RF PLL, 50 Ω system
+2
Input available voltage OSCIN
VOSC
VCC
0.7 VCC
+ 0.4
“H” level input voltage
Data
IH
Schmitt triger input
Schmitt triger input
V
V
V
LE
0.3 VCC
− 0.4
Clock
“L” level input voltage
VIL
“H” level input voltage
“L” level input voltage
VIH
0.7 VCC
V
V
PSIF
PSRF
VIL
0.3 VCC
*4
Data
LE
Clock
PS
“H” level input current
“L” level input current
IIH
−1.0
−1.0
+1.0
µA
µA
*4
IIL
+1.0
“H” level input current
“L” level input current
“H” level output voltage
“L” level output voltage
“H” level output voltage
“L” level output voltage
IIH
0
+100
µA
µA
V
OSCIN
*4
IIL
−100
0
VOH
VOL
VCC = Vp = 2.7 V, IOH = −1 mA VCC − 0.4
VCC = Vp = 2.7 V, IOL = 1 mA
LD/
fout
0.4
V
VDOH
VDOL
VCC = Vp = 2.7 V, IDOH = −0.5 mA Vp − 0.4
VCC = Vp = 2.7 V, IDOL = 0.5 mA
V
DoIF
DoRF
0.4
2.5
V
High impedance cutoff DoIF
current
VCC = Vp = 2.7 V
VOFF = 0.5 V to Vp − 0.5 V
IOFF
nA
DoRF
*4
“H” level output current
“L” level output current
IOH
VCC = Vp = 2.7 V
−1.0
mA
mA
LD/
fout
IOL
VCC = Vp = 2.7 V
1.0
(Continued)
6
MB15F73SP
(Continued)
(VCC = 2.4 V to 3.6 V, Ta = −40 °C to +85 °C)
Value
Unit
Parameter
Symbol
Condition
VCC = Vp = 2.7 V,
VDOH = Vp /2,
Ta = +25 °C
Min.
Typ.
Max.
CS bit = “H”
CS bit = “L”
CS bit = “H”
CS bit = “L”
−6.0
mA
mA
mA
mA
“H” level output
current
DoIF
DoRF
*4
IDOH
−1.5
6.0
VCC = Vp = 2.7 V,
VDOL = Vp /2,
Ta = +25 °C
“L” level output
current
DoIF
DoRF
IDOL
*5
1.5
IDOL/IDOH IDOMT
VDO = Vp / 2
3
%
%
*6
*7
Charge pump
current rate
vs VDO
IDOVD
0.5 V ≤ VDO ≤ Vp − 0.5 V
10
−40 °C ≤ Ta ≤ 85 °C,
VDO = Vp / 2
vs Ta
IDOTA
10
%
*1 : finIF = 480 MHz, fosc = 12.8 MHz, VCCIF = VpIF = 2.7 V, SWIF = 0, Ta = + 25 °C, in locking state.
*2 : finRF = 2000 MHz, fosc = 12.8 MHz, VCCRF = VpRF = 2.7 V, SWRF = 0, Ta = + 25 °C, in locking state.
*3 :AC coupling. 1000 pF capacitor is connected under the condition of minimum operating frequency.
*4 : The symbol “–” (minus) means direction of current flow.
*5 : VCC = Vp = 2.7 V, Ta = + 25 °C
(||I3| – |I4||) / [ (|I3| + |I4|) / 2 ] × 100 (%)
*6 : VCC = Vp = 2.7 V, Ta = + 25 °C (Applied to each IDOL, IDOH)
[ (||I2| – |I1||) / 2 ] / [ (|I1| + |I2|) / 2 ] × 100 (%)
*7 : VCC = Vp = 2.7 V, Ta = + 25 °C (Applied to each IDOL, IDOH)
[ ||IDO (85°C) | – |IDO (–40°C) || / 2 ] / [ |IDO (85°C) | + |IDO (–40°C) | / 2 ] × 100 (%)
*8 : fosc = 12.8 MHz, VCCRF = VpRF = VCCIF = VpIF = 2.7 V, Ta = + 25 °C
I3
I4
I1
I2
I2
IDOL
IDOH
I1
0.5
Vp/2
Vp − 0.5
Vp
Charge pump output voltage (V)
7
MB15F73SP
■ FUNCTIONAL DESCRIPTION
1. Pulse swallow function
fVCO = [(P × N) + A] × fOSC ÷ R
fVCO : Output frequency of external voltage controlled oscillator (VCO)
P
N
A
: Preset divide ratio of dual modulus prescaler (8 or 16 for IF-PLL, 64or 128 for RF-PLL)
: Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
: Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127, A < N)
fOSC : Reference oscillation frequency (OSCIN input frequency)
: Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
R
2. Serial Data Input
Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF-PLL sec-
tions, programmable reference dividers of IF/RF-PLL sections are controlled individually.
Serial data of binary data is entered through Data pin.
On rising edge of Clock, one bit of serial data is transferred into the shift register. On a rising edge of load enable
signal, the data stored in the shift register is transferred to one of latch of them depending upon the control bit data
setting.
The programmable The programmable
The programmable
The programmable
reference counter reference counter counter and the swallow counter and the swallow
for the IF-PLL
for the RF-PLL
counter for the IF-PLL
counter for the RF-PLL
CN1
CN2
0
0
1
0
0
1
1
1
(1) Shift Register Configuration
• Programmable Reference Counter
Data Flow
(LSB)
(MSB)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CN1 CN2 T1 T2 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 CS X
X
X
X
CS
: Charge pump current select bit
R1 to R14 : Divide ratio setting bits for the programmable reference counter (3 to 16,383)
T1, 2
CN1, 2
X
: Test purpose bit
: Control bit
: Dummy bits (Set “0” or “1”)
Note : Data input with MSB first.
8
MB15F73SP
• Programmable Counter
Data Flow
(LSB)
(MSB)
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CN1 CN2 LDS
A1 A2 A3 A4 A5 A6 A7 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11
SWIF/RF FCIF/RF
A1 to A7
: Divide ratio setting bits for the swallow counter (0 to 127)
: Divide ratio setting bits for the programmable counter (3 to 2,047)
: LD/fout signal select bit
N1 to N11
LDS
: Divide ratio setting bit for the prescaler
SWIF/RF
(8/9 or 16/17 for the SWIF, 64/65 or 128/129 for the SWRF)
FCIF/RF
CN1, 2
: Phase control bit for the phase detector (IF: FCIF, RF: FCRF)
: Control bit
Note : Data input with MSB first.
(2) Data setting
• Binary 14-bit Programmable Reference Counter Data Setting
Divide ratio R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1
3
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
•
0
•
0
•
0
•
0
•
0
•
0
•
0
•
0
•
0
•
0
•
0
•
1
•
0
•
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note : Divide ratio less than 3 is prohibited.
• Binary 11-bit Programmable Counter Data Setting
Divide ratio N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1
3
0
0
0
0
0
0
0
0
0
1
1
4
•
0
•
0
•
0
•
0
•
0
•
0
•
0
•
0
•
1
•
0
•
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2047
1
1
1
1
1
1
1
1
1
1
1
Note : Divide ratio less than 3 is prohibited
• Binary 7-bit Swallow Counter Data Setting
Divide ratio A7 A6 A5 A4 A3 A2 A1
0
0
0
0
0
0
0
0
1
•
0
•
0
•
0
•
0
•
0
•
0
•
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
127
1
1
1
1
1
1
1
9
MB15F73SP
• Prescaler Data Setting
Divide ratio
SW = “H”
8/9
SW = “L”
16/17
Prescaler divide ratio IF-PLL
Prescaler divide ratio RF-PLL
128/129
64/65
• Charge Pump Current Setting
• LD/fout Output Select Data Setting
Current value
±6.0 mA
CS
1
LD/fout output signal
fout signals
LDS
1
0
±1.5 mA
0
LD signal
• Test Purpose Bit Setting
LD/fout pin state
Outputs frIF.
T1
0
T2
0
Outputs frRF.
1
0
Outputs fpIF.
0
1
Outputs fpRF.
1
1
• Phase Comparator Phase Switching Data Setting
FCIF, RF = “H”
Phase comparator input
DoIF, RF
FCIF, RF = “L”
DoIF, RF
fr > fp
fr < fp
H
L
L
H
Z
fr = fp
Z
Z : High-impedance
Depending upon the VCO and LPF polarity, FC bit should be set.
High
(1)
(1) VCO polarity FC = “H”
(2) VCO polarity FC = “L”
VCO Output
Frequency
(2)
Max.
LPF Output voltage
Note : Give attention to the polarity for using active type LPF.
10
MB15F73SP
3. Power Saving Mode (Intermittent Mode Control Circuit)
Status
PS pin
Normal mode
H
L
Power saving mode
The intermittent mode control circuit reduces the PLL power consumption.
By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See
the Electrical Characteristics chart for the specific value.
The phase detector output, Do, becomes high impedance.
For the single PLL, the lock detector, LD, remains high, indicating a locked condition.
For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table.
Setting the PS pin high, releases the power saving mode, and the device works normally.
The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation.
When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is be-
cause of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which
can cause a major change in the comparaor output, resulting in a VCO frequency jump and an increase in lockup
time.
To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error sig-
nal from the phase detector when it returns to normal operation.
Note : When power (VCC) is first applied, the device must be in standby mode, PS = Low, for at least 1µs.
Note : PS pin must be set "L" for Power-ON.
OFF
ON
VCC
tV ≥ 1 µs
Clock
Data
LE
PS
tPS ≥ 100 ns
(1)
(2)
(3)
(1) PS = L (power saving mode) at Power-ON
(2) Set serial data 1 µs later after power supply remains stable (VCC > 2.2 V).
(3) Release power saving mode (PS : L → H) 100 ns later after setting serial data.
11
MB15F73SP
4. SERIAL DATA INPUT TIMING
Frequency multiplier setting is performed through a serial interface using the Data pin, Clock pin, and LE pin.
Setting data is read into the shift register at the rise of the clock signal, and transferred to a latch at the rise of
the LE signal. The following diagram shows the data input timing.
1st data
2nd data
Invalid data
Control bit
Data
MSB
LSB
Clock
LE
t1
t2
t5
t4
t7
t3
t6
Parameter Min.
Typ.
Max.
Unit
ns
Parameter
Min. Typ. Max.
Unit
ns
t1
t2
t3
t4
20
20
30
20
t5
t6
t7
30
ns
100
100
ns
ns
ns
ns
Note : LE should be “L” when the data is transferred into the shift register.
12
MB15F73SP
■ PHASE COMPARATOR OUTPUT WAVEFORM
frIF/RF
fpIF/RF
tWU
tWL
LD
(FC bit = High)
H
DoIF/RF
Z
L
(FC bit = Low)
H
DoIF/RF
Z
L
• LD Output Logic
IF-PLL section
Locking state/Power saving state
Locking state/Power saving state
Unlocking state
RF-PLL section
Locking state/Power saving state
Unlocking state
LD output
H
L
L
L
Locking state/Power saving state
Unlocking state
Unlocking state
Notes :• Phase error detection range = –2π to +2π
• Pulses on DoIF/RF signals during locking state are output to prevent dead zone.
• LD output becomes low when phase error is tWU or more.
• LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more.
• tWU and tWL depend on OSCIN input frequency as follows.
tWU > 2/fosc: e.g. tWU > 156.3 ns when fosc = 12.8 MHz
tWU < 4/fosc: e.g. tWL < 312.5 ns when fosc = 12.8 MHz
13
MB15F73SP
■ TEST CIRCUIT (for Measuring Input Sensitivity fin/OSCIN)
fout
Oscilloscope
1000 pF
VpIF
VCCIF
1000 pF
S.G.
50 Ω
0.1 µF
0.1 µF
1000 pF
S.G.
50 Ω
LD/fout
10
DoIF
9
VpIF
PSIF
VCCIF
GNDIF
XfinIF
4
finIF
3
GND
2
OSCIN
8
7
6
5
1
11
12
13
14
15
16
17
18
LE
19
20
DoRF
VpRF
PSRF
VCCRF GNDRF XfinRF
finRF
Data
Clock
1000 pF
Controller
(divide ratio setting)
1000 pF
VpRF
VCCRF
S.G.
50 Ω
0.1 µF
0.1 µF
Note : The terminal number shows that of TSSOP-20.
14
MB15F73SP
■ TYPICAL CHARACTERISTICS
1. fin input sensitivity
RF-PLL input sensitivity - Input frequency
10.0
0.0
SPEC
−10.0
−20.0
−30.0
−40.0
−50.0
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
0
500
1000
1500
2000
2500
Input frequency finRF (MHz)
IF-PLL input sensitivity - Input frequency
10.0
0.0
SPEC
−10.0
−20.0
−30.0
−40.0
−50.0
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
0
100
200
300
400
500
600
700
Input frequency finIF (MHz)
15
MB15F73SP
2. OSCIN input sensitivity
Input sensitivity - Input frequency
Ta = +25 °C
10
SPEC
0
−10
−20
−30
−40
−50
−60
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
0
20
40
60
80
100
120
140
160
180
200
220
Input frequency fOSC (MHz)
16
MB15F73SP
3. RF-PLL Do output current
• 1.5 mA mode
IDO - VDO
10.0
Ta = +25 °C
VCC = Vp = 2.7 V
IDOL
0.0
IDOH
−10.0
0.0
1.0
2.0
2.7
Charge pump output voltage VDO (V)
• 6.0 mA mode
IDO - VDO
10.0
Ta = +25 °C
VCC = Vp = 2.7 V
IDOL
0.0
IDOH
−10.0
0.0
1.0
2.0
2.7
Charge pump output voltage VDO (V)
17
MB15F73SP
4. IF-PLL Do output current
• 1.5 mA mode
IDO − VDO
10.0
Ta = +25 °C
VCC = Vp = 2.7 V
IDOL
IDOH
0.0
−10.0
2.7
0.0
1.0
2.0
Charge pump output voltage VDO (V)
• 6.0 mA mode
IDO − VDO
10.0
Ta = +25 °C
VCC = Vp = 2.7 V
IDOL
0.0
IDOH
−10.0
1.0
2.0
2.7
0.0
Charge pump output voltage VDO (V)
18
MB15F73SP
5. fin input impedance
finIF input impedance
4 : 17.262
Ω
−115.55
Ω
2.2956 pF
600.000 000 MHz
1 : 669.97
Ω
−1.0088 kΩ
50 MHz
2 :
72.875
−351.75
Ω
Ω
200 MHz
3 :
27.047
−178.02
Ω
Ω
400 MHz
1
2
4
3
START 50.000 000 MHz
STOP 600.000 000 MHz
finRF input impedance
4 : 13.596 Ω
−5.6699 Ω
14.035 pF
2 000.000 000 MHz
1 : 289.69 Ω
−647.06 Ω
100 MHz
2 :
12.887 Ω
−65.199 Ω
1 GHz
3 :
11.751 Ω
−30.16 Ω
1.5 GHz
4
1
3
2
START 100.000 000 MHz
STOP 2 000.000 000 MHz
19
MB15F73SP
6. OSCIN input impedance
OSCIN input impedance
4 : 31.813 Ω
−679.69 Ω
2.3416 pF
100.000 000 MHz
1 :12.425 kΩ
−10.812 kΩ
3 MHz
2 :
524 Ω
−3.3809 kΩ
20 MHz
3 :
128.94 Ω
−1.7113 kΩ
40 MHz
4
3
1
2
START 3.000 000 MHz
STOP 100.000 000 MHz
20
MB15F73SP
■ REFERENCE INFORMATION
(for Lock-up Time, Phase Noise and Reference Leakage)
fVCO = 1624 MHz VCC = 3.0 V
KV = 22 MHz/V
fr = 10 kHz
fOSC = 19.68 MHz CP : 6 mA mode
VVCO = 3.0 V
Ta = + 25 °C
Test Circuit
OSCIN
S.G.
LPF
Do
LPF
fin
10 k Ω
4.1 k Ω
Spectrum
Analyzer
VCO
3900 pF
3300 pF
0.047 µF
• PLL Reference Leakage
ATTEN 10 dB VAVG 25
∆MKR −70.00 dB
10.0 kHz
RL 0 dBm
10 dB/
∆MKR
10.0 kHz
−70.00 dB
D
S
CENTER 1.6240000 GHz
VBW 300 Hz
SPAN 100.0 kHz
SWP 2.80 sec
RBW 300 Hz
• PLL Phase Noise
ATTEN 10 dB VAVG 20
∆MKR −43.00 dB
1.18 kHz
RL 0 dBm
10 dB/
∆MKR
1.18 kHz
−43.00 dB
D
S
CENTER 1.62400000 GHz
VBW 100 Hz
SPAN 10.00 kHz
SWP 802 ms
RBW 100 Hz
(Continued)
21
MB15F73SP
(Continued)
PLL Lock Up time
953 MHz→981 MHz within ± 1 kHz
PLL Lock Up time
981 MHz→953 MHz within ± 1 kHz
L ch→H ch
4.822 ms
H ch→L ch
4.956 ms
1.646004500 GHz
1.646000500 GHz
1.624004750 GHz
1.624000750 GHz
1.645996500 GHz
1.623996750 GHz
−2.178 ms
2.822 ms
7.822 ms
∆ 4.822 ms
−2.178 ms
2.822 ms
7.822 ms
∆ 4.956 ms
1.000 ms/div
1.000 ms/div
T1 489 µs
T2 5.311 ms
T1 489 µs
T2 5.444 ms
22
MB15F73SP
■ APPLICATION EXAMPLE
OUTPUT
VCO
2.7 V
LPF
2.7 V
from controller
1000 pF
1000 pF
0.1 µF 0.1 µF
Clock DATA
LE
18
finRF
17
XfinRF GNDRF
VCCRF
PSRF
VpRF
DoRF
20
19
16
15
14
13
12
11
MB 15F73SP
1
2
3
4
5
6
7
8
9
10
OSCIN
GND
finIF
XfinIF
GNDIF
VCCIF
PSIF
VpIF
DoIF
LD/fout
Lock Det.
2.7 V
2.7 V
1000 pF
1000 pF
1000 pF
0.1 µF
0.1 µF
TCXO
OUTPUT
VCO
LPF
Note •Clock, Data, LE : Schmitt trigger circuit is provided(insert a pull-down or pull-up registor
to prevent oscillation when open-circuite in the input).
•The terminal number shows that of TSSOP-20.
23
MB15F73SP
■ USAGE PRECAUTIONS
(1) VCCRF, VpRF, VCCIF and VpIF must equal equal voltage.
Even if either RF-PLL or IF-PLL is not used, power must be supplied to both VCCRF, VpRF, VCCIF and VpIF to
keep them equal. It is recommended that the non-use PLL is controlled by power saving function.
(2) To protect against damage by electrostatic discharge, note the following handling precautions:
-Store and transport devices in conductive containers.
-Use properly grounded workstations, tools, and equipment.
-Turn off power before inserting or removing this device into or from a socket.
-Protect leads with conductive sheet, when transporting a board mounted device
■ ORDERING INFORMATION
Part number
MB15F73SPPFT
MB15F73SPPV
Package
Remarks
20-pin plastic TSSOP
(FPT-20P-M06)
20-pad plastic BCC
(LCC-20P-M04)
24
MB15F73SP
■ PACKAGE DIMENSIONS
20-pin plastic SSOP
(FPT-20P-M06)
6.42/6.78(.253/.267)
6.50±0.10(.256±.004)
"A"
20
11
4.40±0.10
(.173±.004)
6.40±0.10
(.252±.004)
5.40±0.18
(.213±.007)
4.80(.189)
MAX
INDEX
Details of "A" part
1.05±0.05
(.041±.002)
5° –+53°°
1
10
0.65(.026)
TYP
0.22 –+00..0073
.009 –+..000036
0.50(.020)
0.07±0.03
(.003±.001)
0.415(.016)
0.98±0.02
(.039±.001)
0.10(.004)
Dimensions in mm (inches)
(Continued)
C
1998 FUJITSU LIMITED F20026S-1C-1
25
MB15F73SP
(Continued)
20-pad plastic BCC
(LCC-20P-M04)
3.00(.118)TYP
0.25±0.10
3.60±0.10(.142±.004)
0.80(.031)MAX
(Mounting height)
(.010±.004)
16
11
11
16
0.50(.020)
TYP
0.25±0.10
(.010±.004)
INDEX AREA
3.40±0.10
(.134±.004)
2.70(.106)
TYP
"D"
"A"
"B"
"C"
1
6
6
1
0.50(.020)
TYP
2.80(.110)REF
0.085±0.04
(.003±.002)
(Stand off)
0.05(.002)
Details of "A" part
Details of "B" part
Details of "C" part
Details of "D" part
0.50±0.10
0.50±0.10
0.50±0.10
0.30±0.10
(.020±.004)
(.020±.004)
(.020±.004)
(.012±.004)
C0.20(.008)
0.60±0.10
(.024±.004)
0.30±0.10
(.012±.004)
0.60±0.10
(.024±.004)
0.40±0.10
(.016±.004)
Dimensions in mm (inches)
C
1999 FUJITSU LIMITED C20055S-1C-1
26
MB15F73SP
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: 81(44) 754-3763
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
Fax: 81(44) 754-3329
http://www.fujitsu.co.jp/
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and
Fax: (408) 922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: (800) 866-8608
measurement equipment, personal or household devices, etc.).
CAUTION:
Fax: (408) 922-9179
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded
(such as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
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FUJITSU MICROELECTRONICS EUROPE GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
Any semiconductor devices have an inherent chance of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
http://www.fujitsu-ede.com/
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FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for
export of those products from Japan.
http://www.fmap.com.sg/
F9911
FUJITSU LIMITED Printed in Japan
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