MB2146-301A_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-12608-2E

8-bit Proprietary Microcontrollers

CMOS

F²MC-8FX MB95140 Series

MB95F146S/F146W/FV100D-101

■ DESCRIPTION

The MB95140 series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set,

the microcontrollers contain a variety of peripheral functions.

Note : F²MC is the abbreviation of FUJITSU Flexible Microcontroller.

■ FEATURE

• F²MC-8FX CPU core

Instruction set optimized for controllers

• Multiplication and division instructions

• 16-bit arithmetic operations

• Bit test branch instruction

• Bit manipulation instructions etc.

• Clock

• Main clock

• Main PLL clock

• Sub clock (for dual clock product)

• Sub PLL clock (for dual clock product)

(Continued)

Be sure to refer to the “Check Sheet” for the latest cautions on development.

“Check Sheet” is seen at the following support page

URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html

“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system

development.

MB95140 Series

(Continued)

• Timer

• 8/16-bit compound timer × 2 channels

• 8/16-bit PPG × 2 channels

• 16-bit PPG

• Timebase timer

• Watch prescaler (for dual clock product)

• LIN-UART

• Full duplex double buffer

• Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable

• UART/SIO

• Full duplex double buffer

• Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable

• External interrupt

• Interrupt by edge detection (rising, falling, or both edges can be selected)

• Can be used to recover from low-power consumption (standby) modes.

• 8/10-bit A/D converter

8-bit or 10-bit resolution can be selected.

• Low-power consumption (standby) mode

• Stop mode

• Sleep mode

• Watch mode (for dual clock product)

• Timebase timer mode

• I/O port

• The number of maximum ports

• Single clock product : 24 ports

• Dual clock product : 22 ports

• Port configuration

• General-purpose I/O ports (CMOS) : Single-clock product : 24 ports

: Dual-clock product : 22 ports

• Flash memory security function

Protects the content of Flash memory (Flash memory device only)

2

MB95140 Series

■ PRODUCT LINEUP

Part number^*1

MB95F146S

MB95F146W

Parameter

Flash memory

product

Type

ROM capacity

RAM capacity

Reset output

Clock system

32K bytes

1K byte

No

Single clock

Dual clock

Low voltage

detection reset

No

Number of basic instructions

Instruction bit length

Instruction length

: 136

: 8 bits

: 1 to 3 bytes

: 1, 8, and 16 bits

CPU functions

Data bit length

Minimum instruction execution time : 61.5 ns (at machine clock frequency 16.25 MHz)

Interrupt processing time

: 0.6 µs (at machine clock frequency 16.25 MHz)

General purpose

I/O ports

Single clock product : 24 ports

Dual clock product : 22 ports

Timebase timer

Interrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at 4 MHz main oscillation clock)

Reset generated cycle

Watchdog timer

Wild register

At 10 MHz main oscillation clock : Min 105 ms

At 32.768 kHz sub oscillation clock (for dual clock product) : Min 250 ms

Capable of replacing 3 bytes of ROM data

Data transfer capable in UART/SIO

Full duplex double buffer, variable data length (5/6/7/8 bits), built-in baud rate generator

NRZ type transfer format, error detected function

LSB-first or MSB-first can be selected.

UART/SIO

LIN-UART

Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable

Dedicated reload timer allowing a wide range of communication speeds to be set.

Full duplex double buffer.

Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable

LIN functions available as the LIN master or LIN slave.

8/10-bit A/D

converter

8-bit or 10-bit resolution can be selected.

(8 channels)

(Continued)

3

MB95140 Series

(Continued)

Part number^*1

MB95F146S

MB95F146W

Parameter

Each channel of the timer can be used as “8-bit timer × 2 channels” or “16-bit timer × 1

channel”.

8/16-bitcompound

timer (2 channels)

Built-in timer function, PWC function, PWM function, capture function and square wave

form output

Count clock : 7 internal clocks and external clock can be selected.

PWM mode or one-shot mode can be selected.

Counter operating clock : 8 selectable clock sources

Support for external trigger start

16-bit PPG

Each channel of the PPG can be used as “8-bit PPG × 2 channels” or “16-bit PPG × 1

channel”.

Counter operating clock : 8 selectable clock sources

8/16-bit PPG

(2 channels)

Watch counter

(for dual clock

product)

Count clock : 4 selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s)

Counter value can be set from 0 to 63. (Capable of counting for 1 minute when selecting

clock source 1 second and setting counter value to 60)

Watch prescaler

(for dual clock

product)

4 selectable interval times (125 ms, 250 ms, 500 ms, or 1 s)

External interrupt Interrupt by edge detection (rising, falling, or both edges can be selected.)

(12 channels)

Flash memory

Standby mode

Can be used to recover from standby modes.

Supports automatic programming, Embedded Algorithm^{TM *2}

Write/Erase/Erase-Suspend/Resume commands

A flag indicating completion of the algorithm

Number of write/erase cycles (Minimum) : 10000 times

Data retention time : 20 years

Boot block configuration

Erase can be performed on each block

Block protection with external programming voltage

Flash Security Feature for protecting the content of the Flash

Sleep, stop, watch (for dual clock product), and timebase timer

*1 : MASK ROM products are currently under consideration.

*2 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.

Note : Part number of the evaluation device in MB95140 series is MB95FV100D-101. When using it, the MCU

board (MB2146-301A) is required.

4

MB95140 Series

■ OSCILLATION STABILIZATION WAIT TIME

The initial value of the main clock oscillation stabilization wait time is fixed to the maximum value.

The maximum value is shown as follows.

Oscillation stabilization wait time

Remarks

(2¹⁴− 2) /FCH

Approx. 4.10 ms (at 4 MHz main oscillation clock)

■ PACKAGES AND CORRESPONDING PRODUCTS

Part number

MB95F146S

MB95FV100D-101

MB95F146W

Package

FPT-32P-M21

BGA-224P-M08

: Available

: Unavailable

5

MB95140 Series

■ DIFFERENCES AMONG PRODUCTS AND NOTES ON SELECTING PRODUCTS

• Notes on Using Evaluation Products

The Evaluation product has not only the functions of the MB95140 series but also those of other products to

support software development for multiple series and models of the F²MC-8FX family. The I/O addresses for

peripheral resources not used by the MB95140 series are therefore access-barred. Read/write access to these

access-barred addresses may cause peripheral resources supposed to be unused to operate, resulting in

unexpected malfunctions of hardware or software.

Particularly, do not use word access to odd numbered byte address in the prohibited areas (If these access are

used, the address may be read or written unexpectedly).

Note that the values read from barred addresses are different between the Evaluation product and the Flash

memory product. Therefore, the value must not be used for program.

The Evaluation product does not support the functions of some bits in single-byte registers. Read/write access

to these bits does not cause hardware malfunctions. The Evaluation, and Flash memory products are designed

to behave completely the same way in terms of hardware and software.

• Difference of Memory Spaces

If the amount of memory on the Evaluation product is different from that of the Flash memory product, carefully

check the difference in the amount of memory from the model to be actually used when developing software.

For details of memory space, refer to “■ CPU CORE”.

• Current Consumption

For details of current consumption, refer to “■ ELECTRICAL CHARACTERISTICS”.

• Package

For details of information on each package, refer to “■ PACKAGES AND CORRESPONDING PRODUCTS” and

“■ PACKAGE DIMENSIONS”.

• Operating voltage

The operating voltage is different among the Evaluation and Flash memory products.

For details of operating voltage, refer to “■ ELECTRICAL CHARACTERISTICS”

• Difference between RST and MOD pins

The input type of RST and MOD pins is CMOS input on the Flash memory product.

6

MB95140 Series

■ PIN ASSIGNMENT

(TOP VIEW)

32 31 30 29 28 27 26 25

P06/INT06/AN06/TO01

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

P62/TO10

P63/TO11

P64/EC1

RST

P05/INT05/AN05/TO00

P04/INT04/AN04/SIN

P03/INT03/AN03/SOT

P02/INT02/AN02/SCK

P01/INT01/AN01/PPG01

P00/INT00/AN00/PPG00

AVss

PG1/X0A*

PG2/X1A*

PG0

Vcc

9 10 11 12 13 14 15 16

(FPT-32P-M21)

* : The pins are general-purpose port in single clock product and sub clock oscillation pin in dual clock product.

7

MB95140 Series

■ PIN DESCRIPTION

I/O

circuit

type*

Pin no.

Pin name

Function

P06/INT06/

AN06/TO01

General-purpose I/O port.

1

2

Shared with external interrupt input (INT05, INT06), A/D analog

input (AN05, AN06) and 8/16-bit compound timer ch.0 output (TO00,

TO01).

D

P05/INT05/

AN05/TO00

General-purpose I/O port.

Shared with external interrupt input (INT04), A/D converter analog

input (AN04) and LIN-UART data input (SIN).

P04/INT04/

AN04/SIN

3

4

5

E

D

General-purpose I/O port.

Shared with external interrupt input (INT03), A/D converter analog

input (AN03) and LIN-UART data output (SOT).

P03/INT03/

AN03/SOT

General-purpose I/O port.

Shared with external interrupt input (INT02), A/D converter analog

input (AN02) and LIN-UART clock I/O (SCK).

P02/INT02/

AN02/SCK

P01/INT01/

AN01/PPG01

General-purpose I/O port.

6

7

Shared with external interrupt input (INT00, INT01), A/D converter

analog input (AN00, AN01) and 8/16-bit PPG ch.0 output (PPG00,

PPG01).

D

P00/INT00/

AN00/PPG00

8

AVss

AVcc

PF2

PF1

PF0

MOD

X0

⎯

A/D converter power supply pin (GND)

A/D converter power supply pin

9

10

11

12

13

14

15

16

17

18

General-purpose I/O port.

Large current port.

K

B

A

Operating mode designation pin

Main clock input oscillation pin

Main clock I/O oscillation pin

Power supply pin (GND)

Power supply pin

X1

Vss

⎯

H

Vcc

PG0

General-purpose I/O port

This pin is general-purpose port in single clock product (PG2) .

This pin is sub clock oscillation pin in dual clock product (32 kHz) .

19

PG2/X1A

H/A

B’

This pin is general-purpose port in single clock product (PG1) .

This pin is sub clock oscillation pin in dual clock product (32 kHz) .

20

21

PG1/X0A

RST

Reset pin

(Continued)

8

MB95140 Series

(Continued)

I/O

circuit

type*

Pin no.

Pin name

Function

General-purpose I/O port.

Shared with 8/16-bit compound timer ch.1 clock input.

22

P64/EC1

23

24

P63/TO11

P62/TO10

General-purpose I/O port.

Shared with 8/16-bit compound timer ch.1 output.

K

General-purpose I/O port.

Shared with 8/16-bit PPG ch.1 output.

25

26

27

P61/PPG11

P60/PPG10

P14/PPG0

General-purpose I/O port.

Shared with 8/16-bit PPG ch.1 output.

K

H

General-purpose I/O port.

Shared with 16-bit PPG ch.0 output.

General-purpose I/O port.

Shared with 16-bit PPG ch.0 trigger input (TRG0) and A/D trigger

input (ADTG).

P13/TRG0/

ADTG

28

29

H

General-purpose I/O port.

Shared with UART/SIO ch.0 clock I/O (UCK0) and 8/16-bit compound

timer ch.0 clock input (EC0).

P12/UCK0/EC0

General-purpose I/O port.

Shared with UART/SIO ch.0 data output.

30

31

P11/UO0

P10/UI0

H

G

General-purpose I/O port.

Shared with UART/SIO ch.0 data input.

General-purpose I/O port.

Shared with external interrupt input (INT07) and A/D converter analog

input (AN07).

P07/INT07/

AN07

32

D

* : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”.

9

MB95140 Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

• Oscillation circuit

• High-speed side

Feedback resistance : approx. 1 MΩ

• Low-speed side

X1 (X1A)

X0 (X0A)

Clock

input

N-ch

Feedback resistance : approx. 24 MΩ

(Evaluation product : approx. 10 MΩ)

Dumping resistance : approx. 144 kΩ

(Evaluation product : without dumping

resistance)

A

Standby control

• Only for input

• Hysteresis input

B

Mode input

Reset input

Hysteresis input

B’

• CMOS output

• Hysteresis input

• Analog input

• With pull - up control

R

P-ch

Pull-up control

P-ch

N-ch

Digital output

D

Analog input

Hysteresis

input

A/D control

Standby control

External control

• CMOS output

• CMOS input

• Hysteresis input

• Analog input

R

P-ch

Pull-up control

P-ch

N-ch

Digital output

• With pull - up control

E

Analog input

CMOS input

Hysteresis

input

A/D control

Standby control

External control

(Continued)

10

MB95140 Series

(Continued)

Type

Circuit

Remarks

• CMOS output

• CMOS input

• Hysteresis input

• With pull - up control

R

Pull-up control

Digital output

P-ch

N-ch

G

Digital output

CMOS input

Hysteresis

input

Standby control

• CMOS output

• Hysteresis input

• With pull - up control

R

Pull-up control

P-ch

N-ch

Digital output

H

Hysteresis

input

Standby control

• CMOS output

• Hysteresis input

P-ch

N-ch

Digital output

K

Hysteresis

input

11

MB95140 Series

■ HANDLING DEVICES

• Preventing Latch-up

Care must be taken to ensure that maximum voltage ratings are not exceeded when they are used.

Latch-up may occur on CMOS ICs if voltage higher than V^CCor lower than VSS is applied to input and output pins

other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between VCC

pin and VSS pin.

When latch-up occurs, power supply current increases rapidly and might thermally damage elements.

Also, take care to prevent the analog power supply voltage (AV^CC) and analog input voltage from exceeding the

digital power supply voltage (VCC) when the analog system power supply is turned on or off.

• Stable Supply Voltage

Supply voltage should be stabilized.

A sudden change in power-supply voltage may cause a malfunction even within the guaranteed operating range

of the V^CCpower-supply voltage.

For stabilization, in principle, keep the variation in VCC ripple (p-p value) in a commercial frequency range

(50/60 Hz) not to exceed 10% of the standard VCC value and suppress the voltage variation so that the transient

variation rate does not exceed 0.1 V/ms during a momentary change such as when the power supply is switched.

• Precautions for Use of External Clock

Even when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up

from sub clock mode or stop mode.

■ PIN CONNECTION

• Treatment of Unused Pin

Leaving unused input pins unconnected can cause abnormal operation or latch-up, leaving to permanent dam-

age.

Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused input/

output pins may be set to output mode and left open, or set to input mode and treated the same as unused input

pins. If there is unused output pin, make it to open.

• Treatment of Power Supply Pins on A/D Converter

Connect to be AV^CC= VCC and AVSS = VSS even if the A/D converter is not in use.

Noise riding on the AVCC pin may cause accuracy degradation. So, connect approx. 0.1 µF ceramic capacitor

as a bypass capacitor between AVCC and AVSS pins in the vicinity of this device.

• Power Supply Pins

In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device

to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply

and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals

caused by the rise in the ground level, and to conform to the total output current rating.

Moreover, connect the current supply source with the V^CCand VSS pins of this device at the low impedance.

It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between VCC and VSS pins

near this device.

12

MB95140 Series

• Mode Pin (MOD)

Connect the MOD pin directly to V^CCor VSS pins.

To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to

minimize the distance from the MOD pin to V^CCor VSS pins and to provide a low-impedance connection.

• Analog Power Supply

Always set the same potential to AV^CCand VCC pins. When VCC > AVCC, the current may flow through the AN00

to AN07 pins.

13

MB95140 Series

■ PROGRAMMING FLASH MEMORY MICROCONTROLLERS USING PARALLEL

PROGRAMMER

• Supported Parallel Programmers and Adapters

The following table lists supported parallel programmers and adapters.

Package

Applicable adapter model

Parallel programmers

AF9708 (Ver 02.35G or more)

AF9709/B (Ver 02.35G or more)

FPT-32P-M21

TEF110-95F146

Note : For information on applicable adapter models and parallel programmers, contact the following:

Flash Support Group, Inc. TEL: +81-53-428-8380

• Sector Configuration

The individual sectors of Flash memory correspond to addresses used for CPU access and programming by

the parallel programmer as follows:

Flash memory

32 Kbytes

CPU address

8000^H

Programmer address*

18000H

FFFFH

1FFFFH

*: Programmer addresses are corresponding to CPU addresses, used when the parallel programmer

programs data into Flash memory.

These programmer addresses are used for the parallel programmer to program or erase data in Flash memory.

• Programming Method

1) Set the type code of the parallel programmer to “1723E”.

2) Load program data to programmer addresses 18000^Hto 1FFFFH.

3) Programmed by parallel programmer

14

MB95140 Series

■ BLOCK DIAGRAM

F²MC-8FX CPU

RST

Reset control

Clock control

ROM

X0, X1

PG2/(X1A)*

PG1/(X0A)*

PG0

RAM

Interrupt control

Wild register

Watch prescaler

Watch counter

External interrupt

P00/INT00 to P07/INT07

P60/PPG10

P61/PPG11

8/16-bit PPG ch.1

P10/UI0

P11/UO0

P12/UCK0

UART/SIO

P62/TO10

P63/TO11

P64/EC1

8/16-bit compound

timer ch.1

P13/TRG0/ADTG

P14/PPG0

16-bit PPG

PF0 to PF2

PG0

(P00/PPG00)

(P01/PPG01)

8/16-bit PPG ch.0

(P02/SCK)

(P03/SOT)

(P04/SIN)

LIN-UART

(P05/TO00)

(P06/TO01)

(P12/EC0)

8/16-bit compound

timer ch.0

(P00/AN00 to P07/AN07)

8/10-bit

A/D converter

AV^CC

AVSS

Port

Other pins

MOD, V^CC, VSS

* : The pins are general-purpose port in single clock product and sub clock oscillation pin in dual clock product.

15

MB95140 Series

■ CPU CORE

1. Memory space

Memory space of the MB95140 series is 64K bytes and consists of I/O area, data area, and program area. The

memoryspaceincludesspecial-purposeareassuchasthegeneral-purpose7registersandvectortable. Memory

map of the MB95140 series is shown below.

• Memory Map

MB95F146S

MB95F146W

MB95FV100D-101

I/O

0000H

I/O

0080H

0100H

0200H

RAM 1 Kbyte

Register

RAM 3.75 Kbytes

Register

0100H

0200H

0480H

Access

prohibited

0F80H

Extended I/O

1000H

Access

prohibited

8000^H

Flash memory

60 Kbytes

Flash memory

32 Kbytes

FFFFH

16

MB95140 Series

2. Register

The MB95140 series has two types of registers; dedicated registers in the CPU and general-purpose registers

in the memory. The dedicated registers are as follows:

Program counter (PC)

: A 16-bit register to indicate locations where instructions are stored.

Accumulator (A)

: A 16-bit register for temporary storage of arithmetic operations. In the case of

an 8-bit data processing instruction, the lower 1 byte is used.

Temporary accumulator (T) : A 16-bit register which performs arithmetic operations with the accumulator.

In the case of an 8-bit data processing instruction, the lower 1 byte is used.

Index register (IX)

Extra pointer (EP)

Stack pointer (SP)

Program status (PS)

: A 16-bit register for index modification

: A 16-bit pointer to point to a memory address.

: A 16-bit register to indicate a stack area.

: A 16-bit register for storing a register bank pointer, a direct bank pointer, and

a condition code register

Initial Value

16-bit

FFFD^H

0000H

0030H

: Program counter

: Accumulator

PC

A

T

: Temporary accumulator

: Index register

IX

EP

SP

PS

: Extra pointer

: Stack pointer

: Program status

The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and a direct bank pointer

(DP) and the lower 8 bits for use as a condition code register (CCR) . (Refer to the diagram below.)

• Structure of the Program Status

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1

bit0

C

R4

R3

R2

R1

R0 DP2 DP1 DP0

H

I

IL1

IL0

N

Z

PS

V

RP

DP

CCR

17

MB95140 Series

The RP indicates the address of the register bank currently being used. The relationship between the content

of RP and the real address conforms to the conversion rule illustrated below:

• Rule for Conversion of Actual Addresses in the General-purpose Register Area

RP upper

OP code lower

"0" "0" "0" "0" "0" "0" "0" "1"

R4 R3 R2 R1 R0 b2

b1

b0

Generated address

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

The DP specifies the area for mapping instructions (16 different instructions such as MOV A, dir) using direct

addresses to 0080^Hto 00FFH.

Direct bank pointer (DP2 to DP0)

Specified address area

Mapping area

0000H to 007FH (without mapping)

0080H to 00FFH (without mapping)

0100H to 017FH

XXX^B(no effect to mapping)

0000H to 007FH

000^B(initial value)

001^B

010B

011B

100B

101B

110B

111B

0180H to 01FFH

0200H to 027FH

0080^Hto 00FFH

0280H to 02FFH

0300H to 037FH

0380H to 03FFH

0400H to 047FH

The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that

control CPU operations at interrupt.

H flag

I flag

Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.

Cleared to “0” otherwise. This flag is for decimal adjustment instructions.

Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when this flag is set to “0”.

The flag is cleared to “0” when reset.

Indicates the level of the interrupt currently enabled. Processes an interrupt only if its request level

is higher than the value indicated by these bits.

:

IL1, IL0

IL1

0

IL0

0

Interrupt level

Priority

0

1

2

High

0

1

0

1

3

Low = no interruption

N flag

Set to “1” if the MSB is set to “1” as the result of an arithmetic operation. Cleared to “0” when the

bit is set to “0”.

:

Z flag

V flag

Set to “1” when an arithmetic operation results in “0”. Cleared to “0” otherwise.

Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0”

otherwise.

C flag

Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared

to “0” otherwise. Set to the shift-out value in the case of a shift instruction.

:

18

MB95140 Series

The following general-purpose registers are provided:

General-purpose registers: 8-bit data storage registers

The general-purpose registers are 8 bits and located in the register banks on the memory. 1-bank contains 8-

register. Up to a total of 32 banks can be used on the MB95140 series. The bank currently in use is specified

by the register bank pointer (RP), and the lower 3 bits of OP code indicates the general-purpose register 0 (R0)

to general-purpose register 7 (R7).

• Register Bank Configuration

8-bit

1F8_H

This address = 0100^H+ 8 × (RP)

R0

Address 100_H

R0

R1

R2

R3

R4

R5

R6

R7

R0

R1

R2

R3

R4

R5

R6

R7

R2

R3

R4

R5

R6

R7

1FF_H

Bank 31

107_H

32 banks

32 banks (RAM area)

The number of banks is

limited by the usable RAM

capacitance.

Bank 0

Memory area

19

MB95140 Series

■ I/O MAP

Register

Address

Register name

R/W

Initial value

abbreviation

0000^H

0001H

0002H

0003H

0004H

0005^H

0006H

0007H

0008H

0009H

000AH

000BH

000CH

PDR0

DDR0

PDR1

DDR1

⎯

Port 0 data register

Port 0 direction register

R/W

⎯

00000000B

⎯

Port 1 data register

Port 1 direction register

(Disabled)

WATR

PLLC

SYCC

STBC

RSRR

TBTC

WPCR

WDTC

Oscillation stabilization wait time setting register

PLL control register

R/W

R

11111111B

00000000B

1010X011B

00000000B

XXXXXXXXB

00000000B

System clock control register

Standby control register

Reset source register

Timebase timer control register

Watch prescaler control register

Watchdog timer control register

R/W

000DH

to

0015H

⎯

(Disabled)

⎯

0016^H

0017H

PDR6

DDR6

Port 6 data register

R/W

00000000B

Port 6 direction register

0018H

to

0027H

⎯

(Disabled)

⎯

0028^H

0029H

002AH

002BH

002CH

002DH

PDRF

DDRF

PDRG

DDRG

PUL0

PUL1

Port F data register

Port F direction register

Port G data register

R/W

00000000B

Port G direction register

Port 0 pull-up register

Port 1 pull-up register

002EH

to

0034H

⎯

(Disabled)

⎯

0035^H

0036H

0037H

0038H

0039H

003AH

PULG

T01CR1

T00CR1

T11CR1

T10CR1

PC01

Port G pull-up register

R/W

00000000B

8/16-bit compound timer 01 control status register 1 ch.0

8/16-bit compound timer 00 control status register 1 ch.0

8/16-bit compound timer 11 control status register 1 ch.1

8/16-bit compound timer 10 control status register 1 ch.1

8/16-bit PPG1 control register ch.0

(Continued)

20

MB95140 Series

Register

abbreviation

Address

Register name

R/W Initial value

003B^H

003CH

003DH

PC00

PC11

PC10

8/16-bit PPG0 control register ch.0

8/16-bit PPG1 control register ch.1

8/16-bit PPG0 control register ch.1

R/W

00000000B

003EH

to

0041H

⎯

(Disabled)

⎯

0042H

0043H

PCNTH0

PCNTL0

16-bit PPG control status register (Upper byte) ch.0

16-bit PPG control status register (Lower byte) ch.0

R/W

00000000B

0044H

to

0047H

⎯

(Disabled)

⎯

0048^H

0049H

004AH

004BH

EIC00

EIC10

EIC20

EIC30

External interrupt circuit control register ch.0/ch.1

External interrupt circuit control register ch.2/ch.3

External interrupt circuit control register ch.4/ch.5

External interrupt circuit control register ch.6/ch.7

R/W

00000000B

004CH

to

004FH

⎯

(Disabled)

⎯

0050^H

0051H

0052H

0053H

0054H

0055H

0056H

0057H

0058H

0059H

005AH

SCR

SMR

LIN-UART serial control register

LIN-UART serial mode register

R/W

R

00000000B

00001000B

00000000B

00000100B

000000XXB

00000000B

00100000B

00000001B

00000000B

SSR

LIN-UART serial status register

RDR/TDR

ESCR

ECCR

SMC10

SMC20

SSR0

LIN-UART reception/transmission data register

LIN-UART extended status control register

LIN-UART extended communication control register

UART/SIO serial mode control register 1 ch.0

UART/SIO serial mode control register 2 ch.0

UART/SIO serial status register ch.0

TDR0

UART/SIO serial output data register ch.0

UART/SIO serial input data register ch.0

RDR0

005BH

to

006BH

⎯

(Disabled)

⎯

006C^H

006DH

006EH

006FH

ADC1

ADC2

ADDH

ADDL

8/10-bit A/D converter control register 1

8/10-bit A/D converter control register 2

R/W

00000000B

8/10-bit A/D converter data register (Upper byte)

8/10-bit A/D converter data register (Lower byte)

00000000B

(Continued)

21

MB95140 Series

Register

Address

Register name

R/W Initial value

abbreviation

0070^H

0071H

0072^H

0073H

0074H

0075H

0076H

0077H

WCSR

⎯

Watch counter status register

(Disabled)

R/W

⎯

00000000B

⎯

FSR

Flash memory status register

R/W

⎯

000X0000B

00000000B

⎯

SWRE0

SWRE1

⎯

Flash memory sector writing control register 0

Flash memory sector writing control register 1

(Disabled)

WREN

WROR

Wild register address compare enable register

Wild register data test setting register

R/W

00000000B

(Mirror of register bank pointer (RP)

and direct bank pointer (DP) )

0078H

⎯

0079^H

007AH

007BH

007CH

007DH

007EH

007FH

0F80H

0F81H

0F82H

0F83H

0F84H

0F85H

0F86H

0F87H

0F88H

ILR0

ILR1

Interrupt level setting register 0

Interrupt level setting register 1

R/W

⎯

11111111B

⎯

ILR2

Interrupt level setting register 2

ILR3

Interrupt level setting register 3

ILR4

Interrupt level setting register 4

ILR5

Interrupt level setting register 5

⎯

(Disabled)

WRARH0

WRARL0

WRDR0

WRARH1

WRARL1

WRDR1

WRARH2

WRARL2

WRDR2

Wild register address setting register (Upper byte) ch.0

Wild register address setting register (Lower byte) ch.0

Wild register data setting register ch.0

Wild register address setting register (Upper byte) ch.1

Wild register address setting register (Lower byte) ch.1

Wild register data setting register ch.1

Wild register address setting register (Upper byte) ch.2

Wild register address setting register (Lower byte) ch.2

Wild register data setting register ch.2

R/W

00000000B

0F89H

to

0F91H

⎯

(Disabled)

⎯

0F92^H

0F93H

0F94H

0F95H

T01CR0

T00CR0

T01DR

T00DR

8/16-bit compound timer 01 control status register 0 ch.0

8/16-bit compound timer 00 control status register 0 ch.0

8/16-bit compound timer 01 data register ch.0

R/W

00000000B

8/16-bit compound timer 00 data register ch.0

8/16-bit compound timer 00/01 timer mode control register

ch.0

0F96H

0F97H

TMCR0

T11CR0

R/W

00000000B

8/16-bit compound timer 11 control status register 0 ch.1

00000000B

(Continued)

22

MB95140 Series

Register

abbreviation

Address

Register name

R/W Initial value

0F98^H

0F99H

0F9AH

T10CR0

T11DR

T10DR

8/16-bit compound timer 10 control status register 0 ch.1

8/16-bit compound timer 11 data register ch.1

8/16-bit compound timer 10 data register ch.1

R/W

00000000B

8/16-bit compound timer 10/11 timer mode control register

ch.1

0F9BH

TMCR1

R/W

00000000B

0F9CH

0F9DH

0F9EH

0F9FH

0FA0H

0FA1H

0FA2H

0FA3H

0FA4H

0FA5H

PPS01

PPS00

PDS01

PDS00

PPS11

PPS10

PDS11

PDS10

PPGS

8/16-bit PPG1 cycle setting buffer register ch.0

8/16-bit PPG0 cycle setting buffer register ch.0

8/16-bit PPG1 duty setting buffer register ch.0

8/16-bit PPG0 duty setting buffer register ch.0

8/16-bit PPG1 cycle setting buffer register ch.1

8/16-bit PPG0 cycle setting buffer register ch.1

8/16-bit PPG1 duty setting buffer register ch.1

8/16-bit PPG0 duty setting buffer register ch.1

8/16-bit PPG start register

R/W

11111111B

00000000B

REVC

8/16-bit PPG output inversion register

0FA6H

to

0FA9H

⎯

(Disabled)

⎯

0FAAH

0FABH

0FACH

0FADH

0FAEH

0FAFH

PDCRH0

PDCRL0

PCSRH0

PCSRL0

PDUTH0

PDUTL0

16-bit PPG down counter register (Upper byte) ch.0

16-bit PPG down counter register (Lower byte) ch.0

16-bit PPG cycle setting buffer register (Upper byte) ch.0

16-bit PPG cycle setting buffer register (Lower byte) ch.0

16-bit PPG duty setting buffer register (Upper byte) ch.0

16-bit PPG duty setting buffer register (Lower byte) ch.0

R

00000000B

11111111B

R

R/W

0FB0H

to

0FBBH

⎯

(Disabled)

⎯

0FBCH

0FBDH

BGR1

BGR0

LIN-UART baud rate generator register 1

LIN-UART baud rate generator register 0

R/W

00000000B

UART/SIO dedicated baud rate generator

prescaler selection register ch.0

0FBEH

0FBFH

PSSR0

BRSR0

R/W

00000000B

UART/SIO dedicated baud rate generator

baud rate setting register ch.0

0FC0H

to

0FC2H

⎯

AIDRL

⎯

(Disabled)

A/D input disable register (Lower byte)

(Disabled)

⎯

R/W

⎯

0FC3H

00000000B

⎯

0FC4H

to

0FE2H

(Continued)

23

MB95140 Series

(Continued)

Register

Address

Register name

R/W Initial value

abbreviation

0FE3^H

WCDR

Watch counter data register

R/W

00111111B

0FE4H

to

0FEDH

⎯

(Disabled)

⎯

0FEE^H

0FEFH

ILSR

Input level select register

R/W

00000000B

01000000B

WICR

Interrupt pin control register

0FF0H

to

0FFFH

⎯

(Disabled)

⎯

• R/W access symbols

R/W : Readable/Writable

R

W

: Read only

: Write only

• Initial value symbols

0

1

X

: The initial value of this bit is “0”.

: The initial value of this bit is “1”.

: The initial value of this bit is undefined.

Note : Do not write to the “ (Disabled) ”. Reading the “ (Disabled) ” returns an undefined value.

24

MB95140 Series

■ INTERRUPT SOURCE TABLE

Vector table address

Same level

Bit name of

Interrupt

request

number

priority order

Interrupt source

interrupt level

(atsimultaneous

setting register

occurrence)

Upper

FFFA^H

FFF8^H

FFF6^H

FFF4^H

Lower

FFFBH

FFF9H

FFF7H

FFF5H

External interrupt ch.0

External interrupt ch.4

External interrupt ch.1

External interrupt ch.5

External interrupt ch.2

External interrupt ch.6

External interrupt ch.3

External interrupt ch.7

UART/SIO ch.0

High

IRQ0

IRQ1

IRQ2

IRQ3

L00 [1 : 0]

L01 [1 : 0]

L02 [1 : 0]

L03 [1 : 0]

IRQ4

IRQ5

FFF2^H

FFF0H

FFEEH

FFEC^H

FFEAH

FFE8H

FFE6^H

FFE4H

FFE2^H

FFE0H

FFDEH

FFDC^H

FFDAH

FFD8H

FFD6^H

FFD4^H

FFD2H

FFD0H

FFCE^H

FFCC^H

FFF3H

FFF1H

FFEFH

FFEDH

FFEBH

FFE9H

FFE7H

FFE5H

FFE3H

FFE1H

FFDFH

FFDDH

FFDBH

FFD9H

FFD7H

FFD5H

FFD3H

FFD1H

FFCFH

FFCDH

L04 [1 : 0]

L05 [1 : 0]

L06 [1 : 0]

L07 [1 : 0]

L08 [1 : 0]

L09 [1 : 0]

L10 [1 : 0]

L11 [1 : 0]

L12 [1 : 0]

L13 [1 : 0]

L14 [1 : 0]

L15 [1 : 0]

L16 [1 : 0]

L17 [1 : 0]

L18 [1 : 0]

L19 [1 : 0]

L20 [1 : 0]

L21 [1 : 0]

L22 [1 : 0]

8/16-bit compound timer ch.0 (Lower)

8/16-bit compound timer ch.0 (Upper)

LIN-UART (reception)

LIN-UART (transmission)

8/16-bit PPG ch.1 (Lower)

8/16-bit PPG ch.1 (Upper)

(Unused)

IRQ6

IRQ7

IRQ8

IRQ9

IRQ10

IRQ11

IRQ12

IRQ13

IRQ14

IRQ15

IRQ16

IRQ17

IRQ18

IRQ19

IRQ20

IRQ21

IRQ22

IRQ23

8/16-bit PPG ch.0 (Upper)

8/16-bit PPG ch.0 (Lower)

8/16-bit compound timer ch.1 (Upper)

16-bit PPG ch.0

(Unused)

8/10-bit A/D converter

Timebase timer

Watch timer/Watch counter

(Unused)

8/16-bit compound timer ch.1 (Lower)

Flash memory

L23 [1 : 0]

Low

25

MB95140 Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

Rating

Parameter

Symbol

Unit

Remarks

Min

Max

VCC

AVCC

Power supply voltage*¹

VSS − 0.3

VSS + 4.0

V

*2

Input voltage*¹

Output voltage*¹

VI

VO

VSS − 0.3

− 2.0

VSS + 4.0

+ 2.0

V

*3

Maximum clamp current

ICLAMP

mA Applicable to pins*⁴

Total maximum clamp

current

Σ|ICLAMP|

⎯

20

mA Applicable to pins*⁴

I^OL1

I^OL2

15

Other than PF0 to PF2

“L” level maximum

output current

mA

PF0 to PF2

Other than PF0 to PF2

Average output current =

IOLAV1

4

operating current × operating ratio

(1 pin)

mA

“L” level average

current

⎯

PF0 to PF2

Average output current =

operating current × operating ratio

(1 pin)

I^OLAV2

12

“L” level total maximum

output current

ΣIOL

⎯

100

50

mA

Total average output current =

mA operating current × operating ratio

(Total of pins)

“L” level total average

output current

ΣI^OLAV

I^OH1

I^OH2

− 15

Other than PF0 to PF2

“H” level maximum

output current

⎯

mA

PF0 to PF2

Other than PF0 to PF2

Average output current =

I^OHAV1

− 4

− 8

operating current × operating ratio

(1 pin)

mA

“H” level average

current

⎯

PF0 to PF2

Average output current =

operating current × operating ratio

(1 pin)

I^OHAV2

“H” level total maximum

output current

ΣIOH

⎯

− 100

− 50

mA

Total average output current =

mA operating current × operating ratio

(Total of pins)

“H” level total average

output current

ΣI^OHAV

(Continued)

26

MB95140 Series

(Continued)

Parameter

Rating

Symbol

Unit

Remarks

Min

⎯

Max

320

Power consumption

Operating temperature

Storage temperature

Pd

T^A

mW

°C

− 40

− 55

+ 85

+ 150

Tstg

°C

*1 : The parameter is based on AV^SS= VSS = 0.0 V.

*2 : Apply equal potential to AVCC and VCC.

*3 : V^Iand Vo should not exceed VCC + 0.3 V. VI must not exceed the rating voltage. However, if the maximum

current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the

VI rating.

*4 : Applicable to pins : P00 to P07, P10 to P14, P60 to P64, PF0 to PF2, PG0

• Use within recommended operating conditions.

• Use at DC voltage (current).

• The+ BsignalisaninputsignalthatexceedsV^CCvoltage. The+ Bsignalshouldalwaysbeappliedalimiting

resistance placed between the + B signal and the microcontroller.

• The value of the limiting resistance should be set so that when the + B signal is applied the input current

to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.

• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input

potential may pass through the protective diode and increase the potential at the VCC pin, and this affects

other devices.

• Note that if the + B signal is inputted when the microcontroller power supply is off (not fixed at 0 V), the power

supply is provided from the pins, so that incomplete operation may result.

• Note that if the + B input is applied during power-on, the power supply is provided from the pins and the

resulting power supply voltage may not be sufficient to operate the power-on reset.

• Care must be taken not to leave the + B input pin open.

• Sample recommended circuits :

• Input/Output Equivalent Circuits

Protective diode

Vcc

Limiting

P-ch

resistance

+ B input (0 V to 16 V)

N-ch

R

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

27

MB95140 Series

2. Recommended Operating Conditions

(AVSS = VSS = 0.0 V)

Value

Sym-

bol

Condi-

tion

Parameter

Pin name

Unit

Remarks

Min

Max

At normal operating,

TA = −10 °C to +85 °C

⎯

2.3*

3.3

At normal operating,

TA = −40 °C to +85 °C

⎯

2.4*

3.3

3.6

Power supply

V^CC,

V

voltage

AVCC

MB95FV100D-101

T^A= +5 to +35

2.6

1.5

⎯

3.3

Retain status in stop mode

Operating temperature

T^A

− 40

+ 85

°C

* : The values vary with the operating frequency.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

28

MB95140 Series

3. DC Characteristics

(VCC = AVCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)

Value

Sym-

Parameter

bol

Pin name

Conditions

Unit

Remarks

Min

Typ

Max

At selecting CMOS

input level

V^IHP04, P10

*1

0.7 VCC

⎯

VCC + 0.3

V

P00 to P07,

P10 to P14,

VIHS P60 to P64,

“H” level input

voltage

*1

0.8 VCC

⎯

VCC + 0.3

V

Hysteresis input

PF0 to PF2, PG0,

PG1*², PG2*²

V^IHMRST, MOD

⎯

0.8 VCC

⎯

VCC + 0.3

V

At selecting CMOS

input level

(Hysteresis input)

V^ILP04, P10

*1

VSS − 0.3

0.3 VCC

P00 to P07,

P10 to P14,

V^ILSP60 to P64,

PF0 to PF2, PG0,

PG1*², PG2*²

“L” level input

voltage

*1

VSS − 0.3

⎯

0.2 VCC

V

Hysteresis input

V^ILM

RST, MOD

⎯

VSS − 0.3

2.4

⎯

0.2 VCC

⎯

V

Output pin other

than PF0 to PF2

V^OH1

IOH = − 4.0 mA

IOH = − 8.0 mA

IOL = 4.0 mA

IOL = 12 mA

“H” level output

voltage

V^OH2PF0 to PF2

2.4

⎯

Output pin other

than PF0 to PF2

V^OL2PF0 to PF2

V^OL1

⎯

0.4

“L” level output

voltage

⎯

0.4

Input leakage

current (Hi-Z

output leakage

current)

When the pull-up is

prohibition setting

ILI

All input pins

P00 to P07,

0.0 V < VI < VCC

− 5

⎯

+ 5

µA

kΩ

When the pull-up is

permission setting

Pull-up resistor R^PULLP10 to P14, PG0, VI = 0.0 V

25

50

100

PG1*², PG2*²

At other than Flash

mA memory writing

and erasing

F^CH= 20 MHz

⎯

11.0

30.0

17.6

38.1

14.0

35.0

22.4

44.9

FMP = 10 MHz

Main clock

mode

At Flash memory

mA

VCC

(divided by 2)

writing and erasing

Power supply

current*³

ICC (External clock

operation)

At other than Flash

mA memory writing

and erasing

F^CH= 32 MHz

F^MP= 16 MHz

Main clock

mode

At Flash memory

mA

(divided by 2)

writing and erasing

(Continued)

29

MB95140 Series

(V^CC= AVCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)

Value

Sym-

bol

Parameter

Pin name

Conditions

Unit

Remarks

Min

Typ

Max

F^CH= 20 MHz

FMP = 10 MHz

Main Sleep mode

(divided by 2)

⎯

4.5

6.0

mA

ICCS

FCH = 32 MHz

FMP = 16 MHz

Main Sleep mode

(divided by 2)

⎯

7.2

25

9.6

35

mA

FCL = 32 kHz

FMPL = 16 kHz

Sub clock mode

(divided by 2) ,

TA = + 25 °C

I^CCL

µA

FCL = 32 kHz

FMPL = 16 kHz

Sub sleep mode

(divided by 2) ,

TA = + 25 °C

I^CCLS

⎯

7

15

µA

FCL = 32 kHz

Watch mode

Main stop mode

TA = + 25 °C

VCC

I^CCT

⎯

2

10

14

µA

Power supply

current*³

(External clock

operation)

FCH = 4 MHz

FMP = 10 MHz

Main PLL mode

(multiplied by 2.5)

10

mA

I^CCMPLL

F^CH= 6.4 MHz

FMP = 16 MHz

Main PLL mode

(multiplied by 2.5)

16.0

22.4 mA

FCL = 32 kHz

FMPL = 128 kHz

Sub PLL mode

(multiplied by 4) ,

TA = + 25 °C

I^CCSPLL

⎯

190

250

µA

FCH = 10 MHz

Timebase timer

mode

I^CTS

⎯

0.64

1

0.80 mA

T^A= + 25 °C

Sub stop mode

T^A= + 25 °C

ICCH

5

µA

(Continued)

30

MB95140 Series

(Continued)

(V^CC= AVCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)

Value

Sym-

bol

Parameter

Pin name

Conditions

Unit

Remarks

Min

Typ

Max

FCH = 10 MHz

At operating of A/D

conversion

IA

⎯

1.3

2.2

mA

Power supply

current*³

AVCC

FCH = 10 MHz

At stopping of A/D

conversion

I^AH

⎯

1

5

µA

TA = + 25 °C

Input

capacitance

Other than AVCC,

AVSS, VCC, VSS

CIN

f = 1 MHz

15

pF

*1 : P04, P10 can switch the input level to either the “CMOS input level” or “hysteresis input level”.

The switching of the input level can be set by the input level selection register (ILSR).

*2 : Single clock product only

*3 : Power supply current is regulated by external clock.

• Refer to “4. AC Characteristics (1) Clock Timing” for F^CHand FCL.

• Refer to “4. AC Characteristics (2) Source Clock/Machine Clock” for F^MPand FMPL.

31

MB95140 Series

4. AC Characteristics

(1) Clock Timing

(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)

Value

Sym-

bol

Parameter

Pin name Conditions

Unit

Remarks

Min

Typ

Max

When using main

oscillation circuit

1.00

⎯

16.25 MHz

1.00

3.00

⎯

32.50 MHz When using external clock

10.00 MHz Main PLL multiplied by 1

8.13 MHz Main PLL multiplied by 2

6.50 MHz Main PLL multiplied by 2.5

4.06 MHz Main PLL multiplied by 4

When using sub oscillation

F^CH

X0, X1

Clock frequency

⎯

32.768

⎯

kHz

circuit

F^CLX0A, X1A

When using sub PLL

32.768

⎯

kHz Flash memory product :

V^CC= 2.3 V to 3.3 V

⎯

When using main

ns

100

50

⎯

1000

oscillation circuit

t^HCYL

X0, X1

ns When using external clock

Clock cycle time

When using sub oscillation

µs circuit, When using

external clock

t^LCYLX0A, X1A

⎯

30.5

⎯

t^WH1

tWL1

X0

10

⎯

15.2

⎯

10

ns

When using external clock

Duty ratio is about 30% to

70%.

Input clock pulse

width

tWH2

X0A

tWL2

µs

Input clock rise time

and fall time

tCR

X0, X0A

tCF

ns When using external clock

32

MB95140 Series

• Input wave form for using external clock (main clock)

tHCYL

tWH1

tWL1

tCR

tCF

0.8 VCC 0.8 VCC

X0

0.2 VCC

• Figure of main clock input port external connection

When using a crystal or

ceramic oscillator

When using external clock

Microcontroller

X0

X1

X0

X1

Open

F^CH

C2

F^CH

C1

• Input wave form for using external clock (sub clock)

tLCYL

tWH2

tWL2

tCR

tCF

0.8 VCC 0.8 VCC

X0A

0.1 VCC

• Figure of sub clock input port external connection

When using a crystal or

ceramic oscillator

When using external clock

Microcontroller

X0A

X1A

X0A

X1A

Open

F^CL

C2

F^CL

C1

33

MB95140 Series

(2) Source Clock/Machine Clock

(V^CC= 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)

Value

Typ

Sym-

Parameter

Unit

Remarks

bol name

Min

Max

When using main clock

Min : F^CH= 8.125 MHz,

PLL multiplied by 2

61.5

⎯

2000

ns

Source clock cycle time*¹

(Clock before setting

division)

Max : FCH = 1 MHz, divided by 2

tSCLK

⎯

When using sub clock

Min : F^CL= 32 kHz,

7.6

61.0

µs

PLL multiplied by 4

Max : FCL = 32 kHz, divided by 2

FSP

⎯

0.5

⎯

16.25 MHz When using main clock

131.072 kHz When using sub clock

When using main clock

Source clock frequency

FSPL

16.384

100

7.6

⎯

32000

ns Min : F^SP= 16.25 MHz, no division

Machine clock cycle time*²

(Minimum instruction

execution time)

Max : FSP = 0.5 MHz, divided by 16

tMCLK

⎯

When using sub clock

976.5

µs Min : F^SPL= 131 kHz, no division

Max : FSPL = 16 kHz, divided by 16

F^MP

0.031

1.024

⎯

16.250 MHz When using main clock

131.072 kHz When using sub clock

Machine clock frequency

⎯

F^MPL

*1 : Clock before setting division due to machine clock division ratio selection bits (SYCC : DIV1 and DIV0) .

This source clock is divided by the machine clock division ratio selection bits (SYCC : DIV1 and DIV0) , and it

becomes the machine clock. Further, the source clock can be selected as follows.

• Main clock divided by 2

• PLL multiplication of main clock (select from 1, 2, 2.5, 4 multiplication)

• Sub clock divided by 2

• PLL multiplication of sub clock (select from 2, 3, 4 multiplication)

*2 : Operation clock of the microcontroller. Machine clock can be selected as follows.

• Source clock (no division)

• Source clock divided by 4

• Source clock divided by 8

• Source clock divided by 16

34

MB95140 Series

• Outline of Clock Generation Block

F

CH

Divided by 2

(main oscillation)

Main PLL

× 1

× 2

× 2.5

× 4

Division

circuit

SCLK

(source clock)

× 1

MCLK

(machine clock)

× 1/4

× 1/8

× 1/16

F

CL

Divided by 2

(sub oscillation)

Clock mode select bit

(SYCC: SCS1, SCS0)

Sub PLL

× 2

× 3

× 4

35

MB95140 Series

• Operating Voltage - Operating Frequency (When T^A= − 10 °C to + 85 °C)

• MB95F146S, MB95F146W

Sub PLL operation guarantee range

Sub clock mode and watch mode

operation guarantee range

Main clock mode and main PLL mode

operation guarantee range

3.3

2.3

3.3

2.7

2.3

16.384 kHz

32 kHz

131.072 kHz

0.5 MHz 3 MHz 5 MHz

16.25 MHz

PLL operation guarantee range

Main clock operation guarantee range

Source clock frequency (FSP)

Source clock frequency (F^SPL)

• Operating Voltage - Operating Frequency (When T^A= − 40 °C to + 85 °C)

• MB95F146S, MB95F146W

Sub PLL operation guarantee range

Sub clock mode and watch mode

operation guarantee range

Main clock mode and main PLL mode

operation guarantee range

3.3

2.4

3.3

2.7

2.4

16.384 kHz

32 kHz

131.072 kHz

0.5 MHz 3 MHz 5 MHz

16.25 MHz

PLL operation guarantee range

Main clock operation guarantee range

Source clock frequency (FSP)

Source clock frequency (F^SPL)

36

MB95140 Series

• Operating voltage − Operating frequency (TA = + 5 °C to + 35 °C)

• MB95FV100D-101

Sub PLL, sub clock mode and watch

mode operation guarantee range

Main clock mode and main PLL mode

operation guarantee range

3.6

3.3

2.6

16.384 kHz

32 kHz

131.072 kHz

0.5 MHz 3 MHz

10 MHz

16.25 MHz

PLL operation guarantee range

Main clock operation guarantee range

Source clock frequency (FSPL)

Source clock frequency (FSP)

37

MB95140 Series

• Main PLL Operation Frequency

[MHz]

16.25

16

15

× 4

12

10

× 2.5

× 1

× 2

7.5

6

5

3

[MHz]

10

0

3

4

5

6.4

8

6.5

4.062

8.125

Machine clock frequency (F^MP)

38

MB95140 Series

(3) External Reset

Parameter

(V^CC= 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)

Value

Symbol

Unit

Remarks

Min

Max

2 tMCLK*¹

⎯

ns At normal operating

RST “L” level pulse

width

Oscillation time of oscillator*²

At stop mode, sub clock mode,

ns

tRSTL

⎯

+ 2 tMCLK*¹

sub sleep mode, and watch mode

*1 : Refer to “ (2) Source Clock/Machine Clock” for t^MCLK.

*2 : Oscillation start time of oscillator is the time that the amplitude reaches 90 %. In the crystal oscillator, the

oscillation time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between

hundreds of µs and several ms. In the external clock, the oscillation time is 0 ms.

• At Normal Operating

tRSTL

RST

0.2 VCC

• At Stop Mode, Sub clock Mode, Sub Sleep Mode, Watch Mode, and Power-on

tRSTL

RST

0.2 VCC

90% of

amplitude

X0

Internal

operating

clock

2 tMCLK

Oscillation time

of oscillator

Oscillation stabilization wait time

Execute instruction

Internal reset

39

MB95140 Series

(4) Power-on Reset

(AV^SS= VSS = 0.0 V, TA = − 40 °C to + 85 °C)

Value

Parameter

Symbol

Conditions

Unit

Remarks

Min

Max

Power supply rising time

Power supply cutoff time

t^R

⎯

36

ms

Waiting time until

power-on

t^OFF

1

⎯

tR

tOFF

1.5 V

0.2 V

VCC

Note : Sudden change of power supply voltage may activate the power-on reset function. When changing power

supply voltages during operation, set the slope of rising within 20 mV/ms as shown below.

VCC

Limiting the slope of rising within

20 mV/ms is recommended.

1.5 V

Hold condition in stop mode

VSS

40

MB95140 Series

(5) Peripheral Input Timing

Parameter

(V^CC= 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)

Value

Symbol

Pin name

Unit

Min

Max

⎯

tILIH

tIHIL

Peripheral input “H” pulse width

Peripheral input “L” pulse width

2 t^MCLK*

2 tMCLK*

ns

INT00 to INT07,

EC0, EC1, TRG0/ADTG

⎯

* : Refer to “ (2) Source Clock/Machine Clock” for t^MCLK.

tILIH

tIHIL

INT00 to INT07,

EC0, EC1,

0.8 VCC 0.8 VCC

TRG0/ADTG

0.2 VCC

41

MB95140 Series

(6) UART/SIO, Serial I/O Timing

(V^CC= 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)

Value

Parameter

Symbol

Pin name

Conditions

Unit

Min

Max

⎯

Serial clock cycle time

UCK ↓ → UO time

t^SCYC

t^SLOV

t^IVSH

tSHIX

t^SHSL

t^SLSH

tSLOV

t^IVSH

tSHIX

UCK0

UCK0, UO0

UCK0, UI0

UCK0

4 t^MCLK*

− 190

ns

Internal clock

operation

output pin :

+ 190

⎯

Valid UI → UCK ↑

2 tMCLK*

4 t^MCLK*

4 tMCLK*

0

C^L= 80 pF + 1TTL.

UCK ↑ → valid UI hold time

Serial clock “H” pulse width

Serial clock “L” pulse width

UCK ↓ → UO time

⎯

External clock

operation

output pin :

UCK0

⎯

UCK0, UO0

UCK0, UI0

190

⎯

Valid UI → UCK ↑

2 tMCLK*

C^L= 80 pF + 1TTL.

UCK ↑ → valid UI hold time

⎯

* : Refer to “ (2) Source Clock/Machine Clock” for t^MCLK.

• Internal shift clock mode

2.4 V

UCK0

0.8 V

tSLOV

UO0

UI0

2.4 V

0.8 V

tIVSH

tSHIX

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

• External shift clock mode

UCK0

tSLSH

tSHSL

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

tSLOV

UO0

UI0

2.4 V

0.8 V

tIVSH

tSHIX

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

42

MB95140 Series

(7) LIN-UART Timing

Sampling at the rising edge of sampling clock*¹and prohibited serial clock delay*²

(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 0)

(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C)

Value

Sym-

bol

Parameter

Pin name

Conditions

Unit

Min

5 t^MCLK*³

−95

Max

Serial clock cycle time

SCK ↓ → SOT delay time

Valid SIN → SCK ↑

t^SCYC

SCK

⎯

ns

Internal clock

operation output pin :

C^L= 80 pF + 1 TTL.

tSLOVI SCK, SOT

+ 95

t^IVSHI

t^SHIXI

tSLSH

t^SHSL

SCK, SIN

SCK

tMCLK*³+ 190

⎯

SCK ↑ → valid SIN hold time

Serial clock “L” pulse width

Serial clock “H” pulse width

SCK ↓ → SOT delay time

Valid SIN → SCK ↑

0

3 t^MCLK*³− tR

tMCLK*³+ 95

⎯

SCK

⎯

t^SLOVESCK, SOT

2 tMCLK*³+ 95

External clock

t^IVSHESCK, SIN operationoutputpin:

190

⎯

10

C^L= 80 pF + 1 TTL.

SCK ↑ → valid SIN hold time

SCK fall time

t^SHIXESCK, SIN

tMCLK*³+ 95

⎯

t^F

SCK

SCK rise time

t^R

⎯

*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the

serial clock.

*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.

*3 : Refer to “ (2) Source Clock/Machine Clock” for t^MCLK.

43

MB95140 Series

• Internal shift clock mode

SCK

t

SCYC

2.4 V

0.8 V

t

SLOVI

2.4 V

0.8 V

SOT

SIN

t

IVSHI

tSHIXI

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

• External shift clock mode

SCK

tSHSL

tSLSH

0.8 VCC

0.2 VCC

t

R

t

F

t

SLOVE

2.4 V

0.8 V

SOT

SIN

t

IVSHE

t

SHIXE

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

44

MB95140 Series

Sampling at the falling edge of sampling clock*¹and prohibited serial clock delay*²

(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0)

(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C)

Value

Sym-

bol

Parameter

Pin name

Conditions

Unit

Min

5 t^MCLK*³

−95

Max

Serial clock cycle time

SCK ↑ → SOT delay time

Valid SIN → SCK ↓

t^SCYC

t^SHOVI

tIVSLI

t^SLIXI

t^SHSL

tSLSH

SCK

SCK, SOT

SCK, SIN

SCK

⎯

ns

Internal clock

operation output pin :

C^L= 80 pF + 1 TTL.

+ 95

tMCLK*³+ 190

⎯

SCK ↓ → valid SIN hold time

Serial clock “H” pulse width

Serial clock “L” pulse width

SCK ↑ → SOT delay time

Valid SIN → SCK ↓

0

3 t^MCLK*³− tR

tMCLK*³+ 95

⎯

SCK

⎯

t^SHOVESCK, SOT

2 tMCLK*³+ 95

External clock

t^IVSLE

t^SLIXE

t^F

SCK, SIN operation output pin :

190

⎯

10

C^L= 80 pF + 1 TTL.

SCK ↓ → valid SIN hold time

SCK fall time

SCK, SIN

tMCLK*³+ 95

⎯

SCK

SCK rise time

t^R

⎯

*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the

serial clock.

*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.

*3 : Refer to “ (2) Source Clock/Machine Clock” for t^MCLK.

45

MB95140 Series

• Internal shift clock mode

SCK

t

SCYC

2.4 V

0.8 V

t

SHOVI

2.4 V

0.8 V

SOT

SIN

tSLIXI

tIVSLI

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

• External shift clock mode

SCK

tSHSL

tSLSH

0.8 VCC

0.2 VCC

tF

t

R

tSHOVE

2.4 V

0.8 V

SOT

SIN

tIVSLE

t

SLIXE

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

46

MB95140 Series

Sampling at the rising edge of sampling clock*¹and enabled serial clock delay*²

(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1)

(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C)

Value

Sym-

bol

Parameter

Pin name

Conditions

Unit

Min

Max

⎯

Serial clock cycle time

SCK ↑ → SOT delay time

Valid SIN → SCK ↓

t^SCYC

t^SHOVI

tIVSLI

SCK

5 tMCLK*³

ns

SCK, SOT

−95

+ 95

⎯

Internal clock

SCK, SIN operation output pin : tMCLK*³+ 190

CL = 80 pF + 1 TTL.

SCK ↓ → valid SIN hold time

SOT → SCK ↓ delay time

t^SLIXI

SCK, SIN

SCK, SOT

0

⎯

4 tMCLK*³

t^SOVLI

⎯

*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of

the serial clock.

*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.

*3 : Refer to “ (2) Source Clock/Machine Clock” for t^MCLK.

tSCYC

2.4 V

SCK

0.8 V

tSHOVI

tSOVLI

2.4 V

0.8 V

2.4 V

0.8 V

SOT

SIN

tSLIXI

tIVSLI

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

47

MB95140 Series

Sampling at the falling edge of sampling clock*¹and enabled serial clock delay*²

(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1)

(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C)

Value

Sym-

bol

Parameter

Pin name

Conditions

Unit

Min

Max

⎯

Serial clock cycle time

SCK ↓ → SOT delay time

Valid SIN → SCK ↑

t^SCYC

t^SLOVI

tIVSHI

t^SHIXI

t^SOVHI

SCK

5 tMCLK*³

ns

SCK, SOT

−95

+ 95

⎯

Internal clock

SCK, SIN operating output pin : tMCLK*³+ 190

CL = 80 pF + 1 TTL.

SCK ↑ → valid SIN hold time

SOT → SCK ↑ delay time

SCK, SIN

SCK, SOT

0

⎯

4 tMCLK*³

⎯

*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the

serial clock.

*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.

*3 : Refer to “ (2) Source Clock/Machine Clock” for t^MCLK.

tSCYC

2.4 V

SCK

0.8 V

tSOVHI

t^SLOVI

2.4 V

0.8 V

2.4 V

0.8 V

SOT

SIN

tSHIXI

tIVSHI

0.8 V^CC

0.2 VCC

0.8 VCC

0.2 VCC

48

MB95140 Series

5. A/D Converter

(1) A/D Converter Electrical Characteristics

(AV^CC= VCC = 1.8 V to 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)

Value

Sym-

bol

Parameter

Resolution

Unit

Remarks

Min

⎯

Typ

⎯

Max

10

bit

Total error

− 3.0

− 2.5

⎯

+ 3.0

+ 2.5

LSB

⎯

Linearity error

⎯

Differential linear

error

− 1.9

⎯

+ 1.9

LSB

AVSS − 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB

AVSS − 0.5 LSB AVSS + 1.5 LSB AVSS + 3.5 LSB

AVCC − 3.5 LSB AVCC − 1.5 LSB AVCC + 0.5 LSB

AVCC − 2.5 LSB AVCC − 0.5 LSB AVCC + 1.5 LSB

V

2.7 V ≤ AVCC ≤ 3.3 V

1.8 V ≤ AVCC < 2.7 V

2.7 V ≤ AVCC ≤ 3.3 V

1.8 V ≤ AVCC < 2.7 V

2.7 V ≤ AVCC ≤ 3.3 V

1.8 V ≤ AV^CC< 2.7 V

Zero transition

voltage

V^OT

V^FST

⎯

V

Full-scale transition

voltage

V

0.6

20

⎯

140

µs

Compare time

2.7 V ≤ AVCC ≤ 3.3 V

external impedance <

at 1.8 kΩ

0.4

30

⎯

∞

µs

Sampling time

⎯

1.8 V ≤ AV^CC< 2.7 V

external impedance <

at 14.8 kΩ

Analog input current

Analog input voltage

Reference voltage

I^AIN

VAIN

⎯

−0.3

AVSS

⎯

+ 0.3

AVCC

µA

V

AV^SS+ 1.8

V

AVCC pin

AVCC pin,

During A/D operation

IR

⎯

400

600

5

µA

Reference voltage

supply current

AV^CCpin,

At stop mode

IRH

⎯

49

MB95140 Series

(2) Notes on Using A/D Converter

• About the external impedance of analog input and its sampling time

• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling

time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting

A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship

between the external impedance and minimum sampling time and either adjust the register value and operating

frequency or decrease the external impedance so that the sampling time is longer than the minimum value.

Also, if the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.

• Analog input equivalent circuit

R

Analog input

Comparator

C

During sampling : ON

R

C

2.7 V ≤ AV^CC≤ 3.6 V

1.8 V ≤ AV^CC< 2.7 V

1.7 kΩ (Max)

84 kΩ (Max)

14.5 pF (Max)

25.2 pF (Max)

Note : The values are reference values.

• The relationship between external impedance and minimum sampling time

(External impedance = 0 kΩ to 20 kΩ)

(External impedance = 0 kΩ to 100 kΩ)

AV^CC≥ 2.7 V

100

20

90

80

70

60

18

16

14

12

10

8

AVCC ≥ 1.8 V

50

40

30

20

10

0

6

4

2

0

5

10 15 20 25 30 35 40

0

1

2

3

4

Minimum sampling time [µs]

• About errors

As |AV^CC− AVSS| becomes smaller, values of relative errors grow larger.

50

MB95140 Series

(3) Definition of A/D Converter Terms

• Resolution

The level of analog variation that can be distinguished by the A/D converter.

When the number of bits is 10, analog voltage can be divided into 2¹⁰= 1024.

• Linearity error (unit : LSB)

The deviation between the value along a straight line connecting the zero transition point

(“00 0000 0000” ← → “00 0000 0001”) of a device and the full-scale transition point

(“11 1111 1111” ← → “11 1111 1110”) compared with the actual conversion values obtained.

• Differential linear error (Unit : LSB)

Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.

• Total error (unit: LSB)

Difference between actual and theoretical values, caused by a zero transition error, full-scale transition error,

linearity error, quantum error, and noise.

Ideal I/O characteristics

Total error

V

FST

3FF

H

3FFH

3FE

H

3FE

H

Actual conversion

characteristic

1.5 LSB

3FD

H

3FD

H

{1 LSB × (N − 1) + 0.5 LSB}

004

003

002

001

H

004

003

002

001

H

V

NT

VOT

Actual conversion

characteristic

1 LSB

0.5 LSB

Ideal characteristics

AVSS

AVCC

Analog input

V^NT− {1 LSB × (N − 1) + 0.5 LSB}

Total error of

digital output N

AV^CC− AVSS

=

1 LSB =

(V)

[LSB]

1024

1 LSB

N

: A/D converter digital output value

VNT : A voltage at which digital output transits from (N − 1) to N.

(Continued)

51

MB95140 Series

(Continued)

Full-scale transition error

Zero transition error

Ideal characteristics

004H

003H

002H

001H

Actual conversion

characteristic

3FFH

3FEH

3FDH

3FCH

Actual conversion

characteristic

Ideal

characteristics

VFST

(measurement

value)

Actual conversion

characteristic

Actual conversion

characteristic

VOT (measurement value)

AVSS

AVCC

AVSS

AVCC

Analog input

Linearity error

Differential linear error

Actual conversion

characteristic

Ideal characteristics

3FFH

3FEH

3FDH

N+1H

NH

Actual conversion

characteristic

{1 LSB × N + VOT}

V (N+1)T

V^FST

(measurement

value)

V^NT

004H

003H

002H

001H

N-1H

N-2H

VNT

Actual conversion

characteristic

Actual conversion

characteristic

Ideal characteristics

VOT (measurement value)

AVSS

AVCC

AVSS

AVCC

Analog input

V^NT− {1 LSB × N + VOT}

Linear error in

digital output N

V ^(N+ 1) T − VNT

Differentiallinearerror

in digital output N

=

− 1

1 LSB

N

: A/D converter digital output value

VNT : A voltage at which digital output transits from (N − 1) to N.

VOT (Ideal value) = AVSS + 0.5 LSB [V]

VFST (Ideal value) = AVCC − 1.5 LSB [V]

52

MB95140 Series

6. Flash Memory Program/Erase Characteristics

Value

Parameter

Unit

Remarks

Min

⎯

Typ

1*¹

32

Max

1.5*²

3600*²

⎯

Chip erase time

s

Excludes 00H programming prior erasure.

Byte programming time

Program/erase cycle

⎯

µs Excludes system-level overhead time.

cycle

10000

⎯

Power supply voltage at

program/erase

2.7

⎯

3.3

V

Flash memory data retention

time

20*³

⎯

year Average TA = +85 °C

*1 : TA = + 25 °C, VCC = 3.0 V, 10000 cycles

*2 : TA = + 85 °C, VCC = 2.7 V, 10000 cycles

*3 : This value comes from the technology qualification (using Arrhenius equation to translate high temperature

measurements into normalized value at +85 °C) .

53

MB95140 Series

■ MASK OPTION

Part number

No.

MB95F146S

MB95F146W

MB95FV100D-101

Setting disabled

Specifying procedure

Setting disabled

Clock mode select*

• Single-system clock mode

• Dual-system clock mode

Single-system

clock mode

Dual-system

clock mode

Changing by the

switch on MCU board

1

2

3

Low voltage detection reset*

• With low voltage detection reset

• Without low voltage

No

detection reset

Clock supervisor*

• With clock supervisor

• Without clock supervisor

Selection of oscillation

stabilization wait time

• Selectable the initial value of

main clock oscillation stabilization

wait time

Fixed to oscillation

stabilization wait

Fixed to oscillation

stabilization wait

Fixed to oscillation

stabilization wait time

4

time of (2¹⁴− 2) /FCH time of (2¹⁴− 2) /FCH of (2¹⁴− 2) /FCH

* : Low voltage detection reset and clock supervisor are options of 5-V products.

54

MB95140 Series

■ ORDERING INFORMATION

Part number

Package

MB95F146SPFM

MB95F146WPFM

32-pin plastic LQFP

(FPT-32P-M21)

MCU board

224-pin plastic PFBGA

MB2146-301A

(MB95FV100D-101PBT)

(

)

(BGA-224P-M08)

55

MB95140 Series

■ PACKAGE DIMENSIONS

32-pin plastic LQFP

Lead pitch

0.80 mm

7 × 7 mm

Package width ×

package length

Lead shape

Sealing method

Mounting height

Gullwing

Plastic mold

1.70 mm MAX

P-LQFP32-7×7-0.80

Code

(Reference)

(FPT-32P-M21)

32-pin plastic LQFP

(FPT-32P-M21)

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

9.00 0.20(.354 .008)SQ

*

7.00 0.10(.276 .004)SQ

0.145 0.055

(.0057 .0022)

24

17

25

16

Details of "A" part

1.50 ⁺^–0⁰^.^.¹²⁰⁰

(Mounting height)

0.10(.004)

.059 –⁺.^.0⁰0⁰4⁸

0.25(.010)

INDEX

0~8˚

32

9

0.50 0.20

0.10 0.10

(.020 .008)

(.004 .004)

(Stand off)

1

8

"A"

0.60 0.15

(.024 .006)

0.80(.031)

0.32 0.05

(.013 .002)

M

0.20(.008)

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

C

2002 FUJITSU LIMITED F32032S-c-3-5

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html

56

MB95140 Series

■ MAIN CHANGES IN THIS EDITION

Page

Section

Change Results

⎯

Preliminary Data Sheet→Data Sheet

Changed the part number

MB95FV100B-101→MB95FV100D-101

⎯

CPU functions

Minimum instruction execution time : 0.1 µs

(at machine clock frequency 10 MHz)

→Minimum instruction execution time : 61.5 ns

(at machine clock frequency 16.25 MHz)

Interrupt processing time : 0.9 µs

3

■ PRODUCT LINEUP

(at machine clock frequency 10 MHz)

→Interrupt processing time : 0.6 µs

(at machine clock frequency 16.25 MHz)

4

Added the description Flash memory

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

Changed under the table*3;

V^I1→VI

27

Changed the Min value of power supply voltage V^CC, AVCC.

T^A= − 10 °C to + 85 °C 1.8→2.3

28

2. Recommended Operating Conditions

T^A= − 40 °C to + 85 °C 2.0→2.4

Moved “H” level input voltage and “L” level input voltage from

the section "2. Recommended Operating Conditions".

Added to F^MP= 16 MHz in the section of ICC, ICCS, ICCMPLL of

power supply voltage.

29, 30 3. DC Characteristics

Changed the Typ and Max values of I^CTS

0.4 → 0.64 (Typ value)

0.5 → 0.80 (Max value)

Changed the Max values of clock frequency X0, X1.

When using main oscillation circuit 10→16.25

When using external clock 20→32.50

4. AC Characteristics

(1) Clock Timing

32

Main PLL multiplied by 2 : 5→8.13

Main PLL multiplied by 2.5 : 4 →6.50

Added the Main PLL multiplied by 4

Changed source clock cycle time (when using main clock)

Min : F^CH= 10 MHz, PLL multiplied by 1

→Min : F^CH= 8.125 MHz, PLL multiplied by 2

Changed the Max value of source clock frequency F^SP.

10→16.25

34

(2) Source Clock/Machine Clock

Changed machine clock cycle time (when using main clock)

Min : F^SP= 10 MHz→Min : FSP = 16.25 MHz

Changed the Max value of machine clock frequency F^MP.

10 .000→16.250

(Continued)

57

MB95140 Series

(Continued)

Page

Section

Change Results

Changed the diagram of • Outline of Clock Generation

Block

35

4. AC Characteristics

(2) Source Clock/Machine Clock

Changed the diagram of • Operating voltage - Operating

36, 37

38

frequency

Changed the diagram of • Main PLL operation frequency

range.

Changed the pin name in the value section of full-scale

transition voltage;

AVR→AV^CC

5. A/D Converter

(1) A/D Converter Electrical Characteristics

49

The part number is revised as follows;

MB2146-301 MB2146-301A

55 ■ ORDERING INFORMATION

The vertical lines marked in the left side of the page show the changes.

58

MB95140 Series

The information for microcontroller supports is shown in the following homepage.

http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

The company names and brand names herein are the trademarks or

registered trademarks of their respective owners.

Edited

Business Promotion Dept.

F0701


型号：	MB2146-301A
厂家：	FUJITSU
描述：	8-bit Proprietary Microcontrollers 8位微控制器专用微控制器
文件：	总59页 (文件大小：550K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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