MB81F643242C-70 [FUJITSU]
4 X 512 K X 32 BIT SYNCHRONOUS DYNAMIC RAM; 4× 512 ; K X 32位同步动态RAM
| 型号： | MB81F643242C-70 |
| 厂家： | 
FUJITSU |
| 描述： | 4 X 512 K X 32 BIT SYNCHRONOUS DYNAMIC RAM |
| 文件： | 总56页 (文件大小：935K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
ADVANCED INFO.
AE0.1E
MEMORY
CMOS
4 × 512 K × 32 BIT
SYNCHRONOUS DYNAMIC RAM
MB81F643242C-60/-70/-10
CMOS 4-Bank × 524,288-Word × 32 Bit
Synchronous Dynamic Random Access Memory
■ DESCRIPTION
The Fujitsu MB81F643242C is a CMOS Synchronous Dynamic Random Access Memory (SDRAM) containing
67,108,864 memory cells accessible in a 32-bit format. The MB81F643242C features a fully synchronous
operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which
enables high performance and simple user interface coexistence. The MB81F643242C SDRAM is designed to
reduce the complexity of using a standard dynamic RAM (DRAM) which requires many control signal timing
constraints, and may improve data bandwidth of memory as much as 5 times more than a conventional DRAM.
The MB81F643242C is ideally suited for workstations, personal computers, laser printers, high resolution graphic
adapters/accelerators and other applications where an extremely large memory and bandwidth are required and
where a simple interface is needed.
■ PRODUCT LINE & FEATURES
MB81F643242C
-70
Reference
Value@ 67 MHz,
CL=3
Parameter
CL - tRCD - tRP
-60
-10
CL = 2 2 - 2 - 2 clk min.
CL = 3 3 - 3 - 3 clk min.
167 MHz max.
2 - 2 - 2 clk min.
3 - 3 - 3 clk min.
143 MHz max.
10 ns min.
2 - 2 - 2 clk min.
3 - 3 - 3 clk min.
100 MHz max.
15 ns min.
2 - 2 - 2 clk min.
3 - 3 - 3 clk min.
67 MHz max.
20 ns min.
Clock Frequency
CL = 2
CL = 3
CL = 2
CL = 3
10 ns min.
6 ns min.
Burst Mode Cycle Time
7 ns min.
10 ns min.
15 ns min.
6 ns max.
6 ns max.
7 ns max.
7 ns max.
Access Time from Clock
Operating Current
5.5 ns max.
165 mA max.
5.5 ns max.
155 mA max.
7 ns max.
7 ns max.
115 mA max.
100 mA max.
Power Down Mode Current (ICC2P)
Self Refresh Current (ICC6)
2 mA max.
2 mA max.
• Single +3.3 V Supply ±0.3 V tolerance
• LVTTL compatible I/O interface
• 4 K refresh cycles every 64 ms
• Four bank operation
• Programmable burst type, burst length, and
CAS latency
• Auto-and Self-refresh (every 15.6 µs)
• CKE power down mode
• Burst read/write operation and burst
read/single write operation capability
• Output Enable and Input Data Mask
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
■ PACKAGE
86 pin Plastic TSOP(II) Package
(FPT-86P-M01)
(Normal Bend)
Package and Ordering Information
– 86-pin plastic (10.16 × 22.22 mm) TSOP-II without SCITT Function, order as MB81F643242C-××FN
– 86-pin plastic (10.16 × 22.22 mm) TSOP-II with SCITT Function, order as MB81F643242C-××FN-S
2
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
■ PIN ASSIGNMENTS AND DESCRIPTIONS
86-Pin TSOP(II)
(TOP VIEW)
<Normal Bend: FPT-86P-M01>
VCC
DQ0
VCCQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VCCQ
DQ5
DQ6
VSSQ
DQ7
N.C.
VCC
DQM0
WE
CAS
RAS
CS
N.C.
BA0
BA1
VSS
1
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
DQ15
VSSQ
DQ14
DQ13
VCCQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VCCQ
DQ8
N.C.
VSS
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
DQM1
N.C.
N.C.
CLK
CKE
A9
A8
A7
A10/AP
A0
A6
A5
A1
A2
A4
A3
DQM2
VCC
DQM3
VSS
N.C.
DQ16
VSSQ
DQ17
DQ18
VCCQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VCCQ
DQ23
VCC
N.C.
DQ31
VCCQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VCCQ
DQ26
DQ25
VSSQ
DQ24
VSS
3
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
Pin Number
Symbol
Function
1, 3, 9, 15, 29, 35, 41, 43, 49, 55, 75, 81
VCC, VCCQ
Supply Voltage
Data I/O
2, 4, 5, 7, 8, 10, 11, 13, 31, 33, 34, 36, 37,
39, 40, 42, 45, 47, 48, 50, 51, 53, 54, 56,
74, 76, 77, 79, 80, 82, 83, 85
DQ0 to DQ31
6, 12, 32, 38, 44, 46, 52, 58, 72, 78, 84, 86
VSS, VSSQ
N.C.
Ground
14, 21, 30, 57, 69, 70, 73
No Connection
Write Enable
17
18
WE
CAS
Column Address Strobe
Row Address Strobe
Chip Select
19
RAS
20
CS
22, 23
24
BA1, BA0
AP
Bank Select (Bank Address)
Auto Precharge Enable
• Row: A0 to A10
• Column: A0 to A7
24, 25, 26, 27, 60, 61, 62, 63, 64, 65, 66
A0 to A10
Address Input
67
68
CKE
CLK
Clock Enable
Clock Input
16, 28, 59, 71
DQM0 to DQM3
Input Mask/Output Enable
4
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
■ BLOCK DIAGRAM
Fig. 1 – MB81F643242C BLOCK DIAGRAM
CLK
To each block
BANK-3
CLOCK
BUFFER
BANK-2
CKE
BANK-1
BANK-0
RAS
CS
CONTROL
SIGNAL
CAS
LATCH
RAS
COMMAND
DECODER
WE
CAS
WE
DRAM
CORE
MODE
REGISTER
(2,048 × 256 × 32)
A0 to A9,
A10/AP
ADDRESS
BUFFER/
REGISTER
ROW
ADDR.
BA1
BA0
COL.
ADDR.
DQM0
to
DQM3
COLUMN
ADDRESS
I/O
COUNTER
I/O DATA
BUFFER/
REGISTER
VCC
DQ0
to
DQ31
VCCQ
VSS
VSSQ
5
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
■ FUNCTIONAL TRUTH TABLE Note *1
COMMAND TRUTH TABLE Note *2, *3, and *4
CKE
A9
to
A8
A7
to
A0
BA1,
A10
Function
Notes Symbol
CS RAS CAS WE
BA0 (AP)
n-1
H
H
H
H
H
H
H
H
H
H
H
n
X
X
X
X
X
X
X
X
X
X
X
Device Deselect
*5 DESL
*5 NOP
BST
H
L
L
L
L
L
L
L
L
L
L
X
H
H
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
V
V
V
V
V
V
X
L
X
X
X
L
X
X
X
X
X
X
X
V
X
X
V
X
X
X
V
V
V
V
V
X
X
V
No Operation
Burst Stop
Read
*6 READ
*6 READA
*6 WRIT
*6 WRITA
*7 ACTV
PRE
H
H
L
Read with Auto-precharge
Write
L
H
L
L
Write with Auto-precharge
Bank Active
L
L
H
V
L
H
H
H
L
H
L
Precharge Single Bank
Precharge All Banks
Mode Register Set
L
PALL
L
L
H
L
*8, *9 MRS
L
L
Notes: *1. V = Valid, L = Logic Low, H = Logic High, X = either L or H.
*2. All commands assumes no CSUS command on previous rising edge of clock.
*3. All commands are assumed to be valid state transitions.
*4. All inputs are latched on the rising edge of clock.
*5. NOP and DESL commands have the same effect on the part. Unless specifically noted, NOP will
represent both NOP and DESL command in later descriptions.
*6. READ, READA, WRIT and WRITA commands should only be issued after the corresponding bank has
been activated (ACTV command). Refer to “STATE DIAGRAM” in section “■ FUNCTIONAL
DESCRIPTION“.
*7. ACTV command should only be issued after corresponding bank has been precharged (PRE or PALL
command).
*8. Required after power up.
*9. MRS command should only be issued after all banks have been precharged (PRE or PALL command).
Refer to “STATE DIAGRAM” in section “■ FUNCTIONAL DESCRIPTION“.
6
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
DQM TRUTH TABLE
Function
CKE
DQMi *1, *2
Symbol
n-1
H
n
X
X
Data Write/Output Enable
Data Mask/Output Disable
ENBi *1
L
MASKi *1
H
H
Notes: *1. i = 0, 1, 2, 3
*2. DQM0 for DQ0 to DQ7, DQM1 for DQ8 to DQ15, DQM2 for DQ16 to DQ23, DQM3 for DQ24 to DQ31,
CKE TRUTH TABLE
CKE
A9
to
A0
Current
State
BA1, A10
BA0 (AP)
Function
Notes Symbol
CS RAS CAS WE
n-1
n
Bank Active Clock Suspend Mode Entry
*1 CSUS
*1
H
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Any
Clock Suspend Continue
(Except Idle)
L
Clock
Clock Suspend Mode Exit
Suspend
L
H
X
X
X
X
X
X
X
Idle
Idle
Auto-refresh Command
Self-refresh Entry
*2 REF
H
H
L
H
L
L
L
L
L
L
L
H
H
H
X
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
*2, *3 SELF
H
H
L
L
H
X
H
X
H
X
H
X
H
X
H
X
Self Refresh Self-refresh Exit
*4 SELFX
L
H
L
H
H
L
Idle
Power Down Entry
*3
PD
L
H
L
H
H
Power Down Power Down Exit
L
H
Notes: *1. The CSUS command requires that at least one bank is active. Refer to “STATE DIAGRAM” in section
“■ FUNCTIONAL DESCRIPTION“.
NOP or DSEL commands should only be issued after CSUS and PRE(or PALL) commands asserted
at the same time.
*2. REF and SELF commands should only be issued after all banks have been precharged (PRE or PALL
command). Refer to “STATE DIAGRAM” in section “■ FUNCTIONAL DESCRIPTION“.
*3. SELF and PD commands should only be issued after the last read data have been appeared on DQ.
*4. CKE should be held high within one tRC period after tCKSP.
7
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
OPERATION COMMAND TABLE (Applicable to single bank)
Current
CS RAS CAS WE
Addr
Command
Function
Notes
State
Idle
H
L
L
L
L
L
L
L
X
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
DESL
NOP
BST
NOP
NOP
NOP
H
L
BA, CA, AP READ/READA Illegal
*2
*2
L
BA, CA, AP
BA, RA
BA, AP
X
WRIT/WRITA Illegal
H
H
L
H
L
ACTV
Bank Active after tRCD
NOP
L
PRE/PALL
REF/SELF
L
H
Auto-refresh or Self-refresh
*3, *6
*3, *7
Mode Register Set
(Idle after tRSC)
L
L
L
L
MODE
MRS
Bank Active
H
L
L
L
L
L
L
L
L
X
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
DESL
NOP
BST
NOP
NOP
NOP
H
L
BA, CA, AP READ/READA Begin Read; Determine AP
L
BA, CA, AP
BA, RA
BA, AP
X
WRIT/WRITA Begin Write; Determine AP
H
H
L
H
L
ACTV
PRE/PALL
REF/SELF
MRS
Illegal
*2
L
Precharge; Determine Precharge Type
L
H
L
Illegal
L
L
MODE
Illegal
(Continued)
8
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
(Continued)
Current
State
CS RAS CAS WE
Addr
Command
Function
Notes
Read
NOP (Continue Burst to End → Bank
Active)
H
X
X
X
X
DESL
NOP (Continue Burst to End → Bank
Active)
L
L
L
H
H
H
H
H
L
H
L
X
X
NOP
BST
Burst Stop → Bank Active
Terminate Burst, New Read;
Determine AP
H
BA, CA, AP READ/READA
Terminate Burst, Start Write;
Determine AP
L
L
L
H
L
L
L
H
H
L
H
L
BA, CA, AP
BA, RA
WRIT/WRITA
ACTV
*4
Illegal
*2
Terminate Burst, Precharge → Idle;
Determine Precharge Type
BA, AP
PRE/PALL
L
L
L
L
L
L
H
L
X
REF/SELF
MRS
Illegal
Illegal
MODE
Write
NOP (Continue Burst to End →
Bank Active)
H
X
X
X
X
DESL
NOP (Continue Burst to End →
Bank Active)
L
L
L
H
H
H
H
H
L
H
L
X
X
NOP
BST
Burst Stop → Bank Active
Terminate Burst, Start Read;
Determine AP
*4
*2
H
BA, CA, AP READ/READA
Terminate Burst, New Write;
Determine AP
L
L
L
H
L
L
L
H
H
L
H
L
BA, CA, AP
BA, RA
WRIT/WRITA
ACTV
Illegal
Terminate Burst, Precharge;
Determine Precharge Type
BA, AP
PRE/PALL
L
L
L
L
L
L
H
L
X
REF/SELF
MRS
Illegal
Illegal
MODE
(Continued)
9
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
(Continued)
Current
State
CS RAS CAS WE
Addr
Command
Function
Notes
Read with
Auto-
precharge
NOP (Continue Burst to End →
Precharge → Idle)
H
L
X
H
X
H
X
H
X
DESL
NOP (Continue Burst to End →
Precharge → Idle)
X
X
NOP
BST
L
L
L
L
L
L
L
H
H
H
L
H
L
L
H
L
Illegal
BA, CA, AP READ/READA Illegal
*2
*2
*2
*2
L
BA, CA, AP
BA, RA
BA, AP
X
WRIT/WRITA Illegal
H
H
L
H
L
ACTV
PRE/PALL
REF/SELF
MRS
Illegal
Illegal
Illegal
Illegal
L
L
H
L
L
L
MODE
Write with
Auto-
precharge
NOP (Continue Burst to End →
Precharge → Idle)
H
L
X
H
X
H
X
H
X
DESL
NOP (Continue Burst to End →
Precharge → Idle)
X
X
NOP
BST
L
L
L
L
L
L
L
H
H
H
L
H
L
L
H
L
Illegal
BA, CA, AP READ/READA Illegal
*2
*2
*2
*2
L
BA, CA, AP
BA, RA
BA, AP
X
WRIT/WRITA Illegal
H
H
L
H
L
ACTV
PRE/PALL
REF/SELF
MRS
Illegal
Illegal
Illegal
Illegal
L
L
H
L
L
L
MODE
(Continued)
10
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
(Continued)
Current
State
CS RAS CAS WE
Addr
Command
Function
Notes
Pre-
charging
H
L
L
L
L
L
X
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
DESL
NOP
BST
NOP (Idle after tRP)
NOP (Idle after tRP)
NOP (Idle after tRP)
H
L
BA, CA, AP READ/READA Illegal
*2
*2
*2
L
BA, CA, AP
BA, RA
WRIT/WRITA Illegal
H
H
ACTV
Illegal
NOP (PALL may affect other
bank)
L
L
H
L
BA, AP
PRE/PALL
*5
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
H
L
X
REF/SELF
MRS
Illegal
MODE
Illegal
Bank
Activating
X
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
DESL
NOP
NOP (Bank Active after tRCD)
NOP (Bank Active after tRCD)
NOP (Bank Active after tRCD)
BST
H
L
BA, CA, AP READ/READA Illegal
*2
*2
*2
*2
L
BA, CA, AP
BA, RA
BA, AP
X
WRIT/WRITA Illegal
H
H
L
H
L
ACTV
PRE/PALL
REF/SELF
MRS
Illegal
Illegal
Illegal
Illegal
L
L
H
L
L
L
MODE
(Continued)
11
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
(Continued)
Current
State
CS RAS CAS WE
Addr
Command
Function
Notes
Refreshing
H
L
X
H
X
H
X
X
X
X
DESL
NOP (Idle after tRC)
NOP (Idle after tRC)
NOP/BST
READ/READA/
WRIT/WRITA
L
L
L
H
L
L
L
H
L
X
X
X
X
X
X
Illegal
Illegal
Illegal
ACTV/
PRE/PALL
REF/SELF/
MRS
Mode
Register
Setting
H
L
L
X
H
H
X
H
H
X
H
L
X
X
X
DESL
NOP
BST
NOP (Idle after tRSC)
NOP (Idle after tRSC)
Illegal
READ/READA/
WRIT/WRITA
L
L
H
L
L
X
X
X
X
Illegal
Illegal
ACTV/PRE/
PALL/REF/
SELF/MRS
X
ABBREVIATIONS:
RA = Row Address
BA = Bank Address
AP = Auto Precharge
CA = Column Address
Notes: *1. All entries in OPERATION COMMAND TABLE assume the CKE was High during the proceeding clock
cycle and the current clock cycle.
Illegal means don’t used command. If used, power up sequence be asserted after power shut down.
*2. Illegal to bank in specified state; entry may be legal in the bank specified by BA, depending on the state
of that bank.
*3. Illegal if any bank is not idle.
*4. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
Refer to “TIMING DIAGRAM -11 & -12” in section “■ TIMING DIAGRAMS“.
*5. NOP to bank precharging or in idle state. May precharge bank specified by BA (and AP).
*6. SELF command should only be issued after the last read data have been appeared on DQ.
*7. MRS command should only be issued on condition that all DQ are in Hi-Z.
12
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
COMMAND TRUTH TABLE FOR CKE Note *1
Current
State
CKE CKE
CS RAS CAS WE
Addr
X
Function
Notes
n-1
n
Self-
refresh
H
X
X
H
X
X
X
X
X
X
Invalid
Exit Self-refresh
L
L
H
H
X
(Self-refresh Recovery → Idle after tRC)
Exit Self-refresh
(Self-refresh Recovery → Idle after tRC)
L
H
H
H
X
L
L
H
H
H
L
L
L
H
H
L
H
L
L
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
Illegal
Illegal
L
L
X
X
X
X
H
H
L
Illegal
L
X
X
H
L
X
X
X
H
H
H
L
NOP (Maintain Self-refresh)
Self-
refresh
Recovery
L
X
H
H
H
H
H
H
L
Invalid
H
H
H
H
H
H
H
Idle after tRC
Idle after tRC
Illegal
L
L
X
X
X
X
Illegal
L
X
X
X
Illegal
X
X
X
X
Illegal
Illegal
*2
(Continued)
13
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
(Continued)
Current
State
CKE CKE
CS RAS CAS WE
Addr
Function
Notes
n-1
H
L
n
X
H
H
L
Power
Down
X
H
L
X
X
H
X
L
X
X
H
X
X
L
X
X
H
X
X
X
X
X
X
X
X
X
Invalid
Exit Power Down Mode → Idle
L
L
X
L
NOP (Maintain Power Down Mode)
L
H
H
Illegal
Illegal
L
L
H
All
Banks
Idle
Refer to the Operation Command
Table.
H
H
H
H
H
L
X
H
X
X
X
X
MODE
MODE
Refer to the Operation Command
Table.
Refer to the Operation Command
Table.
H
H
H
H
H
H
L
L
L
L
L
L
H
L
L
X
H
L
MODE
X
Auto-refresh
Refer to the Operation Command
Table.
MODE
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
X
H
L
L
L
L
L
L
X
X
H
H
H
L
X
H
H
L
X
H
L
X
X
X
X
X
X
X
X
Power Down
Power Down
Illegal
X
X
H
L
Illegal
H
L
Illegal
L
Self-refresh
Illegal
*3
L
L
X
X
X
Invalid
(Continued)
14
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
(Continued)
Current
State
CKE CKE
CS RAS CAS WE
Addr
Function
Notes
n-1
n
Bank
Active,
Bank
Activating,
Refer to the Operation Command
Table.
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
L
Begin Clock Suspend next cycle
Invalid
Read/Write
X
Clock
Suspend
H
L
L
L
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Invalid
Exit Clock Suspend next cycle
Maintain Clock Suspend
Invalid
Any State
Other Than
Listed
X
Refer to the Operation Command
Table.
H
H
H
L
X
X
X
X
X
X
X
X
X
X
Above
Illegal
Notes: *1. All entries in “COMMAND TRUTH TABLE FOR CKE” are specified at CKE(n) state and CKE input
from CKE(n-1) to CKE(n) state must satisfy corresponding set up and hold time for CKE.
*2. CKE should be held High for tRC period.
*3. SELF command should only be issued after the last data have been appeared on DQ.
15
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
■ FUNCTIONAL DESCRIPTION
SDRAM BASIC FUNCTION
Three major differences between this SDRAM and conventional DRAMs are: synchronized operation, burst mode,
and mode register.
The synchronized operation is the fundamental difference. An SDRAM uses a clock input for the synchronization,
where the DRAM is basically asynchronous memory although it has been using two clocks, RAS and CAS. Each
operation of DRAM is determined by their timing phase differences while each operation of SDRAM is determined
by commands and all operations are referenced to a positive clock edge. Fig. 2 shows the basic timing diagram
differences between SDRAMs and DRAMs.
The burst mode is a very high speed access mode utilizing an internal column address generator. Once a column
addresses for the first access isset, following addresses are automaticallygenerated by the internal column address
counter.
The mode register is to justify the SDRAM operation and function into desired system conditions. MODE
REGISTER TABLE shows how SDRAM can be configured for system requirement by mode register programming.
CLOCK INPUT (CLK) and CLOCK ENABLE (CKE)
All input and output signals of SDRAM use register type buffers. A CLK is used as a trigger for the register and
internal burst counter increment. All inputs are latched by a positive edge of CLK. All outputs are validated by the
CLK. CKE is a high active clock enable signal. When CKE = Low is latched at a clock input during active cycle, the
next clock will be internally masked. During idle state (all banks have been precharged), the Power Down mode
(standby) is entered with CKE = Low and this will make extremely low standby current.
CHIP SELECT (CS)
CS enables all commands inputs, RAS, CAS, and WE, and address input. When CS is High, command signals are
negated but internal operation such as burst cycle will not be suspended. If such a control isn’t needed, CS can be
tied to ground level.
COMMAND INPUT (RAS, CAS and WE)
Unlike a conventional DRAM, RAS, CAS, and WE do not directly imply SDRAM operation, such as Row address
strobe by RAS. Instead, each combination of RAS, CAS, and WE input in conjunction with CS input at a rising edge
of the CLK determines SDRAM operation. Refer to “■ FUNCTIONAL TRUTH TABLE”.
ADDRESS INPUT (A0 to A10)
Address input selects an arbitrary location of a total of 524,288 words of each memory cell matrix. A total of nineteen
address input signals are required to decode such a matrix. SDRAM adopts an address multiplexer in order to
reduce the pin count of the address line. At a Bank Active command (ACTV), eleven Row addresses are initially
latched and the remainder of eight Column addresses are then latched by a Column address strobe command of
either a Read command (READ or READA) or Write command (WRIT or WRITA).
BANK SELECT (BA0, BA1)
This SDRAM has four banks and each bank is organized as 512 K words by 32-bit.
Bank selection by BA0, BA1 occurs at Bank Active command (ACTV) followed by read (READ or READA), write
(WRIT or WRITA), and precharge command (PRE).
16
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
DATA INPUT AND OUTPUT (DQ0 to DQ31)
Input data is latched and written into the memory at the clock following the write command input. Data output is
obtained by the following conditions followed by a read command input:
tRAC ; from the bank active command when tRCD (min) is satisfied. (This parameter is reference only.)
tCAC ; from the read command when tRCD is greater than tRCD (min). (This parameter is reference only.)
tAC ; from the clock edge after tRAC and tCAC.
The polarity of the output data is identical to that of the input. Data is valid between access time (determined by
the three conditions above) and the next positive clock edge (tOH).
DATA I/O MASK (DQM)
DQM is an active high enable input and has an output disable and input mask function. During burst cycle and
when DQM0 to DQM3 = High is latched by a clock, input is masked at the same clock and output will be masked at
the second clock later while internal burst counter will increment by one or will go to the next stage depending on
burst type. DQM0, DQM1, DQM2, DQM3, controls DQ0 to DQ7, DQ8 to DQ15, DQ16 to DQ23, DQ24 to DQ31, respectively.
BURST MODE OPERATION AND BURST TYPE
The burst mode provides faster memory access. The burst mode is implemented by keeping the same Row address
and by automatic strobing column address. Access time and cycle time of Burst mode is specified as tAC and tCK,
respectively. The internal column address counter operation is determined by a mode register which defines burst
type and burst count length of 1, 2, 4 or 8 bits of boundary. In order to terminate or to move from the current burst
mode to the next stage while the remaining burst count is more than 1, the following combinations will be required:
Current Stage
Next Stage
Method (Assert the following command)
Burst Read
Burst Read
Read Command
1st Step
2nd Step
Mask Command (Normally 3 clock cycles)
Write Command after lOWD
Burst Read
Burst Write
Burst Write
Burst Write
Burst Read
Burst Write
Burst Write
Burst Read
Precharge
Precharge
Write Command
Read Command
Precharge Command
Precharge Command
The burst type can be selected either sequential or interleave mode if burst length is 2, 4 or 8. The sequential mode
is an incremental decoding scheme within a boundary address to be determined by count length, it assigns +1 to
the previous (or initial) address until reaching the end of boundary address and then wraps round to least significant
address (= 0). The interleave mode is a scrambled decoding scheme for A0 and A2. If the first access of column
address is even (0), the next address will be odd (1), or vice-versa.When the full burst operation is executed at
single write mode, Auto-precharge command is valid only at write operation.
The burst type can be selected either sequential or interleave mode. But only the sequential mode is usable to the
full column burst. The sequential mode is an incremental decoding scheme within a boundary address to be
determined by burst length, it assigns +1 to the previous (or initial) address until reaching the end of boundary
address and then wraps round to least significant address (= 0).
17
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
Starting Column
Burst
Address
Sequential Mode
Interleave
Length
A2 A1 A0
X X 0
X X 1
X 0 0
X 0 1
X 1 0
X 1 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 – 1
0 – 1
2
1 – 0
1 – 0
0 – 1 – 2 – 3
0 – 1 – 2 – 3
1 – 2 – 3 – 0
1 – 0 – 3 – 2
4
2 – 3 – 0 – 1
2 – 3 – 0 – 1
3 – 0 – 1 – 2
3 – 2 – 1 – 0
0 – 1 – 2 – 3 – 4 – 5 – 6 – 7
1 – 2 – 3 – 4 – 5 – 6 – 7 – 0
2 – 3 – 4 – 5 – 6 – 7 – 0 – 1
3 – 4 – 5 – 6 – 7 – 0 – 1 – 2
4 – 5 – 6 – 7 – 0 – 1 – 2 – 3
5 – 6 – 7 – 0 – 1 – 2 – 3 – 4
6 – 7 – 0 – 1 – 2 – 3 – 4 – 5
7 – 0 – 1 – 2 – 3 – 4 – 5 – 6
0 – 1 – 2 – 3 – 4 – 5 – 6 – 7
1 – 0 – 3 – 2 – 5 – 4 – 7 – 6
2 – 3 – 0 – 1 – 6 – 7 – 4 – 5
3 – 2 – 1 – 0 – 7 – 6 – 5 – 4
4 – 5 – 6 – 7 – 0 – 1 – 2 – 3
5 – 4 – 7 – 6 – 1 – 0 – 3 – 2
6 – 7 – 4 – 5 – 2 – 3 – 0 – 1
7 – 6 – 5 – 4 – 3 – 2 – 1 – 0
8
FULL COLUMN BURST AND BURST STOP COMMAND (BST)
The full column burst is an option of burst length and available only at sequential mode of burst type. This full column
burst mode is repeatedly access to the same column. If burst mode reaches end of column address, then it wraps
round to first column address (= 0) and continues to count until interrupted by the news read (READ) /write (WRIT),
precharge (PRE), or burst stop (BST) command. The selection of Auto-precharge option is illegal during the full
column burst operation except write command at BURST READ & SINGLE WRITE mode.
The BST command is applicable to terminate the burst operation. If the BST command is asserted during the burst
mode, its operation is terminated immediately and the internal state moves to Bank Active.
When read mode is interrupted by BST command, the output will be in High-Z.
For the detail rule, please refer to “TIMING DIAGRAM - 8” in section “■ TIMING DIAGRAMS“.
When write mode is interrupted by BST command, the data to be applied at the same time with BST command will
be ignored.
BURST READ & SINGLE WRITE
The burst read and single write mode provides single word write operation regardless of its burst length. In this
mode, burst read operation does not be affected by this mode.
18
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
PRECHARGE AND PRECHARGE OPTION (PRE, PALL)
SDRAM memory core is the same as conventional DRAMs’, requiring precharge and refresh operations. Precharge
rewrites the bit line and to reset the internal Row address line and is executed by the Precharge command (PRE).
With the Precharge command, SDRAM will automatically be in standby state after precharge time (tRP).
The precharged bank is selected by combination of AP and BA0, BA1 when Precharge command is asserted. If AP
= High, all banks are precharged regardless of BA0, BA1 (PALL). If AP = Low, a bank to be selected by BA0, BA1 is
precharged (PRE).
The auto-precharge enters precharge mode at the end of burst mode of read or write without Precharge command
assertion.
This auto precharge is entered by AP = High when a read or write command is asserted. Refer to “■FUNCTIONAL
TRUTH TABLE”.
AUTO-REFRESH (REF)
Auto-refresh uses the internal refresh address counter. The SDRAM Auto-refresh command (REF) generates
Precharge command internally. All banks of SDRAM should be precharged prior to the Auto-refresh command.
The Auto-refresh command should also be asserted every 16 µs or a total 4096 refresh commands within a 64 ms
period.
SELF-REFRESH ENTRY (SELF)
Self-refresh function provides automatic refresh by an internal timer as well as Auto-refresh and will continue the
refresh function until cancelled by SELFX.
The Self-refresh is entered by applying an Auto-refresh command in conjunction with CKE = Low (SELF). Once
SDRAM enters the self-refresh mode, all inputs except for CKE will be “don’t care” (either logic high or low level
state) and outputs will be in a High-Z state. During a self-refresh mode, CKE = Low should be maintained. SELF
command should only be issued after last read data has been appeared on DQ
Notes: When the burst refresh method is used, a total of 4096 auto-refresh commands within 4 ms must be
asserted prior to the self-refresh mode entry.
SELF-REFRESH EXIT (SELFX)
To exit self-refresh mode, apply minimum tCKSP after CKE brought high, and then the No Operation command (NOP)
or the Deselect command (DESL) should be asserted within one tRC period. CKE should be held High within one
tRC period after tCKSP. Refer to “TIMING DIAGRAM -16” in section “■ TIMING DIAGRAMS” for the detail.
It is recommended to assert an Auto-refresh command just after the tRC period to avoid the violation of refresh period.
Notes: When the burst refresh method is used, a total of 4096 auto-refresh commands within 4 ms must be
asserted after the self-refresh exit.
MODE REGISTER SET (MRS)
The mode register of SDRAM provides a variety of different operations. The register consists of four operation
fields; Burst Length, Burst Type, CAS latency, and Operation Code. Refer to “■ MODE REGISTER TABLE”.
The mode register can be programmed by the Mode Register Set command (MRS). Each field is set by the address
line. Once a mode register is programmed, the contents of the register will be held until re-programmed by another
MRS command (or part loses power). MRS command should only be issued on condition that all DQ is in Hi-Z.
The condition of the mode register is undefined after the power-up stage. It is required to set each field after
initialization of SDRAM. Refer to “POWER-UP INITIALIZATION” below.
19
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
POWER-UP INITIALIZATION
The SDRAM internal condition after power-up will be undefined. It is required to follow the following Power On
Sequence to execute read or write operation.
1. Apply power and start clock. Attempt to maintain either NOP or DESL command at the input.
2. Maintain stable power, stable clock, and NOP condition for a minimum of 100 µs.
3. Precharge all banks by Precharge (PRE) or Precharge All command (PALL).
4. Assert minimum of 2 Auto-refresh command (REF).
5. Program the mode register by Mode Register Set command (MRS).
In addition, it is recommended DQM and CKE to track VCC to insure that output is High-Z state. The Mode Register
Set command (MRS) can be set before 2 Auto-refresh command (REF).
20
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
Fig. 2 – BASIC TIMING FOR CONVENTIONAL DRAM VS SYNCHRONOUS DRAM
<SDRAM>
Active
Read/Write
Precharge
CLK
CKE
H
H
H
tSI
tHI
CS
RAS
CAS
WE
H : Read
L : Write
Address
BA
CA
BA
AP (A10)
BA
RA
CASLatency=2
DQ0
to
DQ31
Burst Length = 4
<Conventional DRAM>
Row Address Select
Column Address Select
Precharge
RAS
CAS
DQ0
to
DQ31
21
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
Fig. 3 – STATE DIAGRAM (Simplified for Single BANK Operation State Diagram)
MRS
SELF
MODE
REGISTER
SET
SELF
REFRESH
SELFX
IDLE
REF
CKE\(PD)
CKE
AUTO
REFRESH
POWER
DOWN
CKE\(CSUS)
CKE
BANK
ACTIVE
SUSPEND
BANK
ACTIVE
BST
BST
READ
WRIT
READ
CKE\(CSUS)
WRIT
WRITA
READA
CKE\(CSUS)
CKE
WRITE
SUSPEND
READ
SUSPEND
READ
WRIT
WRITE
READ
CKE
WRITA
READA
READA
WRITA
CKE\(CSUS)
CKE
CKE\(CSUS)
CKE
WRITE WITH
AUTO
PRECHARGE
READ WITH
AUTO
PRECHARGE
WRITE
SUSPEND
READ
SUSPEND
PRE or
PALL
PRE or
PALL
PRE or PALL
POWER
ON
PRECHARGE
DEFINITION OF ALLOWS
POWER
APPLIED
Manual
Input
Automatic
Sequence
Note: CKE\ means CKE goes Low-level from High-level.
22
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
■ BANK OPERATION COMMAND TABLE
MINIMUM CLOCK LATENCY OR DELAY TIME FOR 1 BANK OPERATION
Second
command
(same
*4
*4
bank)
First
command
MRS
tRSC
tRSC
tRSC
tRSC
tRSC
tRSC
tRSC
ACTV
READ
tRCD
tRCD
tRCD
tRCD
tRAS
tRAS
1
*5
*5
*4
*4
1
1
1
1
1
1
1
*1,*2
*2,*7
BL
+
BL
+
BL *4
+
BL *4
+
BL *2
+
BL
+
READA
WRIT
tRP
tRP
tRP
tRP
tRP
tRP
*4
*4
tWR
tWR
1
1
tDPL
tDPL
1
*2
*4
*4
*2
*2
BL-1
+
tDAL
BL-1
+
tDAL
BL-1
+
tDAL
BL-1
+
tDAL
BL-1
+
tDAL
BL-1
+
tDAL
WRITA
*2,*3
*4
*2
*2,*6
PRE
PALL
REF
tRP
tRP
tRC
tRC
tRP
tRP
tRC
tRC
1
1
1
tRP
tRP
tRP
tRC
tRC
1
*3
*6
1
tRP
tRC
tRC
1
tRC
tRC
tRC
SELFX
tRC
tRC
tRC
Notes: *1. If tRP(min.)<CL×tCK, minimum latency is a sum of (BL+CL)×tCK.
*2. Assume all banks are in Idle state.
*3. Assume output is in High-Z state.
*4. Assume tRAS(min.) is satisfied.
*5. Assume no I/O conflict.
*6. Assume after the last data have been appeared on DQ.
*7. If tRP(min.)<(CL-1)×tCK, minimum latency is a sum of (BL+CL-1)×tCK.
Illegal Command
23
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
■ MULTI BANK OPERATION COMMAND TABLE
MINIMUM CLOCK LATENCY OR DELAY TIME FOR MULTI BANK OPERATION
Second
command
(other
*5
*5,*6
*5
*5,*6
bank)
First
command
MRS
tRSC
tRSC
tRSC
tRSC
tRSC
tRSC
tRSC
*2
*7
*7
*7
*7
*6,*7
*7
ACTV
READ
tRRD
1
1
1
1
1
1
1
1
1
1
1
1
tRAS
1
*2,*4
*10
*10
*6
*6
*6
1
1
1
1
1
1
1
*1,*2
*2,*4
*6
*6
*6,*10
*6,*10
*6
*6
*2
*2,*9
BL+
tRP
1
1
1
BL+
tRP
BL+
tRP
BL+
tRP
READA
WRIT
*2,*4
*6
1
1
1
tDPL
1
*2
*2,*4
*6
*7
*6
*7
*6
*6
*6
*6
*2
*2
BL-1
+
BL-1
+
BL-1
+
BL-1
+
WRITA
1
1
1
1
1
1
1
1
tDAL
tDAL
tDAL
tDAL
*2,*3
*2,*4
*7
*7
*6,*7
*7
*2
*2,*8
PRE
PALL
REF
tRP
tRP
tRC
tRC
1
1
1
1
1
tRP
tRP
tRC
tRC
tRP
tRP
tRC
tRC
1
*3
*8
tRP
tRC
tRC
1
1
1
tRC
tRC
tRC
SELFX
tRC
tRC
tRC
Notes: *1. If tRP(min.)<CL×tCK, minimum latency is a sum of (BL+CL)×tCK.
*2. Assume bank of the object is in Idle sate.
*3. Assume output is in High-Z sate.
*4. tRRD(min.) of other bank (second command will be asserted) is satisfied.
*5. Assume other bank is in active, read or write state.
*6. Assume tRAS(min.) is satisfied.
*7. Assume other banks are not in READA/WRITA state.
*8. Assume after the last data have been appeared on DQ.
*9. If tRP(min.)<(CL-1)×tCK, minimum latency is a sum of (BL+CL-1)×tCK.
*10. Assume no I/O conflict.
Illegal Command
24
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
■ MODE REGISTER TABLE
MODE REGISTER SET
BA1 BA0
A10
0
A9
A8
0
A7
A6
A5
A4
A3
A2
A1
A0
ADDRESS
*3
*3
Op-
code
MODE
REGISTER
0
0
0
CL
BT
BL
A5
Burst Length
A6
A4
CAS Latency
A2
A1
A0
*2
BT = 0
BT = 1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
Reserved
2
2
4
3
4
Reserved
Reserved
Reserved
Reserved
8
8
Reserved
Reserved
Reserved
Full Column
Reserved
Reserved
Reserved
Reserved
A9
Op-code
A3
Burst Type
0
1
Burst Read & Burst Write
Burst Read & Single Write
0
1
Sequential (Wrap round, Binary-up)
Interleave (Wrap round, Binary-up)
*1
Notes: *1. When A9 = 1, burst length at Write is always one regardless of BL value.
*2. BL = 1 and Full Column are not applicable to the interleave mode.
*3. A7 = 1 and A8 = 1 are reserved for vender test.
25
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
■ ABSOLUTE MAXIMUM RATINGS (See WARNING)
Parameter
Voltage of VCC Supply Relative to VSS
Voltage at Any Pin Relative to VSS
Short Circuit Output Current
Power Dissipation
Symbol
VCC, VCCQ
VIN, VOUT
IOUT
Value
–0.5 to +4.6
–0.5 to +4.6
±50
Unit
V
V
mA
W
PD
1.3
Storage Temperature
TSTG
–55 to +125
°C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
(Referenced to VSS)
Parameter
Notes
Symbol
VCC, VCCQ
VSS, VSSQ
VIH
Min.
3.0
0
Typ.
3.3
0
Max.
3.6
Unit
V
Supply Voltage
0
V
Input High Voltage
Input Low Voltage
Ambient Temperature
*1
*2
2.0
–0.5
0
—
VCC + 0.5
0.8
V
VIL
—
V
TA
—
70
°C
Notes:
VIH
Pulse width ≤ 5 ns
4.6V
VIL(max.)
VIL
50% of pulse amplitude
VIH
VIH(min.)
50% of pulse amplitude
-1.5V
Pulse width ≤ 5 ns
VIL
*2. Undershoot limit: VIL (min.)
*1. Overshoot limit: VIH (max.)
= VSS -1.5V for pulse width <= 5 ns acceptable,
pulse width measured at 50% of pulse amplitude.
= 4.6V for pulse width <= 5 ns acceptable,
pulse width measured at 50% of pulse amplitude.
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All
the device’s electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside
these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.
■ CAPACITANCE
(TA = 25°C, f = 1 MHz)
Parameter
Symbol
CIN1
Min.
2.5
Typ.
—
Max.
Unit
pF
Input Capacitance, Except for CLK
Input Capacitance for CLK
I/O Capacitance
5.0
4.0
6.5
CIN2
2.5
—
pF
CI/O
4.0
—
pF
26
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
■ DC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.) Note *1, *2, and 3*
Value
Parameter
Output High Voltage
Symbol
Condition
Unit
Min.
2.4
—
Max.
—
VOH(DC) IOH = –2 mA
VOL(DC) IOL = 2 mA
0 V ≤ VIN ≤ VCC;
V
V
Output Low Voltage
0.4
Input Leakage Current (Any Input)
ILI
All other pins not under
test = 0 V
–5
–5
5
µA
µA
0 V ≤ VIN ≤ VCC;
Data out disabled
Output Leakage Current
ILO
5
MB81F643242C-60
165
Burst: Length = 1
tRC = min, tCK = min
One bank active
Output pin open
Addresses changed up to
1-time during tRC (min)
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
MB81F643242C-70
MB81F643242C-10
155
115
100
Operating Current
(Average Power
Supply Current)
ICC1
—
mA
Reference Value *4
@67MHz (CL=3)
CKE = VIL
All banks idle
tCK = min
ICC2P
—
—
2
1
mA
mA
Power down mode
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
CKE = VIL
All banks idle
CLK = VIH or VIL
Power down mode
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
ICC2PS
Precharge Standby Current
(Power Supply Current)
CKE = VIH
All banks idle, tCK = 15 ns
NOP commands only,
Input signals (except to
CMD) are changed 1 time
during 30 ns
ICC2N
—
—
12
mA
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
CKE = VIH
All banks idle
CLK = VIH or VIL
Input signal are stable
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
ICC2NS
2
mA
(Continued)
27
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
(Continued)
Value
Parameter
Symbol
Condition
CKE = VIL
Unit
Min.
Max.
Any bank active
tCK = min
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
ICC3P
—
—
2
mA
CKE = VIL
Any bank active
CLK = VIH or VIL
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
ICC3PS
1
mA
mA
CKE = VIH
Any bank active
tCK = 15 ns
NOP commands only,
Input signals (except to
CMD) are changed 1 time
during 30 ns
Active Standby Current (Power Supply Current)
ICC3N
—
25
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
CKE = VIH
Any bank idle
CLK = VIH or VIL
Input signals are stable
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
ICC3NS
—
—
2
mA
mA
tCK = min
MB81F643242C-60
305
260
185
Burst Length = 4
Output pin open
All banks active
Gapless data
MB81F643242C-70
MB81F643242C-10
Burst mode Current
(Average Power
Supply Current)
ICC4
Reference Value *4
@67MHz (CL=3)
0 V ≤ VIN ≤ VIL max
VIH max ≤ VIN ≤ VCC
125
MB81F643242C-60
MB81F643242C-70
MB81F643242C-10
235
220
155
Auto-refresh;
tCK = min
tRC = min
0 V ≤ VIN ≤ VIL max
VIH max ≤ VIN ≤ VCC
Refresh Current #1
(Average Power
Supply Current)
ICC5
—
—
mA
mA
Reference Value *4
@67MHz (CL=3)
125
Self-refresh;
tCK = min
CKE ≤ 0.2 V
0 V ≤ VIN ≤ VIL max
VIH max ≤ VIN ≤ VCC
Refresh Current #2
ICC6
2
(Average Power Supply Current)
Notes: *1. All voltage are referenced to VSS.
*2. DC characteristics are measured after following the POWER-UP INITIALIZATION procedure in section
“■ FUNCTIONAL DESCRIPTION“.
*3. ICC depends on the output termination or load conditions, clock cycle rate, signal clocking rate. The
specified values are obtained with the output open and no termination register.
*4. This value is for reference only.
28
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
■ AC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.) Note *1, 2, and *3
MB81F643242C MB81F643242C MB81F643242C Reference Value *4
-60
-70
-10
@67MHz, CL=3
Parameter
Notes
Symbol
Unit
Min. Max. Min. Max. Min. Max.
Min.
20
15
4
Max.
CL = 2
CL = 3
*5
tCK2
tCK3
tCH
tCL
10
6
10
7
15
10
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Period
—
—
—
—
Clock High Time
Clock Low Time
2.5
2.5
1.5
1
—
—
—
—
6
2.5
2.5
2
—
—
—
—
6
—
—
—
—
7
—
—
—
—
7
*5
3
4
Input Setup Time
Input Hold Time
*5
tSI
2
3
*5
tHI
1
1
1
Access Time
from Clock
(tCK = min)
*5,*6, CL = 2
tAC2
tAC3
tLZ
*7
—
1
—
1
—
1
—
1
CL = 3
5.5
—
6
5.5
—
6
7
7
Output in Low-Z
*5
—
7
—
7
CL = 2
*5,*8
tHZ2
tHZ3
Output in
High-Z
2.5
2.5
3
3
CL = 3
5.5
5.5
7
7
CL = 2
*5,*7
Output Hold
Time
tOH
2.5
—
—
2.5
—
—
3
—
3
—
CL = 3
Time between Auto-Refresh
command interval
tREFI
15.6
15.6
—
15.6
—
15.6
µs
*4
*5
Time between Refresh
Transition Time
tREF
tT
—
64
10
—
64
10
—
64
10
—
64
10
ms
ns
0.5
0.5
0.5
0.5
CKE Setup Time for Power
Down Exit Time
tCKSP
1.5
—
2
—
3
—
3
—
ns
29
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
BASE VALUES FOR CLOCK COUNT/LATENCY
MB81F643242C MB81F643242C MB81F643242C Reference Value *4
-60 -70 -10
@67MHz, CL=3
Parameter Notes
Symbol
Unit
Min. Max. Min. Max. Min. Max.
Min.
Max.
RAS Cycle
*9
t
RC
60
—
63
—
90
—
110
—
ns
Time
RAS Precharge Time
RAS Active Time
tRP
tRAS
tRCD
tWR
18
42
18
6
—
110K
—
20
42
20
7
—
110K
—
30
60
30
10
—
110K
—
40
70
30
15
—
110K
—
ns
ns
ns
ns
RAS to CAS Delay Time
Write Recovery Time
—
—
—
—
RAS to RAS Bank Active
Delay Time
tRRD
tDPL
12
7
—
—
—
—
—
14
7
—
—
—
—
—
20
10
—
—
—
—
—
30
15
—
—
—
—
—
ns
ns
ns
ns
ns
Data-in to Precharge Lead
Time
1 cyc
+ tRP
1cyc
+ tRP
1cyc
+ tRP
1 cyc
+ tRP
CL=2
tDAL2
tDAL3
tRSC
Data-in to Active/
Refresh Command
2 cyc
+ tRP
2cyc
+ tRP
2cyc
+ tRP
2 cyc
+ tRP
Period
CL=3
Mode Resister Set Cycle
Time
12
14
20
30
CLOCK COUNT FORMULA Note *10
Base Value
Clock ≥
(Round off a whole number)
Clock Period
30
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
LATENCY - FIXED VALUES
(The latency values on these parameters are fixed regardless of clock period.)
MB81F643242C
-60
MB81F643242C MB81F643242C
Parameter
Symbol
Unit
-70
-10
CKE to Clock Disable
lCKE
lDQZ
1
2
0
2
0
2
3
2
3
1
1
1
1
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
DQM to Output in High-Z
2
2
DQM to Input Data Delay
lDQD
lOWD
lDWD
lROH2
lROH3
lBSH2
lBSH3
lCCD
0
0
Last Output to Write Command Delay
Write Command to Input Data Delay
2
2
0
0
CL = 2
CL = 3
CL = 2
CL = 3
2
2
Precharge to Outputing
High-Z Delay
3
3
2
2
Burst Stop Command to Output
in High-Z Delay
3
3
CAS to CAS Delay (min)
CAS Bank Delay (min)
1
1
lCBD
1
1
Notes: *1. AC characteristics are measured after following the POWER-UP INITIALIZATION procedure in section
“■ FUNCTIONAL DESCRIPTION“.
*2. AC characteristics assume tT = 1 ns and 30 pF of capacitive load.
*3. 1.4 V is the reference level for measuring timing of input signals. Transition times are measured
between VIH (min) and VIL (max). (See Fig. 5)
*4. This value is for reference only.
*5. If input signal transition time (tT) is longer than 1 ns; [(tT/2) –0.5] ns should be added to tAC (max), tHZ
(max), and tCKSP (min) spec values, [(tT/2) –0.5] ns should be subtracted from tLZ (min), tHZ (min), and
tOH (min) spec values, and (tT –1.0) ns should be added to tCH (min), tCL (min), tSI (min), and tHI (min)
spec values.
*6. tAC also specifies the access time at burst mode.
*7. tAC and tOH are the specs value under OUTPUT LOAD CIRCUIT shown in Fig. 4.
*8. Specified where output buffer is no longer driven.
*9. Actual clock count of tRC (lRC) will be sum of clock count of tRAS (lRAS) and tRP (lRP).
*10. All base values are measured from the clock edge at the command input to the clock edge for the next
command input. All clock counts are calculated by a simple formula: clock count equals base value
divided by clock period (round off to a whole number).
31
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
Fig. 4 – OUTPUT LOAD CIRCUIT
R1 = 50 Ω
Output
1.4 V
CL = 30 pF
LVTTL
Note: By adding appropriate correlation factors to the test conditions, t
AC and tOH measured when the Output is coupled to
the Output Load Circuit are within specifications.
32
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
Fig. 5 – TIMING DIAGRAM, SETUP, HOLD AND DELAY TIME
tCK
tCH
tCL
2.4 V
1.4 V
CLK
0.4 V
tSI
tHI
2.4 V
0.4 V
Input
(Control,
Addr. & Data)
1.4 V
tAC
tHZ
tOH
tLZ
2.4 V
0.4 V
Output
1.4 V
Note: Reference level of input signal is 1.4 V for LVTTL.
Access time is measured at 1.4 V for LVTTL.
Fig. 6 – TIMING DIAGRAM, DELAY TIME FOR POWER DOWN EXIT
Don’t Care
CLK
CKE
1 clock (min)
tCKSP (min)
Don’t Care
NOP
NOP
ACTV
Command
33
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
Fig. 7 – TIMING DIAGRAM, PULSE WIDTH
CLK
tRC, tRP, tRAS, tRCD, tWR, tREF,
tDPL, tDAL, tRSC, tRRD, tCKSP
Input
(Control)
COMMAND
COMMAND
Note: These parameters are a limit value of the rising edge of the clock from one command input to next input. tCKSP is the
latency value from the rising edge of CKE.
Measurement reference voltage is 1.4 V.
Fig. 8 – TIMING DIAGRAM, ACCESS TIME
CLK
READ
Command
tAC
tAC
tAC
(CAS Latency – 1) × tCK
DQ0 to DQ31
(Output)
Q(Valid)
Q(Valid)
Q(Valid)
34
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
■ TIMING DIAGRAMS
TIMING DIAGRAM – 1 : CLOCK ENABLE - READ AND WRITE SUSPEND (@ BL = 4)
CLK
CKE
*1
*1
ICKE (1 clock)
ICKE (1 clock)
*2
*2
CLK
(Internal)
*2
(NO CHANGE)
*2
(NO CHANGE)
DQ0 to DQ31
(Read)
Q1
D1
Q2
Q3
Q4
D4
*3
*3
WRITTEN
DQ0 to DQ31
(Write)
NOT
WRITTEN
NOT
D2
D3
Notes: *1. The latency of CKE (lCKE) is one clock.
*2. During read mode, burst counter will not be incremented/decremented at the next clock of CSUS command. Output
data remain the same data.
*3. During the write mode, data at the next clock of CSUS command is ignored.
TIMING DIAGRAM – 2 : CLOCK ENABLE - POWER DOWN ENTRY AND EXIT
CLK
tCKSP
(min)
1 clock
(min)
CKE
*1
*2
*3
*3
*4
Command
NOP
PD(NOP)
DON’T CARE
tREF (max)
NOP
NOP
ACTV
Notes: *1. Precharge command (PRE or PALL) should be asserted if any bank is active and in the burst mode.
*2. Precharge command can be posted in conjunction with CKE after the last read data have been appeared on DQ.
*3. It is recommended to apply NOP command in conjunction with CKE.
*4. The ACTV command can be latched after tCKSP (min) + 1 clock (min).
35
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
TIMING DIAGRAM – 3 : COLUMN ADDRESS TO COLUMN ADDRESS INPUT DELAY
CLK
RAS
ICCD
(1 clock)
ICCD
ICCD
ICCD
tRCD (min)
CAS
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
ROW
ADDRESS
Address
Note: CAS to CAS delay can be one or more clock period.
TIMING DIAGRAM – 4 : DIFFERENT BANK ADDRESS INPUT DELAY
CLK
tRRD (min)
RAS
CAS
ICBD
(1 clock)
tRCD (min) or more
ICBD
tRCD (min)
ROW
ADDRESS
ROW
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
Address
BA0, BA1
Bank 0
Bank 3
Bank 0
Bank 3
Bank 0
Bank 3
Note: CAS Bank delay can be one or more clock period.
36
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
TIMING DIAGRAM – 5 : DQM0 - DQM3 - INPUT MASK AND OUTPUT DISABLE (@ BL = 4)
CLK
DQM0 to DQM3
(@ Read)
IDQZ (2 clocks)
DQ0 to DQ31
(@ Read)
Q1
Q2
Hi-Z
Q4
End of burst
DQM0 to DQM3
(@ Write)
IDQD (same clock)
DQ0 to DQ31
(@ Write)
D1
MASKED
D3
D4
End of burst
TIMING DIAGRAM – 6 : PRECHARGE TIMING (APPLIED TO THE SAME BANK)
CLK
tRAS (min)
Command
PRE
ACTV
Note: PRECHARGE means ’ PRE’ or ’PALL’.
37
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
TIMING DIAGRAM – 7 : READ INTERRUPTED BY PRECHARGE (EXAMPLE @ CL = 2, BL = 4)
CLK
Command
DQ0 to DQ31
Command
DQ0 to DQ31
Command
DQ0 to DQ31
Command
DQ0 to DQ31
PRECHARGE
IROH (2 clocks)
Q1
Hi-Z
PRECHARGE
IROH (2 clocks)
Hi-Z
Q1
Q2
PRECHARGE
IROH (2 clocks)
Hi-Z
Q1
Q2
Q3
PRECHARGE
No effect (end of burst)
Q3 Q4
Q1
Q2
Note: In case of CL = 2, the lROH is 2 clocks.
In case of CL = 3, the lROH is 3 clocks.
PRECHARGE means ’ PRE’ or ’PALL’.
38
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
TIMING DIAGRAM – 8 : READ INTERRUPTED BY BURST STOP (EXAMPLE @ BL = Full Column)
CLK
Command
(CL = 2)
BST
lBSH (2 clocks)
Hi-Z
Qn–2
Qn–1
Qn
Qn+1
DQ0 to DQ31
BST
Command
(CL = 3)
lBSH (3 clocks)
Hi-Z
DQ0 to DQ31
Qn-2
Qn-1
Qn
Qn+1
Qn+2
TIMING DIAGRAM – 9 : WRITE INTERRUPTED BY BURST STOP (EXAMPLE @ BL = 2)
CLK
Command
BST
COMMAND
LAST
DATA-IN
Masked
by BST
DQ0 to DQ31
39
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
TIMING DIAGRAM – 10 : WRITE INTERRUPTED BY PRECHARGE (EXAMPLE @ CL = 3)
CLK
ACTV
PRECHARGE
tDPL (min)
Command
tRP (min)
DQ0 to DQ31
LAST
DATA-IN
MASKED
by Precharge
DATA-
Note: The precharge command (PRE) should only be issued after the tDPL of final data input is satisfied.
PRECHARGE means ’ PRE’ or ’PALL’.
TIMING DIAGRAM – 11 : READ INTERRUPTED BY WRITE (EXAMPLE @ CL = 3, BL = 4)
CLK
IOWD (2 clocks)
READ
WRIT
Command
*1
*2
*3
DQM
(DQM0 to DQM3)
IDQZ (2 clocks)
IDWD (same clock)
DQ0 to DQ31
Q1
D1
D2
Masked
Notes: *1. First DQM makes high-impedance state High-Z between last output and first input data.
*2. Second DQM makes internal output data mask to avoid bus contention.
*3. Third DQM in illustrated above also makes internal output data mask. If burst read ends (final data output) at or after the
second clock of burst write, this third DQM is required to avoid internal bus contention.
40
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
TIMING DIAGRAM – 12 : WRITE TO READ TIMING (EXAMPLE @ CL = 3, BL = 4)
tWR (min)
CLK
Command
WRIT
READ
DQM
(DQM0 to DQM3)
(CL-1) × tCK
tAC (max)
D3
DQ0 to DQ31
D1
D2
Q1
Q2
Masked
by READ
Note: Read command should be issued after tWR of final data input is satisfied.
41
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
TIMING DIAGRAM – 13 : READ WITH AUTO-PRECHARGE
(EXAMPLE @ CL = 2, BL = 2 Applied to same bank)
CLK
tRAS (min)
READA
tRP (min)
ACTV
NOP or DESL
ACTV
Command
DQM
*1
2 clocks
(same value as BL)
*2
BL+tRP (min)
(DQM0 to DQM3)
DQ0 to DQ31
Q1
Q2
Notes: *1. Precharge at read with Auto-precharge command (READA) is started from number of clocks that is the same as
Burst Length (BL) after the READA command is asserted.
*2. Next ACTV command should be issued after BL+tRP (min) from READA command.
TIMING DIAGRAM – 14 : WRITE WITH AUTO-PRECHARGE *1, *2, and *3
(EXAMPLE @ CL = 2, BL = 2 Applied to same bank)
tRAS (min)
CLK
*4
CL- 1
tDAL (min)
BL+tRP (min) *5
Command
ACTV
WRITA
NOP or DESL
ACTV
DQM
(DQM0 to DQM3)
DQ0 to DQ31
D1
D2
Notes: *1. Even if the final data is masked by DQM, the precharge does not start the clock of final data input.
*2. Once auto precharge command is asserted, no new command within the same bank can be issued.
*3. Auto-precharge command doesn’t affect at full column burst operation except Burst READ & Single Write.
*4. Precharge at write with Auto-precharge is started after the CL - 1 from the end of burst.
*5. Next command should be issued after BL+ tRP (min) at CL = 2, BL+1+tRP (min) at CL = 3 from WRITA command.
42
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
TIMING DIAGRAM – 15 : AUTO-REFRESH TIMING
CLK
*3
*4
*1
*3
*3
*3
Command
REF
NOP
NOP
NOP
REF
NOP
Command
tRC (min)
tRC (min)
*2
DON’T CARE
*2
DON’T CARE
BA
BA0, BA1
Notes: *1. All banks should be precharged prior to the first Auto-refresh command (REF).
*2. Bank select is ignored at REF command. The refresh address and bank select are selected by internal refresh counter.
*3. Either NOP or DESL command should be asserted during tRC period while Auto-refresh mode.
*4. Any activation command such as ACTV or MRS command other than REF command should be asserted after tRC from the
last REF command.
TIMING DIAGRAM – 16 : SELF-REFRESH ENTRY AND EXIT TIMING
CLK
tCKSP (min)
tSI (min)
CKE
*4
tRC (min)
*2
*3
*1
SELF
DON’T CARE
SELFX
Command
NOP
NOP
NOP
Command
Notes: *1. Precharge command (PRE or PALL) should be asserted if any bank is active prior to Self-refresh Entry command (SELF).
*2. The Self-refresh Exit command (SELFX) is latched after tCKSP (min). It is recommended to apply NOP command in
conjunction with CKE.
*3. Either NOP or DESL command can be used during tRC period.
*4. CKE should be held high within one tRC period after tCKSP.
43
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
TIMING DIAGRAM – 17 : MODE REGISTER SET TIMING
CLK
tRSC (min)
MRS
NOP or DESL
ACTV
Command
Address
ROW
ADDRESS
MODE
Notes: The Mode Register Set command (MRS) should only be asserted after all banks have been precharged.
44
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
■ SCITT TEST MODE
ABOUT SCITT
SCITT (Static Component Interconnection Test Technology) is an XNOR circuit based test technology that is used
for testing interconnection between SDRAM and SDRAM controller on the printed circuit boards. SCITT provides
inexpensive board level test mode in combination with boundary-scan. The basic idea is simple, consider all output
of SDRAM as output of XNOR circuit and each output pin has a unique mapping on the input of SDRAM. The ideal
schematic block diagram is as shown below.
TEST
Control
µC
SDRAM
CORE
xAddress
Boundary
Scan
Bus
XNOR
ASIC
Data Bus
TEST Control : CAS, CS, CKE
xAddress Bus : A0 to A10, BA0, BA1, RAS, DQM0 to DQM3, CLK, WE
Data Bus : DQ0 to DQ31
It is static and provides easy test pattern that result in a high diagnostic resolution for detecting all open/short faults.
The MB81F643242C adopts SCITT as an optional function. See Package and “Ordering Information” in section “■
PACKAGE“.
45
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
SCITT TEST SEQUENCE
The followings are the SCITT test sequence. SCITT Test can be executed after power-on and prior to Precharge
command in POWER-UP INITIALIZATION. Once Precharge command is issued to SDRAM, it never get back to
SCITT Test Mode during regular operation for the purpose of a fail-safe way in get in and out of test mode.
1. Apply power. Attempt to maintain either NOP or DESL command at the input.
2. Maintain stable power for a minimum of 100us.
3. Enter SCITT test mode.
4. Execute SCITT test.
5. Exit from SCITT mode.
It is required to follow Power On Sequence to execute read or write operation.
6. Start clock. Attempt to maintain either NOP or DESL command at the input.
7. Precharge all banks by Precharge (PRE) or Precharge All command (PALL).
8. Assert minimum of 2 Auto-Refresh command (REF).
9. Program the mode register by Mode Register Set command (MRS).
The 3,4,5 steps define the SCITT mode available. It is possible to skip these steps if necessary (Refer to POWER-
UP INITIALIZATION).
COMMAND TRUTH TABLE Note *1
Control
CS
Input
Output
DQM0
to
DQM3
DQ0
to
DQ31
A0 to A10
BA0, BA1
CAS
CKE
WE
RAS
CLK
H→L *2
L→H *3
SCITT mode entry
SCITT mode exit
L
L
X
X
X
X
X
X
X
X
X
X
X
X
H *5
L *5
SCITT mode
L
L
H
V
V
V
V
V
V
output enable *4
Notes: *1. L = Logic Low, H = Logic High, V = Valid, X = either L or H
*2. The SCITT mode entry command assumes the first CAS falling edge with CS and CKE = L after power
on.
*3. The SCITT mode exit command assumes the first CAS rising edge after the test mode entry.
*4. Refer the test code table.
*5. CS = H or CKE = L is necessary to disable outputs in SCITT mode exit.
46
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
TEST CODE TABLE
DQ0 to DQ31 output data is static and is determined by following logic during the SCITT mode operation.
DQ0 = RAS xnor A0
DQ1 = RAS xnor A1
DQ2 = RAS xnor A2
DQ3 = RAS xnor A3
DQ4 = RAS xnor A4
DQ5 = RAS xnor A5
DQ6 = RAS xnor A6
DQ7 = RAS xnor A7
DQ8 = RAS xnor A8
DQ9 = RAS xnor A9
DQ10 = RAS xnor A10
DQ11 = RAS xnor BA1
DQ12 = RAS xnor BA0
DQ13 = RAS xnor DQM0
DQ14 = RAS xnor DQM1
DQ15 = RAS xnor DQM2
DQ16 = RAS xnor DQM3
DQ17 = RAS xnor CLK
DQ18 = RAS xnor WE
DQ19 = A0 xnor A1
DQ22 = A0 xnor A4
DQ23 = A0 xnor A5
DQ24 = A0 xnor A6
DQ25 = A0 xnor A7
DQ26 = A0 xnor A8
DQ27 = A0 xnor A9
DQ28 = A0 xnor A10
DQ29 = A0 xnor BA1
DQ30 = A0 xnor BA0
DQ31 = A0 xnor DQM0
DQ20 = A0 xnor A2
DQ21 = A0 xnor A3
• EXAMPLE OF TEST CODE TABLE
Input bus
Output bus
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L L L L L L L L L L L L L L L L L L L H H H H H H H H H H H H H
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L H H H H H H H H H H H H H H H H H H L L L L L L L L L L L L L
0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 H L H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 H H L H H H H H H H H H H H H H H H H H L H H H H H H H H H H H
0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 H H H L H H H H H H H H H H H H H H H H H L H H H H H H H H H H
0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 H H H H L H H H H H H H H H H H H H H H H H L H H H H H H H H H
0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 H H H H H L H H H H H H H H H H H H H H H H H L H H H H H H H H
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 H H H H H H L H H H H H H H H H H H H H H H H H L H H H H H H H
0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 H H H H H H H L H H H H H H H H H H H H H H H H H L H H H H H H
0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 H H H H H H H H L H H H H H H H H H H H H H H H H H L H H H H H
0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 H H H H H H H H H L H H H H H H H H H H H H H H H H H L H H H H
0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 H H H H H H H H H H L H H H H H H H H H H H H H H H H H L H H H
0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 H H H H H H H H H H H L H H H H H H H H H H H H H H H H H L H H
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H L H
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H L
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 H H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 L L L L L L L L L L L L L L L L L L L H H H H H H H H H H H H H
1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 L H H H H H H H H H H H H H H H H H H L L L L L L L L L L L L L
1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 H L H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H
1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 H H L H H H H H H H H H H H H H H H H H L H H H H H H H H H H H
1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 H H H L H H H H H H H H H H H H H H H H H L H H H H H H H H H H
1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 H H H H L H H H H H H H H H H H H H H H H H L H H H H H H H H H
1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 H H H H H L H H H H H H H H H H H H H H H H H L H H H H H H H H
1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 H H H H H H L H H H H H H H H H H H H H H H H H L H H H H H H H
1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 H H H H H H H L H H H H H H H H H H H H H H H H H L H H H H H H
1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 H H H H H H H H L H H H H H H H H H H H H H H H H H L H H H H H
1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 H H H H H H H H H L H H H H H H H H H H H H H H H H H L H H H H
1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 H H H H H H H H H H L H H H H H H H H H H H H H H H H H L H H H
1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 H H H H H H H H H H H L H H H H H H H H H H H H H H H H H L H H
1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H L H
1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H L
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 H H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H
0 = input Low, 1 = input High, L = output Low, H = output High
47
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
AC SPECIFICATION
Parameter
Description
Test mode entry set up time
Minimum
Maximum
Units
ns
tTS
tTH
10
10
10
0
—
—
—
—
20
Test mode entry hold time
ns
tEPD
tTLZ
tTHZ
Test mode exit to power on sequence delay time
Test mode output in Low-Z time
Test mode output in High-Z time
ns
ns
0
ns
Test mode access time from control signals
(output enable & chip select)
tTCA
—
40
ns
tTIA
tTOH
tETD
tTIH
Test mode Input access time
Test mode Output Hold time
Test mode entry to test delay time
Test mode input hold time
—
0
20
—
—
—
ns
ns
ns
ns
10
30
TIMING DIAGRAMS
TIMING DIAGRAM – 1 : POWER-UP TIMING DIAGRAM
*2
VDD
100µs Pause Time
Test Mode Entry Point
CS
CKE
*3
CAS
*1
Notes: *1. SCITT is enabled if CS = L, CKE = L, CAS = L at just power on.
*2. All output buffers maintains in High-Z state regardless of the state of control signals as long as
the above timing is maintained.
*3. CAS must not be brought from High to Low.
48
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
TIMING DIAGRAM – 2 : SCITT TEST ENTRY AND EXIT *1
Next power on sequence
and normal operation
VCC
Pause 100µs
tTS
tTH
Test Mode
tEPD
H → L
CAS
CS
L
L
CKE
*3
*2
Exit
Entry
Notes: *1. If entry and exit operation have not been done correctly, CAS, CS, CKE pins will have some problems.
*2. PRE or PALL commands must not be asserted. Test mode is disable by those commands.
*3. Outputs must be disabled by CS = H or CKE = L before Exit.
49
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
TIMING DIAGRAM – 3 : OUTPUT CONTROL (1)
VDD
Entry
CAS must not brought from High to Low
CAS
DQ turn to Low-Z at CS=L and CKE=H
DQ turn to High-Z at CS=H
CS
CKE
High-Z
High-Z
DQ0 to DQ31
tTLZ
tTHZ
Memory device
Low-Z
High-Z
output buffer status
Time (a)
Time (b)
Time (c)
This is not bus line level
TIMING DIAGRAM – 4 : OUTPUT CONTROL (2)
VDD
Entry
CAS must not brought from High to Low
CAS
CS
DQ turn to Low-Z at CS=L and CKE=H
DQ turn to High-Z at CKE=L
CKE
High-Z
High-Z
DQ0 to DQ31
tTLZ
tTHZ
Memory device
Low-Z
High-Z
output buffer status
Time (a)
Time (b)
Time (c)
This is not bus line level
50
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
TIMING DIAGRAM – 5 : TEST TIMING (1)
Test mode
Entry Command
Test mode
Entry
tETD
Under test
CAS
CS
CKE
DQ becomes Low-Z at CS=L and CKE=H
A0
A1
A2
tTCA
Under
Check
Pins
tTIA
tTIA
tTIA
tTOH
Valid
tTOH
Valid
Valid
DQ0 to DQ31
tTLZ
51
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
TIMING DIAGRAM – 6 : TEST TIMING (2)
Test mode
Entry
Test mode
Exit
Under test
CAS
L
CS-#1
L
Changed under test devices
Tested #2 device
H
CS-#2
CKE
Tested #1 device
tTIH
tTIH
tTIH
tTCA
A0
A1
A2
tTLZ
tTHZ
Under
Check
Pins
tTIA
tTIA
tTIA
tTIA
tTIA
tTOH
Valid
tTOH
Valid
tTOH
Valid
Valid
Valid
DQ0 to DQ31
52
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
TIMING DIAGRAM – 7 : TEST TIMING (3)
Test mode
Entry
Test mode
Exit
Under test
CAS
L
CS-#1
L
Changed under test devices
Tested #2 device
H
CS-#2
CKE
Tested #1 device
tTIH
tTHZ
tTIH
tTIH
A0
A1
A2
tTCA
Under
Check
Pins
tTLZ
tTIA
tTIA
tTIA
tTIA
tTIA
tTOH
Valid
tTOH
Valid
tTOH
Valid
Valid
Valid
DQ0 to DQ31
53
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
■ PACKAGE DIMENSION
86-pin plastic TSOP(II)
*: Resin protrusion. (Each side: 0.15 (.006) MAX)
(FPT-86P-M01)
86
44
Details of "A" part
0.25(.010)
INDEX
0.45/0.75
(.018/.030)
0~8˚
1
43
LEAD No.
*22.22±0.10(.875±.004)
11.76±0.20(.463±.008)
10.16±0.10(.400±.004)
0.22−+00..0045
.009 −+..000022
1.20(.047)MAX
(Mounting height)
0.145+−00..0035
.006−+..000012
M
0.10(.004)
"A"
0.50(.020)TYP
0.10±0.05
(.004±.002)
(STAND OFF)
0.10(.004)
21.00(.827)REF
C
Dimensions in MM (inches)
1996 FUJITSU LIMITED F86001S-1C-1
54
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
MEMO
55
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
FUJITSU LIMITED
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F0001
FUJITSU LIMITED Printed in Japan
相关型号：
MB81F64442B-103LFN
Synchronous DRAM, 16MX4, 6ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54
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