MB81F64842D-102FN [FUJITSU]
Synchronous DRAM, 8MX8, 6ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54;
| 型号： | MB81F64842D-102FN |
| 厂家： | 
FUJITSU |
| 描述： | Synchronous DRAM, 8MX8, 6ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54 时钟 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总45页 (文件大小：716K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-11053-1E
MEMORY
CMOS
4 × 2 M × 8 BIT
SYNCHRONOUS DYNAMIC RAM
MB81F64842D-75/-102/-102L
CMOS 4-Bank × 2,097,152-Word × 8 Bit
Synchronous Dynamic Random Access Memory
■ DESCRIPTION
The Fujitsu MB81F64842D is a CMOS Synchronous Dynamic Random Access Memory (SDRAM) containing
67,108,864 memory cells accessible in a 8-bit format. The MB81F64842D features a fully synchronous operation
referenced to a positive edge clock whereby all operations are synchronized at a clock input which enables high
performance and simple user interface coexistence. The MB81F64842D SDRAM is designed to reduce the
complexity of using a standard dynamic RAM (DRAM) which requires many control signal timing constraints, and
may improve data bandwidth of memory as much as 5 times more than a conventional DRAM.
The MB81F64842D is ideally suited for workstations, personal computers, laser printers, high resolution graphic
adapters/accelerators and other applications where an extremely large memory and bandwidth are required and
where a simple interface is needed.
■ PRODUCT LINE & FEATURES
MB81F64842D
Parameter
Reference Value
@66MHz(CL=2)
-75
-102/-102L
CL - tRCD - tRP
3 - 3 - 3 clk min.
133 MHz max.
10 ns min.
2 - 2 - 2 clk min.
100 MHz max.
10 ns min.
2 - 2 - 2 clk min.
66 MHz max.
15ns min.
Clock Frequency
CL = 2
CL = 3
CL = 2
CL = 3
Burst Mode Cycle Time
7.5 ns min.
6 ns max.
10 ns min.
10 ns min.
8 ns max.
6 ns max.
Access Time from Clock
Operating Current
5.4 ns max.
85 mA max.
1 mA max.
6 ns max.
6 ns max.
80 mA max.
65 mA max.
1 mA max.
1 mA max.
Power Down Mode Current (ICC2P)
Self Refresh Current (ICC6)
1 mA max.
1 mA max.
1 mA max./ 500 µA max.
• Single +3.3 V Supply ±0.3 V tolerance
• LVTTL compatible I/O interface
• 4 K refresh cycles every 64 ms
• Four bank operation
• Programmable burst type, burst length, and
CAS latency
• Auto-and Self-refresh (every 15.6 µs)
• CKE power down mode
• Burst read/write operation and burst
read/single write operation capability
• Output Enable and Input Data Mask
MB81F64842D-75/-102/-102L
■ PACKAGE
54-pin plastic TSOP(II)
Marking side
(FPT-54P-M02)
(Normal Bend)
Package and Ordering Information
– 54-pin plastic (400 mil) TSOP-II, order as MB81F64842D-×××FN (Standard version) or
MB81F64842D-×××LFN (Low power version)
2
MB81F64842D-75/-102/-102L
■ PIN ASSIGNMENTS AND DESCRIPTIONS
54-Pin TSOP(II)
(TOP VIEW)
<Normal Bend: FPT-54P-M02>
VCC
DQ0
VCCQ
N.C.
DQ1
VSSQ
N.C.
DQ2
VCCQ
N.C.
DQ3
VSSQ
N.C.
VCC
VSS
54
53
52
1
2
3
4
5
6
7
8
DQ7
VSSQ
N.C.
DQ6
VCCQ
N.C.
DQ5
VSSQ
N.C.
DQ4
VCCQ
N.C.
VSS
N.C.
DQM
CLK
CKE
N.C.
A11
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
N.C.
WE
CAS
RAS
CS
A13 (BA0)
A12 (BA1)
A10/AP
A0
A9
A8
A7
A6
A5
A4
VSS
A1
A2
A3
VCC
(Marking side)
Pin Number
Symbol
VCC, VCCQ
DQ0 to DQ7
VSS, VSSQ *
N.C.
Function
1, 3, 9, 14, 27, 43, 49
2, 5, 8, 11, 44, 47, 50, 53
6, 12, 28, 41, 46, 52, 54
Supply Voltage
Data I/O
Ground
4, 7, 10, 13, 15, 36, 40, 42, 45, 48, 51
No Connection
Write Enable
16
17
WE
CAS
Column Address Strobe
Row Address Strobe
Chip Select
18
RAS
19
CS
20, 21
22
A13 (BA0), A12 (BA1) Bank Select (Bank Address)
AP
Auto Precharge Enable
• Row: A0 to A11
• Column: A0 to A8
22, 23, 24, 25, 26, 29, 30, 31, 32, 33,
34, 35
A0 to A11
Address Input
37
38
39
CKE
CLK
Clock Enable
Clock Input
DQ MASK
DQM
* : These pins are connected internally in the chip.
3
MB81F64842D-75/-102/-102L
■ BLOCK DIAGRAM
Fig. 1 – MB81F64842D BLOCK DIAGRAM
CLK
CKE
To each block
BANK-3
BANK-2
BANK-1
BANK-0
CLOCK
BUFFER
RAS
CS
CONTROL
SIGNAL
LATCH
CAS
WE
RAS
CAS
COMMAND
DECODER
WE
DRAM
CORE
MODE
REGISTER
(4,096 × 512 × 8)
A0 to A11,
A10/AP
ADDRESS
BUFFER/
REGISTER
ROW
ADDR.
A12 (BA1)
A13 (BA0)
COL.
ADDR.
COLUMN
ADDRESS
COUNTER
DQM
I/O
I/O DATA
BUFFER/
REGISTER
VCC
DQ0
to
DQ7
VCCQ
VSS/VSSQ
4
MB81F64842D-75/-102/-102L
■ FUNCTIONAL TRUTH TABLE Note *1
COMMAND TRUTH TABLE Note *2, *3, and *4
CKE
A13,
CS RAS CAS WE A12
(BA)
A8
to
A0
A10
Symbol
Function
Notes
A11
A9
(AP)
n-1
H
H
H
H
H
H
H
H
H
H
H
n
X
X
X
X
X
X
X
X
X
X
X
Device Deselect
No Operation
*5 DESL
*5 NOP
BST
H
L
L
L
L
L
L
L
L
L
L
X
H
H
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
V
V
V
V
V
V
X
L
X
X
X
X
X
X
X
V
X
X
L
X
X
X
L
X
X
X
X
X
X
X
V
X
X
V
X
X
X
V
V
V
V
V
X
X
V
Burst Stop
Read
*6 READ
*6 READA
*6 WRIT
*6 WRITA
*7 ACTV
PRE
H
H
L
Read with Auto-precharge
Write
L
H
L
L
Write with Auto-precharge
Bank Active
L
L
H
V
L
H
H
H
L
H
L
Precharge Single Bank
Precharge All Banks
Mode Register Set
L
PALL
L
L
H
L
*8,*9 MRS
L
L
Notes: *1. V = Valid, L = Logic Low, H = Logic High, X = either L or H.
*2. All commands assumes no CSUS command on previous rising edge of clock.
*3. All commands are assumed to be valid state transitions.
*4. All inputs are latched on the rising edge of clock.
*5. NOP and DESL commands have the same effect on the part. Unless spcifically noted, NOP will
represent both NOP and DESL command in later discriptions.
*6. READ, READA, WRIT and WRITA commands should only be issued after the corresponding bank has
been activated (ACTV command). Refer to STATE DIAGRAM.
*7. ACTV command should only be issued after corresponding bank has been precharged (PRE or PALL
command).
*8. Required after power up. Refer to POWER-UP INITIALIZATION in page 19.
*9. MRS command should only be issued after all banks have been precharged (PRE or PALL command).
Refer to STATE DIAGRAM.
5
MB81F64842D-75/-102/-102L
DQM TRUTH TABLE
CKE
Function
Symbol
DQM
n-1
H
n
X
X
Data Write/Output Enable
Data Mask/Output Disable
ENBL
MASK
L
H
H
CKE TRUTH TABLE
Current
CKE
A13,
A9
to
A0
A10
(AP)
Symbol
Function
Notes
CS RAS CAS WE A12
(BA)
A11
State
n-1
n
Bank Active Clock Suspend Mode Entry *1 CSUS
Any
H
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Clock Suspend Continue
*1
L
(Except Idle)
Clock
Suspend
Clock Suspend Mode Exit
L
H
X
X
X
X
X
X
X
X
Idle
Idle
Auto-refresh Command
Self-refresh Entry
*2 REF
H
H
L
H
L
L
L
L
L
L
L
H
H
H
X
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
*2, *3 SELF
H
H
L
L
H
X
H
X
H
X
H
X
H
X
H
X
Self Refresh Self-refresh Exit
SELFX
L
H
L
H
H
L
Idle
Power Down Entry
*3
PD
L
H
L
H
H
Power Down Power Down Exit
L
H
Notes: *1. The CSUS command requires that at least one bank is active. Refer to STATE DIAGRAM.
NOP or DESL commands should be issued after CSUS and PRE(or PALL) commands asserted at the
same time.
*2. REF and SELF commands should only be issued after all banks have been precharged (PRE or PALL
command). Refer to STATE DIAGRAM.
*3. SELF and PD commands should only be issued after the last read data have been appeared on DQ.
6
MB81F64842D-75/-102/-102L
OPERATION COMMAND TABLE (Applicable to single bank) Note *1
Current
State
CS RAS CAS WE
Addr
Command
Function
Notes
Idle
H
L
L
L
L
L
L
L
X
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
DESL
NOP
BST
NOP
NOP
NOP
H
L
BA, CA, AP READ/READA Illegal
*2
*2
L
BA, CA, AP
BA, RA
BA, AP
X
WRIT/WRITA Illegal
H
H
L
H
L
ACTV
Bank Active after tRCD
NOP
L
PRE/PALL
REF/SELF
L
H
Auto-refresh or Self-refresh
*3, *6
*3, *7
Mode Register Set
(Idle after tRSC)
L
L
L
L
MODE
MRS
Bank Active
H
L
L
L
L
L
L
L
L
X
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
DESL
NOP
BST
NOP
NOP
NOP
H
L
BA, CA, AP READ/READA Begin Read; Determine AP
L
BA, CA, AP
BA, RA
BA, AP
X
WRIT/WRITA Begin Write; Determine AP
H
H
L
H
L
ACTV
PRE/PALL
REF/SELF
MRS
Illegal
*2
L
Precharge; Determine Precharge Type
L
H
L
Illegal
L
L
MODE
Illegal
(Continued)
7
MB81F64842D-75/-102/-102L
Current
State
CS RAS CAS WE
Addr
Command
Function
Notes
Read
NOP (Continue Burst to End → Bank
Active)
H
X
X
X
X
DESL
NOP (Continue Burst to End → Bank
Active)
L
L
L
H
H
H
H
H
L
H
L
X
X
NOP
BST
Burst Stop → Bank Active
Terminate Burst, New Read;
Determine AP
H
BA, CA, AP READ/READA
Terminate Burst, Start Write;
Determine AP
L
L
L
H
L
L
L
H
H
L
H
L
BA, CA, AP
BA, RA
WRIT/WRITA
ACTV
*4
Illegal
*2
Terminate Burst, Precharge → Idle;
Determine Precharge Type
BA, AP
PRE/PALL
L
L
L
L
L
L
H
L
X
REF/SELF
MRS
Illegal
Illegal
MODE
Write
NOP (Continue Burst to End →
Bank Active)
H
X
X
X
X
DESL
NOP (Continue Burst to End →
Bank Active)
L
L
L
H
H
H
H
H
L
H
L
X
X
NOP
BST
Burst Stop → Bank Active
Terminate Burst, Start Read;
Determine AP
*4
*2
H
BA, CA, AP READ/READA
Terminate Burst, New Write;
Determine AP
L
L
L
H
L
L
L
H
H
L
H
L
BA, CA, AP
BA, RA
WRIT/WRITA
ACTV
Illegal
Terminate Burst, Precharge;
Determine Precharge Type
BA, AP
PRE/PALL
L
L
L
L
L
L
H
L
X
REF/SELF
MRS
Illegal
Illegal
MODE
(Continued)
8
MB81F64842D-75/-102/-102L
Current
State
CS RAS CAS WE
Addr
Command
Function
Notes
Read with
Auto-
precharge
NOP (Continue Burst to End →
Precharge → Idle)
H
L
X
H
X
H
X
H
X
DESL
NOP (Continue Burst to End →
Precharge → Idle)
X
X
NOP
BST
L
L
L
L
L
L
L
H
H
H
L
H
L
L
H
L
Illegal
BA, CA, AP READ/READA Illegal
*2
*2
*2
*2
L
BA, CA, AP
BA, RA
BA, AP
X
WRIT/WRITA Illegal
H
H
L
H
L
ACTV
PRE/PALL
REF/SELF
MRS
Illegal
Illegal
Illegal
Illegal
L
L
H
L
L
L
MODE
Write with
Auto-
precharge
NOP (Continue Burst to End →
Precharge → Idle)
H
L
X
H
X
H
X
H
X
DESL
NOP (Continue Burst to End →
Precharge → Idle)
X
X
NOP
BST
L
L
L
L
L
L
L
H
H
H
L
H
L
L
H
L
Illegal
BA, CA, AP READ/READA Illegal
*2
*2
*2
*2
L
BA, CA, AP
BA, RA
BA, AP
X
WRIT/WRITA Illegal
H
H
L
H
L
ACTV
PRE/PALL
REF/SELF
MRS
Illegal
Illegal
Illegal
Illegal
L
L
H
L
L
L
MODE
(Continued)
9
MB81F64842D-75/-102/-102L
Current
State
CS RAS CAS WE
Addr
Command
Function
Notes
Pre-
charging
H
L
L
L
L
L
X
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
DESL
NOP
BST
NOP (Idle after tRP)
NOP (Idle after tRP)
NOP (Idle after tRP)
H
L
BA, CA, AP READ/READA Illegal
*2
*2
*2
L
BA, CA, AP
BA, RA
WRIT/WRITA Illegal
H
H
ACTV
Illegal
NOP (PALL may affect other
bank)
L
L
H
L
BA, AP
PRE/PALL
*5
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
H
L
X
REF/SELF
MRS
Illegal
MODE
Illegal
Bank
Activating
X
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
DESL
NOP
NOP (Bank Active after tRCD)
NOP (Bank Active after tRCD)
NOP (Bank Active after tRCD)
BST
H
L
BA, CA, AP READ/READA Illegal
*2
*2
*2
*2
L
BA, CA, AP
BA, RA
BA, AP
X
WRIT/WRITA Illegal
H
H
L
H
L
ACTV
PRE/PALL
REF/SELF
MRS
Illegal
Illegal
Illegal
Illegal
L
L
H
L
L
L
MODE
(Continued)
10
MB81F64842D-75/-102/-102L
(Continued)
Current
State
CS RAS CAS WE
Addr
Command
Function
Notes
Refreshing
H
L
X
H
X
H
X
X
X
X
DESL
NOP (Idle after tRC)
NOP (Idle after tRC)
NOP/BST
READ/READA/
WRIT/WRITA
L
L
L
H
L
L
L
H
L
X
X
X
X
X
X
Illegal
Illegal
Illegal
ACTV/
PRE/PALL
REF/SELF/
MRS
Mode
Register
Setting
H
L
L
X
H
H
X
H
H
X
H
L
X
X
X
DESL
NOP
BST
NOP (Idle after tRSC)
NOP (Idle after tRSC)
Illegal
READ/READA/
WRIT/WRITA
L
L
H
L
L
X
X
X
X
Illegal
Illegal
ACTV/PRE/
PALL/REF/
SELF/MRS
X
ABBREVIATIONS:
RA = Row Address
BA = Bank Address
AP = Auto Precharge
CA = Column Address
Notes: *1. All entries in ORERATION COMMAND TABLE assume the CKE was High during the proceeding clock
cycle and the current clock cycle.
Illegal means don’t used command. If used, power up sequence be asserted after power shut down.
*2. Illegal to bank in specified state; entry may be legal in the bank specified by BA, depending on the state
of that bank.
*3. Illegal if any bank is not idle.
*4. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
Refer to TIMING DIAGRAM -11 & -12.
*5. NOP to bank precharging or in idle state. May precharge bank specified by BA (and AP).
*6. SELF command should only be issued after the last read data have been appeared on DQ.
*7. MRS command should only be issued on condition that all DQ are in Hi-Z.
11
MB81F64842D-75/-102/-102L
COMMAND TRUTH TABLE FOR CKE Note*1
Current
State
CKE CKE
CS RAS CAS WE
Addr
X
Function
Notes
n-1
n
Self-
refresh
H
X
X
H
X
X
X
X
X
X
Invalid
Exit Self-refresh
L
L
H
H
X
(Self-refresh Recovery → Idle after tRC)
Exit Self-refresh
(Self-refresh Recovery → Idle after tRC)
L
H
H
H
X
L
L
H
H
H
L
L
L
L
X
X
H
L
L
L
L
X
H
H
L
H
L
L
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
Illegal
Illegal
L
X
X
X
X
H
H
L
Illegal
L
X
X
X
H
H
H
L
NOP (Maintain Self-refresh)
Self-
refresh
Recovery
L
X
H
H
H
H
H
L
Invalid
H
H
H
H
H
H
Idle after tRC
Idle after tRC
Illegal
X
X
X
Illegal
X
X
Illegal
X
Illegal
*2
(Continued)
12
MB81F64842D-75/-102/-102L
Current
State
CKE CKE
CS RAS CAS WE
Addr
Function
Notes
n-1
H
L
n
X
H
H
L
Power
Down
X
H
L
X
L
L
L
H
L
L
L
L
H
L
L
L
L
L
L
X
X
X
H
X
L
X
X
H
X
X
L
X
X
H
X
X
X
L
X
Invalid
X
Exit Power Down Mode → Idle
L
X
L
X
NOP (Maintain Power Down Mode)
L
H
H
H
H
H
H
H
H
L
X
Illegal
L
H
H
X
H
L
X
Illegal
L
H
X
X
H
L
X
Illegal
All
Banks
Idle
H
H
H
H
H
H
H
H
H
H
H
H
L
X
X
X
H
L
MODE
Refer to the Operation Command Table.
MODE
Refer to the Operation Command Table.
MODE
Refer to the Operation Command Table.
L
X
Auto-refresh
L
L
MODE
Refer to the Operation Command Table.
X
H
H
H
L
X
H
H
L
X
H
L
X
X
X
X
X
X
X
X
Power Down
Power Down
Illegal
L
L
L
X
X
H
L
Illegal
L
H
L
Illegal
L
L
Self-refresh
Illegal
*3
L
L
L
X
X
X
X
Invalid
(Continued)
13
MB81F64842D-75/-102/-102L
(Continued)
Current
State
CKE CKE
CS RAS CAS WE
Addr
Function
Notes
n-1
n
Bank Active
Bank
Activating
Read/Write
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
Refer to the Operation Command Table.
Begin Clock Suspend next cycle
Invalid
H
L
L
X
X
Read with
Auto-
precharge/
Write with
Auto-
X
precharge
Clock
Suspend
H
L
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Invalid
Exit Clock Suspend next cycle
Maintain Clock Suspend
Invalid
L
Any State
Other Than
Listed
L
X
H
L
H
H
Refer to the Operation Command Table.
Illegal
Above
Notes: *1. All entries in COMMAND TRUTH TABLE FOR CKE are specified at CKE(n) state and CKE input from
CKE(n-1) to CKE(n) state must satisfy corresponding set up and hold time for CKE.
*2. CKE should be held High for tRC period.
*3. SELF command should only be issued after the last data have been appeared on DQ.
14
MB81F64842D-75/-102/-102L
■ FUNCTIONAL DESCRIPTION
SDRAM BASIC FUNCTION
Three major differences between this SDRAM and conventional DRAMs are: synchronized operation, burst mode,
and mode register.
The synchronized operation is the fundamental difference. An SDRAM uses a clock input for the synchronization,
where the DRAM is basically asynchronous memory although it has been using two clocks, RAS and CAS. Each
operation of DRAM is determined by their timing phase differences while each operation of SDRAM is determined
by commands and all operations are referenced to a positive clock edge. Fig. 2 shows the basic timing diagram
differences between SDRAMs and DRAMs.
The burst mode is a very high speed access mode utilizing an internal column address generator. Once a column
addresses for the first access is set, following addresses are automatically generated by the internal column address
counter.
ThemoderegisteristojustifytheSDRAMoperationandfunctionintodesiredsystemconditions.MODEREGISTER
TABLE shows how SDRAM can be configured for system requirement by mode register programming.
CLOCK (CLK) and CLOCK ENABLE (CKE)
All input and output signals of SDRAM use register type buffers. A CLK is used as a trigger for the register and
internal burst counter increment. All inputs are latched by a positive edge of CLK. All outputs are validated by the
CLK. CKE is a high active clock enable signal. When CKE = Low is latched at a clock input during active cycle, the
next clock will be internally masked. During idle state (all banks have been precharged), the Power Down mode
(standby) is entered with CKE = Low and this will make extremely low standby current.
CHIP SELECT (CS)
CS enables all commands inputs, RAS, CAS, and WE, and address input. When CS is High, command signals are
negated but internal operation such as burst cycle will not be suspended. If such a control isn’t needed, CS can be
tied to ground level.
COMMAND INPUT (RAS, CAS and WE)
Unlike a conventional DRAM, RAS, CAS, and WE do not directly imply SDRAM operation, such as Row address
strobe by RAS. Instead, each combination of RAS, CAS, and WE input in conjunction with CS input at a rising edge
of the CLK determines SDRAM operation. Refer to FUNCTIONAL TRUTH TABLE in page 5.
ADDRESS INPUT (A0 to A11)
Address input selects an arbitrary location of a total of 2,097,152 words of each memory cell matrix. A total of twenty
one address input signals are required to decode such a matrix. SDRAM adopts an address multiplexer in order to
reduce the pin count of the address line. At a Bank Active command (ACTV), twelve Row addresses are initially
latched and the remainder of nine Column addresses are then latched by a Column address strobe command of
either a Read command (READ or READA) or Write command (WRIT or WRITA).
BANK SELECT (A12, A13)
This SDRAM has four banks and each bank is organized as 2 M words by 8-bit.
Bank selection by A13, A12 occurs at Bank Active command (ACTV) followed by read (READ or READA), write (WRIT
or WRITA), and precharge command (PRE).
15
MB81F64842D-75/-102/-102L
DATA INPUT AND OUTPUT (DQ0 to DQ7)
Input data is latched and written into the memory at the clock following the write command input. Data output is
obtained by the following conditions followed by a read command input:
tRAC ; from the bank active command when tRCD (min) is satisfied. (This parameter is reference only.)
tCAC ; from the read command when tRCD is greater than tRCD (min). (This parameter is reference only.)
tAC ; from the clock edge after tRAC and tCAC.
The polarity of the output data is identical to that of the input. Data is valid between access time (determined by
the three conditions above) and the next positive clock edge (tOH).
DATA I/O MASK (DQM)
DQM is an active high enable input and has an output disable and input mask function. During burst cycle and when
DQM = High is latched by a clock, input is masked at the same clock and output will be masked at the second clock
later while internal burst counter will increment by one or will go to the next stage depending on burst type.
BURST MODE OPERATION AND BURST TYPE
The burst mode provides faster memory access. The burst mode is implemented by keeping the same Row address
and by automatic strobing column address. Access time and cycle time of Burst mode is specified as tAC and tCK,
respectively. The internal column address counter operation is determined by a mode register which defines burst
type and burst count length of 1, 2, 4 or 8 bits of boundary. In order to terminate or to move from the current burst
mode to the next stage while the remaining burst count is more than 1, the following combinations will be required:
Current Stage
Next Stage
Method (Assert the following command)
Burst Read
Burst Read
Read Command
1st Step
2nd Step
Mask Command (Normally 3 clock cycles)
Write Command after lOWD
Burst Read
Burst Write
Burst Write
Burst Write
Burst Read
Burst Write
Burst Write
Burst Read
Precharge
Precharge
Write Command
Read Command
Precharge Command
Precharge Command
The burst type can be selected either sequential or interleave mode if burst length is 2, 4 or 8. The sequential mode
is an incremental decoding scheme within a boundary address to be determined by count length, it assigns +1 to
the previous (or initial) address until reaching the end of boundary address and then wraps round to least significant
address (= 0). The interleave mode is a scrambled decoding scheme for A0 and A2. If the first access of column
address is even (0), the next address will be odd (1), or vice-versa.
(Continued)
16
MB81F64842D-75/-102/-102L
(Continued)
When the full burst operation is executed at single write mode, Auto-precharge command is valid only at write
operation.
The burst type can be selected either sequential or interleave mode. But only the sequential mode is usable to the
full column burst. The sequential mode is an incremental decoding scheme within a boundary address to be
determined by burst length, it assigns +1 to the previous (or initial) address until reaching the end of boundary
address and then wraps round to least significant address (= 0).
Starting Column
Burst
Address
Sequential Mode
Interleave
Length
A2 A1 A0
X X 0
X X 1
X 0 0
X 0 1
X 1 0
X 1 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 – 1
0 – 1
2
1 – 0
1 – 0
0 – 1 – 2 – 3
0 – 1 – 2 – 3
1 – 2 – 3 – 0
1 – 0 – 3 – 2
4
2 – 3 – 0 – 1
2 – 3 – 0 – 1
3 – 0 – 1 – 2
3 – 2 – 1 – 0
0 – 1 – 2 – 3 – 4 – 5 – 6 – 7
1 – 2 – 3 – 4 – 5 – 6 – 7 – 0
2 – 3 – 4 – 5 – 6 – 7 – 0 – 1
3 – 4 – 5 – 6 – 7 – 0 – 1 – 2
4 – 5 – 6 – 7 – 0 – 1 – 2 – 3
5 – 6 – 7 – 0 – 1 – 2 – 3 – 4
6 – 7 – 0 – 1 – 2 – 3 – 4 – 5
7 – 0 – 1 – 2 – 3 – 4 – 5 – 6
0 – 1 – 2 – 3 – 4 – 5 – 6 – 7
1 – 0 – 3 – 2 – 5 – 4 – 7 – 6
2 – 3 – 0 – 1 – 6 – 7 – 4 – 5
3 – 2 – 1 – 0 – 7 – 6 – 5 – 4
4 – 5 – 6 – 7 – 0 – 1 – 2 – 3
5 – 4 – 7 – 6 – 1 – 0 – 3 – 2
6 – 7 – 4 – 5 – 2 – 3 – 0 – 1
7 – 6 – 5 – 4 – 3 – 2 – 1 – 0
8
FULL COLUMN BURST AND BURST STOP COMMAND (BST)
The full column burst is an option of burst length and available only at sequential mode of burst type. This full column
burst mode is repeatedly access to the same column. If burst mode reaches end of column address, then it wraps
round to first column address (= 0) and continues to count until interrupted by the news read (READ) /write (WRIT),
precharge (PRE), or burst stop (BST) command. The selection of Auto-precharge option is illegal during the full
column burst operation except write command at BURST READ & SINGLE WRITE mode.
The BST command is applicable to terminate the burst operation. If the BST command is asserted during the burst
mode, its operation is terminated immediately and the internal state moves to Bank Active.
When read mode is interrupted by BST command, the output will be in High-Z.
For the detail rule, please refer to TIMING DIAGRAM – 8.
When write mode is interrupted by BST command, the data to be applied at the same time with BST command will
be ignored.
BURST READ & SINGLE WRITE
The burst read and single write mode provides single word write operation regardless of its burst length. In this
mode, burst read operation does not be affected by this mode.
17
MB81F64842D-75/-102/-102L
PRECHARGE AND PRECHARGE OPTION (PRE, PALL)
SDRAM memory core is the same as conventional DRAMs’, requiring precharge and refresh operations. Precharge
rewrites the bit line and to reset the internal Row address line and is executed by the Precharge command (PRE).
With the Precharge command, SDRAM will automatically be in standby state after precharge time (tRP).
The precharged bank is selected by combination of AP and A12, A13 when Precharge command is asserted. If AP
= High, all banks are precharged regardless of A12, A13 (PALL). If AP = Low, a bank to be selected by A12, A13 is
precharged (PRE).
The auto-precharge enters precharge mode at the end of burst mode of read or write without Precharge command
assertion.
This auto precharge is entered by AP = High when a read or write command is asserted. Refer to FUNCTIONAL
TRUTH TABLE.
AUTO-REFRESH (REF)
Auto-refresh uses the internal refresh address counter. The SDRAM Auto-refresh command (REF) generates
Precharge command internally. All banks of SDRAM should be precharged prior to the Auto-refresh command. The
Auto-refresh command should also be asserted every 16 µs or a total 4096 refresh commands within a 64 ms period.
SELF-REFRESH ENTRY (SELF)
Self-refresh function provides automatic refresh by an internal timer as well as Auto-refresh and will continue the
refresh function until cancelled by SELFX.
The Self-refresh is entered by applying an Auto-refresh command in conjunction with CKE = Low (SELF). Once
SDRAM enters the self-refresh mode, all inputs except for CKE will be “don’t care” (either logic high or low level
state) and outputs will be in a High-Z state. During a self-refresh mode, CKE = Low should be maintained. SELF
command should only be issued after last read data has been appeared on DQ.
Note: When the burst refresh method is used, a total of 4096 auto-refresh commands within 4 ms must be asserted
prior to the self-refresh mode entry.
SELF-REFRESH EXIT (SELFX)
To exit self-refresh mode, apply minimum tCKSP after CKE brought high, and then the No Operation command (NOP)
or the Deselect command (DESL) should be asserted within one tRC period. CKE should be held High within one
tRC period after tCKSP. Refer to Timing Diagram-16 for the detail.
It is recommended to assert an Auto-refresh command just after the tRC period to avoid the violation of refresh period.
Note: When the burst refresh method is used, a total of 4096 auto-refresh commands within 4 ms must be asserted
after the self-refresh exit.
MODE REGISTER SET (MRS)
The mode register of SDRAM provides a variety of different operations. The register consists of four operation fields;
Burst Length, Burst Type, CAS latency, and Operation Code. Refer to MODE REGISTER TABLE.
The mode register can be programmed by the Mode Register Set command (MRS). Each field is set by the address
line. Once a mode register is programmed, the contents of the register will be held until re-programmed by another
MRS command (or part loses power). MRS command should only be issued on condition that all DQ is in Hi-Z.
The condition of the mode register is undefined after the power-up stage. It is required to set each field after
initialization of SDRAM. Refer to POWER-UP INITIALIZATION below.
18
MB81F64842D-75/-102/-102L
POWER-UP INITIALIZATION
The SDRAM internal condition after power-up will be undefined. It is required to follow the following Power On
Sequence to execute read or write operation.
1. Apply power and start clock. Attempt to maintain either NOP or DESL command at the input.
2. Maintain stable power, stable clock, and NOP condition for a minimum of 100 µs.
3. Precharge all banks by Precharge (PRE) or Precharge All command (PALL).
4. Assert minimum of 2 Auto-refresh command (REF).
5. Program the mode register by Mode Register Set command (MRS).
In addition, it is recommended DQM and CKE to track VCC to insure that output is High-Z state. The Mode Register
Set command (MRS) can be set before 2 Auto-refresh command (REF).
19
MB81F64842D-75/-102/-102L
Fig. 2 – BASIC TIMING FOR CONVENTIONAL DRAM VS SYNCHRONOUS DRAM
<SDRAM>
Active
Precharge
Read/Write
CLK
CKE
H
H
H
tSI
tHI
CS
RAS
CAS
WE
H : Read
L : Write
Address
DQ
BA (A13, A12)
CA
BA (A13, A12)
RA
BA (A13, A12)
AP (A10)
CASLatency=2
Burst Length = 4
<Conventional DRAM>
Row Address Select
Column Address Select
Precharge
RAS
CAS
DQ
20
MB81F64842D-75/-102/-102L
Fig. 3 – STATE DIAGRAM (Simplified for Single BANK Operation State Diagram)
MRS
SELF
MODE
REGISTER
SET
SELF
REFRESH
SELFX
IDLE
REF
CKE\(PD)
CKE
AUTO
REFRESH
POWER
DOWN
CKE\(CSUS)
CKE
BANK
ACTIVE
SUSPEND
BANK
ACTIVE
BST
BST
READ
WRIT
READ
WRIT
WRITA
READA
CKE\(CSUS)
CKE
WRITE
SUSPEND
READ
SUSPEND
CKE\(CSUS)
CKE
READ
WRIT
WRITE
READ
WRITA
READA
READA
WRITA
CKE\(CSUS)
CKE
WRITE WITH
AUTO
PRECHARGE
READ WITH
AUTO
PRECHARGE
CKE\(CSUS)
CKE
WRITE
SUSPEND
READ
SUSPEND
PRE or
PALL
PRE or
PALL
PRE or PALL
POWER
ON
PRECHARGE
POWER
APPLIED
DEFINITION OF ALLOWS
Manual
Input
Automatic
Sequence
Note: CKE\ means CKE goes Low-level from High-level.
21
MB81F64842D-75/-102/-102L
■ BANK OPERATION COMMAND TABLE
MINIMUM CLOCK LATENCY OR DELAY TIME FOR SINGLE BANK OPERATION
Second
*4
*4
command
(same
bank)
First
command
MRS
tRSC
tRSC
tRSC
tRSC
tRSC
tRSC
tRSC
ACTV
READ
READA
WRIT
WRITA
PRE
tRCD
tRCD
tRCD
tRCD
tRAS
tRAS
1
*5
*5
*4
*4
1
1
1
1
1
1
1
*1
*2
BL+
tRP
*4
*4
*2
*2
*7
BL+
tRP
BL+
tRP
BL+
tRP
BL+
tRP
BL+
tRP
*4
*4
tWR
tWR
1
1
tDPL
tDPL
1
*2
*4
*4
*2
*2
BL-1
+ tDAL
BL-1
+ tDAL
BL-1
+ tDAL
BL-1
+ tDAL
BL-1
+ tDAL
BL-1
+ tDAL
*2
*3
*4
*2
*2
*6
tRP
tRP
tRC
tRC
tRP
tRP
tRC
tRC
1
1
1
1
tRP
tRP
tRC
tRC
tRP
tRP
tRC
tRC
1
1
*3
*6
PALL
REF
tRC
tRC
tRC
SELFX
tRC
tRC
tRC
Notes: *1. If tRP(min) ≤ CL × tCK, minimum latency is a sum of (BL + CL) × tCK.
*2. Assume all banks are in Idle state.
*3. Assume output is in High-Z state.
*4. Assume tRAS(min) is satisfied.
*5. Assume no I/O conflict.
*6. Assume after the last data have been appeared on DQ.
*7. If tRP(min) ≤ (CL-1) × tCK, minimum latency is a sum of (BL + CL-1) × tCK.
Illegal Command
22
MB81F64842D-75/-102/-102L
■ MULTI BANK OPERATIVE COMMAND TABLE
MINIMUM CLOCK LATENCY OR DELAY TIME FOR MULTI BANK OPERATION
Second
*5
*5,*6
*5
*5, *6
command
(other
bank)
First
command
MRS
tRSC
tRSC
tRSC
tRSC
tRSC
tRSC
tRSC
*2
*7
*7
*7
*10
*6
*7
*6
*7
*7
ACTV
READ
READA
WRIT
WRITA
PRE
tRRD
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
tRAS
1
*2
*4
*10
*6
1 *10
*6
*6
*6
1
1
1
*1
*2
BL+
tRP
*2
*4
*6
*6
*6
*6
*6
*2
*2
*9
BL+
tRP
1
1 *10
1
BL+
tRP
BL+
tRP
*2
*4
*6
1
1
1
1
tDPL
1
*2
*2
*4
*6
*7
*6
*7
*6
*6
*6
*2
*2
BL-1
+ tDAL
1
1
1
1
BL-1
+ tDAL
BL-1
+ tDAL
BL-1
+ tDAL
*2
*3
*2
*4
*7
*7
*6
*7
*7
*2
*2
*8
tRP
tRP
tRC
tRC
1
1
1
1
1
1
tRP
tRP
tRC
tRC
tRP
tRP
tRC
tRC
1
1
*3
*8
PALL
REF
tRP
tRC
tRC
1
tRC
tRC
tRC
SELFX
tRC
tRC
tRC
Notes: *1. If tRP(min) ≤ CL × tCK, minimum latency is a sum of (BL + CL) × tCK.
*2. Assume bank of the object is in Idle state.
*3. Assume output is in High-Z state.
*4. tRRD(min) of other bank (second command will be asserted) is satisfied.
*5. Assume other bank is in active, read or write state.
*6. Assume tRAS(min) is satisfied.
*7. Assume other banks are not in READA/WRITA state.
*8. Assume after the last data have been appeared on DQ.
*9. If tRP(min) ≤ (CL-1) × tCK, minimum latency is a sum of (BL + CL-1) × tCK.
*10. Assume no I/O conflict.
Illegal Command
23
MB81F64842D-75/-102/-102L
■ MODE REGISTER TABLE
MODE REGISTER SET
A13
0
A12
0
A11
0
A10
0
A9
A8
0
A7
0
A6
A5
A4
A3
A2
A1
A0
ADDRESS
Op-
code
MODE
REGISTER
CL
BT
BL
A5
Burst Length
A6
A4
CAS Latency
A2
A1
A0
BT = 1 *2
BT = 0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
Reserved
2
2
4
3
4
Reserved
Reserved
Reserved
Reserved
8
8
Reserved
Reserved
Reserved
Full Column
Reserved
Reserved
Reserved
Reserved
A9
Op-code
A3
Burst Type
0
1
Burst Read & Burst Write
Burst Read & Single Write *1
0
1
Sequential (Wrap round, Binary-up)
Interleave (Wrap round, Binary-up)
Notes: *1. When A9 = 1, burst length at Write is always one regardless of BL value.
*2. BL = 1 and Full Column are not applicable to the interleave mode.
24
MB81F64842D-75/-102/-102L
■ ABSOLUTE MAXIMUM RATINGS (See WARNING)
Parameter
Voltage of VCC Supply Relative to VSS
Voltage at Any Pin Relative to VSS
Short Circuit Output Current
Power Dissipation
Symbol
VCC, VCCQ
VIN, VOUT
IOUT
Value
–0.5 to +4.6
–0.5 to +4.6
±50
Unit
V
V
mA
W
PD
1.3
Storage Temperature
TSTG
–55 to +125
°C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
(Referenced to VSS)
Parameter
Notes
Symbol
VCC, VCCQ
VSS, VSSQ
VIH
Min.
3.0
0
Typ.
3.3
0
Max.
3.6
Unit
V
Supply Voltage
0
V
Input High Voltage
Input Low Voltage
Ambient Temperature
*1
*2
2.0
–0.5
0
—
VCC + 0.5
0.8
V
VIL
—
V
TA
—
70
°C
Notes:
VIH
Pulse width ≤ 5 ns
4.6 V
VIL max
VIL
50% of pulse amplitude
VIH
VIH min
50% of pulse amplitude
–1.5V
Pulse width ≤ 5 ns
VIL
*2. Undershoot limit: VIL (min)
*1. Overshoot limit: VIH (max)
= VSS –1.5 V for pulse width <= 5 ns acceptable,
pulse width measured at 50% of pulse amplitude.
= 4.6 V for pulse width <= 5 ns acceptable,
pulse width measured at 50% of pulse amplitude.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
■ CAPACITANCE
(TA = 25°C, f = 1 MHz)
Parameter
Symbol
CIN1
Min.
2.5
Typ.
—
Max.
Unit
pF
Input Capacitance, Except for CLK
Input Capacitance for CLK
I/O Capacitance
5.0
4.0
6.5
CIN2
2.5
—
pF
CI/O
4.0
—
pF
25
MB81F64842D-75/-102/-102L
■ DC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.) Note *1, *2 , and *3
Value
Parameter
Symbol
Condition
Unit
Min.
2.4
—
Max.
—
Output High Voltage
VOH(DC) IOH = –2 mA
VOL(DC) IOL = 2 mA
0 V ≤ VIN ≤ VCC;
V
V
Output Low Voltage
0.4
Input Leakage Current (Any Input)
ILI
All other pins not under
test = 0 V
–5
–5
5
µA
µA
0 V ≤ VIN ≤ VCC;
Data out disabled
Output Leakage Current
ILO
5
Burst Length = 1
tRC = min
tCK = min
One bank active
Output pin open
Addresses changed up to
one time during tCK (min)
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
MB81F64842D-75
85
80
MB81F64842D-102
/-102L
Operating Current
(Average Power
Supply Current)
ICC1S
—
mA
*4
65
Reference Value
@66MHz(CL=2)
CKE = VIL
All banks idle
tCK = min
Power down mode
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
ICC2P
—
—
1.0
mA
mA
CKE = VIL
All banks idle
CLK = VIH or VIL
Power down mode
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
MB81F64842D-75
/-102
1.0
0.5
ICC2PS
MB81F64842D-102L
MB81F64842D-75
Precharge Standby
Current
(Power Supply
Current)
CKE = VIH
15
15
All banks idle, tCK = 15 ns
NOP command only,
Input signals (except to
CMD) are changed one
time during 30 ns
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
MB81F64842D-102
/-102L
ICC2N
—
—
mA
mA
*4
Reference Value
@66MHz(CL=2)
15
CKE = VIH
All banks idle
CLK =VIH or VIL
Input signal are stable
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
ICC2NS
2
(Continued)
26
MB81F64842D-75/-102/-102L
(Continued)
Value
Parameter
Symbol
Condition
CKE = VIL
Any bank active
tCK = min
Unit
Min.
Max.
MB81F64842D-75
/-102
2
ICC3P
—
mA
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
MB81F64842D-102L
1
1
CKE = VIL
Any bank active
CLK = VIH or VIL
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
ICC3PS
—
—
mA
mA
CKE = VIH
Any bank active
tCK = 15 ns
NOP command only,
Input signals (except to
CMD) are changed one
time during 30 ns
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
Active Standby
Current
(Power Supply
Current)
MB81F64842D-75
25
25
MB81F64842D-102
/-102L
ICC3N
*4
25
2
Reference Value
@66MHz(CL=2)
CKE = VIH
Any bank active
CLK = VIH or VIL
Input signals are stable
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
ICC3NS
—
—
mA
mA
tCK = min
MB81F64842D-75
135
100
Burst Length = 4
Output pin open
All-banks active
Gapless data
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
Burst mode Current MB81F64842D-102
(Average Power
Supply Current)
/-102L
ICC4
*4
70
Reference Value
@66MHz(CL=2)
MB81F64842D-75
150
140
Auto-refresh;
tCK = min
tRC = min
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
Refresh Current #1 MB81F64842D-102
(Average Power
Supply Current)
/-102L
ICC5
—
—
mA
*4
100
1
Reference Value
@66MHz(CL=2)
MB81F64842D-75
Self-refresh;
tCK = min
CKE ≤ 0.2 V
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
mA
µA
Refresh Current #2
(Average Power
Supply Current)
/-102
ICC6
MB81F64842D-102L
500
Notes: *1. All voltage are referenced to VSS.
*2. DC characteristics are measured after following the POWER-UP INITIALIZATION procedure.
*3. ICC depends on the output termination or load conditions, clock cycle rate, signal clocking rate.
The specified values are obtained with the output open and no termination register.
*4. This value is for reference only.
27
MB81F64842D-75/-102/-102L
■ AC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.) Note *1, *2, and *3
*4
ReferenceValue
@66MHz(CL=2)
MB81F64842D
-75
MB81F64842D
-102/-102L
Parameter
Notes
Symbol
Unit
Min.
10
Max.
Min.
10
10
3
Max.
Min.
15
10
3
Max.
CL = 2
CL = 3
tCK2
tCK3
tCH
tCL
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Period
—
—
—
7.5
2.5
2.5
1.5
0.8
Clock High Time
Clock Low Time
Input Setup Time
Input Hold Time
*5
—
—
—
—
6
—
—
—
—
6
—
—
—
—
8
*5
*5
*5
3
3
tSI
2
2
tHI
1
1
Access Time
from Clock
(tCK = min)
CL = 2
CL = 3
tAC2
tAC3
tLZ
*5,*6,*7
*5
—
—
0
—
0
5.4
—
6
6
6
Output in Low-Z
0
3
—
6
—
8
CL = 2
CL = 3
CL = 2
CL = 3
tHZ2
tHZ3
Output in High-Z
*5,*8
3
3
2.7
3
5.4
6
6
Output Hold Time
*5,*7
tOH
—
3
—
3
—
2.7
Time between Auto-Refresh
tREFI
—
15.6
—
15.6
—
15.6
µs
command interval
Time between Refresh
Transition Time
*4
tREF
tT
—
64
10
—
64
10
—
64
10
ms
ns
0.5
0.5
0.5
CKE Setup Time
for Power Down
Exit Time
*5
tCKSP
1.5
—
2
—
2
—
ns
28
MB81F64842D-75/-102/-102L
BASE VALUES FOR CLOCK COUNT/LATENCY
*4
MB81F64842D
-75
MB81F64842D
-102/-102L
Reference
Value
@66MHz(CL=2)
Parameter
Notes
Symbol
Unit
Min.
Max.
Min.
Max.
Min.
Max.
CL=3 CL=2
RAS Cycle Time
*9
t
RC
67.5
22.5
45
70
20
50
20
10
—
—
70
20
50
20
10
—
—
80
30
50
30
10
—
—
ns
ns
RAS Precharge Time
RAS Active Time
tRP
tRAS
tRCD
tWR
110000
—
110000
—
110000 ns
RAS to CAS Delay Time
Write Recovery Time
22.5
7.5
—
—
ns
ns
—
—
RAS to RAS Bank Active Delay
Time
tRRD
tDPL
15
15
—
20
10
—
—
—
20
10
—
—
—
20
10
—
—
—
ns
ns
ns
Data-in to Precharge Lead Time
1 cyc
+ tRP
1 cyc
+ tRP
1 cyc
+ tRP
CL=2
tDAL2
Data-in to Active/
Refresh Command
2 cyc
+ tRP
2 cyc
+ tRP
2 cyc
+ tRP
Period
CL=3
tDAL3
tRSC
—
—
—
—
—
—
—
ns
ns
Mode Resister Set Cycle Time
15
20
20
20
CLOCK COUNT FORMULA Note *10
Base Value
Clock ≥
(Round off a whole number)
Clock Period
29
MB81F64842D-75/-102/-102L
LATENCY - FIXED VALUES
(The latency values on these parameters are fixed regardless of clock period.)
*4
MB81F64842D
-75
MB81F64842D
-102/-102L
Reference
Value
Parameter
Notes Symbol
Unit
@66MHz(CL=2)
CKE to Clock Disable
lCKE
lDQZ
lDQD
1
2
0
1
2
0
1
2
0
cycle
cycle
cycle
DQM to Output in High-Z
DQM to Input Data Delay
Last Output to Write Command
Delay
lOWD
lDWD
2
0
2
0
2
0
cycle
cycle
Write Command to Input Data
Delay
CL = 2
lROH2
lROH3
lBSH2
lBSH3
lCCD
2
3
2
3
1
1
2
3
2
3
1
1
2
3
2
3
1
1
cycle
cycle
cycle
cycle
cycle
cycle
Precharge to Output
in High-Z Delay
CL = 3
CL = 2
CL = 3
Burst Stop Command to
Output in High-Z Delay
CAS to CAS Delay (min)
CAS Bank Delay (min)
lCBD
Notes: *1. AC characteristics are measured after following the POWER-UP INITIALIZATION procedure.
*2. AC characteristics assume tT = 1 ns and 50 pF of capacitive load.
*3. 1.4Visthereferencelevelformeasuringtimingofinputsignals. Transitiontimesaremeasuredbetween
VIH (min) and VIL (max). (See Fig. 5)
*4. This value is for reference only.
*5. If input signal transition time (tT) is longer than 1 ns; [(tT/2) –0.5] ns should be added to tAC (max), tHZ
(max), and tCKSP (min) spec values, [(tT/2) –0.5] ns should be subtracted from tLZ (min), tHZ (min), and
tOH (min) spec values, and (tT –1.0) ns should be added to tCH (min), tCL (min), tSI (min), and tHI (min)
spec values.
*6. tAC also specifies the access time at burst mode .
*7. tAC and tOH are the specs value under AC test load circuit shown in Fig. 4.
*8. Specified where output buffer is no longer driven.
*9. Actual clock count of tRC (lRC) will be sum of clock count of tRAS (lRAS) and tRP (lRP).
*10. All base values are measured from the clock edge at the command input to the clock edge for the next
command input. All clock counts are calculated by a simple formula: clock count equals base value
divided by clock period (round off to a whole number).
30
MB81F64842D-75/-102/-102L
Fig. 4 – OUTPUT LOAD CIRCUIT
Output
CL = 50 pF
LVTTL
Note: By adding appropriate correlation factors to the test conditions, tAC and tOH measured when the output
is coupled to the Output Load Circuit are within specifications.
31
MB81F64842D-75/-102/-102L
Fig. 5 – TIMING DIAGRAM, SETUP, HOLD AND DELAY TIME
tCK
tCH
tCL
2.4 V
1.4 V
CLK
0.4 V
tSI
tHI
2.4 V
0.4 V
Input
(Control,
Addr. & Data)
1.4 V
tAC
tHZ
tOH
tLZ
2.4 V
0.4 V
Output
1.4 V
Note: Reference level of input signal is 1.4 V for LVTTL.
Access time is measured at 1.4 V for LVTTL.
Fig. 6 – TIMING DIAGRAM, DELAY TIME FOR POWER DOWN EXIT
Don’t Care
CLK
CKE
1 clock (min)
tCKSP (min)
Don’t Care
NOP
NOP
ACTV
Command
32
MB81F64842D-75/-102/-102L
Fig. 7 – TIMING DIAGRAM, PULSE WIDTH
CLK
tRC, tRP, tRAS, tRCD, tWR, tREF,
tDPL, tDAL, tRSC, tRRD, tCKSP
Input
COMMAND
COMMAND
(Control)
Note: These parameters are a limit value of the rising edge of the clock from one command input to next input. tCKSP is the
latency value from the rising edge of CKE.
Measurement reference voltage is 1.4 V.
Fig. 8 – TIMING DIAGRAM, ACCESS TIME
CLK
READ
COMMAND
tAC
tAC
tAC
(CL − 1) × tCK
Q (valid)
Q (valid)
Q (valid)
DQ
(OUTPUT)
33
MB81F64842D-75/-102/-102L
■ TIMING DIAGRAMS
TIMING DIAGRAM – 1 : CLOCK ENABLE - READ AND WRITE SUSPEND (@ BL = 4)
CLK
CKE
*1
*1
ICKE (1 clock)
ICKE (1 clock)
*2
*2
CLK
(Internal)
*2
(NO CHANGE)
*2
(NO CHANGE)
DQ
(Read)
Q1
D1
Q2
Q3
Q4
D4
*3
*3
WRITTEN
DQ
(Write)
NOT
WRITTEN
NOT
D2
D3
Notes: *1. The latency of CKE (lCKE) is one clock.
*2. During read mode, burst counter will not be incremented/decremented at the next clock of CSUS command. Output
data remain the same data.
*3. During the write mode, data at the next clock of CSUS command is ignored.
TIMING DIAGRAM – 2 : CLOCK ENABLE - POWER DOWN ENTRY AND EXIT
CLK
tCKSP
(min)
1 clock
(min)
CKE
*4
*1
*2
*3
*3
Command
NOP
PD(NOP)
DON’T CARE
tREF (max)
NOP
NOP
ACTV
Notes: *1. Precharge command (PRE or PALL) should be asserted if any bank is active and in the burst mode.
*2. Precharge command can be posted in conjunction with CKE after the last read data have been appeared on DQ.
*3. It is recommended to apply NOP command in conjunction with CKE.
*4. The ACTV command can be latched after tCKSP (min) + 1 clock (min).
34
MB81F64842D-75/-102/-102L
TIMING DIAGRAM – 3 : COLUMN ADDRESS TO COLUMN ADDRESS INPUT DELAY
CLK
RAS
CAS
ICCD
(1 clock)
ICCD
ICCD
ICCD
tRCD (min)
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
ROW
ADDRESS
Address
Note: CAS to CAS delay can be one or more clock period.
TIMING DIAGRAM – 4 : DIFFERENT BANK ADDRESS INPUT DELAY
CLK
tRRD (min)
RAS
CAS
ICBD
(1 clock)
tRCD (min) or more
ICBD
tRCD (min)
ROW
ADDRESS
ROW
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
Address
A12, A13(BA)
Bank 0
Bank 3
Bank 0
Bank 3
Bank 0
Bank 3
Note: CAS Bank delay can be one or more clock period.
35
MB81F64842D-75/-102/-102L
TIMING DIAGRAM – 5 : DQM - INPUT MASK AND OUTPUT DISABLE (@ BL = 4)
CLK
DQM
(@ Read)
IDQZ (2 clocks)
DQ
(@ Read)
Q1
Q2
Hi-Z
Q4
End of burst
DQM
(@ Write)
IDQD (same clock)
DQ
(@ Write)
D1
MASKED
D3
D4
End of burst
TIMING DIAGRAM – 6 : PRECHARGE TIMING (APPLIED TO THE SAME BANK)
CLK
tRAS (min)
PRECHARGE
ACTV
Command
Note: PRECHARGE means ‘PRE’ or ‘PALL’.
36
MB81F64842D-75/-102/-102L
TIMING DIAGRAM – 7 : READ INTERRUPTED BY PRECHARGE (EXAMPLE @ CL = 2, BL = 4)
CLK
Command
DQ
PRECHARGE
IROH (2 clocks)
Q1
Hi-Z
Command
DQ
PRECHARGE
IROH (2 clocks)
Q2
Hi-Z
Q1
Command
DQ
PRECHARGE
IROH (2 clocks)
Q3
Hi-Z
Q1
Q2
Command
DQ
PRECHARGE
No effect (end of burst)
Q3 Q4
Q1
Q2
Note: In case of CL = 2, the lROH is 2 clocks.
In case of CL = 3, the lROH is 3 clocks.
PRECHARGE means ‘PRE’ or ‘PALL’.
37
MB81F64842D-75/-102/-102L
TIMING DIAGRAM – 8 : READ INTERRUPTED BY BURST STOP (EXAMPLE @ BL = Full Column)
CLK
Command
(CL = 2)
BST
Qn
lBSH (2 clocks)
Hi-Z
Qn–2
Qn–1
Qn+1
DQ
BST
Command
(CL = 3)
lBSH (3 clocks)
Hi-Z
DQ
Qn-2
Qn-1
Qn
Qn+1
Qn+2
TIMING DIAGRAM – 9 : WRITE INTERRUPTED BY BURST STOP (EXAMPLE @ CL = 2)
CLK
Command
DQ
BST
COMMAND
Masked
by BST
LAST Dn
38
MB81F64842D-75/-102/-102L
TIMING DIAGRAM – 10 : WRITE INTERRUPTED BY PRECHARGE (EXAMPLE @ CL = 3)
CLK
ACTV
PRECHARGE
tDPL (min)
Command
tRP (min)
MASKED
by Precharge
DQ
LAST Dn
Dn-1
Note: The precharge command (PRE) should only be issued after the tDPL of final data input is satisfied.
PRECHARGE means ‘PRE’ or ‘PALL’.
TIMING DIAGRAM – 11 : READ INTERRUPTED BY WRITE (EXAMPLE @ CL = 3, BL = 4)
CLK
IOWD (2 clocks)
READ
WRIT
Command
DQM
*1
*2
*3
IDQZ (2 clocks)
IDWD (same clock)
DQ
Q1
D1
D2
Masked
Notes: *1. First DQM makes high-impedance state High-Z between last output and first input data.
*2. Second DQM makes internal output data mask to avoid bus contention.
*3. Third DQM in illustrated above also makes internal output data mask. If burst read ends (final data output) at or after the
second clock of burst write, this third DQM is required to avoid internal bus contention.
39
MB81F64842D-75/-102/-102L
TIMING DIAGRAM – 12 : WRITE TO READ TIMING (EXAMPLE @ CL = 3, BL = 4)
CLK
tWR (min)
Command
WRIT
READ
DQM
DQ
(CL-1) × tCK
tAC (max)
D3
D1
D2
Q1
Q2
Masked
by READ
Note: Read command should be issued after tWR of final data input is satisfied.
40
MB81F64842D-75/-102/-102L
TIMING DIAGRAM – 13 : READ WITH AUTO-PRECHARGE
(EXAPLE @ CL = 2, BL = 2 Applied to same bank)
CLK
tRAS (min)
tRP (min)
ACTV
READA
NOP or DESL
ACTV
Command
*1
2 clocks
*2
(same value as BL)
BL+tRP (min)
DQM
DQ
Q1
Q2
Notes: *1. Precharge at Read with Auto-precharge command (READA) is started from number of clocks that is the same as
Burst Length (BL) after the READA command is asserted.
*2. Next ACTV command should be issued after BL+tRP (min) from READA command.
TIMING DIAGRAM – 14 : WRITE WITH AUTO-PRECHARGE *1, *2, *3
(EXAMPLE @ CL = 2, BL = 2 Applied to same bank)
tRAS (min)
CLK
tDPL (min) *4
tDAL (min)
*5
BL+tRP (min)
Command
ACTV
WRITA
NOP or DESL
ACTV
DQM
DQ
D1
D2
Notes: *1. Even if the final data is masked by DQM, the precharge does not start the clock of final data input.
*2. Once auto precharge command is asserted, no new command within the same bank can be issued.
*3. Auto-precharge command doesn’t affect at full column burst operation except Burst READ & Single Write.
*4. Precharge at write with Auto-precharge is started after the tDPL from the end of burst.
*5. Next command should be issued after BL+ tRP (min) at CL = 2, BL+1+tRP (min) at CL = 3 from WRITA command.
41
MB81F64842D-75/-102/-102L
TIMING DIAGRAM – 15 : AUTO-REFRESH TIMING
CLK
*3
*4
*3
*3
*1
*3
Command
REF
NOP
NOP
NOP
REF
NOP
Command
tRC (min)
tRC (min)
*2
DON’T CARE
*2
DON’T CARE
BA
A12, A13 (BA)
Notes: *1. All banks should be precharged prior to the first Auto-refresh command (REF).
*2. Bank select is ignored at REF command. The refresh address and bank select are selected by internal refresh counter.
*3. Either NOP or DESL command should be asserted during tRC period while Auto-refresh mode.
*4. Any activation command such as ACTV or MRS command other than REF command should be asserted after tRC from the
last REF command.
TIMING DIAGRAM – 16 : SELF-REFRESH ENTRY AND EXIT TIMING
CLK
tCKSP (min)
tSI (min)
CKE
*4
tRC (min)
*2
*3
*1
SELF
DON’T CARE
SELFX
Command
NOP
NOP
NOP
Command
Notes: *1. Precharge command (PRE or PALL) should be asserted if any bank is active prior to Self-refresh Entry command (SELF).
*2. The Self-refresh Exit command (SELFX) is latched after tCKSP (min). It is recommended to apply NOP command in
conjunction with CKE.
*3. Either NOP or DESL command can be used during tRC period.
*4. CKE should be held high within one tRC period after tCKSP.
42
MB81F64842D-75/-102/-102L
TIMING DIAGRAM – 17 : MODE REGISTER SET TIMING
CLK
tRSC (min)
MRS
NOP or DESL
ACTV
Command
Address
ROW
ADDRESS
MODE
Note: The Mode Register Set command (MRS) should only be asserted after all banks have been precharged.
43
MB81F64842D-75/-102/-102L
■ PACKAGE DIMENSION
54-pin plastic TSOP(II)
(FPT-54P-M02)
*: Resin protrusion. (Each side: 0.15 (.006) MAX)
54
28
Details of "A" part
0.15(.006)
0.25(.010)
0.15(.006)
MAX
"A"
INDEX
0.40(.016)
MAX
1
27
LEAD No.
*22.22±0.10
(.875±.004)
1.15±0.05
(.045±.002)
11.76±0.20
(.463±.008)
(Mounting height)
0.32 –+00..0078
.013 –+..000033
10.16±0.10
(.400±.004)
0.125±0.05
(.005±.002)
M
0.16(.006)
0.50±0.10
(.020±.004)
10.76±0.20
(.424±.008)
0.80(.0315)
TYP
0.10(.004)
20.80(.819)REF
0.05(.002)MIN
(STAND OFF)
Dimensions in mm (inches)
C
1997 FUJITSU LIMITED F54003S-1C-1
44
MB81F64842D-75/-102/-102L
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
All Rights Reserved.
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: 81(44) 754-3763
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
Fax: 81(44) 754-3329
http://www.fujitsu.co.jp/
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and
Fax: (408) 922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: (800) 866-8608
measurement equipment, personal or household devices, etc.).
CAUTION:
Fax: (408) 922-9179
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded
(such as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
http://www.fujitsumicro.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
Any semiconductor devices have an inherent chance of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
http://www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for
export of those products from Japan.
http://www.fmap.com.sg/
F9910
FUJITSU LIMITED Printed in Japan
相关型号：
©2020 ICPDF网 联系我们和版权申明