MB82D01161-90PBT [FUJITSU]
Standard SRAM, 1MX16, 90ns, CMOS, PBGA48, 0.80 MM PITCH, PLASTIC, FBGA-48;
| 型号： | MB82D01161-90PBT |
| 厂家： | 
FUJITSU |
| 描述： | Standard SRAM, 1MX16, 90ns, CMOS, PBGA48, 0.80 MM PITCH, PLASTIC, FBGA-48 静态存储器 内存集成电路 |
| 文件： | 总26页 (文件大小：497K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-11405-1E
MEMORY Mobile FCRAM™
CMOS
16Mbit (1M word x 16 bit)
Mobile Phone Application Specific Memory
MB82D01161-85/85L/90/90L
CMOS 1,048,576-WORD x 16 BIT
Fast Cycle Random Access Memory
with Low Power SRAM Interface
■ DESCRIPTION
The Fujitsu MB82D01161 is a CMOS Fast Cycle Random Access Memory (FCRAM) with asynchronous Static
Random Access Memory (SRAM) interface containing 16,777,216 storages accessible in a 16-bit format. This
MB82D01161 is suited for low power applications such as Cellular Handset and PDA.
Note : FCRAM is a trademark of Fujitsu Limited, Japan.
■ PRODUCT LINEUP
MB82D01161
85
85L
90
90L
Access Time ( tAA Max & tCE Max )
Active Current ( IDDA1 Max )
85ns
90ns
20mA
Standby Current ( IDDS1 Max )
Power Down Current ( IDDS1 Max )
200µA
100µA
200µA
100µA
10µA
■ PACKAGES
48-ball plastic FBGA
48-ball plastic FBGA
(BGA-48P-M16)
(BGA-48P-M18)
MB82D01161-85/85L/90/90L
■ FEATURES
• Asynchronous SRAM Interface
• 1M word ×16bit Organization
• Fast Random Cycle Time:
tRC = 90ns
• Fast Random Access Time
tAA = tCE = 85ns (-85), 90ns (-90)
• Low Power Consumption:
IDDS1 = 200µA, 100µA (L version)
• Wide Operating Conditions:
VDD = +2.3V to +2.7V
+2.7V to +3.1V
+3.1V to +3.5V
TA = −30oC to +85oC
• Byte Write Control
• Power Down Control by CE2
2
MB82D01161-85/85L/90/90L
■ PIN ASSIGNMENTS
(TOP VIEW)
Flash Compatible FBGA
(suffix PBT)
SRAM Compatible FBGA
(suffix PBN)
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
E
F
A4
A3
A2
A1
A0
A17
A7
UB
LB
CE2
WE
NC
A8
A9
A12
A13
A14
A15
A16
NC
A
B
C
D
E
F
LB
OE
UB
A0
A3
A1
A4
A2
CE2
DQ9
CE1 DQ1
A6
A18
A10
A11
DQ8
DQ10 DQ11
A5
A6
DQ2
DQ4
DQ5
DQ6
WE
A11
DQ3
VDD
VSS
A5
NC
DQ3
A19
VSS
VDD
DQ12
DQ13
A17
NC
A14
A12
A9
A7
DQ1
DQ6
A16
A15
A13
A10
CE1 DQ9 DQ11 DQ13 DQ15
DQ15 DQ14
DQ7
DQ8
NC
G
H
OE
VSS
DQ10 DQ12
VDD
DQ14 DQ16
G
H
DQ16
A18
A19
A8
DQ2
DQ4
DQ5
DQ7
VSS
(BGA-48P-M16)
(BGA-48P-M18)
■ PIN DESCRIPTION
Pin Name
A0 to A19
CE1
Description
Address Input
Chip Enable (Low Active)
Chip Enable (High Active)
Write Enable (Low Active)
Output Enable (Low Active)
CE2
WE
OE
LB
Lower Byte Write Control (Low Active)
Upper Byte Write Control (Low Active)
Lower Byte Data Input/Output
Upper Byte Data Input/Output
Power Supply
UB
DQ1 to DQ8
DQ9 to DQ16
VDD
VSS
Ground
NC
No Connection
3
MB82D01161-85/85L/90/90L
■ BLOCK DIAGRAM
VDD
VSS
Memory
Cell
Array
A0
to
A19
Address
Latch &
Buffer
Row
Decoder
16,777,216 bit
DQ1
to
Input Data
Latch &
Controller
Input /
Output
Buffer
Output
Data
Controller
DQ8
Sense /
Switch
DQ9
to
DQ16
Column /
Decoder
Address
Latch &
Buffer
Power
Control
CE2
CE1
WE
LB
Timing
Controller
UB
OE
4
MB82D01161-85/85L/90/90L
■ FUNCTION TRUTH TABLE *1
DQ1 to
DQ8
DQ9 to
DQ16
Data
Retention
Mode
CE1 CE2
WE
OE
LB
UB
IDD
Power Down
L
X
X
X
X
X
X
H
X
X
X
X
X
X
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
IDDP
L
No
Standby (Deselect)
H
IDDS
Output Disable*2
Read*3
H
Output
Valid
Output
Valid
L
X
L
X
L
Input
Valid
Input
Valid
H
Yes
Write
L
IDDA
Input
Valid
Write (Upper Byte)
Write (Lower Byte)
L
H
L
H
L
Invalid
Input
Valid
H
Invalid
*1 : L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance
*2 : Output Disable condition should not be kept longer than 1µs.
*3 : Byte control at Read operation is not supported.
5
MB82D01161-85/85L/90/90L
■ ABSOLUTE MAXIMUM RATINGS
Ratings
Parameter
Symbol
Unit
Min
-0.5
-0.5
-50
Max
+3.6
+3.6
+50
Voltage of VDD Supply Relative to VSS
Voltage at Any Pin Relative to VSS
Short Circuit Output Current
Storage Temperature
VDD
VIN, VOUT
IOUT
V
V
mA
oC
TSTG
-55
+125
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Notes
Symbol
Unit
Min
3.1
2.7
2.3
0
Max
3.5
3.1
2.7
0
VDD (31)
VDD (27)
VDD (23)
VSS
V
V
V
V
Supply Voltage
*1
VDD+0.3
and
VIH (31)
2.6
V
≤ 3.6
High Level Input Voltage
*1,*2
*1,*2
VIH (27)
VIH (23)
VIL
2.3
2.0
-0.3
-30
VDD+0.3
VDD+0.3
0.4
V
V
Low Level Input Voltage
Ambient Temperature
V
TA
85
°C
*1 : All voltages are referenced to VSS.
*2 : Minimum DC voltage on input or I/O pins are -0.3V. During voltage transitions, inputs may negative overshoot
VSS to -1.0V for periods of up to 5ns. Maximum DC voltage on input and I/O pins are
VDD+0.3V. During voltage transitions, outputs may positive overshoot to VDD+1.0V for periods of up to 5 ns.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
■ PIN CAPACITANCE
Value
Parameter
Symbol
Conditions
Unit
Typ
—
Max
Address Input Capacitance
Output Capacitance
CIN1
COUT
CIN2
VIN = 0V
5
8
5
pF
pF
pF
VOUT = 0V
VIN = 0V
—
Control Pin Capacitance
—
Note : Test conditions TA = 25°C, f = 1.0 MHz
6
MB82D01161-85/85L/90/90L
■ ELECTRICAL CHARACTERISTICS
1. DC Characteristics
Value
Parameter
Symbol
Test Conditions
Unit
Min
-1.0
-1.0
1.8
—
Max
+1.0
+1.0
—
Input Leakage Current
ILI
VIN = VSS to VDD
µA
µA
V
Output Leakage Current
Output High Voltage Level
Output Low Voltage Level
ILO
VOUT = VSS to VDD, Output Disable
IOH = –0.5 mA
VOH
VOL
IOL = 1 mA
0.4
V
VDD = VDD (31) Max, VIN ≤ 0.2 V or
VIN ≥ VDD – 0.2 V, CE1 = CE2 ≤ 0.2 V,
IOUT=0 mA
—
—
20
10
µA
VDD Power Down Current
IDDP
VDD = VDD (27, 23) Max, VIN ≤ 0.2 V or
VIN ≥ VDD – 0.2 V, CE1 = CE2 ≤ 0.2 V,
IOUT=0 mA
µA
mA
mA
—
—
2.5
2.0
VDD = VDD (31) Max, VIN = VIH or VIL
CE2 = VIL or CE1 = CE2 = VIH, IOUT=0 mA
L version
IDDS
—
2.0
VDD = VDD (27, 23) Max, VIN = VIH or VIL
CE2 = VIL or CE1 = CE2 = VIH, IOUT=0 mA
L version
L version
—
—
1.5
VDD Standby
Current
VDD = VDD (31) Max, VIN ≤ 0.2 V or
VIN ≥ VDD – 0.2 V, CE2 ≤ 0.2 V or,
CE1 = CE2 ≥ VDD – 0.2V, IOUT=0 mA
250
µA
µA
—
150
IDDS1
VDD = VDD (27, 23) Max, VIN ≤ 0.2V or
VIN ≥ VDD – 0.2 V, CE2 ≤ 0.2 V or,
CE1 = CE2 ≥ VDD – 0.2V, IOUT=0 mA
—
—
200
100
L version
tRC / tWC =
Min
VDD = VDD (31) Max,
VIN = VIH or VIL,
CE1 = VIL and CE2= VIH,
IOUT=0 mA
IDDA1
IDDA2
IDDA1
IDDA2
—
—
—
—
25
4.0
20
mA
mA
mA
mA
tRC / tWC =
Max
VDD Active Current
tRC / tWC =
Min
VDD = VDD (27, 23) Max,
VIN = VIH or VIL,
CE1 = VIL and CE2= VIH,
IOUT=0 mA
tRC / tWC =
Max
3.0
Notes : • All voltages are referenced to Vss.
• DC Characteristics are measured after following POWER-UP timing.
• IDDA depends on the output load conditions.
7
MB82D01161-85/85L/90/90L
2. AC Characteristics
(1) Read Operation
-85/-85L
-90/-90L
Parameter
Symbol
Unit
Notes
Min
Max
Min
Max
Read Cycle Time
tRC
90
1000
90
1000
ns
ns
*1
Address Setup Time at CE1 High to Low
Transition
tASC
–5
—
–5
—
Address Hold Time during CE1 Low
Address Access Time
tAHC
tAA
90
—
—
—
5
—
85
85
60
—
—
—
25
15
—
—
90
—
—
—
5
—
90
90
60
—
—
—
25
15
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*2
*3
*3
*3
*3
*4
*4
*4
*4
Chip Enable Access Time
Output Enable Access Time
Output Data Hold Time
tCE
tOE
tOH
CE1 Low to Output Low-Z
OE Low to Output Low-Z
CE1 High to Output High-Z
OE High to Output High-Z
CE1 High Pulse Width
tCLZ
tOLZ
tCHZ
tOHZ
tCP
10
0
10
0
—
—
10
–5
—
—
10
–5
CE1 High to Address Hold Time
tCHAH
*5
Address Invalid Time during Read
(CE1=Low)
tAX
—
10
—
10
ns
*1 : Maximum value is a reference and is applied to Output Disable condition.
*2 : tAHC must be satisfied every address valid state after tAX during CE1=Low.
*3 : The output load is 30pF.
*4 : The output load is 5pF.
*5 : If actual address change before CE1 High transition is earlier than tCHAH (Min), tCP (CE1 High period)
should be kept at least tRC (Min) period.
8
MB82D01161-85/85L/90/90L
(2) Write Operation
Parameter
-85/-85L
-90/-90L
Symbol
Unit Notes
Min
Max
1000
—
Min
Max
1000
—
Write Cycle Time
tWC
tAS
90
0
90
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*1
Address Setup Time
Address Hold Time
tAH
40
0
—
40
0
—
CE1 Write Setup Time
CE1 Write Hold Time
WE, LB, UB Setup Time
WE, LB, UB Hold Time
OE Setup Time
tCS
1000
1000
—
1000
1000
—
*2
*2
tCH
0
0
tBS
0
0
tBH
0
—
0
—
tOES
tOEH
tOHCL
tOHAH
tCW
tWP
tWRC
tWR
tDS
0
—
0
—
OE Hold Time
15
–5
0
—
15
–5
0
—
OE High to CE1 Low Setup Time
OE High to Address Hold Time
CE1 Write Pulse Width
WE Write Pulse Width
CE1 Write Recovery Time
WE Write Recovery Time
Data Setup Time
—
—
*3
*4
—
—
60
60
15
15
20
10
10
0
—
60
60
15
15
20
10
10
0
—
*5, *6
*5, *6
*7
—
—
—
—
1000
—
1000
—
*2, *7
Data Hold Time
tDH
—
—
CE1 Low to Output in Low-Z
OE Low to Output in Low-Z
tCLZ
tOLZ
—
—
*8
*8
—
—
*1 : Minimum value must be equal or greater than the sum of actual write pulse width (tCW or tWP) and write recovery
time (tWRC or tWR).
Maximum value is a reference and applied to Output Disable condition.
*2 : Maximum value is applied to Output Disable condition.
*3 : tOHCL (Min) must be satisfied if read operation is not performed prior to write operation.
In case OE is disabled after tOHCL (Min), WE Low must be asserted after tRC (Min) from CE1 Low.
*4 : Applicable if CE1 stays Low after read operation.
*5 : tWHP (Max) must be satisfied for the high pulse noise.
*6 : tCW and tWP are applied if write operation is initiated by CE1 and WE, respectively.
*7 : tWRC and tWR are applied if write pulse is terminated by CE1 and WE, respectively.
*8 : The output load is 5 pF.
9
MB82D01161-85/85L/90/90L
(3) Power Down Parameter
Parameter
Value
Max
Symbol
Unit
Note
Min
100
100
CE2 Low Setup Time for Power Down Entry
tCSP
tCPP
—
—
ns
ns
CE1 Low Pulse Width during Power Down mode
CE2 Low Hold Time after Power Down Exit
(CE1 = High)
tC2LP
tC1HP
350
300
—
—
µs
µs
*1
*2
CE1 High Hold Time following CE2 High after Power Down
Exit
*1 : Requires at least two dummy read cycles.
*2 : Required when dummy read cycles are not performed.
(4) Other Timing Parameter
Parameter
Value
Symbol
Unit
Note
Min
10
Max
—
CE1 High to OE Invalid Time for Standby Entry
CE1 High to WE Invalid Time for Standby Entry
CE1 and CE2 Active Glitch Pulse Width
tCHOX
tCHWX
tCAP
ns
ns
ns
20
—
—
5
*1
*2
CE1 or WE High Glitch Pulse Width
during Write Cycle
tWHP
—
5
ns
CE2 Low Hold Time after Power-up
tC2LP
tC1HP
350
300
—
—
µs
µs
*3
*4
CE1 High Hold Time following CE2 High after Power-up
*1 : Active means a condition where CE1 = VIL and CE2 =VIH.
*2 : Specified to the one time high pulse width during tCW or tWP and excluded 10ns from beginning
and ending of the write cycle.
*3 : Requires at least two dummy read cycles.
*4 : Required when dummy read cycles are not performed.
(5) AC Test Conditions
Parameter
Symbol
VIH
Conditions
VDD = 3.1V to 3.5V
VDD = 2.7V to 3.1V
VDD = 2.3V to 2.7V
—
Measured
Unit
2.6
2.3
2.0
0.4
1.5
1.3
1.1
5
Input High Level
V
Input Low Level
VIL
V
V
VDD = 3.1V to 3.5V
VDD = 2.7V to 3.1V
VDD = 2.3V to 2.7V
Between VIL and VIH
Input Timing Measurement Level
Input Transition Time
VREF
V
V
tT
ns
10
MB82D01161-85/85L/90/90L
■ TIMING DIAGRAMS
1. READ Timing #1 (CE1 Control)
tRC
tRC
Address
CE1
Address Valid
Address Valid
tAHC
tAHC
tCHAH
tASC
tCE
tCHAH
tCE
tASC
tCP
tCHZ
*
tOE
tOHZ
OE
tOH
tOH
tCLZ
tOLZ
DQ
(Output)
Valid Data Output
Valid Data Output
Note : CE2 and WE must be HIGH for entire read cycle.
* : Output Disable condition before new Read data valid should not be kept longer than 1µs.
2. READ Timing #2 (Address Access)
tAX
tAX
tRC
tRC
Address
CE1
Address Valid
Address Valid
tAHC
tCE
tCHAH
tAA
tASC
tCP
*
tOE
*
OE
tOHZ
tOLZ
tOH
tOH
DQ
(Output)
Valid Data Output
Valid Data Output
Note : CE2 and WE must be HIGH for entire read cycle.
* : Output Disable condition before new Read data valid should not be kept longer than 1µs.
11
MB82D01161-85/85L/90/90L
3. WRITE Timing #1 (CE1 Control)
Address
CE1
Address Valid
tAH
tAS
tWC
tCW
tWRC
tBH
tBS
WE
tBS
tBH
UB, LB
OE
tOHCL
tOEH
tCLZ
tDH
tDS
DQ
(Input)
Valid Data Input
Note : CE2 must be HIGH for write cycle.
12
MB82D01161-85/85L/90/90L
4. WRITE Timing #2 (WE Control)
Address
CE1
Address Valid
tAS
tOHAH
tAH
tCH
tOHCL
tCS
tWC
WE
tWR
tBH
tWP
tBS
UB, LB
OE
tOES
tOEH
tOHZ
tOLZ
tDS
tDH
DQ
(Input)
Valid Data Input
Note : CE2 must be HIGH for write cycle.
13
MB82D01161-85/85L/90/90L
5. BYTE WRITE Timing #1 (CE1 Control)
Address
CE1
Address Valid
tAH
tAS
tWC
tCW
tWRC
tBH
tBS
WE
tBS
tBH
tOEH
tDH
UB, LB
OE
tOHCL
tCLZ
tDS
DQ
(Input)
Valid Data Input
Note : CE2 must be HIGH and either LB or UB must be LOW for byte write cycle.
14
MB82D01161-85/85L/90/90L
6. BYTE WRITE Timing #2 (WE Control)
Address
CE1
Address Valid
tAH
tOHAH
tAS
tCH
tOHCL
tCS
tWC
WE
tWR
tBH
tWP
tBS
UB, LB
OE
tOES
tOEH
tOHZ
tOLZ
tDH
tDS
DQ
(Input)
Valid Data Input
Note : CE2 must be HIGH and either LB or UB must be LOW for byte write cycle.
15
MB82D01161-85/85L/90/90L
7. READ / WRITE Timing #1-1 (CE Control)
Address
CE1
Address Valid
tAH
Don’t Care
tWC
tAS
tASC
tCHAH
tCP
tWRC
tBS
tCW
tBS
tBH
WE
UB, LB
OE
tBS
tBH
tOHCL
tOEH
tCHZ
tCLZ
tDS
tDH
DQ
Read Data Output
Write Data Input
Note : Write address is edge trigger of either CE1 or WE falling edge.
16
MB82D01161-85/85L/90/90L
8. READ / WRITE Timing #1-2 (CE Control)
Address
CE1
Read Address Valid
tAHC
Write Addr.
tASC
tAS
tCHAH
tWRC
tCP
tRC
tBS
tBH
tBS
WE
UB, LB
OE
tBH
tBS
tCE
tOE
tOHCL
tOEH
tOLZ
tCLZ
tCHZ
tDH
tOH
DQ
Write Data Input
Read Data Output
Note : WE must be HIGH for read cycle.
17
MB82D01161-85/85L/90/90L
9. READ / WRITE Timing #2-1 (OE and WE Control)
tAX
Address
CE1
Address Valid
tAH
Don’t Care
tOHAH
tAS
tWC
Low
tWP
tWR
WE
UB, LB
OE
tBS
tBH
tOES
tOEH
tOHZ
tOLZ
tDS
tDH
DQ
Read Data Output
Write Data Input
Note : CE1 can be tied to LOW for WE and OE controlled operation.
When CE1 is tied to LOW, output is exclusively controlled by OE and read address can be issued after
WE is brought to High.
WARNING : The read address following write operation must be changed if CE1 stays LOW.
18
MB82D01161-85/85L/90/90L
10. READ / WRITE Timing #2-2 (OE and WE Control))
tAX
Address
CE1
Read Address Valid
tAHC
Write Addr.
tAS
tOHAH
Low
tWR
tRC
WE
UB, LB
OE
tBH
tAA
tBS
tOEH
tOE
tOES
tOHZ
tDH
tOLZ
tOH
DQ
Write Data Input
Read Data Output
Note : CE1 can be tied to LOW for WE and OE controlled operation.
When CE1 is tied to LOW, output is exclusively controlled by OE and read address can be issued after
WE is brought to High.
WARNING : The read address following write operation must be changed if CE1 stays LOW.
19
MB82D01161-85/85L/90/90L
11. Standby Entry Timing after Read or Write
CE1
tCHOX
tCHWX
OE
WE
Active (Read)
Standby
Active (Write)
Standby
Note : Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it
takes tRC (Min) period from either last address transition or CE1 Low to High transition.
12. Chip Enable Timing
CE1
tCAP
tCAP
tCAP
CE2
Note : tCAP is not applicable CE2 HIGH pulse width while CE1 stays LOW and CE2 should not use as a read
and write timing control signal in stead of CE1.
13. POWER DOWN Timing
tCPP
CE1
tCSP
tC2LP
CE2
Power Down Entry
Power Down Mode
Power Down Exit
Note : A minimum of two dummy read cycle must be performed prior to regular read and write operation after tC2LP.
Otherwise CE1 must kept High for tC1HP period after tC2LP.
20
MB82D01161-85/85L/90/90L
14. Power-Up Timing #1
tRC *2
tRC
1
*
CE1
CE2
VDD
tAHC
tAHC
tCP
tCP
tC2LP
VDD Min
0V
*1 : It is recommended CE1 to track VDD. The tC2LP specifies from valid state of CE1=High and CE2=Low after
VDD reaches specified minimum level.
*2 : A minimum of two dummy read cycle must be performed prior to regular read and write operation after tC2LP.
15. Power-Up Timing #2 (No dummy cycle)
tC1HP *2
1
*
CE1
tC2LP
CE2
VDD
VDD Min
0V
*1 : It is recommended CE1 to track VDD. The tC2LP specifies from valid state of CE1=High and CE2=Low
after VDD reaches specified minimum level.
*2 : No dummy read cycle is required if tC1HP is satisfied.
21
MB82D01161-85/85L/90/90L
■ DATA RETENTION
Low VDD Characteristics
Value
Max
Parameter
Symbol
Test Conditions
Unit
Min
CE1 = CE2 ≥ VDD – 0.2V or,
CE1 = CE2 = VIH,
VDD Data Retention Supply Voltage
-85/-90
VDR
2.1
3.5
V
VDD = VDR,
VIN = VIH(23) or VIL
CE1 = CE2 = VIH(23)
—
—
—
—
2.5
2.0
IDR
mA
-85L/-90L
VDD Data Retention
Supply Current
-85/-90
VDD = VDR Min,
VIN ≤ 0.2V or VIN ≥ VDD – 0.2V,
CE1 = CE2 ≥ VDD – 0.2V
200
100
IDR1
µA
-85L/-90L
VDD = VDD(27) Min
at data retention entry
Data Retention Setup Time
tDRS
0
—
ns
VDD = VDD(27) Min
after data retention
Data Retention Recovery Time
VDD Voltage Transition Time
tDRR
200
0.2
—
—
ns
∆V/∆t
V/µs
Data Retention Timing
tDRS
tDRR
3.5V
VDD
∆V/∆t
∆V/∆t
2.7V
CE2
2.1V
CE2 = CE1 > VDD-0.2V or
VIH(23) Min
CE1
0.4V
VSS
Data Retention Mode
Data bus must be in High-Z at data retention entry.
22
MB82D01161-85/85L/90/90L
■ ORDERING INFORMATION
Part Number
Package
Remarks
tCE = 85ns Max, IDDS1 = 200 µA Max
MB82D01161-85PBT
MB82D01161-85LPBT
Flash Compatible Package
tCE = 85ns Max, IDDS1 = 100 µA Max
Flash Compatible Package
48-ball plastic FBGA 0.8mm pitch
(BGA-48P-M16)
tCE = 90ns Max, IDDS1 = 200 µA Max
MB82D01161-90PBT
MB82D01161-90LPBT
MB82D01161-85PBN
MB82D01161-85LPBN
MB82D01161-90PBN
MB82D01161-90LPBN
Flash Compatible Package
tCE = 90ns Max, IDDS1 = 100 µA Max
Flash Compatible Package
tCE = 85ns Max, IDDS1 = 200 µA Max
SRAM Compatible Package
tCE = 85ns Max, IDDS1 = 100 µA Max
SRAM Compatible Package
48-ball plastic FBGA 0.75mm pitch
(BGA-48P-M18)
tCE = 90ns Max, IDDS1 = 200 µA Max
SRAM Compatible Package
tCE = 90ns Max, IDDS1 = 100 µA Max
SRAM Compatible Package
23
MB82D01161-85/85L/90/90L
■ PACKAGE DIMENSIONS
48-ball plastic FBGA
(BGA-48P-M16)
1.05 –+00..1105
.041 –+..000046
(Mounting height)
(Stand off)
9.00±0.10(.354±.004)
(5.60(.220))
0.36±0.10
(.014±.004)
0.80(.031)
TYP
6
5
4
3
2
1
6.00±0.10
(.236±.004)
(4.00(.157))
0.80(.031)
TYP
H
G
F
E
D
C
B
A
INDEX AREA
48-Ø0.45±0.10
(48-Ø.018±.004)
M
0.08(.003)
0.20(.008) S
S
0.10(.004)
C
2000 FUJITSU LIMITED B48016S-1c-1
Dimensions in mm (inches)
(Continued)
24
MB82D01161-85/85L/90/90L
(Continued)
48-ball plastic FBGA
(BGA-48P-M18)
1.05 –+00..1105
.041 –+..000046
(Mounting height)
(5.25(.207))
9.00±0.10(.354±.004)
0.25±0.10
(.010±.004)
0.75(.030)
(Stand off)
TYP
6
5
4
6.00±0.10
(.236±.004)
(3.75(.148))
3
2
1
0.75(.030)
TYP
INDEX MARK
H
F
E
D
C
B
A
G
INDEX AREA
48-ø0.35±0.10
(48-ø.014±.004)
M
0.08(.003)
0.20(.008)
S
S
0.10(.004)
S
C
2001 FUJITSU LIMITED B48018S-c-1-1
Dimensions in mm (inches)
25
MB82D01161-85/85L/90/90L
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0112
FUJITSU LIMITED Printed in Japan
相关型号：
©2020 ICPDF网 联系我们和版权申明