MB82D01171A-80LPBT [FUJITSU]
16 Mbit (1 M word x 16 bit) Mobile Phone Application Specific Memory; 16兆位（ 1 M个字×16位）手机专用内存
| 型号： | MB82D01171A-80LPBT |
| 厂家： | 
FUJITSU |
| 描述： | 16 Mbit (1 M word x 16 bit) Mobile Phone Application Specific Memory |
| 文件： | 总27页 (文件大小：249K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-11404-2E
MEMORY Mobile FCRAMTM
CMOS
16 Mbit (1 M word × 16 bit)
Mobile Phone Application Specific Memory
MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL
CMOS 1,048,576-WORD × 16 BIT
Fast Cycle Random Access Memory
with Low Power SRAM Interface
■ DESCRIPTION
The Fujitsu MB82D01171A is a CMOS Fast Cycle Random Access Memory (FCRAM) with asynchronous Static
Random Access Memory (SRAM) interface containing 16,777,216 storages accessible in a 16-bit format. This
MB82D01171A is suited for low power applications such as Cellular Handset and PDA.
Note: FCRAM is a trademark of Fujitsu Limited, Japan.
■ PRODUCT LINEUP
MB82D01171A
Parameter
80
80L
80LL
85
85L
85LL
90
90L
90LL
Access Time (tAA Max, tCE Max)
Active Current (IDDA1 Max)
80 ns
85 ns
20 mA
90 ns
Standby Current (IDDS1 Max)
Power Down Current (IDDP Max)
200 µA 100 µA 70 µA 200 µA 100 µA 70 µA 200 µA 100 µA 70 µA
10 µA
■ PACKAGES
48-ball plastic FBGA
48-ball plastic FBGA
(BGA-48P-M16)
(BGA-48P-M18)
MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL
■ FEATURES
• Asynchronous SRAM Interface
• 1 M word × 16 bit Organization
• Fast Random Cycle Time : tRC = 90 ns
• Fast Random Access Time : tAA = tCE = 80 ns, 85 ns, 90 ns
• Low Power Consumption : IDDS1 = 200 µA, 100 µA (L version) , 70 µA (LL version)
• Wide Operating Conditions : VDD = +2.3 V to +2.7 V
+2.7 V to +3.1 V
+3.1 V to +3.5 V
TA = −30 °C to +85 °C
• Byte Write Control
• 4 words Address Access Capability
• Power Down Control by CE2
2
MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL
■ PIN ASSIGNMENTS
(TOP VIEW)
Flash Compatible FBGA
(suffix PBT)
SRAM Compatible FBGA
(suffix PBN)
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
E
F
A
B
C
D
E
F
A4
A3
A2
A1
A0
A17
A7
A6
A5
UB CE2
A8
A9
A12
A13
A14
A15
A16
LB
OE
UB
A0
A3
A1
A4
A2
CE2
LB
A18
NC
WE
NC
A19
DQ9
CE1 DQ1
DQ2 DQ3
A10
A11
DQ10 DQ11
VSS DQ12
A5
A6
A17
A7
DQ4
DQ5
VDD
VSS
DQ1 DQ3 DQ6 DQ8
VDD DQ13 NC
A16
A15
A13
A10
CE1 DQ9 DQ11 DQ13 DQ15 NC
OE DQ10 DQ12 VDD DQ14 DQ16
DQ15 DQ14
DQ16 A19
A14
A12
A9
DQ6 DQ7
WE DQ8
G
H
G
H
VSS
DQ2 DQ4 DQ5 DQ7
VSS
A18
A8
A11
NC
(BGA-48P-M16)
(BGA-48P-M18)
■ PIN DESCRIPTION
Pin Name
A0 to A19
CE1
Description
Address Input
Chip Enable (Low Active)
Chip Enable (High Active)
Write Enable (Low Active)
Output Enable (Low Active)
CE2
WE
OE
LB
Lower Byte Write Control (Low Active)
Upper Byte Write Control (Low Active)
Lower Byte Data Input/Output
Upper Byte Data Input/Output
Power Supply
UB
DQ1 to DQ8
DQ9 to DQ16
VDD
VSS
Ground
NC
No Connection
3
MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL
■ BLOCK DIAGRAM
VDD
VSS
Memory
Address
Cell
Array
16,777,216 bit
Row
Decoder
Latch &
Buffer
A0 to A19
DQ1 to DQ8
DQ9 to DQ16
I/O
Buffer
Output
Data
Control
Input Data
Latch &
Control
Sense /
Switch
Column /
Decoder
Address
Latch &
Buffer
Power
Control
CE2
CE1
WE
LB
Timing
Control
UB
OE
4
MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL
■ FUNCTION TRUTH TABLE *1
DQ1 to
DQ8
DQ9 to
DQ16
Data
Retention
Mode
CE1 CE2 WE
OE
LB
UB
IDD
Power Down *2
X
H
L
X
X
X
X
H
X
X
X
X
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
IDDP
No
Standby (Deselect)
Output Disable*3
IDDS
H
Output
Valid
Output
Valid
Read*4
L
X
L
X
L
Input
Valid
Input
Valid
H
Yes
Write
L
IDDA
Input
Valid
Write (Lower Byte)
Write (Upper Byte)
L
H
L
H
L
Invalid
Input
Valid
H
Invalid
*1 : V = Valid, L = Logic Low, H = Logic High, X = either “L” or “H”, High-Z = High Impedance
*2 : Power Down mode can be entered from Standby state and all DQ pins are in High-Z state.
*3 : Output Disable mode should not be kept longer than 1 µs.
*4 : Byte control at Read mode is not supported.
5
MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL
■ ABSOLUTE MAXIMUM RATINGS
Rating
Parameter
Voltage of VDD Supply Relative to VSS
Voltage at Any Pin Relative to VSS
Symbol
Unit
Min
−0.5
−0.5
−0.5
−50
Max
+3.6
+3.6
+3.6
+50
VDD
VIN
V
V
VOUT
IOUT
TSTG
V
Short Circuit Output Current
Storage Temperature
mA
°C
−55
+125
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Unit
Min
3.1
2.7
2.3
0
Max
3.5
3.1
2.7
0
VDD (31)
VDD (27)
VDD (23)
VSS
V
V
V
V
Supply Voltage *1
VDD + 0.3
and
VIH (31)
2.6
V
≤ 3.6
High Level Input Voltage *1, *2
Low Level Input Voltage *1, *2
VIH (27)
VIH (23)
VIL (31)
VIL (27)
VIL (23)
TA
2.2
2.0
VDD + 0.3
VDD + 0.3
0.5
V
V
−0.3
−0.3
−0.3
−30
V
0.5
V
0.4
V
Ambient Temperature
85
°C
*1 : All voltages are referenced to VSS.
*2 : Minimum DC voltage on input or I/O pins are −0.3 V. During voltage transitions, inputs may undershoot VSS to
−1.0 V for periods of up to 5 ns. Maximum DC voltage on input and I/O pins are VDD + 0.3 V.
During voltage transitions, inputs may positive overshoot to VDD + 1.0 V for periods of up to 5 ns.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
6
MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL
■ PIN CAPACITANCE
(f = 1.0 MHz, TA = +25 °C)
Value
Parameter
Symbol
Conditions
Unit
Min
Typ
Max
Address Input Capacitance
Control Input Capacitance
Data Input/Output Capacitance
CIN1
CIN2
CIO
VIN = 0 V
VIN = 0 V
VIO = 0 V
5
5
8
pF
pF
pF
■ ELECTRICAL CHARACTERISTICS
1. DC Characteristics
Value
Parameter
Symbol
Conditions
Unit
Min
Max
+1.0
+1.0
Input Leakage Current
Output Leakage Current
ILI
VSS ≤ VIN ≤ VDD
−1.0
−1.0
2.4
µA
µA
V
ILO
0 V ≤ VOUT ≤ VDD, Output Disable
VDD = VDD(31), IOH = −0.5 mA
VDD = VDD(27), IOH = −0.5 mA
VDD = VDD(23), IOH = −0.5 mA
IOL = 1 mA
VOH(31)
VOH(27)
VOH(23)
VOL
Output High Voltage Level
Output Low Voltage Level
2.25
1.8
V
V
0.4
20
V
VDD = VDD(31) Max, VIN = VIH or VIL,
µA
µA
CE2 ≤ 0.2 V
VDD Power Down Current
IDDP
VDD = VDD(27, 23) Max, VIN = VIH or VIL,
10
CE2 ≤ 0.2 V
5.5
2.0
1.5
5
VDD = VDD(31) Max,
VIN = VIH or VIL
CE1 = CE2 = VIH, IOUT = 0 mA
L Version
IDDS
mA
mA
µA
LL Version
VDD = VDD(27, 23) Max,
VIN = VIH or VIL
CE1 = CE2 = VIH, IOUT = 0 mA
L Version
IDDS
1.5
1
LL Version
VDD Standby
Current
250
150
120
200
100
70
VDD = VDD(31) Max,
VIN ≤ 0.2 V or VIN ≥ VDD − 0.2 V,
CE1 = CE2 ≥ VDD − 0.2 V, IOUT = 0 mA
L Version
IDDS1
LL Version
VDD = VDD(27, 23) Max,
VIN ≤ 0.2 V or VIN ≥ VDD − 0.2 V,
CE1 = CE2 ≥ VDD − 0.2 V, IOUT = 0 mA
L Version
IDDS1
µA
LL Version
(Continued)
7
MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL
(Continued)
Value
Min Max
Parameter
Symbol
Conditions
Unit
VDD(31) = VDD Max,
VIN = VIH or VIL,
CE1 = VIL and CE2 = VIH, IOUT
= 0 mA
25
20
tRC / tWC =
Min
IDDA1
mA
VDD(27, 23) = VDD Max,
VIN = VIH or VIL,
CE1 = VIL and CE2 = VIH, IOUT
= 0 mA
VDD Active Current
VDD(31) = VDD Max,
VIN = VIH or VIL,
4.0
3.0
CE1 = VIL and CE2 = VIH, IOUT
= 0 mA
tRC / tWC =
1 µs
IDDA2
mA
VDD(27, 23) = VDD Max,
VIN = VIH or VIL,
CE1 = VIL and CE2 = VIH, IOUT
= 0 mA
Notes: • All voltages are referenced to Vss.
• DC Characteristics are measured after following POWER-UP timing.
• IOUT depends on the output load conditions.
8
MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL
2. AC Characteristics
(1) Read Operation
-80/-80L/
-80LL
-85/-85L/
-85LL
-90/-90L/
-90LL
Parameter
Symbol
Unit
Notes
Min Max Min Max Min Max
Read Cycle Time
tRC
tCE
90
90
90
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable Access Time
Output Enable Access Time
Address Access Time
80
45
80
85
45
85
90
45
90
*1, *3
*1
tOE
tAA
*1, *4
*1
Output Data Hold Time
CE1 Low to Output Low-Z
OE Low to Output Low-Z
CE1 High to Output High-Z
OE High to Output High-Z
Address Setup Time to CE1 Low
tOH
5
5
0
5
5
0
5
5
0
tCLZ
*2
tOLZ
*2
tCHZ
tOHZ
tASC
tASO
tASO[ABS]
tAX
30
25
30
25
30
25
*2
*2
−5
45
10
−5
45
10
−5
45
10
*5
*3, *6
*7
Address Setup Time to OE Low
Address Invalid Time
5
5
5
*4
CE1 Low to Address Hold Time
OE Low to Address Hold Time
CE1 High to Address Hold Time
OE High to Address Hold Time
CE1 Low to OE Low Delay Time
OE Low to CE1 High Delay Time
CE1 High Pulse Width
tCLAH
tOLAH
tCHAH
tOHAH
tCLOL
tOLCH
tCP
90
45
−5
−5
90
45
−5
−5
90
45
−5
−5
*4
*4, *8
45 1000 45 1000 45 1000 ns *3, *6, *8, *9
45
20
45
20
45
20
ns
ns
*8
tOP
45 1000 45 1000 45 1000 ns
20 20 20 ns
*6, *8, *9
*7
OE High Pulse Width
tOP[ABS]
*1: The output load is 30 pF.
*2: The output load is 5 pF.
*3: The tCE is applicable if OE is brought to Low before CE1 goes Low and is also applicable if actual value of both
or either tASO or tCLOL is shorter than specified value.
*4: Applicable only to A0 and A1 when both CE1 and OE are kept at Low for the address access.
*5: Applicable if OE is brought to Low before CE1 goes Low.
*6: The tASO, tCLOL (Min) and tOP (Min) are reference values when the access time is determined by tOE.
If actual value of each parameter is shorter than specified minimum value, tOE become longer by the amount of
subtraction actual value from specified minimum value.
For example, if actual tASO, tASO (actual) , is shorter than specified minimum value, tASO (Min) , during OE control
access (i.e., CE1 stays Low) , the tOE become tOE (Max) + tASO (Min) − tASO (actual) .
*7: The tASO[ABS] and tOP[ABS] is the absolute minimum value during OE control access.
*8: If actual value of either tCLOL or tOP is shorter than specified minimum value, both tOLAH and tOLCH become
tRC (Min) − tCLOL (actual) or tRC (Min) − tOP (actual) .
*9: Maximum value is applicable if CE1 is kept at Low.
9
MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL
(2) Write Operation
-80/-80L/
-80LL
-85/-85L/
-85LL
-90/-90L/
-90LL
Parameter
Symbol
Unit
Notes
Min Max Min Max Min Max
Write Cycle Time
tWC
tAS
90
0
90
0
90
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*1
*2
*2
Address Setup Time
Address Hold Time
CE1 Write Setup Time
CE1 Write Hold Time
WE Setup Time
tAH
45
0
45
0
45
0
tCS
1000
1000
1000
1000
1000
1000
tCH
0
0
0
tWS
0
0
0
WE Hold Time
tWH
0
0
0
LB and UB Setup Time
LB and UB Hold Time
OE Setup Time
tBS
−5
−5
0
−5
−5
0
−5
−5
0
tBH
tOES
tOEH
tOEH[ABS]
tOHCL
tOHAH
tCW
1000
1000
1000
*3
*3, *4
*5
45 1000 45 1000 45 1000
OE Hold Time
20
−3
0
20
−3
0
20
−3
0
OE High to CE1 Low Setup Time
Address Hold Time to OE High
CE1 Write Pulse Width
WE Write Pulse Width
CE1 Write Recovery Time
WE Write Recovery Time
Data Setup Time
*6
*7
60
60
15
60
60
15
60
60
15
*1, *8
*1, *8
*1, *9
tWP
tWRC
tWR
15 1000 15 1000 15 1000
ns *1, *3, *9
tDS
20
0
20
0
20
0
ns
ns
Data Hold Time
tDH
CE1 High Pulse Width
tCP
20
20
20
ns
*9
*1: Minimum value must be equal or greater than the sum of actual tCW (or tWP) and tWRC (or tWR) .
*2: New write address is valid from either CE1 or WE is brought to High.
*3: Maximum value is applicable if CE1 is kept at Low and both WE and OE are kept at High.
*4: The tOEH is specified from end of tWC (Min) and is a reference value when access time is determined by tOE.
If actual value is shorter than specified minimum value, tOE become longer by the amount of subtracting actual
value from specified minimum value.
*5: The tOEH[ABS] is the absolute minimum value if write cycle is terminated by WE and CE1 stays Low.
*6: tOHCL (Min) must be satisfied if read operation is not performed prior to write operation.
In case OE is disabled after tOHCL (Min) , WE Low must be asserted after tRC (Min) from CE1 Low.
In other words, read operation is initiated if tOHCL (Min) is not satisfied.
*7: Applicable if CE1 stays Low after read operation.
*8: tCW and tWP is applicable if write operation is initiated by CE1 and WE, respectively.
*9: tWRC and tWR is applicable if write operation is terminated by CE1 and WE, respectively.
The tWR (Min) can be ignored if CE1 is brought to High together or after WE is brought to High.
In such case, the tCP (Min) must be satisfied.
10
MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL
(3) Power Down Parameters
Parameter
Value
Symbol
Unit
Note
Min
10
Max
CE2 Low Setup Time for Power Down Entry
CE2 Low Hold Time after Power Down Entry
tCSP
ns
ns
tC2LP
100
CE1 High Hold Time following CE2 High
after Power Down Exit
tCHH
tCHS
350
10
µs
CE1 High Setup Time following CE2 High
after Power Down Exit
ns
(4) Other Timing Parameters
Parameter
Value
Symbol
Unit
Note
Min
Max
CE1 High to OE Invalid Time for Standby Entry
tCHOX
tCHWX
20
ns
CE1 High to WE Invalid Time for Standby Entry
CE2 Low Hold Time after Power-up
20
50
50
ns
µs
µs
*1
*2
*3
tC2LH
CE2 High Hold Time after Power-up
tC2HL
CE1 High Hold Time following CE2 High after
Power-up
tCHH
350
1
µs
*2
*4
Input Transition Time
tT
25
ns
*1: It may write some data into any address location if tCHWX is not satisfied.
*2: Must satisfy tCHH (Min) after tC2LH (Min) .
*3: Requires Power Down mode entry and exit after tC2HL.
*4: The Input Transition Time (tT) at AC testing is 5 ns as shown in below. If actual tT is longer than 5 ns,
it may violate some timing parameters of AC specification.
(5) AC Test Conditions
Parameter
Symbol
Conditions
Measured Value
Unit
V
Note
VDD = 3.1 V to 3.5 V
VDD = 2.7 V to 3.1 V
VDD = 2.3 V to 2.7 V
VDD = 3.1 V to 3.5 V
VDD = 2.7 V to 3.1 V
VDD = 2.3 V to 2.7 V
VDD = 3.1 V to 3.5 V
VDD = 2.7 V to 3.1 V
VDD = 2.3 V to 2.7 V
Between VIL and VIH
2.6
2.3
2.0
0.5
0.5
0.4
1.5
1.3
1.1
5
Input High Level
VIH
V
V
V
Input Low Level
VIL
V
V
V
Input Timing Measurement Level
Input Transition Time
VREF
tT
V
V
ns
11
MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL
■ TIMING DIAGRAM
1. READ Timing #1 (OE Control Access)
tRC
tRC
Address
CE1
Address Valid
tCE
Address Valid
tOHAH
tASO
tOHAH
tOLCH
tCLOL
tOE
tOP
tOE
OE
tOHZ
tOH
tOHZ
tASO
tOLZ
tOH
tOLZ
DQ
(Output)
Valid Data Output
Valid Data Output
Note : CE2 and WE must be High for entire read cycle.
2. READ Timing #2 (CE1 Control Access)
tRC
tRC
Address
CE1
Address Valid
tCE
Address Valid
tCE
tASC
tCHAH
tASC
tCHAH
tCHZ
tOLCH
tCP
tCHZ
tOE
OE
tOH
tCLZ
tCLZ
tOH
DQ
(Output)
Valid Data Output
Valid Data Output
Note : CE2 and WE must be High for entire read cycle.
12
MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL
3. READ Timing #3 (Address Access after OE Control Access)
tRC
tRC
Address
(A19 - A2)
Address Valid
Address Valid (No change)
Address
(A1, A0)
Address Valid
tAA
Address Valid
tOHAH
tASO
tOLAH
tAX
CE1
OE
tOHZ
tOE
tOH
tOH
tOLZ
DQ
(Output)
Valid Data Output
Valid Data Output
Note : CE2 and WE must be High for entire read cycle.
4. READ Timing #4 (Address Access after CE1 Control Access)
tRC
tRC
Address
(A19-A2)
Address Valid
Address Valid (No change)
Address
(A1, A0)
Address Valid
tAA
Address Valid
tCHAH
tCLAH
tASC
tAX
CE1
OE
tCHZ
tCE
tOH
tOH
tCLZ
DQ
(Output)
Valid Data Output
Valid Data Output
Note : CE2 and WE must be High for entire read cycle.
13
MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL
5. WRITE Timing #1 (CE1 Control)
tWC
Address
CE1
Address Valid
tAH
tAS
tAS
tCW
tWRC
tWS
tWH
tBH
tWS
WE
tBS
tBS
UB, LB
tOHCL
OE
tDS
tDH
DQ
(Input)
Valid Data Input
Note : CE2 must be High for write cycle.
14
MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL
6. WRITE Timing #2-1 (WE Control, Single Write Operation)
tWC
Address Valid
tAH
Address
CE1
tOHAH
tAS
tAS
tCH
tCP
tOHCL
tCS
tWP
tWR
WE
tBS
tBH
UB, LB
OE
tOES
tOHZ
tDS
tDH
DQ
(Input)
Valid Data Input
Note : CE2 must be High for write cycle.
15
MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL
7. WRITE Timing #2 (WE Control, Continuous Write Operation)
tWC
Address Valid
tAH
Address
CE1
tOHAH
tAS
tAS
tOHCL
tCS
tWP
tWR
WE
tBH
tBS
tBS
UB, LB
OE
tOES
tOHZ
tDS
tDH
DQ
(Input)
Valid Data Input
16
MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL
8. READ/WRITE Timing #1-1 (CE1 Control)
tWC
Write Address
tAH
Read Address
Address
CE1
tCHAH
tASC
tAS
tCP
tWRC
tWS
tCW
tWH
tWS
tWH
tBH
WE
tBS
UB, LB
tCLOL
tOHCL
OE
DQ
tOLZ
tCLZ
tCHZ
tOH
tDS
tDH
Read Data Output
Write Data Input
Note : Write address is valid from either CE1 or WE of last falling edge.
17
MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL
9. READ/WRITE Timing #1-2 (CE1 Control)
tRC
Address
CE1
Read Address
Write Address
tASC
tCHAH
tAS
tWRC
tWRC (Min)
tCP
tWH
tWH
tWS
tWS
WE
tBS
tBH
tCE
UB, LB
tOHCL
tCHZ
tOEH
OE
DQ
tDH
tCLZ
tOH
Write Data Input
Read Data Output
Note : The tOEH is specified from the time satisfied both tWRC and tWR (Min) .
18
MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL
10. READ (OE Control) /WRITE (WE Control) Timing #2-1
tWC
Write Address
tAH
Read Address
Address
CE1
tOHAH
tAS
tASO
Low
tWR
tWP
WE
tBS
tBH
UB, LB
tOEH
tOES
tOHZ
OE
DQ
tOH
tDS
tDH
tOLZ
Read Data Output
Write Data Input
Note : CE1 can be tied to Low for WE and OE controlled operation.
When CE1 is tied to Low, output is exclusively controlled by OE.
19
MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL
11. READ (OE Control) /WRITE (WE Control) Timing #2-2
tRC
Address
CE1
Read Address Valid
Write Address
tOHAH
tAS
tASO
Low
tWR
WE
tBH
tBS
UB, LB
tOES
tOHZ
tOEH
tOE
OE
DQ
tDH
tOLZ
tOH
Write Data Input
Read Data Output
Note : CE1 can be tied to Low for WE and OE controlled operation.
When CE1 is tied to Low, output is exclusively controlled by OE.
20
MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL
12. POWER DOWN Timing
CE1
tCHS
CE2
tCSP
tC2LP
tCHH
High-Z
DQ
Power Down Entry
Power Down Mode
Power Down Exit
13. Standby Entry Timing after Read or Write
CE1
tCHOX
tCHWX
OE
WE
Active (Read)
Standby
Active (Write)
Standby
Note : Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied,
it takes tRC (Min) period from either last address transition of A0 and A1, or CE1 Low to High transition.
14. POWER-UP Timing 1
CE1
tCHS
tC2LH
tCHH
CE2
VDD
VDD Min
0 V
Note : It is recommended to keep CE2 at Low during VDD power-up.
The tC2LH specifies after VDD reaches specified minimum level.
21
MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL
15. POWER-UP Timing 2
CE1
tCHS
tCHH
tC2HL
tC2HL
tCSP
tC2LP
CE2
VDD
VDD Min
0 V
Note : The tC2HL specifies from CE2 Low to High transition after VDD reaches specified minimum level.
CE1 must be brought to High prior to or together with CE2 Low to High transition.
22
MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL
■ DATA RETENTION
1. Low VDD Characteristics
Value
Parameter
Symbol
Test Conditions
Unit
Min
Max
VDD Data Retention Supply
Voltage
CE1 = CE2 ≥ VDD − 0.2 V or,
CE1 = CE2 = VIH,
VDR
2.1
3.5
V
5
VDD = VDD (23) ,
L Version
IDR
VIN = VIH (23) or VIL
CE1 = CE2 = VIH (23) , IOUT = 0 mA
1.5
1
mA
LL Version
VDD Data Retention
Supply Current
200
100
70
VDD = VDD (23) ,
VIN ≤ 0.2 V or VIN ≥ VDD − 0.2 V,
CE1 = CE2 ≥ VDD − 0.2 V, IOUT = 0 mA
L Version
IDR1
µA
LL Version
Data Retention Setup Time
Data Retention Recovery Time
VDD Voltage Transition Time
tDRS
VDD = VDD (27) at data retention entry
VDD = VDD (27) after data retention
0
ns
ns
tDRR
90
0.5
∆V/∆t
V/µs
2. Data Retention Timing
tDRS
tDRR
3.5 V
2.7 V
VDD
∆V/∆t
∆V/∆t
CE2
CE1
2.1 V
CE1 = CE2 ≥ VDD - 0.2 V or
VIH (23) Min
0.4 V
VSS
Data Retention Mode
Data bus must be in High-Z at data retention entry.
23
MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL
■ ORDERING INFORMATION
Part Number
Package
48-ball plastic FBGA 0.8 mm pitch tCE = 80 ns Max, IDDS1 = 200 µA Max
(BGA-48P-M16) Flash Compatible Package
48-ball plastic FBGA 0.8 mm pitch tCE = 80 ns Max, IDDS1 = 100 µA Max
Remarks
MB82D01171A-80PBT
MB82D01171A-80LPBT
MB82D01171A-80LLPBT
MB82D01171A-85PBT
MB82D01171A-85LPBT
MB82D01171A-85LLPBT
MB82D01171A-90PBT
MB82D01171A-90LPBT
MB82D01171A-90LLPBT
MB82D01171A-80PBN
MB82D01171A-80LPBN
MB82D01171A-80LLPBN
MB82D01171A-85PBN
MB82D01171A-85LPBN
MB82D01171A-85LLPBN
MB82D01171A-90PBN
MB82D01171A-90LPBN
MB82D01171A-90LLPBN
(BGA-48P-M16)
Flash Compatible Package
48-ball plastic FBGA 0.8 mm pitch
(BGA-48P-M16)
tCE = 80 ns Max, IDDS1 = 70 µA Max
Flash Compatible Package
48-ball plastic FBGA 0.8 mm pitch tCE = 85 ns Max, IDDS1 = 200 µA Max
(BGA-48P-M16) Flash Compatible Package
48-ball plastic FBGA 0.8 mm pitch tCE = 85 ns Max, IDDS1 = 100 µA Max
(BGA-48P-M16)
Flash Compatible Package
48-ball plastic FBGA 0.8 mm pitch
(BGA-48P-M16)
tCE = 85 ns Max, IDDS1 = 70 µA Max
Flash Compatible Package
48-ball plastic FBGA 0.8 mm pitch tCE = 90 ns Max, IDDS1 = 200 µA Max
(BGA-48P-M16) Flash Compatible Package
48-ball plastic FBGA 0.8 mm pitch tCE = 90 ns Max, IDDS1 = 100 µA Max
(BGA-48P-M16)
Flash Compatible Package
48-ball plastic FBGA 0.8 mm pitch
(BGA-48P-M16)
tCE = 90 ns Max, IDDS1 = 70 µA Max
Flash Compatible Package
48-ball plastic FBGA 0.75 mm pitch tCE = 80 ns Max, IDDS1 = 200 µA Max
(BGA-48P-M18) SRAM Compatible Package
48-ball plastic FBGA 0.75 mm pitch tCE = 80 ns Max, IDDS1 = 100 µA Max
(BGA-48P-M18) SRAM Compatible Package
48-ball plastic FBGA 0.75 mm pitch tCE = 80 ns Max, IDDS1 = 70 µA Max
(BGA-48P-M18) SRAM Compatible Package
48-ball plastic FBGA 0.75 mm pitch tCE = 85 ns Max, IDDS1 = 200 µA Max
(BGA-48P-M18) SRAM Compatible Package
48-ball plastic FBGA 0.75 mm pitch tCE = 85 ns Max, IDDS1 = 100 µA Max
(BGA-48P-M18) SRAM Compatible Package
48-ball plastic FBGA 0.75 mm pitch tCE = 85 ns Max, IDDS1 = 70 µA Max
(BGA-48P-M18) SRAM Compatible Package
48-ball plastic FBGA 0.75 mm pitch tCE = 90 ns Max, IDDS1 = 200 µA Max
(BGA-48P-M18) SRAM Compatible Package
48-ball plastic FBGA 0.75 mm pitch tCE = 90 ns Max, IDDS1 = 100 µA Max
(BGA-48P-M18) SRAM Compatible Package
48-ball plastic FBGA 0.75 mm pitch tCE = 90 ns Max, IDDS1 = 70 µA Max
(BGA-48P-M18) SRAM Compatible Package
24
MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL
■ PACKAGE DIMENSIONS
48-ball plastic FBGA
(BGA-48P-M16)
1.05 –+00..1105
.041 –+..000046
(Mounting height)
(Stand off)
9.00±0.10(.354±.004)
(5.60(.220))
0.36±0.10
(.014±.004)
0.80(.031)
TYP
6
5
4
3
2
1
6.00±0.10
(.236±.004)
(4.00(.157))
0.80(.031)
TYP
H
G
F
E
D
C
B
A
INDEX AREA
48-Ø0.45±0.10
(48-Ø.018±.004)
M
0.08(.003)
0.20(.008) S
S
0.10(.004)
C
2000 FUJITSU LIMITED B48016S-1c-1
Dimensions in mm (inches)
(Continued)
25
MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL
(Continued)
48-ball plastic FBGA
(BGA-48P-M18)
1.05 –+00..1105
(Mounting height)
.041 –+..000046
9.00±0.10(.354±.004)
(5.25(.207))
0.25±0.10
(.010±.004)
0.75(.030)
TYP
(Stand off)
6
5
4
6.00±0.10
(.236±.004)
(3.75(.148))
3
2
1
0.75(.030)
TYP
INDEX MARK
H
F
E
D
C
B
A
G
INDEX AREA
48-ø0.35±0.10
(48-ø.014±.004)
M
0.08(.003)
0.20(.008)
S
S
0.10(.004)
S
C
2001 FUJITSU LIMITED B48018S-c-1-1
Dimensions in mm (inches)
26
MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0112
FUJITSU LIMITED Printed in Japan
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