MB84VA2107_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-50109-1E

MCP (Multi-Chip Package) FLASH MEMORY & SRAM

CMOS

16M (×16) FLASH MEMORY &

1M (× 8) STATIC RAM

MB84VA2106^-10/MB84VA2107^-10

■ FEATURES

• Power supply voltage of 2.7 to 3.6 V

• High performance

100 ns maximum access time

• Operating Temperature

–20 to +85°C

— FLASH MEMORY

• Minimum 100,000 write/erase cycles

• Sector erase architecture

One 8 K word, two 4 K words, one 16 K word, and thirty one 32 K words.

Any combination of sectors can be concurrently erased. Also supports full chip erase.

• Boot Code Sector Architecture

MB84VA2106: Top sector

MB84VA2107: Bottom sector

• Embedded Erase^TMAlgorithms

Automatically pre-programs and erases the chip or any sector

• Embedded Program^TMAlgorithms

Automatically writes and verifies data at specified address

• Data Polling and Toggle Bit feature for detection of program or erase cycle completion

• Ready-Busy output (RY/BY)

Hardware method for detection of program or erase cycle completion

• Automatic sleep mode

When addresses remain stable, automatically switch themselves to low power mode.

• Low V^CCwrite inhibit ≤ 2.5 V

• Erase Suspend/Resume

Suspends the erase operation to allow a read in another sector within the same device

Please refer to "MBM29LV160T/B" data sheet in detailed function

— SRAM

• Power dissipation

Operating: 35 mA max.

Standby : 30 µA max.

• Power down features using CE1s and CE2s

• Data retention supply voltage: 2.0 V to 3.6 V

Embedded Erase^TMand Embedded Program^TMare trademarks of Advanced Micro Devices, Inc.

MB84VA2106^-10/MB84VA2107^-10

■ BLOCK DIAGRAM

V^CCf

V^SS

A⁰to A¹⁹

RY/BY

A⁰to A¹⁹

DQ⁸to DQ¹⁵

16 M bit

RESET

CEf

Flash Memory

DQ⁰to DQ⁷

V^CCs

V^SS

A⁰to A¹⁵

1 M bit

Static RAM

SA

WE

OE

CE1s

CE2s

■ EXAMPLE OF CONNECTION WITH CHIPSET

V^CC

A[1:20]

A0

A[0:20]

V^CCf

A[0:19]

SA

RESET

RY/BY

ROM_CS/

RAM_CS/

CEf

CE1s

Battery

Backup

Control

V^CCs

CE2s

BATTERY BACKUP

HWR/

LWR/

RD/

WE

OE

D[0:15]

DQ[0:15]

CHIPSET

MB84VA2106/7

2

MB84VA2106^-10/MB84VA2107^-10

■ PIN ASSIGNMENTS

(Top View)

A

B

C

D

E

F

G

H

6

5

4

3

2

1

CE1s

A¹⁰

V^SS

DQ⁵

DQ⁷

A⁸

DQ¹

DQ²

DQ⁴

A⁵

A¹

A²

A⁴

CE2s

RY/BY

A⁹

A¹⁴

A⁰

A³

A⁷

OE

A¹¹

DQ⁰

DQ⁸

CEf

V^SS

A⁶

A¹⁸

DQ¹²

V^CCf

DQ¹¹

RESET A¹⁵

DQ³

DQ¹⁰

DQ⁹

A¹²

A¹⁹

A¹³

A¹⁷

V^CCs

SA*

A¹⁶

DQ⁶

DQ¹³

DQ¹⁵/A^-1

DQ¹⁴

WE

*: A¹⁶for SRAM

Table 1 Pin Configuration

Function

Input/

Output

A⁰to A¹⁵

A¹⁶to A¹⁹

SA

Address Inputs (Common)

Address Input (Flash)

I

Address Input (SRAM)

Data Inputs/Outputs (Common)

Data Inputs/Outputs (Flash)

Chip Enable (Flash)

I

DQ⁰to DQ⁷

DQ⁸to DQ¹⁵

CEf

I/O

I

CE1s

Chip Enable (SRAM)

I

CE2s

Chip Enable (SRAM)

I

OE

Output Enable (Common)

Write Enable (Common)

Ready/Busy Outputs (Flash)

I

WE

I

RY/BY

RESET

N.C.

O

Hardware Reset Pin/Sector Protection Unlock (Flash)

No Internal Connection

I

—

V^SS

Device Ground (Common)

Power

V^CCf

Device Power Supply (Flash)

V^CCs

Device Power Supply (SRAM)

3

MB84VA2106^-10/MB84VA2107^-10

■ PRODUCT LINE UP

Flash Memory

SRAM

+0.6 V

Ordering Part No.

MB84VA2106-10/MB84VA2107-10

V^CC= 3.0 V

–0.3 V

Max. Address Access Time (ns)

Max. CE Access Time (ns)

Max. OE Access Time (ns)

100

40

100

50

■ BUS OPERATIONS

Table 2 User Bus Operations

Operation (1), (3)

Full Standby

CEf

CE1s CE2s

OE

WE

DQ⁰to DQ⁷DQ⁸to DQ¹⁵RESET

H

X

H

X

H

X

L

X

L

H

X

L

X

HIGH-Z

D^OUT

HIGH-Z

D^OUT

H

Output Disable

X

L

H

Read from Flash (2)

L

H

X

L

Write to Flash

L

H

L

D^IN

H

Read from SRAM

Write to SRAM

H

X

L

H

L

D^OUT

D^IN

HIGH-Z

H

L

X

H

X

Flash Hardware Reset

X

HIGH-Z

L

Legend: L = V^IL, H = V^IH, X = V^ILor V^IH. See DC Characteristics for voltage levels.

Notes: 1. Other operations except for indicated this column are inhibited.

2. WE can be V^ILif OE is V^IL, OE at V^IHinitiates the write operations.

3. Do not apply CEf = V^IL, CE1s = V^ILand CE2s = V^IHat a time.

4

MB84VA2106^-10/MB84VA2107^-10

■ FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY

•One 8 K word, two 4 K words, one 16 K word, and thirty one 32 K words.

•Individual-sector, multiple-sector, or bulk-erase capability.

Sector Sector Size

Address Range

Sector Sector Size

Address Range

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

32K Words

00000H to 07FFFH

08000H to 0FFFFH

10000H to 17FFFH

18000H to 1FFFFH

20000H to 27FFFH

28000H to 2FFFFH

30000H to 37FFFH

38000H to 3FFFFH

40000H to 47FFFH

48000H to 4FFFFH

50000H to 57FFFH

58000H to 5FFFFH

60000H to 67FFFH

68000H to 6FFFFH

70000H to 77FFFH

78000H to 7FFFFH

80000H to 87FFFH

88000H to 8FFFFH

90000H to 97FFFH

98000H to 9FFFFH

A0000H to A7FFFH

A8000H to AFFFFH

B0000H to B7FFFH

B8000H to BFFFFH

C0000H to C7FFFH

C8000H to CFFFFH

D0000H to D7FFFH

D8000H to DFFFFH

E0000H to E7FFFH

E8000H to EFFFFH

F0000H to F7FFFH

F8000H to FBFFFH

FC000H to FCFFFH

FD000H to FDFFFH

FE000H to FFFFFH

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

8K Words

4K Words

00000H to 01FFFH

02000H to 02FFFH

03000H to 03FFFH

04000H to 07FFFH

08000H to 0FFFFH

10000H to 17FFFH

18000H to 1FFFFH

20000H to 27FFFH

28000H to 2FFFFH

30000H to 37FFFH

38000H to 3FFFFH

40000H to 47FFFH

48000H to 4FFFFH

50000H to 57FFFH

58000H to 5FFFFH

60000H to 67FFFH

68000H to 6FFFFH

70000H to 77FFFH

78000H to 7FFFFH

80000H to 87FFFH

88000H to 8FFFFH

90000H to 97FFFH

98000H to 9FFFFH

A0000H to A7FFFH

A8000H to AFFFFH

B0000H to B7FFFH

B8000H to BFFFFH

C0000H to C7FFFH

C8000H to CFFFFH

D0000H to D7FFFH

D8000H to DFFFFH

E0000H to E7FFFH

E8000H to EFFFFH

F0000H to F7FFFH

F8000H to FFFFFH

16K Words

32K Words

SA8

SA9

SA10 32K Words

SA11 32K Words

SA12 32K Words

SA13 32K Words

SA14 32K Words

SA15 32K Words

SA16 32K Words

SA17 32K Words

SA18 32K Words

SA19 32K Words

SA20 32K Words

SA21 32K Words

SA22 32K Words

SA23 32K Words

SA24 32K Words

SA25 32K Words

SA26 32K Words

SA27 32K Words

SA28 32K Words

SA29 32K Words

SA30 32K Words

SA31 16K Words

SA32 4K Words

SA33 4K Words

SA34 8K Words

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

MB84VA2106 Sector Architecture

MB84VA2107 Sector Architecture

5

MB84VA2106^-10/MB84VA2107^-10

Table 3 Sector Address Tables (MB84VA2106)

Sector

A¹⁹

A¹⁸

A¹⁷

A¹⁶

A¹⁵

A¹⁴

A¹³

A¹²

Address Range

Address

SA0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

X

0

X

0

00000H to 07FFFH

08000H to 0FFFFH

10000H to 17FFFH

18000H to 1FFFFH

20000H to 27FFFH

28000H to 2FFFFH

30000H to 37FFFH

38000H to 3FFFFH

40000H to 47FFFH

48000H to 4FFFFH

50000H to 57FFFH

58000H to 5FFFFH

60000H to 67FFFH

68000H to 6FFFFH

70000H to 77FFFH

78000H to 7FFFFH

80000H to 87FFFH

88000H to 8FFFFH

90000H to 97FFFH

98000H to 9FFFFH

A0000H to A7FFFH

A8000H to AFFFFH

B0000H to B7FFFH

B8000H to BFFFFH

C0000H to C7FFFH

C8000H to CFFFFH

D0000H to D7FFFH

D8000H to DFFFFH

E0000H to E7FFFH

E8000H to EFFFFH

F0000H to F7FFFH

F8000H to FBFFFH

FC000H to FCFFFH

FD000H to FDFFFH

FE000H to FFFFFH

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

1

0

1

X

6

MB84VA2106^-10/MB84VA2107^-10

Table 4 Sector Address Tables (MB84VA2107)

Sector

Address

A¹⁹

A¹⁸

A¹⁷

A¹⁶

A¹⁵

A¹⁴

A¹³

A¹²

Address Range

SA0

SA1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

00000H to 01FFFH

02000H to 02FFFH

03000H to 03FFFH

04000H to 07FFFH

08000H to 0FFFFH

10000H to 17FFFH

18000H to 1FFFFH

20000H to 27FFFH

28000H to 2FFFFH

30000H to 37FFFH

38000H to 3FFFFH

40000H to 47FFFH

48000H to 4FFFFH

50000H to 57FFFH

58000H to 5FFFFH

60000H to 67FFFH

68000H to 6FFFFH

70000H to 77FFFH

78000H to 7FFFFH

80000H to 87FFFH

88000H to 8FFFFH

90000H to 97FFFH

98000H to 9FFFFH

A0000H to A7FFFH

A8000H to 8FFFFH

B0000H to B7FFFH

B8000H to BFFFFH

C0000H to C7FFFH

C8000H to CFFFFH

D0000H to D7FFFH

D8000H to DFFFFH

E0000H to E7FFFH

E8000H to EFFFFH

F0000H to F7FFFH

F8000H to FFFFFH

SA2

0

1

SA3

1

0

X

SA4

X

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

7

MB84VA2106^-10/MB84VA2107^-10

Table 5. 1 Flash Memory Autoselect Codes

Type

A⁶

V^IL

A¹

V^IL

A⁰

V^IL

V^IH

Code (HEX)

04H

Manufacturer’s Code

Device Code

MB84VA2106

MB84VA2107

22C4H

2249H

Table 5. 2 Expanded Autoselect Code Table

Code DQ¹⁵DQ¹⁴DQ¹³DQ¹²DQ¹¹DQ¹⁰DQ⁹DQ⁸DQ⁷DQ⁶DQ⁵DQ⁴DQ³DQ²DQ¹DQ⁰

Type

04H

22C4H

2249H

0

1

0

1

0

1

0

1

0

1

0

1

Manufacturer’s Code

MB84VA2106

MB84VA2107

Device

Code

8

MB84VA2106^-10/MB84VA2107^-10

Table 6 Flash Memory Command Definitions

Fourth Bus

Read/Write

Cycle

First Bus

Second Bus

Write Cycle

Third Bus

Fifth Bus

Sixth Bus

Bus

Write

Cycles

Req’d

Write Cycle

Write Cycle Write Cycle

Command

Sequence

Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

Read/Reset

1

3

4

6

XXXH F0H

—

RA

—

RD

—

Read/Reset

Autoselect

Program

555H AAH 2AAH 55H 555H F0H

555H AAH 2AAH 55H 555H 90H

555H AAH 2AAH 55H 555H A0H

PA

PD

Chip Erase

Sector Erase

555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H

555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H

Erase can be suspended during sector erase with Addr. (“H” or “L”). Data (B0H)

Erase can be resumed after suspend with Addr. (“H” or “L”). Data (30H)

SA

30H

Sector Erase Suspend

Sector Erase Resume

Set to

Fast Mode

3

2

4

555H AAH 2AAH 55H 555H 20H

—

Fast Program

(Note)

XXXH A0H

PA

PD

—

Reset from Fast

Mode (Note)

XXXH 90H XXXH F0H

Extended Sector

Protect

XXXH 60H SPA 60H SPA 40H SPA SD

Address bits A¹¹to A²⁰= X = “H” or “L” for all address commands except for Program Address (PA) and Sector

Address (SA).

Bus operations are defined in Table 2.

Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.

RA =Address of the memory location to be read.

PA =Address of the memory location to be programmed. Addresses are latched on the falling edge of

the write pulse.

SA =Address of the sector to be erased. The combination of A²⁰, A¹⁹, A¹⁸, A¹⁷, A¹⁶, A¹⁵, A¹⁴, and A¹³will

uniquely select any sector.

RD =Data read from location RA during read operation.

PD =Data to be programmed at location PA.

SPA =Sector address to be protected. Set sector address (SA) and (A⁶, A¹, A⁰) = (0, 1, 0).

SD =Sector protection verify data. Output 01H at protected sector addresses and output 00H at unprotected

sector addresses.

Note:This command is valid while Fast Mode.

9

MB84VA2106^-10/MB84VA2107^-10

■ ABSOLUTE MAXIMUM RATINGS

Storage Temperature ..................................................................................................–55°C to +125°C

Ambient Temperature with Power Applied ..................................................................–25°C to +85°C

Voltage with Respect to Ground All pins (Note)..........................................................–0.3 V to V^CCf +0.5 V

–0.3 V to V^CCs +0.5 V

V^CCf/V^CCs Supply (Note) ..............................................................................................–0.3 V to +4.6 V

Note: Minimum DC voltage on input or I/O pins are –0.5 V. During voltage transitions, inputs may negative

overshoot V^SSto –2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins are V^CCf +0.5

V or V^CCs +0.5 V. During voltage transitions, outputs may positive overshoot to V^CC+2.0 V for periods of up

to 20 ns.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■ RECOMMENDED OPERATING RANGES

Commercial Devices

Ambient Temperature (T^A) .........................................................................–20°C to +85°C

V^CCf/V^CCs Supply Voltages.........................................................................+2.7 V to +3.6 V

Operating ranges define those limits between which the functionality of the device is guaranteed.

WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All

the device’s electrical characteristics are warranted when operated within these ranges.

Always use semiconductor devices within the recommended operating conditions. Operation outside

these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representative beforehand.

10

MB84VA2106^-10/MB84VA2107^-10

■ DC CHARACTERISTICS

Parameter

Parameter Description

Test Conditions

Min.

Typ.

Max. Unit

Symbol

I^LI

Input Leakage Current

Output Leakage Current

—

–1.0

—

+1.0

µA

I^LO

t^CYCLE= 10 MHz

35

—

Flash V^CCActive Current V^CCf = V^CCMax., CEf = V^IL

(Read)

I^CC1f

mA

OE = V^IH

—

t^CYCLE= 5 MHz

17

35

—

Flash V^CCActive Current

(Program/Erase)

I^CC2f

V^CCf = V^CCMax., CEf = V^IL, OE = V^IH

—

mA

t^CYCLE=10 MHz

—

40

12

35

8

mA

SRAM V^CCActive

Current

V^CCs = V^CCMax.,

I^CC1s

CE1s = V^IL, CE2s = V^IH

t^CYCLE= 1 MHz

t^CYCLE= 10 MHz

t^CYCLE= 1 MHz

CE1s = 0.2 V,

CE2s = V^CCs – 0.2 V,

WE = V^CCs – 0.2 V

SRAM V^CCActive

Current

I^CC2s

Flash V^CCStandby

Current

V^CCf = V^CCMax., CEf = V^CCf ± 0.3 V

RESET = V^CCf ± 0.3 V

I^SB1f

I^SB2f

I^SB1s

—

5

µA

Flash V^CCStandby

Current (RESET)

V^CCf = V^CCMax., RESET = V^SS± 0.3 V

CE1s = V^IHor CE2s = V^IL

SRAM V^CCStandby

Current

—

1

2

mA

µA

T^A= 25°C

V^CCs =

3.0 V

±10%

T^A= –20 to

+85°C

—

2

35

3

T^A= 25°C

V^CCs =

3.3 V

±0.3 V

CE1s = V^CC–

0.2 V or CE2s

= 0.2 V

T^A= –20 to

+85°C

SRAM V^CCStandby

Current

—

40

1

I^SB2s**

T^A= 25°C

T^A= –20 to

+40°C

V^CCs =

3.0 V

3

T^A= –20 to

+85°C

—

30

µA

V^IL

V^IH

Input Low Level

Input High Level

—

–0.3

2.2

—

0.6

V

V^CC+0.3*

Output Low Voltage

Level

I^OL= 2.1 mA,

V^OL

V^OH

V^LKO

—

V^CC– 0.5

2.3

—

0.4

—

V

V^CCf = V^CCs = V^CCMin.

Output High Voltage

Level

I^OH= –500 µA,

V^CCf = V^CCs = V^CCMin.

Flash Low V^CCLock-Out

Voltage

—

2.5

* : V^CCindicate lower of V^CCf or V^CCs

** :During standby mode with CE1s = V^CCS– 0.2 V, CE2s should be CE2s < 0.2V or CE2s > V^CCS– 0.2V

11

MB84VA2106^-10/MB84VA2107^-10

■ AC CHARACTERISTICS

• CE Timing

Parameter

Symbols

Description

Test Setup

-10

Unit

JEDEC Standard

—

t^CCR

CE Recover Time

—

Min.

0

ns

• Timing Diagram for alternating SRAM to Flash

CEf

t^CCR

CE1s

CE2s

t^CCR

12

MB84VA2106^-10/MB84VA2107^-10

• Read Only Operations Characteristics (Flash)

Parameter

Symbols

-10

(Note)

Test

Setup

Description

Unit

JEDEC Standard

Min.

Max.

t^AVAV

t^AVQV

t^RC

Read Cycle Time

—

100

—

ns

CEf = V^IL

OE = V^IL

t^ACC

Address to Output Delay

100

t^ELQV

t^GLQV

t^EHQZ

t^GHQZ

t^CEf

t^OE

t^DF

Chip Enable to Output Delay

Output Enable to Output Delay

Chip Enable to Output High-Z

Output Enable to Output High-Z

OE = V^IL

—

100

40

ns

—

30

Output Hold Time From Addresses,

CEf or OE, Whichever Occurs First

t^AXQX

—

t^OH

—

0

—

ns

µs

t^READY

RESET Pin Low to Read Mode

—

20

Note: Test Conditions–Output Load: 1 TTL gate and 30 pF

Input rise and fall times: 5 ns

Input pulse levels: 0.0 V to 3.0 V

Timing measurement reference level

Input: 1.5 V

Output: 1.5 V

13

MB84VA2106^-10/MB84VA2107^-10

• Read Cycle (Flash)

t^RC

Addresses Stable

ADDRESSES

t^ACC

CEf

t^OE

t^DF

OE

t^OEH

WE

t^CE

HIGH-Z

DQ

Output Valid

t^RC

ADDRESSES

Addresses Stable

t^ACC

t^RH

RESET

t^OH

HIGH-Z

DQ

Output Valid

14

MB84VA2106^-10/MB84VA2107^-10

• Erase/Program Operations (Flash)

Parameter Symbols

-10

Description

Unit

JEDEC

t^AVAV

t^AVWL

t^AVEL

Standard

Min. Typ. Max.

t^WC

t^AS

Write Cycle Time

100

0

—

16

1

—

15

—

100

90

ns

µs

sec

µs

ns

Address Setup Time (WE to Addr.)

Address Setup Time (CEf to Addr.)

Address Hold Time (WE to Addr.)

Address Hold Time (CEf to Addr.)

Data Setup Time

t^AS

0

t^WLAX

t^ELAX

t^AH

t^DS

t^DH

t^OES

50

0

t^DVWH

t^WHDX

—

Data Hold Time

Output Enable Setup Time

0

Read

0

—

t^OEH

Output Enable Hold Time

Toggle and Data Polling

10

0

t^GHEL

t^GHWL

t^WLEL

t^ELWL

t^EHWH

t^WHEH

t^WLWH

t^ELEH

t^GHEL

t^GHWL

t^WS

Read Recover Time Before Write (OE to CEf)

Read Recover Time Before Write (OE to WE)

WE Setup Time (CEf to WE)

CEf Setup Time (WE to CEf)

WE Hold Time (CEf to WE)

CEf Hold Time (WE to CEf)

Write Pulse Width

0

t^CS

0

t^WH

0

t^CH

0

t^WP

50

30

—

50

4

t^CP

CEf Pulse Width

t^WHWL

t^EHEL

t^WPH

t^CPH

t^WHWH1

Write Pulse Width High

CEf Pulse Width High

t^WHWH1

Programming Operation

t^WHWH2

Sector Erase Operation (Note 1)

—

t^VCS

t^VLHT

t^VIDR

t^RB

V^CCf Setup Time

Voltage Transition Time (Note 2)

Rise Time to V^ID(Note 2)

500

0

Recover Time from RY/BY

t^RP

RESET Pulse Width

500

200

—

t^RH

RESET Hold Time Before Read

Delay Time from Embedded Output Enable

Program/Erase Valid to RY/BY Delay

t^EOE

t^BUSY

Note : 1. This does not include the preprogramming time.

2. This timing is for Sector Protection Operation.

15

MB84VA2106^-10/MB84VA2107^-10

• Write Cycle (WE control) (Flash)

3rd Bus Cycle

Data Polling

555H

t^WC

PA

ADDRESSES

t^RC

t^AS

t^AH

CEf

t^CH

t^CS

t^CO

OE

t^GHWL

t^F^OE

t^WHWH1

t^WP

t^WPH

WE

t^OH

t^DS

t^DH

PD

D^OUT

A0H

DQ⁷

DQ

Notes: 1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at byte address.

3. DQ⁷is the output of the complement of the data written to the device.

4. D^OUTis the output of the data written to the device.

5. Figure indicates last two bus cycles out of four bus cycle sequence

16

MB84VA2106^-10/MB84VA2107^-10

• Write Cycle (CEf control) (Flash)

3rd Bus Cycle

Data Polling

PA

ADDRESSES

PA

555H

t^WC

t^AH

t^AS

WE

t^WS

t^WH

OE

t^GHEL

t^WHWH1

t^CP

t^CPH

CEf

DQ

t^DS

t^DH

PD

D^OUT

DQ⁷

A0H

Notes: 1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at byte address.

3. DQ⁷is the output of the complement of the data written to the device.

4. D^OUTis the output of the data written to the device.

5. Figure indicates last two bus cycles out of four bus cycle sequence.

17

MB84VA2106^-10/MB84VA2107^-10

• AC Waveforms Chip/Sector Erase Operations (Flash)

SA^*1

2AAH

555H

t^WC

2AAH

t^AS

555H

ADDRESSES

t^AH

CEf

t^CS

t^CH

OE

t^WP

t^WPH

t^GHWL

WE

t^DS

t^DH

30H for Sector Erase

10H/

30H

AAH

55H

80H

55H

DQ

V^CC

t^VCS

Notes: 1. SA is the sector address for Sector Erase. Addresses = 555H for Chip Erase.

18

MB84VA2106^-10/MB84VA2107^-10

• AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash)

CEf

t^CH

t^O^D

t^F^OE

OE

t^OEH

WE

t^CO

*

High-Z

DQ⁷=

Valid Data

Data In

DQ⁷

t^{WHWH1 or 2}

DQ

(DQ⁰to DQ⁶)

DQ⁰to DQ⁶

Valid Data

DQ⁰to DQ⁶= Invalid

t^EOE

*DQ⁷= Valid Data (The device has completed the Embedded operation.)

• AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash)

CEf

t^OEH

WE

t^OES

OE

*

DQ⁶=

Stop Toggling

DQ⁰to DQ⁷

Data Valid

DQ⁶=

Toggle

DQ⁶= Toggle

Data In

DQ⁶

t^EOE

*DQ⁶= Stops toggling. (The device has completed the Embedded operation.)

19

MB84VA2106^-10/MB84VA2107^-10

• RY/BY Timing Diagram during Write/Erase Operations (Flash)

CEf

The rising edge of the last WE signal

WE

Entire programming

or erase operations

RY/BY

t^BUSY

• RESET, RY/BY Timing Diagram (Flash)

WE

RESET

RY/BY

t^RP

t^RB

t^READY

• Temporary Sector Unprotection (Flash)

VCC

t

VIDR

t

VCS

t

VLHT

V

ID

3 V

RESET

CE

WE

t

VLHT

t

VLHT

Program or Erase Command Sequence

Unprotection period

RY/BY

20

MB84VA2106^-10/MB84VA2107^-10

• Extended Sector Protection (Flash)

V^CC

t^VCS

RESET

Add

t^VLHT

t^VIDR

SPAX

SPAY

A⁰

A¹

A⁶

CE

OE

TIME-OUT

WE

Data

60H

40H

01H

60H

t^OE

SPAX : Sector Address to be protected

SPAY : Next Sector Address to be protected

TIME-OUT : Time-Out window = 150 µs (min)

21

MB84VA2106^-10/MB84VA2107^-10

• Read Cycle (SRAM)

Parameter

Parameter Description

Symbol

Min.

Max.

Unit

t^RC

t^AA

Read Cycle Time

100

—

5

—

100

50

ns

Address Access Time

t^CO1

t^CO2

t^OE

Chip Enable (CE1s) Access Time

Chip Enable (CE2s) Access Time

Output Enable Access Time

t^COE

t^OEE

t^OD

Chip Enable (CE1s Low and CE2s High) to Output Active

Output Enable Low to Output Active

Chip Enable (CE1s High or CE2s Low) to Output High-Z

Output Enable High to Output High-Z

Output Data Hold Time

—

0

—

10

40

t^ODO

t^OH

40

—

• Read Cycle (Note 1) (SRAM)

t^RC

ADDRESSES

CE1s

t^AA

t^OH

t^CO1

t^COE

t^OD

t^CO2

CE2s

t^OD

t^OE

OE

DQ

t^ODO

t^OEE

t^COE

VALID DATA OUT

Note: 1. WE remains HIGH for the read cycle.

22

MB84VA2106^-10/MB84VA2107^-10

•

Write Cycle (SRAM)

Parameter

Symbol

Parameter Description

Write Cycle Time

Min.

Max.

Unit

t^WC

t^WP

t^CW

t^AS

100

60

80

0

—

40

—

ns

Write Pulse Width

Chip Enable to End of Write

Address Setup Time

Write Recovery Time

WE Low to Output High-Z

WE High to Output Active

Data Setup Time

t^WR

t^ODW

t^OEW

t^DS

0

—

0

60

0

t^DH

Data Hold Time

• Write Cycle (Note 4) (WE control) (SRAM)

t^WC

ADDRESSES

t^AS

t^WP

t^WR

WE

CE1s

CE2s

t^CW

t^ODW

t^OEW

D^OUT

Note 2

Note 5

Note 3

t^DS

t^DH

D^IN

VALID DATA IN

Note 5

Notes: 2.If CE1s goes LOW (or CE2s goes HIGH) coincident with or after WE goes LOW, the

output will remain at high impedance.

3.If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the

output will remain at high impedance.

4.If OE is HIGH during the write cycle, the outputs will remain at high impedance.

5.Because I/O signals may be in the output state at this Time, input signals of reverse

polarity must not be applied.

23

MB84VA2106^-10/MB84VA2107^-10

• Write Cycle (Note 4) (CE1s control) (SRAM)

t^WC

ADDRESSES

t^AS

t^WP

t^WR

WE

t^CW

CE1s

CE2s

t^CW

t^COE

t^ODW

D^OUT

t^DS

t^DH

D^IN

Note 5

VALID DATA IN

Notes: 2.If CE1s goes LOW (or CE2s goes HIGH) coincident with or after WE goes LOW, the

output will remain at high impedance.

3.If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the

output will remain at high impedance.

4.If OE is HIGH during the write cycle, the outputs will remain at high impedance.

5.Because I/O signals may be in the output state at this Time, input signals of reverse

polarity must not be applied.

24

MB84VA2106^-10/MB84VA2107^-10

• Write Cycle (Note 4) (CE2s Control) (SRAM)

t^WC

ADDRESSES

t^AS

t^WP

t^WR

WE

t^CW

CE1s

CE2s

t^CW

t^ODW

t^COE

D^OUT

t^DS

t^DH

D^IN

Note 5

VALID DATA IN

Note 5

Notes: 2.If CE1s goes LOW (or CE2s goes HIGH) coincident with or after WE goes LOW, the

output will remain at high impedance.

3.If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the

output will remain at high impedance.

4.If OE is HIGH during the write cycle, the outputs will remain at high impedance.

5.Because I/O signals may be in the output state at this Time, input signals of reverse

polarity must not be applied.

25

MB84VA2106^-10/MB84VA2107^-10

■ ERASE AND PROGRAMMING PERFORMANCE (Flash)

Limits

Parameter

Unit

Comment

Min.

Typ.

Max.

Excludes programming time

prior to erasure

Sector Erase Time

Programming Time

—

1

15

sec

Excludes system-level

overhead

—

16

5,200

µs

Excludes system-level

overhead

Chip Programming Time

Erase/Program Cycle

—

16.8

—

100

—

sec

100,000

cycles

■ DATA RETENTION CHARACTERISTICS (SRAM)

Parameter

Parameter Description

Symbol

Min.

Typ.

Max.

Unit

V^DH

Data Retention Supply Voltage

2.0

—

0

—

3.6

30*

40

—

V

V^DH= 3.0 V

V^DH= 3.6 V

µA

ns

I^DDS2

Standby Current

t^CDR

t^R

Chip Deselect to Data Retention Mode Time

Recovery Time

5

—

ms

* : 5 µA (Max.) at T^A= –20°C to +40°C

• CE1s Controlled Data Retention Mode (Note 1)

V^CCs

DATA RETENTION MODE

2.7 V

See Note 2

V^IH

V^CCS–0.2 V

CE1s

t^CDR

t^R

GND

26

MB84VA2106^-10/MB84VA2107^-10

• CE2s Controlled Data Retention Mode (Note 3)

V^CCs

DATA RETENTION MODE

2.7 V

V^IH

CE2s

t^CDR

t^R

V^IL

0.2 V

GND

Notes: 1. In CE1s controlled data retention mode, input level of CE2s should be fixed Vccs to Vccs-0.2V or Vss

to 0.2V during data retention mode. Other input and input/output pins can be used between -0.3V to

Vccs+0.3V.

2. When CE1s is operating at the V^IHmin. level (2.2 V), the standby current is given by I^SB1s during the

transition of V^CCs from 3.6 to 2.2 V.

3. In CE2s controlled data retention mode, input and input/output pins can be used between

-0.3V to Vccs+0.3V.

■ PIN CAPACITANCE

Parameter

Parameter Description

Test Setup

V^IN= 0

Typ.

Max.

Unit

Symbol

C^IN

Input Capacitance

T.B.D

pF

C^OUT

Output Capacitance

Control Pin Capacitance

V^OUT= 0

V^IN= 0

C^IN2

Note: Test conditions T^A= 25°C, f = 1.0 MHz

■ HANDLING OF PACKAGE

Please handle this package carefully since the sides of packages are right angle.

■ CAUTION

1)The high voltage (VID) can not apply to address pins and control pins except RESET. Therefore, it can not

use autoselect and sector protect function by applying the high voltage (VID) to specific pins.

2)For the sector protection, since the high voltage (VID) can be applied to the RESET, it can be protected the

sector useing "Extended sector protect" command.

27

MB84VA2106^-10/MB84VA2107^-10

■ PACKAGE

48-pin plastic FBGA

(BGA-48P-M10)

■ PACKAGE DIMENSIONS

48-pin plastic BGA

(BGA-48P-M10)

Note: The actual shape of coners may differ from the dimension.

14.00±0.15(.551±.006)

1.40±0.20

7.00±0.15(.276±.006)

(.055±.008)

0.30±0.10

(.012±.004)

10.00±0.15

(.394±.006)

5.00±0.15

(.197±.006)

1st PIN

INDEX

Ø0.40±0.10

(Ø.016±.004)

1.00±0.15

(.039±.006)

0.15(.006)

Dimension in mm (inches).

C

1998 FUJITSU LIMITED MCM-M002-3-2

28

MB84VA2106^-10/MB84VA2107^-10

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

KAWASAKI PLANT, 4-1-1, Kamikodanaka

Nakahara-ku, Kawasaki-shi

Kanagawa 211-8588, Japan

Tel: (044) 754-3763

The contents of this document are subject to change without

notice. Customers are advised to consult with FUJITSU sales

representatives before ordering.

Fax: (044) 754-3329

http://www.fujitsu.co.jp/

The information and circuit diagrams in this document presented

as examples of semiconductor device applications, and are not

intended to be incorporated in devices for actual use. Also,

FUJITSU is unable to assume responsibility for infringement of

any patent rights or other rights of third parties arising from the

use of this information or circuit diagrams.

North and South America

FUJITSU MICROELECTRONICS, INC.

Semiconductor Division

3545 North First Street

San Jose, CA 95134-1804, USA

Tel: (408) 922-9000

Fax: (408) 922-9179

FUJITSU semiconductor devices are intended for use in

standard applications (computers, office automation and other

office equipment, industrial, communications, and measurement

equipment, personal or household devices, etc.).

CAUTION:

Customers considering the use of our products in special

applications where failure or abnormal operation may directly

affect human lives or cause physical injury or property damage,

or where extremely high levels of reliability are demanded (such

as aerospace systems, atomic energy controls, sea floor

repeaters, vehicle operating controls, medical devices for life

support, etc.) are requested to consult with FUJITSU sales

representatives before such use. The company will not be

responsible for damages arising from such use without prior

approval.

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: (800) 866-8608

Fax: (408) 922-9179

http://www.fujitsumicro.com/

Europe

FUJITSU MIKROELEKTRONIK GmbH

Am Siebenstein 6-10

D-63303 Dreieich-Buchschlag

Germany

Tel: (06103) 690-0

Fax: (06103) 690-122

Any semiconductor devices have inherently a certain rate of

failure. You must protect against injury, damage or loss from

such failures by incorporating safety design measures into your

facility and equipment such as redundancy, fire protection, and

prevention of over-current levels and other abnormal operating

conditions.

http://www.fujitsu-ede.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE LTD

#05-08, 151 Lorong Chuan

New Tech Park

Singapore 556741

Tel: (65) 281-0770

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Control Law of Japan, the

prior authorization by Japanese government should be required

for export of those products from Japan.

Fax: (65) 281-0220

http://www.fmap.com.sg/

F9805

FUJITSU LIMITED Printed in Japan

29


型号：	MB84VA2107
厂家：	FUJITSU
描述：	16M (x16) FLASH MEMORY & 1M (x 8) STATIC RAM 16M （ X16 ）闪存和1M （ ×8 ）静态RAM 闪存
文件：	总29页 (文件大小：398K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB84VA2107 [FUJITSU]

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