MB84VB2000 [FUJITSU]
8M (x 8/x 16) FLASH MEMORY & 8M (x 8/x 16) FLASH MEMORY; 8M ( ×8 / ×16 )Flash存储器和8M ( ×8 / ×16 )Flash存储器型号: | MB84VB2000 |
厂家: | FUJITSU |
描述: | 8M (x 8/x 16) FLASH MEMORY & 8M (x 8/x 16) FLASH MEMORY |
文件: | 总28页 (文件大小:295K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-50102-2E
MCP (Multi-Chip Package) FLASH MEMORY
CMOS
8M (× 8/× 16) FLASH MEMORY &
8M (× 8/× 16) FLASH MEMORY
MB84VB2000-10/MB84VB2001-10
■ FEATURES
• Contain 2 chips of MBM29LV800A, and each chip have separate CE.
• Power supply voltage of 2.7 to 3.6 V
• High performance
100 ns maximum access time
• Operating Temperature
–40 to +85°C
• Minimum 100,000 write/erase cycles
• Sector erase architecture
One 16 K byte, two 8 K bytes, one 32 K byte, and fifteen 64 K bytes × 2 chips
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
MB84VB2000: Top sector
MB84VB2001: Bottom sector
• Embedded EraseTM Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
When addresses remain stable, automatically switch themselves to low power mode.
• Low VCC write inhibit ≤ 2.5 V
• Erase Suspend/Resume
Suspends the erase operation to allow a read data in another sector within the same device
• Please refer to "MBM29LV800TA/BA" data sheet in detailed function
Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
MB84VB2000-10/MB84VB2001-10
■ BLOCK DIAGRAM
VCC
VSS
RY/BY
A0 to A18
A-1
RESET
CE1
8 M bit
Flash Memory
BYTE
DQ0 to DQ15
VCC
VSS
8 M bit
Flash Memory
CE2
WE
OE
2
MB84VB2000-10/MB84VB2001-10
■ CONNECTION DIAGRAM
(Top View)
A
B
C
D
E
F
G
H
6
5
4
3
2
1
N.C.
A10
VSS
DQ5
DQ7
A8
DQ1
DQ2
DQ4
A5
A1
A2
A4
N.C.
RY/BY
A9
A14
A0
A3
A7
OE
A11
DQ0
DQ8
CE1
VSS
A6
A18
DQ12
VCC
DQ11
RESET A15
DQ3
DQ10
DQ9
A12
BYTE
A13
A17
N.C.
CE2
A16
DQ6
DQ13
DQ15/A-1
DQ14
WE
Table 1 MB84VB2000/MB84VB2001 Pin Configuration
Function
Input/
Output
Pin
A-1, A0 to A18
DQ0 to DQ15
CE1
Address Inputs (Common)
Data Inputs/Outputs (Common)
Chip Enable 1
I
I/O
I
CE2
Chip Enable 2
I
OE
Output Enable (Common)
I
WE
Write Enable (Common)
I
RY/BY
RESET
BYTE
N.C.
Ready/Busy Outputs (Common)
Hardware Reset Pin/Sector Protection Unlock (Common)
Selects 8-bit or 16-bit mode (Common)
No Internal Connection
O
I
I
—
VSS
Device Ground (Common)
Power
Power
VCC
Device Power Supply (Common)
3
MB84VB2000-10/MB84VB2001-10
■ PRODUCT LINE UP
Part No.
MB84VB2000/MB84VB2001
+0.6 V
–0.3 V
Ordering Part No.
-10
VCC = 3.0 V
Max. Address Access Time (ns)
Max. CE Access Time (ns)
Max. OE Access Time (ns)
100
100
40
■ LOGIC SYMBOL
Table 2 MB84VB2000/MB84VB2001 User Bus Operations (BYTE = VIH)
Operation (5)
CE1 CE2 OE WE
A0
A1
A6
A9
DQ0 to DQ15 RESET
H
L
L
H
L
Auto-Select Manufacture’s Code (1)
L
L
L
H
H
H
L
L
L
VID
Code
Code
DOUT
H
H
H
H
L
Auto-Select Device Code (1)
Read (3)
H
L
L
VID
A9
H
L
H
L
A0
A1
A6
H
H
X
L
Full Standby
H
X
H
L
X
H
X
H
X
X
X
X
X
X
X
X
HIGH-Z
HIGH-Z
H
H
Output Disable
Write (Program/Erase)
H
VID
L
L
A0
L
A1
H
A6
L
A9
VID
VID
DIN
X
H
H
H
H
L
H
L
Enable Sector Protection (2), (4)
Verify Sector Protection (2), (4)
H
L
H
L
H
L
H
L
Code
H
X
X
Temporary Sector Unprotection
Reset (Hardware)/Standby
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
VID
L
HIGH-Z
4
MB84VB2000-10/MB84VB2001-10
Table 3 MB84VB2000/MB84VB2001 User Bus Operations (BYTE = VIL)
DQ15/
A-1
DQ0 to
DQ7
Operation (5)
CE1 CE2 OE WE
A0
A1
A6
A9
RESET
H
L
L
H
L
Auto-Select Manufacture’s
Code (1)
L
L
L
H
H
H
L
L
L
L
L
VID
Code
Code
DOUT
H
H
L
Auto-Select Device Code (1)
Read (3)
H
L
L
VID
A9
H
H
H
L
H
L
A-1
A0
A1
A6
H
H
X
L
Full Standby
H
X
H
L
X
H
X
H
X
X
X
X
X
X
X
X
X
X
HIGH-Z
HIGH-Z
H
H
Output Disable
Write (Program/Erase)
H
VID
L
L
A-1
L
A0
L
A1
H
A6
L
A9
VID
VID
DIN
X
H
H
H
H
L
H
L
Enable Sector Protection
(2), (4)
H
L
H
L
Verify Sector Protection
(2), (4)
H
L
L
H
L
Code
H
Temporary Sector
Unprotection
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
VID
L
Reset (Hardware)/Standby
HIGH-Z
Legend: L = VIL, H = VIH, X = VIL or VIH,
= Pulse input. See DC Characteristics for voltage levels.
Notes: 1.Manufacturer and device codes may also be accessed via a command register write sequence. See
Table 7.
2.Refer to the section on Sector Protection.
3.WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
4.VCC = 3.3 V ±10%
5.Do not apply CE1 = CE2 = VIL at a time.
5
MB84VB2000-10/MB84VB2001-10
■ FLEXIBLE SECTOR-ERASE ARCHITECTURE
• One 16 K byte, two 8 K bytes, one 32 K byte, and fifteen 64 K bytes × 2.
• Individual-sector, multiple-sector, or bulk-erase capability.
(×8)
(×16)
(×8)
(×16)
FFFFFH 7FFFFH
FC000H 7E000H
FA000H 7D000H
F8000H 7C000H
F0000H 78000H
E0000H 70000H
D0000H 68000H
C0000H 60000H
B0000H 58000H
A0000H 50000H
90000H 48000H
80000H 40000H
70000H 38000H
60000H 30000H
50000H 28000H
40000H 20000H
30000H 18000H
20000H 10000H
10000H 08000H
00000H 00000H
FFFFFH 7FFFFH
16K byte/8K word
8K byte/4K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
32K byte/16K word
8K byte/4K word
F0000H
78000H
E0000H 70000H
D0000H 68000H
C0000H 60000H
B0000H 58000H
A0000H 50000H
8K byte/4K word
32K byte/16K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
90000H
80000H
70000H
60000H
50000H
40000H
30000H
20000H
10000H
08000H
06000H
04000H
00000H
48000H
40000H
38000H
30000H
28000H
20000H
18000H
10000H
08000H
04000H
03000H
02000H
00000H
8K byte/4K word
16K byte/8K word
MB84VB2000 Sector Architecture
MB84VB2001 Sector Architecture
6
MB84VB2000-10/MB84VB2001-10
■ FUNCTIONAL DESCRIPTION
Table 4 Sector Address Tables (MB84VB2000)
Sector
Address
A18
A17
A16
A15
A14
A13
A12
Address Range (×8) Address Range (×16)
SA0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
00000H to 0FFFFH
10000H to 1FFFFH
20000H to 2FFFFH
30000H to 3FFFFH
40000H to 4FFFFH
50000H to 5FFFFH
60000H to 6FFFFH
70000H to 7FFFFH
80000H to 8FFFFH
90000H to 9FFFFH
A0000H to AFFFFH
B0000H to BFFFFH
C0000H to CFFFFH
D0000H to DFFFFH
E0000H to EFFFFH
F0000H to F7FFFH
F8000H to F9FFFH
FA000H to FBFFFH
FC000H to FFFFFH
00000H to 07FFFH
08000H to 0FFFFH
10000H to 17FFFH
18000H to 1FFFFH
20000H to 27FFFH
28000H to 2FFFFH
30000H to 37FFFH
38000H to 3FFFFH
40000H to 47FFFH
48000H to 4FFFFH
50000H to 57FFFH
58000H to 5FFFFH
60000H to 67FFFH
68000H to 6FFFFH
70000H to 77FFFH
78000H to 7BFFFH
7C000H to 7CFFFH
7D000H to 7DFFFH
7E000H to 7FFFFH
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
1
1
0
1
1
1
X
7
MB84VB2000-10/MB84VB2001-10
Table 5 Sector Address Tables (MB84VB2001)
Sector
A18
A17
A16
A15
A14
A13
A12
Address Range (×8) Address Range (×16)
Address
SA0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
X
0
00000H to 03FFFH
04000H to 05FFFH
06000H to 07FFFH
08000H to 0FFFFH
10000H to 1FFFFH
20000H to 2FFFFH
30000H to 3FFFFH
40000H to 4FFFFH
50000H to 5FFFFH
60000H to 6FFFFH
70000H to 7FFFFH
80000H to 8FFFFH
90000H to 9FFFFH
A0000H to AFFFFH
B0000H to BFFFFH
C0000H to CFFFFH
D0000H to DFFFFH
E0000H to EFFFFH
F0000H to FFFFFH
00000H to 01FFFH
02000H to 02FFFH
03000H to 03FFFH
04000H to 07FFFH
08000H to 0FFFFH
10000H to 17FFFH
18000H to 1FFFFH
20000H to 27FFFH
28000H to 2FFFFH
30000H to 37FFFH
38000H to 3FFFFH
40000H to 47FFFH
48000H to 4FFFFH
50000H to 57FFFH
58000H to 5FFFFH
60000H to 67FFFH
68000H to 6FFFFH
70000H to 77FFFH
78000H to 7FFFFH
SA1
SA2
0
1
1
SA3
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
8
MB84VB2000-10/MB84VB2001-10
Table 6.1 Flash Memory Autoselect Codes
*1
Type
Manufacture’s Code
A6
A1
A0
A-1
VIL
VIL
X
Code (HEX)
04H
VIL
VIL
VIL
Byte
Word
Byte
DAH
MB84VB2000
MB84VB2001
VIL
VIL
VIL
VIL
VIH
VIH
22DAH
5BH
Device Code
VIL
X
Word
225BH
*1: A-1 is for Byte mode.
Table 6.2 Expanded Autoselect Code Table
Code DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
Type
04H A-1/0
DAH A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
22DAH
5BH A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
225BH
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
1
1
Manufacture’s Code
(B)
(W)
(B)
MB84VB2000
0
0
1
0
0
0
1
0
Device
Code
MB84VB2001
0
0
1
0
0
0
1
0
(W)
(B): Byte mode
(W): Word mode
9
MB84VB2000-10/MB84VB2001-10
Table 7 Flash Memory Command Definitions
Fourth Bus
Read/Write
Cycle
Bus
Write
Cycles
Req’d
First Bus Second Bus Third Bus
Write Cycle Write Cycle Write Cycle
Fifth Bus
Write Cycle Write Cycle
Sixth Bus
Command
Sequence
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
Read/Reset
Read/Reset
1
XXXH F0H
—
—
—
—
—
—
—
—
—
—
555H
AAH
2AAH
555H
2AAH
555H
2AAH
555H
2AAH
555H
2AAH
555H
555H
AAAH
555H
AAAH
555H
AAAH
555H
AAAH
555H
AAAH
3
55H
F0H RA
90H
RD
—
—
—
—
AAAH
555H
AAH
Autoselect
Program
3
4
6
6
55H
55H
55H
55H
—
—
—
—
—
—
—
—
—
—
AAAH
555H
AAH
A0H PA
PD
AAAH
555H
AAH
555H
80H
2AAH
555H
2AAH
555H
555H
Chip Erase
Sector Erase
AAH
AAH
55H
55H
10H
30H
AAAH
AAAH
AAAH
555H
AAH
555H
80H
SA
AAAH
AAAH
Sector Erase Suspend
Sector Erase Resume
Erase can be suspended during sector erase with Addr. (“H” or “L”). Data (B0H)
Erase can be resumed after suspend with Addr. (“H” or “L”). Data (30H)
555H
AAAH
XXXH
XXXH
XXXH
XXXH
2AAH
555H
555H
Set to
Fast Mode
3
AAH
A0H
90H
55H
PD
20H
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AAAH
Fast Program
(Note)
2
PA
—
—
XXXH
XXXH
Reset from Fast
2
F0H
—
—
—
—
—
—
—
—
—
Mode (Note)
Extended
4
XXXH 60H SPA 60H SPA 40H SPA SD
Sector Protect
Address bits A11 to A17 = X = “H” or “L” for all address commands except or Program Address (PA) and Sector
Address (SA).
Bus operations are defined in Tables 2 and 3.
The system should generate the following address patterns:
Word Mode: 555H or 2AAH to addresses A0 to A10
Byte Mode: AAAH or 555H to addresses A-1 and A0 to A10
Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
RA =Address of the memory location to be read
PA =Address of the memory location to be programmed
Addresses are latched on the falling edge of the write pulse.
SA =Address of the sector to be erased. The combination of A18, A17, A16, A15, A14, A13, and A12 will
uniquely select any sector.
RD =Data read from location RA during read operation.
PD =Data to be programmed at location PA. Data is latched on the falling edge of write pulse.
SPA:Sector address to be protected. Set sector address (SA) and (A6, A1, A0) = (0, 1, 0).
SD:Sector protection verify data. Output 01H at protected sector addresses and output 00H at unprotected
sector addresses.
10
MB84VB2000-10/MB84VB2001-10
■ ABSOLUTE MAXIMUM RATINGS
Storage Temperature ..................................................................................................–55°C to +125°C
Ambient Temperature with Power Applied ..................................................................–25°C to +85°C
Voltage with Respect to Ground All pins (Note)..........................................................–0.3 V to VCC + 0.5 V
VCCf/VCCs Supply (Note) ..............................................................................................–0.3 V to +4.6 V
Note: Minimum DC voltage on input or I/O pins are –0.5 V. During voltage transitions, inputs may negative overshoot
VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins are VCCf + 0.5 V or VCCs
+ 0.5 V. During voltage transitions, outputs may positive overshoot to VCC + 2.0 V for periods of up to 20 ns.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING RANGES
Commercial Devices
Ambient Temperature (TA) .........................................................................–40°C to +85°C
VCC Supply Voltages..................................................................................+2.7 V to +3.6 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All
the device’s electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside
these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.
11
MB84VB2000-10/MB84VB2001-10
■ DC CHARACTERISTICS
Parameter
Symbol
Parameter Description
Test Conditions
Min.
Max.
Unit
ILI
Input Leakage Current
Output Leakage Current
VIN = VSS to VCC, VCC = VCC Max.
VOUT = VSS to VCC, VCC = VCC Max.
–1.0
–1.0
+1.0
+1.0
µA
µA
ILO
A9, OE, RESET Inputs Leakage VCC = VCC Max.
ILIT
—
—
70
µA
Current
A9, OE, RESET = 12.5 V
Byte
Word
Byte
22
25
12
15
35
CE = VIL, OE = VIH,
f = 10 MHz
mA
ICC1
VCC Active Current (Note 1, 5)
CE = VIL, OE = VIH,
f = 5 MHz
—
mA
Word
ICC2
ICC3
ICC4
VCC Active Current (Note 2, 5)
VCC Current (Standby) (Note 5)
CE = VIL, OE = VIH
—
—
mA
VCC = VCC Max., CE = VCC ± 0.3 V,
RESET = VCC ± 0.3 V
5
5
µA
VCC Current (Standby, Reset)
(Note 5)
VCC = VCC Max.,
RESET = VSS ± 0.3 V
—
—
µA
VCC Current
(Automatic Sleep Mode)
(Note 3, 5)
VCC = VCC Max., CE = VSS ± 0.3 V,
RESET = VCC ± 0.3 V
VIN = VCC ± 0.3 V or VSS ± 0.3 V
ICC5
5
µA
VIL
VIH
Input Low Level
Input High Level
—
—
–0.5
2.0
0.6
V
V
VCC + 0.3
Voltage for Autoselect and Sector
Protection (A9, OE, RESET)
(Note 4)
VID
—
11.5
12.5
V
VOL
VOH1
VOH2
VLKO
Output Low Voltage Level
Output High Voltage Level
Low VCC Lock-Out Voltage
IOL = 4.0 mA, VCC = VCC Min.
IOH = –2.0 mA, VCC = VCC Min.
IOH = –100 µA, VCC = VCC Min.
—
—
2.4
0.45
—
V
V
V
V
VCC – 0.4
2.3
—
2.5
Notes: 1.The ICC current listed includes both the DC operating current and the frequency dependent component
(at 10 MHz).
2.ICC active while Embedded Algorithm (program or erase) is in progress.
3. Automatic sleep mode enables the low power mode when address remain stable for 150 ns.
4. (VID – VCC) do not exceed 9 V.
5. Total power consumption is (condition of Flash 1) + (condition of Flash 2).
12
MB84VB2000-10/MB84VB2001-10
■ AC CHARACTERISTICS
• CE Timing
Parameter
Symbols
Description
Test Setup
-10
Unit
JEDEC Standard
—
tCCR
CE Recover Time
—
Min.
0
ns
• Read Only Operations Characteristics
Parameter
Symbols
-10
(Note)
Test
Setup
Description
Unit
JEDEC Standard
Min.
Max.
tAVAV
tAVQV
tRC
Read Cycle Time
—
100
—
—
ns
ns
CE = VIL
OE = VIL
tACC
Address to Output Delay
100
tELQV
tGLQV
tEHQZ
tGHQZ
tCE
tOE
tDF
tDF
Chip Enable to Output Delay
Output Enable to Output Delay
Chip Enable to Output High-Z
Output Enable to Output High-Z
OE = VIL
—
—
—
—
100
40
ns
ns
ns
ns
—
—
—
30
30
Output Hold Time from Addresses,
CE or OE, Whichever Occurs First
tAXQX
—
tOH
—
—
—
0
—
20
5
ns
µs
ns
tREADY
RESET Pin Low to Read Mode
—
—
tELFL
tELFH
—
CE or BYTE Switching Low or High
Note: Test Conditions–Output Load: 1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to 3.0 V
Timing measurement reference level
Input: 1.5 V
Output: 1.5 V
13
MB84VB2000-10/MB84VB2001-10
• Erase/Program Operations
Parameter Symbols
Description
-10
Unit
JEDEC
tAVAV
tAVWL
tAVEL
Standard
Min. Typ. Max.
tWC
tAS
Write Cycle Time
100
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
—
—
—
—
—
—
—
—
—
100
90
30
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
sec
µs
ns
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
Address Setup Time (WE to Addr.)
Address Setup Time (CE to Addr.)
Address Hold Time (WE to Addr.)
Address Hold Time (CE to Addr.)
Data Setup Time
tAS
0
tWLAX
tELAX
tAH
tAH
tDS
tDH
tOES
50
50
50
0
tDVWH
tWHDX
—
Data Hold Time
Output Enable Setup Time
0
Read
0
—
tOEH
Output Enable Hold Time
Toggle and Data Polling
10
0
tGHEL
tGHWL
tWLEL
tELWL
tEHWH
tWHEH
tWLWH
tELEH
tWHWL
tEHEL
tWHWH1
tWHWH2
—
tGHEL
tGHWL
tWS
Read Recover Time Before Write (OE to CE)
Read Recover Time Before Write (OE to WE)
WE Setup Time (CE to WE)
CE Setup Time (WE to CE)
WE Hold Time (CE to WE)
0
0
tCS
0
tWH
0
tCH
CE Hold Time (WE to CE)
0
tWP
Write Pulse Width
50
50
30
30
—
—
50
500
4
tCP
CE Pulse Width
tWPH
tCPH
tWHWH1
tWHWH2
tVCS
tVIDR
tVLHT
tWPP
tOESP
tCSP
tRB
Write Pulse Width High
CE Pulse Width High
Byte Programming Operation
Sector Erase Operation (Note 1)
VCC Setup Time
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Rise Time to VID (Note 2)
—
Voltage Transition Time (Note 2)
Write Pulse Width (Note 2)
—
100
4
—
OE Setup Time to WE Active (Note 2)
CE Setup Time to WE Active (Note 2)
Recover Time from RY/BY
—
4
—
0
—
tRP
RESET Pulse Width
500
200
—
—
—
30
—
tRH
RESET Hold Time Before Read
Delay Time from Embedded Output Enable
Program/Erase Valid to RY/BY Delay
BYTE Switching Low to Output High-Z
BYTE Switching High to Output Active
—
tEOE
tBUSY
tFLQZ
tFLQV
—
—
—
Notes: 1. This does not include the preprogramming time.
2. This timing is for Sector Protection operation.
14
MB84VB2000-10/MB84VB2001-10
■ SWITCHING WAVEFORMS
CE1
CE2
tCCR
tCCR
Figure 1 Timing Diagram for Alternating Flash to Flash
15
MB84VB2000-10/MB84VB2001-10
tRC
Addresses
Addresses Stable
tACC
CE
OE
tOE
tDF
tOEH
WE
DQ
tCE
HIGH-Z
HIGH-Z
Output Valid
tRC
Addresses
Addresses Stable
tACC
tRH
RESET
DQ
tOH
HIGH-Z
Output Valid
Figure 2 AC Waveforms for Read Operations
16
MB84VB2000-10/MB84VB2001-10
3rd Bus Cycle
555H
Data Polling
Addresses
PA
PA
t
WC
t
RC
t
AS
t
AH
CE
t
CH
t
CS
t
CE
OE
t
WP
t
WPH
t
OE
t
GHWL
t
WHWH1
WE
t
OH
t
DS
t
DH
A0H
PD
D
OUT
DOUT
DQ7
Data
Notes: 1.PA is address of the memory location to be programmed.
2.PD is data to be programmed at byte address.
3.DQ7 is the output of the complement of the data written to the device.
4.DOUT is the output of the data written to the device.
5.Figure indicates last two bus cycles out of four bus cycle sequence.
6.These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)
Figure 3 Alternate WE Controlled Program Operation Timings
17
MB84VB2000-10/MB84VB2001-10
Data Polling
3rd Bus Cycle
Addresses
PA
PA
555H
tWC
tAS
tAH
WE
tWS
tWH
OE
tGHEL
tCP
tCPH
tWHWH1
CE
tDS
tDH
DQ7
A0H
PD
DOUT
Data
Notes: 1.PA is address of the memory location to be programmed.
2.PD is data to be programmed at byte address.
3.DQ7 is the output of the complement of the data written to the device.
4.DOUT is the output of the data written to the device.
5.Figure indicates last two bus cycles out of four bus cycle sequence.
6.These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)
Figure 4 Alternate CE Controlled Program Operation Timings
18
MB84VB2000-10/MB84VB2001-10
2AAH
555H
555H
Addresses
555H
2AAH
SA*
tWC
tAS
tAH
CE
tCS
tCH
OE
tWP
tWPH
tGHWL
WE
tDS
tDH
10H/
30H
AAH
55H
80H
AAH
55H
Data
tVCS
VCC
* : SA is the sector address for Sector Erase. Addresses = 555H (Word), AAAH (Byte)
for Chip Erase.
Note: These waveforms are for the × 16 mode. (The addresses differ from × 8 mode.)
Figure 5 AC Waveforms Chip/Sector Erase Operations
19
MB84VB2000-10/MB84VB2001-10
CE
tCH
tOE
tDF
OE
tOEH
WE
tCE
*
High-Z
High-Z
DQ7 =
Data
Data
DQ7
DQ7
Valid Data
tWHWH1 or 2
DQ0 to DQ6
Valid Data
DQ0 to DQ6
DQ0 to DQ6 = Output Flag
tEOE
* : DQ7 = Valid Data (The device has completed the Embedded operation.)
Figure 6 AC Waveforms for Data Polling during Embedded Algorithm Operations
CE
t
OEH
WE
t
OES
OE
*
DQ
6
=
DQ
6
Data
DQ
6
= Toggle
DQ
6
= Toggle
Valid
Stop Toggling
t
OE
* : DQ6 stops toggling.(The device has completed the Embedded operation.)
Figure 7 AC Waveforms for Toggle Bit during Embedded Algorithm Operations
20
MB84VB2000-10/MB84VB2001-10
CE
TherisingedgeofthelastWEsignal
WE
Entire programming
or erase operations
RY/BY
tBUSY
Figure 8 RY/BY Timing Diagram during Write/Erase Operations
WE
RESET
tRP
tRB
RY/BY
tREADY
Figure 9 RESET, RY/BY Timing Diagram
21
MB84VB2000-10/MB84VB2001-10
CE
BYTE
Data Output
(DQ0 to DQ7)
Data Output
(DQ0 to DQ14)
DQ0 to DQ14
tELFH
tFHQV
DQ15
DQ15/A-1
A-1
Figure 10 Timing Diagram for Word Mode Configuration
CE
BYTE
tELFL
DQ0 to DQ14
Data Output
(DQ0 to DQ14)
Data Output
(DQ0 to DQ7)
DQ15/A-1
DQ15
A-1
tFLQZ
Figure 11 Timing Diagram for Byte Mode Configuration
The falling edge of the last WE signal
CE or WE
Input
Valid
BYTE
tSET
(tAS)
tHOLD
(tAH)
Figure 12 BYTE Timing Diagram for Write Operations
22
MB84VB2000-10/MB84VB2001-10
A
18, A17, A16
SAX
SAY
A
15, A14
13, A12
A
A
0
A
A
1
6
12 V
3 V
A
9
t
t
VLHT
12 V
3 V
OE
VLHT
t
VLHT
t
VLHT
t
WPP
WE
t
OESP
t
CSP
CE
Data
01H
t
VCS
t
OE
V
CC
SAX : Sector Address for initial sector
SAY : Sector Address for next sector
Note: A-1 is VIL on byte mode.
Figure 13 AC Waveforms for Sector Protection Timing Diagram
23
MB84VB2000-10/MB84VB2001-10
FAST MODE ALGORITHM
Start
RESET = VID
Wait to 4 µs
Device is Operating in
Temporary Sector
Unprotection Mode
No
Extended Sector
Protection Entry?
Yes
To Setup Sector Protection
Write XXXH/60H
PLSCNT = 1
To Sector Protection
Write SPA/60H
(A0 = VIL, A1 = VIH, A6 = VIL)
Time Out 150 µs
Increment PLSCNT
To Verify Sector Protection
Write SPA/40H
Setup Next Sector Address
(A0 = VIL, A1 = VIH, A6 = VIL)
Read from Sector Address
(A0 = VIL, A1 = VIH, A6 = VIL)
No
No
Data = 01H?
Yes
PLSCNT = 25?
Yes
Yes
Remove VID from RESET
Write Reset Command
Protection Other Sector
?
No
Remove VID from RESET
Write Reset Command
Device Failed
Sector Protection
Completed
Figure 14 Extended Sector Protection Algorithm
24
MB84VB2000-10/MB84VB2001-10
VCC
t
VIDR
t
VLHT
t
VCS
12 V
3 V
3 V
RESET
CE
WE
t
VLHT
t
VLHT
Program or Erase Command Sequence
RY/BY
Figure 15 Temporary Sector Unprotection Timing Diagram
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
WE
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase Suspend
Read
Erase
Erase
Complete
DQ
DQ
6
2
Toggle
DQ2 and DQ6
with OE
Note: DQ2 is read from the erase-suspended sector.
Figure 16 DQ2 vs DQ6
25
MB84VB2000-10/MB84VB2001-10
■ ERASE AND PROGRAMMING PERFORMANCE
Limits
Parameter
Unit
Comments
Min.
Typ.
Max.
Excludes programming time
prior to erasure
Sector Erase Time
—
1
15
sec
Word Programming Time
Byte Programming Time
—
—
16
8
5,200
3,600
µs
µs
Excludes system-level
overhead
Chip Programming Time
(1M Byte)
Excludes system-level
overhead
—
8.4
—
50
—
sec
Erase/Program Cycle
100,000
cycles
■ PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Test Setup
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0
VOUT = 0
VIN = 0
TBD
TBD
TBD
TBD
TBD
TBD
pF
pF
pF
COUT
Output Capacitance
Control Pin Capacitance
CIN2
Note: Test conditions TA = 25°C, f = 1.0 MHz
■ HANDLING OF PACKAGE
Please hadle this package carefully since the sides of package are right angle.
26
MB84VB2000-10/MB84VB2001-10
■ PACKAGE
48-pin plastic FBGA
(BGA-48P-M06)
■ PACKAGE DIMENSIONS
48-pin plastic BGA
(BGA-48P-M06)
Note: The actual shape of corners may differ from the dimension.
11.00±0.15(.433±.006)
1.40±0.20
7.00±0.15(.276±.006)
(.055±.008)
0.30±0.10
(.012±.004)
Ø0.40±0.10
(Ø.016±.004)
10.00±0.15
(.394±.006)
5.00±0.15
(.197±.006)
0.15(.006)
1st PIN
INDEX
INDEX
1.00±0.15
(.039±.006)
Dimension in mm (inches).
C
1998 FUJITSU LIMITED MCM-M001-2-3
27
MB84VB2000-10/MB84VB2001-10
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: (044) 754-3763
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The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
Fax: (044) 754-3329
http://www.fujitsu.co.jp/
The information and circuit diagrams in this document presented
as examples of semiconductor device applications, and are not
intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the
use of this information or circuit diagrams.
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Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
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F9804
FUJITSU LIMITED Printed in Japan
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