MB84VD21092EA-85-PTS [FUJITSU]
Memory Circuit, 1MX16, CMOS, PDSO56, PLASTIC, TSOP1-56;
| 型号： | MB84VD21092EA-85-PTS |
| 厂家： | 
FUJITSU |
| 描述： | Memory Circuit, 1MX16, CMOS, PDSO56, PLASTIC, TSOP1-56 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总55页 (文件大小：961K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-50216-1E
Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM
CMOS
16M (× 8/×16) FLASH MEMORY &
2M (× 8/×16) STATIC RAM
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
■ FEATURES
• Power Supply Voltage of 2.7 to 3.3 V
• High Performance
70 ns maximum access time
• Operating Temperature
–40 to +85°C
• Package 56-ball FBGA, 56-pin TSOP
■ PRODUCT LINE UP
Flash Memory
SRAM
-70
VCCf* = 3.0 V
-85
-70
-85
+0.3 V
+0.3 V
–0.3 V
Power Supply Voltage (V)
Max Address Access Time (ns)
Max CE Access Time (ns)
Max OE Access Time (ns)
VCCs* = 3.0 V
–0.3 V
70
85
85
35
70
70
35
85
85
45
70
30
* : Both VCCf and VCCs must be in recommend operation range when either part is being accessed.
■ PACKAGES
56-ball plastic FBGA
56-pin plastic TSOP
(BGA-56P-M01)
(FPT-56P-M04)
Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
FLASH MEMORY
• Simultaneous Read/Write Operations (dual bank)
Miltiple devices available with different bank sizes (refer to “■ PIN DESCRIPTION”)
Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
Zero latency between read and write operations
Read-while-erase
Read-while-program
• Minimum 100,000 Write/Erase Cycles
• Sector Erase Architecture
Eight 4 K words and thirty one 32 K words.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
MB84VD2108XEA: Top sector
MB84VD2109XEA: Bottom sector
• Embedded EraseTM Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready-Busy Output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic Sleep Mode
When addresses remain stable, automatically switch themselves to low power mode.
• Low VCC Write Inhibit ≤ 2.5 V
• Hidden ROM (Hi-ROM) Region
64K byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC Input Pin
At VIL, allows protection of boot sectors, regardless of sector protection/unprotection status
(MB84VD2108XEA:SA37,SA38 MB84VD2109XEA:SA0,SA1)
At VIH, allows removal of boot sector protection
At VACC, program time will reduse by 40%.
• Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
• Please refer to “MBM29DL16XTE/BE” datasheet in detailed function
SRAM
• Power Dissipation
Operating : 50 mA Max
Standby : 7 µA Max
• Power Down Features Using CE1s and CE2s
• Data Retention Supply Voltage: 1.5 V to 3.3 V
• CE1s and CE2s Chip Select
• Byte Data Control: LBs (DQ7-DQ0), UBs (DQ15-DQ8)
2
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
■ PIN ASSIGNMENTS
(TOP VIEW)
Marking side
B8
C8
D8
E8
F8
G8
A15
NC
NC
A16
CIOf
Vss
A7
B7
C7
D7
E7
SA
F7
G7
H7
A11
A12
A13
A14
DQ15/A-1
DQ7
DQ14
A6
A8
B6
C6
A9
D6
E6
F6
G6
H6
A19
A10
DQ6
DQ13
DQ12
DQ5
A5
C5
F5
G5
B5
H5
WE
CE2s
NC
DQ4
Vccs
CIOs
A4
B4
C4
F4
G4
H4
INDEX
LAND*
RESET
WP/ACC
RY/BY
DQ3
Vccf
DQ11
A3
B3
C3
D3
E3
F3
G3
H3
LBs
UBs
A18
A17
DQ1
DQ9
DQ10
DQ2
A2
A7
B2
A6
C2
A5
D2
A4
E2
F2
G2
H2
Vss
OE
DQ0
DQ8
B1
A3
C1
A2
D1
A1
E1
A0
F1
G1
CEf
CE1s
* : There is no solder ball. This land should be open electrically.
56-ball FBGA
(BGA-56P-M01)
(Continued)
3
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
(Continued)
(Top View)
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
A16
NC
A15
A14
A13
A12
A11
A10
A9
1
CIOf
VSS
SA
2
3
4
DQ15/A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
CIOs
VCCs
VCCf
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
5
6
7
8
A8
9
A19
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
WE
CE2S
RESET
WP/ACC
RY/BY
UBs
LBs
A18
A17
A7
A6
A5
A4
VSS
CE1s
CEf
A3
A2
A1
A0
NC
56-pin TSOP
(FPT-56P-M04)
4
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
■ PIN DESCRIPTION
Pin
A0 to A16
A–1, A17 to A19
SA
Function
Input/Output
Address Input (Common)
Address Input (Flash)
Address Input (SRAM)
Data Input/Output (Common)
Chip Enable (Flash)
I
I
I
DQ0 to DQ15
CEf
I/O
I
I
CE1s
Chip Enable (SRAM)
CE2s
Chip Enable (SRAM)
I
OE
Output Enable (Common)
Write Enable (Common)
I
WE
I
RY/BY
UBs
Ready/Busy Outputs (Flash) Open Drain Output
Upper Byte Control (SRAM)
O
I
LBs
Lower Byte Control (SRAM)
I
I/O Configuration (Flash)
CIOf = VCCf is Word mode (×16), CIOf = VSS is Byte mode (×8)
CIOf
I
I
I/O Configuration (SRAM)
CIOs = VCCs is Word mode (×16), CIOs = VSS is Byte mode (×8)
CIOs
RESET
WP/ACC
N.C.
Hardware Reset Pin/Sector Protection Unlock (Flash)
Write Protect / Acceleration (Flash)
No Internal Connection
I
I
—
VSS
Device Ground (Common)
Power
Power
Power
VCCf
Device Power Supply (Flash)
VCCs
Device Power Supply (SRAM)
5
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
■ BLOCK DIAGRAM
VCCf
VSS
A19 to A0
RY/BY
A19 to A0
A–1
WP/ACC
RESET
CEf
16 M bit
Flash Memory
DQ15/A–1 to DQ0
CIOf
DQ15/A–1 to DQ0
VCCs
VSS
A16 to A0
DQ15 to DQ0
2 M bit
SA
LBs
UBs
WE
Static RAM
OE
CE1s
CE2s
CIOs
6
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
■ DEVICE BUS OPERATIONS
User Bus Operations (Flash=Word mode; CIOf=VCCf, SRAM=Word mode; CIOs=VCCs)
WP/
LBs UBs
Operation *1, *3
ACC
CEf CE1s CE2s OE WE SA
DQ7 to DQ0 DQ15 to DQ8 RESET
6
6
*
*
5
*
H
X
X
L
Full Standby
H
H
L
X
X
X
X
X
High-Z
High-Z
H
H
X
X
H
X
H
X
X
X
X
H
X
H
High-Z
High-Z
High-Z
High-Z
L
H
Output Disable
H
X
H
X
H
X
X
L
X
L
X
L
H
L
H
H
L
X
X
X
X
X
X
X
X
X
High-Z
DOUT
DIN
High-Z
DOUT
DIN
Read from Flash *2
L
H
H
X
X
Write to Flash
L
H
L
H
L
L
L
DOUT
High-Z
DOUT
DOUT
DOUT
High-Z
DIN
Read from SRAM
Write to SRAM
H
L
H
L
H
X
H
X
H
L
L
DIN
H
X
L
H
X
X
X
L
X
X
H
L
L
High-Z
DIN
DIN
H
X
X
H
High-Z
Temporary Sector
Group Unprotec-
tion *4
X
X
X
X
X
X
VID
H
X
X
L
Flash Hardware
Reset
X
X
X
X
X
X
X
X
X
X
X
X
High-Z
X
High-Z
X
L
X
L
Boot Block Sector
Write Protection
X
X
X
Legend: L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels.
*1: Other operations except for indicated this column are prohibited.
*2: WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*3: Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH all at once.
*4: Also used for the extended sector group protections.
*5: WP/ACC = VIL : protection of boot sectors.
WP/ACC = VIH : removal of boot sectors protection.
WP/ACC = VACC (9V) : Program time will reduce by 40%.
*6: SA : Don’t care or Open.
7
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
User Bus Operations (Flash=Word mode; CIOf=VCCf, SRAM=Byte mode; CIOs=VSS)
LBs UBs
WP/
Operation *1, *3
ACC
CEf CE1s CE2s OE WE SA
DQ7 to DQ0 DQ15 to DQ8 RESET
6
6
*
*
5
*
H
X
X
L
Full Standby
H
H
L
X
X
X
X
X
High-Z
High-Z
H
H
X
X
H
X
H
X
X
X
X
H
X
H
High-Z
High-Z
High-Z
High-Z
L
H
Output Disable
H
X
H
X
H
X
L
X
L
H
L
H
H
L
X
X
X
X
X
X
X
X
X
High-Z
DOUT
DIN
High-Z
DOUT
DIN
X
L
Read from Flash *2
L
H
H
X
X
X
L
Write to Flash
L
H
Read from SRAM
Write to SRAM
H
H
H
H
L
H
L
SA
SA
X
X
X
X
DOUT
DIN
High-Z
High-Z
H
H
X
X
L
X
Temporary Sector
Group Unprotec-
tion *4
X
X
X
X
X
X
X
X
X
X
VID
X
H
X
X
L
Flash Hardware
Reset
X
X
X
X
X
X
X
X
X
X
X
X
High-Z
X
High-Z
X
L
X
L
Boot Block Sector
Write Protection
X
X
X
Legend: L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels.
*1: Other operations except for indicated this column are prohibited.
*2: WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*3: Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH all at once.
*4: Also used for the extended sector group protections.
*5: WP/ACC = VIL : protection of boot sectors.
WP/ACC = VIH : removal of boot sectors protection.
WP/ACC = VACC (9V) : Program time will reduce by 40%.
*6: LBS , UBS : Don’t care or Open.
8
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
User Bus Operations (Flash=Byte mode; CIOf=VSS, SRAM=Byte mode; CIOs=VSS)
WP/
LBs UBs
DQ7 to DQ14 to
Operation *1, *3
ACC
CEf CE1s CE2s DQ15/A–1 OE WE SA
RESET
6
6
*
*
DQ
0
DQ8
5
*
H
X
X
L
Full Standby
H
H
L
X
X
X
X
X
X
High-Z
High-Z
H
X
X
X
X
H
X
H
X
X
X
X
H
X
H
High-Z
High-Z
High-Z
High-Z
L
H
Output Disable
H
H
X
H
X
H
X
L
X
L
A–1
A–1
A–1
H
L
H
H
L
X
X
X
X
X
X
X
X
X
High-Z
DOUT
DIN
High-Z
X
L
Read from Flash *2
L
X
X
H
H
X
X
X
L
Write to Flash
L
H
Read from SRAM
Write to SRAM
H
H
H
H
X
X
L
H
L
SA
SA
X
X
X
X
DOUT
DIN
High-Z
High-Z
H
H
X
X
L
X
Temporary Sector
Group
X
X
X
X
X
X
X
X
X
X
X
VID
X
Unprotection *4
H
X
X
L
Flash Hardware
Reset
X
X
X
X
X
X
X
X
X
X
X
X
X
X
High-Z
X
High-Z
X
L
X
L
Boot Block Sector
Write Protection
X
X
X
Legend: L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels.
*1: Other operations except for indicated this column are prohibited.
*2: WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*3: Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH all at once.
*4: Also used for the extended sector group protections.
*5: WP/ACC = VIL : protection of boot sectors.
WP/ACC = VIH : removal of boot sectors protection.
WP/ACC = VACC (9V) : Program time will reduce by 40%.
*6: LBS , UBS : Don’t care or Open.
9
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
■ FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY
• Eight 4 K words, and thirty one 32 K words.
• Individual-sector, multiple-sector, or bulk-erase capability.
Word mode
Byte mode
0FFFFFh
0FF000h
0FE000h
0FD000h
0FC000h
0FB000h
0FA000h
0F9000h
0F8000h
0F0000h
0E8000h
0E0000h
0D8000h
0D0000h
0C8000h
0C0000h
0B8000h
0B0000h
0A8000h
0A0000h
098000h
090000h
088000h
080000h
078000h
070000h
068000h
060000h
058000h
050000h
048000h
040000h
038000h
030000h
028000h
020000h
018000h
010000h
008000h
000000h
1FFFFFh
1FE000h
1FC000h
1FA000h
1F8000h
1F6000h
1F4000h
1F2000h
1F0000h
1E0000h
1D0000h
1C0000h
1B0000h
1A0000h
190000h
180000h
170000h
160000h
150000h
140000h
130000h
120000h
110000h
100000h
0F0000h
0E0000h
0D0000h
0C0000h
0B0000h
0A0000h
090000h
080000h
070000h
060000h
050000h
040000h
030000h
020000h
010000h
000000h
SA38 : 8KB (4KW)
SA37 : 8KB (4KW)
SA36 : 8KB (4KW)
SA35 : 8KB (4KW)
SA34 : 8KB (4KW)
SA33 : 8KB (4KW)
SA32 : 8KB (4KW)
SA31 : 8KB (4KW)
SA30 : 64KB (32KW)
SA29 : 64KB (32KW)
SA28 : 64KB (32KW)
SA27 : 64KB (32KW)
SA26 : 64KB (32KW)
SA25 : 64KB (32KW)
SA24 : 64KB (32KW)
SA23 : 64KB (32KW)
SA22 : 64KB (32KW)
SA21 : 64KB (32KW)
SA20 : 64KB (32KW)
SA19 : 64KB (32KW)
SA18 : 64KB (32KW)
SA17 : 64KB (32KW)
SA16 : 64KB (32KW)
SA15 : 64KB (32KW)
SA14 : 64KB (32KW)
SA13 : 64KB (32KW)
SA12 : 64KB (32KW)
SA11 : 64KB (32KW)
SA10 : 64KB (32KW)
SA9 : 64KB (32KW)
SA8 : 64KB (32KW)
SA7 : 64KB (32KW)
SA6 : 64KB (32KW)
SA5 : 64KB (32KW)
SA4 : 64KB (32KW)
SA3 : 64KB (32KW)
SA2 : 64KB (32KW)
SA1 : 64KB (32KW)
SA0 : 64KB (32KW)
Bank 1
MB84VD21081EA
Bank 1
MB84VD21082EA
Bank 1
MB84VD21083EA
Bank 1
MB84VD21084EA
Bank 2
MB84VD21081EA
Bank 2
MB84VD21082EA
Bank 2
MB84VD21083EA
Bank 2
MB84VD21084EA
MB84VD2108XEA Sector Architecture (Top Boot Block)
(Continued)
10
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
(Continued)
Word mode Byte mode
0FFFFFh
0F8000h
0F0000h
0E8000h
0E0000h
0D8000h
0D0000h
0C8000h
0C0000h
0B8000h
0B0000h
0A8000h
0A0000h
098000h
090000h
088000h
080000h
078000h
070000h
068000h
060000h
058000h
050000h
048000h
040000h
038000h
030000h
028000h
020000h
018000h
010000h
008000h
007000h
006000h
005000h
004000h
003000h
002000h
001000h
000000h
1FFFFFh
1F0000h
1E0000h
1D0000h
1C0000h
1B0000h
1A0000h
190000h
180000h
170000h
160000h
150000h
140000h
130000h
120000h
110000h
100000h
0F0000h
0E0000h
0D0000h
0C0000h
0B0000h
0A0000h
090000h
080000h
070000h
060000h
050000h
040000h
030000h
020000h
010000h
00E000h
00C000h
00A000h
008000h
006000h
004000h
002000h
000000h
SA38 : 64KB (32KW)
SA37 : 64KB (32KW)
SA36 : 64KB (32KW)
SA35 : 64KB (32KW)
SA34 : 64KB (32KW)
SA33 : 64KB (32KW)
SA32 : 64KB (32KW)
SA31 : 64KB (32KW)
SA30 : 64KB (32KW)
SA29 : 64KB (32KW)
SA28 : 64KB (32KW)
SA27 : 64KB (32KW)
SA26 : 64KB (32KW)
SA25 : 64KB (32KW)
SA24 : 64KB (32KW)
SA23 : 64KB (32KW)
SA22 : 64KB (32KW)
SA21 : 64KB (32KW)
SA20 : 64KB (32KW)
SA19 : 64KB (32KW)
SA18 : 64KB (32KW)
SA17 : 64KB (32KW)
SA16 : 64KB (32KW)
SA15 : 64KB (32KW)
SA14 : 64KB (32KW)
SA13 : 64KB (32KW)
SA12 : 64KB (32KW)
SA11 : 64KB (32KW)
SA10 : 64KB (32KW)
SA9 : 64KB (32KW)
SA8 : 64KB (32KW)
SA7 : 8KB (4KW)
SA6 : 8KB (4KW)
SA5 : 8KB (4KW)
SA4 : 8KB (4KW)
SA3 : 8KB (4KW)
SA2 : 8KB (4KW)
SA1 : 8KB (4KW)
SA0 : 8KB (4KW)
Bank 2
MB84VD21094EA
Bank 2
MB84VD21093EA
Bank 2
MB84VD21092EA
Bank 2
MB84VD21091EA
Bank 1
MB84VD21094EA
Bank 1
MB84VD21093EA
Bank 1
MB84VD21092EA
Bank 1
MB84VD21091EA
MB84VD2109XEA Sector Architecture (Bottom Boot Block)
11
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
Sector Address Tables (MB84VD21081EA)
Sector Address
Address Range
(Byte mode)
Address Range
(Word mode)
Bank
Sector
Bank Address
A19
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A18
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A17
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
A16
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
A15
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
A14
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
A13
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
A12
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
SA0
SA1
000000h to 00FFFFh
010000h to 01FFFFh
020000h to 02FFFFh
030000h to 03FFFFh
040000h to 04FFFFh
050000h to 05FFFFh
060000h to 06FFFFh
070000h to 07FFFFh
080000h to 08FFFFh
090000h to 09FFFFh
0A0000h to 0AFFFFh
0B0000h to 0BFFFFh
0C0000h to 0CFFFFh
0D0000h to 0DFFFFh
0E0000h to 0EFFFFh
0F0000h to 0FFFFFh
100000h to 10FFFFh
110000h to 11FFFFh
120000h to 12FFFFh
130000h to 13FFFFh
140000h to 14FFFFh
150000h to 15FFFFh
160000h to 16FFFFh
170000h to 17FFFFh
180000h to 18FFFFh
190000h to 19FFFFh
1A0000h to 1AFFFFh
1B0000h to 1BFFFFh
1C0000h to 1CFFFFh
1D0000h to 1DFFFFh
1E0000h to 1EFFFFh
1F0000h to 1F1FFFh
1F2000h to 1F3FFFh
1F4000h to 1F5FFFh
1F6000h to 1F7FFFh
1F8000h to 1F9FFFh
1FA000h to 1FBFFFh
1FC000h to 1FDFFFh
1FE000h to 1FFFFFh
000000h to 007FFFh
008000h to 00FFFFh
010000h to 017FFFh
018000h to 01FFFFh
020000h to 027FFFh
028000h to 02FFFFh
030000h to 037FFFh
038000h to 03FFFFh
040000h to 047FFFh
048000h to 04FFFFh
050000h to 057FFFh
058000h to 05FFFFh
060000h to 067FFFh
068000h to 06FFFFh
070000h to 077FFFh
078000h to 07FFFFh
080000h to 087FFFh
088000h to 08FFFFh
090000h to 097FFFh
098000h to 09FFFFh
0A0000h to 0A7FFFh
0A8000h to 0AFFFFh
0B0000h to 0B7FFFh
0B8000h to 0BFFFFh
0C0000h to 0C7FFFh
0C8000h to 0CFFFFh
0D0000h to 0D7FFFh
0D8000h to 0DFFFFh
0E0000h to 0E7FFFh
0E8000h to 0EFFFFh
0F0000h to 0F7FFFh
0F8000h to 0F8FFFh
0F9000h to 0F9FFFh
0FA000h to 0FAFFFh
0FB000h to 0FBFFFh
0FC000h to 0FCFFFh
0FD000h to 0FDFFFh
0FE000h to 0FEFFFh
0FF000h to 0FFFFFh
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
Bank 2
0
0
1
0
1
0
0
1
1
Bank 1
1
0
0
1
0
1
1
1
0
1
1
1
12
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
Sector Address Tables (MB84VD21091EA)
Sector Address
Address Range
(BYTE mode)
Address Range
(WORD mode)
Bank
Sector
Bank Address
A19
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A18
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A17
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A16
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A15
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A14
0
A13
0
A12
0
SA0
SA1
000000h to 001FFFh
002000h to 003FFFh
004000h to 005FFFh
006000h to 007FFFh
008000h to 009FFFh
00A000h to 00BFFFh
00C000h to 00DFFFh
00E000h to 00FFFFh
010000h to 01FFFFh
020000h to 02FFFFh
030000h to 03FFFFh
040000h to 04FFFFh
050000h to 05FFFFh
060000h to 06FFFFh
070000h to 07FFFFh
080000h to 08FFFFh
090000h to 09FFFFh
0A0000h to 0AFFFFh
0B0000h to 0BFFFFh
0C0000h to 0CFFFFh
0D0000h to 0DFFFFh
0E0000h to 0EFFFFh
0F0000h to 0FFFFFh
100000h to 10FFFFh
110000h to 11FFFFh
120000h to 12FFFFh
130000h to 13FFFFh
140000h to 14FFFFh
150000h to 15FFFFh
160000h to 16FFFFh
170000h to 17FFFFh
180000h to 18FFFFh
190000h to 19FFFFh
1A0000h to 1AFFFFh
1B0000h to 1BFFFFh
1C0000h to 1CFFFFh
1D0000h to 1DFFFFh
1E0000h to 1EFFFFh
1F0000h to 1FFFFFh
000000h to 000FFFh
001000h to 001FFFh
002000h to 002FFFh
003000h to 003FFFh
004000h to 004FFFh
005000h to 005FFFh
006000h to 006FFFh
007000h to 007FFFh
008000h to 00FFFFh
010000h to 017FFFh
018000h to 01FFFFh
020000h to 027FFFh
028000h to 02FFFFh
030000h to 037FFFh
038000h to 03FFFFh
040000h to 047FFFh
048000h to 04FFFFh
050000h to 057FFFh
058000h to 05FFFFh
060000h to 067FFFh
068000h to 06FFFFh
070000h to 077FFFh
078000h to 07FFFFh
080000h to 087FFFh
088000h to 08FFFFh
090000h to 097FFFh
098000h to 09FFFFh
0A0000h to 0A7FFFh
0A8000h to 0AFFFFh
0B0000h to 0B7FFFh
0B8000h to 0BFFFFh
0C0000h to 0C7FFFh
0C8000h to 0CFFFFh
0D0000h to 0D7FFFh
0D8000h to 0DFFFFh
0E0000h to 0E7FFFh
0E8000h to 0EFFFFh
0F0000h to 0F7FFFh
0F8000h to 0FFFFFh
0
0
1
SA2
0
1
0
SA3
0
1
1
Bank 1
SA4
1
0
0
SA5
1
0
1
SA6
1
1
0
SA7
1
1
1
SA8
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
Bank 2
13
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
Sector Address Tables (MB84VD21082EA)
Sector Address
Address Range
(BYTE mode)
Address Range
(WORD mode)
Bank
Sector
Bank Address
A19
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A18
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A17
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
A16
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
A15
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
A14
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
A13
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
A12
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
SA0
SA1
000000h to 00FFFFh
010000h to 01FFFFh
020000h to 02FFFFh
030000h to 03FFFFh
040000h to 04FFFFh
050000h to 05FFFFh
060000h to 06FFFFh
070000h to 07FFFFh
080000h to 08FFFFh
090000h to 09FFFFh
0A0000h to 0AFFFFh
0B0000h to 0BFFFFh
0C0000h to 0CFFFFh
0D0000h to 0DFFFFh
0E0000h to 0EFFFFh
0F0000h to 0FFFFFh
100000h to 10FFFFh
110000h to 11FFFFh
120000h to 12FFFFh
130000h to 13FFFFh
140000h to 14FFFFh
150000h to 15FFFFh
160000h to 16FFFFh
170000h to 17FFFFh
180000h to 18FFFFh
190000h to 19FFFFh
1A0000h to 1AFFFFh
1B0000h to 1BFFFFh
1C0000h to 1CFFFFh
1D0000h to 1DFFFFh
1E0000h to 1EFFFFh
1F0000h to 1F1FFFh
1F2000h to 1F3FFFh
1F4000h to 1F5FFFh
1F6000h to 1F7FFFh
1F8000h to 1F9FFFh
1FA000h to 1FBFFFh
1FC000h to 1FDFFFh
1FE000h to 1FFFFFh
000000h to 007FFFh
008000h to 00FFFFh
010000h to 017FFFh
018000h to 01FFFFh
020000h to 027FFFh
028000h to 02FFFFh
030000h to 037FFFh
038000h to 03FFFFh
040000h to 047FFFh
048000h to 04FFFFh
050000h to 057FFFh
058000h to 05FFFFh
060000h to 067FFFh
068000h to 06FFFFh
070000h to 077FFFh
078000h to 07FFFFh
080000h to 087FFFh
088000h to 08FFFFh
090000h to 097FFFh
098000h to 09FFFFh
0A0000h to 0A7FFFh
0A8000h to 0AFFFFh
0B0000h to 0B7FFFh
0B8000h to 0BFFFFh
0C0000h to 0C7FFFh
0C8000h to 0CFFFFh
0D0000h to 0D7FFFh
0D8000h to 0DFFFFh
0E0000h to 0E7FFFh
0E8000h to 0EFFFFh
0F0000h to 0F7FFFh
0F8000h to 0F8FFFh
0F9000h to 0F9FFFh
0FA000h to 0FAFFFh
0FB000h to 0FBFFFh
0FC000h to 0FCFFFh
0FD000h to 0FDFFFh
0FE000h to 0FEFFFh
0FF000h to 0FFFFFh
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
Bank 2
0
0
1
0
1
0
Bank 1
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
14
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
Sector Address Tables (MB84VD21092EA)
Sector Address
Address Range
(BYTE mode)
Address Range
(WORD mode)
Bank
Sector
Bank Address
A19
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A18
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A17
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A16
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A15
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A14
0
A13
0
A12
0
SA0
SA1
000000h to 001FFFh
002000h to 003FFFh
004000h to 005FFFh
006000h to 007FFFh
008000h to 009FFFh
00A000h to 00BFFFh
00C000h to 00DFFFh
00E000h to 00FFFFh
010000h to 01FFFFh
020000h to 02FFFFh
030000h to 03FFFFh
040000h to 04FFFFh
050000h to 05FFFFh
060000h to 06FFFFh
070000h to 07FFFFh
080000h to 08FFFFh
090000h to 09FFFFh
0A0000h to 0AFFFFh
0B0000h to 0BFFFFh
0C0000h to 0CFFFFh
0D0000h to 0DFFFFh
0E0000h to 0EFFFFh
0F0000h to 0FFFFFh
100000h to 10FFFFh
110000h to 11FFFFh
120000h to 12FFFFh
130000h to 13FFFFh
140000h to 14FFFFh
150000h to 15FFFFh
160000h to 16FFFFh
170000h to 17FFFFh
180000h to 18FFFFh
190000h to 19FFFFh
1A0000h to 1AFFFFh
1B0000h to 1BFFFFh
1C0000h to 1CFFFFh
1D0000h to 1DFFFFh
1E0000h to 1EFFFFh
1F0000h to 1FFFFFh
000000h to 000FFFh
001000h to 001FFFh
002000h to 002FFFh
003000h to 003FFFh
004000h to 004FFFh
005000h to 005FFFh
006000h to 006FFFh
007000h to 007FFFh
008000h to 00FFFFh
010000h to 017FFFh
018000h to 01FFFFh
020000h to 027FFFh
028000h to 02FFFFh
030000h to 037FFFh
038000h to 03FFFFh
040000h to 047FFFh
048000h to 04FFFFh
050000h to 057FFFh
058000h to 05FFFFh
060000h to 067FFFh
068000h to 06FFFFh
070000h to 077FFFh
078000h to 07FFFFh
080000h to 087FFFh
088000h to 08FFFFh
090000h to 097FFFh
098000h to 09FFFFh
0A0000h to 0A7FFFh
0A8000h to 0AFFFFh
0B0000h to 0B7FFFh
0B8000h to 0BFFFFh
0C0000h to 0C7FFFh
0C8000h to 0CFFFFh
0D0000h to 0D7FFFh
0D8000h to 0DFFFFh
0E0000h to 0E7FFFh
0E8000h to 0EFFFFh
0F0000h to 0F7FFFh
0F8000h to 0FFFFFh
0
0
1
SA2
0
1
0
SA3
0
1
1
SA4
1
0
0
SA5
1
0
1
Bank 1
SA6
1
1
0
SA7
1
1
1
SA8
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
Bank 2
15
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
Sector Address Tables (MB84VD21083EA)
Sector Address
Address Range
(BYTE mode)
Address Range
(WORD mode)
Bank
Sector
Bank Address
A19
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A18
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A17
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
A16
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
A15
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
A14
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
A13
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
A12
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
SA0
SA1
000000h to 00FFFFh
010000h to 01FFFFh
020000h to 02FFFFh
030000h to 03FFFFh
040000h to 04FFFFh
050000h to 05FFFFh
060000h to 06FFFFh
070000h to 07FFFFh
080000h to 08FFFFh
090000h to 09FFFFh
0A0000h to 0AFFFFh
0B0000h to 0BFFFFh
0C0000h to 0CFFFFh
0D0000h to 0DFFFFh
0E0000h to 0EFFFFh
0F0000h to 0FFFFFh
100000h to 10FFFFh
110000h to 11FFFFh
120000h to 12FFFFh
130000h to 13FFFFh
140000h to 14FFFFh
150000h to 15FFFFh
160000h to 16FFFFh
170000h to 17FFFFh
180000h to 18FFFFh
190000h to 19FFFFh
1A0000h to 1AFFFFh
1B0000h to 1BFFFFh
1C0000h to 1CFFFFh
1D0000h to 1DFFFFh
1E0000h to 1EFFFFh
1F0000h to 1F1FFFh
1F2000h to 1F3FFFh
1F4000h to 1F5FFFh
1F6000h to 1F7FFFh
1F8000h to 1F9FFFh
1FA000h to 1FBFFFh
1FC000h to 1FDFFFh
1FE000h to 1FFFFFh
000000h to 007FFFh
008000h to 00FFFFh
010000h to 017FFFh
018000h to 01FFFFh
020000h to 027FFFh
028000h to 02FFFFh
030000h to 037FFFh
038000h to 03FFFFh
040000h to 047FFFh
048000h to 04FFFFh
050000h to 057FFFh
058000h to 05FFFFh
060000h to 067FFFh
068000h to 06FFFFh
070000h to 077FFFh
078000h to 07FFFFh
080000h to 087FFFh
088000h to 08FFFFh
090000h to 097FFFh
098000h to 09FFFFh
0A0000h to 0A7FFFh
0A8000h to 0AFFFFh
0B0000h to 0B7FFFh
0B8000h to 0BFFFFh
0C0000h to 0C7FFFh
0C8000h to 0CFFFFh
0D0000h to 0D7FFFh
0D8000h to 0DFFFFh
0E0000h to 0E7FFFh
0E8000h to 0EFFFFh
0F0000h to 0F7FFFh
0F8000h to 0F8FFFh
0F9000h to 0F9FFFh
0FA000h to 0FAFFFh
0FB000h to 0FBFFFh
0FC000h to 0FCFFFh
0FD000h to 0FDFFFh
0FE000h to 0FEFFFh
0FF000h to 0FFFFFh
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
Bank 2
Bank 1
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
16
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
Sector Address Tables (MB84VD21093EA)
Sector Address
Address Range
(BYTE mode)
Address Range
(WORD mode)
Bank
Sector
Bank Address
A19
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A18
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A17
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A16
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A15
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A14
0
A13
0
A12
0
SA0
SA1
000000h to 001FFFh
002000h to 003FFFh
004000h to 005FFFh
006000h to 007FFFh
008000h to 009FFFh
00A000h to 00BFFFh
00C000h to 00DFFFh
00E000h to 00FFFFh
010000h to 01FFFFh
020000h to 02FFFFh
030000h to 03FFFFh
040000h to 04FFFFh
050000h to 05FFFFh
060000h to 06FFFFh
070000h to 07FFFFh
080000h to 08FFFFh
090000h to 09FFFFh
0A0000h to 0AFFFFh
0B0000h to 0BFFFFh
0C0000h to 0CFFFFh
0D0000h to 0DFFFFh
0E0000h to 0EFFFFh
0F0000h to 0FFFFFh
100000h to 10FFFFh
110000h to 11FFFFh
120000h to 12FFFFh
130000h to 13FFFFh
140000h to 14FFFFh
150000h to 15FFFFh
160000h to 16FFFFh
170000h to 17FFFFh
180000h to 18FFFFh
190000h to 19FFFFh
1A0000h to 1AFFFFh
1B0000h to 1BFFFFh
1C0000h to 1CFFFFh
1D0000h to 1DFFFFh
1E0000h to 1EFFFFh
1F0000h to 1FFFFFh
000000h to 000FFFh
001000h to 001FFFh
002000h to 002FFFh
003000h to 003FFFh
004000h to 004FFFh
005000h to 005FFFh
006000h to 006FFFh
007000h to 007FFFh
008000h to 00FFFFh
010000h to 017FFFh
018000h to 01FFFFh
020000h to 027FFFh
028000h to 02FFFFh
030000h to 037FFFh
038000h to 03FFFFh
040000h to 047FFFh
048000h to 04FFFFh
050000h to 057FFFh
058000h to 05FFFFh
060000h to 067FFFh
068000h to 06FFFFh
070000h to 077FFFh
078000h to 07FFFFh
080000h to 087FFFh
088000h to 08FFFFh
090000h to 097FFFh
098000h to 09FFFFh
0A0000h to 0A7FFFh
0A8000h to 0AFFFFh
0B0000h to 0B7FFFh
0B8000h to 0BFFFFh
0C0000h to 0C7FFFh
0C8000h to 0CFFFFh
0D0000h to 0D7FFFh
0D8000h to 0DFFFFh
0E0000h to 0E7FFFh
0E8000h to 0EFFFFh
0F0000h to 0F7FFFh
0F8000h to 0FFFFFh
0
0
1
SA2
0
1
0
SA3
0
1
1
SA4
1
0
0
SA5
1
0
1
SA6
1
1
0
SA7
1
1
1
Bank 1
SA8
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
Bank 2
17
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
Sector Address Tables (MB84VD21084EA)
Sector Address
Address Range
(BYTE mode)
Address Range
(WORD mode)
Bank
Sector
Bank Address
A19
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A18
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A17
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
A16
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
A15
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
A14
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
A13
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
A12
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
SA0
SA1
000000h to 00FFFFh
010000h to 01FFFFh
020000h to 02FFFFh
030000h to 03FFFFh
040000h to 04FFFFh
050000h to 05FFFFh
060000h to 06FFFFh
070000h to 07FFFFh
080000h to 08FFFFh
090000h to 09FFFFh
0A0000h to 0AFFFFh
0B0000h to 0BFFFFh
0C0000h to 0CFFFFh
0D0000h to 0DFFFFh
0E0000h to 0EFFFFh
0F0000h to 0FFFFFh
100000h to 10FFFFh
110000h to 11FFFFh
120000h to 12FFFFh
130000h to 13FFFFh
140000h to 14FFFFh
150000h to 15FFFFh
160000h to 16FFFFh
170000h to 17FFFFh
180000h to 18FFFFh
190000h to 19FFFFh
1A0000h to 1AFFFFh
1B0000h to 1BFFFFh
1C0000h to 1CFFFFh
1D0000h to 1DFFFFh
1E0000h to 1EFFFFh
1F0000h to 1F1FFFh
1F2000h to 1F3FFFh
1F4000h to 1F5FFFh
1F6000h to 1F7FFFh
1F8000h to 1F9FFFh
1FA000h to 1FBFFFh
1FC000h to 1FDFFFh
1FE000h to 1FFFFFh
000000h to 007FFFh
008000h to 00FFFFh
010000h to 017FFFh
018000h to 01FFFFh
020000h to 027FFFh
028000h to 02FFFFh
030000h to 037FFFh
038000h to 03FFFFh
040000h to 047FFFh
048000h to 04FFFFh
050000h to 057FFFh
058000h to 05FFFFh
060000h to 067FFFh
068000h to 06FFFFh
070000h to 077FFFh
078000h to 07FFFFh
080000h to 087FFFh
088000h to 08FFFFh
090000h to 097FFFh
098000h to 09FFFFh
0A0000h to 0A7FFFh
0A8000h to 0AFFFFh
0B0000h to 0B7FFFh
0B8000h to 0BFFFFh
0C0000h to 0C7FFFh
0C8000h to 0CFFFFh
0D0000h to 0D7FFFh
0D8000h to 0DFFFFh
0E0000h to 0E7FFFh
0E8000h to 0EFFFFh
0F0000h to 0F7FFFh
0F8000h to 0F8FFFh
0F9000h to 0F9FFFh
0FA000h to 0FAFFFh
0FB000h to 0FBFFFh
0FC000h to 0FCFFFh
0FD000h to 0FDFFFh
0FE000h to 0FEFFFh
0FF000h to 0FFFFFh
SA2
SA3
SA4
SA5
SA6
SA7
Bank 2
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
Bank 1
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
18
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
Sector Address Tables (MB84VD21094EA)
Sector Address
Address Range
(BYTE mode)
Address Range
(WORD mode)
Bank
Sector
Bank Address
A19
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A18
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A17
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A16
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A15
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A14
0
A13
0
A12
0
SA0
SA1
000000h to 001FFFh
002000h to 003FFFh
004000h to 005FFFh
006000h to 007FFFh
008000h to 009FFFh
00A000h to 00BFFFh
00C000h to 00DFFFh
00E000h to 00FFFFh
010000h to 01FFFFh
020000h to 02FFFFh
030000h to 03FFFFh
040000h to 04FFFFh
050000h to 05FFFFh
060000h to 06FFFFh
070000h to 07FFFFh
080000h to 08FFFFh
090000h to 09FFFFh
0A0000h to 0AFFFFh
0B0000h to 0BFFFFh
0C0000h to 0CFFFFh
0D0000h to 0DFFFFh
0E0000h to 0EFFFFh
0F0000h to 0FFFFFh
100000h to 10FFFFh
110000h to 11FFFFh
120000h to 12FFFFh
130000h to 13FFFFh
140000h to 14FFFFh
150000h to 15FFFFh
160000h to 16FFFFh
170000h to 17FFFFh
180000h to 18FFFFh
190000h to 19FFFFh
1A0000h to 1AFFFFh
1B0000h to 1BFFFFh
1C0000h to 1CFFFFh
1D0000h to 1DFFFFh
1E0000h to 1EFFFFh
1F0000h to 1FFFFFh
000000h to 000FFFh
001000h to 001FFFh
002000h to 002FFFh
003000h to 003FFFh
004000h to 004FFFh
005000h to 005FFFh
006000h to 006FFFh
007000h to 007FFFh
008000h to 00FFFFh
010000h to 017FFFh
018000h to 01FFFFh
020000h to 027FFFh
028000h to 02FFFFh
030000h to 037FFFh
038000h to 03FFFFh
040000h to 047FFFh
048000h to 04FFFFh
050000h to 057FFFh
058000h to 05FFFFh
060000h to 067FFFh
068000h to 06FFFFh
070000h to 077FFFh
078000h to 07FFFFh
080000h to 087FFFh
088000h to 08FFFFh
090000h to 097FFFh
098000h to 09FFFFh
0A0000h to 0A7FFFh
0A8000h to 0AFFFFh
0B0000h to 0B7FFFh
0B8000h to 0BFFFFh
0C0000h to 0C7FFFh
0C8000h to 0CFFFFh
0D0000h to 0D7FFFh
0D8000h to 0DFFFFh
0E0000h to 0E7FFFh
0E8000h to 0EFFFFh
0F0000h to 0F7FFFh
0F8000h to 0FFFFFh
0
0
1
SA2
0
1
0
SA3
0
1
1
SA4
1
0
0
SA5
1
0
1
SA6
1
1
0
SA7
1
1
1
SA8
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
Bank 1
Bank 2
19
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
Sector Group Addresses (MB84VD2108XEA)
(Top Boot Block)
Sector Group
A19
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A18
0
0
0
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
A17
0
0
0
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
A16
0
A15
0
A14
X
X
X
X
X
X
X
X
X
X
X
X
X
0
A13
X
X
X
X
X
X
X
X
X
X
X
X
X
0
A12
X
X
X
X
X
X
X
X
X
X
X
X
X
0
Sectors
SGA0
SA0
0
1
SGA1
1
0
SA1 to SA3
1
1
SGA2
SGA3
SGA4
SGA5
SGA6
SGA7
X
X
X
X
X
X
0
X
X
X
X
X
X
0
SA4 to SA7
SA8 to SA11
SA12 to SA15
SA16 to SA19
SA20 to SA23
SA24 to SA27
SGA8
0
1
SA28 to SA30
1
0
SGA9
SGA10
SGA11
SGA12
SGA13
SGA14
SGA15
SGA16
1
1
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
20
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
Sector Group Addresses (MB84VD2109XEA)
(Bottom Boot Block)
Sector Group
SGA0
A19
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
A18
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
1
1
A17
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
1
1
A16
0
A15
0
A14
0
A13
0
A12
0
Sectors
SA0
SGA1
0
0
0
0
1
SA1
SGA2
0
0
0
1
0
SA2
SGA3
0
0
0
1
1
SA3
SGA4
0
0
1
0
0
SA4
SGA5
0
0
1
0
1
SA5
SGA6
0
0
1
1
0
SA6
SGA7
0
0
1
1
1
SA7
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SGA8
1
0
SA8 to SA10
1
1
SGA9
SGA10
SGA11
SGA12
SGA13
SGA14
X
X
X
X
X
X
0
X
X
X
X
X
X
0
SA11 to SA14
SA15 to SA18
SA19 to SA22
SA23 to SA26
SA27 to SA30
SA31 to SA34
SGA15
SGA16
0
1
SA35 to SA37
SA38
1
0
1
1
21
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
Flash Memory Autoselect Codes
A–1*1
VIL
VIL
X
Type
Manufacturer’s Code
A12 to A19
A6
A1
A0
Code (HEX)
04h
X
VIL
VIL
VIL
Byte
Word
Byte
36h
MB84VD21081EA
MB84VD21091EA
MB84VD21082EA
MB84VD21092EA
MB84VD21083EA
MB84VD21093EA
MB84VD21084EA
MB84VD21094EA
X
X
X
X
X
X
X
X
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIL
2236h
39
VIL
X
Word
Byte
2239h
2D
VIL
X
Word
Byte
222Dh
2E
VIL
X
Word
Byte
222Eh
28h
Device
Code
VIL
X
Word
Byte
2228h
2Bh
VIL
X
Word
Byte
222Bh
33h
VIL
X
Word
Byte
2233h
35
VIL
X
Word
2235h
Sector
Group
Sector Group protect
VIL
01h*2
Address
*1: A–1 is for Byte mode.
*2: Output 01h at protected sector address and output 00h at unprotected sector address.
22
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
Flash Memory Command Definitions
Bus
Write
Cycles
Req’d
Fourth Bus
Read/Write
Cycle
First Bus
Second Bus
Write Cycle
Third Bus
Fifth Bus
Sixth Bus
Command
Sequence
Write Cycle
Write Cycle
Write Cycle Write Cycle
Addr. Data Addr. Data
Addr. Data Addr. Data Addr. Data Addr. Data
Read/Reset *1
Read/Reset *1
1
3
XXXh F0h
—
—
—
—
—
—
—
—
—
—
Word
Byte
555h
AAh
2AAh
555h
555h
AAAh
55h
F0h
RA
RD
—
—
—
—
AAAh
(BA)
555h
Word
Byte
555h
AAh
2AAh
555h
Autoselect
3
55h
90h
—
—
—
—
—
—
—
—
(BA)
AAAh
AAAh
Word
Byte
Word
Byte
Word
Byte
555h
AAh
2AAh
555h
2AAh
555h
2AAh
555h
—
555h
AAAh
555h
AAAh
555h
AAAh
—
Program
4
6
6
55h
55h
55h
A0h
80h
80h
PA
PD
—
—
AAAh
555h
AAh
555h
AAAh
555h
AAAh
—
2AAh
555h
2AAh
555h
—
555h
Chip Erase
Sector Erase
AAh
AAh
55h
55h
10h
30h
AAAh
AAAh
555h
AAh
SA
AAAh
Sector Erase Suspend
Sector Erase Resume
1
1
BA
BA
B0h
30h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Word
Byte
Word
Byte
Word
Byte
555h
AAAh
2AAh
555h
555h
AAAh
Set to
Fast Mode
3
2
2
AAh
55h
PD
20h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Fast Program *2
XXXh A0h
BA
PA
—
—
Reset from Fast
Mode *2
F0h *6
90h XXXh
—
Extended
Sector Group
Protection *3
Word
Byte
4
XXXh 60h SPA
55h
60h
SPA
—
40h SPA
SD
—
—
—
—
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Query *4
1
3
4
6
98h
AAh
AAh
AAh
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AAh
555h
AAAh
555h
AAAh
555h
AAAh
2AAh
555h
2AAh
555h
2AAh
555h
555h
AAAh
555h
AAAh
555h
AAAh
Hi-ROM Entry
55h
55h
55h
88h
A0h
80h
Hi-ROM
Program *5
PA
PD
AAh
555h
2AAh
555h
Hi-ROM
Erase *5
55h HRA 30h
AAAh
(HRBA)
555h
Word
Byte
555h
2AAh
555h
Hi-ROM Exit *5
4
AAh
55h
90h XXXh 00h
—
—
—
—
(HRBA)
AAAh
AAAh
*1: Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
*2: This command is valid during Fast Mode.
*3: This command is valid while RESET=VID.
*4: The valid Address is A6 to A0.
*5: This command is valid during Hi-ROM mode.
*6: The data “00h” is also acceptable.
23
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
Notes: Address bits A19 to A12 = X = “H” or “L” for all address commands except for Program Address (PA),
Sector Address (SA), and Bank Address (BA).
Bus operations are defined in “User Bus Operations” in “■ DEVICE BUS OPERATION”.
RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed.
Addresses are latched on the falling edge of the write pulse.
SA = Address of the sector to be erased. The combination of A19, A18, A17, A16, A15, A14, A13, and A12 will
uniquely select any sector.
BA = Bank address (A19 to A15)
SPA = Sector group address to be protected. Set sector group address (SPA) and (A6, A1, A0) = (0, 1, 0).
HRA= Address of the Hidden-ROM area.
MB84VD2108XEA(Top Boot Type)
Word mode: 0F8000h to 0FFFFFh
Byte mode: 1F0000h to 1FFFFFh
MB84VD2109XEA (Bottom Boot Type) Word mode: 000000h to 007FFFh
Byte mode: 000000h to 00FFFFh
HRBA = Bank address of the Hidden-ROM area.
MB84VD2108XEA (Top Boot Type):
A20 = A19 = A18 = A17 = A16 = A15 = 1
MB84VD2109XEA (Bottom Boot Type):A20 = A19 = A18 = A17 = A16 = A15 = 0
RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA.
SD = Sector protection verify data. Output 01h at protected sector addresses and output 00h
at unprotected sector addresses.
The system should generate the following address patterns;
Word mode:555h or 2AAh to addresses A10 to A0
Byte mode :AAAh or 555h to addresses A10 to A0 and A–1
24
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
■ ABSOLUTE MAXIMUM RATINGS
Rating
Parameter
Symbol
Unit
Min
−55
−40
Max
+125
Storage Temperature
Tstg
TA
°C
°C
V
Ambient Temperature with Power Applied
+85
VCCf + 0.4
VCCs + 0.4
+4.0
Voltage with Respect to Ground All pins except
RESET and WP/ACC *1
VIN, VOUT
−0.3
V
VCCf / VCCs Supply *1
RESET *2
VCCf, VCCs
VIN
−0.3
−0.5
−0.5
V
+13.0
V
WP/ACC *3
VIN
+10.5
V
* 1:Minimum DC voltage on input or I/O pins is –0.3 V. During voltage transitions, input or I/O pins may undershoot
VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCCf +0.4 V or VCCs +0.4 V.
During voltage transitions, input I/O pins may overshoot to VCCf +2.0 V or VCCs +2.0 Vfor periods of up to 20 ns.
*2: Minimum DC input voltage on RESET pin is –0.5 V. During voltage transitions, RESET pin may undershoot VSS
to –2.0 V for periods of up to 20 ns.
Voltage difference between input and supply voltage (VIN−VCCf or VCCs) does not exceed 9.0 V.
Maximum DC input voltage on RESET pin is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns.
* 3:Minimum DC input voltage on WP/ACC pin is -0.5 V.During voltage transitions, WP/ACC pin may undershoot
Vss to -2.0V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may
overshoot to 12.0 V for periods of up to 20 ns, when VCCf is applied.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Unit
Min
−40
+2.7
Max
+85
Ambient Temperature
VCCf / VCCs Supply Voltage
TA
°C
VCCf, VCCs
+3.3
V
Note : Operating ranges define those limits between which the functionality of the device is guaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
25
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
■ DC CHARACTERISTICS
Value
Symbol
Unit
Parameter
Test Conditions
VIN = VSS to VCCf, VCCs
Min
–1.0
–1.0
Typ
—
Max
+1.0
+1.0
Input Leakage Current
Output Leakage Current
ILI
µA
µA
ILO
VOUT = VSS to VCCf, VCCs
—
RESET Inputs Leakage
Current
VCCf= VCCf Max, VCCs= VCCs Max
RESET = 12.5V
ILIT
ILIA
—
—
—
—
35
20
µA
ACC Input Leakage
Current
VCCf= VCCf Max, VCCs= VCCs Max
WP/ACC = VACC Max
mA
tCYCLE = 5 MHz Byte
—
—
—
—
—
—
—
—
13
15
7
mA
tCYCLE = 5 MHz Word
tCYCLE = 1 MHz Byte
tCYCLE = 1 MHz Word
Flash VCC Active Current
(Read) *1
ICC1f
CEf = VIL, OE = VIH
mA
mA
mA
7
Flash VCC Active Current
(Program/Erase) *2
ICC2f
ICC3f
CEf = VIL, OE = VIH
CEf = VIL, OE = VIH
—
—
35
Byte
Word
Byte
Word
—
—
—
—
—
—
—
—
48
50
48
50
Flash VCC Active Current
(Read-While-Program) *5
Flash VCC Active Current
(Read-While-Erase) *5
ICC4f
ICC5f
CEf = VIL, OE = VIH
mA
mA
Flash VCC Active Current
(Erase-Suspend-Program)
CEf = VIL, OE = VIH
VCCs = VCCs Max,
—
—
—
—
35
50
SRAM VCC Active Current
SRAM VCC Active Current
Flash VCC Standby Current
ICC1s CE1s = VIL,
CE2s = VIH
tCYCLE =10 MHz
mA
tCYCLE = 10 MHz
tCYCLE = 1 MHz
—
—
—
—
40
8
mA
mA
CE1s = 0.2 V,
ICC2s
CE2s = VCCs – 0.2 V
VCCf = VCCf Max, CEf = VCCf ± 0.3 V,
RESET = VCCf ± 0.3 V,
WP/ACC = VCCf± 0.3 V
ISB1f
—
—
1
1
5
5
µA
µA
Flash VCC Standby Current
(RESET)
VCCf = VCCf Max, RESET = VSS ± 0.3 V,
WP/ACC = VCCf± 0.3 V
ISB2f
VCCf = VCCf Max, CEf = VSS ± 0.3 V,
RESET = VCCf ± 0.3 V,
Flash VCC Current
ISB3f
—
1
5
µA
(Automatic Sleep Mode) *3
WP/ACC = VCCf ± 0.3 V,
VIN = VCCf ± 0.3 V or VSS ± 0.3 V
SRAM VCC Standby Current
SRAM VCC Standby Current
Input Low Level
ISB1s CE1s > VCCs – 0.2V, CE2s > VCCs – 0.2V
ISB2s CE2s < 0.2V
—
—
—
—
—
—
7
7
µA
µA
V
VIL
VIH
—
—
–0.3
2.4
0.5
Input High Level
VCC+0.3
V
Voltage for Sector Protection,
and Temporary Sector
VID
—
11.5
—
12.5
V
Unprotection (RESET) *4
(Continued)
26
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
(Continued)
Parameter
Value
Symbol
Unit
Test Conditions
Min
Typ
Max
Voltage for Program
VACC
—
8.5
9.0
9.5
V
V
Acceleration (WP/ACC) *4
VCCf = VCCf Min VCCs = VCCs Min,
IOL = 4.0mA
Flash
—
—
0.45
Output Low Voltage Level
VOL
VCCf = VCCf Min VCCs = VCCs Min,
IOH = 1.0mA
SRAM
—
—
—
—
0.4
—
V
V
V
Output High Voltage Level
VOH
VCCf = VCCs = VCC Min, IOH=–0.5mA
—
2.4
2.3
Flash Low VCC Lock-Out
Voltage
VLKO
2.5
*1: The ICC current listed includes both the DC operating current and the frequency dependent component.
*2: ICC active while Embedded Algorithm (program or erase) is in progress.
*3: Automatic sleep mode enables the low power mode when address remain stable for 150ns.
*4: Applicable for only VCCf applying.
*5: Embedded Algorithm (program or erase) is in progress. (@5MHz)
27
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
■ AC CHARACTERISTICS
• CE Timing
Symbol
Value
Parameter
Test Setup
Unit
JEDEC Standard
Min
CE Recover Time
—
tCCR
—
0
ns
• Timing Diagram for alternating SRAM to Flash
CEf
tCCR
tCCR
CE1s
CE2s
tCCR
tCCR
28
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
• Read Only Operations Characteristics (Flash)
Value (Note)
Symbol
Parameter
Test Setup
-70
-85
Unit
Standard
tRC
JEDEC
tAVAV
Min Max Min Max
Read Cycle Time
—
70
—
—
—
—
—
—
70
70
30
25
25
85
—
—
—
—
—
—
85
85
35
30
30
ns
ns
ns
ns
ns
ns
Address to Output Delay
tAVQV
tELQV
tACC
tCEf
CEf = VIL, OE = VIL
Chip Enable to Output Delay
Output Enable to Output Delay
Chip Enable to Output High-Z
Output Enable to Output High-Z
OE = VIL
tGLQV
tEHQZ
tGHQZ
tOE
—
—
—
tDF
tDF
Output Hold Time From Addresses,
CEf or OE, Whichever Occurs First
tAXQX
—
tOH
—
—
0
—
0
—
ns
µs
RESET Pin Low to Read Mode
tREADY
—
20
—
20
Note: Test Conditions: Output Load : 1 TTL gate and 30 pF
Input rise and fall times : 5 ns
Input pulse levels: 0.0 V or 3.0 V
Timing measurement reference level
Input : 0.5 × Vccf
Output : 0.5 × Vccf
29
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
• Read Cycle (Flash)
tRC
Address Stable
Address
tACC
CEf
tOE
tDF
OE
tOEH
WE
DQ
tCEf
High-Z
High-Z
Output Valid
tRC
Address
CEf
Address Stable
tACC
tRH
tRH
tCEf
tRP
RESET
DQ
tOH
High-Z
Output Valid
30
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
• Erase/Program Operations (Flash)
Value
Symbol
Unit
Parameter
-70
-85
Standard
JEDEC
tAVAV
Min Typ Max Min Typ Max
Write Cycle Time
tWC
tAS
70
0
—
—
—
—
85
0
—
—
—
—
ns
ns
Address Setup Time (WE to Addr.)
tAVWL
Address Setup Time to CEf Low During Toggle Bit
Polling
—
tWLAX
—
tASO
tAH
12
45
0
—
—
—
—
—
—
15
45
0
—
—
—
—
—
—
ns
ns
ns
Address Hold Time (WE to Addr.)
Address Hold Time from CEf or OE High During
Toggle Bit Polling
tAHT
Data Setup Time
tDVWH
tWHDX
—
tDS
tDH
30
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
70
—
90
35
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
85
—
90
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
sec
µs
µs
ns
ns
ns
ns
ns
ns
ns
Data Hold Time
Output Enable Setup Time
tOES
0
0
Read
Output Enable Hold Time
Toggle and Data Polling
0
0
—
tOEH
10
20
20
0
10
20
20
0
CEf High During Toggle Bit Polling
OE High During Toggle Bit Polling
Read Recover Time Before Write (OE to CEf)
Read Recover Time Before Write (OE to WE)
WE Setup Time (CEf to WE)
CEf Setup Time (WE to CEf)
WE Hold Time (CEf to WE)
CEf Hold Time (WE to CEf)
Write Pulse Width
—
tCEPH
tOEPH
tGHEL
tGHWL
tWS
—
tGHEL
tGHWL
tWLEL
tELWL
tEHWH
tWHEH
tWLWH
tELEH
tWHWL
tEHEL
0
0
0
0
tCS
0
0
tWH
0
0
tCH
0
0
tWP
35
35
25
25
—
—
—
50
4
35
35
30
30
—
—
—
50
4
CEf Pulse Width
tCP
Write Pulse Width High
tWPH
tCPH
CEf Pulse Width High
Byte Programming Operation
Word Programming Operation
Sector Erase Operation *1
VCCf Setup Time
tWHWH1
tWHWH1
16
1
16
1
tWHWH2
—
tWHWH2
tVCS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Voltage Transition Time *2
Rise Time to VID *2
—
tVLHT
tVIDR
tVACCR
tRB
—
500
500
0
500
500
0
Rise Time to VACC
—
Recover Time from RY/BY
RESET Pulse Width
—
—
tRP
500
—
200
—
500
—
200
—
Delay Time from Embedded Output Enable
RESET Hold Time Before Read
Program/Erase Valid to RY/BY Delay
—
tEOE
tRH
—
—
tBUSY
(Continued)
31
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
(Continued)
Value
Symbol
Unit
Parameter
-70
-85
Standard
tTOW
JEDEC
Min Typ Max Min Typ Max
Erase Time-out Time *3
Erase Suspend Transition Time *4
—
—
50
—
—
—
—
50
—
—
—
—
µs
µs
tSPD
20
20
*1: This does not include the preprogramming time.
*2: This timing is for Sector Protection Operation.
*3: The time between writes must be less than “tTOW” otherwise that command will not be accepted and erasure will
start. A time-out or “tTOW” from the rising edge of last CEf or WE whichever happens first will initiate the execution
of the Sector Erase command(s).
*4: When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum
of “tSPD” to suspend the erase operation.
32
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
• Write Cycle (WE control) (Flash)
3rd Bus Cycle
Data Polling
555h
PA
PA
Address
CEf
tWC
tRC
tAS
tAH
tCH
tCS
tCEf
OE
tGHWL
tOE
tWHWH1
tWP
tWPH
WE
tOH
tDS
tDH
PD
DOUT
DOUT
A0h
DQ7
DQ
Notes: • PA is address of the memory location to be programmed.
• PD is data to be programmed at byte address.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates the last two bus cycles out of four bus cycle sequence.
• These waveforms are for the ×16 mode (the addresses differ from ×8 mode).
33
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
• Write Cycle (CEf control) (Flash)
3rd Bus Cycle
Data Polling
Address
PA
PA
555h
tWC
tAH
tAS
WE
tWS
tWH
OE
tGHEL
tWHWH1
tCP
tCPH
CEf
tDS
tDH
PD
DOUT
DQ7
A0h
DQ
Notes: • PA is address of the memory location to be programmed.
• PD is data to be programmed at byte address.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates the last two bus cycles out of four bus cycle sequence.
• These waveforms are for the ×16 mode (the addresses differ from ×8 mode).
34
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
• AC Waveforms Chip/Sector Erase Operations (Flash)
SA*
2AAh
555h
2AAh
555h
555h
Address
CEf
tWC
tAS
tAH
tCS
tCH
OE
tWP
tWPH
tGHWL
WE
tDS
tDH
30h for Sector Erase
10h/
30h
AAh
AAh
55h
80h
55h
DQ
tVCS
VCCf
* : SA is the sector address for Sector Erase. Addresses = 555h for Chip Erase.
Note : These waveform are for the ×16 mode (the addresses differ from ×8 mode).
35
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
• AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash)
CEf
tCH
tDF
tOE
OE
tOEH
WE
tCEf
*
High-Z
High-Z
DQ7 =
Data
Data
DQ7
DQ7
Valid Data
tWHWH1 or 2
DQ6 to DQ0
Valid Data
DQ6 to DQ0 = Output Flag
DQ6 to DQ0
RY/BY
tBUSY
tEOE
* : DQ7 = Valid Data (The device has completed the Embedded operation.)
36
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
• AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash)
Address
tAHT
tASO
tAHT
tAS
CEf
tCEPH
WE
OE
tOEH
tOEH
tOEPH
tOE
tCEf
*
tDH
Toggle
Data
Toggle
Data
Toggle
Data
Stop
Toggling
Output
Valid
DQ6/DQ2
RY/BY
Data
tBUSY
*: DQ6 stops toggling (the device has completed the Embedded operation).
37
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
• Back-to-Back Read/Write Timing Diagram (Flash)
Read
tRC
Read
tRC
Command
tWC
Read
tRC
Command
tWC
Read
tRC
BA2
(PA)
BA2
(555h)
BA2
(PA)
BA1
Address
CEf
BA1
BA1
tACC
tAS
tAH
tAS
tCE
tOE
tAHT
tCEPH
OE
tOEH
tDF
tGHWL
tWP
tDS
WE
tDH
tDF
Valid
Output
Valid
Input
Valid
Output
Valid
Input
Valid
Output
Valid
Input
DQ
(PD)
(A0H)
Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.
BA1: Address corresponding to Bank 1.
BA2: Address corresponding to Bank 2.
38
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
• RY/BY Timing Diagram during Write/Erase Operations (Flash)
CEf
Rising edge of the last write pulse
WE
Entire programming
or erase operations
RY/BY
tBUSY
• RESET, RY/BY Timing Diagram (Flash)
WE
RESET
tRP
tRB
RY/BY
tREADY
39
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
• Temporary Sector Group Unprotection (Flash)
VCCf
tVIDR
tVCS
tVLHT
VID
VIH
RESET
CEf
WE
tVLHT
tVLHT
Program or Erase Command Sequence
Unprotection Period
RY/BY
40
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
• Extended Sector Group Protection (Flash)
VCCf
tVCS
RESET
tVLHT
tVIDR
tWC
tWC
Address
SPAX
SPAX
SPAY
A6, A0
A1
CEf
OE
TIME-OUT
tWP
WE
Data
60h
60h
40h
01h
60h
tOE
SPAX: Sector Group Address to be protected
SPAY : Next Group Sector Address to be protected
TIME-OUT : Time-Out window = 250 µs (Min)
41
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
• Accelerated Program (Flash)
VCCf
tVACCR
tVCS
tVLHT
VID
VIH
WP/ACC
CEf
WE
tVLHT
tVLHT
Program or Erase Command Sequence
Acceleration Period
RY/BY
42
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
• Read Cycle (SRAM)
Value
Parameter
Symbol
-70
-85
Unit
Min
70
—
—
—
—
—
5
Max
Min
85
—
—
—
—
—
5
Max
—
Read Cycle Time
tRC
tAA
—
70
70
70
35
70
—
—
—
25
25
25
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
85
85
85
45
85
—
Chip Enable (CE1s) Access Time
tCO1
tCO2
tOE
Chip Enable (CE2s) Access Time
Output Enable Access Time
UBs, LBs to Output Valid
tBA
Chip Enable (CE1s Low and CE2s High) to Output Active
Output Enable Low to Output Active
UBs, LBs Enable Low to Output Active
Chip Enable (CE1s High or CE2s Low) to Output High-Z
Output Enable High to Output High-Z
UBs, LBs Output Enable to Output High-Z
Output Data Hold Time
tCOE
tOEE
tBE
0
0
—
0
0
—
tOD
—
—
—
10
—
—
—
10
35
35
35
—
tODO
tBD
tOH
Note: Test Conditions:Output Load : 1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Input pulse levels : 0.0 V or 3.0 V
Timing measurement reference level
Input : 1.5 V x VCCs
Output : 1.5 V x VCCs
43
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
• Read Cycle (Note 1) (SRAM)
tRC
Address
tAA
tOH
tCO1
CE1s
CE2s
tCOE
tOD
tCO2
tOD
tOE
OE
tODO
tOEE
LBs, UBs
tBA
tBD
tBE
tCOE
DQ
Valid Data Out
Note : WE remains “H” during the read cycle.
44
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
• Write Cycle (SRAM)
Value
Parameter
Symbol
-70
-85
Unit
Min
70
50
55
55
55
0
Max
—
—
—
—
—
—
—
25
—
—
—
Min
85
55
70
70
55
0
Max
—
—
—
—
—
—
—
35
—
—
—
Write Cycle Time
tWC
tWP
tCW
tAW
tBW
tAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Pulse Width
Chip Enable to End of Write
Address valid to End of Write
UBs, LBs to End of Write
Address Setup Time
Write Recovery Time
WE Low to Output High-Z
WE High to Output Active
Data Setup Time
tWR
tODW
tOEW
tDS
0
0
—
0
—
0
25
0
35
0
Data Hold Time
tDH
45
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
• Write Cycle (Note 3) (WE control) (SRAM)
tWC
Address
tAS
tWP
tWR
WE
CE1s
CE2s
tAW
tCW
tCW
tBW
LBs, UBs
tOEW
tODW
DOUT
Note 1
Note 4
Note 2
Note 4
tDS
tDH
DIN
Valid Data In
Notes:• If CE1s goes “L” (or CE2s goes “H”) coincident with or after WE goes “L”, the output will
remain at high impedance.
• If CE1s goes “H” (or CE2s goes “L”) coincident with or before WE goes “H”, the output will
remain at high impedance.
• If OE is “H” during the write cycle, the outputs will remain at high impedance.
• Because I/O signals may be in the output state at this Time, input signals of reverse polarity
must not be applied.
46
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
• Write Cycle (Note 1) (CE1s control) (SRAM)
tWC
Address
tAS
tWP
tWR
WE
tAW
tCW
CE1s
CE2s
tCW
tBW
LBs, UBs
tBE
tCOE
tODW
DOUT
tDS
tDH
DIN
Note 2
Valid Data In
Notes: • If OE is “H” during the write cycle, the outputs will remain at High-Z.
• Because I/O signals may be in the output state at this time, input signals of reverse
polarity must not be applied.
47
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
• Write Cycle (Note 1) (CE2s Control) (SRAM)
tWC
Address
tAS
tWP
tWR
WE
tCW
CE1s
CE2s
tAW
tCW
tBW
LBs, UBs
tBE
tCOE
tODW
DOUT
tDS
tDH
DIN
Note 2
Valid Data In
Notes: • If OE is “H” during the write cycle, the outputs will remain at High-Z.
• Because I/O signals may be in the output state at this time, input signals of reverse
polarity must not be applied.
48
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
• Write Cycle (Note 1) (LBs, UBs Control) (SRAM)
tWC
Address
tWP
tWR
WE
tCW
CE1s
tCW
CE2s
tAW
tBW
tAS
LBs, UBs
tBE
tCOE
tODW
DOUT
tDS
tDH
Note 2
Valid Data In
DIN
Notes: • If OE is “H” during the write cycle, the outputs will remain at High-Z.
• Because I/O signals may be in the output state at this time, input signals of reverse
polarity must not be applied.
49
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
■ ERASE AND PROGRAMMING PERFORMANCE (Flash)
Limit
Parameter
Unit
Comment
Min
Typ
Max
Excludes programming time
prior to erasure
Sector Erase Time
—
1
10
s
Excludes system-level
overhead
Byte Programming Time
Word Programming Time
—
—
8
300
360
µs
µs
Excludes system-level
overhead
16
Excludes system-level
overhead
Chip Programming Time
Erase/Program Cycle
—
—
—
50
—
s
100,000
cycle
■ DATA RETENTION CHARACTERISTICS (SRAM)
Value
Parameter
Symbol
Condition
Unit
Min
Typ
—
Max
3.6
5
Data Retention Supply Voltage
Standby Current
VDH
IDDS2
tCDR
tR
—
1.5
—
0
V
VDH = 3.0 V
0.3
—
µA
ns
ns
Chip Deselect to Data Retention Mode Time
Recovery Time
—
—
—
tRC
—
—
Note : tRC: Read cycle time
• CE1s Controlled Data Retention Mode *1
VCCs
Data Retention Mode
2.7 V
2
2
*
*
VIH
VDH
VCCS –0.2 V
CE1s
tCDR
tR
GND
*1: In CE1s controlled data retention mode, input level of CE2s should be fixed Vccs to Vccs–0.2 V or Vss
to 0.2 V during data retention mode. Other input and input/output pins can be used between –0.3 V to
Vccs+0.3 V.
*2: When CE1s is operating at the VIH Min level (2.2 V), the standby current is given by ISB1s during the
transition of VCCs from 3.6 to 2.2 V.
50
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
• CE2s Controlled Data Retention Mode *
VCCs
Data Retention Mode
2.7 V
VDH
VIH
CE2s
tCDR
tR
VIL
0.2 V
GND
*: In CE2s controlled data retention mode, input and input/output pins can be used between –0.3 V to
Vccs+0.3 V.
■ PACKAGEPIN CAPACITANCE
Value
Parameter
Symbol
Test Setup
VIN = 0
Unit
Typ
11
Max
14
Input Capacitance
CIN
pF
pF
pF
pF
Output Capacitance
COUT
CIN2
CIN3
VOUT = 0
VIN = 0
VIN = 0
12
16
Control Pin Capacitance
WP/ACC Pin Capacitance
14
16
17
20
Note : Test conditions TA = 25°C, f = 1.0 MHz
■ HANDRING OF PACKAGE
Please handle this package carefully since the sides of package are created with acute angles.
■ CAUTION
•
The high voltage (VID) cannot apply to address pins and control pins except RESET. Exception is when use
autoselect and sector Group protection function are used. Then the high voltage can be applied to RESET.
•
Without the high voltage (VID) , sector Group protection can be achieved by using “Extended sector Group
protection” command.
51
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
■ ORDERING INFORMATION
MB84VD2108
X
EA
-70
-PBS
PACKAGE TYPE
PBS = 56-ball BGA
PTS = 56-pin TSOP
SPEED OPTION
See Product Guide
Device Revision
EA
Bank Size
1 = 0.5Mbit / 15.5Mbit
2 = 2Mbit / 14Mbit
3 = 4Mbit / 12Mbit
4 = 8Mbit / 8Mbit
DEVICE NUMBER/DESCRIPTION
16Mega-bit (2M × 8-bit or 1M × 16-bit) Dual Operation Flash Memory
3.0 V-only Read, Program, and Erase
2Mega-bit(256K × 8-bit or 128K x 16-bit) SRAM
BOOT CODE SECTOR ARCHITECTURE
84VD2108 = Top sector
84VD2109 = Bottom sector
52
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
■ PACKAGE DIMENSIONS
56-pin plastic FBGA
(BGA-56P-M01)
7.20±0.10(.283±.004)
1.05 ±+00..1105
.041 –+..000046
(Mounting height)
(Stand off)
5.60(.220)REF
0.38±0.10
(.015±.004)
0.80
(.031)
8
7
6
5
4
3
2
1
5.60(.220)
7.00±0.10
(.276±.004)
REF
0.80
(.031)
H
G
F
E
D
C
B
A
INDEX-MARK AREA
INDEX
56-Ø0.45 –+00..0150
56-Ø.018 –+..000024
M
0.08(.003)
0.10(.004)
C
2000 FUJITSU LIMITED B56001S-1c-1
Dimensions in mm (inches)
(Continued)
53
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
(Continued)
56-pin plastic TSOP (I)
(FPT-56P-M04)
14.00±0.20(.551±.008)
12.40±0.10(.488±.004)
INDEX
0.40(.016)
TYP
12.00±0.10
(.472±.004)
0.18±0.035
(.007±.001)
M
0.10(.004)
Details of "A" part
"A"
0.25(.010)
0°~8°
1.15±0.05
(.045±.002)
(.004±.002) (Mounting height)
(Stand off)
0.145 +–00..0035
.006 +–..000012
0.10±0.05
0.08(.003)
0.45/0.75
(.018/.030)
C
1998 FUJITSU LIMITED F56004S-1C-1
Dimensions in mm (inches)
54
MB84VD2108XEA-70/85/MB84VD2109XEA-70/85
FUJITSU LIMITED
For further information please contact:
Japan
All Rights Reserved.
FUJITSU LIMITED
Marketing Division
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
Electronic Devices
Shinjuku Dai-Ichi Seimei Bldg. 7-1,
Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0721, Japan
Tel: +81-3-5322-3353
Fax: +81-3-5322-3386
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
http://edevice.fujitsu.com/
North and South America
FUJITSU MICROELECTRONICS AMERICA, INC.
3545 North First Street,
San Jose, CA 95134-1804, U.S.A.
Tel: +1-408-922-9000
Fax: +1-408-922-9179
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: +1-800-866-8608
Fax: +1-408-922-9179
http://www.fma.fujitsu.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Am Siebenstein 6-10,
D-63303 Dreieich-Buchschlag,
Germany
Tel: +49-6103-690-0
Fax: +49-6103-690-122
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
http://www.fme.fujitsu.com/
Asia Pacific
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: +65-281-0770
Fax: +65-281-0220
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
http://www.fmal.fujitsu.com/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
1702 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Tel: +82-2-3484-7100
Fax: +82-2-3484-7111
F0112
FUJITSU LIMITED Printed in Japan
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