MB84VD22193EB-90-PBS

FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-50213-1E

Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM

CMOS

32M (× 8/×16) FLASH MEMORY &

4M (× 8/×16) STATIC RAM

MB84VD2218XEB^-85/90/MB84VD2219XEB^-85/90

MB84VD2218XEE^-85/90/MB84VD2219XEE^-85/90

■ FEATURES

• Power supply voltage of 2.7 V to 3.3 V

• High performance

85 ns / 90 ns maximum access time (Flash)

85 ns maximum access time (SRAM)

• Operating Temperature

–25 °C to +85 °C

• Package 73-ball BGA

(Continued)

■ PRODUCT LINE UP

Flash Memory

SRAM

-85

-90

+0.3 V

–0.3 V

+0.3 V

–0.3 V

Power Supply Voltage (V)

Max. Address Access Time (ns)

Max. CE Access Time (ns)

Max. OE Access Time (ns)

V^CCf* = 3.0 V _{–0.3 V}

V^CCf* = 3.0 V

V^CCs* = 3.0 V

85

35

90

40

85

45

* : Both V^CCf and V^CCs must be in recommended operation range when either part is being accessed.

■ PACKAGE

73-pin plastic FBGA

(BGA-73P-M01)

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

(Continued)

1.FLASH MEMORY

• Simultaneous Read/Write operations (dual bank)

Multiple devices available with different bank sizes

Host system can program or erase in one bank, then immediately and simultaneously read from the other bank.

Zero latency between read and write operations

Read-while-erase

Read-while-program

• Minimum 100,000 write/erase cycles

• Sector erase architecture

Eight 4 K words and sixty three 32 K words

Any combination of sectors can be concurrently erased. Also supports full chip erase.

• Boot Code Sector Architecture

MB84VD2218X: Top sector

MB84VD2219X: Bottom sector

• Embedded Erase^TMAlgorithms

Automatically pre-programs and erases the chip or any sector

• Embedded Program^TMAlgorithms

Automatically writes and verifies data at specified address

• Data Polling and Toggle Bit feature for detection of program or erase cycle completion

• Ready-Busy output (RY/BY)

Hardware method for detection of program or erase cycle completion

• Automatic sleep mode

When addresses remain stable, automatically switch themselves to low power mode.

• Low V^CCf write inhibit ≤ 2.5 V

• Hidden ROM (Hi-ROM) region

64 K byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence

Factory serialized and protected to provide a secure electronic serial number (ESN)

• WP/ACC input pin

At V^IL, allows protection of boot sectors, regardless of sector protection/unprotection status.

(MB84VD2218XEB/EE:SA69,SA70 MB84VD2219XEB/EE:SA0,SA1)

At V^IH, allows removal of boot sector protection.

At VACC, program time will reduce by 40%.

• Erase Suspend/Resume

Suspends the erase operation to allow a read in another sector within the same device

• Please refer to “MBM29DL32XTE/BE” data sheet in detailed function

2.SRAM

• Power dissipation

Operating: 40 mA Max.

Standby : 7 µA Max.

• Power down features using CE1s and CE2s

• Data retention supply voltage: 1.5 V to 3.3 V

• CE1s and CE2s Chip Select

• Byte data control: LBs(DQ⁰to DQ⁷), UBs(DQ⁸to DQ¹⁵)

2

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

■ PIN ASSIGNMENT

FBGA

(Top View)

Marking Side

A10

B10

F10

G10

N.C.

L10

M10

N.C.

D9

E9

F9

G9

H9

J9

A15

N.C.

A16

CIOf

V^SS

C8

D8

E8

F8

G8

SA

H8

J8

K8

A11

A12

A13

A14

DQ15/A-1 DQ7

DQ14

C7

D7

E7

A⁹

F7

G7

H7

J7

K7

A8

A19

A10

DQ6

DQ13

DQ12

DQ5

B6

C6

D6

E6

H6

J6

K6

L6

N.C.

WE

CE2s

A20

DQ4

VCCs

CIOs

N.C.

B5

C5

D5

E5

H5

J5

K5

L5

WP/ACC RESET

N.C.

RY/BY

DQ3

VCCf

DQ11

N.C.

C4

D4

E4

F4

G4

H4

J4

K4

LBs

UBs

A18

A17

DQ1

DQ9

DQ10

DQ2

C3

D3

E3

F3

G3

H3

J3

K3

A7

A6

A5

A4

V^SS

OE

DQ0

DQ8

D2

E2

F2

G2

H2

J2

A3

A2

A1

A0

CEf

CE1s

A1

B1

C1

F1

G1

L1

M1

N.C.

(BGA-73P-M01)

3

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

■ PIN DESCRIPTION

Pin Name

A⁰to A17

A^–1, A18 to A20

SA

Function

Input/Output

Address Inputs (Common)

Address Inputs (Flash)

Address Input (SRAM)

I

DQ⁰to DQ15

CEf

Data Inputs/Outputs (Common)

Chip Enable (Flash)

I/O

I

CE1s

Chip Enable (SRAM)

CE2s

Chip Enable (SRAM)

I

OE

Output Enable (Common)

Write Enable (Common)

I

WE

I

RY/BY

UBs

Ready/Busy Outputs (Flash) Open Drain Output

Upper Byte Control (SRAM)

Lower Byte Control (SRAM)

O

I

LBs

I

I/O Configuration (Flash)

CIOf = V^CCf is Word mode (×16), CIOf = VSS is Byte mode (×8)

CIOf

I

I/O Configuration (SRAM)

CIOs = V^CCs is Word mode (×16), CIOs = VSS is Byte mode (×8)

CIOs

RESET

WP/ACC

N.C.

Hardware Reset Pin/Sector Protection Unlock (Flash)

Write Protect / Acceleration (Flash)

No Internal Connection

I

—

V^SS

Device Ground (Common)

Power

V^CCf

Device Power Supply (Flash)

V^CCs

Device Power Supply (SRAM)

4

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

■ BLOCK DIAGRAM

V^CCf

V^SS

A⁰to A²⁰

RY/BY

A⁰to A²⁰

A^–1

WP/ACC

RESET

CEf

32 M bit

Flash Memory

DQ⁰to DQ¹⁵/A–1

CIOf

DQ⁰to DQ¹⁵/A–1

V^CCs

V^SS

A⁰to A¹⁷

DQ⁰to DQ¹⁵

4 M bit

SA

LBs

UBs

WE

Static RAM

OE

CE1s

CE2s

CIOs

5

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

■ DEVICE BUS OPERATIONS

Table 1. 1 User Bus Operations (Flash=Word mode; CIOf=V^ccf, SRAM=Word mode; CIOs=V^ccs)

WP/

ACC*

1,

3

6

CEf CE1s CE2s OE WE

LBs UBs DQ⁰to DQ⁷DQ⁸to DQ¹⁵RESET

Operation * *

SA*

5

H

X

L

Full Standby

H

L

X

High-Z

H

X

H

X

H

X

H

X

H

High-Z

L

H

Output Disable

H

X

H

X

H

X

H

X

L

X

L

X

L

H

L

H

L

X

High-Z

D^OUT

D^IN

High-Z

D^OUT

D^IN

2

L

H

X

Read from Flash *

Write to Flash

L

H

L

H

L

D^OUT

High-Z

D^OUT

Read from SRAM

Write to SRAM

H

L

H

L

H

X

H

X

H

L

High-Z

D^IN

L

D^IN

H

X

L

H

X

L

X

H

L

High-Z

D^IN

H

X

H

High-Z

Temporary Sector

Group

X

V^ID

4

Unprotection*

H

X

L

Flash Hardware

Reset

X

High-Z

X

High-Z

X

L

X

L

Boot Block Sector

Write Protection

X

Legend: L = V^IL, H = V^IH, X = V^ILor V^IH. See “ ELECTRICAL CHARACTERISTICS 1.DC Characteristics” for

voltage levels.

*1 : Other operations except for indicated this column are inhibited.

*2 : WE can be V^ILif OE is V^IL, OE at V^IHinitiates the write operations.

*3 : Do not apply CEf = V^IL, CE1s = V^ILand CE2s = V^IHat a time.

*4 : It is also used for the extended sector group protections.

*5 : WP/ACC = V^IL; protection of boot sectors.

WP/ACC = V^IH; removal of boot sectors protection.

WP/ACC = V^ACC(9V) ; Program time will reduce by 40%.

*6 : SA; Don’t care or Open.

6

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

Table 1. 2 User Bus Operations (Flash=Word mode; CIOf=V^ccf, SRAM=Byte mode; CIOs=V^ss)

WP/

1,

3

6

CEf CE1s CE2s OE WE SA

DQ⁰to DQ⁷DQ⁸to DQ¹⁵RESET

LBs* UBs*

Operation * *

5

ACC*

H

X

L

Full Standby

H

L

X

High-Z

H

X

H

X

H

X

H

X

H

High-Z

L

H

Output Disable

X

H

X

H

X

H

X

L

X

L

H

L

H

L

X

High-Z

D^OUT

D^IN

High-Z

D^OUT

D^IN

X

L

2

L

H

X

Read from Flash *

Write to Flash

X

L

H

Read from SRAM

Write to SRAM

H

L

H

L

SA

X

D^OUT

D^IN

High-Z

H

X

L

X

Temporary Sector

Group

Unprotection*

X

V^ID

X

4

H

X

L

Flash Hardware

Reset

X

High-Z

X

High-Z

X

L

X

L

Boot Block Sector

Write Protection

X

Legend: L = V^IL, H = V^IH, X = V^ILor V^IH. See “ ELECTRICAL CHARACTERISTICS 1.DC Characteristics” for

voltage levels.

*1 : Other operations except for indicated this column are inhibited.

*2 : WE can be V^ILif OE is V^IL, OE at V^IHinitiates the write operations.

*3 : Do not apply CEf = V^IL, CE1s = V^ILand CE2s = V^IHat a time.

*4 : It is also used for the extended sector group protections.

*5 : WP/ACC = V^IL; protection of boot sectors.

WP/ACC = V^IH; removal of boot sectors protection.

WP/ACC = V^ACC(9V); Program time will reduce by 40%.

*6 : LBs^,UBs; Don’t care or Open.

7

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

Table 1. 3 User Bus Operations (Flash=Byte mode; CIOf=V^ss, SRAM=Byte mode; CIOs=V^ss)

WP/

ACC*

DQ⁰to DQ⁸to

6

1,

3

6

CEf CE1s CE2s DQ¹⁵/A^–1OE WE SA

RESET

Operation * *

LBs* UBs*

5

DQ⁷

DQ¹⁴

H

X

L

Full Standby

H

L

X

High-Z High-Z

H

X

H

X

H

X

H

X

H

High-Z High-Z

L

H

Output Disable

H

X

H

X

H

X

H

X

L

X

L

A–1

A^–1

H

L

H

L

X

High-Z High-Z

X

L

2

L

D^OUT

D^IN

X

H

X

Read from Flash *

X

L

Write to Flash

L

H

Read from SRAM

Write to SRAM

H

X

L

H

L

SA

X

D^OUTHigh-Z

H

X

L

X

D^IN

High-Z

Temporary Sector

Group

Unprotection*

X

V^ID

X

4

H

X

L

Flash Hardware

Reset

X

High-Z High-Z

L

X

L

Boot Block Sector

Write Protection

X

Legend: L = V^IL, H = V^IH, X = V^ILor V^IH. See “

ELECTRICAL CHARACTERISTICS 1.DC Characteristics” for

voltage levels.

*1 : Other operations except for indicated this column are inhibited.

*2 : WE can be V^ILif OE is V^IL, OE at V^IHinitiates the write operations.

*3 : Do not apply CEf = V^IL, CE1s = V^ILand CE2s = V^IHat a time.

*4 : It is also used for the extended sector group protections.

*5 : WP/ACC = V^IL; protection of boot sectors.

WP/ACC = V^IH; removal of boot sectors protection.

WP/ACC = V^ACC(9V); Program time will reduce by 40%.

*6 : LBs^,UBs; Don’t care or Open.

8

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

■ FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY

• Eight 4 K words and sixty three 32 K words

• Individual-sector, multiple-sector or bulk-erase capability

Word Mode

Byte Mode

1FFFFFh

1FF000h

1FE000h

1FD000h

1FC000h

1FB000h

1FA000h

1F9000h

1F8000h

1F0000h

1E8000h

1E0000h

1D8000h

1D0000h

1C8000h

1C0000h

1B8000h

1B0000h

1A8000h

1A0000h

198000h

190000h

188000h

180000h

178000h

170000h

168000h

160000h

158000h

150000h

148000h

140000h

138000h

130000h

128000h

120000h

118000h

110000h

108000h

100000h

0F8000h

0F0000h

0E8000h

0E0000h

0D8000h

0D0000h

0C8000h

0C0000h

0B8000h

0B0000h

0A8000h

0A0000h

098000h

090000h

088000h

080000h

078000h

070000h

068000h

060000h

058000h

050000h

048000h

040000h

038000h

030000h

028000h

020000h

018000h

010000h

008000h

000000h

3FFFFFh

3FE000h

3FC000h

3FA000h

3F8000h

3F6000h

3F4000h

3F2000h

3F0000h

3E0000h

3D0000h

3C0000h

3B0000h

3A0000h

390000h

380000h

370000h

360000h

350000h

340000h

330000h

320000h

310000h

300000h

2F0000h

2E0000h

2D0000h

2C0000h

2B0000h

2A0000h

290000h

280000h

270000h

260000h

250000h

240000h

230000h

220000h

210000h

200000h

1F0000h

1E0000h

1D0000h

1C0000h

1B0000h

1A0000h

190000h

180000h

170000h

160000h

150000h

140000h

130000h

120000h

110000h

100000h

0F0000h

0E0000h

0D0000h

0C0000h

0B0000h

0A0000h

090000h

080000h

070000h

060000h

050000h

040000h

030000h

020000h

010000h

000000h

SA70 : 8KB (4KW)

SA69 : 8KB (4KW)

SA68 : 8KB (4KW)

SA67 : 8KB (4KW)

SA66 : 8KB (4KW)

SA65 : 8KB (4KW)

SA64 : 8KB (4KW)

SA63 : 8KB (4KW)

SA62 : 64KB (32KW)

SA61 : 64KB (32KW)

SA60 : 64KB (32KW)

SA59 : 64KB (32KW)

SA58 : 64KB (32KW)

SA57 : 64KB (32KW)

SA56 : 64KB (32KW)

SA55 : 64KB (32KW)

SA54 : 64KB (32KW)

SA53 : 64KB (32KW)

SA52 : 64KB (32KW)

SA51 : 64KB (32KW)

SA50 : 64KB (32KW)

SA49 : 64KB (32KW)

SA48 : 64KB (32KW)

SA47 : 64KB (32KW)

SA46 : 64KB (32KW)

SA45 : 64KB (32KW)

SA44 : 64KB (32KW)

SA43 : 64KB (32KW)

SA42 : 64KB (32KW)

SA41 : 64KB (32KW)

SA40 : 64KB (32KW)

SA39 : 64KB (32KW)

SA38 : 64KB (32KW)

SA37 : 64KB (32KW)

SA36 : 64KB (32KW)

SA35 : 64KB (32KW)

SA34 : 64KB (32KW)

SA33 : 64KB (32KW)

SA32 : 64KB (32KW)

SA31 : 64KB (32KW)

SA30 : 64KB (32KW)

SA29 : 64KB (32KW)

SA28 : 64KB (32KW)

SA27 : 64KB (32KW)

SA26 : 64KB (32KW)

SA25 : 64KB (32KW)

SA24 : 64KB (32KW)

SA23 : 64KB (32KW)

SA22 : 64KB (32KW)

SA21 : 64KB (32KW)

SA20 : 64KB (32KW)

SA19 : 64KB (32KW)

SA18 : 64KB (32KW)

SA17 : 64KB (32KW)

SA16 : 64KB (32KW)

SA15 : 64KB (32KW)

SA14 : 64KB (32KW)

SA13 : 64KB (32KW)

SA12 : 64KB (32KW)

SA11 : 64KB (32KW)

SA10 : 64KB (32KW)

SA9 : 64KB (32KW)

SA8 : 64KB (32KW)

SA7 : 64KB (32KW)

SA6 : 64KB (32KW)

SA5 : 64KB (32KW)

SA4 : 64KB (32KW)

SA3 : 64KB (32KW)

SA2 : 64KB (32KW)

SA1 : 64KB (32KW)

SA0 : 64KB (32KW)

Bank 1

MB84VD22182EB/EE

Bank 1

MB84VD22183EB/EE

Bank 1

MB84VD22184EB/EE

Bank 2

MB84VD22182EB/EE

Bank 2

MB84VD22183EB/EE

Bank 2

MB84VD22184EB/EE

MB84VD2218XEB/EE Sector Architecture (Top Boot Block)

(Continued)

9

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

(Continued)

Word Mode

Byte Mode

1FFFFFh

1F8000h

1F0000h

1E8000h

1E0000h

1D8000h

1D0000h

1C8000h

1C0000h

1B8000h

1B0000h

1A8000h

1A0000h

198000h

190000h

188000h

180000h

178000h

170000h

168000h

160000h

158000h

150000h

148000h

140000h

138000h

130000h

128000h

120000h

118000h

110000h

108000h

100000h

0F8000h

0F0000h

0E8000h

0E0000h

0D8000h

0D0000h

0C8000h

0C0000h

0B8000h

0B0000h

0A8000h

0A0000h

098000h

090000h

088000h

080000h

078000h

070000h

068000h

060000h

058000h

050000h

048000h

040000h

038000h

030000h

028000h

020000h

018000h

010000h

008000h

007000h

006000h

005000h

004000h

003000h

002000h

001000h

000000h

3FFFFFh

3F0000h

3E0000h

3D0000h

3C0000h

3B0000h

3A0000h

390000h

380000h

370000h

360000h

350000h

340000h

330000h

320000h

310000h

300000h

2F0000h

2E0000h

2D0000h

2C0000h

2B0000h

2A0000h

290000h

280000h

270000h

260000h

250000h

240000h

230000h

220000h

210000h

200000h

1F0000h

1E0000h

1D0000h

1C0000h

1B0000h

1A0000h

190000h

180000h

170000h

160000h

150000h

140000h

130000h

120000h

110000h

100000h

0F0000h

0E0000h

0D0000h

0C0000h

0B0000h

0A0000h

090000h

080000h

070000h

060000h

050000h

040000h

030000h

020000h

010000h

00E000h

00C000h

00A000h

008000h

006000h

004000h

002000h

000000h

SA70 : 64KB (32KW)

SA69 : 64KB (32KW)

SA68 : 64KB (32KW)

SA67 : 64KB (32KW)

SA66 : 64KB (32KW)

SA65 : 64KB (32KW)

SA64 : 64KB (32KW)

SA63 : 64KB (32KW)

SA62 : 64KB (32KW)

SA61 : 64KB (32KW)

SA60 : 64KB (32KW)

SA59 : 64KB (32KW)

SA58 : 64KB (32KW)

SA57 : 64KB (32KW)

SA56 : 64KB (32KW)

SA55 : 64KB (32KW)

SA54 : 64KB (32KW)

SA53 : 64KB (32KW)

SA52 : 64KB (32KW)

SA51 : 64KB (32KW)

SA50 : 64KB (32KW)

SA49 : 64KB (32KW)

SA48 : 64KB (32KW)

SA47 : 64KB (32KW)

SA46 : 64KB (32KW)

SA45 : 64KB (32KW)

SA44 : 64KB (32KW)

SA43 : 64KB (32KW)

SA42 : 64KB (32KW)

SA41 : 64KB (32KW)

SA40 : 64KB (32KW)

SA39 : 64KB (32KW)

SA38 : 64KB (32KW)

SA37 : 64KB (32KW)

SA36 : 64KB (32KW)

SA35 : 64KB (32KW)

SA34 : 64KB (32KW)

SA33 : 64KB (32KW)

SA32 : 64KB (32KW)

SA31 : 64KB (32KW)

SA30 : 64KB (32KW)

SA29 : 64KB (32KW)

SA28 : 64KB (32KW)

SA27 : 64KB (32KW)

SA26 : 64KB (32KW)

SA25 : 64KB (32KW)

SA24 : 64KB (32KW)

SA23 : 64KB (32KW)

SA22 : 64KB (32KW)

SA21 : 64KB (32KW)

SA20 : 64KB (32KW)

SA19 : 64KB (32KW)

SA18 : 64KB (32KW)

SA17 : 64KB (32KW)

SA16 : 64KB (32KW)

SA15 : 64KB (32KW)

SA14 : 64KB (32KW)

SA13 : 64KB (32KW)

SA12 : 64KB (32KW)

SA11 : 64KB (32KW)

SA10 : 64KB (32KW)

SA9 : 64KB (32KW)

SA8 : 64KB (32KW)

SA7 : 8KB (4KW)

SA6 : 8KB (4KW)

SA5 : 8KB (4KW)

SA4 : 8KB (4KW)

SA3 : 8KB (4KW)

SA2 : 8KB (4KW)

SA1 : 8KB (4KW)

SA0 : 8KB (4KW)

Bank 2

MB84VD22194EB/EE

Bank 2

MB84VD22193EB/EE

Bank 2

MB84VD22192EB/EE

Bank 1

MB84VD22194EB/EE

Bank 1

MB84VD22193EB/EE

Bank 1

MB84VD22192EB/EE

MB84VD2219XEB/EE Sector Architecture (Bottom Boot Block)

10

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

Table 2.1 Sector Address Tables (MB84VD22182EB/EE)

Sector Address

Address Range Address Range

Bank Sector

Bank Address

(Byte mode)

(Word mode)

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹

SA0

SA1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

000000h to 00FFFFh

010000h to 01FFFFh

020000h to 02FFFFh

030000h to 03FFFFh

040000h to 04FFFFh

050000h to 05FFFFh

060000h to 06FFFFh

070000h to 07FFFFh

080000h to 08FFFFh

090000h to 09FFFFh

0A0000h to 0AFFFFh

000000h to 007FFFh

008000h to 00FFFFh

010000h to 017FFFh

018000h to 01FFFFh

020000h to 027FFFh

028000h to 02FFFFh

030000h to 037FFFh

038000h to 03FFFFh

040000h to 047FFFh

048000h to 04FFFFh

050000h to 057FFFh

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

0B0000h to 0BFFFFh 058000h to 05FFFFh

0C0000h to 0CFFFFh 060000h to 067FFFh

0D0000h to 0DFFFFh 068000h to 06FFFFh

0E0000h to 0EFFFFh

0F0000h to 0FFFFFh

100000h to 10FFFFh

110000h to 11FFFFh

120000h to 12FFFFh

130000h to 13FFFFh

140000h to 14FFFFh

070000h to 077FFFh

078000h to 07FFFFh

080000h to 087FFFh

088000h to 08FFFFh

090000h to 097FFFh

098000h to 09FFFFh

0A0000h to 0A7FFFh

SA15

Bank 2

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

150000h to 15FFFFh 0A8000h to 0AFFFFh

160000h to 16FFFFh 0B0000h to 0B7FFFh

170000h to 17FFFFh 0B8000h to 0BFFFFh

180000h to 18FFFFh 0C0000h to 0C7FFFh

190000h to 19FFFFh 0C8000h to 0CFFFFh

1A0000h to 1AFFFFh 0D0000h to 0D7FFFh

1B0000h to 1BFFFFh 0D8000h to 0DFFFFh

1C0000h to 1CFFFFh 0E0000h to 0E7FFFh

1D0000h to 1DFFFFh 0E8000h to 0EFFFFh

1E0000h to 1EFFFFh 0F0000h to 0F7FFFh

1F0000h to 1FFFFFh 0F8000h to 0FFFFFh

(Continued)

11

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

(Continued)

Sector Address

Address Range Address Range

Bank Sector

Bank Address

(Byte mode)

(Word mode)

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

X

0

X

0

X

200000h to 20FFFFh

210000h to 21FFFFh

220000h to 22FFFFh

230000h to 23FFFFh

240000h to 24FFFFh

250000h to 25FFFFh

260000h to 26FFFFh

270000h to 27FFFFh

280000h to 28FFFFh

290000h to 29FFFFh

2A0000h to 2AFFFFh

100000h to 107FFFh

108000h to 10FFFFh

110000h to 117FFFh

118000h to 11FFFFh

120000h to 127FFFh

128000h to 12FFFFh

130000h to 137FFFh

138000h to 13FFFFh

140000h to 147FFFh

148000h to 14FFFFh

150000h to 157FFFh

SA43

Bank 2

2B0000h to 2BFFFFh 158000h to 15FFFFh

2C0000h to 2CFFFFh 160000h to 167FFFh

2D0000h to 2DFFFFh 168000h to 16FFFFh

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

2E0000h to 2EFFFFh

2F0000h to 2FFFFFh

300000h to 30FFFFh

310000h to 31FFFFh

320000h to 32FFFFh

330000h to 33FFFFh

340000h to 34FFFFh

170000h to 177FFFh

178000h to 17FFFFh

180000h to 187FFFh

188000h to 18FFFFh

190000h to 197FFFh

198000h to 19FFFFh

1A0000h to 1A7FFFh

350000h to 35FFFFh 1A8000h to 1AFFFFh

360000h to 36FFFFh 1B0000h to 1B7FFFh

370000h to 37FFFFh 1B8000h to 1BFFFFh

380000h to 38FFFFh 1C0000h to 1C7FFFh

390000h to 39FFFFh 1C8000h to 1CFFFFh

3A0000h to 3AFFFFh 1D0000h to 1D7FFFh

3B0000h to 3BFFFFh 1D8000h to 1DFFFFh

3C0000h to 3CFFFFh 1E0000h to 1E7FFFh

3D0000h to 3DFFFFh 1E8000h to 1EFFFFh

3E0000h to 3EFFFFh 1F0000h to 1F7FFFh

Bank 1

SA63

3F0000h to 3F1FFFh

3F2000h to 3F3FFFh

1F8000h to 1F8FFFh

1F9000h to 1F9FFFh

SA64

SA65

SA66

SA67

SA68

SA69

SA70

0

1

0

1

0

3F4000h to 3F5FFFh 1FA000h to 1FAFFFh

3F6000h to 3F7FFFh 1FB000h to 1FBFFFh

3F8000h to 3F9FFFh 1FC000h to 1FCFFFh

3FA000h to 3FAFFFh 1FD000h to 1FDFFFh

3FC000h to 3FCFFFh 1FE000h to 1FEFFFh

3FE000h to 3FFFFFh 1FF000h to 1FFFFFh

0

1

0

1

0

1

0

1

12

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

Table 2.2 Sector Address Tables (MB84VD22192EB/EE)

Sector Address

Address Range Address Range

Bank Sector

Bank Address

(Byte mode)

(Word mode)

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹

SA0

SA1

SA2

SA3

SA4

SA5

SA6

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

000000h to 001FFFh

002000h to 003FFFh

004000h to 005FFFh

006000h to 007FFFh

008000h to 009FFFh

00A000h to 00BFFFh

000000h to 000FFFh

001000h to 001FFFh

002000h to 002FFFh

003000h to 003FFFh

004000h to 004FFFh

005000h to 005FFFh

0

1

0

1

0

1

0

1

0

00C000h to 00DFFFh 006000h to 006FFFh

SA7

1

00E000h to 00FFFFh

010000h to 01FFFFh

020000h to 02FFFFh

030000h to 03FFFFh

040000h to 04FFFFh

050000h to 05FFFFh

060000h to 06FFFFh

070000h to 07FFFFh

080000h to 08FFFFh

090000h to 09FFFFh

0A0000h to 0AFFFFh

007000h to 007FFFh

008000h to 00FFFFh

010000h to 017FFFh

018000h to 01FFFFh

020000h to 027FFFh

028000h to 02FFFFh

030000h to 037FFFh

038000h to 03FFFFh

040000h to 047FFFh

048000h to 04FFFFh

050000h to 057FFFh

Bank 1

SA8

X

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

0B0000h to 0BFFFFh 058000h to 05FFFFh

0C0000h to 0CFFFFh 060000h to 067FFFh

0D0000h to 0DFFFFh 068000h to 06FFFFh

0E0000h to 0EFFFFh

0F0000h to 0FFFFFh

100000h to 10FFFFh

110000h to 11FFFFh

120000h to 12FFFFh

130000h to 13FFFFh

140000h to 14FFFFh

070000h to 077FFFh

078000h to 07FFFFh

080000h to 087FFFh

088000h to 08FFFFh

090000h to 097FFFh

098000h to 09FFFFh

0A0000h to 0A7FFFh

Bank 2

150000h to 15FFFFh 0A8000h to 0AFFFFh

160000h to 16FFFFh 0B0000h to 0B7FFFh

170000h to 17FFFFh 0B8000h to 0BFFFFh

180000h to 18FFFFh 0C0000h to 0C7FFFh

190000h to 19FFFFh 0C8000h to 0CFFFFh

1A0000h to 1AFFFFh 0D0000h to 0D7FFFh

1B0000h to 1BFFFFh 0D8000h to 0DFFFFh

1C0000h to 1CFFFFh 0E0000h to 0E7FFFh

(Continued)

13

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

(Continued)

Sector Address

Address Range Address Range

Bank Sector

Bank Address

(Byte mode)

(Word mode)

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

1D0000h to 1DFFFFh 0E8000h to 0EFFFFh

1E0000h to 1EFFFFh 0F0000h to 0F7FFFh

1F0000h to 1FFFFFh 0F8000h to 0FFFFFh

200000h to 20FFFFh

210000h to 21FFFFh

220000h to 22FFFFh

230000h to 23FFFFh

240000h to 24FFFFh

250000h to 25FFFFh

260000h to 26FFFFh

270000h to 27FFFFh

280000h to 28FFFFh

290000h to 29FFFFh

2A0000h to 2AFFFFh

100000h to 107FFFh

108000h to 10FFFFh

110000h to 117FFFh

118000h to 11FFFFh

120000h to 127FFFh

128000h to 12FFFFh

130000h to 137FFFh

138000h to 13FFFFh

140000h to 147FFFh

148000h to 14FFFFh

150000h to 157FFFh

2B0000h to 2BFFFFh 158000h to 15FFFFh

2C0000h to 2CFFFFh 160000h to 167FFFh

2D0000h to 2DFFFFh 168000h to 16FFFFh

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

2E0000h to 2EFFFFh

2F0000h to 2FFFFFh

300000h to 30FFFFh

310000h to 31FFFFh

320000h to 32FFFFh

330000h to 33FFFFh

340000h to 34FFFFh

170000h to 177FFFh

178000h to 17FFFFh

180000h to 187FFFh

188000h to 18FFFFh

190000h to 197FFFh

198000h to 19FFFFh

1A0000h to 1A7FFFh

Bank 2

350000h to 35FFFFh 1A8000h to 1AFFFFh

360000h to 36FFFFh 1B0000h to 1B7FFFh

370000h to 37FFFFh 1B8000h to 1BFFFFh

380000h to 38FFFFh 1C0000h to 1C7FFFh

390000h to 39FFFFh 1C8000h to 1CFFFFh

3A0000h to 3AFFFFh 1D0000h to 1D7FFFh

3B0000h to 3BFFFFh 1D8000h to 1DFFFFh

3C0000h to 3CFFFFh 1E0000h to 1E7FFFh

3D0000h to 3DFFFFh 1E8000h to 1EFFFFh

3E0000h to 3EFFFFh 1F0000h to 1F7FFFh

3F0000h to 3FFFFFh 1F8000h to 1FFFFFh

14

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

Table 2.3 Sector Address Tables (MB84VD22183EB/EE)

Sector Address

Address Range Address Range

Bank Sector

Bank Address

(Byte mode)

(Word mode)

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹

SA0

SA1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

000000h to 00FFFFh

010000h to 01FFFFh

020000h to 02FFFFh

030000h to 03FFFFh

040000h to 04FFFFh

050000h to 05FFFFh

060000h to 06FFFFh

070000h to 07FFFFh

080000h to 08FFFFh

090000h to 09FFFFh

0A0000h to 0AFFFFh

000000h to 007FFFh

008000h to 00FFFFh

010000h to 017FFFh

018000h to 01FFFFh

020000h to 027FFFh

028000h to 02FFFFh

030000h to 037FFFh

038000h to 03FFFFh

040000h to 047FFFh

048000h to 04FFFFh

050000h to 057FFFh

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

0B0000h to 0BFFFFh 058000h to 05FFFFh

0C0000h to 0CFFFFh 060000h to 067FFFh

0D0000h to 0DFFFFh 068000h to 06FFFFh

0E0000h to 0EFFFFh

0F0000h to 0FFFFFh

100000h to 10FFFFh

110000h to 11FFFFh

120000h to 12FFFFh

130000h to 13FFFFh

140000h to 14FFFFh

070000h to 077FFFh

078000h to 07FFFFh

080000h to 087FFFh

088000h to 08FFFFh

090000h to 097FFFh

098000h to 09FFFFh

0A0000h to 0A7FFFh

SA15

Bank 2

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

150000h to 15FFFFh 0A8000h to 0AFFFFh

160000h to 16FFFFh 0B0000h to 0B7FFFh

170000h to 17FFFFh 0B8000h to 0BFFFFh

180000h to 18FFFFh 0C0000h to 0C7FFFh

190000h to 19FFFFh 0C8000h to 0CFFFFh

1A0000h to 1AFFFFh 0D0000h to 0D7FFFh

1B0000h to 1BFFFFh 0D8000h to 0DFFFFh

1C0000h to 1CFFFFh 0E0000h to 0E7FFFh

1D0000h to 1DFFFFh 0E8000h to 0EFFFFh

1E0000h to 1EFFFFh 0F0000h to 0F7FFFh

1F0000h to 1FFFFFh 0F8000h to 0FFFFFh

(Continued)

15

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

(Continued)

Sector Address

Address Range Address Range

Bank Sector

Bank Address

(Byte mode)

(Word mode)

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹

SA32

SA33

SA34

SA35

SA36

SA37

SA38

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

X

0

X

0

X

200000h to 20FFFFh

210000h to 21FFFFh

220000h to 22FFFFh

230000h to 23FFFFh

240000h to 24FFFFh

250000h to 25FFFFh

260000h to 26FFFFh

270000h to 27FFFFh

280000h to 28FFFFh

290000h to 29FFFFh

2A0000h to 2AFFFFh

100000h to 107FFFh

108000h to 10FFFFh

110000h to 117FFFh

118000h to 11FFFFh

120000h to 127FFFh

128000h to 12FFFFh

130000h to 137FFFh

138000h to 13FFFFh

140000h to 147FFFh

148000h to 14FFFFh

150000h to 157FFFh

SA39

Bank 2

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

2B0000h to 2BFFFFh 158000h to 15FFFFh

2C0000h to 2CFFFFh 160000h to 167FFFh

2D0000h to 2DFFFFh 168000h to 16FFFFh

2E0000h to 2EFFFFh

2F0000h to 2FFFFFh

300000h to 30FFFFh

310000h to 31FFFFh

320000h to 32FFFFh

330000h to 33FFFFh

340000h to 34FFFFh

170000h to 177FFFh

178000h to 17FFFFh

180000h to 187FFFh

188000h to 18FFFFh

190000h to 197FFFh

198000h to 19FFFFh

1A0000h to 1A7FFFh

350000h to 35FFFFh 1A8000h to 1AFFFFh

360000h to 36FFFFh 1B0000h to 1B7FFFh

370000h to 37FFFFh 1B8000h to 1BFFFFh

380000h to 38FFFFh 1C0000h to 1C7FFFh

390000h to 39FFFFh 1C8000h to 1CFFFFh

3A0000h to 3AFFFFh 1D0000h to 1D7FFFh

3B0000h to 3BFFFFh 1D8000h to 1DFFFFh

3C0000h to 3CFFFFh 1E0000h to 1E7FFFh

3D0000h to 3DFFFFh 1E8000h to 1EFFFFh

3E0000h to 3EFFFFh 1F0000h to 1F7FFFh

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

Bank 1

3F0000h to 3F1FFFh

3F2000h to 3F3FFFh

1F8000h to 1F8FFFh

1F9000h to 1F9FFFh

0

1

0

1

0

3F4000h to 3F5FFFh 1FA000h to 1FAFFFh

3F6000h to 3F7FFFh 1FB000h to 1FBFFFh

3F8000h to 3F9FFFh 1FC000h to 1FCFFFh

3FA000h to 3FAFFFh 1FD000h to 1FDFFFh

3FC000h to 3FCFFFh 1FE000h to 1FEFFFh

3FE000h to 3FFFFFh 1FF000h to 1FFFFFh

0

1

0

1

0

1

0

1

16

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

Table 2.4 Sector Address Tables (MB84VD22193EB/EE)

Sector Address

Address Range Address Range

Bank Sector

Bank Address

(Byte mode)

(Word mode)

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

000000h to 001FFFh

002000h to 003FFFh

004000h to 005FFFh

006000h to 007FFFh

008000h to 009FFFh

00A000h to 00BFFFh

000000h to 000FFFh

001000h to 001FFFh

002000h to 002FFFh

003000h to 003FFFh

004000h to 004FFFh

005000h to 005FFFh

0

1

0

1

0

1

0

1

0

00C000h to 00DFFFh 006000h to 006FFFh

1

00E000h to 00FFFFh

010000h to 01FFFFh

020000h to 02FFFFh

030000h to 03FFFFh

040000h to 04FFFFh

050000h to 05FFFFh

060000h to 06FFFFh

070000h to 07FFFFh

080000h to 08FFFFh

090000h to 09FFFFh

0A0000h to 0AFFFFh

007000h to 007FFFh

008000h to 00FFFFh

010000h to 017FFFh

018000h to 01FFFFh

020000h to 027FFFh

028000h to 02FFFFh

030000h to 037FFFh

038000h to 03FFFFh

040000h to 047FFFh

048000h to 04FFFFh

050000h to 057FFFh

X

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

Bank 1

0B0000h to 0BFFFFh 058000h to 05FFFFh

0C0000h to 0CFFFFh 060000h to 067FFFh

0D0000h to 0DFFFFh 068000h to 06FFFFh

0E0000h to 0EFFFFh

0F0000h to 0FFFFFh

100000h to 10FFFFh

110000h to 11FFFFh

120000h to 12FFFFh

130000h to 13FFFFh

140000h to 14FFFFh

070000h to 077FFFh

078000h to 07FFFFh

080000h to 087FFFh

088000h to 08FFFFh

090000h to 097FFFh

098000h to 09FFFFh

0A0000h to 0A7FFFh

150000h to 15FFFFh 0A8000h to 0AFFFFh

160000h to 16FFFFh 0B0000h to 0B7FFFh

Bank 2

170000h to 17FFFFh 0B8000h to 0BFFFFh

180000h to 18FFFFh 0C0000h to 0C7FFFh

190000h to 19FFFFh 0C8000h to 0CFFFFh

1A0000h to 1AFFFFh 0D0000h to 0D7FFFh

1B0000h to 1BFFFFh 0D8000h to 0DFFFFh

1C0000h to 1CFFFFh 0E0000h to 0E7FFFh

(Continued)

17

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

(Continued)

Sector Address

Address Range Address Range

Bank Sector

Bank Address

(Byte mode)

(Word mode)

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

1D0000h to 1DFFFFh 0E8000h to 0EFFFFh

1E0000h to 1EFFFFh 0F0000h to 0F7FFFh

1F0000h to 1FFFFFh 0F8000h to 0FFFFFh

200000h to 20FFFFh

210000h to 21FFFFh

220000h to 22FFFFh

230000h to 23FFFFh

240000h to 24FFFFh

250000h to 25FFFFh

260000h to 26FFFFh

270000h to 27FFFFh

280000h to 28FFFFh

290000h to 29FFFFh

2A0000h to 2AFFFFh

100000h to 107FFFh

108000h to 10FFFFh

110000h to 117FFFh

118000h to 11FFFFh

120000h to 127FFFh

128000h to 12FFFFh

130000h to 137FFFh

138000h to 13FFFFh

140000h to 147FFFh

148000h to 14FFFFh

150000h to 157FFFh

2B0000h to 2BFFFFh 158000h to 15FFFFh

2C0000h to 2CFFFFh 160000h to 167FFFh

2D0000h to 2DFFFFh 168000h to 16FFFFh

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

2E0000h to 2EFFFFh

2F0000h to 2FFFFFh

300000h to 30FFFFh

310000h to 31FFFFh

320000h to 32FFFFh

330000h to 33FFFFh

340000h to 34FFFFh

170000h to 177FFFh

178000h to 17FFFFh

180000h to 187FFFh

188000h to 18FFFFh

190000h to 197FFFh

198000h to 19FFFFh

1A0000h to 1A7FFFh

Bank 2

350000h to 35FFFFh 1A8000h to 1AFFFFh

360000h to 36FFFFh 1B0000h to 1B7FFFh

370000h to 37FFFFh 1B8000h to 1BFFFFh

380000h to 38FFFFh 1C0000h to 1C7FFFh

390000h to 39FFFFh 1C8000h to 1CFFFFh

3A0000h to 3AFFFFh 1D0000h to 1D7FFFh

3B0000h to 3BFFFFh 1D8000h to 1DFFFFh

3C0000h to 3CFFFFh 1E0000h to 1E7FFFh

3D0000h to 3DFFFFh 1E8000h to 1EFFFFh

3E0000h to 3EFFFFh 1F0000h to 1F7FFFh

3F0000h to 3FFFFFh 1F8000h to 1FFFFFh

18

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

Table 2.5 Sector Address Tables (MB84VD22184EB/EE)

Sector Address

Address Range Address Range

Bank Sector

Bank Address

(Byte mode)

(Word mode)

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹

SA0

SA1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

000000h to 00FFFFh

010000h to 01FFFFh

020000h to 02FFFFh

030000h to 03FFFFh

040000h to 04FFFFh

050000h to 05FFFFh

060000h to 06FFFFh

070000h to 07FFFFh

080000h to 08FFFFh

090000h to 09FFFFh

0A0000h to 0AFFFFh

000000h to 007FFFh

008000h to 00FFFFh

010000h to 017FFFh

018000h to 01FFFFh

020000h to 027FFFh

028000h to 02FFFFh

030000h to 037FFFh

038000h to 03FFFFh

040000h to 047FFFh

048000h to 04FFFFh

050000h to 057FFFh

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

0B0000h to 0BFFFFh 058000h to 05FFFFh

0C0000h to 0CFFFFh 060000h to 067FFFh

0D0000h to 0DFFFFh 068000h to 06FFFFh

0E0000h to 0EFFFFh

0F0000h to 0FFFFFh

100000h to 10FFFFh

110000h to 11FFFFh

120000h to 12FFFFh

130000h to 13FFFFh

140000h to 14FFFFh

070000h to 077FFFh

078000h to 07FFFFh

080000h to 087FFFh

088000h to 08FFFFh

090000h to 097FFFh

098000h to 09FFFFh

0A0000h to 0A7FFFh

SA15

Bank 2

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

150000h to 15FFFFh 0A8000h to 0AFFFFh

160000h to 16FFFFh 0B0000h to 0B7FFFh

170000h to 17FFFFh 0B8000h to 0BFFFFh

180000h to 18FFFFh 0C0000h to 0C7FFFh

190000h to 19FFFFh 0C8000h to 0CFFFFh

1A0000h to 1AFFFFh 0D0000h to 0D7FFFh

1B0000h to 1BFFFFh 0D8000h to 0DFFFFh

1C0000h to 1CFFFFh 0E0000h to 0E7FFFh

1D0000h to 1DFFFFh 0E8000h to 0EFFFFh

1E0000h to 1EFFFFh 0F0000h to 0F7FFFh

1F0000h to 1FFFFFh 0F8000h to 0FFFFFh

(Continued)

19

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

(Continued)

Sector Address

Address Range Address Range

Bank Sector

Bank Address

(Byte mode)

(Word mode)

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

X

0

X

0

X

200000h to 20FFFFh

210000h to 21FFFFh

220000h to 22FFFFh

230000h to 23FFFFh

240000h to 24FFFFh

250000h to 25FFFFh

260000h to 26FFFFh

270000h to 27FFFFh

280000h to 28FFFFh

290000h to 29FFFFh

2A0000h to 2AFFFFh

100000h to 107FFFh

108000h to 10FFFFh

110000h to 117FFFh

118000h to 11FFFFh

120000h to 127FFFh

128000h to 12FFFFh

130000h to 137FFFh

138000h to 13FFFFh

140000h to 147FFFh

148000h to 14FFFFh

150000h to 157FFFh

2B0000h to 2BFFFFh 158000h to 15FFFFh

2C0000h to 2CFFFFh 160000h to 167FFFh

2D0000h to 2DFFFFh 168000h to 16FFFFh

2E0000h to 2EFFFFh

2F0000h to 2FFFFFh

300000h to 30FFFFh

310000h to 31FFFFh

320000h to 32FFFFh

330000h to 33FFFFh

340000h to 34FFFFh

170000h to 177FFFh

178000h to 17FFFFh

180000h to 187FFFh

188000h to 18FFFFh

190000h to 197FFFh

198000h to 19FFFFh

1A0000h to 1A7FFFh

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

Bank 1

350000h to 35FFFFh 1A8000h to 1AFFFFh

360000h to 36FFFFh 1B0000h to 1B7FFFh

370000h to 37FFFFh 1B8000h to 1BFFFFh

380000h to 38FFFFh 1C0000h to 1C7FFFh

390000h to 39FFFFh 1C8000h to 1CFFFFh

3A0000h to 3AFFFFh 1D0000h to 1D7FFFh

3B0000h to 3BFFFFh 1D8000h to 1DFFFFh

3C0000h to 3CFFFFh 1E0000h to 1E7FFFh

3D0000h to 3DFFFFh 1E8000h to 1EFFFFh

3E0000h to 3EFFFFh 1F0000h to 1F7FFFh

3F0000h to 3F1FFFh

3F2000h to 3F3FFFh

1F8000h to 1F8FFFh

1F9000h to 1F9FFFh

0

1

0

1

0

3F4000h to 3F5FFFh 1FA000h to 1FAFFFh

3F6000h to 3F7FFFh 1FB000h to 1FBFFFh

3F8000h to 3F9FFFh 1FC000h to 1FCFFFh

3FA000h to 3FAFFFh 1FD000h to 1FDFFFh

3FC000h to 3FCFFFh 1FE000h to 1FEFFFh

3FE000h to 3FFFFFh 1FF000h to 1FFFFFh

0

1

0

1

0

1

0

1

20

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

Table 2.6 Sector Address Tables (MB84VD22194EB/EE)

Sector Address

Address Range Address Range

Bank Sector

Bank Address

(Byte mode)

(Word mode)

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹

SA0

SA1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

000000h to 001FFFh

002000h to 003FFFh

004000h to 005FFFh

006000h to 007FFFh

008000h to 009FFFh

00A000h to 00BFFFh

000000h to 000FFFh

001000h to 001FFFh

002000h to 002FFFh

003000h to 003FFFh

004000h to 004FFFh

005000h to 005FFFh

SA2

0

1

0

SA3

0

1

SA4

1

0

SA5

1

0

1

SA6

1

0

00C000h to 00DFFFh 006000h to 006FFFh

SA7

1

00E000h to 00FFFFh

010000h to 01FFFFh

020000h to 02FFFFh

030000h to 03FFFFh

040000h to 04FFFFh

050000h to 05FFFFh

060000h to 06FFFFh

070000h to 07FFFFh

080000h to 08FFFFh

090000h to 09FFFFh

0A0000h to 0AFFFFh

007000h to 007FFFh

008000h to 00FFFFh

010000h to 017FFFh

018000h to 01FFFFh

020000h to 027FFFh

028000h to 02FFFFh

030000h to 037FFFh

038000h to 03FFFFh

040000h to 047FFFh

048000h to 04FFFFh

050000h to 057FFFh

SA8

X

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

Bank 1

0B0000h to 0BFFFFh 058000h to 05FFFFh

0C0000h to 0CFFFFh 060000h to 067FFFh

0D0000h to 0DFFFFh 068000h to 06FFFFh

0E0000h to 0EFFFFh

0F0000h to 0FFFFFh

100000h to 10FFFFh

110000h to 11FFFFh

120000h to 12FFFFh

130000h to 13FFFFh

140000h to 14FFFFh

070000h to 077FFFh

078000h to 07FFFFh

080000h to 087FFFh

088000h to 08FFFFh

090000h to 097FFFh

098000h to 09FFFFh

0A0000h to 0A7FFFh

150000h to 15FFFFh 0A8000h to 0AFFFFh

160000h to 16FFFFh 0B0000h to 0B7FFFh

170000h to 17FFFFh 0B8000h to 0BFFFFh

180000h to 18FFFFh 0C0000h to 0C7FFFh

190000h to 19FFFFh 0C8000h to 0CFFFFh

1A0000h to 1AFFFFh 0D0000h to 0D7FFFh

1B0000h to 1BFFFFh 0D8000h to 0DFFFFh

(Continued)

21

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

(Continued)

Sector Address

Address Range Address Range

Bank Sector

Bank Address

(Byte mode)

(Word mode)

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹

SA35

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

1C0000h to 1CFFFFh 0E0000h to 0E7FFFh

1D0000h to 1DFFFFh 0E8000h to 0EFFFFh

1E0000h to 1EFFFFh 0F0000h to 0F7FFFh

1F0000h to 1FFFFFh 0F8000h to 0FFFFFh

SA36

Bank 1

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

200000h to 20FFFFh

210000h to 21FFFFh

220000h to 22FFFFh

230000h to 23FFFFh

240000h to 24FFFFh

250000h to 25FFFFh

260000h to 26FFFFh

270000h to 27FFFFh

280000h to 28FFFFh

290000h to 29FFFFh

2A0000h to 2AFFFFh

100000h to 107FFFh

108000h to 10FFFFh

110000h to 117FFFh

118000h to 11FFFFh

120000h to 127FFFh

128000h to 12FFFFh

130000h to 137FFFh

138000h to 13FFFFh

140000h to 147FFFh

148000h to 14FFFFh

150000h to 157FFFh

2B0000h to 2BFFFFh 158000h to 15FFFFh

2C0000h to 2CFFFFh 160000h to 167FFFh

2D0000h to 2DFFFFh 168000h to 16FFFFh

2E0000h to 2EFFFFh

2F0000h to 2FFFFFh

300000h to 30FFFFh

310000h to 31FFFFh

320000h to 32FFFFh

330000h to 33FFFFh

340000h to 34FFFFh

170000h to 177FFFh

178000h to 17FFFFh

180000h to 187FFFh

188000h to 18FFFFh

190000h to 197FFFh

198000h to 19FFFFh

1A0000h to 1A7FFFh

SA54

Bank 2

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

350000h to 35FFFFh 1A8000h to 1AFFFFh

360000h to 36FFFFh 1B0000h to 1B7FFFh

370000h to 37FFFFh 1B8000h to 1BFFFFh

380000h to 38FFFFh 1C0000h to 1C7FFFh

390000h to 39FFFFh 1C8000h to 1CFFFFh

3A0000h to 3AFFFFh 1D0000h to 1D7FFFh

3B0000h to 3BFFFFh 1D8000h to 1DFFFFh

3C0000h to 3CFFFFh 1E0000h to 1E7FFFh

3D0000h to 3DFFFFh 1E8000h to 1EFFFFh

3E0000h to 3EFFFFh 1F0000h to 1F7FFFh

3F0000h to 3FFFFFh 1F8000h to 1FFFFFh

22

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

Table 3.1 Sector Group Address (MB84VD2218XEB/EE)

(Top Boot Block)

Sector Group

A²⁰

A¹⁹

A¹⁸

A¹⁷

A¹⁶

0

A¹⁵

0

A¹⁴

A¹³

A¹²

Sectors

SGA0

0

X

SA0

0

1

SGA1

0

1

0

X

SA1 to SA3

1

SGA2

SGA3

SGA4

SGA5

SGA6

SGA7

SGA8

SGA9

SGA10

SGA11

SGA12

SGA13

SGA14

SGA15

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

0

X

0

X

SA4 to SA7

SA8 to SA11

SA12 to SA15

SA16 to SA19

SA20 to SA23

SA24 to SA27

SA28 to SA31

SA32 to SA35

SA36 to SA39

SA40 to SA43

SA44 to SA47

SA48 to SA51

SA52 to SA55

SA56 to SA59

SGA16

1

0

1

X

SA60 to SA62

1

0

SGA17

SGA18

SGA19

SGA20

SGA21

SGA22

SGA23

SGA24

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

1

23

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

Table 3.2 Sector Group Address (MB84VD2219XEB/EE)

(Bottom Boot Block)

Sector Group

SGA0

A²⁰

0

A¹⁹

0

A¹⁸

0

A¹⁷

0

A¹⁶

0

A¹⁵

0

A¹⁴

0

A¹³

0

A¹²

0

Sectors

SA0

SGA1

0

1

SA1

SGA2

0

1

0

SA2

SGA3

0

1

SA3

SGA4

0

1

0

SA4

SGA5

0

1

0

1

SA5

SGA6

0

1

0

SA6

SGA7

0

1

SA7

0

1

SGA8

0

1

0

X

SA8 to SA10

1

SGA9

SGA10

SGA11

SGA12

SGA13

SGA14

SGA15

SGA16

SGA17

SGA18

SGA19

SGA20

SGA21

SGA22

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

0

X

0

X

SA11 to SA14

SA15 to SA18

SA19 to SA22

SA23 to SA26

SA27 to SA30

SA31 to SA34

SA35 to SA38

SA39 to SA42

SA43 to SA46

SA47 to SA50

SA51 to SA54

SA55 to SA58

SA59 to SA62

SA63 to SA66

SGA23

SGA24

1

0

1

X

SA67 to SA69

SA70

1

0

1

24

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

Table 4 Flash Memory Autoselect Codes

Type

A¹²to A¹⁹

A⁶

A¹

A⁰

A^–1*¹

V^IL

X

Code (HEX)

04h

Manufacturer’s Code

X

V^IL

Byte

Word

Byte

55h

MB84VD22182EB

MB84VD22182EE

X

V^IL

V^IH

2255h

56h

V^IL

X

MB84VD22192EB

MB84VD22192EE

Word

Byte

2256h

50h

V^IL

X

MB84VD22183EB

MB84VD22183EE

Word

Byte

2250h

53h

Device

Code

V^IL

X

MB84VD22193EB

MB84VD22193EE

Word

Byte

2253h

5Ch

V^IL

X

MB84VD22184EB

MB84VD22184EE

Word

Byte

225Ch

5Fh

V^IL

X

MB84VD22194EB

MB84VD22194EE

V^IL

V^IH

V^IL

Word

225Fh

Sector Group

Address

Sector Group protect

V^IL

01h*²

*1: A^–1is for Byte mode.

*2: Output 01h at protected sector address and output 00h at unprotected sector address.

25

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

Table 5 Flash Memory Command Definitions

Fourth Bus

Bus

Write

Cycles

Req’d

First Bus

Second Bus

Write Cycle

Third Bus

Fifth Bus

Sixth Bus

Read/Write

Cycle

Command

Sequence

Write Cycle

Write Cycle Write Cycle

Addr. Data Addr. Data

Addr. Data Addr. Data Addr. Data Addr. Data

1

3

XXXh F0h

—

Read/Reset *

Word

Byte

555h

AAh

2AAh

555h

AAAh

1

55h

F0h

RA

RD

—

Read/Reset*

AAAh

(BA)

555h

Word

Byte

555h

AAh

2AAh

555h

Autoselect

3

55h

90h

—

(BA)

AAAh

Word

Byte

Word

Byte

Word

Byte

555h

AAh

2AAh

555h

2AAh

555h

2AAh

555h

—

555h

AAAh

555h

AAAh

555h

AAAh

—

Program

4

6

55h

A0h

80h

PA

PD

—

AAAh

555h

AAh

555h

AAAh

555h

AAAh

—

2AAh

555h

2AAh

555h

—

555h

Chip Erase

AAh

55h

10h

30h

AAAh

555h

AAh

Sector Erase

SA

AAAh

Sector Erase Suspend

Sector Erase Resume

1

BA

B0h

30h

—

Word

Byte

Word

Byte

Word

Byte

555h

AAAh

2AAh

555h

AAAh

Set to

Fast Mode

3

2

AAh

55h

PD

20h

—

Fast Program *²

XXXh A0h

BA

PA

—

Reset from Fast

Mode*²

F0h*⁶

90h XXXh

—

Word

Byte

Extended

Sector Group

4

XXXh 60h SPA

55h

60h

SPA

40h SPA

SD

—

Protection*³

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Query*⁴

1

3

4

6

98h

AAh

—

AAh

555h

AAAh

555h

AAAh

555h

AAAh

2AAh

555h

2AAh

555h

2AAh

555h

AAAh

555h

AAAh

555h

AAAh

Hi-ROM Entry

55h

88h

A0h

80h

Hi-ROM

Program*⁵

PA

PD

AAh

555h

2AAh

555h

Hi-ROM

Erase*⁵

55h HRA 30h

AAAh

(HRBA)

555h

Word

Byte

555h

2AAh

555h

Hi-ROM Exit*⁵

4

AAh

55h

90h XXXh 00h

—

(HRBA)

AAAh

*1 : Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.

*2 : This command is valid while Fast Mode.

*3 : This command is valid while RESET=V^ID.

*4 : The valid Address is A⁰to A⁶.

*5 : This command is valid while Hi-ROM mode.

*6 : The data “00h” is also acceptable.

26

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

Address bits A¹¹to A²⁰= X = “H” or “L” for all address commands except for Program Address (PA),

Sector Address (SA) and Bank Address (BA).

Bus operations are defined in Table 2 "User Bus Operations".

RA = Address of the memory location to be read

PA = Address of the memory location to be programmed

Addresses are latched on the falling edge of the write pulse.

SA = Address of the sector to be erased

The combination of A²⁰, A¹⁹, A¹⁸, A¹⁷, A¹⁶, A¹⁵, A¹⁴, A¹³, and A¹²will uniquely select any sector.

BA = Bank address (A¹⁵to A²⁰)

SPA = Sector group address to be protected

Set sector group address (SGA) and (A⁶, A¹, A⁰) = (0, 1, 0).

HRA= Address of the Hidden-ROM area

MB84VD2218XEB/EE (Top Boot Type)

Word mode: 1F8000h to 1FFFFFh

Byte mode: 3F0000h to 3FFFFFh

MB84VD2219XEB/EE (Bottom Boot Type) Word mode: 000000h to 007FFFh

Byte mode: 000000h to 00FFFFh

HRBA = Bank address of the Hidden-ROM area

MB84VD2218XEB/EE (Top Boot Type)

: A¹⁵= A¹⁶= A¹⁷= A¹⁸= A¹⁹= A²⁰= 1

MB84VD2219XEB/EE (Bottom Boot Type) : A¹⁵= A¹⁶= A¹⁷= A¹⁸= A¹⁹= A²⁰= 0

RD = Data read from location RA during read operation

PD = Data to be programmed at location PA

SD = Sector protection verify data

Output 01h at protected sector addresses and output 00h at unprotected sector addresses.

The system should generate the following address patterns;

Word mode : 555h or 2AAh to addresses A⁰to A¹⁰

Byte mode : AAAh or 555h to addresses A^–1and A⁰to A¹⁰

27

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

■ ABSOLUTE MAXIMUM RATINGS

Rating

Parameter

Symbol

Unit

Min.

–55

–25

Max.

+125

Storage Temperature

Ambient Temperature with Power Applied

Tstg

T^A

°C

V

+85

1

V^CCf +0.4

V^CCs +0.4

+4.0

Voltage with Respect to Ground All pins *

except RESET and WP/ACC

V^IN, V^OUT

–0.3

V

1

V^CCf/V^CCs Supply *

V^CCf, V^CCs

V^IN

–0.3

–0.5

V

2

RESET *

+ 13.0

+10.5

V

3

WP/ACC *

V^IN

V

*1 : Minimum DC voltage on input or I/O pins is –0.3 V. During voltage transitions, input or I/O pins may undershoot

V^SSto –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is V^CCf +0.4 V or V^CCs+0.4 V.

During voltage transitions, input or I/O pins may overshoot to V^CCf+2.0 V or V^CCs+2.0 V for periods of up to 20 ns.

*2 : Minimum DC input voltage on RESET pin is –0.5 V. During voltage transitions, RESET pins may undershoot

V^SSto –2.0 V for periods of up to 20 ns.

Voltage difference between input and supply voltage (VIN-V^CCf or V^CCs) does not exceed 9.0 V.

Maximum DC input voltage on RESET pin is +13.0 V which may overshoot to 14.0 V for periods of up to 20 ns.

*3 : Minimum DC input voltage on WP/ACC pin is –0.5 V. During voltage transitions, WP/ACC pin may undershoot

Vss to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may

overshoot to 12.0 V for periods of up to 20 ns, when V^CCf is applied.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■ RECOMMENDED OPERATING CONDITIONS

Value

Parameter

Symbol

Unit

Min.

–25

Max.

+85

Ambient Temperature

V^CCf/V^CCs Supply Voltages

T^A

°C

V

V^CCf, V^CCs

+2.7

+3.3

Note: Operating ranges define those limits between which the functionality of the device is guaranteed.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

28

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

■ ELECTRICAL CHARACTERISTICS

1. DC Characteristics

Value

Symbol

Parameter

Test Conditions

V^IN= V^SSto V^CCf, V^CCs

Unit

Min.

–1.0

Typ.

—

Max.

+1.0

Input Leakage Current

Output Leakage Current

I^LI

µA

I^LO

V^OUT= V^SSto V^CCf, V^CCs

—

RESET Inputs Leakage

Current

V^CCf= V^CCf Max., V^CCs= V^CCs Max.,

RESET = 12.5V

I^LIT

I^LIA

—

35

20

µA

ACC Input Leakage

Current

V^CCf= V^CCf Max.,V^CCs= V^CCs Max.,

WP/ACC = V^ACCMax.

mA

t^CYCLE= 5 MHz Byte

—

16

18

7

mA

t^CYCLE= 5 MHz Word

t^CYCLE= 1 MHz Byte

t^CYCLE= 1 MHz Word

Flash V^CCActive Current

CEf = V^IL,

OE = V^IH

I^CC1f

1

(Read)*

mA

7

Flash V^CCActive Current

I^CC2f

I^CC3f

CEf = V^IL, OE = V^IH

—

35

2

(Program / Erase) *

Byte

Word

Byte

Word

—

51

53

51

53

Flash V^CCActive Current

5

(Read-While-Program)*

Flash V^CCActive Current

I^CC4f

I^CC5f

CEf = V^IL, OE = V^IH

mA

5

(Read-While-Erase)*

Flash V^CCActive Current

(Erase-Suspend-Program)

—

35

40

V^CCs = V^CCMax.,

CE1s = V^IL,

SRAM V^CCActive Current

Flash V^CCStandby Current

I^CC1s

t^CYCLE=10 MHz

mA

CE2s = V^IH

CE1s = 0.2 V,

I^CC2s CE2s = V^CCs – 0.2 V

t^CYCLE= 10 MHz

t^CYCLE= 1 MHz

—

40

8

mA

V^CCf = V^CCMax., CEf = V^CCf ± 0.3 V,

I^SB1f

RESET = V^CCf ± 0.3 V,

—

1

5

µA

WP/ACC = V^CCf ± 0.3 V

Flash V^CCStandby Current

(RESET)

V^CCf = V^CCMax., RESET = V^SS± 0.3 V,

WP/ACC = V^CCf± 0.3 V

I^SB2f

V^CCf = V^CCMax., CEf = V^SS± 0.3 V,

RESET = V^CCf ± 0.3 V,

Flash V^CCCurrent

(Automatic Sleep Mode)*

I^SB3f

—

1

5

µA

3

WP/ACC = V^CCf ± 0.3 V

V^IN= V^CCf± 0.3 V or V^SS± 0.3 V

SRAM V^CCStandby Current

I^SB1s

CE1s > V^CCs – 0.2 V, CE2s > V^CCs – 0.2 V

—

7

µA

SRAM V^CCStandby Current I^SB2s CE2s < 0.2 V

(Continued)

29

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

(Continued)

Value

Symbol

Parameter

Test Conditions

Unit

Min.

–0.3

2.4

Typ.

—

Max.

0.5

Input Low Level

V^IL

V^IH

—

V

V^CC+0.3*⁶

Input High Level

—

Voltage for Sector

Protection, and Temporary

Sector Unprotection

V^ID

—

11.5

—

12.5

V

4

(RESET)*

Voltage for Program

Acceleration (WP/ACC) *

V^ACC

V^OL

—

8.5

—

9.0

—

9.5

0.4

—

V

4

V^CCf = V^CCf Min.,V^CCs = V^CCs Min.,

I^OL=1.0 mA

Output Low Voltage Level

Output High Voltage Level

V^CCf = V^CCf Min.,V^CCs = V^CCs Min.,

I^OH=-0.5 mA

V^OH

V^LKO

2.4

2.3

Flash Low V^CCf Lock-Out

Voltage

—

2.5

*1 : The I^CCcurrent listed includes both the DC operating current and the frequency dependent component.

*2 : I^CCactive while Embedded Algorithm (program or erase) is in progress.

*3 : Automatic sleep mode enables the low power mode when address remain stable for 150 ns.

*4 : Applicable for only V^CCf applying.

*5 : Embedded Algorithm (program or erase) is in progress (@5 MHz).

*6 : V^CCindicates lower of V^CCf or V^CCs.

30

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

2. AC Characteristics

• CE Timing

Symbol

Value

Parameter

CE Recover Time

Test Setup

Unit

JEDEC Standard

Min.

Max.

—

t^CCR

—

0

—

ns

• Timing Diagram for alternating SRAM to Flash

CEf

t^CCR

CE1s

CE2s

t^CCR

31

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

• Read Only Operations Characteristics (Flash)

Value (Note)

Symbol

Test

Parameter

-85

-90

Unit

Setup

JEDEC Standard

Min.

Max.

Min.

Max.

Read Cycle Time

tAVAV

t^RC

—

85

—

90

—

ns

CEf = V^IL

OE = V^IL

Address to Output Delay

t^AVQV

t^ACC

—

85

—

90

Chip Enable to Output Delay

Output Enable to Output Delay

Chip Enable to Output High-Z

Output Enable to Output High-Z

t^ELQV

t^GLQV

t^EHQZ

t^GHQZ

t^CEf

t^OE

t^DF

OE = V^IL

—

85

35

30

—

90

40

30

ns

—

Output Hold Time From Addresses,

CEf or OE, Whichever Occurs First

t^AXQX

—

t^OH

—

0

—

0

—

ns

µs

RESET Pin Low to Read Mode

t^READY

—

20

—

20

Note: Test Conditions–Output Load: 1 TTL gate and 30 pF

Input rise and fall times: 5 ns

Input pulse levels: 0.0 V or 3.0 V

Timing measurement reference level

Input: 1.5 V

Output: 1.5 V

32

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

• Read Cycle (Flash)

t^RC

Address Stable

Address

t^ACC

CEf

t^OE

t^DF

OE

t^OEH

WE

DQ

t^CEf

High-Z

Output Valid

t^RC

Address

CEf

Address Stable

t^ACC

t^RH

t^CEf

t^RP

RESET

DQ

t^OH

High-Z

Output Valid

33

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

• Erase/Program Operations (Flash)

Value

Symbol

Parameter

Unit

-85

-90

JEDEC Standard

Min. Typ. Max. Min. Typ. Max.

Write Cycle Time

t^AVAV

tAVWL

—

tWC

tAS

85

0

—

90

0

—

ns

Address Setup Time (WE to Addr.)

Address Setup Time to CEf Low During Toggle Bit Polling

Address Hold Time (WE to Addr.)

tASO

tAH

15

45

15

45

tWLAX

Address Hold Time from CE or OE High During Toggle Bit

Polling

—

tAHT

0

—

0

—

ns

Data Setup Time

tDVWH

t^WHDX

—

tDS

tDH

35

0

—

8

—

35

0

—

8

—

ns

µs

s

Data Hold Time

Output Enable Setup Time

t^OES

0

Read

Output Enable Hold Time

0

—

t^OEH

Toggle and Data Polling

10

20

0

10

20

0

CEf High During Toggle Bit Polling

OE High During Toggle Bit Polling

Read Recover Time Before Write (OE to CEf)

Read Recover Time Before Write (OE to WE)

WE Setup Time (CEf to WE)

CEf Setup Time (WE to CEf)

WE Hold Time (CEf to WE)

CEf Hold Time (WE to CEf)

Write Pulse Width

—

tCEPH

tOEPH

tGHEL

tGHWL

tWS

—

tGHEL

tGHWL

tWLEL

tELWL

tEHWH

tWHEH

t^WLWH

tELEH

t^WHWL

tEHEL

0

tCS

0

tWH

0

tCH

0

tWP

35

30

—

35

30

—

CEf Pulse Width

tCP

Write Pulse Width High

tWPH

tCPH

CEf Pulse Width High

Byte Programming Operation

Word Programming Operation

t^WHWH1

tWHWH1

tWHWH2

16

1

16

1

tWHWH2

Sector Erase Operation *

(Continued)

34

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

(Continued)

Value

Symbol

Parameter

Unit

-85

-90

JEDEC Standard

Min. Typ. Max. Min. Typ. Max.

V^CCf Setup Time

—

tVCS

50

4

—

85

—

90

—

20

50

4

—

90

—

90

—

20

µs

ns

µs

2

tVLHT

Voltage Transition Time *

2

tVIDR

tVACCR

tRB

500

0

500

0

Rise Time to V^ID

*

Rise Time to V^ACC

Recover Time from RY/BY

RESET Pulse Width

tRP

500

—

500

—

Delay Time from Embedded Output Enable

RESET High Level Period Before Read

Program/Erase Valid to RY/BY Delay

tEOE

tRH

200

—

200

—

tBUSY

tTOW

3

50

—

50

—

Erase Time-out Time *

4

tSPD

Erase Suspend Transition Time *

*1 : This does not include the preprogramming time.

*2 : This timing is for Sector Protection Operation.

*3 : The time between writes must be less than “t^TOW” otherwise that command will not be accepted and erasure

will start. A time-out or “t^TOW” from the rising edge of last CEf or WE whichever happens first will initiate the

execution of the Sector Erase command(s).

*4 : When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum

of “t^SPD” to suspend the erase operation.

35

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

• Write Cycle (WE control) (Flash)

3rd Bus Cycle

Data Polling

555h

t^WC

PA

Address

CEf

t^RC

t^AS

t^AH

t^CH

t^CS

t^CEf

OE

t^GHWL

t^OE

t^WHWH1

t^WP

t^WPH

WE

t^OH

t^DS

t^DH

PD

D^OUT

A0h

DQ⁷

DQ

Notes: • PA is the address of the memory location to be programmed.

• PD is the data to be programmed at byte address.

• DQ⁷is the output of the complement of the data written to the device.

• D^OUTis the output of the data written to the device.

• Figure indicates last two bus cycles out of four bus cycle sequence.

• These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)

36

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

• Write Cycle (CEf control) (Flash)

3rd Bus Cycle

Data Polling

PA

Address

PA

555h

t^WC

t^AH

t^AS

WE

t^WS

t^WH

OE

t^GHEL

t^WHWH1

t^CP

t^CPH

CEf

t^DS

t^DH

PD

D^OUT

DQ⁷

A0h

DQ

Notes: • PA is the address of the memory location to be programmed.

• PD is the data to be programmed at byte address.

• DQ⁷is the output of the complement of the data written to the device.

• D^OUTis the output of the data written to the device.

• Figure indicates last two bus cycles out of four bus cycle sequence.

• These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)

37

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

• AC Waveforms Chip/Sector Erase Operations (Flash)

SA*

2AAh

555h

t^WC

2AAh

t^AS

555h

Address

CEf

t^AH

t^CS

t^CH

OE

t^WP

t^WPH

t^GHWL

WE

t^DS

t^DH

30h for Sector Erase

10h/

30h

AAh

55h

80h

55h

DQ

t^VCS

VCCf

*: SA is the sector address for Sector Erase. Address = 555h for Chip Erase.

Note: These waveform are for the ×16 mode. (The addresses differ from ×8 mode.)

38

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

• AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash)

CEf

t^CH

t^DF

t^OE

OE

t^OEH

WE

tCEf

*

High-Z

DQ⁷=

Valid Data

Data In

DQ⁷

DQ7

t^{WHWH1 or 2}

DQ

(DQ0 to DQ6)

DQ⁰to DQ⁶

Valid Data

DQ⁰to DQ⁶= Output Flag

t^BUSY

t^EOE

RY/BY

*: DQ⁷= Valid Data (The device has completed the Embedded operation.)

39

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

• AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash)

Address

t^AHT

t^ASO

t^AHT

t^AS

CEf

t^CEPH

WE

OE

t^OEH

t^OEPH

*

t^CEf

t^OE

t^DH

Toggle

Data

Toggle

Data

Toggle

Data

Stop

Toggling

Output

Valid

DQ6/DQ2

RY/BY

Data

t^BUSY

* : DQ⁶stops toggling (The device has completed the Embedded operation).

40

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

• Back-to-back Read/Write Timing Diagram (Flash)

Read

Command

Read

Command

Read

t

RC

t

WC

t

RC

t

WC

t

RC

t

RC

BA2

(555h)

BA2

(PA)

BA2

(PA)

Address

CE

BA1

t

ACC

t

AS

t

AS

t

AH

t

AHT

t

CE

t

OE

t

CEPH

OE

WE

DQ

t

DF

t

GHWL

t

OEH

t

WP

t

DH

t

DS

t

DF

Valid

Status

Output

Intput

Output

Intput

Output

(A0h)

(PD)

Note: This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.

BA1: Address of Bank 1.

BA2: Address of Bank 2.

41

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

• RY/BY Timing Diagram during Write/Erase Operations (Flash)

CEf

The rising edge of the last write pulse

WE

Entire programming

or erase operations

RY/BY

t^BUSY

• RESET, RY/BY Timing Diagram (Flash)

WE

RESET

t^RP

t^RB

RY/BY

t^READY

42

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

• Temporary Sector Unprotection (Flash)

VCCf

tVIDR

tVCS

tVLHT

V^ID

3V

RESET

CEf

WE

tVLHT

Program or Erase Command Sequence

Unprotection Period

RY/BY

43

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

• Extended Sector Protection (Flash)

VCCf

tVCS

RESET

tVLHT

tVIDR

tWC

Address

SPAX

SPAY

A6, A0

A1

CEf

OE

TIME-OUT

tWP

WE

Data

60h

40h

01h

t^OE

SPAX: Sector Group Address to be protected

SPAY : Next Group Sector Address to be protected

TIME-OUT : Time-Out window = 250 µs (Min.)

44

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

• Accelerated Program (Flash)

VCC

tVACCR

tVCS

tVLHT

VACC

3 V

WP/ACC

CEf

WE

tVLHT

Program Command Sequence

Acceleration period

RY/BY

45

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

• Read Cycle (SRAM)

Parameter

Value

Symbol

Unit

Min.

85

—

5

Max.

—

Read Cycle Time

t^RC

t^AA

ns

Address Access Time

85

45

85

—

Chip Enable (CE1s) Access Time

t^CO1

t^CO2

t^OE

Chip Enable (CE2s) Access Time

Output Enable Access Time

LBs, UBs to Output Valid

t^BA

Chip Enable (CE1s Low and CE2s High) to Output Active

Output Enable Low to Output Active

LBs, UBs Enable Low to Output Active

Chip Enable (CE1s High or CE2s Low) to Output High-Z

Output Enable High to Output High-Z

LBs, UBs Output Enable to Output High-Z

Output Data Hold Time

t^COE

t^OEE

t^BE

0

—

0

—

t^OD

—

10

35

—

t^ODO

t^BD

t^OH

Note : Test Conditions

Out put load : 1TTL gate and 30 pF

Input rise and fall times : 5 ns

Input pulse levels : 0.0 V to V^CCs

Timing measurement reference level

Input : 0.5 × V^CCs

Output : 0.5 × V^CCs

46

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

• Read Cycle (SRAM)

t^RC

Address

t^AA

t^OH

t^CO1

CE1s

CE2s

t^COE

t^OD

t^CO2

t^OD

t^OE

OE

t^ODO

t^OEE

LBs, UBs

t^BA

t^BD

t^BE

t^COE

DQ

Valid Data Out

Note : WE remains “H” for the read cycle.

47

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

• Write Cycle (SRAM)

Parameter

Value

Symbol

Unit

Min.

85

60

70

0

Max.

—

Write Cycle Time

Write Pulse Width

t^WC

t^WP

t^CW

t^AW

t^BW

t^AS

ns

—

Chip Enable to End of Write

Address valid to End of Write

UBs, LBs to End of Write

Address Setup Time

—

Write Recovery Time

WE Low to Output High-Z

WE High to Output Active

Data Setup Time

t^WR

t^ODW

t^OEW

t^DS

0

—

0

35

—

35

0

—

Data Hold Time

t^DH

—

48

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

• Write Cycle *³(WE control) (SRAM)

t^WC

Address

t^AS

t^WP

t^WR

WE

CE1s

CE2s

t^AW

t^CW

t^BW

LBs, UBs

t^OEW

t^ODW

D^OUT

1

2

*

t^DS

t^DH

4

D^IN

Valid Data In

*

*1 : If CE1s goes “L” (or CE2s goes “H”) coincident with or after WE goes “L”, the output will

remain at High-Z.

*2 : If CE1s goes “H” (or CE2s goes “L”) coincident with or before WE goes “H”, the output will

remain at High-Z.

*3 : If OE is “H” during the write cycle, the outputs will remain at High-Z.

*4 : Because I/O signals may be in the output state at this Time, input signals of reverse

polarity must not be applied.

49

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

• Write Cycle * ¹(CE1s control) (SRAM)

t^WC

Address

t^AS

t^WP

t^WR

WE

t^AW

t^CW

CE1s

CE2s

t^CW

t^BW

LBs, UBs

t^BE

t^COE

t^ODW

D^OUT

t^DS

t^DH

2

D^IN

Valid Data In

*

*1 : If OE is “H” during the write cycle, the outputs will remain at High-Z.

*2 : Because I/O signals may be in the output state at this Time, input signals of reverse

polarity must not be applied.

50

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

• Write Cycle * ¹(CE2s Control) (SRAM)

t^WC

Address

t^AS

t^WP

t^WR

WE

t^CW

CE1s

CE2s

t^AW

t^CW

t^BW

LBs, UBs

t^BE

t^COE

t^ODW

D^OUT

t^DS

t^DH

2

D^IN

Valid Data In

*

*1 : If OE is “H” during the write cycle, the outputs will remain at High-Z.

*2 : Because I/O signals may be in the output state at this Time, input signals of reverse

polarity must not be applied.

51

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

• Write Cycle *¹(LBs, UBs Control) (SRAM)

t^WC

Address

t^WP

t^WR

WE

t^CW

CE1s

t^CW

CE2s

t^AW

t^BW

t^AS

LBs, UBs

t^BE

t^COE

t^ODW

D^OUT

t^DS

t^DH

2

Valid Data In

*

D^IN

*1 : If OE is “H” during the write cycle, the outputs will remain at High-Z.

*2 : Because I/O signals may be in the output state at this Time, input signals of reverse

polarity must not be applied.

52

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

■ ERASE AND PROGRAMMING PERFORMANCE (Flash)

Limits

Parameter

Unit

Comment

Min.

Typ.

Max.

Excludes programming time

prior to erasure

Sector Erase Time

—

1

10

s

Excludes system-level

overhead

Byte Programming Time

Word Programming Time

—

8

300

360

µs

Excludes system-level

overhead

16

Excludes system-level

overhead

Chip Programming Time

Erase/Program Cycle

—

100

—

s

100,000

cycle

■ DATA RETENTION CHARACTERISTICS (SRAM)

Value

Unit

Parameter

Symbol

Min.

Typ.

Max.

3.3

7

Data Retention Supply Voltage

V^DH

I^DDS2

t^CDR

t^R

1.5

—

0

—

V

Standby Current

V^DH= 3.0 V

1.5

—

µA

ns

Chip Deselect to Data Retention Mode Time

Recovery Time

—

t^RC

—

Note: t^RC: Read cycle time

• CE1s Controlled Data Retention Mode *¹

V^CCs

DATA RETENTION MODE

2.7 V

2

*

V^IH

V^DH

V^CCS–0.2 V

CE1s

t^CDR

t^R

GND

53

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

• CE2s Controlled Data Retention Mode *³

V^CCs

DATA RETENTION MODE

2.7 V

V^DH

V^IH

CE2s

t^CDR

t^R

V^IL

0.2 V

GND

*1 : In CE1s controlled data retention mode, input level of CE2s should be fixed Vccs to Vccs–0.2 V or Vss

to 0.2 V during data retention mode. Other input and input/output pins can be used between –0.3 V and Vccs

+ 0.3 V.

*2 : When CE1s is operating at the V^IHMin. level (2.2 V), the standby current is given by I^SB1s during the transition

of V^CCs from 3.6 V to 2.2 V.

*3 : In CE2s controlled data retention mode, input and input/output pins can be used between –0.3 V and Vccs + 0.3 V.

■ PIN CAPACITANCE

Value

Parameter

Symbol

C^IN

Test Setup

V^IN= 0

Unit

Typ.

11

Max.

14

Input Capacitance

pF

Output Capacitance

C^OUT

C^IN2

C^IN3

V^OUT= 0

V^IN= 0

12

16

Control Pin Capacitance

WP/ACC Pin Capacitance

14

16

21.5

26

Note: Test conditions T^A= 25°C, f = 1.0 MHz

■ HANDLING OF PACKAGE

Please handle this package carefully since the sides of packages are right angle.

■ CAUTION

• The high voltage (V^ID) can not apply to address pins and control pins except RESET. Therefore, it can not use

autoselect and sector protect function by applying the high voltage (V^ID) to specific pins.

• For the sector protection, since the high voltage (V^ID) can be applied to the RESET, it can be protected the

sector using “Extended sector protect” command.

54

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

■ ORDERING INFORMATION

MB84VD2218

X

EB

-85

-PBS

PACKAGE TYPE

PBS = 73-ball BGA

SPEED OPTION

See Product Selector Guide

Device Revision (Valid Combination)

EB

EE

Bank Size

2 = 4 Mbit / 28 Mbit

3 = 8 Mbit / 24 Mbit

4 = 16 Mbit / 16 Mbit

DEVICE NUMBER/DESCRIPTION

32 Mega-bit (4 M × 8-bit or 2 M × 16-bit) Dual Operation Flash Memory

3.0 V-only Read, Program, and Erase

4 Mega-bit (512 K × 8-bit or 256 K × 16-bit) SRAM

BOOT CODE SECTOR ARCHITECTURE

84VD2218 = Top sector

84VD2219 = Bottom sector

55

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

■ PACKAGE DIMENSION

73-pin plastic FBGA

(BGA-73P-M01)

8.80(.346)

7.20(.283)

11.60±0.10(.457±.004)

1.25 ⁺–0⁰.^.1¹0⁵.049 –⁺.^.0⁰0⁰4⁶

5.60(.220)REF

0.80(.031)

(Mounting height)

0.38±0.10

(Stand off)

(.015±.004)

10

9

8

7

6

5

4

3

2

1

0.80(.031)

8.00±0.10

(.315±.004)

5.60(.220)

REF

7.20(.283)

M

L

K

J

H

G

F

E

D

C

B

A

INDEX-MARK AREA

INDEX BALL

73-Ø0.45 –⁺0⁰.^.0¹5⁰

73-Ø0.18 –⁺.^.0⁰0⁰2⁴

M

0.08(.003)

0.10(.004)

Dimension in mm (inches)

C

1999 FUJITSU LIMITED B73001S-1C-1

56

MB84VD2218XEB/EE^-85/90/MB84VD2219XEB/EE^-85/90

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Marketing Division

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

Electronic Devices

Shinjuku Dai-Ichi Seimei Bldg. 7-1,

Nishishinjuku 2-chome, Shinjuku-ku,

Tokyo 163-0721, Japan

Tel: +81-3-5322-3353

Fax: +81-3-5322-3386

The information and circuit diagrams in this document are

presented as examples of semiconductor device applications, and

are not intended to be incorporated in devices for actual use. Also,

FUJITSU is unable to assume responsibility for infringement of

any patent rights or other rights of third parties arising from the use

of this information or circuit diagrams.

http://edevice.fujitsu.com/

North and South America

FUJITSU MICROELECTRONICS, INC.

3545 North First Street,

San Jose, CA 95134-1804, U.S.A.

Tel: +1-408-922-9000

Fax: +1-408-922-9179

The products described in this document are designed, and

manufactured as contemplated for general use, including without

limitation, ordinary industrial use, general office use, personal use,

and household use, but are not designed, developed and

manufactured as contemplated (1) for use accompanying fatal risks

or dangers that, unless extremely high safety is secured, could have

a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: +1-800-866-8608

Fax: +1-408-922-9179

http://www.fujitsumicro.com/

Europe

FUJITSU MICROELECTRONICS EUROPE GmbH

Am Siebenstein 6-10,

D-63303 Dreieich-Buchschlag,

Germany

Tel: +49-6103-690-0

Fax: +49-6103-690-122

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

http://www.fujitsu-fme.com/

Asia Pacific

Any semiconductor devices have inherently a certain rate of failure.

You must protect against injury, damage or loss from such failures

by incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

FUJITSU MICROELECTRONICS ASIA PTE. LTD.

#05-08, 151 Lorong Chuan,

New Tech Park,

Singapore 556741

Tel: +65-281-0770

Fax: +65-281-0220

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Control Law of Japan, the

prior authorization by Japanese government should be required for

export of those products from Japan.

http://www.fmal.fujitsu.com/

Korea

FUJITSU MICROELECTRONICS KOREA LTD.

1702 KOSMO TOWER, 1002 Daechi-Dong,

Kangnam-Gu,Seoul 135-280

Korea

Tel: +82-2-3484-7100

Fax: +82-2-3484-7111

F0107

FUJITSU LIMITED Printed in Japan


型号：	MB84VD22193EB-90-PBS
厂家：	FUJITSU
描述：	Memory Circuit, 2MX16, CMOS, PBGA73, PLASTIC, FBGA-73 静态存储器内存集成电路
文件：	总57页 (文件大小：1450K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB84VD22193EB-90-PBS [FUJITSU]

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