MB84VF5F4F5J1-70PBS [FUJITSU]
Memory Circuit, Flash+SRAM, 4MX16, CMOS, PBGA107, PLASTIC, FBGA-107;
| 型号： | MB84VF5F4F5J1-70PBS |
| 厂家： | 
FUJITSU |
| 描述： | Memory Circuit, Flash+SRAM, 4MX16, CMOS, PBGA107, PLASTIC, FBGA-107 静态存储器 内存集成电路 |
| 文件： | 总16页 (文件大小：183K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
SMCP0.1E
3Stacked MCP (Multi-Chip Package) FLASH & FLASH & FCRAM
CMOS
64M (×16) FLASH MEMORY &
32M (×16) FLASH MEMORY &
64M (×16) Mobile FCRAM TM
MB84VF5F4F5J1-70
■ FEATURES
• Power supply voltage of 2.7 to 3.1V
• High performance
70 ns maximum access time (Flash_1: 64Mb Falsh)
70 ns maximum access time (Flash_2 : 32Mb Falsh)
65 ns maximum access time (FCRAM : 64Mb FCRAM)
• Operating Temperature
–30 °C to +85 °C
• Package 107-ball BGA
(Continued)
■ PRODUCT LINEUP
Flash_1
Flash_2
FCRAM
Supply Voltage (V)
VCCf_1* = 2.7V to 3.1V
VCCf_2* = 2.7V to 3.1V
VCCr* = 2.7V to 3.1V
Max. Address Access Time (ns)
Max. CE Access Time (ns)
Max. OE Access Time (ns)
70
70
30
70
70
30
65
65
40
Note:*1,All of VCCf_1, VCCf_2, and VCCr must be the same level when either part is being accessed.
■ PACKAGE
107-pin plastic FBGA
BGA-107P-M01
MB84VF5F4F5J1-70
(Continued)
— FLASH MEMORY_1 & _2
• Simultaneous Read/Write Operations (Dual Bank)
• Flash_1 FlexBankTM
Bank A : 8 Mbit (8 KB × 8 and 64 KB × 15)
Bank B : 24 Mbit (64 KB × 48)
Bank C : 24 Mbit (64 KB × 48)
Bank D : 8 Mbit (8 KB × 8 and 64 KB × 15)
• Flash_2 FlexBankTM
Bank A : 4 Mbit (8 KB × 8 and 64 KB × 7)
Bank B : 12 Mbit (64 KB × 24)
Bank C : 12 Mbit (64 KB × 24)
Bank D : 4 Mbit (64 KB × 8)
Two virtual Banks are chosen from the combination of four physical banks.
Host system can program or erase in one bank, and then read immediately and simultaneously from the other
bank with zero latency between read and write operations.
Read-while-erase
Read-while-program
• Minimum 100,000 Program/Erase Cycles
• Sector Erase Architecture
Sixteen 4 Kword and one hundred twenty-six 32 Kword sectors in word.
Any combination of sectors can be concurrently erased. It also supports full chip erase.
• Hidden ROM (Hi-ROM) Region
256 byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC Input Pin
AtVIL, allowsprotectionof“outermost”2× 8Kbytesonbothendsofbootsectors, regardlessofsectorprotection/
unprotection status
At VIH, allows removal of boot sector protection
At VACC, increases program performance
• Embedded EraseTM Algorithms
Automatically preprograms and erases the chip or any sector
• Embedded ProgramTM Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion
• Ready/Busy Output (RY/BY_1 or RY/BY_2)
Hardware method for detection of program or erase cycle completion
• Automatic Sleep Mode
When addresses remain stable, the device automatically switches itself to low power mode.
• Low VCCf write inhibit ≤ 2.5 V
• Program Suspend/Resume
Suspends the program operation to allow a read in another byte
• Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Please Refer to “MBM29DL64DF” Datasheet in Detailed Function for Flash_1.
• Please Refer to “MBM29DL32BF” Datasheet in Detailed Function for Flash_2.
(Continued)
2 (MB84VF5F4F5J1 SMCP0.1E)
MB84VF5F4F5J1-70
(Continued)
— FCRAM
• Power Dissipation
Operating : 25mA max.
Standby
: 200 µA max.
• Power Down Mode
Sleep
NAP
: 10 µA max.
: 65 µA max.
16M Partial : 85 µA max.
• Power Down Control by CE2r
• Byte Write Control: LB(DQ7-DQ0), UB(DQ15-DQ8)
• 8 words Address Access Capability
*: FlexBankTM is a trademark of Fujitsu Limited, Japan.
*: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
*: Mobile FCRAMTM is a trademark of Fujitsu Limited, Japan.
(MB84VF5F4F5J1 SMCP0.1E) 3
MB84VF5F4F5J1-70
■ PIN ASSIGNMENT
(Top View)
Marking Side
A10
N.C.
A9
B10
N.C.
B9
C10
N.C.
C9
D10
N.C.
D9
E10
N.C.
E9
F10
N.C.
F9
G10
N.C.
G9
H10
N.C.
H9
J10
N.C.
J9
K10
N.C.
K9
L10
M10
N.C.
M9
N.C.
L9
N.C.
L8
N.C.
N.C.
N.C.
B8
N.C.
C8
A15
D8
A21
E8
N.C.
F8
A16
G8
VCCf_1
H8
VSS
J8
N.C.
K8
N.C.
B7
A11
C7
A12
D7
A13
E7
A14
F7
PE
DQ15
H7
DQ7
J7
DQ14
K7
N.C.
L7
G7
N.C.
B6
A8
A19
D6
A9
A10
F6
DQ6
G6
DQ13
H6
DQ12
J6
DQ5
K6
N.C.
L6
C6
E6
N.C.
B5
WE
C5
CE2r
D5
A20
E5
D.U.
F5
D.U.
G5
DQ4
H5
VCCr
J5
N.C.
K5
N.C.
L5
VCCf_2
L4
CEf_2 WP/ACC RESET_1 RY/BY_1
D.U.
F4
D.U.
G4
DQ3
H4
VCCf_1
J4
DQ11
K4
B4
RY/BY_2
B3
C4
LB
C3
A7
C2
D4
UB
D3
A6
D2
E4
A18
E3
A17
F3
DQ1
G3
DQ9
H3
DQ10
J3
DQ2
K3
VSS
L3
VSS
B2
A5
A4
VSS
G2
OE
DQ0
J2
DQ8
K2
RESET_2
L2
A2
M2
E2
F2
H2
N.C.
A1
N.C.
M1
N.C.
N.C.
C1
A3
D1
A2
E1
A1
F1
A0
G1
CEf_1
H1
CE1r
J1
N.C.
K1
N.C.
L1
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
(BGA-107P-M01)
4 (MB84VF5F4F5J1 SMCP0.1E)
MB84VF5F4F5J1-70
■ PIN DESCRIPTION
Input/
Output
Pin name
Description
A20 to A0
A21
I
Address Inputs (Common)
I
Address Inputs (Flash_1 & FCRAM)
Data Inputs/Outputs (Common)
Chip Enable (Flash_1)
DQ15 to DQ0
CEf_1
CEf_2
CE1r
I/O
I
I
Chip Enable (Flash_2)
I
Chip Enable (FCRAM)
CE2r
I
Chip Enable (FCRAM)
OE
I
Output Enable (Common)
Write Enable (Common)
WE
I
RY/BY_1
RY/BY_2
UB
O
Ready/Busy Output (Flash_1) Open Drain Output
Ready/Busy Output (Flash_2) Open Drain Output
Upper Byte Control (FCRAM)
O
I
LB
I
Lower Byte Control (FCRAM)
RESET_1
RESET_2
WP/ACC
PE
I
Hardware Reset Pin/Sector Protection Unlock (Flash_1)
Hardware Reset Pin/Sector Protection Unlock (Flash_2)
Write Protect / Acceleration (Flash_1& Flash_2)
Partial Enable (FCRAM)
I
I
I
N.C.
—
No Internal Connection
D.U.
—
Don’t Use
VSS
Power
Power
Power
Power
Device Ground (Common)
VCCf_1
VCCf_2
VCCr
Device Power Supply (Flash_1)
Device Power Supply (Flash_2)
Device Power Supply (FCRAM)
(MB84VF5F4F5J1 SMCP0.1E) 5
MB84VF5F4F5J1-70
■ BLOCK DIAGRAM
VCCf_1
VSS
A21 to A0
RY/BY_1
64 M bit
Flash Memory_1
RESET_1
CEf_1
VCCf_2
VSS
A20 to A0
RY/BY_2
32 M bit
Flash Memory_2
WP/ACC
RESET_2
CEf_2
DQ15 to DQ0
VCCr
VSS
A21 to A0
64 M bit
FCRAM
LB
UB
WE
OE
CE1r
CE2r
PE
6 (MB84VF5F4F5J1 SMCP0.1E)
MB84VF5F4F5J1-70
■ DEVICE BUS OPERATIONS
WP/
Operation
(1), (2)
A20 to DQ7 to DQ15 to
CEf_1 CEf_2 CE1r CE2r OE WE LB UB PE
RESET_1 RESET_2 ACC
(12)
A0
DQ0
DQ8
Full Standby
H
H
H
H
H
L
H
H
X
H
X
H
X
X
X
X
H
H
X
High-Z High-Z
High-Z High-Z
H
H
X
X
X
(10)
Output
Disable(3)
H
H
L
H
L
H
H
H
H
X
X
X
H
Read from
Flash_1 (4)
L
H
L
H
H
H
H
L
L
H
H
X
X
X
X
H
H
Valid
Valid
DOUT
DOUT
DOUT
DOUT
H
H
H
H
X
X
Read from
Flash_2 (4)
H
Write to Flash _1
Write to Flash_2
L
H
L
H
H
H
H
H
H
L
L
X
X
L
X
X
L
H
H
Valid
Valid
DIN
DIN
DIN
DIN
H
H
H
H
X
X
H
Read from
FCRAM(5)
H
H
L
H
L
H
H
Valid
DOUT
DOUT
H
H
X
(9) (9)
L
H
L
L
L
DIN
DIN
DIN
Write to FCRAM
H
H
L
H
H
L
H
Valid High-Z
DIN
H
H
X
H
High-Z
Flash_1
Temporary
Sector
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
VID
X
X
X
Group
Unprotection(6)
Flash_ 2
Temporary
Sector
X
VID
Group
Unprotection(6)
Flash_1
X
X
X
X
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
High-Z High-Z
High-Z High-Z
L
X
L
X
X
Hardware Reset
Flash_2
Hardware Reset
X
Flash_1 or 2
Boot Block
Sector Write
Protection
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
FCRAM Power
Down Program
H
H
X
H
H
X
H
L
H
H
L
X
L
X
H
X
X
H
X
X
H
X
L
H
X
Valid High-Z High-Z
Valid High-Z High-Z
H
H
X
H
H
X
X
X
X
FCRAM No
Read (7)
FCRAM Power
Down (8)
X
X
X
X
X
Legend: L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels.
(Continued)
(MB84VF5F4F5J1 SMCP0.1E) 7
MB84VF5F4F5J1-70
(Continued)
Notes:
1. Other operations except for indicated this column are inhibited.
2. Do not apply for a following state two or more on the same time;
1) CEf_1 = VIL, 2)CEf_2 = VIL, 3) CE1r = VIL and CE2r = VIH
3. FCRAM Output Disable condition should not be kept longer than 1µs.
4. WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
5. FCRAM LB, UB control at Read operation is not supported.
6. It is also used for the extended sector group protections.
7. The FCRAM Power Down Program can be performed one time after compliance of Power-UP
timings and it should not be re-programmed after regular Read or Write.
8. FCRAM Power Down mode can be entered from Standby state and all DQ pins are in High-Z state.
IPDr current and data retention depends on the selection of Power Down Program.
9. Either or both LB and UB must be Low for FCRAM Read Operation.
10. Can be either VIL or VIH but must be valid before Read or Write.
11. See “ FCRAM Power Down Program Key Table “ in next page.
12. Protect “ outer most “ 2x8K bytes ( 4 words ) on both ends of the boot block sectors.
8 (MB84VF5F4F5J1 SMCP0.1E)
MB84VF5F4F5J1-70
■ ABSOLUTE MAXIMUM RATINGS
Rating
Unit
Parameter
Symbol
Min.
–55
–30
Max.
+125
Storage Temperature
Tstg
TA
°C
°C
V
Ambient Temperature with Power Applied
+85
VCCf_1 +0.3
VCCf_2 +0.3
VCCr +0.3
Voltage with Respect to Ground All pins
except RESET_1 or RESET_2,WP/ACC *1
VIN, VOUT
–0.3
V
V
VCCf_1,VCCf_2,
VCCr
VCCf_1/VCCf_2/VCCr Supply *1
–0.3
+3.3
V
RESET_1 or RESET_2 *2
WP/ACC *3
VIN
VIN
–0.5
–0.5
+ 13.0
+10.5
V
V
*1 Minimum DC voltage on input or I/O pins is –0.3 V. During voltage transitions, input or I/O pins may undershoot
VSS to –1.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCCf_1 + 0.3 V or VCCf_2
+ 0.3 V or VCCr + 0.3 V. During voltage transitions, input or I/O pins may overshoot to VCCf_1 + 2.0 V or VCCf_2
+ 2.0 V or VCCr + 1.0 V for periods of up to 20 ns.
*2: Minimum DC input voltage on RESET_1 or RESET_2 pin is –0.5 V. During voltage transitions RESET_1 or
RESET_2 pins may undershoot VSS to –2.0 V for periods of up to 20 ns.
Voltage difference between input and supply voltage (VIN-VCCf_1 or VCCf_2) does not exceed +9.0 V.
Maximum DC input voltage on RESET_1 or RESET_2 pins is +13.0 V which may overshoot to +14.0 V for
periods of up to 20 ns.
*3: Minimum DC input voltage on WP/ACC pin is –0.5 V. During voltage transitions, WP/ACC pin may undershoot
Vss to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may
overshoot to +12.0 V for periods of up to 20 ns, when VCCf_1 or VCCf_2 is applied.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Unit
Min.
–30
Max.
+85
Ambient Temperature
TA
°C
V
VCCf_1/VCCf_2/VCCr Supply Voltages
VCCf_1,VCCf_2,VCCr
+2.7
+3.1
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
Note: Operating ranges define those limits between which the functionality of the device is guaranteed.
(MB84VF5F4F5J1 SMCP0.1E) 9
MB84VF5F4F5J1-70
■ ELECTRICAL CHARACTERISTICS
1. DC Characteristics
Value
Sym-
Parameter
bol
Conditions
VIN = VSS to VCCf_1,VCCr
Unit
Min. Typ. Max.
Input Leakage Current
Output Leakage Current
ILI
–1.0
–1.0
—
—
+1.0 mA
+1.0 mA
ILO
VOUT = VSS to VCCf_1,VCCr
RESET Inputs Leakage
Current
VCCf= VCCf Max.,
RESET = 12.5 V
ILIT
—
—
35
µA
tCYCLE =5 MHz
tCYCLE =1 MHz
—
—
—
—
18
4
mA
mA
Flash_1 VCC Active Current
(Read) *1
CEf_1 = VIL,
OE = VIH
ICC1f_1
Flash_1 VCC Active Current
(Program/Erase) *2
ICC2f_1 CEf_1 = VIL, OE = VIH
ICC3f_1 CEf_1 = VIL, OE = VIH
ICC4f_1 CEf_1 = VIL, OE = VIH
ICC5f_1 CEf _1= VIL, OE = VIH
—
—
—
—
—
—
—
—
35
53
53
40
mA
mA
mA
mA
Flash_1 VCC Active Current
(Read-While-Program) *5
Flash_1 VCC Active Current
(Read-While-Erase) *5
Flash_1 VCC Active Current
(Erase-Suspend-Program)
tCYCLE =5 MHz
tCYCLE =1 MHz
—
—
—
—
18
4
Flash_2 VCC Active Current
(Read) *1
CEf_2 = VIL,
ICC1f_2
mA
OE = VIH
Flash_2 VCC Active Current
(Program/Erase) *2
ICC2f_2 CE_2 = VIL, OE = VIH
ICC3f_2 CE_2 = VIL, OE = VIH
ICC4f_2 CE_2 = VIL, OE = VIH
ICC5f_2 CE_2 = VIL, OE = VIH
—
—
—
—
—
—
—
—
35
53
53
35
mA
mA
mA
mA
mA
Flash_2 VCC Active Current
(Read-While-Program) *5
Flash_2 VCC Active Current
(Read-While-Erase) *5
Flash_2 VCC Active Current
(Erase-Suspend-Program)
WP/ACC Acceleration
Program Current
VCCf = VCCf Max.,
IACC
—
—
—
—
—
—
20
25
3
WP/ACC = VACC Max.
VCCr = VCCr Max.,
tRC / tWC =min.
tRC / tWC =1ms
CE1r = VIL, CE2r = VIH,
FCRAM VCC Active Current
Flash VCC Standby Current
ICC1r
mA
VIN = VIH or VIL, IOUT =
0mA
VCCf = VCCf Max., CEf = VCCf ± 0.3 V
ISB1f RESET = VCCf ± 0.3 V,
WP/ACC = VCCf± 0.3 V
—
—
1 *7
1 *7
5 *7
5 *7
µA
µA
Flash VCC Standby Current
(RESET)
VCCf = VCCf Max., RESET = VSS ± 0.3 V,
WP/ACC = VCCf± 0.3 V
ISB2f
VCCf = VCCf Max., CEf = VSS ± 0.3 V
RESET = VCCf ± 0.3 V,
WP/ACC = VCCf± 0.3 V,
Flash VCC Current (Auto-
matic Sleep Mode) *3
ISB3f
—
1 *7
5 *7
µA
VIN = VCCf± 0.3 V or VSS ± 0.3 V
(Continued)
10 (MB84VF5F4F5J1 SMCP0.1E)
MB84VF5F4F5J1-70
(Continued)
Parameter
Value
Unit
Sym-
bol
Conditions
Min. Typ. Max.
VCCr = VCCr Max.,CE1r > VCCr – 0.2V,
FCRAM VCC Standby Current ISB1r CE2r > VCCr– 0.2V,
VIN < 0.2 V or VCCr – 0.2 V
—
—
200
µA
Sleep
NAP
IPDSr
IPDNr
—
—
—
—
10
65
µA
µA
VCCr = VCCr Max.,
CE1r > VCCr – 0.2V,
CE2r < 0.2V,
FCRAM VCC Power Down
Current
16M
Partial
VIN Cycle time = tRC min.
IPD8r
VIL
—
–0.3
2.2
—
—
—
85
µA
V
Input Low Level
Input High Level
—
—
0.5
VCC+
0.3 *6
VIH
V
VoltageforSectorProtection,
and Temporary Sector Un-
protection (RESET) *4
VID
—
—
11.5
8.5
—
12.5
9.5
V
V
Voltage for WP/ACC Sector
Protection/Unprotection and
Program Acceleration *4
VACC
9.0
VOLf VCCf = VCCf Min., IOL=4.0 mA
VOLr VCCr = VCCr Min., IOL =1.0mA
Flash
—
—
—
—
0.45
0.4
V
V
Output Low Voltage Level
FCRAM
VCCf–
0.4
VOHf VCCf = VCCf Min., IOH=–0.1 mA
VOHr VCCr = VCCr Min., IOH =–0.5mA
Flash
—
—
—
—
V
V
V
Output High Voltage Level
FCRAM
2.2
Flash Low VCCf Lock-Out
Voltage
VLKO
—
2.3
2.4
2.5
Legend: Flash means Flash_1 or Flash_2, VCCf means VCCf_1 or VCCf_2, VSSf means VSSf_1 or VSSf_2, CEf means
CEf_1 or CEf _2, RESET means RESET_1 or RESET_2
*1: The ICC current listed includes both the DC operating current and the frequency dependent component.
*2: ICC active while Embedded Algorithm (program or erase) is in progress.
*3: Automatic sleep mode enables the low power mode when address remains stable for 150 ns.
*4: Applicable for only VCCf applying.
*5: Embedded Alogorithm (program or erase) is in progress. (@5 MHz)
*6: VCC indicates lower of VCCf_1 or VCCf_2 or VCCr.
*7: Actual Standby Current is twice of what is indicated in the table, due to two Flash memory chips embedment
with one device.
(MB84VF5F4F5J1 SMCP0.1E) 11
MB84VF5F4F5J1-70
2. AC Characteristics
• CE Timing
Symbol
JEDEC Standard
Value
Parameter
Condition
Unit
Min.
Max.
—
CE Recover Time
CE Hold Time
—
—
tCCR
—
—
0
3
ns
ns
tCHOLD
—
CE1r, High to WE Invalid time for
Standby Entry
—
tCHWX
—
10
—
ns
• Timing Diagram for alternating RAM to Flash_1 or Flash_2
CEf
tCCR
tCCR
CE1r
WE
tCHWX
tCHOLD
tCCR
tCCR
CE2r
• Flash_1 Characteristics
Please refer to “64M Flash Memory for MCP“ part. In this part, Flash means Flash_1, VCCf means VCCf_1,
VSSf means VSSf_1, CEf means CEf _1, RESET means RESET_1
• Flash_2 Characteristics
Please refer to “32M Flash Memory for MCP“ part. In this part, Flash means Flash_2, VCCf means VCCf_2,
VSSf means VSSf_2, CEf means CEf _2, RESET means RESET_2
• FCRAM Characteristics
Please refer to “64M FCRAM for MCP“ part.
12 (MB84VF5F4F5J1 SMCP0.1E)
MB84VF5F4F5J1-70
■ PIN CAPACITANCE
Value
Typ.
Parameter
Symbol
Condition
VIN = 0
Unit
Min.
Max.
20.0
25.0
25.0
Input Capacitance
CIN
pF
pF
pF
Output Capacitance
Control Pin Capacitance
COUT
CIN2
VOUT = 0
VIN = 0
Note: Test conditions Ta = 25°C, f = 1.0 MHz
■ HANDLING OF PACKAGE
Please handle this package carefully since the sides of package create acute angles.
■ CAUTION
• The high voltage (VID) cannot apply to address pins and control pins except RESET. Exception is when
autoselect and sector group protect function are used, then the high voltage (VID) can be applied to RESET.
• Without the high voltage (VID) , sector group protection can be achieved by using “Extended Sector Group
Protection” command.
(MB84VF5F4F5J1 SMCP0.1E) 13
MB84VF5F4F5J1-70
■ ORDERING INFORMATION
MB84VF5F4F5J
1
-70 PBS
PACKAGE TYPE
PBS = 107-ball BGA
SPEED OPTION
Device Revision
DEVICE NUMBER/DESCRIPTON
64Mega-bit (4M x 16bit) Dual Operation Flash Memory
32Mega-bit (2M x 16bit) Dual Operation Flash Memory
3.0V-only Read, Program, and Erase
64Mega-bit (4M x 16bit) FCRAM
14 (MB84VF5F4F5J1 SMCP0.1E)
MB84VF5F4F5J1-70
■ PACKAGE DIMENSION
107-pin plastic FBGA
(BGA-107P-M01)
10.00±0.10(.394±.004)
0.20(.008)
S
B
1.25 –+00..1105
B
(SEATED HIGHT)
(STAND OFF)
.049 –+..000046
0.40(.016)
REF
0.80(.031)
REF
0.10±0.05
(.004±.002)
10
9
8
7
6
5
4
3
2
1
0.80(.031)
REF
A
9.00±0.10
(.354±.004)
0.40(.016)
REF
0.08(.003)
S
M
L K J H G F E D C B A
INDEX-MARK AREA
S
107-ø0.40 –+00..0150
107-ø.016 –+..000024
0.20(.008)
S A
M
0.08(.003)
S
A
B
0.08(.003)
S
Dimensions in mm (inches).
C
2002 FUJITSU LIMITED B107001S-c-1-1
(MB84VF5F4F5J1 SMCP0.1E) 15
MB84VF5F4F5J1-70
FUJITSU LIMITED
For further information please contact:
Japan
All Rights Reserved.
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
Shinjuku Dai-Ichi Seimei Bldg. 7-1,
Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0721, Japan
Tel: +81-3-5322-3347
Fax: +81-3-5322-3386
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
http://edevice.fujitsu.com/
North and South America
FUJITSU MICROELECTRONICS, INC.
3545 North First Street,
San Jose, CA 95134-1804, U.S.A.
Tel: +1-408-922-9000
Fax: +1-408-922-9179
The contents of this document may not be reproduced or copied
without the permission of FUJITSU LIMITED.
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: +1-800-866-8608
FUJITSU semiconductor devices are intended for use in standard
applications (computers, office automation and other office
equipments, industrial, communications, and measurement
equipments, personal or household devices, etc.).
Fax: +1-408-922-9179
http://www.fujitsumicro.com/
CAUTION:
Europe
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or
where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters,
vehicle operating controls, medical devices for life support, etc.)
are requested to consult with FUJITSU sales representatives before
such use. The company will not be responsible for damages arising
from such use without prior approval.
FUJITSU MICROELECTRONICS EUROPE GmbH
Am Siebenstein 6-10,
D-63303 Dreieich-Buchschlag,
Germany
Tel: +49-6103-690-0
Fax: +49-6103-690-122
http://www.fujitsu-fme.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
#05-08, 151 Lorong Chuan,
New Tech Park,
Any semiconductor devices have inherently a certain rate of failure.
You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
Singapore 556741
Tel: +65-281-0770
Fax: +65-281-0220
http://www.fmap.com.sg/
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required for
export of those products from Japan.
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
1702 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Tel: +82-2-3484-7100
Fax: +82-2-3484-7111
F0211
FUJITSU LIMITED Printed in Japan
16 (MB84VF5F4F5J1 SMCP0.1E)
相关型号：
©2020 ICPDF网 联系我们和版权申明