MB84VP24491HK-70PBS_技术文档

TM

SPANSION MCP

Data Sheet

September 2003

This document specifies SPANSION^TMmemory products that are now offered by both Advanced Micro Devices and

Fujitsu. Although the document is marked with the name of the company that originally developed the specification,

these products will be offered to customers of both AMD and Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a SPANSION^TMproduct. Future routine

revisions will occur when appropriate, and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these

products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about SPANSION^TMmemory

solutions.

FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-50225-2E

Stacked MCP (Multi-Chip Package) FLASH MEMORY & FCRAM

CMOS

128M (×16) FLASH MEMORY &

32M (×16) Mobile FCRAM^TM

MB84VP24491HK^-70

■ FEATURES

• Power Supply Voltage of 2.7 V to 3.1 V

• High Performance

20 ns maximum page read access time, 70 ns maximum random access time (Flash)

20 ns maximum page read access time, 70 ns maximum random access time (FCRAM)

• Operating Temperature

–30 °C to +85 °C

• Package 73-ball FBGA

(Continued)

■ PRODUCT LINEUP

Flash

FCRAM

+0.1V

–0.3 V

+0.1V

–0.3 V

Supply Voltage (V)

V^CCf* = 3.0 V

VCCr* = 3.0 V

Max Random Address Access Time (ns)

Max Page Address Access Time (ns)

Max CE Access Time (ns)

70

20

70

20

70

20

70

40

Max OE Access Time (ns)

*: Both VCCf and VCCr must be the same level when either part is being accessed.

■ PACKAGE

73-ball plastic FBGA

(BGA-73P-M03)

MB84VP24491HK-70

(Continued)

— FLASH MEMORY

• 0.13 µm Process Technology

• Dual Chip Enable (CE0f, CE1f)

CE0fcontrols64Mbits(BankAandBankB)regionandCE1fcontrols64Mbits(BankCandBankD)bitsregion.

• Single 3.0 V Read, Program and Ease

Minimized system level power requirements

• Simultaneous Read/Write Operations (Dual Bank)

1

• FlexBank^TM

*

Bank A(CE0f): 16 Mbit (4 KW ×8 and 32 KW ×31)

Bank B(CE0f): 48 Mbit (32 KW ×96)

Bank C(CE1f): 48 Mbit (32 KW ×96)

Bank D(CE1f): 16 Mbit (4 KW ×8 and 32 KW ×31)

• High Performance Page Mode

20 ns maximum page access time (70 ns random access time)

• 8 words Page Access Capability

• Minimum 100,000 Program/Erase Cycles

• Sector Erase Architecture

Eight 4 Kwords, two hundred fifty-four 32 Kwords, eight 8 Kwords sectors.

Any combination of sectors can be concurrently erased. Also supports full chip erase

• Dual Boot Block

Sixteen 4Kwords boot block sectors, eight at the top of the address range and eight at the bottom of the address

range

• HiddenROM Region

256 byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence

Factory serialized and protected to provide a secure electronic serial number (ESN)

• WP/ACC Input Pin

At V^IL, allows protection of “outermost” 2×4 K words on both ends of boot sectors, regardless of sector pro-

tection/unprotection status

At V^IH, allows removal of boot sector protection

At VACC, increases program performance

• Embedded Erase^TM*²Algorithms

Automatically preprograms and erases the chip or any sector

• Embedded Program^TM*²Algorithms

Automatically writes and verifies data at specified address

• Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion

• Ready/Busy Output (RY/BY)

Hardware method for detection of program or erase cycle completion

• Automatic Sleep Mode

When addresses remain stable, the device automatically switches itself to low power mode

• Low V^CCWrite Inhibit ≤ 2.5 V

• Program Suspend/Resume

Suspends the program operation to allow a read in another byte

• Erase Suspend/Resume

Suspends the erase operation to allow a read data and/or program in another sector within the same device

• Hardware Reset Pin (RESET)

Hardware method to reset the device for reading array data

(Continued)

2

MB84VP24491HK-70

(Continued)

• New Sector Protection

Persistent Sector Protection

Password Sector Protection

• Please refer to “MBM29RM12DH” Datasheet in detailed function

3

— FCRAM^TM

*

• Power Dissipation

Operating : 30 mA Max

Standby : 100 µA Max

• Power Down Mode

Sleep

: 10 µA Max

4M Partial : 45 µA Max

8M Partial : 55 µA Max

16M Partial: 70 µA Max

• Power Down Control by CE2r

• Byte Write Control: LB(DQ⁷to DQ⁰), UB(DQ¹⁵to DQ⁸)

• 8 words Page Access Capability

*1: FlexBank^TMis a trademark of Fujitsu Limited, Japan.

*2: Embedded Erase^TMand Embedded Program^TMare trademarks of Advanced Micro Devices, Inc.

*3: Mobile FCRAM^TMis a trademark of Fujitsu Limited, Japan.

3

MB84VP24491HK-70

■ PIN ASSIGNMENT

(Top View)

Marking Side

A10

B10

F10

N.C.

F9

G10

N.C.

G9

L10

M10

N.C.

D9

A15

D8

E9

A21

E8

H9

N. C.

H8

J9

V^SS

J8

CE1f

F8

A16

G8

C8

A11

C7

K8

DQ14

K7

A12

D7

A13

E7

A14

F7

N.C.

G7

DQ15

H7

DQ7

J7

A8

A19

D6

A9

A10

DQ6

DQ13

H6

DQ12

J6

DQ5

K6

L6

B6

N.C.

B5

C6

E6

WE

C5

CE2r

D5

A20

E5

DQ4

H5

V^CCr

J5

N.C.

K5

N.C.

L5

N.C.

WP/ACC RESET

RY/BY

E4

DQ3

H4

VCCf

J4

DQ11

K4

N.C.

C4

LB

C3

A7

D4

UB

D3

A6

D2

A3

F4

A17

F3

G4

DQ1

G3

A18

E3

DQ9

H3

DQ10

J3

DQ2

K3

A5

A4

V^SS

G2

OE

DQ0

J2

DQ8

E2

F2

H2

A2

A1

A0

CE0f

CE1r

A1

B1

C1

F1

G1

L1

M1

N.C.

(BGA-73P-M03)

4

MB84VP24491HK-70

■ PIN DESCRIPTION

Input/

Output

Pin name

Description

A²⁰to A0

A²¹

I

Address Inputs (Common)

Address Input (Flash)

I

DQ15 to DQ0

CE0f

CE1f

CE1r

CE2r

OE

I/O

Data Inputs/Outputs (Common)

Chip Enable (Flash)

I

Chip Enable (Flash)

I

Chip Enable (FCRAM)

Output Enable (Common)

Write Enable (Common)

I

WE

I

RY/BY

UB

O

Ready/Busy Output (Flash) Open Drain Output

Upper Byte Control (FCRAM)

I

LB

I

Lower Byte Control (FCRAM)

RESET

WP/ACC

N.C.

I

Hardware Reset Pin/Sector Protection Unlock (Flash)

Write Protect / Acceleration (Flash)

No Internal Connection

I

—

V^SS

Power

Device Ground (Common)

V^CCf

Device Power Supply (Flash)

VCCr

Device Power Supply (FCRAM)

5

MB84VP24491HK-70

■ BLOCK DIAGRAM

V^CCf

V^SS

A²¹to A⁰

RY/BY

A²¹to A⁰

WP/ACC

128 M bit

Flash Memory

(Dual CE)

RESET

CE0f

DQ¹⁵to DQ⁰

CE1f

DQ¹⁵to DQ⁰

V^CCr

V^SS

A²⁰to A⁰

DQ¹⁵to DQ⁰

32 M bit

FCRAM

LB

UB

WE

OE

CE1r

CE2r

6

MB84VP24491HK-70

■ DEVICE BUS OPERATIONS

WP/

A²¹to DQ⁷to DQ¹⁵to

Operation*^1,*²

Full Standby

ACC

CE0f CE1f CE1r CE2r OE WE LB UB

RESET

A⁰

DQ⁰

DQ⁸

9

*

H

L

H

L

H

L

H

X

H

X

H

X

High-Z High-Z

H

X

X*⁸

Output Disable*³

H

X

H

L

H

L

Read from Flash*⁴

Write to Flash

H

L

H

X

Valid

D^OUT

DOUT

H

X

H

L

H

L

H

L

X

L

X

L

Valid

D^IN

DIN

H

X

H

DIN

Read from FCRAM

FCRAM No Read

Write to FCRAM

FCRAM No Write

H

L

H

L

H

L

H

L

Valid High-Z

DIN

H

X

H

L

DIN

High-Z

H

L

Valid High-Z High-Z

DIN

Valid High-Z

DIN

H*⁷

H

L

H

High-Z

H*⁷

X

H

X

H

X

L

X

H

X

H

X

H

X

L

X

H

Valid High-Z High-Z

H

VID

L

X

L

Flash Temporary Sector

Group Unprotection*⁵

X

Flash Hardware Reset

X

High-Z High-Z

Flash Boot Block Sector Write

Protection

X

FCRAM Power Down*⁶

X

Legend: L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance.

See ■DC CHARACTERISTICS for voltage levels.

*1 : Other operations except for indicated this column are inhibited.

*2 : Do not apply for two or more states of the following conditions at the same time;

• CE0f = VIL

• CE1f = VIL

• CE1r = VIL and CE2r = VIH

*3 : Should not be kept FCRAM Output Disable condition longer than 1µs.

*4 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations.

*5 : It is also used for the extended sector group protections.

*6 : FCRAM Power Down mode can be entered from Standby state and all DQ pins are in High-Z state.

Data retention depends on the selection of Power Down Program. Please refer to “Power Down Program”

in FCRAM Characteristics part.

*7 : OE can be VIL during Write operation if the following conditions are satisfied;

1) Write pulse is initiated by CE1r (refer to CE1r Controlled Write timing), or cycle time of the previous

operation cycle is satisfied.

2) OE stays VIL during Write cycle.

*8 : Can be either VIL or VIH but must be valid before Read or Write.

*9 : Protect “outer most” 2x8K bytes (4 words) on both ends of the boot block sectors.

7

MB84VP24491HK-70

■ ABSOLUTE MAXIMUM RATINGS

Rating

Parameter

Symbol

Unit

Min

–55

–30

Max

+125

Storage Temperature

Tstg

T^A

°C

V

Ambient Temperature with Power Applied

+85

V^CCf +0.3

V^CCr +0.3

+3.3

Voltage with Respect to Ground All pins

except RESET, WP/ACC *¹

VIN, VOUT

–0.3

V

V^CCf/VCCr Supply *¹

RESET *²

VCCf, VCCr

VIN

–0.3

–0.5

V

+ 13.0

+10.5

V

WP/ACC *³

VIN

V

*1 Minimum DC voltage on input or I/O pins is –0.3 V. During voltage transitions, input or I/O pins may undershoot

VSS to –1.0 V for periods of up to 5 ns. Maximum DC voltage on input or I/O pins is VCCf + 0.3 V or VCCr + 0.3V.

During voltage transitions, input or I/O pins may overshoot to VCCf + 2.0 V or VCCr + 1.0 V for periods of up to 5 ns.

*2: Minimum DC input voltage on RESET pin is –0.5 V. During voltage transitions RESET pins may undershoot VSS

to –2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN – VCCf) does not

exceed +9.0 V. Maximum DC input voltage on RESET pins is +13.0 V which may overshoot to +14.0 V for periods

of up to 20 ns.

*3: Minimum DC input voltage on WP/ACC pin is –0.5 V. During voltage transitions, WP/ACC pin may undershoot

Vss to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may

overshoot to +12.0 V for periods of up to 20 ns, when VCCf is applied.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■ RECOMMENDED OPERATING CONDITIONS

Value

Parameter

Symbol

Unit

Min

–30

+2.7

Max

+85

Ambient Temperature

T^A

°C

V

VCCf/VCCr Supply Voltages

VCCf, VCCr

+3.1

Note: Operating ranges define those limits between which the functionality of the device is guaranteed.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

8

MB84VP24491HK-70

■ DC CHARACTERISTICS

Value

Unit

Sym-

bol

Parameter

Conditions

Min Typ Max

Input Leakage Current

Output Leakage Current

I^LI

VIN = VSS to VCCf, VCCr

–1.0

—

+1.0 µA

ILO

VOUT = VSS to VCCf, VCCr, Output Disable

VCCf= VCCf Max, RESET = 12.5 V

RESET Inputs Leakage

Current (Flash)

ILIT

ILIA

—

35

20

45

µA

mA

WP/ACC Acceleration

Program Current (Flash)

VCCf = VCCf Max, WP/ACC = VACC Max

CE (CE0f or CE1f) = VIL,

f = 10 MHz

OE= VIH

Flash V^CCActive Current

(Read) *¹

ICC1f

CE (CE0f or CE1f) = VIL,

f = 5 MHz

—

1

25

5

mA

µA

OE= VIH

Flash V^CCActive Current *²

Flash V^CCCurrent (Standby)

ICC2f CE (CE0f or CE1f) = VIL, OEf= VIH

V^CCf = VCCf Max,CE0f, CE1f = VCCf ±0.3 V

ISB1f

RESET= VCCf ±0.3 V, WP/ACC =VCCf ±0.3 V

Flash V^CCCurrent

(Standby, Reset)

I^SB2f VCCf = VCCf Max, RESET= VSS ±0.3 V

—

1

5

µA

VCCf = VCCf Max, CE0f, CE1f= VSS ±0.3 V,

ISB3f RESET= VCCf±0.3 V,

Flash V^CCCurrent

(Automatic Sleep Mode) *³

V^IN= VCCf±0.3 V or VSSf±0.3 V

Flash V^CCActive Current

(Read-while-Program) *⁵

ICC3f CE (CE0f or CE1f) = VIL, OE= VIH

ICC4f CE (CE0f or CE1f) = VIL, OE= VIH

I^CC5f CE (CE0f or CE1f) = VIL, OE= VIH

—

45

25

10

mA

Flash V^CCActive Current

(Read-while-Erase) *⁵

Flash V^CCActive Current

(Erase Suspend Program)

mA

Flash VCC Active Current

(Page Mode Read)

CE (CE0f or CE1f) = VIL, OE = VIH,

I^CC6f

8 Word Read

ICC1r VCCr = VCCr Max,

CE1r = VIL, CE2r = VIH,

VIN = VIH or VIL, IOUT = 0mA*⁷

tRC / tWC =Min

—

30

3

FCRAM V^CCActive Current *⁸

mA

I^CC2r

tRC / tWC =1 µs

V^CCr = VCCr Max, VIN = VIH or VIL,

FCRAM V^CCPage Read

Current *⁸

7

ICC3r CE

—

10

mA

1r = VIL, CE2r = VIH, IOUT = 0 mA * ,

tPRC=Min

FCRAM VCC Standby

Current *⁸

VCCr = VCCr Max, VIN < 0.2V or > VCCr – 0.2V

CE1r > VCCr – 0.2V, CE2r > VCCr– 0.2V

ISB1r

100

µA

IDDPSr

IDDP4r

IDDP8r

IDDP16r

Sleep

—

10

45

55

70

µA

V^CCr = VCCr Max,

CE2r < 0.2V,

VIN = VIH or VIL

4M Partial

8M Partial

16M Partial

FCRAM V^CCPower Down

Current *⁸

(Continued)

9

MB84VP24491HK-70

(Continued)

Value

Typ

—

Sym-

bol

Parameter

Conditions

Unit

Min

–0.3

Max

Input Low Level

V^IL

V^IH

—

VCC × 0.2 *⁶

VCC+ 0.2 *⁶

V

Input High Level

VCC × 0.8

—

Voltage for Sector Protection, and

Temporary Sector Unprotection

(RESET) *⁴

VID

—

11.5

8.5

12

12.5

9.5

V

Voltage for WP/ACC Sector

Protection/Unprotection and

Program Acceleration *⁴

VACC

9.0

VCCf = VCCf Min,

IOL = 0.1 mA

V^OLf

V^OLr

VOHf

Flash

—

VCCf × 0.15

V

Output Low Voltage Level

V^CCr = VCCr Min,

I^OL= 1.0 mA

FCRAM

0.4

—

VCCf = VCCf Min,

IOH = –0.1 mA

Flash VCCf × 0.85

Output High Voltage Level

VCCr = VCCr Min,

IOH = –0.5 mA

V^OHr

FCRAM

2.4

2.3

—

V

Flash Low V^CCf Lock-Out Voltage

VLKO

—

2.4

2.5

*1: The ICC current listed includes both the DC operating current and the frequency dependent component.

*2: I^CCactive while Embedded Algorithm (program or erase) is in progress.

*3: Automatic sleep mode enables the low power mode when address remains stable for 150 ns.

*4: Applicable for only VCCf applying.

*5: Embedded Algorithm (program or erase) is in progress. (@5 MHz)

*6: V^CCindicates lower of VCCf or VCCr.

*7: FCRAM Characteristics are measured after following POWER-UP timing.

*8: I^OUTdepends on the output load conditions.

10

MB84VP24491HK-70

■ AC CHARACTERISTICS

• CE Timing

Symbol

Value

Parameter

Condition

Unit

JEDEC

Standard

tCCR

Min

0

Max

—

CE Recover Time

CE Hold Time

—

ns

tCHOLD

3

—

CE1r High to WE Invalid time for

Standby Entry

—

t^CHWX

—

10

—

ns

• Timing Diagram for alternating RAM to Flash

CE0f or

CE1f

tCCR

CE1r

WE

tCHWX

tCHOLD

tCCR

CE2r

• Flash Characteristics

Please refer to “■128 M PAEG FLASH MEMORY CHARACTERISTICS for MCP”.

• FCRAM Characteristics

Please refer to “■32 M FCRAM CHARACTERISTICS for MCP”.

11

MB84VP24491HK-70

■ 128 M PAGE FLASH MEMORY CHARACTERISTICS for MCP

1. Flexible Sector-erase Architecture on FLASH MEMORY (128M Page Flash)

• Sixteen 4K words, and two hundred fifty-four 32K words.

• Individual-sector, multiple-sector, or bulk-erase capability.

CE0f

CE1f

200000h

208000h

210000h

218000h

220000h

228000h

230000h

238000h

240000h

248000h

250000h

258000h

260000h

268000h

270000h

278000h

280000h

288000h

290000h

298000h

2A0000h

2A8000h

2B0000h

2B8000h

2C0000h

2C8000h

2D0000h

2D8000h

2E0000h

2E8000h

2F0000h

2F8000h

300000h

308000h

310000h

318000h

320000h

328000h

330000h

338000h

340000h

348000h

350000h

358000h

360000h

368000h

370000h

378000h

380000h

388000h

390000h

398000h

3A0000h

3A8000h

3B0000h

3B8000h

3C0000h

3C8000h

3D0000h

3D8000h

3E0000h

3E8000h

3F0000h

3F8000h

3FFFFFh

400000h

408000h

410000h

418000h

420000h

428000h

430000h

438000h

440000h

448000h

450000h

458000h

460000h

468000h

470000h

478000h

480000h

488000h

490000h

498000h

4A0000h

4A8000h

4B0000h

4B8000h

4C0000h

4C8000h

4D0000h

4D8000h

4E0000h

4E8000h

4F0000h

4F8000h

500000h

508000h

510000h

518000h

520000h

528000h

530000h

538000h

540000h

548000h

550000h

558000h

560000h

568000h

570000h

578000h

580000h

588000h

590000h

598000h

5A0000h

5A8000h

5B0000h

5B8000h

5C0000h

5C8000h

5D0000h

5D8000h

5E0000h

5E8000h

5F0000h

5F8000h

5FFFFFh

600000h

608000h

610000h

618000h

620000h

628000h

630000h

638000h

640000h

648000h

650000h

658000h

660000h

668000h

670000h

678000h

680000h

688000h

690000h

698000h

6A0000h

6A8000h

6B0000h

6B8000h

6C0000h

6C8000h

6D0000h

6D8000h

6E0000h

6E8000h

6F0000h

6F8000h

700000h

708000h

710000h

718000h

720000h

728000h

730000h

738000h

740000h

748000h

750000h

758000h

760000h

768000h

770000h

778000h

780000h

788000h

790000h

798000h

7A0000h

7A8000h

7B0000h

7B8000h

7C0000h

7C8000h

7D0000h

7D8000h

7E0000h

7E8000h

7F0000h

7F8000h

7F9000h

7FA000h

7FB000h

7FC000h

7FD000h

7FE000h

7FF000h

7FFFFFh

000000h

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

:

8KB

SA71 : 64KB

SA72 : 64KB

SA73 : 64KB

SA74 : 64KB

SA75 : 64KB

SA76 : 64KB

SA77 : 64KB

SA78 : 64KB

SA79 : 64KB

SA80 : 64KB

SA81 : 64KB

SA82 : 64KB

SA83 : 64KB

SA84 : 64KB

SA85 : 64KB

SA86 : 64KB

SA87 : 64KB

SA88 : 64KB

SA89 : 64KB

SA90 : 64KB

SA91 : 64KB

SA92 : 64KB

SA93 : 64KB

SA94 : 64KB

SA95 : 64KB

SA96 : 64KB

SA97 : 64KB

SA98 : 64KB

SA99 : 64KB

SA100: 64KB

SA101: 64KB

SA102: 64KB

SA103: 64KB

SA104: 64KB

SA105: 64KB

SA106: 64KB

SA107: 64KB

SA108: 64KB

SA109: 64KB

SA110: 64KB

SA111: 64KB

SA112: 64KB

SA113: 64KB

SA114: 64KB

SA115: 64KB

SA116: 64KB

SA117: 64KB

SA118: 64KB

SA119: 64KB

SA120: 64KB

SA121: 64KB

SA122: 64KB

SA123: 64KB

SA124: 64KB

SA125: 64KB

SA126: 64KB

SA127: 64KB

SA128: 64KB

SA129: 64KB

SA130: 64KB

SA131: 64KB

SA132: 64KB

SA133: 64KB

SA134: 64KB

SA135: 64KB

SA136: 64KB

SA137: 64KB

SA138: 64KB

SA139: 64KB

SA140: 64KB

SA141: 64KB

SA142: 64KB

SA143: 64KB

SA144: 64KB

SA145: 64KB

SA146: 64KB

SA147: 64KB

SA148: 64KB

SA149: 64KB

SA150: 64KB

SA151: 64KB

SA152: 64KB

SA153: 64KB

SA154: 64KB

SA155: 64KB

SA156: 64KB

SA157: 64KB

SA158: 64KB

SA159: 64KB

SA160: 64KB

SA161: 64KB

SA162: 64KB

SA163: 64KB

SA164: 64KB

SA165: 64KB

SA166: 64KB

SA167: 64KB

SA168: 64KB

SA169: 64KB

SA170: 64KB

SA171: 64KB

SA172: 64KB

SA173: 64KB

SA174: 64KB

SA175: 64KB

SA176: 64KB

SA177: 64KB

SA178: 64KB

SA179: 64KB

SA170: 64KB

SA181: 64KB

SA182: 64KB

SA183: 64KB

SA184: 64KB

SA185: 64KB

SA186: 64KB

SA187: 64KB

SA188: 64KB

SA189: 64KB

SA190: 64KB

SA191: 64KB

SA192: 64KB

SA193: 64KB

SA194: 64KB

SA195: 64KB

SA196: 64KB

SA197: 64KB

SA198: 64KB

SA199: 64KB

SA200: 64KB

SA201: 64KB

SA202: 64KB

SA203: 64KB

SA204: 64KB

SA205: 64KB

SA206: 64KB

SA207: 64KB

SA208: 64KB

SA209: 64KB

SA210: 64KB

SA211: 64KB

SA212: 64KB

SA213: 64KB

SA214: 64KB

SA215: 64KB

SA216: 64KB

SA217: 64KB

SA218: 64KB

SA219: 64KB

SA220: 64KB

SA221: 64KB

SA222: 64KB

SA223: 64KB

SA224: 64KB

SA225: 64KB

SA226: 64KB

SA227: 64KB

SA228: 64KB

SA229: 64KB

SA230: 64KB

SA231: 64KB

SA232: 64KB

SA233: 64KB

SA234: 64KB

SA235: 64KB

SA236: 64KB

SA237: 64KB

SA238: 64KB

SA239: 64KB

SA240: 64KB

SA241: 64KB

SA242: 64KB

SA243: 64KB

SA244: 64KB

SA245: 64KB

SA246: 64KB

SA247: 64KB

SA248: 64KB

SA249: 64KB

SA250: 64KB

SA251: 64KB

SA252: 64KB

SA253: 64KB

SA254: 64KB

SA255: 64KB

SA256: 64KB

SA257: 64KB

SA258: 64KB

SA259: 64KB

SA260: 64KB

SA261: 64KB

SA262: 8KB

SA263: 8KB

SA264: 8KB

SA265: 8KB

SA266: 8KB

SA267: 8KB

SA268: 8KB

SA269: 8KB

001000h

002000h

003000h

004000h

005000h

006000h

007000h

008000h

010000h

018000h

020000h

028000h

030000h

038000h

040000h

048000h

050000h

058000h

060000h

068000h

070000h

078000h

080000h

088000h

090000h

098000h

0A0000h

0A8000h

0B0000h

0B8000h

0C0000h

0C8000h

0D0000h

0D8000h

0E0000h

0E8000h

0F0000h

0F8000h

100000h

108000h

110000h

118000h

120000h

128000h

130000h

138000h

140000h

148000h

150000h

158000h

160000h

168000h

170000h

178000h

180000h

188000h

190000h

198000h

1A0000h

1A8000h

1B0000h

1B8000h

1C0000h

1C8000h

1D0000h

1D8000h

1E0000h

1E8000h

1F0000h

1F8000h

1FFFFFh

SA8 : 64KB

SA9 : 64KB

SA10 : 64KB

SA11 : 64KB

SA12 : 64KB

SA13 : 64KB

SA14 : 64KB

SA15 : 64KB

SA16 : 64KB

SA17 : 64KB

SA18 : 64KB

SA19 : 64KB

SA20 : 64KB

SA21 : 64KB

SA22 : 64KB

SA23 : 64KB

SA24 : 64KB

SA25 : 64KB

SA26 : 64KB

SA27 : 64KB

SA28 : 64KB

SA29 : 64KB

SA30 : 64KB

SA31 : 64KB

SA32 : 64KB

SA33 : 64KB

SA34 : 64KB

SA35 : 64KB

SA36 : 64KB

SA37 : 64KB

SA38 : 64KB

SA39 : 64KB

SA40 : 64KB

SA41 : 64KB

SA42 : 64KB

SA43 : 64KB

SA44 : 64KB

SA45 : 64KB

SA46 : 64KB

SA47 : 64KB

SA48 : 64KB

SA49 : 64KB

SA50 : 64KB

SA51 : 64KB

SA52 : 64KB

SA53 : 64KB

SA54 : 64KB

SA55 : 64KB

SA56 : 64KB

SA57 : 64KB

SA58 : 64KB

SA59 : 64KB

SA60 : 64KB

SA61 : 64KB

SA62 : 64KB

SA63 : 64KB

SA64 : 64KB

SA65 : 64KB

SA66 : 64KB

SA67 : 64KB

SA68 : 64KB

SA69 : 64KB

SA70 : 64KB

12

MB84VP24491HK-70

• FlexBank^TMArchitecture (128M Page Flash)

Bank 1

Bank

Bank 2

Splits

Volume

16 Mbit

48 Mbit

16 Mbit

Combination

Volume

112 Mbit

80 Mbit

112 Mbit

Combination

1

2

3

4

Bank A

Remainder (Bank B, C, D)

Remainder (Bank A, C, D)

Remainder (Bank A, B, D)

Remainder (Bank A, B, C)

Bank B

Bank C

Bank D

• Example of Virtual Banks Combination (128M Page Flash)

Bank 1

Bank

Bank 2

Splits

Volume

Combination

Sector Size

Volume

Combination

Sector Size

Bank B

+

Bank C

+

8 × 4 Kword

+

31 x 32 Kword

8 x 4 Kword

+

223 x 32 Kword

1

2

3

4

16 Mbit

Bank A

112 Mbit

Bank D

Bank A

+

Bank D

16 x 4 Kword

+

62 x 32 Kword

Bank B

+

Bank C

32 Mbit

48 Mbit

64 Mbit

96 Mbit

80 Mbit

64 Mbit

192 x 32 Kword

Bank A

+

Bank C

+

16 x 4 Kword

+

158 x 32 Kword

Bank B

96 x 32 Kword

Bank D

Bank A

+

8 x 4 Kword

+

Bank C

+

8 x 4 Kword

+

Bank B

127 x 32 Kword

Bank D

127 x 32 Kword

Note : When multiple sector erase over several banks is operated, the system cannot read out of the bank to which

a sector being erased belongs. For example, suppose that erasing is taking place at both Bank A and Bank B,

neither Bank A nor Bank B is read out (they would output the sequence flag once they were selected.)

Meanwhile the system would get to read from either Bank C or Bank D.

13

MB84VP24491HK-70

• Simultaneous Operation (Dual CE) (128M Page Flash)

The device features functions that enable reading of data from one memory bank while a program or erase

operation is in progress in the other memory bank (simultaneous operation) , in addition to conventional features

(read, program, erase, erase-suspend read, and erase-suspend program) . The bank can be selected by bank

address (A²¹, A20) with zero latency. The device consists of the following four banks :

CE0f control: Bank A : 8 x 4 KW and 31 x 32 KW; Bank B : 96 x 32 KW

CE1f control: Bank C : 96 x 32 KW; Bank D : 8 x 4 KW and 31 x 32 KW.

The possible combinations for simultaneous operation is show as following table. ( (Refer to Figure 11 Bank-to-

Bank Read/Write Timing Diagram.)

• Simultaneous Operation for Dual CE (128M Page Flash)

Bank 1 (CE0f) Status

16 Mbit

Bank 2 (CE0f) Status Bank 1 (CE1f) Status Bank 2 (CE1f) Status

Case

48 Mbit

16 Mbit

1

2

Read mode

Autoselect mode

Read mode

3

Autoselect mode

Read mode

4

Read mode

Autoselect mode

Read mode

5

Read mode

Autoselect mode

Read mode

6

Program mode

Read mode

7

Program mode

Read mode

8

Read mode

Program mode

Read mode

9

Read mode

Program mode

Read mode

10

11

12

13

14*

15*

16*

17*

18*

19*

20*

21*

22*

23*

Erase Mode

Read mode

Erase Mode

Read mode

Erase Mode

Read mode

Erase Mode

Multiple Erase Mode

Read mode

Multiple Erase Mode

Read mode

Multiple Erase Mode

Read mode

Multiple Erase Mode

Read mode

Multiple Erase Mode

Read mode

Multiple Erase Mode

Read mode

Multiple Erase Mode

Read mode

Multiple Erase Mode

Read mode

Multiple Erase Mode

Read mode

Multiple Erase Mode

Read mode

Multiple Erase Mode

* : Multiple Erase Mode requires multiple sector erase sequence which is followed by writes of the Sector Erase

command to addresses in other sectors desired to be concurrently erased. The time between writes must be

less than “t^TOW”.

14

MB84VP24491HK-70

2. Flexible Sector-erase Architecture

• Sector Address Tables (Bank A) (128M Page Flash)

Sector Address

Chip

Sector

Bank

(× 16)

Enable

Bank

Sector

Size

Address

Address Range

(Kword)

CE0f CE1f

A

21

A20

A

19

A18

A

17

A16

A15

A14

A13

A12

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

4

000000h to 000FFFh

001000h to 001FFFh

002000h to 002FFFh

003000h to 003FFFh

004000h to 004FFFh

005000h to 005FFFh

006000h to 006FFFh

007000h to 007FFFh

008000h to 00FFFFh

010000h to 017FFFh

018000h to 01FFFFh

020000h to 027FFFh

028000h to 02FFFFh

030000h to 037FFFh

038000h to 03FFFFh

040000h to 047FFFh

048000h to 04FFFFh

050000h to 057FFFh

058000h to 05FFFFh

060000h to 06FFFFh

068000h to 06FFFFh

070000h to 077FFFh

078000h to 07FFFFh

080000h to 087FFFh

088000h to 08FFFFh

090000h to 097FFFh

098000h to 09FFFFh

0A0000h to 0A7FFFh

0A8000h to 0AFFFFh

0B0000h to 0B7FFFh

0B8000h to 0BFFFFh

0C0000h to 0C7FFFh

0C8000h to 0CFFFFh

0D0000h to 0D7FFFh

0D8000h to 0DFFFFh

0E0000h to 0E7FFFh

0E8000h to 0EFFFFh

0F0000h to 0F7FFFh

0F8000h to 0FFFFFh

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

32

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

Bank A

15

MB84VP24491HK-70

• Sector Address Tables (Bank B) (128M Page Flash)

Sector Address

Chip

Sector

Size

(Kword)

Bank

(× 16)

Address Range

Enable

Bank

Sector

Address

CE0f CE1f

A21

A

20

A19

A18

A17

A16

A

15

A14

A

13

A12

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

SA71

SA72

SA73

SA74

SA75

SA76

SA77

0

1

0

1

0

X

32

100000h to 107FFFh

108000h to 10FFFFh

110000h to 117FFFh

118000h to 11FFFFh

120000h to 127FFFh

128000h to 12FFFFh

130000h to 137FFFh

138000h to 13FFFFh

140000h to 147FFFh

148000h to 14FFFFh

150000h to 157FFFh

158000h to 15FFFFh

160000h to 167FFFh

168000h to 16FFFFh

170000h to 177FFFh

178000h to 17FFFFh

180000h to 187FFFh

188000h to 18FFFFh

190000h to 197FFFh

198000h to 19FFFFh

1A0000h to 1A7FFFh

1A8000h to 1AFFFFh

1B0000h to 1B7FFFh

1B8000h to 1BFFFFh

1C0000h to 1C7FFFh

1C8000h to 1CFFFFh

1D0000h to 1D7FFFh

1D8000h to 1DFFFFh

1E0000h to 1E7FFFh

1E8000h to 1EFFFFh

1F0000h to 1F7FFFh

1F8000h to 1FFFFFh

200000h to 207FFFh

208000h to 20FFFFh

210000h to 217FFFh

218000h to 21FFFFh

220000h to 227FFFh

228000h to 22FFFFh

230000h to 237FFFh

(Continued)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

Bank B

16

MB84VP24491HK-70

Sector Address

Chip

Enable

Sector

(× 16)

Bank

Address

Bank

Sector

Size

Address Range

(Kword)

CE0f CE1f

A

21

A20

A

19

A18

A

17

A16

A15

A14

A13

A12

SA78

SA79

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

0

1

0

1

X

32

238000h to 23FFFFh

240000h to 247FFFh

248000h to 24FFFFh

250000h to 257FFFh

258000h to 25FFFFh

260000h to 267FFFh

268000h to 26FFFFh

270000h to 277FFFh

278000h to 27FFFFh

280000h to 287FFFh

288000h to 28FFFFh

290000h to 297FFFh

298000h to 29FFFFh

2A0000h to 2A7FFFh

2A8000h to 2AFFFFh

2B0000h to 2B7FFFh

2B8000h to 2BFFFFh

2C0000h to 2C7FFFh

2C8000h to 2CFFFFh

2D0000h to 2D7FFFh

2D8000h to 2DFFFFh

2E0000h to 2E7FFFh

2E8000h to 2EFFFFh

2F0000h to 2F7FFFh

2F8000h to 2FFFFFh

300000h to 307FFFh

308000h to 30FFFFh

310000h to 317FFFh

318000h to 31FFFFh

320000h to 327FFFh

328000h to 32FFFFh

330000h to 337FFFh

338000h to 33FFFFh

340000h to 347FFFh

348000h to 34FFFFh

350000h to 357FFFh

358000h to 35FFFFh

360000h to 367FFFh

368000h to 36FFFFh

(Continued)

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

SA95

SA96

SA97

SA98

Bank B

SA99

SA100

SA101

SA102

SA103

SA104

SA105

SA106

SA107

SA108

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

17

MB84VP24491HK-70

(Continued)

Sector Address

Chip

Enable

Sector

Size

(Kword)

(× 16)

Address Range

Bank

Address

Bank

Sector

CE0f CE1f

A21

A

20

A19

A

18

A17

A16

A15

A14

A13

A12

SA117

SA118

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

SA128

SA129

SA130

SA131

SA132

SA133

SA134

0

1

0

1

0

X

32

370000h to 377FFFh

378000h to 37FFFFh

380000h to 387FFFh

388000h to 38FFFFh

390000h to 397FFFh

398000h to 39FFFFh

3A0000h to 3A7FFFh

3A8000h to 3AFFFFh

3B0000h to 3B7FFFh

3B8000h to 3BFFFFh

3C0000h to 3C7FFFh

3C8000h to 3CFFFFh

3D0000h to 3D7FFFh

3D8000h to 3DFFFFh

3E0000h to 3E7FFFh

3E8000h to 3EFFFFh

3F0000h to 3F7FFFh

3F8000h to 3FFFFFh

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

Bank B

18

MB84VP24491HK-70

• Sector Address Tables (Bank C) (128M Page Flash)

Sector Address

Chip

Enable

Sector

(× 16)

Bank

Address

Bank

Sector

Size

Address Range

(Kword)

CE0f CE1f

A21

A

20

A19

A18

A17

A16

A

15

A14

A

13

A12

SA135

SA136

SA137

SA138

SA139

SA140

SA141

SA142

SA143

SA144

SA145

SA146

SA147

SA148

SA149

SA150

SA151

SA152

SA153

SA154

SA155

SA156

SA157

SA158

SA159

SA160

SA161

SA162

SA163

SA164

SA165

SA166

SA167

SA168

SA169

SA170

SA171

SA172

SA173

1

0

X

32

400000h to 407FFFh

408000h to 40FFFFh

410000h to 417FFFh

418000h to 41FFFFh

420000h to 427FFFh

428000h to 42FFFFh

430000h to 437FFFh

438000h to 43FFFFh

440000h to 447FFFh

448000h to 44FFFFh

450000h to 457FFFh

458000h to 45FFFFh

460000h to 467FFFh

468000h to 46FFFFh

470000h to 477FFFh

478000h to 47FFFFh

480000h to 487FFFh

488000h to 48FFFFh

490000h to 497FFFh

498000h to 49FFFFh

4A0000h to 4A7FFFh

4A8000h to 4AFFFFh

4B0000h to 4B7FFFh

4B8000h to 4BFFFFh

4C0000h to 4C7FFFh

4C8000h to 4CFFFFh

4D0000h to 4D7FFFh

4D8000h to 4DFFFFh

4E0000h to 4E7FFFh

4E8000h to 4EFFFFh

4F0000h to 4F7FFFh

4F8000h to 4FFFFFh

500000h to 507FFFh

508000h to 50FFFFh

510000h to 517FFFh

518000h to 51FFFFh

520000h to 527FFFh

528000h to 52FFFFh

530000h to 537FFFh

(Continued)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

Bank C

19

MB84VP24491HK-70

Sector Address

Chip

Enable

Sector

Size

(Kword)

(× 16)

Address Range

Bank

Address

Bank

Sector

CE0f CE1f

A21

A20

A

19

A

18

A17

A16

A15

A

14

A13

A12

SA174

SA175

SA176

SA177

SA178

SA179

SA180

SA181

SA182

SA183

SA184

SA185

SA186

SA187

SA188

SA189

SA190

SA191

SA192

SA193

SA194

SA195

SA196

SA197

SA198

SA199

SA200

SA201

SA202

SA203

SA204

SA205

SA206

SA207

SA208

SA209

SA210

SA211

SA212

1

0

1

0

1

X

32

538000h to 53FFFFh

540000h to 547FFFh

548000h to 54FFFFh

550000h to 557FFFh

558000h to 55FFFFh

560000h to 567FFFh

568000h to 56FFFFh

570000h to 577FFFh

578000h to 57FFFFh

580000h to 587FFFh

588000h to 58FFFFh

590000h to 597FFFh

598000h to 59FFFFh

5A0000h to 5A7FFFh

5A8000h to 5AFFFFh

5B0000h to 5B7FFFh

5B8000h to 5BFFFFh

5C0000h to 5C7FFFh

5C8000h to 5CFFFFh

6D0000h to 5D7FFFh

6D8000h to 5DFFFFh

5E0000h to 5E7FFFh

5E8000h to 5EFFFFh

5F0000h to 5F7FFFh

5F8000h to 5FFFFFh

600000h to 607FFFh

608000h to 60FFFFh

610000h to 617FFFh

618000h to 61FFFFh

620000h to 627FFFh

628000h to 62FFFFh

630000h to 637FFFh

638000h to 63FFFFh

640000h to 647FFFh

648000h to 64FFFFh

650000h to 657FFFh

658000h to 65FFFFh

660000h to 667FFFh

668000h to 66FFFFh

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

Bank C

(Continued)

20

MB84VP24491HK-70

(Continued)

Sector Address

Chip

Enable

Sector

(× 16)

Bank

Address

Bank

Sector

Size

Address Range

(Kword)

CE0f CE1f

A

21

A20

A19

A18

A17

A16

A

15

A14

A

13

A12

SA213

SA214

SA215

SA216

SA217

SA218

SA219

SA220

SA221

SA222

SA223

SA224

SA225

SA226

SA227

SA228

SA229

SA230

1

0

1

0

1

0

X

32

670000h to 677FFFh

678000h to 67FFFFh

680000h to 687FFFh

688000h to 68FFFFh

690000h to 697FFFh

698000h to 69FFFFh

6A0000h to 6A7FFFh

6A8000h to 6AFFFFh

6B0000h to 6B7FFFh

8B8000h to 6BFFFFh

6C0000h to 6C7FFFh

6C8000h to 6CFFFFh

6D0000h to 6D7FFFh

6D8000h to 6DFFFFh

6E0000h to 6E7FFFh

6E8000h to 6EFFFFh

6F0000h to 6F7FFFh

6F8000h to 6FFFFFh

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

Bank C

21

MB84VP24491HK-70

• Sector Address Tables (Bank D) (128M Page Flash)

Sector Address

Chip

Enable

Sector

Size

(Kword)

(× 16)

Address Range

Bank

Address

Bank

Sector

CE0f CE1f

A

21

A20

A

19

A18

A

17

A16

A15

A14

A13

A12

SA231

SA232

SA233

SA234

SA235

SA236

SA237

SA238

SA239

SA240

SA241

SA242

SA243

SA244

SA245

SA246

SA247

SA248

SA249

SA250

SA251

SA252

SA253

SA254

SA255

SA256

SA257

SA258

SA259

SA260

SA261

SA262

SA263

SA264

SA265

SA266

SA267

SA268

SA269

1

0

1

0

X

32

4

700000h to 707FFFh

708000h to 70FFFFh

710000h to 717FFFh

718000h to 71FFFFh

720000h to 727FFFh

728000h to 72FFFFh

730000h to 737FFFh

738000h to 73FFFFh

740000h to 747FFFh

748000h to 74FFFFh

750000h to 757FFFh

758000h to 75FFFFh

760000h to 767FFFh

768000h to 76FFFFh

770000h to 777FFFh

778000h to 77FFFFh

780000h to 787FFFh

788000h to 78FFFFh

790000h to 797FFFh

798000h to 79FFFFh

7A0000h to 7A7FFFh

7A8000h to 7AFFFFh

7B0000h to 7B7FFFh

7B8000h to 7BFFFFh

7C0000h to 7C7FFFh

7C8000h to 7CFFFFh

7D0000h to 7D7FFFh

7D8000h to 7DFFFFh

7E0000h to 7E7FFFh

7E8000h to 7EFFFFh

7F0000h to 7F7FFFh

7F8000h to 7F8FFFh

7F9000h to 7F9FFFh

7FA000h to 7FAFFFh

7FB000h to 7FBFFFh

7FC000h to 7FCFFFh

7FD000h to 7FDFFFh

7FE000h to 7FEFFFh

7FF000h to 7FFFFFh

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

X

0

X

0

Bank D

0

1

0

1

0

1

0

1

0

1

0

1

4

22

MB84VP24491HK-70

• Sector Group Address Table (128M Page Flash)

Sector Group CE0f CE1f

A²¹

0

1

A²⁰

0

1

0

1

A¹⁹

0

1

0

1

0

1

0

1

A¹⁸

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁷

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁶

0

A¹⁵

0

A¹⁴

0

A¹³

0

A¹²

0

Sectors

SA0

SGA0

SGA1

0

1

0

1

SA1

SGA2

0

1

0

SA2

SGA3

0

1

SA3

SGA4

0

1

0

SA4

SGA5

0

1

0

1

SA5

SGA6

0

1

0

SA6

SGA7

0

1

SA7

SGA8

0

1

X

SA8

SGA9

1

0

SA9

SGA10

SGA11

SGA12

SGA13

SGA14

SGA15

SGA16

SGA17

SGA18

SGA19

SGA20

SGA21

SGA22

SGA23

SGA24

SGA25

SGA26

SGA27

SGA28

SGA29

SGA30

SGA31

SGA32

SGA33

SGA34

SGA35

SGA36

SGA37

SGA38

SGA39

SGA40

SGA41

1

SA10

X

SA11 to SA14

SA15 to SA18

SA19 to SA22

SA23 to SA26

SA27 to SA30

SA31 to SA34

SA35 to SA38

SA39 to SA42

SA43 to SA46

SA47 to SA50

SA51 to SA54

SA55 to SA58

SA59 to SA62

SA63 to SA66

SA67 to SA70

SA71 to SA74

SA75 to SA78

SA79 to SA82

SA83 to SA86

SA87 to SA90

SA91 to SA94

SA95 to SA98

SA99 to SA102

SA103 to SA106

SA107 to SA110

SA111 to SA114

SA115 to SA118

SA119 to SA122

SA123 to SA126

SA127 to SA130

SA131 to SA134

(Continued)

23

MB84VP24491HK-70

(Continued)

Sector Group CE0f CE1f

A²¹

0

1

A²⁰

0

1

0

1

A¹⁹

0

1

0

1

0

1

0

1

A¹⁸

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁷

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁶

X

0

A¹⁵

X

0

A¹⁴

X

0

A¹³

X

0

A¹²

X

0

Sectors

SGA42

SGA43

SGA44

SGA45

SGA46

SGA47

SGA48

SGA49

SGA50

SGA51

SGA52

SGA53

SGA54

SGA55

SGA56

SGA57

SGA58

SGA59

SGA60

SGA61

SGA62

SGA63

SGA64

SGA65

SGA66

SGA67

SGA68

SGA69

SGA70

SGA71

SGA72

SGA73

SGA74

SGA75

SGA76

SGA77

SGA78

SGA79

SGA80

SGA81

SGA82

SGA83

1

0

SA135 to SA138

SA139 to SA142

SA143 to SA146

SA147 to SA150

SA151 to SA154

SA155 to SA158

SA159 to SA162

SA163 to SA166

SA167 to SA170

SA171 to SA174

SA175 to SA178

SA179 to SA182

SA183 to SA186

SA187 to SA190

SA191 to SA194

SA195 to SA198

SA199 to SA202

SA203 to SA206

SA207 to SA210

SA211 to SA214

SA215 to SA218

SA219 to SA222

SA223 to SA226

SA227 to SA230

SA231 to SA234

SA235 to SA238

SA239 to SA242

SA243 to SA246

SA247 to SA250

SA251 to SA254

SA255 to SA258

SA259

0

1

SA260

1

0

SA261

1

SA262

1

0

1

SA263

1

0

1

0

SA264

1

0

1

SA265

1

0

SA266

1

0

1

SA267

1

0

SA268

1

SA269

24

MB84VP24491HK-70

• Sector Group Protection Verify Autoselect Codes (128M Page Flash)

Type

Manufacture’s Code

Device Code

A²²to A¹²

BA

A⁷A⁶A⁵A⁴A³A²A¹A⁰

Code (HEX)

04h

L

X

L

H

L

BA

227Eh

2221h

H

Extended Device Code^*2

BA

H

2200h

Sector

Group

Sector Group Protection

L

H

L

01h^*1

Addresses

Legend: L = V^IL, H = VIH, X= VIL or VIH

*1 : Sector Group can be protected by “Extended Sector Group Protection”, and “New Sector Protection (PPB

Protection)”. Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group

addresses.

*2 : A read cycle at address (BA) 01h outputs device code. When 227Eh is output, it indicates that two additional

codes, called Extended Device Codes, will be required. Therefore the system may continue reading out these

Extended Device Codes at the address of (BA) 0Eh, as well as at (BA) 0Fh.

25

MB84VP24491HK-70

• Command Definitions (128M Page Flash)

Bus

Fourth Bus

Read/Write

Cycle

First Bus

Second Bus

Write Cycle

Third Bus

Fifth Bus

Sixth Bus

Seventh Bus

Write

Cy-

Command

Sequence

Write Cycle

Write Cycle Write Cycle

cles

Req’d

Addr. Data Addr. Data Addr. Data

Addr.

Data

Addr. Data Addr. Data Addr. Data

Read/Reset

1

3

XXXh F0h

555h AAh 2AAh

RA

RD

55h

—

F0h

—

RA

—

RD

—

555h

(BA)

555h

Autoselect

3

555h AAh 2AAh

55h

90h

—

Program

4

6

555h AAh 2AAh

55h

A0h

80h

PA

555h

PD

AAh

—

2AAh

—

55h

—

555h

SA

—

10h

30h

—

Chip Erase

Sector Erase

Program/Erase

Suspend

Program/Erase

Resume

1

BA

B0h

30h

—

Set to Fast

Mode

Fast Program

Reset from Fast

Mode *¹

3

2

555h AAh 2AAh

55h

PD

555h

—

20h

—

XXXh A0h

BA 90h

PA

4

*

XXXh

—

F0h

Extended

Sector Group

Protection *²

SGA+

WPH

SGA+

WPH

SGA+

WPH

4

XXXh 60h

60h

40h

SD

—

(BA)

98h

55h

Query

1

3

4

6

—

HiddenROM

Entry

HiddenROM

Program *³

HiddenROM

Exit *³

555h AAh 2AAh

55h

555h

88h

A0h

90h

60h

(HRA)

PA

PD

00h

68h

—

(HRBA)

555h

XXXh

OPBP

—

HiddenROM

Protect *³

555h

OPBP

48h OPBP RD(0)

555h AAh 2AAh

55h

555h

38h

XX0h

XX1h

XX2h

XX3h

PD0

PD1

PD2

PD3

Password

Program

4

—

Password

Unlock

Password Verify

PasswordMode

Locking Bit

Program

7

4

555h AAh 2AAh

55h

555h

28h

C8h

XX0h

PWA

PD0

PWD

XX1h

—

PD1 XX2h PD2 XX3h PD3

—

6

555h AAh 2AAh

55h

555h

60h

PL

68h

PL

48h XXXh RD(0)

Persistent

ProtectionMode

Locking Bit

Program

6

555h AAh 2AAh

55h

555h

60h

SPML

68h

SPML

48h XXXh RD(0)

—

PPB Program

6

4

3

555h AAh 2AAh

55h

555h

(BA)

555h

60h

90h

60h

78h

SGA+WP

WP

68h

RD(0)

60h

—

SGA+WP

—

PPB Verify

—

All PPB Erase

PPB Lock Bit

Set

PPB Lock Bit

Verify

SGA+WP

—

40h XXXh RD(0)

555h

—

(BA)

555h

(BA)

555h

4

555h AAh 2AAh

55h

58h

SA

RD(1)

—

DPB Write

DPB Erase

4

555h AAh 2AAh

55h

48h

SA

X1h

X0h

—

DPB Verify

4

555h AAh 2AAh

55h

58h

SA

RD(0)

—

(Continued)

26

MB84VP24491HK-70

(Continued)

Legend:

RA = Address of the memory location to be read

PA = Address of the memory location to be programmed

Addresses are latched on the falling edge of the write pulse.

SA = Address of the sector to be erased. The combination of A²², A21, A20, A19, A18, A17, A16, A15, A14, A13 and

A12 will uniquely select any sector.

BA = Bank Address. Address settled by A22, A21, A20, A19 will select Bank A, Bank B, Bank C and Bank D.

RD = Data read from location RA during read operation.

PD = Data to be programmed at location PA. Data is latched on the rising edge of write pulse.

SGA = Sector group address to be protected.

WPH = (A7, A6, A5, A4, A3, A2, A1, A0) is (0, 0, 0, 0, 0, 0, 1, 0)

SD = Sector group protection verify data. Output 01h at protected sector group addresses and output

00h at unprotected sector group addresses.

HRA = Address of the HiddenROM area Word Mode : 000000h to 00007Fh

HRBA = Bank Address of the HiddenROM area (A²²= A21 = A20 = VIL)

RD (0) = Read Data bit. If protected, DQ0 = 1, if unprotected, DQ0 = 0

RD (1) = Read Data bit. If protected, DQ1 = 1, if unprotected, DQ1 = 0

OPBP = (A7, A6, A5, A4, A3, A2, A1, A0) is (0, 0, 0, 1, 1, 0, 1, 0)

PWA/PWD = Password Address/Password Data

PL = (A7, A6, A5, A4, A3, A2, A1, A0) is (0, 0, 0, 0, 1, 0, 1, 0)

SPML = (A7, A6, A5, A4, A3, A2, A1, A0) is (0, 0, 0, 1, 0, 0, 1, 0)

WP = (A7, A6, A5, A4, A3, A2, A1, A0) is (0, 0, 0, 0, 0, 0, 1, 0)

*1: This command is valid during Fast Mode.

*2: This command is valid while RESET = VID.

*3: This command is valid during HiddenROM mode.

*4: The data “00h” is also acceptable.

Notes : • Address bits A²²to A11 = X = “H” or “L” for all address commands except for

PA, SA, BA, SGA, OPBP, PWA, PL, SPML, WP, WPH.

• Bus operations are defined in this document.

• The system should generate the following address patterns:

Word Mode : 555h or 2AAh to addresses A10 to A0

• Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.

27

MB84VP24491HK-70

3. AC Characteristics

• Read Only Operations Characteristics (Flash) (128M Page Flash)

Symbol

Value*

Test

Parameter

Read Cycle Time

Unit

Setup

JEDEC Standard

Min

Max

t^AVAV

tAVQV

—

tRC

tACC

t^PRC

tPACC

—

70

ns

CEf = VIL

OE = VIL

Address to Output Delay

Page Read Cycle Time

70

—

20

CEf = VIL

OE = VIL

Page Address to Output Delay

—

20

Chip Enable to Output Delay

Output Enable to Output Delay

Chip Enable to Output High-Z

Output Enable to Output High-Z

t^ELQV

t^GLQV

t^EHQZ

t^GHQZ

tCE

tOE

tDF

OE = VIL

70

20

ns

—

Output Hold Time From Address,

CEf or OE, Whichever Occurs First

t^AXQX

tOH

—

5

ns

* : Test Conditions– Output Load : 1 TTL gate and 30 pF

Input rise and fall times: 5 ns

Input pulse levels: 0.0 V to V^CCf

Timing measurement reference level

Input: 0.5×VCCf

Output: 0.5×VCCf

28

MB84VP24491HK-70

• Write/Erase/Program Operations (Flash) (128M Page Flash)

Symbol

JEDEC Standard Min

Value*¹

Unit

Parameter

Typ

Max

Write Cycle Time

Address Setup Time

t^AVAV

t^AVWL

tWC

tAS

70

0

ns

Address Setup Time to OE Low During

Toggle Bit Polling

Address Hold Time

Address Hold Time from CEf or OE High

During Toggle Bit Polling

—

tWLAX

—

t^ASO

tAH

15

35

0

ns

t^AHT

Data Setup Time

Data Hold Time

Output Enable Setup Time

t^DVWH

t^WHDX

—

tDS

tDH

30

0

10

0

ns

t^OES

Read

Output Enable Hold Time

—

t^OEH

Toggle and Data Polling

Read Recover Time Before Write

(OE High to CEf Low)

t^GHWL

t^GHEL

tGHWL

tGHEL

0

ns

CEf Setup Time

WE Setup Time

CEf Hold Time

WE Hold Time

Write Pulse Width

CEf Pulse Width

tELWL

tWLEL

tWHEH

tEHWH

t^WLWH

tELEH

t^WHWL

tEHEL

t^WHWH1

tWHWH2

—

tCS

tWS

0

ns

µs

s

tCH

tWH

0

tWP

40

25

tCP

Write Pulse Width High

CEf Pulse Width High

Programming Operation

Sector Erase Operation *²

V^CCf Setup Time

Rise Time to V^ID*³

Rise Time to V^ACC*⁴

Voltage Transition Time *³

Write Pulse Width*³

Recover Time from RY/BY

RESET Pulse Width

RESET High Level Period Before Read

Program/Erase Valid to RY/BY Delay

Delay Time from Embedded Output Enable

Erase Time-out Time

Erase Suspend Transition Time

tWPH

tCPH

tWHWH1

tWHWH2

tVCS

tVIDR

tVACCR

tVLHT

tWPP

tRB

6

0.5

50

500

4

µs

ns

µs

ns

µs

—

100

0

500

50

tRP

tRH

tBUSY

t^EOE

t^TOW

t^SPD

90

70

50

20

*1 : Test Conditions– Output Load : 1 TTL gate and 30 pF

Input rise and fall times: 5 ns

Input pulse levels: 0.0 V to V^CCf

Timing measurement reference level

Input: 0.5×VCCf

Output: 0.5×VCCf

*2 : This does not include the preprogramming time.

*3 : This timing is for Sector Group Protection / Unprotection.

*4 : This timing is for Accelerated Program operation.

29

MB84VP24491HK-70

• Read Operation Timing Diagram (128M Page Flash)

tRC

Address

Address Stable

tACC

CEf

OE

tOE

tDF

tOEH

WE

tCE

tOH

High-Z

Outputs

Output Valid

CEf : CE0f or CE1f

30

MB84VP24491HK-70

• Page Read Operation Timing Diagram (128M Page Flash)

Same page Addresses

A

22 to A

2

A

2

to A

0

Aa

Ab

Ac

Ad

t

RC

tPRC

t

PRC

t

ACC

t

CE

CEf

t

OEH

t

OE

tDF

t

PACC

t

PACC

t

PACC

WE

tOH

t

OH

t

OH

t

OH

High-Z

Da

Db

Dc

Dd

Output

CEf : CE0f or CE1f

31

MB84VP24491HK-70

• Hardware Reset/Read Operation Timing Diagram (128M Page Flash)

tRC

Address

Address Stable

tACC

CEf

tRH

tRP

tRH

tCE

RESET

Outputs

tOH

High-Z

Outputs Valid

CEf : CE0f or CE1f

32

MB84VP24491HK-70

• Alternate WE Controlled Program Operation Timing Diagram (128M Page Flash)

3rd Bus Cycle

555h

Data Polling

PA

Address

CEf

tWC

tRC

tAS

tAH

tCS

tCH

tCE

OE

tOE

tWP

tWPH

tWHWH1

tGHWL

WE

tOH

tDF

tDH

tDS

A0h

PD

DOUT

DQ7

Data

CEf : CE0f or CE1f

Notes : • PA is address of the memory location to be programmed.

• PD is data to be programmed at word address.

• DQ7 is the output of the complement of the data written to the device.

• DOUT is the output of the data written to the device.

• Figure indicates last two bus cycles out of four bus cycle sequence.

33

MB84VP24491HK-70

• Alternate CEf Controlled Program Operation Timing Diagram (128M Page Flash)

3rd Bus Cycle

555h

Data Polling

PA

Address

WE

tWC

tAS

tAH

tWS

tWH

OE

tCPH

tCP

tWHWH1

tGHEL

CEf

tDS

tDH

A0h

PD

DOUT

DQ7

Data

CEf : CE0f or CE1f

Notes : • PA is address of the memory location to be programmed.

• PD is data to be programmed at word address.

• DQ7 is the output of the complement of the data written to the device.

• DOUT is the output of the data written to the device.

• Figure indicates last two bus cycles out of four bus cycle sequence.

34

MB84VP24491HK-70

• Chip/Sector Erase Operation Timing Diagram (128M Page Flash)

555h

tWC

2AAh

555h

2AAh

SA*

Address

tAS

tAH

CEf

tCS

tCH

OE

tWP

tWPH

tGHWL

WE

tDS

tDH

30h for Sector Erase

10h/30h

AAh

55h

80h

AAh

55h

Data

VCCf

tVCS

CEf : CE0f or CE1f

* : SA is the sector address for Sector Erase. Addresses = 555h (Word) for Chip Erase.

35

MB84VP24491HK-70

• Data Polling during Embedded Algorithm Operation Timing Diagram (128M Page Flash)

CEf

tCH

tDF

tOE

OE

tOEH

WE

tCE

*

High-Z

DQ7 =

Data

DQ7

Valid Data

tWHWH1 or 2

DQ6 to DQ0 =

Output Flag

DQ6 to DQ0

Valid Data

DQ6 to DQ0

RY/BY

tEOE

tBUSY

CEf : CE0f or CE1f

* : DQ7 = Valid Data (The device has completed the Embedded operation) .

36

MB84VP24491HK-70

• AC Waveforms for Toggle Bit I during Embedded Algorithm Operations (128M Page Flash)

Address

CEf

tAHT tASO

tAHT tAS

tCEPH

WE

tOEPH

tOEH

OE

tOE

tCE

tDH

*

Stop

Output

Valid

Toggle

Data

Toggle

Data

Toggle

Data

DQ 6/DQ2

Data

Toggling

tBUSY

RY/BY

CEf : CE0f or CE1f

* : DQ6 stops toggling (The device has completed the Embedded operation).

37

MB84VP24491HK-70

• Bank-to-Bank Read/Write Timing Diagram (128M Page Flash)

Read

Command

Read

Command

Read

tRC

tWC

tRC

tWC

tRC

BA2

(PA)

BA2

(PA)

Address

CEf

BA1

(555h)

tACC

tCE

tAS

tAH

tAHT

tOE

tCEPH

OE

WE

DQ

tDF

tGHWL

tOEH

tWP

tDS

tDH

tDF

Valid

Output

Valid

Output

Valid

Output

Status

Intput

(A0h)

(PD)

CEf : CE0f or CE1f

Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.

BA1 : Address corresponding to Bank 1

BA2 : Address corresponding to Bank 2

38

MB84VP24491HK-70

• RY/BY Timing Diagram during Program/Erase Operation Timing Diagram (128M Page Flash)

CEf

Rising edge of the last WE signal

WE

Entire programming

or erase operations

RY/BY

tBUSY

CEf : CE0f or CE1f

• RESET, RY/BY Timing Diagram (128M Page Flash)

WE

RESET

tRP

tRB

RY/BY

tREADY

39

MB84VP24491HK-70

• Temporary Sector Group Unprotection Timing Diagram (128M Page Flash)

VCCf

tVIDR

tVCS

tVLHT

VID

VIH

RESET

CEf

WE

tVLHT

Program or Erase Command Sequence

Unprotection period

RY/BY

CEf : CE0f or CE1f

40

MB84VP24491HK-70

• Extended Sector Group Protection Timing Diagram (128M Page Flash)

VCCf

tVCS

tVLHT

RESET

tWC

tVIDR

Address

SGAX

SGAY

A7, A6, A5

A4, A3, A2

A0

A1

CEf

OE

TIME-OUT

tWP

WE

60h

40h

01h

60h

Data

tOE

CEf : CE0f or CE1f

SGAX : Sector Group Address to be protected

SGAY : Next Sector Group Address to be protected

TIME-OUT : Time-Out window = 250 µs (Min)

41

MB84VP24491HK-70

• Accelerated Program Timing Diagram (128M Page Flash)

VCCf

tVACCR

tVCS

tVLHT

VACC

VIH

WP/ACC

CEf

WE

tVLHT

Program Sequence

RY/BY

Acceleration period

CEf : CE0f or CE1f

42

MB84VP24491HK-70

4. Erase and Programing Performance (128M Page Flash)

Value

Parameter

Unit

Comments

Min

Typ

Max

Excludes programming time

prior to erasure

Sector Erase Time

—

0.5

2

s

Excludes system-level

overhead

Word Programming Time

—

6.0

100

µs

Excludes system-level

overhead

Chip Programming Time

Erase/Program Cycle

—

50.3

—

200

—

s

100,000

cycle

—

Note: Typical Erase conditions TA = + 25°C, VCC = 2.9 V

Typical Program conditions T^A= + 25°C, VCC = 2.9 V, Data = checker

43

MB84VP24491HK-70

■ 32 M FCRAM CHARACTERISTICS for MCP

1. Power Down (32M Page Mode FCRAM)

• Power Down (32M Page mode FCRAM)

The Power Down is to enter low power idle state when CE2r stays Low.

The 32M page mode FCRAM has four power down mode, Sleep, 4M Partial, 8M Partial, and 16M Partial.

These can be programmed by series of read/write operation. Each mode has follwoing features.

Mode

Data Retention

No

Retention Address

N/A

Sleep (default)

4M Partial

4M bit

00000h to 3FFFFh

00000h to 7FFFFh

00000h to FFFFFh

8M Partial

8M bit

16M Partial

16M bit

The default state is Sleep and it is the lowest power consumption but all data will be lost once CE2r is brought

to Low for Power Down. It is not required to program to Sleep mode after power-up.

• Power Down Program Sequence (32M Page mode FCRAM)

The program requires total 6 read/write operation with unique address and data. Between each read/write

operation requires that device be in standby mode. Following table shows the detail sequence.

Cycle #

1st

Operation

Read

Address

1FFFFFh (MSB)

1FFFFFh

Data

Read Data (RDa)

RDa

2nd

3rd

Write

1FFFFFh

RDa

4th

Write

1FFFFFh

0000h

5th

Write

1FFFFFh

Data Key

Read Data (RDb)

6th

Read

Address Key

The first cycle is to read from most significient address (MSB).

The second and third cycle are to write back the data (RDa) read by first cycle. If the third cycle is written into

the different address, the program is cancelled and the data written by the second or third cycle is valid as a

normal write operation.

The forth and fifth cycle is to write the data key for program. The data of forth cycle must be all 0’s and data of

fifth cycle is a data key for mode selection. If the forth cycle is written into different address, the program is also

cancelled.

The last cycle is to read from specific address key for mode selection. The both data key written by fifth cycle

and address key must be the same mode for proper programming.

Once this program sequence is performed from a Partial mode to other Partial mode, the write data may be lost.

So, it should perform this program prior to regular read/write operation if Partial mode is used.

44

MB84VP24491HK-70

• Address Key (32M Page mode FCRAM)

The address key has following format.

Address

Mode

A²⁰

A¹⁹

1

A¹⁸to A⁰

Binary

Sleep (default)

4M Partial

1

0

1

0

1

1FFFFFh

0FFFFFh

17FFFFh

07FFFFh

1

8M Partial

0

16M Partial

0

• Data Key (32M Page mode FCRAM)

The data key has following format.

Data

DQ⁷to DQ²

Mode

DQ¹⁵to DQ⁸

DQ¹

DQ⁰

1

Sleep (default)

4M Partial

0

1

0

8M Partial

1

16M Partial

0

The upper byte of data code may be ignored and it is just for recommendation to write 0’s to upper byte for future

compatibility.

45

MB84VP24491HK-70

2. AC Characteristics

• READ OPERATION (32M Page mode FCRAM)

Value

Parameter

Read Cycle Time

Symbol

Unit

Remarks

Min

Max

t^RC

tCE

70

—

25

5

1000

70

40

70

30

18

1000

—

ns

*1, *2

*3

CE1r Access Time

OE Access Time

tOE

*3

Address Access Time

tAA

*3, *5

*3

LB / UB Access Time

tBA

Page Address Access Time

Page Read Cycle Time

t^PAA

t^PRC

t^OH

*3, *6

*1, *6, *7

*3

Output Data Hold Time

CE1r Low to Output Low-Z

OE Low to Output Low-Z

LB / UB Low to Output Low-Z

CE1r High to Output High-Z

OE High to Output High-Z

LB / UB High to Output High-Z

Address Setup Time to CE1r Low

Address Setup Time to OE Low

Address Invalid Time

tCLZ

tOLZ

tBLZ

tCHZ

tOHZ

tBHZ

tASC

tASO

tAX

3

—

*4

0

—

*4

0

—

*4

—

–5

10

—

–5

15

20

—

*4

—

10

—

*5, *8

*6, *8

*9

Page Address Invalid Time

Address Hold Time from CE1r High

Address Hold Time from OE High

CE1r High Pulse Width

t^AXP

tCHAH

tOHAH

tCP

—

*1 : Maximum value is applicable if CE1r is kept at Low without change of address input of A20 to A3.

If needed by system operation, please contact local FUJITSU representative for the relaxation of 1 µs limitation.

*2 : Address should not be changed within minimum t^RC.

*3 : The output load 30 pF.

*4 : The output load 5 pF without any other load.

*5 : Applicable to A²⁰to A3 when CE1r is kept at Low.

*6 : Applicable only to A², A1 and A0 when CE1r is kept at Low for the page address access.

*7 : In case Page Read Cycle is continued with keeping CE1r stays Low, CE1r must be brought to High within 4 µs.

In other words, Page Read Cycle must be closed within 4 µs.

*8 : Applicable when at least two of address inputs among applicable are switched from previous state.

*9 : t^RC(Min) and tPRC(Min) must be satisfied.

46

MB84VP24491HK-70

• WRITE OPERATION (32M Page mode FCRAM)

Value

Parameter

Write Cycle Time

Symbol

Unit Remarks

Max

Min

t^WC

t^AS

70

0

1000

—

ns

*1, *2

*2

Address Setup Time

CE1r Write Pulse Width

WE Write Pulse Width

LB / UB Write Pulse Width

CE1r Write Recovery Time

WE Write Recovery Time

LB / UB Write Recovery Time

Data Setup Time

tCW

tWP

tBW

tWRC

tWR

tBR

45

15

20

0

—

*3

—

*3

—

*3

—

*4

1000

—

*4

t^DS

Data Hold Time

t^DH

—

Address Invalid Time after Write

t^AXW

—

10

*5

*6

OE High to CE1r Low Setup Time for

Write

tOHCL

tOES

–5

0

—

ns

OE High to Address Setup Time

for Write

*7

LB and UB Write Pulse Overlap

CE1r High Pulse Width

tBWO

tCP

20

15

—

ns

*1 : Maximum value is applicable if CE1r is kept at Low without any address change. If the relaxation is needed by

system operation, please contact local FUJITSU representative for the relaxation of 1 µs limitation.

*2 : Minimum value must be equal or greater than the sum of write pulse (tCW, tWP or tBW) and write recovery time

(tWRC, tWR or tBR).

*3 : Write pulse is defined from High to Low transition of CE1r, WE, or LB / UB, whichever occurs last.

*4 : Write recovery is defined from Low to High transition of CE1r, WE, or LB / UB, whichever occurs first.

*5 : Applicable to any address change when CE1r stays Low.

*6 : If OE is Low after minimum tOHCL, read cycle is initiated. In other word, OE must be brought to High within 5ns

after CE1r is brought to Low. Once read cycle is initiated, new write pulse should be input after minimum tRC

is met.

*7 : If OE is Low after new address input, read cycle is initiated. In other word, OE must be brought to High at the

same time or before new address valid. Once read cycle is initiated, new write pulse should be input after

minimum t^RCis met.

47

MB84VP24491HK-70

• POWER DOWN PARAMETERS (32M Page mode FCRAM)

Value

Parameter

Symbol

Unit Remarks

Min

Max

—

CE2r Low Setup Time for Power Down Entry

CE2r Low Hold Time after Power Down Entry

t^CSP

10

70

ns

t^C2LP

—

CE1r High Hold Time following CE2r High

after Power Down Exit [SLEEP mode only]

tCHH

tCHHP

tCHS

300

1

—

µs

ns

*1

*2

CE1r High Hold Time following CE2r High

after Power Down Exit [not in SLEEP mode]

CE1r High Setup Time following CE2r High

after Power Down Exit

0

*1 : Applicable also to power-up.

*2 : Applicable when 4M, 8M, and 16M Partial mode is programmed.

• OTHER TIMING PARAMETERS (32M Page mode FCRAM)

Value

Parameter

Symbol

Unit Remarks

Min

10

Max

—

CE1r High to OE Invalid Time for Standby Entry

CE1r High to WE Invalid Time for Standby Entry

CE1r High Hold Time following CE2r High after Power-up

Input Transition Time

tCHOX

tCHWX

tCHH

t^T

ns

10

—

ns

µs

ns

*1

*2

300

1

—

25

*1 : Some data might be written into any address location if t^CHWX(Min) is not satisfied.

*2 : The Input Transition Time (tT) at AC testing is 5 ns as shown in below. If actual tT is longer than 5ns,

it may violate AC specification of some timing parameters.

• AC TEST CONDITIONS (32M Page mode FCRAM)

Description

Input High Level

Symbol

V^IH

Test Setup

Value

VCCr

Unit

V

Remarks

—

Input Low Level

VIL

—

VSS

V

Input Timing Measurement Level

Input Transition Time

VREF

tT

—

VCCr × 0.5

5

V

Between VIL and VIH

ns

48

MB84VP24491HK-70

• READ Timing #1 (Basic Timing) (32M Page FCRAM)

tRC

Address Valid

Address

CE1r

tASC

tCHAH

tASC

tCE

tCP

tCHZ

tOE

OE

tOHZ

tBA

LB / UB

tBHZ

tBLZ

tOLZ

tCLZ

tOH

DQ

(Output)

Valid Data Output

Note : CE2r and WE must be High for entire read cycle.

49

MB84VP24491HK-70

• READ Timing #2 (OE & Address Access) (32M Page FCRAM)

tAx

tRC

Address

Address Valid

tAA

tOHAH

CE1r

Low

tASO

tOE

OE

LB / UB

tOHZ

tOLZ

tOH

DQ

(Output)

Valid Data Output

Note : CE2r and WE must be High for entire read cycle.

50

MB84VP24491HK-70

• READ Timing #3 (LB / UB Byte Access) (32M Page FCRAM)

tAX

tRC

tAx

Address

Address Valid

tAA

CE1r, OE

Low

tBA

LB

tBA

UB

tBHZ

tOH

tBHZ

tBLZ

tOH

tBLZ

DQ7 to DA0

(Output)

Valid Data

Output

Valid Data

Output

tBHZ

tOH

tBLZ

DQ15 to DQ8

(Output)

Valid Data Output

Note : CE2r and WE must be High for entire read cycle.

51

MB84VP24491HK-70

• READ Timing #4 (Page Address Access after CE1r Control Access) (32M Page FCRAM)

tRC

Address

(A²⁰to A3)

Address Valid

tRC

tPRC

Address

(A²to A0)

Address

Valid

Address

Valid

Address

Valid

Address Valid

tASC

tPAA

tCHAH

CE1r

OE

tCE

tCHZ

LB / UB

tOH

tCLZ

DQ

(Output)

Valid Data Output

(Page Access)

Valid Data Output

(Normal Access)

Note : CE2r and WE must be High for entire read cycle.

52

MB84VP24491HK-70

• READ Timing #5 (Random and Page Address Access) (32M Page FCRAM)

tRC

tAX

tRC

tAx

Address

(A²⁰to A3)

Address Valid

tRC

tPRC

t^RC

tPRC

Address

(A²to A0)

Address

Valid

Address

Valid

Address

Valid

Address

Valid

tPAA

tAA

tPAA

CE1r

Low

tASO

tOE

tBA

OE

LB / UB

tOH

tOLZ

tBLZ

tOH

DQ

(Output)

Valid Data Output

(Page Access)

Valid Data Output

(Normal Access)

Note : CE2r and WE must be High for entire read cycle.

Either or both LB and UB must be Low when both CE1r and OE are Low.

53

MB84VP24491HK-70

• WRITE Timing #1 (Basic Timing) (32M Page FCRAM)

tWC

Address

CE1r

Address Valid

tAS

tWRC

tWR

tBR

tAS

tCW

tAS

tWP

WE

tAS

tBW

LB, UB

tOHCL

OE

tDS

tDH

DQ

(Input)

Valid Data Input

Note : CE2r must be High for write cycle.

54

MB84VP24491HK-70

• WRITE Timing #2 (WE Control) (32M Page FCRAM)

tWC

Address Valid

Address

CE1r

WE

tOHAH

Low

tAS

tWP

tWR

tAS

tWP

tWR

LB, UB

OE

tOES

tOHZ

tDS

tDH

tDS

tDH

DQ

(Input)

Valid Data Input

Note : CE2r must be High for write cycle.

55

MB84VP24491HK-70

• WRITE Timing #3-1 (WE / LB / UB Byte Write Control) (32M Page FCRAM)

tWC

Address Valid

Address

CE1r

Low

tAS

tWP

tAS

tWP

WE

tBR

LB

tBR

UB

tDS

tDH

DQ⁷to DQ0

(Input)

tDS

tDH

Valid Data Input

DQ15 to DQ8

(Input)

Valid Data Input

Note : CE2r must be High for write cycle.

56

MB84VP24491HK-70

• WRITE Timing #3-2 (WE / LB / UB Byte Write Control) (32M Page FCRAM)

tWC

Address Valid

Address

CE1r

Low

tWR

WE

tAS

tBW

LB

tAS

tBW

UB

tDS

tDH

DQ⁷to DQ0

(Input)

tDS

tDH

Valid Data Input

DQ15 to DQ8

(Input)

Valid Data Input

Note : CE2r must be High for write cycle.

57

MB84VP24491HK-70

• WRITE Timing #3-3 (WE / LB / UB Byte Write Control) (32M Page FCRAM)

tWC

Address Valid

Address

CE1r

Low

WE

tAS

tBW

tBR

LB

tAS

tBW

tBR

UB

tDS

tDH

DQ⁷to DQ0

(Input)

tDS

tDH

Valid Data Input

DQ15 to DQ8

(Input)

Valid Data Input

Note : CE2r must be High for write cycle.

58

MB84VP24491HK-70

• WRITE Timing #3-4 (WE / LB / UB Byte Write Control) (32M Page FCRAM)

tWC

Address Valid

Address

CE1r

Low

WE

tAS

tBW

tBR

tAS

tBW

tBR

LB

tBWO

tDS

tDH

tDS

tDH

DQ7 to DQ0

(Input)

Valid

Data Input

Valid

Data Input

tBWO

tBW

tAS

tBW

tBR

tAS

tBR

UB

tDS

tDH

tDS

tDH

DQ15 to DQ8

(Input)

Valid

Data Input

Valid

Data Input

Note : CE2r must be High for write cycle.

59

MB84VP24491HK-70

• READ / WRITE Timing #1-1 (CE1r Control) (32M Page FCRAM)

tWC

tRC

Address

CE1r

Write Address

Read Address

tCHAH

tWRC

tAS

tASC

tCHAH

tCW

tCE

tCP

WE

UB, LB

OE

tOHCL

tCHZ

tDH

tOH

tDS

tCLZ

tOH

DQ

Read Data Output

Write Data Input

Note : Write address is valid from either CE1r or WE of last falling edge.

60

MB84VP24491HK-70

• READ / WRITE Timing #1-2 (CE1r / WE / OE Control) (32M Page FCRAM)

tWC

tRC

Address

CE1r

Write Address

Read Address

tCHAH

tAS

tWR

tASC

tCHAH

tCE

tCP

tWP

WE

UB, LB

OE

tOHCL

tOE

tCHZ

tOH

tDS

tDH

tOLZ

tOH

DQ

Read Data Output

Write Data Input

Read Data Output

Note : OE can be Low fixed in write operation under CE1r control RD-WR-RD operation.

61

MB84VP24491HK-70

• READ / WRITE Timing #2 (OE, WE Control) (32M Page FCRAM)

tWC

tRC

Address

CE1r

Write Address

Read Address

tAA

tOHAH

Low

tAS

tWR

tWP

WE

tOES

UB, LB

OE

tASO

tOE

tOHZ

tOH

tDS

tDH

tOLZ

tOH

DQ

Read Data Output

Write Data Input

Note : CE1r can be tied to Low for WE and OE controlled operation.

When CE1r is tied to Low, output is exclusively controlled by OE.

62

MB84VP24491HK-70

• READ / WRITE Timing #3 (OE, WE, LB, UB Control) (32M Page FCRAM)

tWC

tRC

Address

CE1r

Write Address

Read Address

tAA

tOHAH

Low

WE

tOES

tAS

tBW

tBR

tBA

UB, LB

OE

tASO

tBHZ

tOH

tDS

tDH

tBLZ

tOH

DQ

Read Data Output

Write Data Input

Note : CE1r can be tied to Low for WE and OE controlled operation.

When CE1r is tied to Low, output is exclusively controlled by OE.

63

MB84VP24491HK-70

• POWER-UP Timing (32M Page FCRAM)

CE1r

CE2r

tCHH

VCCr

VCCr Min

0V

Note : The t^CHHspecifies after VCCr reaches specified minimum level and applicable both CE1r and CE2r.

• POWER DOWN Entry and Exit Timing

CE1r

tCHS

CE2r

tCSP

tC2LP

tCHH (tCHHP)

High-Z

DQ

Power Down Entry

Power Down Mode

Power Down Exit

Note : This Power Down mode can be also used as a reset timing if POWER-UP timing above could not be satisfied

and Power-Down program was not performed prior to this reset.

• Standby Entry Timing after Read or Write (32M Page FCRAM)

CE1r

tCHOX

tCHWX

OE

WE

Active (Read)

Standby

Active (Write)

Standby

Note : Both t^CHOXand tCHWX define the earliest entry timing for Standby mode.

If either of timing is not satisfied, it takes tRC (Min) period for Standby mode from CE1r Low to High transition.

64

MB84VP24491HK-70

• POWER DOWN PROGRAM Timing (32M Page FCRAM)

tRC

tWC

tRC

MSB*¹

Key*²

Address

CE1r

OE

tCP*⁴

tCP

WE

LB, UB

DQ*³

Key*³

Cycle #5

RDa

Cycle #1

RDa

Cycle #2

RDa

Cycle #3

00

Cycle #4

RDb

Cycle #6

*1 : The all address inputs must be High from Cycle #1 to #5.

*2 : The address key must confirm the format specified in “■ 32 M FCRAM CHARACTERISTICS for MCP 1. Power

Down Program Timing (32 M Page FCRAM) ”. If not, the operation and data are not guaranteed.

*3 : The data key must confirm the format specified in “■ 32 M FCRAM CHARACTERISTICS for MCP 1. Power

Down Program Timing (32 M Page FCRAM) ”. If not, the operation and data are not guaranteed.

*4 : After t^CPfollowing Cycle #6, the Power Down Program is completed and returned to the normal operation.

65

MB84VP24491HK-70

■ PIN CAPACITANCE

Value

Typ

Parameter

Symbol

Condition

Unit

Min

Max

14.0

16.0

26.0

Input Capacitance

C^IN

VIN = 0

11.0

12.0

14.0

21.5

pF

Output Capacitance

COUT

C^IN2

CIN3

VOUT = 0

VIN = 0

Control Pin Capacitance

WP/ACC Pin Capacitance

Note: Test conditions TA = + 25°C, f = 1.0 MHz

■ HANDLING OF PACKAGE

Please handle this package carefully since the sides of package create acute angles.

■ CAUTION

• The high voltage (VID) cannot apply to address pins and control pins except RESET. Exception is when

autoselect and sector group protect function are used, then the high voltage (VID) can be applied to RESET.

• Without the high voltage (VID) , sector group protection can be achieved by using “Extended Sector Group

Protection” command.

66

MB84VP24491HK-70

■ ORDERING INFORMATION

MB84VP24491

HK

-70

PBS

Package Type

PBS = 73-ball FBGA

Speed Option

Device Revision

Device Number/Description

128Mega-bit (4M × 16-bit + 4M × 16-bit) Dual Operation Flash Memory

Dual Chip Enable

3.0V-only Read, Program, and Erase

32Mega-bit(2M × 16-bit) Mobile FCRAM

67

MB84VP24491HK-70

■ PACKAGE DIMENSION

73-ball plastic FBGA

(BGA-73P-M03)

11.60±0.10(.457±.004)

0.20(.008)

S

B

1.19 ⁺–0⁰.^.1¹0⁵.047 –⁺.^.0⁰0⁰4⁶

(Seated height)

0.40(.016)

REF

0.80(.031)

REF

10

9

8

7

6

5

4

3

2

1

0.80(.031)

REF

A

8.00±0.10

(.315±.004)

0.40(.016)

REF

0.10(.004)

S

M

L

K

J

H

G

F

E

D

C

B

A

0.39±0.10

(.015±.004)

(Stand off)

INDEX-MARK AREA

S

INDEX BALL

S AB

0.20(.008) S A

73-ø0.45 –⁺.⁰0^.0¹5⁰

73-ø0.18 –⁺.^.0⁰0⁰2⁴

M

ø0.08(.003)

0.10(.004)

S

C

2003 FUJITSU LIMITED B73003S-c-1-1

Dimensions in mm (inches) .

Note : The values in parentheses are reference values.

68

MB84VP24491HK-70

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

F0312

FUJITSU LIMITED Printed in Japan


型号：	MB84VP24491HK-70PBS
厂家：	FUJITSU
描述：	128M (X16) FLASH MEMORY 32M (X16) Mobile FCRAMTM 128M （ X16 ）闪存32M （ X16 ）手机FCRAMTM 闪存存储内存集成电路静态存储器手机
文件：	总70页 (文件大小：1179K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB84VP24491HK-70PBS [FUJITSU]

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