MB84VZ064G-70PBS_技术文档

MB84VZ064G-70

Data Sheet

July 2003

The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices

and Fujitsu. Although the document is marked with the name of the company that originally developed the specifi-

cation, these products will be offered to customers of both AMD and Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that

have been made are the result of normal datasheet improvement and are noted in the document revision summary,

where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision sum-

mary.

Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order these prod-

ucts, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions.

Publication Number 26829 Revision A Amendment 0 Issue Date October 25, 2002

FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-50502-1E

4 Stacked MCP (Multi-Chip Package) FLASH & FLASH & FCRAM & SRAM

CMOS

64M (×16) FLASH MEMORY & 64M (×16) FLASH MEMORY &

64M (×16) Mobile FCRAM^TM& 8M (×16) STATIC RAM

MB84VZ064G-70

■ FEATURES

• Power Supply Voltage of 2.7 V to 3.1 V

• High Performance

70 ns maximum access time (Flash_1or Flash_2)

70 ns maximum access time (FCRAM)

70 ns maximum access time (SRAM)

• Operating Temperature

–30 °C to +85 °C

• Package 107-ball BGA

(Continued)

■ PRODUCT LINEUP

Flash_1 or Flash_2

FCRAM

SRAM

+0.1 V

–0.3 V

Supply Voltage (V)

V^CCf_1*/VCCf_2* = 3.0 V

VCCr* = 3.0 V

VCCs* = 3.0 V

–0.3 V

Max Address Access Time (ns)

Max CE Access Time (ns)

Max OE Access Time (ns)

70

30

70

40

70

35

* : All of VCCf_1, VCCf_2, VCCr and VCCs must be the same level when either part is being accessed.

■ PACKAGE

107-ball plastic FBGA

BGA-107P-M01

MB84VZ064G-70

(Continued)

1. FLASH MEMORY_1 and FLASH MEMORY_2

• Simultaneous Read/Write Operations (Dual Bank)

• FlexBank^TM*¹

Bank A : 8 Mbit (8 KB × 8 and 64 KB × 15)

Bank B : 24 Mbit (64 KB × 48)

Bank C : 24 Mbit (64 KB × 48)

Bank D : 8 Mbit (8 KB × 8 and 64 KB × 15)

Two virtual Banks are chosen from the combination of four physical banks.

Host system can program or erase in one bank, and then read immediately and simultaneously from the other

bank with zero latency between read and write operations.

Read-while-erase

Read-while-program

• Minimum 100,000 Program/Erase Cycles

• Sector Erase Architecture

Sixteen 4 Kword and one hundred twenty-six 32 Kword sectors in word.

Any combination of sectors can be concurrently erased. It also supports full chip erase.

• HiddenROM Region

256 byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence

Factory serialized and protected to provide a secure electronic serial number (ESN)

• WP/ACC Input Pin

AtV^IL, allowsprotectionof“outermost”2× 8Kbytesonbothendsofbootsectors, regardlessofsectorprotection/

unprotection status

At V^IH, allows removal of boot sector protection

At VACC, increases program performance

• Embedded Erase^TM*³Algorithms

Automatically preprograms and erases the chip or any sector

• Embedded Program^TM*³Algorithms

Automatically writes and verifies data at specified address

• Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion

• Ready/Busy Output (RY/BY_1 or RY/BY_2)

Hardware method for detection of program or erase cycle completion

• Automatic Sleep Mode

When addresses remain stable, the device automatically switches itself to low power mode.

• Low V^CCf write Inhibit ≤ 2.5 V

• Program Suspend/Resume

Suspends the program operation to allow a read in another byte

• Erase Suspend/Resume

Suspends the erase operation to allow a read data and/or program in another sector within the same device

• Please Refer to “MBM29DL64DF” Datasheet in Detailed Function.

(Continued)

2

MB84VZ064G-70

(Continued)

2. FCRAM *³

• Power Dissipation

Operating : 25 mA Max

Standby

: 200 µA Max

• Power Down Mode

Sleep

NAP

: 10 µA Max

: 65 µA Max

16M Partial : 85 µA Max

• Power Down Control by CE2r

• Byte Write Control: LB(DQ⁷to DQ⁰), UB(DQ¹⁵to DQ⁸)

• 8 words Address Access Capability

3. SRAM

• Power Dissipation

Operating: 50 mA Max

Standby : 15 µA Max

• Power Down Features using CE1s and CE2s

• Data Retention Supply Voltage: 1.5 V to 3.1 V

• CE1s and CE2s Chip Select

• Byte Data Control: LB (DQ⁷to DQ⁰), UB (DQ¹⁵to DQ⁸)

*1 : FlexBank^TMis a trademark of Fujitsu Limited, Japan.

*2 : Embedded Erase^TMand Embedded Program^TMare trademarks of Advanced Micro Devices, Inc.

*3 : FCRAM^TMis a trademark of Fujitsu Limited, Japan.

3

MB84VZ064G-70

■ PIN ASSIGNMENT

(Top View)

Marking Side

A10

E10

N.C.

E9

J10

N.C.

J9

M10

N.C.

F10

N.C.

F9

G10

N.C.

G9

H10

N.C.

H9

B10

N.C.

B9

C10

N.C.

C9

D10

N.C.

D9

K10

N.C.

K9

L10

N.C.

L9

N.C.

A9

M9

N.C.

B8

N.C.

C8

A15

D8

A21

E8

N.C.

F8

A16

G8

VCCf_1

H8

VSS

J8

N.C.

K8

N.C.

L8

N.C.

A11

C7

A12

D7

A13

E7

A14

F7

PE

DQ15

H7

DQ7

J7

DQ14

K7

N.C.

L7

G7

B7

N.C.

B6

A8

A19

D6

A9

A10

F6

DQ6

G6

DQ13

H6

DQ12

J6

DQ5

K6

N.C.

L6

C6

E6

N.C.

B5

WE

C5

CE2r

D5

A20

E5

N.C.

F5

CE2s

G5

DQ4

H5

VCCr

J5

N.C.

K5

N.C.

L5

CEf_2 WP/ACC RESET_1 RY/BY_1

CE1s

F4

VCCs

G4

DQ3

H4

VCCf_1

J4

DQ11

K4

VCCf_2

L4

E4

A18

E3

B4

RY/BY_2

B3

C4

LB

D4

UB

D3

A6

A17

F3

DQ1

G3

DQ9

H3

DQ10

J3

DQ2

K3

VSS

L3

C3

VSS

B2

A7

A5

E2

A4

VSS

G2

OE

DQ0

J2

DQ8

K2

RESET_2

L2

D2

A3

M2

A2

N.C.

A1

F2

H2

C2

N.C.

C1

A2

E1

A1

A0

CEf_1

H1

CE1r

J1

N.C.

K1

N.C.

L1

F1

G1

M1

D1

N.C.

(BGA-107P-M01)

4

MB84VZ064G-70

■ PIN DESCRIPTION

Input/

Output

Pin name

Description

A¹⁸to A0

A21 to A19

DQ¹⁵to DQ0

CEf_1

CEf_2

CE1r

I

Address Inputs (Common)

I

Address Inputs (FCRAM & Flash_1 & Flash_2 )

Data Inputs/Outputs (Common)

Chip Enable (Flash_1)

I/O

I

Chip Enable (Flash_2)

I

Chip Enable (FCRAM)

CE1s

I

Chip Enable (SRAM)

CE2r

I

Chip Enable (FCRAM)

CE2s

I

Chip Enable (SRAM)

OE

I

Output Enable (Common)

WE

I

Write Enable (Common)

RY/BY_1

RY/BY_2

UB

O

Ready/Busy Output (Flash_1) Open Drain Output

Ready/Busy Output (Flash_2) Open Drain Output

Upper Byte Control (FCRAM & SRAM)

Lower Byte Control (FCRAM & SRAM)

Hardware Reset Pin/Sector Protection Unlock (Flash_1)

Hardware Reset Pin/Sector Protection Unlock (Flash_2)

Write Protect / Acceleration (Flash_1 & Flash_2)

Partial Enable (FCRAM)

O

I

LB

I

RESET_1

RESET_2

WP/ACC

PE

I

N.C.

—

No Internal Connection

VSS

Power

Device Ground (Common)

V^CCf_1

VCCf_2

VCCr

Device Power Supply (Flash_1)

Device Power Supply (Flash_2)

Device Power Supply (FCRAM)

Device Power Supply (SRAM)

VCCs

5

MB84VZ064G-70

■ BLOCK DIAGRAM

V^CCf_1

V^SS

A²¹to A⁰

RY/BY_1

64 M bit

Flash Memory_1

RESET_1

CEf_1

V^CCf_2

V^SS

A²¹to A⁰

RY/BY_2

64 M bit

Flash Memory_2

WP/ACC

RESET_2

CEf_2

DQ¹⁵to DQ⁰

V^CCr

V^SS

A²¹to A⁰

64 M bit

FCRAM

LB

UB

WE

OE

CE1r

CE2r

PE

V^CCs

V^SS

A¹⁸to A⁰

8 M bit

SRAM

CE1s

CE2s

6

MB84VZ064G-70

■ DEVICE BUS OPERATIONS

WP/

A²⁰DQ⁷DQ¹⁵

Operation*^1,*²

CEf_1 CEf_2 CE1r CE2r CE1s CE2s

RESET_1 RESET_2 ACC

OE WE LB UB PE to

A⁰

to

12

DQ⁰DQ⁸

*

H

X

H

X

L

X

L

High-Z High-Z

H

L

H

L

H

L

H

X

H

X

H

X

H

X

H

X

Full Standby

X*¹⁰

H

X

H

X

H

X

H

L

H

Output Disable*³

H

High-Z High-Z

X

H

X

H

X

H

X

H

X

H

X

H

X

H

X

L

X

L

X

L

X

L

X

L

X

L

X

L

H

X

H

X

H

L

Read from Flash_1*⁴

Read from Flash_2*⁴

Write to Flash _1

Valid

H

L

H

L

H

L

X

H

DOUT

DIN

DOUT

DIN

H

X

H

L

H

L

H

L

H

L

DIN

Write to Flash_2

Read from FCRAM*⁵

H

H L*⁹L*⁹

DOUT

DIN

DOUT

DIN

L

H

L

H

X

L

X

L

H

Valid High-Z DIN

High-Z

DIN

H

L

DIN

H

L

H

L

H

X

Write to FCRAM

L

H

L

Valid High-Z DIN

High-Z

DOUT

High-Z

DIN

H

L

DIN

DOUT

L

Valid High-Z

DOUT

Read from SRAM

Write to SRAM

H

L

H

L

H

L

H

X

H

L

DIN

Valid High-Z

DIN

L

H

L

DIN

High-Z

H

(Continued)

7

MB84VZ064G-70

(Continued)

WP/

A²⁰

OE WE LB UB PE to

A⁰

DQ⁷DQ¹⁵

Operation*^1,*²

CEf_1 CEf_2 CE1r CE2r CE1s CE2s

RESET_1 RESET_2 ACC

to

12

DQ⁰DQ⁸

*

Flash_1 Temporary

Sector Group

X

VID

X

Unprotection*⁶

Flash_ 2 Temporary

Sector Group

Unprotection*⁶

X

VID

High-Z High-Z

H

X

H

X

L

X

L

Flash_1 Hardware

Reset

X

H

X

L

X

L

X

Flash_2 Hardware

Reset

X

Flash_1 or 2 Boot

Block Sector Write

Protection

X

H

X

H

X

H

X

H

X

L

X

H

X

H

L

H

X

H

X

L

X

L

FCRAM Power

Down Program

Valid

*11

High-Z High-Z

X

FCRAM NO READ*⁷

H

X

H

X

L

H

L

H

X

H

X

H

X

H

X

Valid

X

H

X

H

X

FCRAM Power

Down*⁸

X

Legend: L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels.

*1 : Other operations except for indicated this column are inhibited.

*2 : Do not apply for a following state two or more on the same time;

1) CEf_1 = VIL, 2)CEf_2 = VIL, 3) CE1r = VIL and CE2r = VIH, 4) CE1s = VIL and CE2s = VIH

*3 : FCRAM Output Disable condition should not be kept longer than 1 µs.

*4 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations.

*5 : FCRAM LB, UB control at Read operation is not supported.

*6 : It is also used for the extended sector group protections.

*7 : The FCRAM Power Down Program can be performed one time after compliance of Power-UP timings and it

should not be re-programmed after regular Read or Write.

*8 : FCRAM Power Down mode can be entered from Standby state and all DQ pins are in High-Z state.

IPDr current and data retention depends on the selection of Power Down Program.

*9 : Either or both LB and UB must be Low for FCRAM Read Operation.

*10 : Can be either VIL or VIH but must be valid before Read or Write.

*11 : See “FCRAM Power Down Program Key Table” in “■ 64 M FCRAM CHARACTERISTICS for MCP”.

*12 : Protect “ outer most “ 2 × 8K bytes ( 4 words ) on both ends of the boot block sectors.

8

MB84VZ064G-70

■ ABSOLUTE MAXIMUM RATINGS

Rating

Unit

Parameter

Symbol

Min

Max

Storage Temperature

Tstg

–55

–30

+125

°C

V

Ambient Temperature with Power Applied

TA

+85

V^CCf_1 + 0.3

V^CCf_2 + 0.3

VCCr + 0.3

V^CCs + 0.3

V

Voltage with Respect to Ground All pins

except RESET_1 or RESET_2, WP/ACC *¹

VIN, VOUT

–0.3

V

VCCf_1,VCCf_2,

VCCr, VCCs

V^CCf_1/VCCf_2/VCCr/VCCs Supply *¹

–0.3

+3.3

V

RESET_1 or RESET_2 *²

WP/ACC *³

VIN

–0.5

+ 13.0

+10.5

V

*1 : Minimum DC voltage on input or I/O pins is –0.3 V. During voltage transitions, input or I/O pins may undershoot

VSS to –1.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCCf_1 + 0.3 V or

VCCf_2 + 0.3 V or VCCr + 0.3 V or VCCs + 0.3 V. During voltage transitions, input or I/O pins may overshoot to

VCCf_1 + 2.0 V or VCCf_2 + 2.0 V or VCCr + 1.0 V or VCCs + 2.0 V for periods of up to 20 ns.

*2 : Minimum DC input voltage on RESET_1 or RESET_2 pin is –0.5 V. During voltage transitions RESET_1 or

RESET_2 pins may undershoot VSS to –2.0 V for periods of up to 20 ns.

Voltage difference between input and supply voltage (VIN-VCCf_1 or VCCf_2) does not exceed +9.0 V.

Maximum DC input voltage on RESET_1 or RESET_2 pins is +13.0 V which may overshoot to +14.0 V for

periods of up to 20 ns.

*3 : Minimum DC input voltage on WP/ACC pin is –0.5 V. During voltage transitions, WP/ACC pin may undershoot

Vss to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may

overshoot to +12.0 V for periods of up to 20 ns, when VCCf_1 or VCCf_2 is applied.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■ RECOMMENDED OPERATING CONDITIONS

Value

Parameter

Symbol

Unit

Min

Max

Ambient Temperature

T^A

–30

+85

°C

V

VCCf_1/VCCf_2/VCCr/VCCs Supply

Voltages

VCCf_1,VCCf_2,VCCr,VCCs

+2.7

+3.1

Note: Operating ranges define those limits between which the functionality of the device is guaranteed.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

9

MB84VZ064G-70

■ ELECTRICAL CHARACTERISTICS

1. DC Characteristics

Value

Parameter

Symbol

Conditions

Unit

Min Typ Max

Input Leakage Current

Output Leakage Current

I^LI

VIN = VSS to VCCf_1,VCCr,VCCs

VOUT = VSS to VCCf_1,VCCr,VCCs

–1.0

—

+1.0 µA

I^LO

RESET Inputs Leakage

Current

VCCf= VCCf Max,

RESET = 12.5 V

ILIT

—

35

µA

tCYCLE =5 MHz

—

18

4

mA

Flash V^CCActive Current

(Read) *¹

CEf = VIL,

OE = VIH

ICC1f

t^CYCLE=1 MHz

Flash V^CCActive Current

(Program/Erase) *²

ICC2f

ICC3f

ICC4f

ICC5f

IACC

CEf = VIL, OE = VIH

—

35

53

40

20

mA

Flash VCC Active Current

(Read-While-Program) *⁵

Flash VCC Active Current

(Read-While-Erase) *⁵

Flash V^CCActive Current

(Erase-Suspend-Program)

WP/ACC Acceleration

Program Current

VCCf = VCCf Max,

WP/ACC = VACC Max

V^CCr = VCCr Max,

t^RC/ tWC =Min

—

25

3

FCRAM V^CCActive Current

ICC1r

CE1r = VIL, CE2r = VIH,

VIN = VIH or VIL, IOUT = 0 mA

mA

t^RC/ tWC =1 µs

VCCs = VCCs Max,

CE1s = VIL, CE2s = VIH

SRAM V^CCActive Current

ICC1s

ICC2s

tCYCLE =10 MHz

—

50

t^CYCLE=10 MHz

t^CYCLE=1 MHz

—

50

10

mA

CE1s = 0.2 V,

CE2s = VCCs – 0.2 V

VCCf = VCCf Max, CEf = VCCf ± 0.3 V,

RESET = VCCf ± 0.3 V,

WP/ACC = VCCf ± 0.3 V

Flash V^CCStandby Current

ISB1f

ISB2f

—

1 *⁷

5 *⁷

µA

Flash VCC Standby Current

(RESET)

VCCf = VCCf Max, RESET = VSS ± 0.3 V,

WP/ACC = VCCf ± 0.3 V

VCCf = VCCf Max, CEf = VSS ± 0.3 V,

RESET = VCCf ± 0.3 V,

WP/ACC = VCCf ± 0.3 V,

Flash V^CCCurrent (Automatic

Sleep Mode) *³

ISB3f

—

1 *⁷

5 *⁷

µA

VIN = VCCf ± 0.3 V or VSS ± 0.3 V

(Continued)

10

MB84VZ064G-70

(Continued)

Parameter

Value

Unit

Symbol

Conditions

Min

Typ

Max

VCCr = VCCr Max,CE1r > VCCr – 0.2 V,

CE2r > VCCr – 0.2 V,

V^IN< 0.2 V or VCCr – 0.2 V

FCRAM V^CCStandby Current

ISB1r

—

200

µA

Sleep

I^PDSr

I^PDNr

—

10

65

µA

VCCr = VCCr Max,

FCRAM V^CCPower Down

Current

CE1r > VCCr – 0.2 V,

CE2r < 0.2 V,

NAP

16 M

Partial

VIN Cycle time = tRC Min

IPD8r

ISB1s

—

85

15

µA

SRAM VCC Standby

Current

CE1s > VCCs – 0.2 V,

CE2s > VCCs – 0.2 V

SRAM V^CCStandby

Current

I^SB2s CE2s < 0.2 V

—

15

µA

Input Low Level

Input High Level

V^IL

—

–0.3

2.2

—

0.5

V

VCC + 0.3 *⁶

VIH

Voltage for Sector Protection,

and Temporary Sector

VID

—

11.5

8.5

—

12.5

9.5

V

Unprotection (RESET) *⁴

Voltage for WP/ACC Sector

Protection/Unprotection and

Program Acceleration *⁴

VACC

9.0

V^OLf

V^OLr

VCCf = VCCf Min, IOL=4.0 mA

Flash

—

0.45

0.4

—

V

Output Low Voltage Level

Output High Voltage Level

VCCr = VCCr Min, IOL =1.0 mA FCRAM

VOLs VCCs = VCCs Min, IOL=1.0 mA SRAM

VOHf VCCf = VCCf Min, IOH=–0.1 mA

Flash VCCf − 0.4

V^OHr VCCr = VCCr Min, IOH =–0.5 mA FCRAM

VOHs VCCs = VCCs Min, IOH=–0.5 mA SRAM

2.2

—

Flash Low VCCf Lock-Out

Voltage

VLKO

—

2.3

2.4

2.5

V

Legend: Flash means Flash_1 or Flash_2, VCCf means VCCf_1 or VCCf_2, VSSf means VSSf_1 or VSSf_2, CEf means

CEf_1 or CEf _2, RESET means RESET_1 or RESET_2

*1: The I^CCcurrent listed includes both the DC operating current and the frequency dependent component.

*2: ICC active while Embedded Algorithm (program or erase) is in progress.

*3: Automatic sleep mode enables the low power mode when address remains stable for 150 ns.

*4: Applicable for only VCCf applying.

*5: Embedded Alogorithm (program or erase) is in progress. (@5 MHz)

*6: V^CCindicates lower of VCCf_1 or VCCf_2 or VCCs or VCCr.

*7: Actual Standby Current is twice of what is indicated in the table, due to two Flash memory chips embedment

with in one device.

11

MB84VZ064G-70

2. AC Characteristics

• CE Timing

Symbol

Value

Parameter

Condition

Unit

JEDEC

Standard

tCCR

Min

0

Max

—

CE Recover Time

CE Hold Time

—

ns

tCHOLD

3

—

CE1r, CE1s High to WE Invalid time

for Standby Entry

—

tCHWX

—

10

—

ns

• Timing Diagram for alternating RAM to Flash_1 or Flash_2

CEf

tCCR

CE1r or

CE1s

WE

tCHWX

tCHOLD

tCCR

CE2r or

CE2s

• Flash_1 Characteristics

Please refer to “■64M FLASH MEMORY CHARACTERISTICS for MCP” part. In this part, Flash means

Flash_1, V^CCf means VCCf_1, VSSf means VSSf_1, CEf means CEf _1, RESET means RESET_1

• Flash_2 Characteristics

Please refer to “■64M FLASH MEMORY CHARACTERISTICS for MCP” part. In this part, Flash means

Flash_2, V^CCf means VCCf_2, VSSf means VSSf_2, CEf means CEf _2, RESET means RESET_2

• FCRAM Characteristics

Please refer to “■64M FCRAM CHARACTERISTICS for MCP” part.

• SRAM Characteristics,

Please refer to “■8M SRAM CHARACTERISTICS for MCP” part.

12

MB84VZ064G-70

■ 64M FLASH MEMORY CHARACTERISTICS for MCP

1. Flexible Sector-erase Architecture on Flash Memory

• Sixteen 4 K words, and one hundred twenty-six 32 K words.

• Individual-sector, multiple-sector, or bulk-erase capability.

Word Mode

200000h

Word Mode

000000h

SA0 : 8KB (4KW)

001000h

SA71 : 64KB (32KW)

208000h

SA1 : 8KB (4KW)

002000h

SA72 : 64KB (32KW)

210000h

SA2 : 8KB (4KW)

003000h

SA73 : 64KB (32KW)

218000h

SA3 : 8KB (4KW)

004000h

SA74 : 64KB (32KW)

220000h

SA4 : 8KB (4KW)

005000h

SA75 : 64KB (32KW)

228000h

SA5 : 8KB (4KW)

006000h

SA76 : 64KB (32KW)

230000h

SA6 : 8KB (4KW)

007000h

SA77 : 64KB (32KW)

238000h

SA7 : 8KB (4KW)

008000h

SA78 : 64KB (32KW)

240000h

SA8 : 64KB (32KW)

010000h

SA79 : 64KB (32KW)

248000h

SA9 : 64KB (32KW)

018000h

SA80 : 64KB (32KW)

250000h

Bank A

SA10 : 64KB (32KW)

SA11 : 64KB (32KW)

SA12 : 64KB (32KW)

SA13 : 64KB (32KW)

SA14 : 64KB (32KW)

SA15 : 64KB (32KW)

SA16 : 64KB (32KW)

SA17 : 64KB (32KW)

SA18 : 64KB (32KW)

SA19 : 64KB (32KW)

SA20 : 64KB (32KW)

SA21 : 64KB (32KW)

SA22 : 64KB (32KW)

SA23 : 64KB (32KW)

SA24 : 64KB (32KW)

SA25 : 64KB (32KW)

SA26 : 64KB (32KW)

SA27 : 64KB (32KW)

SA28 : 64KB (32KW)

SA29 : 64KB (32KW)

SA30 : 64KB (32KW)

SA31 : 64KB (32KW)

SA32 : 64KB (32KW)

SA33 : 64KB (32KW)

SA34 : 64KB (32KW)

SA35 : 64KB (32KW)

SA36 : 64KB (32KW)

SA37 : 64KB (32KW)

SA38 : 64KB (32KW)

SA39 : 64KB (32KW)

SA40 : 64KB (32KW)

SA41 : 64KB (32KW)

SA42 : 64KB (32KW)

SA43 : 64KB (32KW)

SA44 : 64KB (32KW)

SA45 : 64KB (32KW)

SA46 : 64KB (32KW)

SA47 : 64KB (32KW)

SA48 : 64KB (32KW)

SA49 : 64KB (32KW)

SA50 : 64KB (32KW)

SA51 : 64KB (32KW)

SA52 : 64KB (32KW)

SA53 : 64KB (32KW)

SA54 : 64KB (32KW)

SA55 : 64KB (32KW)

SA56 : 64KB (32KW)

SA57 : 64KB (32KW)

SA58 : 64KB (32KW)

SA59 : 64KB (32KW)

SA60 : 64KB (32KW)

SA61 : 64KB (32KW)

SA62 : 64KB (32KW)

SA63 : 64KB (32KW)

SA64 : 64KB (32KW)

SA65 : 64KB (32KW)

SA66 : 64KB (32KW)

SA67 : 64KB (32KW)

SA68 : 64KB (32KW)

SA69 : 64KB (32KW)

SA70 : 64KB (32KW)

SA81 : 64KB (32KW)

258000h

020000h

028000h

030000h

038000h

040000h

048000h

050000h

058000h

060000h

068000h

070000h

078000h

080000h

088000h

090000h

098000h

0A0000h

0A8000h

0B0000h

0B8000h

0C0000h

0C8000h

0D0000h

0D8000h

0E0000h

0E8000h

0F0000h

0F8000h

100000h

108000h

110000h

118000h

120000h

128000h

130000h

138000h

140000h

148000h

150000h

158000h

160000h

168000h

170000h

178000h

180000h

188000h

190000h

198000h

1A0000h

1A8000h

1B0000h

1B8000h

1C0000h

1C8000h

1D0000h

1D8000h

1E0000h

1E8000h

1F0000h

1F8000h

1FFFFFh

SA82 : 64KB (32KW)

260000h

SA83 : 64KB (32KW)

268000h

SA84 : 64KB (32KW)

270000h

SA85 : 64KB (32KW)

278000h

SA86 : 64KB (32KW)

280000h

SA87 : 64KB (32KW)

288000h

SA88 : 64KB (32KW)

290000h

SA89 : 64KB (32KW)

298000h

SA90 : 64KB (32KW)

2A0000h

SA91 : 64KB (32KW)

2A8000h

SA92 : 64KB (32KW)

2B0000h

SA93 : 64KB (32KW)

2B8000h

SA94 : 64KB (32KW)

2C0000h

SA95 : 64KB (32KW)

2C8000h

SA96 : 64KB (32KW)

2D0000h

SA97 : 64KB (32KW)

2D8000h

SA98 : 64KB (32KW)

2E0000h

Bank C

SA99 : 64KB (32KW)

2E8000h

SA100 : 64KB (32KW)

2F0000h

SA101 : 64KB (32KW)

2F8000h

SA102 : 64KB (32KW)

300000h

SA103 : 64KB (32KW)

308000h

SA104 : 64KB (32KW)

310000h

SA105 : 64KB (32KW)

318000h

SA106 : 64KB (32KW)

320000h

SA107 : 64KB (32KW)

328000h

SA108 : 64KB (32KW)

330000h

SA109 : 64KB (32KW)

338000h

SA110 : 64KB (32KW)

340000h

SA111 : 64KB (32KW)

348000h

SA112 : 64KB (32KW)

350000h

SA113 : 64KB (32KW)

358000h

SA114 : 64KB (32KW)

360000h

SA115 : 64KB (32KW)

368000h

SA116 : 64KB (32KW)

370000h

Bank B

SA117 : 64KB (32KW)

378000h

SA118 : 64KB (32KW)

380000h

SA119 : 64KB (32KW)

388000h

SA120 : 64KB (32KW)

390000h

SA121 : 64KB (32KW)

398000h

SA122 : 64KB (32KW)

3A0000h

SA123 : 64KB (32KW)

3A8000h

SA124 : 64KB (32KW)

3B0000h

SA125 : 64KB (32KW)

3B8000h

SA126 : 64KB (32KW)

3C0000h

SA127 : 64KB (32KW)

3C8000h

Bank D

SA128 : 64KB (32KW)

3D0000h

SA129 : 64KB (32KW)

3D8000h

SA130 : 64KB (32KW)

3E0000h

SA131 : 64KB (32KW)

3E8000h

SA132 : 64KB (32KW)

3F0000h

SA133 : 64KB (32KW)

3F8000h

SA134 : 8KB (4KW)

3F9000h

SA135 : 8KB (4KW)

3FA000h

SA136 : 8KB (4KW)

3FB000h

SA137 : 8KB (4KW)

SA138 : 8KB (4KW)

SA139 : 8KB (4KW)

SA140 : 8KB (4KW)

3FC000h

3FD000h

3FE000h

3FF000h

3FFFFFh

SA141 : 8KB (4KW)

Sector Architecture

13

MB84VZ064G-70

FlexBank^TMArchitecture Table

Volume

Bank 1

Bank

Bank 2

Combination

Splits

Volume

Combination

1

2

3

4

8 Mbit

Bank A

56 Mbit

40 Mbit

56 Mbit

Remainder (Bank B, C, D)

Remainder (Bank A, C, D)

Remainder (Bank A, B, D)

Remainder (Bank A, B, C)

24 Mbit

8 Mbit

Bank B

Bank C

Bank D

Example of Virtual Banks Combination Table

Bank 1

Volume Combination

Bank 2

Volume Combination

Bank

Splits

Sector Size

Bank B

+

8 × 8 Kbyte/4 Kword

1

2

3

4

8 Mbit

16 Mbit

24 Mbit

32 Mbit

Bank A

+

56 Mbit

48 Mbit

Bank C

+

Bank D

+

15 × 64 Kbyte/32 Kword

111 × 64 Kbyte/32 Kword

Bank A

+

Bank D

16 × 8 Kbyte/4 Kword

Bank B

+

Bank C

+

96 × 64 Kbyte/32 Kword

30 × 64 Kbyte/32 Kword

Bank A

+

Bank C

+

16 × 8 Kbyte/4 Kword

Bank B

48 × 64 Kbyte/32 Kword 40 Mbit

+

78 × 64 Kbyte/32 Kword

Bank D

Bank A

+

8 × 8 Kbyte/4 Kword

Bank C

+

8 × 8 Kbyte/4 Kword

+

32 Mbit

+

Bank B

63 × 64 Kbyte/32 Kword

Bank D

63 × 64 Kbyte/32 Kword

Note : When multiple sector erase over several banks is operated, the system cannot read out of the bank to which

a sector being erased belongs. For example, suppose that erasing is taking place at both Bank A and Bank B,

neither Bank A nor Bank B is read out (they would output the sequence flag once they were selected.)

Meanwhile the system would get to read from either Bank C or Bank D.

Simultaneous Operation Table

Case

Bank 1 Status

Read mode

Bank 2 Status

Read mode

1

2

3

4

5

6

7

Read mode

Autoselect mode

Program mode

Erase mode *

Read mode

Autoselect mode

Program mode

Erase mode *

Read mode

* : By writing erase suspend command on the bank address of sector being erased, the erase operation gets

suspended so that it enables reading from or programming the remaining sectors.

Note: Bank 1 and Bank 2 are divided for the sake of convenience at Simultaneous Operation. Actually, the Bank

consists of 4 banks, Bank A, Bank B, Bank C and Bank D. Bank Address (BA) meant to specify each of the

Banks.

14

MB84VZ064G-70

Sector Address Table

Sector Address

Address Range

Word Mode

Bank

Sector

Bank Address

A²¹

0

A²⁰

0

A¹⁹

0

A¹⁸

0

1

A¹⁷

0

1

0

1

A¹⁶

0

1

0

1

0

1

0

1

A¹⁵

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁴

0

A¹³

0

A¹²

0

1

SA0

SA1

000000h to 000FFFh

001000h to 001FFFh

002000h to 002FFFh

003000h to 003FFFh

004000h to 004FFFh

005000h to 005FFFh

006000h to 006FFFh

007000h to 007FFFh

008000h to 00FFFFh

010000h to 017FFFh

018000h to 01FFFFh

020000h to 027FFFh

028000h to 02FFFFh

030000h to 037FFFh

038000h to 03FFFFh

040000h to 047FFFh

048000h to 04FFFFh

050000h to 057FFFh

058000h to 05FFFFh

060000h to 067FFFh

068000h to 06FFFFh

070000h to 077FFFh

078000h to 07FFFFh

SA2

0

1

0

SA3

0

1

SA4

1

0

SA5

1

0

1

SA6

1

0

SA7

1

SA8

X

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

Bank A

(Continued)

15

MB84VZ064G-70

Sector Address

Address Range

Word Mode

Bank

Sector

Bank Address

A²¹

0

A²⁰

0

1

A¹⁹

1

0

1

A¹⁸

0

1

0

1

0

1

A¹⁷

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁶

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁵

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁴

X

A¹³

X

A¹²

X

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

080000h to 087FFFh

088000h to 08FFFFh

090000h to 097FFFh

098000h to 09FFFFh

0A0000h to 0A7FFFh

0A8000h to 0AFFFFh

0B0000h to 0B7FFFh

0B8000h to 0BFFFFh

0C0000h to 0C7FFFh

0C8000h to 0CFFFFh

0D0000h to 0D7FFFh

0D8000h to 0DFFFFh

0E0000h to 0E7FFFh

0E8000h to 0EFFFFh

0F0000h to 0F7FFFh

0F8000h to 0FFFFFh

100000h to 107FFFh

108000h to 10FFFFh

110000h to 117FFFh

118000h to 11FFFFh

120000h to 127FFFh

128000h to 12FFFFh

130000h to 137FFFh

138000h to 13FFFFh

140000h to 147FFFh

148000h to 14FFFFh

150000h to 157FFFh

158000h to 15FFFFh

160000h to 167FFFh

168000h to 16FFFFh

170000h to 177FFFh

178000h to 17FFFFh

180000h to 187FFFh

188000h to 18FFFFh

190000h to 197FFFh

198000h to 19FFFFh

1A0000h to 1A7FFFh

1A8000h to 1AFFFFh

1B0000h to 1B7FFFh

1B8000h to 1BFFFFh

1C0000h to 1C7FFFh

1C8000h to 1CFFFFh

1D0000h to 1D7FFFh

1D8000h to 1DFFFFh

1E0000h to 1E7FFFh

1E8000h to 1EFFFFh

1F0000h to 1F7FFFh

1F8000h to 1FFFFFh

Bank B

(Continued)

16

MB84VZ064G-70

Sector Address

Address Range

Word Mode

Bank

Sector

Bank Address

A²¹

1

A²⁰

0

1

A¹⁹

0

1

0

A¹⁸

0

1

0

1

0

1

A¹⁷

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁶

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁵

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁴

X

A¹³

X

A¹²

X

SA71

SA72

SA73

SA74

SA75

SA76

SA77

SA78

SA79

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

SA95

SA96

SA97

SA98

SA99

SA100

SA101

SA102

SA103

SA104

SA105

SA106

SA107

SA108

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

SA117

SA118

200000h to 207FFFh

208000h to 20FFFFh

210000h to 217FFFh

218000h to 21FFFFh

220000h to 227FFFh

228000h to 22FFFFh

230000h to 237FFFh

238000h to 23FFFFh

240000h to 247FFFh

248000h to 24FFFFh

250000h to 257FFFh

258000h to 25FFFFh

260000h to 267FFFh

268000h to 26FFFFh

270000h to 277FFFh

278000h to 27FFFFh

280000h to 287FFFh

288000h to 28FFFFh

290000h to 297FFFh

298000h to 29FFFFh

2A0000h to 2A7FFFh

2A8000h to 2AFFFFh

2B0000h to 2B7FFFh

2B8000h to 2BFFFFh

2C0000h to 2C7FFFh

2C8000h to 2CFFFFh

2D0000h to 2D7FFFh

2D8000h to 2DFFFFh

2E0000h to 2E7FFFh

2E8000h to 2EFFFFh

2F0000h to 2F7FFFh

2F8000h to 2FFFFFh

300000h to 307FFFh

308000h to 30FFFFh

310000h to 317FFFh

318000h to 31FFFFh

320000h to 327FFFh

328000h to 32FFFFh

330000h to 337FFFh

338000h to 33FFFFh

340000h to 347FFFh

348000h to 34FFFFh

350000h to 357FFFh

358000h to 35FFFFh

360000h to 367FFFh

368000h to 36FFFFh

370000h to 377FFFh

378000h to 37FFFFh

Bank C

(Continued)

17

MB84VZ064G-70

(Continued)

Sector Address

Address Range

Word Mode

Bank

Sector

Bank Address

A²¹

1

A²⁰

1

A¹⁹

1

A¹⁸

0

1

A¹⁷

0

1

0

1

A¹⁶

0

1

0

1

0

1

0

1

A¹⁵

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁴

X

0

A¹³

X

0

A¹²

X

0

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

SA128

SA129

SA130

SA131

SA132

SA133

SA134

SA135

SA136

SA137

SA138

SA139

SA140

SA141

380000h to 387FFFh

388000h to 38FFFFh

390000h to 397FFFh

398000h to 39FFFFh

3A0000h to 3A7FFFh

3A8000h to 3AFFFFh

3B0000h to 3B7FFFh

3B8000h to 3BFFFFh

3C0000h to 3C7FFFh

3C8000h to 3CFFFFh

3D0000h to 3D7FFFh

3D8000h to 3DFFFFh

3E0000h to 3E7FFFh

3E8000h to 3EFFFFh

3F0000h to 3F7FFFh

3F8000h to 3F8FFFh

3F9000h to 3F9FFFh

3FA000h to 3FAFFFh

3FB000h to 3FBFFFh

3FC000h to 3FCFFFh

3FD000h to 3FDFFFh

3FE000h to 3FEFFFh

3FF000h to 3FFFFFh

Bank D

0

1

0

1

0

1

0

1

0

1

0

1

18

MB84VZ064G-70

Sector Group Addresses Table

Sector Group

SGA0

A²¹

0

A²⁰

0

A¹⁹

0

A¹⁸

0

A¹⁷

0

A¹⁶

0

1

X

0

1

A¹⁵

0

1

0

1

X

0

1

0

1

A¹⁴

0

1

A¹³

0

1

0

1

A¹²

0

1

0

1

0

1

0

1

Sectors

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SGA1

SGA2

SGA3

SGA4

SGA5

SGA6

SGA7

X

SGA8

0

SA8 to SA10

X

SGA9

SGA10

SGA11

SGA12

SGA13

SGA14

SGA15

SGA16

SGA17

SGA18

SGA19

SGA20

SGA21

SGA22

SGA23

SGA24

SGA25

SGA26

SGA27

SGA28

SGA29

SGA30

SGA31

SGA32

SGA33

SGA34

SGA35

SGA36

SGA37

SGA38

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

SA11 to SA14

SA15 to SA18

SA19 to SA22

SA23 to SA26

SA27 to SA30

SA31 to SA34

SA35 to SA38

SA39 to SA42

SA43 to SA46

SA47 to SA50

SA51 to SA54

SA55 to SA58

SA59 to SA62

SA63 to SA66

SA67 to SA70

SA71 to SA74

SA75 to SA78

SA79 to SA82

SA83 to SA86

SA87 to SA90

SA91 to SA94

SA95 to SA98

SA99 to SA102

SA103 to SA106

SA107 to SA110

SA111 to SA114

SA115 to SA118

SA119 to SA122

SA123 to SA126

SA127 to SA130

X

SGA39

1

SA131 to SA133

SGA40

SGA41

SGA42

SGA43

SGA44

SGA45

SGA46

SGA47

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

SA134

SA135

SA136

SA137

SA138

SA139

SA140

SA141

19

MB84VZ064G-70

Flash Memory Autoselect Codes Table

Type

A²¹to A¹²

BA

A⁶

L

A³

L

A²

L

A¹

L

A⁰

L

Code (HEX)

04h

Manufacture’s Code

Device Code

BA

L

H

L

227Eh

2202h

BA

L

H

Extended Device

Code *²

BA

L

H

2201h

Sector Group

Protection

Sector Group

Addresses

L

H

L

01h*¹

Legend: L = V^IL, H = VIH. See DC Characteristics for voltage levels.

*1 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.

*2 : A read cycle at address (BA) 01h outputs device code. When 227Eh was output, this indicates that there will

require two additional codes, called Extended Device Codes. Therefore the system may continue reading out

these Extended Device Codes at the address of (BA) 0Eh, as well as at (BA) 0Fh.

20

MB84VZ064G-70

Flash Memory Command Definitions Table

Fourth Bus

Read/Write

Cycle

First Bus

Second Bus

Third Bus

Fifth Bus

Sixth Bus

Bus

Write

Cycles

Req’d

Command

Sequence

Write Cycle Write Cycle

Write Cycle

Write Cycle Write Cycle

Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

Read/Reset

1

3

XXXh F0h

—

RD*⁹

—

555h AAh 2AAh 55h

555h

(BA*⁸)

555h

F0h RA*⁵

Autoselect

Program

3

4

1

90h

A0h

—

PA*⁶PD*¹⁰

555h

Program

Suspend

BA*⁸

B0h

—

Program

Resume

1

6

BA*⁸30h

—

Chip Erase

555h AAh 2AAh 55h

555h

80h 555h AAh 2AAh 55h 555h 10h

Sector

Erase

SA*⁷

80h 555h AAh 2AAh 55h

30h

—

Erase

Suspend

1

BA*⁸B0h

30h

—

Erase

Resume

BA*⁸

—

Extended

Sector

Group

Protection*²

4

XXXh 60h SPA*¹¹60h SPA*¹¹40h SPA*¹¹SD*¹²

—

Set to

Fast Mode

3

2

1

3

4

555h AAh 2AAh 55h

555h

—

20h

—

Fast

Program*¹

PA*⁶PD*¹⁰

XXXh A0h

4

Reset from

Fast Mode*¹

*

BA*⁸90h XXXh

(BA*⁸)

—

F0h

Query

98h

—

55h

HiddenROM

Entry

555h AAh 2AAh 55h

555h

88h

A0h

—

(HRA*¹³)

PA*⁶

HiddenROM

Program*³

PD*¹⁰

(HRBA*¹⁴)

555h

HiddenROM

Exit*³

90h XXXh 00h

(Continued)

21

MB84VZ064G-70

(Continued)

*1 : This command is valid during Fast Mode.

*2 : This command is valid while RESET = VID.

*3 : This command is valid during HiddenROM mode.

*4 : The data “00h” is also acceptable.

*5 : RA

*6 : PA

= Address of the memory location to be read

= Address of the memory location to be programmed Addresses are latched on the falling edge of the

write pulse.

*7 : SA

= Address of the sector to be erased. The combination of A21, A20, A19, A18, A17, A16, A15, A14, A13, and A12

will uniquely select any sector.

*8 : BA

*9 : RD

*10 : PD

= Bank Address (A21, A20, A19)

= Data read from location RA during read operation.

= Data to be programmed at location PA. Data is latched on the rising edge of write pulse.

*11 : SPA = Sector group address to be protected. Set sector group address and (A⁶, A3, A2, A1, A0) = (0, 0, 0, 1, 0).

*12 : SD

= Sector group protection verify data. Output 01h at protected sector group addresses and output 00h at

unprotected sector group addresses.

*13 : HRA = Address of the HiddenROM area: 000000h to 00007Fh

*14 : HRBA = Bank Address of the HiddenROM area (A²¹= A20 = A19 = VIL)

Notes : • Address bits A²¹to A11 = X = “H” or “L” for all address commands except or Program Address (PA),

Sector Address (SA), and Bank Address (BA), and Sector Group Address (SPA).

• Bus operations are defined in ■DEVICE BUS OPERATION.

• The system should generate the following address patterns: 555h or 2AAh to addresses A10 to A0

• Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.

• The command combinations not described in this table are illegal.

22

MB84VZ064G-70

2. AC Characteristics

• Read Only Operations Characteristics (Flash)

Symbol

Value (Note)

Parameter

Read Cycle Time

Condition

Unit

JEDEC

Standard

Min

Max

t^AVAV

tRC

—

70

—

ns

CEf = VIL

OE = VIL

Address to Output Delay

t^AVQV

tACC

—

70

Chip Enable to Output Delay

Output Enable to Output Delay

Chip Enable to Output High-Z

Output Enable to Output High-Z

tELQV

t^GLQV

t^EHQZ

tGHQZ

tCEf

tOE

tDF

OE = VIL

—

70

30

25

ns

—

Output Hold Time From Addresses,

CEf or OE, Whichever Occurs First

tAXQX

tOH

—

0

—

ns

µs

RESET Pin Low to Read Mode

—

tREADY

—

20

Note: Test Conditions– Output Load:1 TTL gate and 30 pF

Input rise and fall times: 5 ns

Input pulse levels: 0.0 V to V^CCf

Timing measurement reference level

Input: 0.5 × VCCf

Output: 0.5 × VCCf

23

MB84VZ064G-70

• Read Operation Timing Diagram (Flash)

tRC

Address

Address Stable

tACC

CEf

tOE

tDF

OE

tOEH

WE

tOH

tCE

High-Z

Outputs Valid

Outputs

• Hardware Reset/Read Operation Timing Diagram (Flash)

tRC

Address

Address Stable

tACC

CEf

tRH

tRP

tRH

tCE

RESET

Outputs

tOH

High-Z

Outputs Valid

24

MB84VZ064G-70

• Write/Erase/Program Operations (Flash)

Symbol

Standard

Value

Unit

Parameter

JEDEC

t^AVAV

Min

70

0

Typ

Max

Write Cycle Time

tWC

tAS

ns

Address Setup Time

tAVWL

Address Setup Time to OE Low During Toggle Bit

Polling

tASO

tAH

12

30

0

ns

Address Hold Time

t^WLAX

Address Hold Time from CEf or OE High During

Toggle Bit Polling

tAHT

Data Setup Time

Data Hold Time

t^DVWH

t^WHDX

tDS

tDH

25

0

ns

Output

Read

0

Enable Hold

Time

t^OEH

Toggle and Data Polling

10

ns

CEf High During Toggle Bit Polling

OE High During Toggle Bit Polling

Read Recover Time Before Write

CEf Setup Time

tCEPH

tOEPH

tGHWL

tGHEL

tCS

20

0

ns

µs

s

t^GHWL

tGHEL

0

tELWL

0

WE Setup Time

tWLEL

tWS

0

CEf Hold Time

tWHEH

tEHWH

tWLWH

tELEH

tCH

0

WE Hold Time

tWH

0

Write Pulse Width

tWP

35

20

CEf Pulse Width

tCP

Write Pulse Width High

CEf Pulse Width High

Programming Operation

Sector Erase Operation *¹

V^CCf Setup Time

t^WHWL

tEHEL

tWPH

tCPH

tWHWH1

tWHWH2

tWHWH1

tWHWH2

tVCS

6

0.5

50

500

4

µs

ns

µs

Rise Time to VID *²

tVIDR

tVACCR

tVLHT

tWPP

Rise Time to VACC *³

Voltage Transition Time *²

Write Pulse Width *²

100

(Continued)

25

MB84VZ064G-70

(Continued)

Symbol

JEDEC Standard

Value

Typ

Parameter

Unit

Min

4

Max

OE Setup Time to WE Active *²

CEf Setup Time to WE Active *²

Recover Time from RY/BY

tOESP

tCSP

tRB

µs

ns

µs

4

0

RESET Pulse Width

tRP

500

200

RESET High Level Period Before Read

Program/Erase Valid to RY/BY Delay

Delay Time from Embedded Output Enable

Erase Time-out Time

tRH

tBUSY

t^EOE

t^TOW

tSPD

90

70

50

Erase Suspend Transition Time

20

*1: This does not include preprogramming time.

*2: This timing is for Sector Group Protection operation.

*3: This timing is for Accelerated Program operation.

26

MB84VZ064G-70

• Write Cycle (WE control) (Flash)

3rd Bus Cycle

Data Polling

PA

555h

PA

Address

tWC

tRC

tAS

tAH

CEf

tCS

tCH

tCE

OE

tOE

tWP

tWPH

tWHWH1

tGHWL

WE

tOH

tDF

tDH

tDS

A0h

PD

DOUT

DQ7

Data

Notes : • PA is address of the memory location to be programmed.

• PD is data to be programmed at word address.

• DQ7 is the output of the complement of the data written to the device.

• DOUT is the output of the data written to the device.

• Figure indicates last two bus cycles out of four bus cycle sequence.

27

MB84VZ064G-70

• Write Cycle (CEf control) (Flash)

3rd Bus Cycle

Data Polling

PA

555h

tWC

PA

Address

WE

tAS

tAH

tWS

tWH

OE

tCPH

tCP

tWHWH1

tGHEL

CEf

tDS

tDH

A0h

PD

DOUT

DQ7

Data

Notes : • PA is address of the memory location to be programmed.

• PD is data to be programmed at word address.

• DQ7 is the output of the complement of the data written to the device.

• DOUT is the output of the data written to the device.

• Figure indicates last two bus cycles out of four bus cycle sequence.

28

MB84VZ064G-70

• AC Waveforms Chip/Sector Erase Operations (Flash)

555h

tWC

2AAh

555h

2AAh

SA*

Address

CEf

tAS

tAH

tCS

tCH

OE

tWP

tWPH

tGHWL

WE

tDS

tDH

30h for Sector Erase

10h

AAh

55h

80h

AAh

55h

Data

VCCf

tVCS

* : SA is the sector address for Sector Erase. Addresses = 555h (Word) for Chip Erase.

29

MB84VZ064G-70

• AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash)

CEf

tCH

tDF

tOE

OE

tOEH

WE

tCE

*

High-Z

DQ7 =

Data

DQ7

Valid Data

tWHWH1 or 2

DQ6 to DQ0 =

Output Flag

DQ6 to DQ0

Valid Data

DQ6 to DQ0

RY/BY

tEOE

tBUSY

* : DQ7 = Valid Data (the device has completed the Embedded operation) .

30

MB84VZ064G-70

• AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash)

Address

CEf

tAHT tASO

tAHT tAS

tCEPH

WE

tOEPH

tOEH

OE

tOE

tCE

tDH

*

Stop

Output

Valid

Toggle

Data

Toggle

Data

Toggle

Data

DQ 6/DQ2

Data

Toggling

tBUSY

RY/BY

* : DQ6 stops toggling (the device has completed the Embedded operation).

31

MB84VZ064G-70

• Bank-to-bank Read/Write Timing Diagram (Flash)

Read

Command

Read

Command

Read

tRC

tWC

tRC

tWC

tRC

BA2

(PA)

BA2

(PA)

Address

CEf

BA1

(555h)

tACC

tCE

tAS

tAH

tAHT

tOE

tCEPH

OE

WE

DQ

tDF

tGHWL

tOEH

tWP

tDS

tDH

tDF

Valid

Output

Valid

Output

Valid

Output

Status

Intput

(A0h)

(PD)

Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.

BA1 : Address corresponding to Bank 1

BA2 : Address corresponding to Bank 2

32

MB84VZ064G-70

• RY/BY Timing Diagram during Write/Erase Operations (Flash)

CEf

Rising edge of the last WE signal

WE

Entire programming

or erase operations

RY/BY

tBUSY

• RESET, RY/BY Timing Diagram (Flash)

WE

RESET

tRP

tRB

RY/BY

tREADY

33

MB84VZ064G-70

• Temporary Sector Unprotection (Flash)

VCCf

tVIDR

tVCS

tVLHT

VID

VIH

RESET

CEf

WE

tVLHT

Program or Erase Command Sequence

Unprotection period

RY/BY

• Acceleration Mode Timing Diagram (Flash)

VCCf

tVACCR

tVCS

tVLHT

VACC

VIH

WP/ACC

CEf

WE

tVLHT

Program Command Sequence

Acceleration period

RY/BY

34

MB84VZ064G-70

• Extended Sector Group Protection (Flash)

VCCf

tVCS

tVLHT

RESET

tWC

tVIDR

Address

SPAX

SPAY

A6, A3,

A2, A0

A1

CEf

OE

TIME-OUT

tWP

WE

60h

40h

01h

60h

Data

tOE

SPAX : Sector Group Address to be protected

SPAY : Next Sector Group Address to be protected

TIME-OUT : Time-Out window = 250 µs (Min)

35

MB84VZ064G-70

3. Erase and Programming Performance (Flash)

Value

Parameter

Unit

Remarks

Min

—

Typ

0.5

6

Max

2.0

Sector Erase Time

s

Excludes programming time prior to erasure

Word Programming Time

Chip Programming Time

Erase/Program Cycle

—

100

200

—

µs Excludes system-level overhead

—

s

Excludes system-level overhead

100,000

—

cycle

Typical Erase conditions TA = +25°C, VCCf_1 & VCCf_2 = 2.9 V

Typical Program conditions TA = +25°C, VCCf_1 & VCCf_2 = 2.9 V

Data= Checker

36

MB84VZ064G-70

■ 64M FCRAM CHARACTERISTICS for MCP

1. FCRAM Power Down Program Key Table

Basic Key Table

Definition

A¹⁶

A¹⁷

A¹⁹

A²⁰

A²¹

KEY

Mode Select

Area Select

A¹⁹

A²⁰

L

A²¹

AREA

L

X

H

BOTTOM *²

RESERVED

TOP *³

H

L

H

A¹⁶

A¹⁷

MODE

NAP *⁴

L

H

L

RESERVED

16 M Partial

SLEEP *^4,*⁵

H

Available Key Table

A¹⁶

A¹⁷

A¹⁹

A²⁰

A²¹

Data Retention

MODE

NAP

Area

Mode Select

Area Select

L

H

L

X

L

X

L

X

L

None

Bottom 16 M only

Top 16 M only

None

16M Partial

SLEEP

L

H

X

H

X

H

X

H

*1 : The Power Down Program can be performed one time after compliance of Power-up timings and

it should not be re-programmed after regular Read or Write.

Unspecified addresses, A¹⁵to A0, can be either High or Low during the programming.

The RESERVED key should not be used.

*2 : BOTTOM area is from the lowest address location. (i.e., A²⁰to A0 = L)

*3 : TOP area is from the highest address location. (i.e., A20 to A0 = H)

*4 : NAP and SLEEP do not retain the data and Area Select is ignored.

*5 : Default state. Power Down Program to this SLEEP mode can be omitted.

37

MB84VZ064G-70

2. AC Characteristics

• READ Operation (FCRAM)

Value

Parameter

Symbol

Unit

Remarks

Min

Max

Read Cycle Time

t^RC

tCE

70

—

5

—

65

40

65

—

ns

Chip Enable Access Time

Output Enable Access Time

Address Access Time

*1,*3

*1

t^OE

t^AA

*1,*4

*1

Output Data Hold Time

tOH

CE1r Low to Output Low-Z

OE Low to Output Low-Z

CE1r High to Output High-Z

OE High to Output High-Z

Address Setup Time to CE1r Low

tCLZ

5

—

*2

tOLZ

0

—

*2

tCHZ

—

–5

25

10

–5

10

—

70

45

–5

25

45

12

25

12

20

—

*2

tOHZ

tASC

*2

*5

tASO

t^ASO(ABS)

tBSC

—

*3,*6

*7

Address Setup Time to OE

—

LB / UB Setup Time to CE1r Low

LB / UB Setup Time to OE Low

Address Invalid Time

—

*5

tBSO

t^AX

—

5

*4,*8

*4

Address Hold Time from CE1r Low

Address Hold Time from OE Low

Address Hold Time from CE1r High

Address Hold Time from OE High

LB / UB Hold Time from CE1r High

LB / UB Hold Time from OE High

CE1r Low to OE Low Delay Time

OE Low to CE1r High Delay Time

CE1r High Pulse Width

tCLAH

tOLAH

tCHAH

tOHAH

tCHBH

tOHBH

tCLOL

tOLCH

tCP

—

*4,*9

—

1000

—

*3,*6,*9,*10

*9

—

t^OP

1000

—

*6,*9,*10

*7

OE High Pulse Width

t^OP(ABS)

(Continued)

38

MB84VZ064G-70

(Continued)

*1 : The output load is 30 pF.

*2 : The output load is 5 pF.

*3 : The t^CEis applicable if OE is brought to Low before CE1r goes Low and is also applicable if actual value of

both or either tASO or tCLOL is shorter than specified value.

*4 : Applicable only to A¹and A0 when both CE1r and OE are kept at Low for the address access.

*5 : Applicable if OE is brought to Low before CE1r goes Low.

*6 : The t^ASO, tCLOL(Min) and tOP(Min) are reference values when the access time is determined by tOE.

If actual value of each parameter is shorter than specified minimum value, tOE become longer by the amount

of subtracting actual value from specified minimum value.

For example, if actual tASO, tASO(actual), is shorter than specified minimum value, tASO(Min), during OE control

access (i.e., CE1r stays Low), the tOE become tOE(Max) + tASO(Min) – tASO(actual).

*7 : The tASO(ABS) and tOP(ABS) is the absolute minimum value during OE control access.

*8 : The t^AXis applicable when both A1 and A0 are switched from previous state.

*9 : If actual value of either tCLOL or tOP is shorter than specified minimum value, both tOLAH and tOLCH become

tRC(Min) – tCLOL(actual) or tRC(Min) – tOP(actual).

*10 : Maximum value is applicable if CE1r is kept at Low.

39

MB84VZ064G-70

• WRITE Operation (FCRAM)

Parameter

Value

Symbol

Unit Remarks

Min

Max

Write Cycle Time

t^WC

t^AS

70

0

—

ns

*1

*2

Address Setup Time

Address Hold Time

CE1r Write Setup Time

CE1r Write Hold Time

WE Setup Time

t^AH

35

0

—

tCS

1000

—

tCH

0

tWS

0

WE Hold Time

tWH

0

—

LB and UB Setup Time

LB and UB Hold Time

OE Setup Time

tBS

–5

0

—

tBH

—

tOES

t^OEH

t^OEH(ABS)

tOHCL

tOHAH

tCW

1000

—

*3

*3, *4

*5

25

12

–5

45

10

15

0

OE Hold Time

OE High to CE1r Low Setup Time

OE High to Address Hold Time

CE1r Write Pulse Width

WE Write Pulse Width

CE1r Write Recovery Time

WE Write Recovery Time

Data Setup Time

—

*6

—

*7

—

*1, *8

*1, *9

*1, *3, *9

tWP

—

tWRC

tWR

—

1000

—

t^DS

Data Hold Time

t^DH

—

CE1r High Pulse Width

tCP

12

—

*9

*1 : Minimum value must be equal or greater then the sum of actual t^CW(or tWP) and tWRC (or tWR).

*2 : New write address is valid from either CE1r or WE is bought to High.

*3 : The tOEH is specified from end of tWC(Min). The tOEH(Min) is a reference value when the access time is determined

by tOE.

If actual value, tOEH(actual) is shorter than specified minimum value, tOE become longer by the amount of

subtracting actual value from specified minimum value.

*4 : The tOEH(Max) is applicable if CE1r is kept at Low and both WE and OE are kept at High.

*5 : The tOEH(ABS) is the absolute minimum value if write cycle is terminated by WE and CE1r stays Low.

*6 : tOHCL(Min) must be satisfied if read operation is not performed prior to write operation.

In case OE is disabled after tOHCL(Min), WE Low must be asserted after tRC(Min) from CE1r Low.

In other words, read operation is initiated if tOHCL (Min) is not satisfied.

*7 : Applicable if CE1r stays Low after read operation.

*8 : tCW and tWP is applicable if write operation is initiated by CE1r and WE, respectively.

*9 : t^WRCand tWR is applicable if write operation is terminated by CE1r and WE, respectively.

The tWR(Min) can be ignored if CE1r is brought to High together or after WE is brought to High.

In such case, the tCP(Min) must be satisfied.

40

MB84VZ064G-70

• Power Down and Power Down Program Parameters (FCRAM)

Value

Remarks

Parameter

Symbol

Unit

Min

10

Max

—

CE2r Low Setup Time for Power Down Entry

CE2r Low Hold Time after Power Down Entry

t^CSP

ns

t^C2LP

70

—

CE1r High Hold Time following CE2r High after

Power Down Exit (SLEEP mode only)

tCHH

tCHHN

tCHS

350

1

—

µs

ns

CE1r High Setup Time following CE2r High after

Power Down Exit (Except for SLEEP mode)

CE1r High Setup Time following CE2r High after

Power Down Exit

10

CE1r High to PE Low Setup Time

PE Power Down Program Pulse Width

PE High to CE1r Low Hold Time

Address Setup Time to PE High

Address Setup Time from PE High

tEPS

tEP

70

15

0

—

ns

*

tEPH

tEAS

tEAH

* : Applicable to Down Program.

• Other Timing Parameters (FCRAM)

Parameter

Value

Symbol

Unit

Remarks

Min

Max

CE1r High to OE Invalid Time for Standby Entry

CE1r High to WE Invalid Time for Standby Entry

tCHOX

tCHWX

10

—

ns

10

—

*1

CE2r Low Hold Time after Power-up

CE2r High Hold Time after Power-up

t^C2LH

t^C2HL

50

—

µs

*2

*3

CE1r High Hold Time following CE2r High after

Power-up

tCHH

350

1

—

µs

*2

*4

Input Transition Time

t^T

25

ns

*1: It may write some data into any address location if t^CHWXis not satisfied.

*2: Must satisfy t^CHH(Min) after tC2LH(Min).

*3: Requires Power Down mode entry and exit after tC2HL.

*4: The input Transition Time (tT) at AC testing is 5 ns as shown in below. If actual tT is longer than 5 ns, it may

violate AC specification of some timing parameters.

• AC Test Conditions (FCRAM)

Remarks

Symbol

VIH

Description

Input High Level

Test Setup

Value

2.3

0.4

1.3

5

Unit

V

VCCr = 2.7 V to 3.1 V

Between VIL and VIH

V^IL

Input Low Level

V

V^REF

tT

Input Timing Measurement Level

Input Transition Time

V

ns

41

MB84VZ064G-70

• READ Timing #1 (OE Control Access) (FCRAM)

tRC

Address

Address Valid

tOHAH

tCE

tASO

tOHAH

CE1r

tOLCH

tOP

tOE

tCLOL

tOE

OE

tASO

tBSO

tOHBH

tBSO

tOHBH

LB / UB

tOHZ

tOLZ

tOH

tOLZ

tOH

DQ

(Output)

Valid Data Output

Note : CE2r, PE and WE must be High for entire read cycle.

Either or both LB and UB must be Low when both CE1r and OE are Low.

42

MB84VZ064G-70

• READ Timing #2 (CE1r Control Access) (FCRAM)

tRC

Address

CE1r

Address Valid

tCHAH

tASC

tCE

tCHAH

tASC

tCE

tCP

OE

tBSC

tCHBH

tBSC

tCHBH

LB / UB

tCHZ

tOH

tCHZ

tOH

tCLZ

DQ

(Output)

Valid Data Output

Note : CE2r, PE and WE must be High for entire read cycle.

Either or both LB and UB must be Low when both CE1r and OE are Low.

43

MB84VZ064G-70

• READ Timing #3 (Address Access after OE Control Access) (FCRAM)

tRC

Address

(A²¹to A3)

Address Valid

Address Valid (No change)

Address

(A²to A0)

Address Valid

tOHAH

tASO

tOLAH

tAA

tAX

CE1r

tOE

tOHZ

OE

tBSO

tOHBH

LB / UB

tOLZ

tOH

DQ

(Output)

Valid Data Output

Note : CE2r, PE and WE must be High for entire read cycle.

Either or both LB and UB must be Low when both CE1r and OE are Low.

44

MB84VZ064G-70

• READ Timing #4 (Address Access after CE1r Control Access) (FCRAM)

tRC

Address

(A²¹to A3)

Address Valid

Address Valid (No change)

Address

(A²to A0)

Address Valid

tCHAH

tASC

tCLAH

tAA

tAX

CE1r

tCE

tCHZ

OE

tBSC

tCHBH

LB / UB

tOH

tCLZ

DQ

(Output)

Valid Data Output

Note : CE2r, PE and WE must be High for entire read cycle.

Either or both LB and UB must be Low when both CE1r and OE are Low.

45

MB84VZ064G-70

• WRITE Timing #1 (CE1r Control) (FCRAM)

tWC

Address

CE1r

Address Valid

tAS

tAH

tAS

tCW

tWRC

tWS

tBS

tWH

tBH

tWS

WE

tBS

UB, LB

tOHCL

OE

tDS

tDH

DQ

(Input)

Valid Data Input

Note : CE2r and PE must be High for write cycle.

46

MB84VZ064G-70

• WRITE Timing #2-1 (WE Control, Single Write Operation) (FCRAM)

tWC

Address

CE1r

WE

Address Valid

tOHAH

tAS

tAH

tAS

tCH

tCP

tOHCL

tCS

tWP

tWR

tOHBH

tBS

tBH

UB, LB

OE

tOES

tOHZ

tDS

tDH

DQ

(Input)

Valid Data Input

Note : CE2r and PE must be High for write cycle.

47

MB84VZ064G-70

• WRITE Timing #2-2 (WE Control, Continuous Write Operation) (FCRAM)

tWC

Address

CE1r

WE

Address Valid

tOHAH

tAS

tAH

tAS

tOHCL

tCS

tWP

tWR

tBH

tBS

tBH

tBS

UB, LB

OE

tOES

tOHZ

tDS

tDH

DQ

(Input)

Valid Data Input

Note : CE2r and PE must be High for write cycle.

48

MB84VZ064G-70

• READ / WRITE Timing #1-1 (CE1r Control) (FCRAM)

tWC

Address

CE1r

Write Address

Read Address

tCHAH

tAS

tAH

tASC

tCP

tWRC

tCW

tWS

tCLOL

tBSO

tWH

tBH

tWH

t^WS

WE

tCHBH

tBS

UB, LB

OE

tOHCL

tCHZ

tDH

tOH

tDS

tOLZ

DQ

Read Data Output

Write Data Input

Note : Write address is valid from either CE1r or WE of last falling edge.

49

MB84VZ064G-70

• READ / WRITE Timing #1-2 (CE1r Control) (FCRAM)

tRC

Address

CE1r

Read Address

Write Address

tASC

tCHAH

tAS

tWRC

tWRC(Min)

tWH

tCP

tWS

tCE

tWH

tWS

WE

UB, LB

OE

tBH

tBSC

tCHBH

tBS

tOEH

tOHCL

tCHZ

tDH

tCLZ

tOH

DQ

Write Data Input

Read Data Output

Note : The t^OEHis specified from the time satisfied both tWRC and tWR(Min).

50

MB84VZ064G-70

• READ(OE Control) / WRITE(WE Control) Timing #2-1 (FCRAM)

tWC

Address

Read Address

Write Address

tOHAH

tAS

tAH

tASO

CE1r

WE

Low

tWP

tWR

tOEH

tBSO

tOHBH

tBS

tBH

UB, LB

OE

tOES

tOHZ

tOLZ

tOH

tDS

tDH

DQ

Read Data Output

Write Data Input

Note : CE1r can be tied to Low for WE and OE controlled operation.

When CE1r is tied to Low, output is exclusively controlled by OE.

51

MB84VZ064G-70

• READ(OE Control) / WRITE(WE Control) Timing #2-2

tRC

Address

CE1r

Read Address Valid

Write Address

tOHAH

tAS

tASO

tOEH

tBSO

Low

tWR

WE

tOHBH

tBH

tBS

UB, LB

OE

tOES

tOE

tOHZ

tOH

tDH

tOLZ

DQ

Write Data Input

Read Data Output

Note : CE1r can be tied to Low for WE and OE controlled operation.

When CE1r is tied to Low, output is exclusively controlled by OE.

• Power Down Program Timing (FCRAM)

CE1r

tEPS

tEP

tEPH

PE

tEAS

tEAH

Address

(A²¹to A16)

KEY

Note: CE2r must be High for Power Down Programming.

Any other inputs not specified above can be either High or Low.

52

MB84VZ064G-70

• Power Down Entry and Exit Timing (FCRAM)

CE1r

tCHS

CE2r

tCSP

tC2LP

tCHH (tCHHN)

High-Z

DQ

Power Down Entry

Power Down Mode

Power Down Exit

Note: This Power Down mode can be also used for Power-up #2 below except that t^CHHNcan not be used at Power-

up timing.

• Power-up Timing #1 (FCRAM)

CE1r

tCHS

tC2LH

tCHH

CE2r

VCCr

VCCr Min

0V

Note: The tC2LH specifies after VCCr reaches specified minimum level.

• Power-up Timing #2 (FCRAM)

CE1r

tCHS

tCSP

tC2HL

tC2LP

tCHH

CE2r

tC2HL

VCCr

VCCr Min

0V

Note: The t^C2HLspecifies from CE2r Low to High transition after VCCr reaches specified minimum level.

CE1r must be brought to High prior to or together with CE2r Low to High transition.

53

MB84VZ064G-70

• Standby Entry Timing after Read or Write (FCRAM)

CE1r

tCHOX

tCHWX

OE

WE

Active (Read)

Standby

Active (Write)

Standby

Note : Both t^CHOXand tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it

takes tRC (Min) period from either last address transition of A1 and A0, or CE1r Low to High transition.

54

MB84VZ064G-70

3. Data Retention Low VCCr Characteristics (FCRAM)

Value

Unit

Parameter

Symbol

VDR

Test Conditions

Min

Max

V^CCr Data Retention Supply

Voltage

CE1r = CE2r ≥ VCCr – 0.2 V or

CE1r = CE2r = VIH

2.3

3.1

V

2.3 V ≤ VCCr ≤ 2.7 V,

I^DR

VIN = VIH* or VIL,

—

1.5

mA

CE1r = CE2r = VIH*, IOUT=0 mA

V^CCr Data Retention Supply

Current

2.3 V ≤ VCCr ≤ 2.7 V,

I^DR1

VIN ≤ 0.2 V or VIN ≥ VCCr – 0.2 V,

CE1r = CE2r ≥ VCCr – 0.2 V, IOUT =0 mA

—

0

150

—

µA

2.7 V ≤ VCCr ≤ 3.1 V

at data retention entry

Data Retention Setup Time

t^DRS

ns

2.7 V ≤ VCCr ≤ 3.1 V

after data retention

Data Retention Recovery Time

t^DRR

200

0.2

—

ns

V^CCr Voltage Transition Time

* : 2.0 V ≤ VIH ≤ VCCr + 0.3 V

• Data Retention Timing

∆V/∆t

V/µs

tDRS

tDRR

3.1 V

VCCr

2.7 V

∆V/∆t

CE2r

2.3 V

CE2r and CE1r

>VCCr - 0.2 V or VIH* Min

CE1r

0.4 V

VSS

Data Retention Mode

Data bus must be in High-Z at data retention entry.

* : 2.0 V ≤ VIH ≤ VCCr + 0.3 V

55

MB84VZ064G-70

■ 8M SRAM CHARACTERISTICS for MCP

1. AC Characteristics

• Read Cycle (SRAM)

Value

Parameter

Symbol

Unit

Min

70

—

5

Max

—

Read Cycle Time

t^RC

t^AA

ns

Address Access Time

70

35

70

—

Chip Enable (CE1s) Access Time

Chip Enable (CE2s) Access Time

Output Enable Access Time

tCO1

tCO2

t^OE

LB, UB to Output Valid

tBA

Chip Enable (CE1s Low and CE2s High) to Output Active

Output Enable Low to Output Active

LB, UB Enable Low to Output Active

Chip Enable (CE1s High or CE2s Low) to Output High-Z

Output Enable High to Output High-Z

LB, UB Output Enable to Output High-Z

Output Data Hold Time

tCOE

tOEE

tBE

0

—

0

—

tOD

—

10

25

—

tODO

tBD

t^OH

Note: Test Conditions–Output Load:1 TTL gate and 30 pF

Input rise and fall times: 5 ns

Input pulse levels: 0.0 V to 3.0 V

Timing measurement reference level

Input: 0.5 × V^CCs

Output: 0.5 × VCCs

56

MB84VZ064G-70

• Read Cycle (SRAM)

t^RC

Address

CE1s

t^AA

t^OH

t^CO1

t^COE

t^OD

t^CO2

CE2s

t^OD

t^OE

OE

t^ODO

t^OEE

LB, UB

t^BA

t^BD

t^BE

t^COE

DQ

Valid Data Output

Note: WE remains HIGH for the read cycle.

57

MB84VZ064G-70

• Write Cycle (SRAM)

Parameter

Value

Symbol

Unit

Min

70

50

55

0

Max

—

25

—

Write Cycle Time

t^WC

tWP

t^CW

t^AW

tBW

t^AS

ns

Write Pulse Width

Chip Enable to End of Write

Address valid to End of Write

LB, UB to End of Write

Address Setup Time

Write Recovery Time

WE Low to Output High-Z

WE High to Output Active

Data Setup Time

t^WR

tODW

tOEW

tDS

0

—

0

30

0

Data Hold Time

t^DH

58

MB84VZ064G-70

• Write Cycle*¹(WE control) (SRAM)

t^WC

Address

t^AS

t^WP

t^WR

WE

CE1s

CE2s

t^AW

t^CW

t^BW

LB, UB

t^OEW

t^ODW

D^OUT

*2

*4

*3

*4

t^DS

t^DH

D^IN

Valid Data Input

*1 : If OE is HIGH during the write cycle, the outputs will remain at high impedance.

*2 : If CE1s goes LOW (or CE2s goes HIGH) coincident with or after WE goes LOW, the output

will remain at high impedance.

*3 : If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the output

will remain at high impedance.

*4 : Because I/O signals may be in the output state at this Time, input signals of reverse polarity

must not be applied.

59

MB84VZ064G-70

• Write Cycle *¹(CE1s control) (SRAM)

t^WC

Address

t^AS

t^WP

t^WR

WE

t^AW

t^CW

CE1s

CE2s

t^CW

t^BW

LB, UB

t^BE

t^COE

t^ODW

D^OUT

t^DS

t^DH

D^IN

*2

Valid Data Input

*1 : If OE is HIGH during the write cycle, the outputs will remain at high impedance.

*2 : Because I/O signals may be in the output state at this Time, input signals of reverse polarity

must not be applied.

60

MB84VZ064G-70

• Write Cycle *¹(CE2s Control) (SRAM)

t^WC

Address

t^AS

t^WP

t^WR

WE

t^CW

CE1s

CE2s

t^AW

t^CW

t^BW

LB, UB

t^BE

t^COE

t^ODW

D^OUT

t^DS

t^DH

D^IN

*2

Valid Data Input

*2

*1 : If OE is HIGH during the write cycle, the outputs will remain at high impedance.

*2 : Because I/O signals may be in the output state at this Time, input signals of reverse polarity

must not be applied.

61

MB84VZ064G-70

• Write Cycle *¹(LB, UB Control) (SRAM)

t^WC

Address

WE

t^WP

t^WR

t^CW

CE1s

CE2s

t^CW

t^AW

t^BW

t^AS

LB, UB

t^BE

t^COE

t^ODW

D^OUT

t^DS

t^DH

*2

Valid Data Input

*2

D^IN

*1 : If OE is HIGH during the write cycle, the outputs will remain at high impedance.

*2 : Because I/O signals may be in the output state at this Time, input signals of reverse polarity must

not be applied.

62

MB84VZ064G-70

2. Data Retention Characteristics (SRAM)

Parameter

Value

Unit

Symbol

Min

1.5

—

Typ

Max

3.1

15

Data Retention Supply Voltage

V^DH

IDDS2

tCDR

t^R

—

V

Standby Current

V^DH= 3.0 V

—

µA

ns

Chip Deselect to Data Retention Mode Time

Recovery Time

0

—

tRC

—

Note : t^RC: Read cycle time

• CE1s Controlled Data Retention Mode*¹

VCCs

Data Retention Mode

2.7 V

*2

V^IH

VDH

V^CCS– 0.2 V

t^CDR

t^R

CE1s

VSS

*1 : In CE1s controlled data retention mode, input level of CE2s should be fixed Vccs to VCCs–0.2 V or VSS to 0.2 V

during data retention mode. Other input and input/output pins can be used between –0.3 V to VCCs+0.3 V.

*2 : When CE1s is operating at the VIH Min. level, the standby current is given by ISB1s during the transition of VCCs

from Vccs Max to V^IHMin level.

63

MB84VZ064G-70

• CE2s Controlled Data Retention Mode*

V^CCs

2.7 V

V^DH

Data Retention Mode

V^IH

t^CDR

t^R

CE2s

V^IL

0.2 V

V^SS

* : In CE2s controlled data retention mode, input and input/output pins can be used between – 0.3 V to Vccs + 0.3 V.

64

MB84VZ064G-70

■ PIN CAPACITANCE

Value

Typ

Parameter

Symbol

Condition

Unit

Min

Max

30

Input Capacitance

C^IN

COUT

C^IN2

VIN = 0

VOUT = 0

VIN = 0

pF

Output Capacitance

Control Pin Capacitance

35

Note: Test conditions TA = +25°C, f = 1.0 MHz

■ HANDLING OF PACKAGE

Please handle this package carefully since the sides of package create acute angles.

■ CAUTION

• The high voltage (VID) cannot apply to address pins and control pins except RESET_1 or RESET_2. Exception

is when autoselect and sector group protect function are used, then the high voltage (VID) can be applied to

RESET_1 or RESET_2.

• Without the high voltage (V^ID) , sector group protection can be achieved by using “Extended Sector Group

Protection” command.

65

MB84VZ064G-70

■ ORDERING INFORMATION

MB84VZ064G

-70

PBS

PACKAGE TYPE

PBS = 107-ball BGA

SPEED OPTION

DEVICE NUMBER/DESCRIPTON

64Mega-bit (4M x 16bit) Dual Operation Flash Memory

3.0 V-only Read, Program, and Erase

64Mega-bit (2M x 16bit) FCRAM

8Mega-bit (256K x 16bit) SRAM

66

MB84VZ064G-70

■ PACKAGE DIMENSION

107-ball plastic FBGA

(BGA-107P-M01)

10.00±0.10(.394±.004)

0.20(.008)

S

B

1.25 –⁺0⁰.^.1¹0⁵

B

(SEATED HIGHT)

(STAND OFF)

.049 –⁺.^.0⁰0⁰4⁶

0.40(.016)

REF

0.80(.031)

REF

0.10±0.05

(.004±.002)

10

9

8

7

6

5

4

3

2

1

0.80(.031)

REF

A

9.00±0.10

(.354±.004)

0.40(.016)

REF

0.08(.003)

S

M

L K J H G F E D C B A

INDEX-MARK AREA

S

107-ø0.40 –⁺0⁰.^.0¹5⁰

107-ø.016 –⁺.^.0⁰0⁰2⁴

0.20(.008)

S A

M

0.08(.003)

S

A

B

0.08(.003)

S

C

2002 FUJITSU LIMITED B107001S-c-1-1

Dimensions in mm (inches)

67

MB84VZ064G-70

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

F0302

FUJITSU LIMITED Printed in Japan


型号：	MB84VZ064G-70PBS
厂家：	FUJITSU
描述：	Memory Circuit, Flash+SRAM, 4MX16, CMOS, PBGA107, PLASTIC, FBGA-107 静态存储器内存集成电路
文件：	总69页 (文件大小：983K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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