MB85RC64APNF-G [FUJITSU]
64 K (8 K Ã 8) Bit I2C;
| 型号： | MB85RC64APNF-G |
| 厂家： | 
FUJITSU |
| 描述： | 64 K (8 K Ã 8) Bit I2C |
| 文件： | 总32页 (文件大小：287K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS501-00019-2v0-E
Memory FRAM
64 K (8 K × 8) Bit I2C
MB85RC64A
■ DESCRIPTION
The MB85RC64A is an FRAM (Ferroelectric Random Access Memory) chip in a configuration of 8,192
words × 8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the
nonvolatile memory cells.
Unlike SRAM, the MB85RC64A is able to retain data without using a data backup battery.
The read/write endurance of the nonvolatile memory cells used for the MB85RC64A has improved to be at
least 1012 cycles, significantly outperforming Flash memory and E2PROM in the number.
The MB85RC64A does not need a polling sequence after writing to the memory such as the case of Flash
memory or E2PROM.
■ FEATURES
• Bit configuration
: 8,192 words × 8 bits
• Two-wire serial interface
• Operating frequency
• Read/write endurance
• Data retention
: Fully controllable by two ports: serial clock (SCL) and serial data (SDA).
: 1 MHz (Max)
: 1012 times / byte
: 10 years ( + 85 °C), 95 years ( + 55 °C), over 200 years ( + 35 °C)
• Operating power supply voltage : 2.7 V to 3.6 V
• Low power consumption : Operating power supply current 250 μA (Typ @1 MHz)
Standby current 5 μA (Typ)
• Operation ambient temperature range : − 40 °C to + 85 °C
• Package
: 8-pin plastic SOP (FPT-8P-M02)
RoHS compliant
Copyright©2012-2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2013.2
MB85RC64A
■ PIN ASSIGNMENT
(TOP VIEW)
A0
A1
A2
1
2
3
4
8
7
6
5
VDD
WP
SCL
SDA
VSS
(FPT-8P-M02)
■ PIN FUNCTIONAL DESCRIPTIONS
Pin
Pin Name
Number
Functional Description
Device Address pins
The MB85RC64A can be connected to the same data bus up to 8 devices.
Device addresses are used in order to identify each of these devices. Connect
these pins to VDD pin or VSS pin externally. Only if the combination of VDD and
VSS pins matches a Device Address Code inputted from the SDA pin, the
device operates. In the open pin state, A0, A1, and A2 pins are internally pulled-
down and recognized as the “L” level.
1 to 3
A0 to A2
4
5
VSS
SDA
Ground pin
Serial Data I/O pin
This is an I/O pin which performs bidirectional communication for both memory
address and writing/reading data. It is possible to connect multiple devices. It is
an open drain output, so a pull-up resistor is required to be connected to the ex-
ternal circuit.
Serial Clock pin
6
SCL
This is a clock input pin for input/output timing serial data. Data is sampled on
the rising edge of the clock and output on the falling edge.
Write Protect pin
When the Write Protect pin is the “H” level, the writing operation is disabled.
When the Write Protect pin is the “L” level, the entire memory region can be
overwritten. The reading operation is always enabled regardless of the Write
Protect pin input level. The write protect pin is internally pulled down to VSS pin,
and that is recognized as the “L” level (write enabled) when the pin is the open
state.
7
8
WP
VDD
Supply Voltage pin
2
DS501-00019-2v0-E
MB85RC64A
■ BLOCK DIAGRAM
Serial/Parallel Converter
SDA
FRAM Array
8,192 × 8
SCL
WP
Column Decoder/Sense Amp/
Write Amp
A0, A1, A2
■ I2C (Inter-Integrated Circuit)
The MB85RC64A has the two-wire serial interface; the I2C bus,and operates as a slave device.
The I2C bus defines communication roles of “master” and “slave” devices, with the master side holding the
authority to initiate control. Furthermore, an I2C bus connection is possible where a single master device is
connected to multiple slave devices in a party-line configuration. In this case, it is necessary to assign a
unique device address to the slave device, the master side starts communication after specifying the slave
to communicate by addresses.
• I2C Interface System Configuration Example
VDD
Pull-up
Resistors
SCL
SDA
I2C Bus
MB85RC64A
I2C Bus
MB85RC64A
I2C Bus
MB85RC64A
I2C Bus
Master
...
A2 A1 A0
A2 A1 A0
A2 A1 A0
0
0
0
0
0
1
0
1
0
Device address
DS501-00019-2v0-E
3
MB85RC64A
■ I2C COMMUNICATION PROTOCOL
The I2C bus is a two wire serial interface that uses a bidirectional data bus (SDA) and serial clock (SCL). A
data transfer can only be initiated by the master, which will also provide the serial clock for synchronization.
The SDA signal should change while SCL is the “L” level. However, as an exception, when starting and
stopping communication sequence, SDA is allowed to change while SCL is the “H” level.
• Start Condition
To start read or write operations by the I2C bus, change the SDA input from the “H” level to the “L” level while
the SCL input is in the “H” level.
• Stop Condition
To stop the I2C bus communication, change the SDA input from the “L” level to the “H” level while the SCL
input is in the “H” level. In the reading operation, inputting the stop condition finishes reading and enters the
standby state. In the writing operation, inputting the stop condition finishes inputting the rewrite data and
enters the standby state.
• Start Condition, Stop Condition
SCL
SDA
“H” or “L”
Start
Stop
Note : At the write operation, the FRAM device does not need the programming wait time (tWC) after issuing the
Stop Condition.
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MB85RC64A
■ ACKNOWLEDGE (ACK)
In the I2C bus, serial data including address or memory information is sent in units of 8 bits. The acknowledge
signal indicates that every 8 bits of the data is successfully sent and received. The receiver side usually
outputs the “L” level every time on the 9th SCL clock after each 8 bits are successfully transmitted and
received. On the transmitter side, the bus is temporarily released to Hi-Z every time on this 9th clock to allow
the acknowledge signal to be received and checked. During this Hi-Z-released period, the receiver side pulls
the SDA line down to indicate the “L” level that the previous 8 bits communication is successfully received.
In case the slave side receives Stop condition before sending or receiving the ACK “L” level, the slave side
stops the operation and enters to the standby state. On the other hand, the slave side releases the bus state
after sending or receiving the NACK “H” level. The master side generates Stop condition or Start condition
in this released bus state.
• Acknowledge timing overview diagram
1
2
3
8
9
SCL
SDA
ACK
The transmitter side should always release SDA on the
9th bit. At this time, the receiver side outputs a pull-down if
the previous 8 bits data are received correctly (ACK re-
sponse).
Start
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5
MB85RC64A
■ DEVICE ADDRESS WORD (Slave address)
Following the start condition, the master sends the 8 bits device address word to start I2C communication.
The device address word (8 bits) consists of a device Type code (4 bits), device address code (3 bits), and
a read/write code (1 bit).
• Device Type Code (4 bits)
The upper 4 bits of the device address word are a device type code that identifies the device type, and are
fixed at “1010” for the MB85RC64A.
• Device Address Code (3 bits)
Following the device type code, the 3 bits of the device address code are input in order of A2, A1, and A0.
The device address code identifies one device from up to eight devices connected to the bus.
Each MB85RC64A is given a unique 3 bits code on the device address pin (external hardware pin A2, A1,
and A0). The slave only responds if the received device address code is equal to this unique 3 bits code.
• Read/Write Code (1 bit)
The 8th bit of the device address word is the R/W (read/write) code. When the R/W code is “0”, a write
operation is enabled, and the R/W code is “1”, a read operation is enabled for the MB85RC64A.
It turns to a stand-by state if the device code is not “1010” or device address code does not equal to pins
A2, A1, and A0.
• Device Address Word
2
Start
1
2
3
4
5
6
7
8
9
1
..
..
SCL
SDA
ACK
A
1
0
1
0
R/W
S
A2 A1 A0
Device Code Device Address Code Read/Write Code
Access from master
Access from slave
S
A
Start Condition
ACK (SDA is the "L" level)
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MB85RC64A
■ DATA STRUCTURE
In the I2C bus, the acknowledge “L” level is output on the 9th bit by a slave, after the 8 bits of the device
address word following the start condition are input by a master. After confirming the acknowledge response
by the master, the master outputs 8bits × 2 memory address to the slave. When the each memory address
input ends, the slave again outputs the acknowledge “L” level. After this operation, the I/O data follows in
units of 8 bits, with the acknowledge “L” level output after every 8 bits.
It is determined by the R/W code whether the data line is driven by the master or the slave. However, the
clock line shall be driven by the master. For a write operation, the slave will accept 8 bits from the master,
then send an acknowledge. If the master detects the acknowledge, the master will transfer the next 8 bits.
For a read operation, the slave will place 8 bits on the data line, then wait for an acknowledge from the master.
■ FRAM ACKNOWLEDGE -- POLLING NOT REQUIRED
The MB85RC64A performs write operations at the same speed as read operations, so any waiting time for
an ACK polling* does not occur. The write cycle takes no additional time.
*: In E2PROM, the Acknowledge Polling is performed as a progress check whether rewriting is executed or not.
It is normal to judge by the 9th bit of Acknowledge whether rewriting is performed or not after inputting the
start condition and then the device address word (8 bits) during rewriting.
■ WRITE PROTECT (WP)
The entire memory array can be write protected using the Write Protect pin. When the Write Protect pin is
set to the “H” level, the entire memory array will be write protected. When the Write Protect pin is the “L”
level, entire memory array will be rewritten. Reading is allowed regardless of the WP pin's “H” level or “L” level.
Note : The Write Protect pin is pulled down internally to VSS pin, therefore if the Write Protect pin is open, the
pin status is detected as the “L” level (write enabled).
DS501-00019-2v0-E
7
MB85RC64A
■ COMMAND
• Byte Write
If the device address word (R/W “0” input ) is sent following the start condition, the slave responds with an
ACK. After this ACK, write addresses and data are sent in the same way, and the write ends by generating
a stop condition at the end.
Address
High 8bits
Address
Low 8bits
Write
Data 8bits
1
0
1
0 A2 A1 A0 0
A
A
A
A P
S
0 0 0 X X X X X
X X X X X X XX
Access from master
Access from slave
MSB
LSB
S
P
A
Start Condition
Stop Condition
ACK (SDA is the "L" level)
Note : In the MB85RC64A, input “000” as the upper 3 bits of the MSB.
• Page Write
If additional 8 bits are continuously sent after the same command (except stop condition) as Byte Write, a
page write is performed. The memory address rolls over to first memory address (0000H) at the end of the
address. Therefore, if more than 8 Kbytes are sent, the data is overwritten in order starting from the start of
the memory address that was written first. Because FRAM performs the high-speed write operations, the
data will be written to FRAM right after the ACK response finished.
Address
High 8bits
Address
Low 8bits
Write
Data 8bits
Write
Data
...
1
0
1
0 A2 A1 A0 0
A
A
A
A
A
P
S
Access from master
Access from slave
S
P
Start Condition
Stop Condition
A
ACK (SDA is the "L" level)
Note : It is not necessary to take a period for internal write operation cycles from the buffer to the memory after
the stop condition is generated.
8
DS501-00019-2v0-E
MB85RC64A
• Current Address Read
When the previous write or read operation finishes successfully up to the stop condition and assumes the
last accessed address is “n”, then the address at “n+1” is read by sending the following command unless
turning the power off. If the memory address is last address, the address counter will roll over to 0000H. The
current address in memory address buffer is undefined immediately after the power is turned on.
Access from master
Access from slave
S
Start Condition
Stop Condition
(n+1) address
Read
Data 8bits
P
A
N
1
0 1 0 A2 A1 A0 1 A
N P
S
ACK(SDA is the "L" level)
NACK (SDA is the "H" level)
• Random Read
The one byte of data from the memory address saved in the memory address buffer can be read out
synchronously to SCL by specifying the address in the same way as for a write, and then issuing another
start condition and sending the Device Address Word (R/W “1” input).
The final NACK is issued by the receiver that receives the data. In this case, this bit is issued by the master
side.
Address
High 8bits
Address
Low 8bits
Read
Data 8bits
1
0
1
0 A2 A1 A0 0
A
A
A
1
0
1
0 A2 A1 A0 1
A
N P
S
S
Access from master
Access from slave
S
P
A
N
Start Condition
Stop Condition
ACK (SDA is the "L" level)
NACK (SDA is the "H" level)
DS501-00019-2v0-E
9
MB85RC64A
• Sequential Read
Data can be received continuously following the Device address word (R/W “1” input) after specifying the
address in the same way as for Random Read. If the read reaches the end of address, the internal read
address automatically rolls over to first memory address 0000H and keeps reading.
Read
Data
Read
Data 8bits
Read
Data 8bits
...
...
A
A
A
N
P
Access from master
Access from slave
Stop Condition
P
A
N
ACK (SDA is the "L" level)
NACK (SDA is the "H" level)
■ SOFTWARE RESET SEQUENCE OR COMMAND RETRY
In case the malfunction has occurred after power on, the master side stopped the I2C communication during
processing, or unexpected malfunction has occurred, execute the following (1) software recovery sequence
just before each command, or (2) retry command just after failure of each command.
(1) Software Reset Sequence
Since the slave side may be outputting “L” level, do not force to drive “H” level, when the master side drives
the SDA port. This is for preventing a bus conflict. The additional hardware is not necessary for this software
reset sequence.
9 set of “Start Conditions and one “1” data”
SCL
SDA
Hi-Z state by pull up Resistor
Send “Start Condition and one data “1”” .
Repeat these 9 times just before Write or Read command.
(2) Command Retry
Command retry is useful to recover from failure response during I2C communication.
10
DS501-00019-2v0-E
MB85RC64A
■ ABSOLUTE MAXIMUM RATINGS
Rating
Parameter
Symbol
Unit
Max
Min
Power supply voltage*
Input voltage*
VDD
VIN
− 0.5
− 0.5
− 0.5
− 40
− 55
+4.0
V
VDD + 0.5 ( ≤ 4.0)
VDD + 0.5 ( ≤ 4.0)
+ 85
V
Output voltage*
VOUT
TA
V
Operation ambient temperature
Storage temperature
°C
°C
Tstg
+ 125
*: These parameters are based on the condition that VSS is 0 V.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Unit
Min
Typ
Max
Power supply voltage*
“H” level input voltage*
VDD
VIH
2.7
3.3
3.6
V
V
VDD + 0.5
( ≤ 4.0)
VDD × 0.8
⎯
“L” level input voltage*
VIL
TA
− 0.5
− 40
⎯
⎯
+ 0.6
+ 85
V
Operation ambient temperature
°C
*: These parameters are based on the condition that VSS is 0 V.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
onthedatasheet.Usersconsideringapplicationoutsidethelistedconditionsareadvisedtocontact
their representatives beforehand.
DS501-00019-2v0-E
11
MB85RC64A
■ ELECTRICAL CHARACTERISTICS
1. DC Characteristics
(within recommended operating conditions)
Value
Parameter
Symbol
Condition
Unit
Min
⎯
Typ
⎯
Max
1
Input leakage current
|ILI|
|ILO|
IDD
SCL, SDA = 0 V to VDD
SDA = 0 V to VDD
SCL = 1 MHz
μA
μA
μA
Output leakage current
Operating power supply current
⎯
⎯
1
⎯
250
375
SCL, SDA = VDD
A0, A1, A2, WP = 0 V or VDD
Standby current
ISB
⎯
5
20
μA
“L” level output voltage
VOL
IOL = 3 mA
⎯
50
1
⎯
⎯
⎯
0.4
⎯
V
VIN = VIL (Max)
VIN = VIH (Min)
kΩ
MΩ
Input resistance for
WP, A0, A1 and A2
RIN
⎯
2. AC Characteristics
Parameter
Value
Fast Mode
Symbol Standard Mode
Fast Mode Plus Unit
Min
0
Max
100
⎯
Min
0
Max
400
⎯
Min
0
Max
1000
⎯
SCL clock frequency
Clock high time
FSCL
THIGH
TLOW
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4000
4700
⎯
600
1300
⎯
400
600
⎯
Clock low time
⎯
⎯
⎯
SCL/SDA rising time
SCL/SDA falling time
Start condition hold
Start condition setup
SDA input hold
Tr
1000
300
⎯
300
300
⎯
300
100
⎯
Tf
⎯
⎯
⎯
THD:STA
TSU:STA
THD:DAT
TSU:DAT
TDH:DAT
TSU:STO
TAA
4000
4700
0
600
600
0
250
250
0
⎯
⎯
⎯
⎯
⎯
⎯
SDA input setup
250
0
⎯
100
0
⎯
100
0
⎯
SDA output hold
⎯
⎯
⎯
Stop condition setup
SDA output access after SCL falling
Pre-charge time
4000
⎯
⎯
600
⎯
⎯
250
⎯
⎯
3000
-
900
-
550
⎯
TBUF
4700
1300
500
Noise suppression time
(SCL and SDA)
TSP
⎯
50
⎯
50
⎯
50
ns
AC characteristics were measured under the following measurement conditions.
Power supply voltage : 2.7 V to 3.6 V
Operation ambient temperature : − 40 °C to + 85 °C
Input voltage magnitude
Input rising time
: 0.3 V to 2.7 V
: 5 ns
Input falling time
: 5 ns
Input judge level
: VDD/2
Output judge level
: VDD/2
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DS501-00019-2v0-E
MB85RC64A
3. AC Timing Definitions
TSU:DAT
THD:DAT
VIH
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
SCL
Stop
Start
VIL
VIH
VIH
VIL
VIH
VIL
VIH
VIL
SDA
VIL
TSU:STA THD:STA
TSU:STO
Tr
Tf
THIGH
TLOW
VIH
VIL
VIH
VIL
VIH
VIH
VIL
SCL
SDA
Stop
Start
VIL
VIH
VIH
VIH
VIL
VIH
VIL
VIL
VIL
TBUF
Tr
TAA
Tf
Tsp
TDH:DAT
VIH
SCL
SDA
VIL
VIL
VIH
VIL
VIH
VIL
Valid
VIL
1/FSCL
4. Pin Capacitance
Parameter
Value
Typ
⎯
Symbol
Conditions
Unit
Min
Min
15
I/O capacitance
CI/O
CIN
⎯
⎯
pF
pF
VDD = VIN = VOUT = 0 V,
f = 1 MHz, TA = + 25 °C
Input capacitance
⎯
15
5. AC Test Load Circuit
3.3 V
1.1 k
Ω
Output
100 pF
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13
MB85RC64A
■ POWER ON/OFF SEQUENCE
If VDD falls down below 2.0V, VDD is required to be started from 0V to prevent malfunctions when the power
is turned on again.
tr
tpu
tpd
VDD
VDD
2.7 V
2.7 V
VIH (Min)
VIH (Min)
1.0 V
1.0 V
VIL (Max)
VIL (Max)
0 V
0 V
*
*
SDA, SCL >VDD × 0.8
SDA, SCL : Don't care
SDA, SCL >VDD × 0.8
SDA, SCL
SDA, SCL
* : SDA, SCL (Max) < VDD + 0.5 V
Value
Parameter
Symbol
Unit
Min
85
Max
SDA, SCL level hold time during power down
SDA, SCL level hold time during power up
Power supply rising time
tpd
tpu
tr
⎯
⎯
⎯
ns
ns
μs
85
10
If the device does not operate within the specified conditions of read cycle, write cycle or power on/off
sequence, memory data can not be guaranteed.
■ FRAM CHARACTERISTICS
Item
Min
1012
10
Max
⎯
Unit
Parameter
Read/Write Endurance*1
Times/byte Operation Ambient Temperature TA = + 85 °C
Operation Ambient Temperature TA = + 85 °C
⎯
Data Retention*2
95
⎯
Years
Operation Ambient Temperature TA = + 55 °C
Operation Ambient Temperature TA = + 35 °C
≥ 200
⎯
*1 : Total number of reading and writing defines the minimum value of endurance, as an FRAM memory operates
with destructive readout mechanism.
*2 : Minimun values define retention time of the first reading/writing data right after shipment, and these values
are calculated by qualification results.
■ NOTE ON USE
• Data written before performing IR reflow is not guaranteed after IR reflow.
• During the access period from the start condition to the stop condition, keep the level of WP, A0, A1, and
A2 pins to the “H” level or the “L” level.
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MB85RC64A
■ ESD AND LATCH-UP
Test
DUT
Value
ESD HBM (Human Body Model)
JESD22-A114 compliant
≥ |2000 V|
ESD MM (Machine Model)
JESD22-A115 compliant
≥ |200 V|
ESD CDM (Charged Device Model)
JESD22-C101 compliant
⎯
⎯
⎯
⎯
⎯
Latch-Up (I-test)
JESD78 compliant
MB85RC64APNF-G-JNE1
Latch-Up (Vsupply overvoltage test)
JESD78 compliant
Latch-Up (Current Method)
Proprietary method
Latch-Up (C-V Method)
Proprietary method
• Current method of Latch-Up Resistance Test
Protection Resistance
A
VDD
I
IN
Test terminal
VDD
(Max.Rating)
DUT
+
-
VIN
V
VSS
Reference
terminal
Note : The voltage VIN is increased gradually and the current IIN of 300 mA at maximum shall flow. Confirm the
latch up does not occur under IIN = 300 mA.
In case the specific requirement is specified for I/O and IIN cannot be 300 mA, the voltage shall be
increased to the level that meets the specific requirement.
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15
MB85RC64A
• C-V method of Latch-Up Resistance Test
Protection Resistance
A
Test
terminal
VDD
1
2
VDD
(Max.Rating)
SW
DUT
+
V
IN
V
C
200pF
-
VSS
Reference
terminal
Note Charge voltage alternately switching 1 and 2 approximately 2 sec interval. This switching process is
considered as one cycle.
Repeat this process 5 times. However, if the latch-up condition occurs before completing 5 times, this
test must be stopped immediately.
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MB85RC64A
■ REFLOW CONDITIONS AND FLOOR LIFE
Item
Condition
Method
Times
IR (infrared reflow) , Convection
2
Before unpacking
Please use within 2 years after production.
Within 8 days
From unpacking to 2nd reflow
In case over period of floor life
Baking with 125 °C+/-3 °C for
24hrs+2hrs/-0hrs is required.
Then please use within 8 days.
Floor life
(Please remember baking is up to 2 times)
Between 5 °C and 30 °C and also below 70%RH required.
(It is preferred lower humidity in the required temp range.)
Floor life condition
Reflow Profile
260°C
255°C
Liquidous
Temperature
170 °C
to
190 °C
(b)
(c)
(d)
(e)
RT
(a)
(d')
(a) Average ramp-up rate
(b) Preheat & Soak
(c) Average ramp-up rate
(d) Peak temperature
(d’) Liquidous temperature
: 1 °C/s to 4 °C/s
: 170 °C to 190 °C, 60 s to 180 s
: 1 °C/s to 4 °C/s
: Temperature 260 °C Max; 255 °C within 10 s
: Up to 230 °C within 40 s or
Up to 225 °C within 60 s or
Up to 220 °C within 80 s
(e) Cooling
: Natural cooling or forced cooling
Note : Temperature on the top of the package body is measured.
DS501-00019-2v0-E
17
MB85RC64A
■ RESTRICTED SUBSTANCES
This product complies with the regulations below (Based on current knowledge as of November 2011).
• EU RoHS Directive (2002/95/EC)
• China RoHS (Administration on the Control of Pollution Caused by Electronic Information Products
(
))
• Vietnam RoHS (30/2011/TT-BCT)
Restricted substances in each regulation are as follows.
Substances Threshold
Lead and its compounds
Contain status*
1,000 ppm
1,000 ppm
100 ppm
❍
❍
❍
❍
❍
❍
Mercury and its compounds
Cadmium and its compounds
Hexavalent chromium compound
Polybrominated biphenyls (PBB)
Polybrominated diphenyl ethers (PBDE)
1,000 ppm
1,000 ppm
1,000 ppm
* : The mark of “❍” shows below a threshold value.
18
DS501-00019-2v0-E
MB85RC64A
■ ORDERING INFORMATION
Minimum shipping
quantity
Part number
Package
Shipping form
8-pin, plastic SOP
(FPT-8P-M02)
MB85RC64APNF-G-JNE1
Tube
1
8-pin, plastic SOP
(FPT-8P-M02)
MB85RC64APNF-G-JNERE1
Embossed Carrier tape
1500
DS501-00019-2v0-E
19
MB85RC64A
■ PACKAGE DIMENSION
8-pin plastic SOP
Lead pitch
1.27 mm
3.9 mm × 5.05 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.75 mm MAX
0.06 g
(FPT-8P-M02)
8-pin plastic SOP
Note 1) *1 : These dimensions include resin protrusion.
(FPT-8P-M02)
*
Note 2) 2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
+0.25
1 5.05 –0.20 .199 +–..000180
0.22 –+00..0073
.009 +–..000031
*
8
5
*
2 3.90±0.30 6.00±0.20
(.154±.012) (.236±.008)
Details of "A" part
1.55±0.20
45°
(Mounting height)
(.061±.008)
0.25(.010)
0.40(.016)
0~8
°
"A"
1
4
1.27(.050)
0.44±0.08
(.017±.003)
M
0.13(.005)
0.50±0.20
(.020±.008)
0.15±0.10
(.006±.004)
(Stand off)
0.60±0.15
(.024±.006)
0.10(.004)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2002-2012 FUJITSU SEMICONDUCTOR LIMITED F08004S-c-5-10
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
20
DS501-00019-2v0-E
MB85RC64A
■ MARKING
[MB85RC64APNF-G-JNE1]
[MB85RC64APNF-G-JNERE1]
RC64A
E11000
300
[FPT-8P-M02]
DS501-00019-2v0-E
21
MB85RC64A
■ PACKING INFORMATION
1. Tube
1.1 Tube Dimensions
• Tube/stopper shape
Tube
Transparent polyethylene terephthalate
(treated to antistatic)
Stopper
(treated to antistatic)
Tube length: 520 mm
Tube cross-sections and Maximum quantity
Package form
Maximum quantity
Package code
FPT-8P-M02
pcs/
tube
pcs/inner
box
pcs/outer
box
SOP, 8, plastic (2)
95
7600
30400
7.4
6.4
4.4
©2006-2010 FUJITSU SEMICONDUCTOR LIMITED
F08008-SET1-PET:FJ99L-0022-E0008-1-K-3
t = 0.5
Transparent polyethylene terephthalate
(Dimensions in mm)
22
DS501-00019-2v0-E
MB85RC64A
1.2 Tube Dry pack packing specifications
IC
Tube
Stopper
For SOP
Index mark
Label I *1*3
Aluminum Iaminated bag
Heat seal
Dry pack
Inner box
Desiccant
Humidity indicater
Aluminum Iaminated bag
(tubes inside)
Cushioning material
Inner box
Label I *1*3
Cushioning material
Outer box*2
Outer box
Use adhesive tapes.
Label II-A *3
Label II-B *3
*1: For a product of witch part number is suffixed with “E1”, a “
bag and the inner boxes.
G
Pb ” marks is display to the moisture barrier
*2: The space in the outer box will be filled with empty inner boxes, or cushions, etc.
*3: Please refer to an attached sheet about the indication label.
Note: The packing specifications may not be applied when the product is delivered via a distributer.
DS501-00019-2v0-E
23
MB85RC64A
1.3 Product label indicators
Label I: Label on Inner box/Moisture Barrier Bag/ (It sticks it on the reel for the emboss taping)
[C-3 Label (50mm × 100mm) Supplemental Label (20mm × 100mm)]
(Customer part number or FJ part number)
XXXXXXXXXXXXXX
C-3 Label
(3N)1 XXXXXXXXXXXXXX XXX
(LEAD FREE mark)
(Part number and quantity)
QC PASS
(3N)2 XXXXXXXXXX XXXXXX
(FJ control number)
(Quantity)
(Customer part number or FJ part number)
(Customer part number or FJ part number
bar code)
XXX pcs
XXXXXXXXXXXXXX
XXXX/XX/XX (Packed years/month/day) ASSEMBLED IN xxxx
Perforated line
XXXXXXXXXXXXXX
(Customer part number or FJ part number)
(FJ control number bar code)
Supplemental Label
XX/XX
(Package count)
XXXX-XXX XXX
XXXX-XXX XXX
XXXXXXXXXX
(FJ control number )
(Lot Number and quantity)
XXXXXXXXXXXXXX
(Comment)
Label II-A: Label on Outer box [D Label] (100mm × 100mm)
D Label
XXXXXXXXXXXXX (Customer Name)
(CUST.)
XXXXXXXXX (Delivery Address)
(DELIVERY POINT)
XXX (FJ control number)
XXXXXXXXXXXXXX
XXX (FJ control number)
(TRANS.NO.) (FJ control number)
XXX (FJ control number)
XXXXXXXXXXXXXX
(Customer part number or
XXXXXXXXXXXXXX
(Part number)
(PART NO.)
FJ part number)
(PART NAME) XXXXXXXXXXXXXX (Part number)
XXX/XXX
XX
(Q’TY/TOTAL Q’TY)
(UNIT)
(CUSTOMER'S
(PACKAGE COUNT)
XXX/XXX
REMARKS)
XXXXXXXXXXXXXXXXXXXX
(3N)3 XXXXXXXXXXXXXX XXX
(FJ control number + Product quantity)
(FJ control number + Product quantity
bar code)
(3N)4 XXXXXXXXXXXXXX XXX
(3N)5 XXXXXXXXXX
(Part number + Product quantity)
(Part number + Product quantity bar code)
(FJ control number)
(FJ control number bar code)
Label II-B: Outer boxes product indicate
XXXXXXXXXXXXXX (Part number)
(Count)
X
X
(Quantity)
XXX
XXX
(Lot Number)
XXXX-XXX
XXXX-XXX
XXX
Note: Depending on shipment state, “Label II-A” and “Label II-B” on the external boxes might not be printed.
24
DS501-00019-2v0-E
MB85RC64A
1.4 Dimensions for Containers
(1) Dimensions for inner box
H
W
L
L
W
H
540
125
75
(Dimensions in mm)
(2) Dimensions for outer box
H
W
L
L
W
H
565
270
180
(Dimensions in mm)
DS501-00019-2v0-E
25
MB85RC64A
2. Emboss Tape
2.1 Tape Dimensions
Maximum storage capacity
pcs/reel
PKG code
Reel No
pcs/inner box pcs/outer box
FPT-8P-M02
3
1500
1500
10500
2±0.05
4±0.1
+0.1
0.3±0.05
8±0.1
ø1.5
–0
B
+0.1
ø1.5
–0
A
B
A
SEC.B-B
6.4±0.1
3.9±0.2
SEC.A-A
C
2012 FUJITSU SEMICONDUCTOR LIMITED SOL8-EMBOSSTAPE9 : NFME-EMB-X0084-1-P-1
(Dimensions in mm)
Material : Conductive polystyrene
Heat proof temperature : No heat resistance.
Package should not be baked
by using tape and reel.
26
DS501-00019-2v0-E
MB85RC64A
2.2 IC orientation
Index mark
• ER type
(User Direction of Feed)
(Reel side)
(User Direction of Feed)
2.3 Reel dimensions
Reel cutout dimensions
E
∗
W1
W2
W3
r
∗: Hub unit width dimensions
Dimensions in mm
Reel No
1
8
2
3
4
5
6
7
8
9
10
11
12
56
13
12
14
15
Tape width
Symbol
12
16
24
32
44
16
24
A
B
C
254 ± 2 254 ± 2 330 ± 2 254 ± 2 330 ± 2 254 ± 2 330 ± 2
330 ± 2
+2
+2
-0
+2
-0
+2
-0
+2
-0
+2
-0
100 ± 2
100
100
150
100
150
100
-0
+0.5
-0.2
13 ± 0.2
21 ± 0.8
13
+1
-0.2
D
E
20.5
2 ± 0.5
32.4
+2
-0
+2
-0
+2
-0
+2
-0
+2
-0
+2
+2
-0
+1
-0
+1
-0
+0.1
W1
8.4
12.4
16.4
24.4
44.4
56.4
12.4
16.4
24.4
-0
-0
less than
14.4
less than less than less than less than
W2
less than 18.4
11.9 ~ 15.4
less than 22.4
15.9 ~ 19.4
less than 30.4
23.9 ~ 27.4
less than 38.4
less than 50.4
43.9 ~ 47.4
62.4
18.4
22.4
30.4
55.9 ~
59.4
12.4 ~
14.4
16.4 ~
18.4
24.4 ~
26.4
W3
r
7.9 ~ 10.9
31.9 ~ 35.4
1.0
DS501-00019-2v0-E
27
MB85RC64A
2.4 Taping (φ330mm Reel) Dry Pack Packing Specifications
φ
Outside diameter: 330mm reel
Label I *1, *4
Embossed
tapes
Label I *1, *4
Desiccant
Humidity indicator
Aluminum laminated bag
Label I *1, *4
Dry pack
Heat seal
Inner box
Inner box
Label I *1, *4
Taping
Outer box *2, *3
Outer box
Use adhesive tapes.
Label II-A *4
Label II-B *4
*1: For a product of witch part number is suffixed with “E1”, a “
bag and the inner boxes.
G
” marks is display to the moisture barrier
Pb
*2: The size of the outer box may be changed depending on the quantity of inner boxes.
*3: The space in the outer box will be filled with empty inner boxes, or cushions, etc.
*4: Please refer to an attached sheet about the indication label.
Note: The packing specifications may not be applied when the product is delivered via a distributer.
28
DS501-00019-2v0-E
MB85RC64A
2.5 Product label indicators
Label I: Label on Inner box/Moisture Barrier Bag/ (It sticks it on the reel for the emboss taping)
[C-3 Label (50mm × 100mm) Supplemental Label (20mm × 100mm)]
(Customer part number or FJ part number)
XXXXXXXXXXXXXX
C-3 Label
(3N)1 XXXXXXXXXXXXXX XXX
(LEAD FREE mark)
(Part number and quantity)
QC PASS
(3N)2 XXXXXXXXXX XXXXXX
(FJ control number)
(Quantity)
(Customer part number or FJ part number)
(Customer part number or FJ part number
bar code)
XXX pcs
XXXXXXXXXXXXXX
XXXX/XX/XX (Packed years/month/day) ASSEMBLED IN xxxx
Perforated line
XXXXXXXXXXXXXX
(Customer part number or FJ part number)
(FJ control number bar code)
Supplemental Label
XX/XX
(Package count)
XXXX-XXX XXX
XXXX-XXX XXX
XXXXXXXXXX
(FJ control number )
(Lot Number and quantity)
XXXXXXXXXXXXXX
(Comment)
Label II-A: Label on Outer box [D Label] (100mm × 100mm)
D Label
XXXXXXXXXXXXX (Customer Name)
(CUST.)
XXXXXXXXX (Delivery Address)
(DELIVERY POINT)
XXX (FJ control number)
XXXXXXXXXXXXXX
XXX (FJ control number)
(TRANS.NO.) (FJ control number)
XXX (FJ control number)
XXXXXXXXXXXXXX
(Customer part number or
XXXXXXXXXXXXXX
(Part number)
(PART NO.)
FJ part number)
(PART NAME) XXXXXXXXXXXXXX (Part number)
XXX/XXX
XX
(Q’TY/TOTAL Q’TY)
(UNIT)
(CUSTOMER'S
(PACKAGE COUNT)
XXX/XXX
REMARKS)
XXXXXXXXXXXXXXXXXXXX
(3N)3 XXXXXXXXXXXXXX XXX
(FJ control number + Product quantity)
(FJ control number + Product quantity
bar code)
(3N)4 XXXXXXXXXXXXXX XXX
(3N)5 XXXXXXXXXX
(Part number + Product quantity)
(Part number + Product quantity bar code)
(FJ control number)
(FJ control number bar code)
Label II-B: Outer boxes product indicate
XXXXXXXXXXXXXX (Part number)
(Count)
X
X
(Quantity)
XXX
XXX
(Lot Number)
XXXX-XXX
XXXX-XXX
XXX
Note: Depending on shipment state, “Label II-A” and “Label II-B” on the external boxes might not be printed.
DS501-00019-2v0-E
29
MB85RC64A
2.6 Dimensions for Containers
(1) Dimensions for inner box
H
W
L
Tape width
12, 16
24, 32
44
L
W
H
40
50
65
75
365
345
56
(Dimensions in mm)
(2) Dimensions for outer box
H
W
L
L
W
H
415
400
315
(Dimensions in mm)
30
DS501-00019-2v0-E
MB85RC64A
■ MAJOR CHANGES IN THIS EDITION
A change on a page is indicated by a vertical line drawn on the left side of that page.
Page
Section
■ FEATURES
Change Results
Revised the Data retention
10 years ( + 85 °C)
→10 years ( + 85 °C), 95 years ( + 55 °C),
over 200 years ( + 35 °C)
1
■ POWER ON/OFF SEQUENCE Revised the following description:
“POWER ON SEQUENCE” → “POWER ON/OFF SEQUENCE”
Added the following description:
“If the device does not operate within the specified conditions of
read cycle, write cycle or power on/off sequence, memory data
can not be guaranteed.”
14
Revised the following description:
“VDD pin is required to be rising from 0 V because turning the pow-
er on from an intermediate level may cause malfunctions, when
the power is turned on”
→“If VDD falls down below 2.0V, VDD is required to be started from
0V to prevent malfunctions when the power is turned on again.”
■ FRAM CHARACTERISTICS
Revised the table and Note
DS501-00019-2v0-E
31
MB85RC64A
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
North and South America
Asia Pacific
FUJITSU SEMICONDUCTOR AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://us.fujitsu.com/micro/
FUJITSU SEMICONDUCTOR ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://sg.fujitsu.com/semiconductor/
Europe
FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.
30F, Kerry Parkside, 1155 Fang Dian Road, Pudong District,
Shanghai 201204, China
Tel : +86-21-6146-3688 Fax : +86-21-6146-3660
http://cn.fujitsu.com/fss/
FUJITSU SEMICONDUCTOR EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/semiconductor/
Korea
FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.
2/F, Green 18 Building, Hong Kong Science Park,
Shatin, N.T., Hong Kong
Tel : +852-2736-3232 Fax : +852-2314-4207
http://cn.fujitsu.com/fsp/
FUJITSU SEMICONDUCTOR KOREA LTD.
902 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fsk/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does
not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any
third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right
by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or
other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in
nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in
weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages aris-
ing in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-
current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations
of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department
相关型号：
MB85RC64APNF-G-JNERE1
Memory Circuit, 8KX8, CMOS, PDSO8, 3.90 X 5.05 MM, 1.75 MM HEIGHT, 1.27 MM PITCH, ROHS COMPLIANT, PLASTIC, SOP-8
FUJITSU
MB85RS128APNF-G-JNE1
Memory Circuit, 16KX8, CMOS, PDSO8, 3.90 X 5.05 MM, 1.27 MM PITCH, 1.75 MM HEIGHT, ROHS COMPLIANT, PLASTIC, SOP-8
FUJITSU
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