MB86611A [FUJITSU]
Serial I/O Controller, 2 Channel(s), 12.288MBps, CMOS, PQFP100, 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100;
| 型号： | MB86611A |
| 厂家： | 
FUJITSU |
| 描述： | Serial I/O Controller, 2 Channel(s), 12.288MBps, CMOS, PQFP100, 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 时钟 数据传输 外围集成电路 |
| 文件： | 总43页 (文件大小：480K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
- PRELIMINARY -
February 1998
Edition 2.0
DATA SHEET
MB86611A
IEEE 1394 Serial Bus Controller (DV-over-1394)
DESCRIPTION
100-PIN PLASTIC LQFP
Fujitsu MB86611A is a high performance 1394 Serial Bus Controller LSI conforming to
IEEE1394 standard draft (P1394; Rev.8.0 ver. 2). This controller LSI has two cable ports
with on-chip differential transceivers and comparators for a network under the 1394 cable
environment. For data rate, the MB86611A supports S100.
(FPT-100P-M05)
The 1394 physical layer and link layer are integrated into s single-chip for down-sizing and
low power consumption.
Also, the device has a set of specific data ports for Isochronous data transfer making the
isolation of header and data sections, and packetize automatically to achieve the consecu-
tive data transfer.
Furthermore, since MB86611A has the DVC mode for the AV/C protocol to support the vari-
ous automatic operations and CSR function, it is suitable for DVC use.
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields.
However, it is advised that normal precautions be taken to
avoid application of any voltage higher than maximum rated
voltages to this high impedance circuit.
FEATURES
• Complies with IEEE 1394-1995 high-performance serial bus standard draft
• Integrates Physical layer and Link layer into a single-chip
• 2 cable ports (S100: 98.304Mbps data rate ).
• 3.3V single power supply
• Internal clock generator by on-chip PLL (with crystal oscillator)
• Power Down Modes:
1) Forced sleep by an instruction of external MPU
2) Automatic sleep for non-connected ports
• Cycle master function
• On-chip various CSRs for Isochronous-Resource-Manager
• 32-bit CRC generation & check
• General-purpose ports for asynchronous transfer (16-bit MPU/DMA common bus)
• Isochronous-transfer ports (8-bit bus)
• On-chip Transaction sequencer
• 4-pin Cable Support
• Power supply voltage: Single +3.3 V
• Package: 100-Pin Plastic LQFP
Copyright
1998 by FUJITSU LIMITED
1
MB86611A
MB86611A Pin Assignment
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
RESET
INT
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
AVDD
AVSS
TPA0
2
3
VDD
VSS
ALE
D15
D14
D13
D12
D11
D10
D9
4
TPB0
TPA0
5
6
TPB0
AVDD
AVSS
TPBIAS0
AVDD
AVSS
RO0
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
LQFP100P
TOP VIEW
AVSS
AVDD
TPA1
D8
VDD
VSS
D7
TPB1
TPA1
D6
TPB1
AVSS
AVDD
TPBIAS1
AVSS
AVDD
RO1
AD5
AD4
AD3
AD2
AD1
D0
VDD
VSS
TESTIO
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
2
MB86611A
PIN LIST
80-MPU I/F Mode 68-MPU I/F Mode
80-MPU I/F Mode 68-MPU I/F Mode
Pin
No.
Pin
No.
I/O
I/O
Pin Name
Pin Name
Pin Name
Pin Name
1
2
I
RESET
RESET
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
-
-
VDD
VDD
O
INT
VDD
VSS
ALE
D15
D14
D13
D12
D11
D10
D9
INT
VDD
VSS
ALE
D15
D14
D13
D12
D11
D10
D9
VSS
WR
VSS
DS
3
-
I
4
-
I
RD
R/W
5
I
-
VDD
VSS
CS
VDD
VSS
CS
6
IU/O
IU/O
IU/O
IU/O
IU/O
IU/O
IU/O
IU/O
-
-
7
I
8
I
A5
A5
9
I
A4
A4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
I
A3
A3
I
A2
A2
I
A1
A1
D8
D8
-
N.C.
DREQ
DACK
VDD
VSS
X0
N.C.
DREQ
DACK
VDD
VSS
X0
VDD
VSS
D7
VDD
VSS
D7
O
I
-
IU/O
IU/O
IU/O
IU/O
IU/O
IU/O
IU/O
IU/O
-
D6
D6
-
AD5
AD4
AD3
AD2
AD1
D0
AD5
AD4
AD3
AD2
AD1
D0
I/O
I
X1
X1
O
-
TESTP
AVSS
AVDD
VCOIN
TESTP
AVSS
AVDD
VCOIN
(Continued)
-
I
3
MB86611A
80-MPU I/F Mode 68-MPU I/F Mode
80-MPU I/F Mode 68-MPU I/F Mode
Pin
No.
Pin
No.
I/O
I/O
Pin Name
Pin Name
Pin Name
Pin Name
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
O
O
-
CHPO
CHPO
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
I/O
I/O
I/O
I/O
-
TPB0
TPB0
ROP
AVSS
AVDD
TESTIO
RO1
ROP
AVSS
AVDD
TESTIO
RO1
TPA0
TPB0
TPA0
AVSS
AVDD
TEST1
TEST2
VDD
VSS
TEST3
TEST4
ID7
TPA0
TPB0
TPA0
AVSS
AVDD
TEST1
TEST2
VDD
-
O
O
-
-
AVDD
AVSS
TPBIAS1
AVDD
AVSS
TPB1
AVDD
AVSS
TPBIAS1
AVDD
AVSS
TPB1
IU/O
IU/O
-
-
O
-
-
VSS
-
IU/O
IU/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
TEST3
TEST4
ID7
I/O
I/O
I/O
I/O
-
TPA1
TPA1
TPB1
TPB1
ID6
ID6
TPA1
TPA1
ID5
ID5
AVDD
AVSS
RO0
AVDD
AVSS
RO0
ID4
ID4
-
ID3
ID3
O
-
ID2
ID2
AVSS
AVDD
TPBIAS0
AVSS
AVDD
AVSS
AVDD
TPBIAS0
AVSS
AVDD
ID1
ID1
-
ID0
ID0
O
-
VSS
VDD
ICLK
VSS
-
VDD
-
I
ICLK
(Continued)
4
MB86611A
80-MPU I/F Mode 68-MPU I/F Mode
80-MPU I/F Mode 68-MPU I/F Mode
Pin
No.
Pin
No.
I/O
I/O
Pin Name
Pin Name
Pin Name
Pin Name
93
94
95
96
I
O
I
IDIR
IDIR
97
98
I/O
FP
FP
ILWRE
IV
ILWRE
IV
O
I
TEST5
MODE0
MODE1
TEST5
MODE0
MODE1
99
O
ICRCE
ICRCE
100
I
5
MB86611A
PIN FUNCTION
1394 INTERFACE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
Function
Name of pin
TPA0
TPA positive signal of cable port 0
TPA negative signal of cable port 0
TPB positive signal of cable port 0
TPB negative signal of cable port 0
TPA positive signal of cable port 1
TPA negative signal of cable port 1
TPB positive signal of cable port 1
TPB negative signal of cable port 1
TPA0
TPB0
TPB0
TPA1
TPA1
TPB1
TPB1
TPBIAS0
TPBIAS1
RO0
Reference voltage output pin for common voltage on cable port 0
Reference voltage output pin for common voltage on cable port 0
Ground this pin through a 4.8kΩ resistor.
O
O
RO1
O
Ground this pin through a 4.8kΩ resistor.
6
MB86611A
ISOCHRONOUS INTERFACE
I/O
Function
Name of pin
ICLK
I
Clock input pin for Isochronous-Data Interface. (4MHz to 16MHz)
Data Direction Control pin for Isochronous transfer.
IDIR
I
When ”0” is input, it clears FIFO and enters ”Transmission” state. Data transmission starts
after asserting ILWRE signal and receiving one packet data specified in the packet header
setting register at address 10h of bank-0 registers. When ”1” is input, it clears FIFO and
enters ”Receipt” state. However, when there are any packets in process (in transmission), the
device will not be in ”receipt” state until all the packet is transmitted. Receiving 1 packet as-
serts ILWRE signal.
IDIR signal should normally be ”1” (”H”), and should be ”0” (”L”) only when transmitting the
data.
Access Permission Signal output pin for Isochronous-FIFO.
ILWRE
O
For Transmission state : It becomes ”Active” if FIFO has a space. This signal is negated by
the FIFO state ”Full”. At the negate state of this signal, the device receives the data for a
rising edge of the next ICLK signal. When the Bus-Reset is detected, it is negated after re-
ceiving the data on packet boundary. After the bus reset, this signal is again asserted at the
completion of transmitting one packet data from the FIFO.
For Receipt state: This signal is asserted when one packet is completely received in the
FIFO. It is once negated every time when one packet is read out from the FIFO. When the
FIFO still has packets in it, the signal is again asserted.
ID7 - ID0
IV
I/O
I
Data input/output pins for Isochronous transfer. (MSB:ID7, LSB:ID0)
Enable Signal Input pin for ID7-ID0.
For Transmission state : While this signal is active, the data are fetched into FIFO at the ris-
ing edge of ICLK.
For Receipt state : Making this signal state ”Active” starts to send the data in FIFO to
ID7-ID0. After that, the data changes synchronizing with the rising edge of ICLK.
ICRCE
FP
O
This signal indicates that data CRC error occurred in the received data.
I/O
Time-Stamp Trigger Signal input/output pin.
For transmission state: This is a Time-Stamp Trigger input pin. The MB86611A fetches it’s
internal cycle timer register value by a falling edge of this signal.
For Receipt state : This pin outputs the detection signal that Time-Stamp matched.
7
MB86611A
SYSTEM INTERFACE
Name of pin
CS
I/O
Function
I
I
Chip Select signal Input pin for MPU to select this device as an I/O device
A5 to A1
Address input pin for selecting internal registers. These signals are valid only when the Non-
multiplexed Mode is selected. This signal must be at ”0” for multiplexed mode.
I/O
I/O
I
D15 to D6,
D0
16-bit data bus input/output pins. (MSB:D15, LSB:D0)
AD5 to AD1
RD (R/W)
16-bit data bus input/output pins. (MSBAD5, LSB:AD1) When address/data multiplexed mode
is selected, these signals also serve as the address input pins.
In 80-system mode: Input pin of read strobe signal for output data to data bus from this device
In 68-system mode: Input pin of control signal R/W for output and input data from/to this
device
I
I
WR (DS)
ALE
In 80-system mode: Input pin for Write strobe signal for input data on data bus to this device
In 68-system mode: Input pin of DS signal output when data bus enabled
This is a ALE signal input pin used to input ALE signal which is output while the specified
address is valid in the Multiplexed mode. For the non-multiplexed mode, please input ”0” to
this pin.
DREQ
O
DMA transfer request signal for DMAC during asynchronous transfer in DMA mode. DMA
transfer is requested between this device and memory.
I
DACK
INT
DMA acknowledgement signal from DMA during asynchronous transfer in DMA mode
Interrupt output pin.
O
8
MB86611A
OTHERS
Name of pin
X0
I/O
I/O
I
Function
External crystal oscillator pins for oscillation circuit
X1
VCOIN
CHPO
ROP
I
VCO input pin for internal PLL
O
O
I
Charge pump output pin for internal PLL
Ground this pin through a 4.8kΩ resistor.
RESET
Reset signal input pin. By detecting the assertion of this signal, the device enters a Force-Sleep
mode automatically.
MODE0
MODE1
I
I
MPU Mode select pin. When ”0” : 80-system mode, and
when ”1” : 68-system mode
Address/Data Multiplexed Mode select pin. When ”0” : Non-multiplexed mode, and when ”1” :
Multiplexed mode.
AVDD
-
Analog power supply pin
Analog GND pin
AVSS
-
-
VDD
Digital power supply pin
Digital GND pin
VSS
-
TEST1,2,3,4
TEST5
IU/O
O
Device test pins. Do not connect with these pins.
Non-connection pin. Do not connect.
TESTP,
TESTIO
O
NC
-
9
MB86611A
BLOCK DIAGRAM
IDIR
ICLK
Transmission
packet
TPA0
TPA0
TPB0
TPB0
process
Isoch-
FIFO
data
1394
I/F
ILWRE
ID7-
ID0
(1KB)
I/F
Reception
packet
process
(1)
Link layer
Control
IV
PHY-
layer
control
TPBIAS0
ICRCE
FP
Transmission
packet
FIFO
(128B)
TPA1
TPA1
TPB1
TPB1
CS
process
1394
I/F
A5-
Async-
A1
data
Reception
packet
D15-
D6,D0
I/F
(DMA)
FIFO
(2)
(128B)
process
&
AD5-
AD1
TPBIAS1
MPU
I/F
cycle master
RD
(R/W)
Sequencer
Dedicated
for transaction transaction
control
circuit
WR
(DS)
PLL
circuit
Various registers
CSR
ALE
INT
DREQ
DACK
10
MB86611A
BLOCK FUNCTION
<Physical layer>
• Supports asynchronous transfer and isochronous transfer under IEEE 1394 cable environment
• 100 Mb/s transfer speed
• Two ports for analog transceiver/receiver, with bus status monitor, initialization, arbitration and encode/decode functions for data transmission/
reception
<Link layer>
• Controls generation and transfer of standard packet in compliance with IEEE 1394
• Generates and checks 32-bits CRC for data and header
• Incorporates 32-bits cycle timer register and cycle master function
<Transmission/Receipt Packet Processing Unit>
• Transmission : Packetizes the header, data, and CRC sections. CRC is generated and added automatically.
• Receipt : Separates the 1394 packet into header and data sections and discards CRC section.
<Transmission/Reception FIFO>
• Incorporates 1KB FIFO for combined transmission/reception as isochronous transfer
• Incorporates 128B FIFO for both transmission/reception as asynchronous transfer
<Sequencer for Universal Transaction>
• Controls 1394 bus protocol by setting universal transfer command and transfer auxiliary command
<Dedicated Transaction Circuit>
• Packetizes the data dedicated to DVC format from data interface pin and reconstructs a receive data to data interface pin with transmission/re-
ception packet processing unit for transfer
<Registers>
• MB86611A’s own control registers, transfer parameter registers, DVC registers, and CSRs are built in. The built-in CSRs have the function
required for Isochronous Resource Manager.
<PLL circuit>
• Generates internal operation clock and transfer clock from reference clock generated by crystal oscillator circuit. Reference oscillation frequen-
cy: 8.192 MHz
11
MB86611A
ABSOLUTE MAXIMUM RATINGS
Rating
Parameter
Symbol
Unit
Min.
Max.
Supply voltage
V
V
SS
V
SS
V
SS
- 0.5
- 0.5
- 0.5
+4.0
V
V
DD
Input voltage
V
V
V
+ 0.5
+ 0.5
I
DD
Output voltage
V
V
O
DD
Operating ambient temperature*2
Storage temperature
Output current *3
Overshoot *4
T
-40
+85
°C
°C
mA
V
OP
T
STG
-55
-14
-
+125
+ 14
I
O
-
VDD+1.0
VSS-1.0
Undershoot *4
-
-
V
*1: The voltage ratings are based on VSS=0V.
*2: Operating ambient temperature rating does not guarantee the continuous chip operation.
*3: Output current rating is the output current that can be flown in steady. (Min.: at Vo=0V, Max.: Vo=VDD).
*4: Overshoot/Undershoot are within 50ns.
NOTE:
Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Unit
Min.
3.0
0
Max.
3.6
Power-supply voltage
Ambient temperature
”H” level Input Voltage
”L” level Input Voltage
V
V
°C
V
DD
T
70
A
V
V
x 0.65
V
DD
CMOS Input
CMOS Input
Cable Input
Cable Input
Cable Input
Cable Input
Cable Input
CMOS Output
TPBIAS
IH
DD
V
V
V
SS
V
x 0.25
V
IL
DD
Differential Input Voltage @ data xfer
Differential Input Voltage @ arbitration
Common Phase Input Voltage
Receive Input Jitter
142
173
1.165
-
260
260
2.515
1.08
0.8
mV
mV
V
ID
V
IDA
V
CM
-
ns
ns
mA
mA
Receive Input Skew
-
-
I
/I
-4
+4
OL OL
Output Current
I
-2
10
OT
*1: Voltage is based on VSS=0V.
12
MB86611A
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS
1394 INTERFACE
(1) Driver
(V = +3 V to +3.6V, V = 0V, T =0 to+70°C)
DD
SS
A
Value
Parameter
Symbol
Unit
Condition
Max.
265
Min.
172
Typ.
Differential Output voltage
Common Phase Current
Off-state Voltage
V
OD
RI=55Ω
-
-
-
-
mV
mA
mV
V
I
Driver enabled
-0.81
-
0.44
20
CM
V
OFF
Driver disabled
-
TPBIAS Output Voltage
V
O
1.665
2.015
(2) Comparator
(V = +3 V to +3.6V, V = 0V, T =0 to+70°C)
DD
SS
A
Value
Parameter
Symbol
Unit
Condition
Max.
20
Min.
-20
89
Typ.
Common Phase Input Current
I
IC
Driver disabled
-
-
-
-
µA
mV
mV
V
Rising Arbitration Comparator Threshold Voltage
Falling Arbitration Comparator Threshold Voltage
Cable Bias Detection Threshold Voltage / TPBx Input
V
SCR
-
-
-
168
-89
1.0
V
SCL
-168
0.6
V
SD
SYSTEM INTERFACE
(V = +3 V to +3.6V, V = 0V, T =0 to+70°C)
DD
SS
A
Value
Parameter
Symbol
Unit
Condition
Max.
Min.
x0.65
Typ.
”H” Level Input Voltage
”L” Level Input Voltage
”H” Level Output Voltage
”L” Level Output Voltage
V
IH
CMOS Input
CMOS Input
V
-
-
V
DD
V
DD
V
IL
V
SS
V x0.25
DD
V
V
OH
I
=-4mA
OH
V
-0.5
SS
-
V
DD
V
DD
V
I
I
=4mA
OL
V
-
0.4
5
V
OL
Input Pins
Input Leakage Current
-5
-5
25
-
-
mA
mA
kΩ
mA
mA
mA
mA
LI
V =0V to VDD
I
Three-state input pins
I
LZ
-
5
Input Pull-up Resistor
When 2 ports used.
R
V =0V
IH
50
-
200
250
200
180
30
P
I
-
DD
When 1 port used.
Supply Current
I
-
-
-
DD1
DD0
DDS
When port is not used.
I
-
-
-
Forced-sleep state
I
-
-
-
13
MB86611A
AC CHARACTERISTICS
1394 DRIVER
Value
Parameter
Symbol
Unit
Condition
Max.
±0.8
±0.8
3.2
Min.
Typ.
Transmit Jitter
t
JT
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
Transmit Skew
t
t
SK
Transmit Rising Time *
Transmit Falling Time *
Note * : The levels are between 10% and 90%.
DR
C =10pF , R =55Ω
L
L
t
DF
3.2
SYSTEM CLOCK
Value
Parameter
Symbol
Unit
Condition
Max.
Min.
Typ.
Clock Frequency
f
-
-
-
-
-
-
-
-
8.192
-
-
MHz
ns
C
Clock Cycle Time
Clock Pulse ”H” Width
Clock Pulse ”L” Width
Clock Rising Time
Clock Falling Time
t
1/fc
CLF
t
50
50
-
-
-
-
-
-
ns
CLCH
t
-
ns
CLCL
t
5
5
ns
CR
t
CF
-
ns
tCLF
tCLCH
tCR
tCF
0.65Vdd
0.25Vdd
CLK
tCLCL
14
MB86611A
SYSTEM RESET
Value
Typ.
-
Parameter
Symbol
Unit
Condition
Max.
Min.
4t
Reset Signal ”L” level Pulse Width
t
-
-
ns
WRSL
CLF
tWRSL
RESET
15
MB86611A
MPU INTERFACE
(1) 68-Series MPU Register Write Operation (Multiplex)
Value
Condition
Parameter
Symbol
Unit
Max.
Min.
10
10
20
10
20
10
15
15
40
10
0
Typ.
-
-
-
-
-
-
-
-
-
-
-
-
Address Setup Time
t
t
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AWSM
AWHM
CWSM
CWHM
RWSM
RWHM
Address Hold Time
CS Setup Time
t
t
t
t
CS Hold Time
R/W Setup Time
R/W Hold Time
ALE ”H” Level Pulse Width
ALE Falling → DS Falling Time
DS ”L” Level Pulse Width
Data Setup Time
t
ALE
t
DWD
t
DSM
t
t
DWSM
DWHM
Data Hold Time
t
20
DS Rising → ALE Rising Time
LWD
tCWSM
tCWHM
CS
tRWSM
tRWHM
R/W
tALE
tDWD
tLWD
ALE
DS
tDSM
tAWSM
tAWHM
tDWSM
tDWHM
D15-D6, D0,
AD5-AD1
Address
Data
16
MB86611A
(2) 68-Series MPU Register Read Operation (Multiplex)
Value
Condition
Parameter
Symbol
Unit
Max.
Min.
10
10
20
10
20
10
15
15
40
-
Typ.
-
-
-
-
-
-
-
-
-
-
-
-
Address Setup Time
t
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ARSM
ARHM
CRSM
CRHM
Address Hold Time
t
t
t
CS Setup Time
-
CS Hold Time
-
R/W Setup Time
t
-
RWSM
R/W Hold Time
t
-
RWH
ALE ”H” Level Pulse Width
ALE Falling → DS Falling Time
DS ”L” Level Pulse Width
Data Output Defined Time
Data Output Disable Time
DS Rising → ALE Rising Time
t
-
ALE
DRD
DSM
t
-
t
-
t
40
-
RLDM
RHDM
t
5
t
20
-
LRD
tCRSM
tCRHM
CS
tRWSM
tRWH
R/W
tALE
tDRD
tLRD
ALE
DS
tDSM
tARSM
tARHM
tRLDM
tRHDM
D15-D6, D0,
AD5-AD1
Address
Defined Data
17
MB86611A
(3) 68-Series MPU Register Write Operation (Non-multiplex)
Value
Condition
Parameter
Symbol
Unit
Max.
Min.
10
20
20
10
20
10
40
40
0
Typ.
-
-
-
-
-
-
-
-
-
Address Setup Time
t
t
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
AWS
AWH
CWS
CWH
RWS
RWH
Address Hold Time
CS Setup Time
t
t
t
t
CS Hold Time
R/W Setup Time
R/W Hold Time
DS ”L” Level Pulse Width
Data Setup Time
Data Hold Time
t
DS
t
t
DWS
DWH
tAWS
tAWH
A5-A0
Address
tCWH
tCWS
CS
tRWS
tRWH
R/W
tDS
DS
tDWS
tDWH
D15-D6, D0,
AD5-AD1
Data
18
MB86611A
(4) 68-Series MPU Register Read Operation (Non-multiplex)
Value
Condition
Parameter
Symbol
Unit
Max.
Min.
10
20
20
10
20
10
40
-
Typ.
-
-
-
-
-
-
-
-
-
Address Setup Time
t
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ARS
ARH
CRS
CRH
Address Hold Time
CS Setup Time
t
t
t
-
CS Hold Time
-
R/W Setup Time
t
t
-
RWS
RWH
R/W Hold Time
-
DS ”L” Level Pulse Width
Data Output Defined Time
Data Output Disable Time
t
-
DS
t
40
-
RLD
RHD
t
5
tARS
tARH
A5-A0
Address
tCRH
tCRS
CS
tRWS
tRWH
R/W
tDS
DS
tRLD
tRHD
D15-D6, D0,
AD5-AD1
Defined Data
19
MB86611A
(5) 80-Series MPU Register Write Operation (Multiplex)
Value
Condition
Parameter
Symbol
Unit
Max.
Min.
10
10
20
10
15
15
40
40
0
Typ.
-
-
-
-
-
-
-
-
-
-
Address Setup Time
t
t
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AWSM
AWHM
CWSM
CWHM
Address Hold Time
CS Setup Time
t
t
CS Hold Time
ALE ”H” Level Pulse Width
ALE Falling → WR Falling Time
WR ”L” Level Pulse Width
Data Setup Time
t
ALE
t
t
DWD
WRM
DWSM
DWHM
t
t
Data Hold Time
t
20
WR Rising → ALE Rising Time
LWD
tCWSM
tCWHM
CS
tALE
tDWD
tLWD
ALE
WR
tWRM
tAWSM
tAWHM
tDWSM
tDWHM
D15-D6, D0,
AD5-AD1
Address
Data
20
MB86611A
(6) 80-Series MPU Register Read Operation (Multiplex)
Value
Condition
Parameter
Symbol
Unit
Max.
Min.
10
10
20
10
15
15
40
-
Typ.
-
-
-
-
-
-
-
-
-
-
Address Setup Time
t
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ARSM
ARHM
CRSM
CRHM
Address Hold Time
t
t
t
CS Setup Time
-
CS Hold Time
-
ALE ”H” Level Pulse Width
ALE Falling → RD Falling Time
RD ”L” Level Pulse Width
Data Output Defined Time
Data Output Disable Time
RD Rising → ALE Rising Time
t
-
ALE
t
-
DRD
t
-
RDM
RLDM
RHDM
t
40
-
t
5
t
20
-
LRD
tCRSM
tCRHM
CS
tALE
tDRD
tLRD
ALE
RD
tRDM
tARSM
tARHM
tRLDM
tRHDM
D15-D6, D0,
AD5-AD1
Address
Defined Data
21
MB86611A
(7) 80-Series MPU Register Write Operation (Non-multiplex)
Value
Condition
Parameter
Symbol
Unit
Max.
Min.
10
20
20
10
40
40
0
Typ.
-
-
-
-
-
-
-
Address Setup Time
t
t
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
AWS
AWH
CWS
CWH
Address Hold Time
CS Setup Time
t
t
CS Hold Time
WR ”L” Level Pulse Width
Data Setup Time
Data Hold Time
t
WR
t
t
DWS
DWH
tAWH
tAWS
A5-A0
Address
tCWS
tCWH
CS
tWR
WR
tDWS
tDWH
D15-D6, D0,
AD5-AD1
Data
22
MB86611A
(8) 80-Series MPU Register Read Operation (Non-multiplex)
Value
Condition
Parameter
Symbol
Unit
Max.
Min.
10
20
20
10
40
-
Typ.
-
-
-
-
-
-
-
Address Setup Time
t
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ARS
ARH
CRS
CRH
Address Hold Time
CS Setup Time
t
t
t
-
CS Hold Time
-
RD ”L” Level Pulse Width
Data Output Defined Time
Data Output Disable Time
t
-
RD
t
40
-
RLD
RHD
t
5
tARH
tARS
A5-A0
Address
tCRS
tCRH
CS
RD
tRD
tRLD
tRHD
D15-D6, D0,
AD5-AD1
Defined Data
23
MB86611A
(9) INT Signal Timing
Value
Typ.
-
Condition
Parameter
Symbol
Unit
Max.
Min.
-
INT Read out → INT Signal Negation
t
100
-
ns
INTD
This AC timing is applicable to only when the last data is read out from the interrupt register. The other timing specifications for read operation follow the
specification for each operation mode.
RD,
DS
tINTD
INT
24
MB86611A
DMA ACCESS
(1) 68-Series DMA Write Operation
Value
Condition
Parameter
Symbol
Unit
Max.
Min.
0
Typ.
-
-
-
-
-
-
-
-
-
-
DREQ ”H” → DACK ”L”
DS ”H” → DREQ ”L”
DACK Setup Time
t
t
-
-
-
-
-
-
-
-
-
-
-
30
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DHAL
-
DHDL
DAWS
t
t
20
0
-
DACK Hold Time
DAWH
DRWS
t
t
20
10
40
30
30
0
-
R/W Setup Time
-
R/W Hold Time
DRWH
t
-
DS ”L” Level Pulse Width
DS ”H” Level Pulse Width
Input Data Setup Time
Input Data Hold Time
DDS
t
-
DDSH
DDWS
t
t
-
-
DDWH
tDHAL
tDHDL
DREQ
DACK
tDAWS
tDAWH
tDRWS
tDRWH
R/W
DS
tDDS
tDDSH
tDDWS
tDDWH
D15-D6, D0,
AD5-AD1
Data
Data
25
MB86611A
(2) 68-Series DMA Read Operation
Value
Condition
Parameter
Symbol
Unit
Max.
Min.
0
Typ.
-
-
-
-
-
-
-
-
-
-
DREQ ”H” → DACK ”L”
DS ”H” → DREQ ”L”
DACK Setup Time
t
t
-
-
-
-
-
-
-
-
-
-
-
30
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DHAL
-
DHDL
DARS
DARH
t
t
20
0
-
DACK Hold Time
t
t
20
10
40
30
-
-
R/W Setup Time
DRWS
-
R/W Hold Time
DRWH
t
-
DS ”L” Level Pulse Width
DS ”H” Level Pulse Width
Data Output Defined Time
Data Output Disable Time
DDS
t
-
DDSH
t
40
-
DRLD
DRHD
t
5
tDHAL
tDHDL
DREQ
DACK
tDARS
tDARH
tDRWS
tDRWH
R/W
DS
tDDS
tDDSH
tDRLD
tDRHD
D15-D6, D0,
AD5-AD1
Defined Data
Defined Data
26
MB86611A
(3) 80-Series DMA Write Operation
Value
Condition
Parameter
Symbol
Unit
Max.
Min.
0
Typ.
-
-
-
-
-
-
-
-
DREQ ”H” → DACK ”L”
WR ”H” → DREQ ”L”
DACK Setup Time
t
t
-
-
-
-
-
-
-
-
-
30
-
ns
ns
ns
ns
ns
ns
ns
ns
DHAL
-
DHDL
DAWS
t
t
20
0
-
DACK Hold Time
DAWH
t
40
30
30
0
-
WR ”L” Level Pulse Width
WR ”H” Level Pulse Width
Input Data Setup Time
Input Data Hold Time
DWR
t
-
DWRH
t
-
DDWS
t
-
DDWH
tDHAL
tDHDL
DREQ
DACK
tDAWS
tDAWH
tDWR
tDWRH
WR
tDDWS
tDDWH
D15-D6, D0,
AD5-AD1
Data
Data
27
MB86611A
(4) 80-Series DMA Read Operation
Value
Condition
Parameter
Symbol
Unit
Max.
Min.
0
Typ.
-
-
-
-
-
-
-
-
DREQ ”H” → DACK ”L”
RD ”H” → DREQ ”L”
DACK Setup Time
t
t
-
-
-
-
-
-
-
-
-
30
-
ns
ns
ns
ns
ns
ns
ns
ns
DHAL
-
DHDL
DARS
DARH
t
t
20
0
-
DACK Hold Time
t
40
30
-
-
RD ”L” Level Pulse Width
RD ”H” Level Pulse Width
Data Output Defined Time
Data Output Disable Time
DRD
t
-
DRDH
t
40
-
DRLD
DRHD
t
5
tDHAL
tDHDL
DREQ
DACK
tDARS
tDARH
tDRD
tDRDH
RD
tDRLD
tDRHD
D15-D6, D0,
AD5-AD1
Defined Data
Defined Data
28
MB86611A
ISOCHRONOUS INTERFACE
(1) ICLK Timing
Value
Parameter
Symbol
Unit
Condition
Max.
Min.
4
Typ.
Clock Frequency
f
IC
-
-
-
-
-
-
-
-
-
-
-
-
16
250
-
MHz
ns
Clock Cycle Time
Clock Pulse ”H” Width
Clock Pulse ”L” Width
Clock Rising Time
Clock Falling Time
t
t
62.5
20
20
-
ICLK
ICLH
ns
t
-
ns
ICLL
t
7
ns
ICR
t
-
7
ns
ICF
tICLK
tICLH
tICR
tICF
0.65Vdd
0.25Vdd
ICLK
tICLL
29
MB86611A
(2) Transmit Timing
Xmit Activation
Value
Condition
Parameter
Symbol
Unit
Max.
t +125 ns
ICLK
Min.
-
Typ.
-
-
-
-
-
-
IDIR Falling → ILWRE Falling Time
ICLK Rising → IV Falling Time
ILWRE Falling → IV Falling Time
IV Setup Time
t
-
-
-
-
-
-
SDIR
t
-
40
ns
ns
ns
ns
ns
SIDIR
t
0
-
ILIV
t
40
20
0
-
-
-
SIV
t
Data Setup Time
SD
t
Data Hold Time
HD
ICLK
IDIR
tSIDIR
tSDIR
ILWRE
IV
tILIV
tSIV
tSD
tHD
ID7-ID
0
1
2
3
30
MB86611A
Xmit Termination
Value
Condition
Parameter
Symbol
Unit
Max.
Min.
Typ.
-
-
-
-
IV Rising → IDIR Rising Time
IDIR Rising → ILWRE Rising Time
ICLK Rising → ILWRE Rising Time
IDIR Rising → IDIR Falling Time
t
0
-
-
-
-
-
ns
+40 ns
ns
HDIR
t
-
-
1t
DWR
ICLK
t
40
SWDIR
t
250
-
µs
DIRH
ICLK
IDIR
tSWDIR
tDWR
ILWRE
IV
tHDIR
tDIRH
ID7-ID0
N-1
N
N+1
31
MB86611A
Transmission to IV Temporary Negation
Value
Condition
Parameter
Symbol
Unit
Max.
Min.
0
Typ.
-
-
-
IV Hold Time
t
-
-
-
t
-40
ns
ns
ns
HIV
ICLK
Data Setup Time
Data Hold Time
t
20
0
-
SD
t
-
HD
ICLK
IDIR
ILWRE
IV
tHIV
tSD
tHD
ID7-ID0
N-1
N
N+1
32
MB86611A
ILWRE Negation during Transmission (at Bus Reset detected or FIFO-full state)
Value
Condition
Parameter
Symbol
Unit
Max.
Min.
Typ.
-
-
-
ICLK Rising → ILWRE Rising Time
ILWRE Rising → IV Rising Time
ICLK Rising → ILWRE Falling Time
t
-
-
-
-
40
ns
HWRL
t
t
2t
-40 ns
ns
REMIV
ICLK
ICLK
t
-
40
HWRH
Because the MB86611A pauses the write operation for transmit data under the following conditions, it negates the ILWRE signal.
1) When the transmit Isochronous-FIFO is full. (ILWRE is negated synchronized with one ICLK before the FIFO is full.)
2) When bus reset is detected. (After the bus reset detected, ILWRE is negated synchronized with one ICLK before fetching 1 packet into the FIFO.)
Condition to resume the transmit: When 1 packet is transmitted.
ICLK
IDIR
tHWRL
tHWRH
ILWRE
IV
tREMIV
ID7-ID0
valid
valid
valid
ignore
33
MB86611A
Switch to Transmission during Receive
Value
Condition
Parameter
Symbol
Unit
Max.
+40
Min.
Typ.
-
-
IDIR Falling → ILWRE Rising Time
IDIR Falling → ILWRE Falling Time
t
-
-
-
-
t
ns
DLWRH
ICLK
t
2t
ICLK
+40 ns
DLWRL
ICLK
IDIR
tDLWRL
tDLWRH
ILWRE
34
MB86611A
FP Input Timing
Value
Condition
Parameter
Symbol
Unit
Max.
Min.
100
125
80
Typ.
-
-
-
FP ”L” Level Pulse Width
t
-
-
-
-
-
ns
µs
ns
FPL
FP ”H” Level Pulse Width
t
t
FPH
150
FP ”L” Detected → CTR Value Fetch
CTR
tFPL
tFPH
FP
35
MB86611A
(2) Receive Timing
Rcv Activation
Value
Condition
Parameter
Symbol
Unit
Max.
40
-
Min.
Typ.
-
-
-
-
-
ICLK Rising → ILWRE Falling Time
IV Setup Time
t
-
40
-
-
-
-
-
-
ns
ns
ns
ns
ns
WREH
t
SIV
t
DZ
40
40
40
Data Output Defined Time
Data Output Disable Time
IV Falling → ICRCE Falling Time *
t
D
10
-
t
ERRL
* : ICRCE signal is output only when there is an error on the received data.
ICLK
IDIR
tWREH
ILWRE
tSIV
IV
tD
1
tDZ
ID7-ID
Hi-Z
0
2
3
tERRL
ICRCE
36
MB86611A
Rcv Termination
Value
Condition
Parameter
Symbol
Unit
Max.
Min.
Typ.
-
-
-
-
ICLK Rising → ILWRE Rising Time
Data Output Disable Time
t
-
-
-
-
-
40
50
-
ns
ns
ns
ns
WREL
t
ZD
0
t
6t
ILWRE Negate Time *1
WREH
ICLK
t
-
40
IV Rising → ICRCE Rising Time *2
ERRH
*1: MB86611A negates the ILWRE signal once every time 1 packet is read out.
*2 : ICRCE signal is output only when there is an error on the received data.
ICLK
IDIR
tWREL
tWREH
ILWRE
IV
tZD
ID7-ID
0
N-2
N-1
N
Hi-Z
tERRH
ICRCE
37
MB86611A
Receive to IV Temporary Negation
Value
Condition
Parameter
Symbol
Unit
Max.
-
Min.
Typ.
-
-
-
IV Rising → ICLK Rising Time
IV Rising → ICRCE Rising Time
IV Falling → ICRCE Falling Time
t
40
-
-
-
-
ns
ns
ns
HIV
t
40
40
ERRH
t
-
ERRL
ICLK
IDIR
ILWRE
tHIV
IV
ID7-ID0
N-3
N-2
tERRH
Hi-Z
N-1
tERRL
ICRCE
38
MB86611A
FP Signal Output Timing
Value
Condition
Parameter
Symbol
Unit
Max.
Min.
Typ.
-
-
-
IDIR Falling → FP Output Enable
FP ”L” Level Pulse Width
t
-
600
-
-
-
-
40
730
40
ns
ns
ns
ZFP
t
FPW
t
Timestamp Match → FP Output
DTMP
IDIR
tFPW
tZFP
FP
Hi-Z
39
MB86611A
Recommended Connection Diagram for 1394 Port (Example)
TPBIAS
1µF
55Ω
Cable
TPA
TPB
55Ω
Cable
Cable
TPA
TPB
TPB
TPA
55Ω
TPB
Cable
TPA
55Ω
5kΩ
250pF
RO
4.8kΩ ±1%
40
MB86611A
Recommended Connection Diagram for On-chip PLL Loop Filter (Example)
1kΩ ±5%
VCOIN
CHPO
820Ω ±5%
1000pF±5%
100pF±5%
ROP
4.8kΩ ±1%
Recommended Connection Diagram for Crystal Oscillator (Example)
1MΩ ±5%
X1
X0
20pF±10%
20pF±10%
41
MB86611A
Notes on Use
Current Leak at the Power-Off
At the device powered-off, when the TP signal is biassed from the counterpart device via the 1394 cable, it is possible to
flow overcurrent on the device via the TPB driver’s current lines. Therefore, load components (14kΩ or greater is rec-
ommended) should be connected with the VDD lines.
TPBIAS
55Ω
VDD should be con-
nected with GND line
when power is off.
TPB
TPA
TPA
55Ω
TPB
55Ω
55Ω
5kΩ
250pF
<Own Device (with MB86611A)>
<Counterpart Device>
42
LOW PROFILE SHRINK QUAD FLAT L-LEADED PACKAGE
100 PIN PLASTIC
FPT-100P-M05
EIAJ code : QFP100-P-1414-1
Lead pitch
0.50mm
14 × 14mm
Gullwing
100-pin plastic LQFP
Package width ×
package length
Lead shape
Sealing method
Plastic mold
(FPT-100P-M05)
100-pin plastic LQFP
(FPT-100P-M05)
1.50−+00..2100
16.00±0.20(.630±.008)SQ
(Mounting height)
.059 −+..000048
75
51
14.00±0.10(.551±.004)SQ
76
50
12.00
(.472)
REF
15.00
(.591)
NOM
Details of "A" part
0.15(.006)
INDEX
0.15(.006)
100
26
0.15(.006)MAX
0.40(.016)MAX
"B"
1
25
LEAD No.
"A"
0.50(.0197)TYP
0.18−+00..0038
0.127 +−00..0025
.005−+..000012
M
Details of "B" part
0.08(.003)
.007 −+..000013
0.10±0.10
(.004±.004)
(STAND OFF)
0.50±0.20(.020±.008)
0.10(.004)
0~10˚
C
Dimensions in mm (inches).
相关型号：
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