MB88141APFV [FUJITSU]
D/A Converter for Digital Tuning (Compatible with I2C Bus); D / A转换器,用于数字调谐(兼容I2C总线)![MB88141APFV](http://pdffile.icpdf.com/pdf1/p00045/img/icpdf/MB88141A_234184_icpdf.jpg)
型号: | MB88141APFV |
厂家: | ![]() |
描述: | D/A Converter for Digital Tuning (Compatible with I2C Bus) |
文件: | 总22页 (文件大小:264K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-13213-1E
Linear IC Converter
CMOS
D/A Converter for Digital Tuning
(Compatible with I2C Bus)
MB88141A
■ DESCRIPTION
The FUJITSU MB88141A is an 8-bit D/A converter with 12 built−in channels.
The 12 analog output channels have built-in OP Amps, providing large current drive capability.
Data input is compatible with I2C specifications, and is controlled by two control lines.
The built-in I/O expander function allows the MB88141A to be controlled by devices incompatible with I2C bus
specifications (provides conversion between I2C serial and 8- or 4-bit parallel I/O).
The MB88141A is ideal for replacing electronic knob or pre-set variable resistance tuning devices.
■ FEATURES
• Ultra-low power consumption (0.9 mW/channel Typ.)
• Ultra-compact package
• Built-in 12-channel R-2R type 8-bit D/A converter
• Built-in analog output amplifier (maximum sink current 1.0 mA, maximum source current 1.0 mA)
• Analog output range 0 V to VCC
(Continued)
■ PACKAGES
24-pin plastic DIP
24-pin plastic SOP
24-pin plastic SSOP
(DIP-24P-M02)
(FPT-24P-M01)
(FPT-24P-M03)
“Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use these
components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined
by Philips.”
MB88141A
(Continued)
• 5 V single power supply
• Power supply/GND for MCU interface and OP Amp is separate from power supply/GND for D/A converter
• Power supply for D/A converter is divided into two systems for VDDI/VSSI (AO1 to AO4) and VDD2/VSS2 (AO5 to
AO12) , allowing separate level settings for each system
• Compatible with serial data input, I2C specifications
• Built-in I/O expander function (converts between I2C serial and 8-or 4-bit parallel)
• CMOS process
• Packages : DIP 24-pin, SOP 24-pin, SSOP 24-pin
2
MB88141A
■ PIN ASSIGNMENT
(Top View)
AO1
AO2
1
24
23
22
21
20
19
18
17
16
15
14
13
GND
VSS1
VDD1
SDA
SCL
2
AO3
3
AO4
4
AO5/D7
AO6/D6
AO7/D5
AO8/D4
AO9/D3
AO10/D2
AO11/D1
AO12/D0
5
6
MOD
CS2
7
8
CS1
9
CS0
10
11
12
VDD2
VSS2
VCC
(DIP-24P-M02)
(FPT-24P-M01)
(FPT-24P-M03)
3
MB88141A
■ PIN DESCRIPTION
Pin no.
21
Symbol
SDA
Circuit Type
I/O
I/O
I
Description
I2C bus data input/output pin (hysteresis input).
Outputs the acknowledge signal.
C
B
20
SCL
I2C bus shift clock input pin (hysteresis input) .
D/A converter and I/O expander mode switching pin. *1, *2
Input “L” to operate as a D/A converter, “H” to operate as I/O
expander and D/A converter.
19
MOD
A
A
I
I
16
17
18
CS0
CS1
CS2
These pins set the lower 3 bits of the slave address. *1
This allows up to eight MB88141A chips to be used on the same
bus line.
1
2
3
4
AO1
AO2
AO3
AO4
D
E
O
8-bit D/A outputs with OP Amp. *2
5
6
7
8
9
10
11
12
AO5/D7
AO6/D6
AO7/D5
AO8/D4
AO9/D3
AO10/D2
AO11/D1
AO12/D0
8-bit D/A outputs with OP Amp. *2
I/O In I/O expander operation, these pins function as parallel data in-
put/output pins.
13
24
22
23
15
14
VCC
GND
Power supply
GND
Power supply pin for digital circuits and OP Amp.
GND pin for digital circuits and OP Amp.
VDD1
VSS1
VDD2
VSS2
Power supply
Power supply
Power supply
Power supply
Reference power supply pin for D/A converter (H) . AO1 to AO4.
Reference power supply pin for D/A converter (L) . AO1 to AO4.
Reference power supply pin for D/A converter (H) . AO5 to AO12.
Reference power supply pin for D/A converter (L) . AO5 to AO12.
*1: The MOD and CS0-CS2 pins should be used with fixed level input.
*2: When using the I/O expander function together with the D/A converter function, take care that D/A converter
output precision is within a range that will not affect overall system operation.
4
MB88141A
■ BLOCK DIAGRAM
SDA
SCL
CS2
I2C Bus Interface
D/A & I/O Control Logic
CS1
CS0
MOD
D0
D7
D0
D7
D0
D7
D0
D7
8-bit latch
8-bit latch
R-2R
8-bit latch
R-2R
8-bit latch
1 ch
4 ch
5 ch
12 ch
VDD2
VSS2
VDD1
VSS1
R-2R
ladder circuit
R-2R
ladder circuit
ladder circuit
ladder circuit
−
+
−
+
−
+
−
+
8
VCC
GND
AO1
AO4
D7/AO5
D0/AO12
5
MB88141A
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
Pch Tr
A
B
C
D
Input dedicated pin
Nch Tr
Digital input
Pch Tr
Input dedicated pin
• I2C bus pin
• Hysteresis input
Nch Tr
Digital input
Pch Tr
Input/output pin
• I2C bus pin
• Hysteresis input
• N-ch open drain output
Digital output
Digital input
Nch Tr
Pch Tr
Nch Tr
Analog output
Analog output pin
Analog output
Analog feedback
(Continued)
6
MB88141A
(Continued)
Type
Circuit
Remarks
Pch Tr
Analog/digital
output
Analog/digital
output
E
Analog/digital input/output pin
Nch Tr
Analog feedback
Digital input
Mode control
Note : Circuit types B and C are I2C bus pins. Caution should be taken in using these pins because when the VCC
power is off current from the I2C bus line power supply VCCS can enter the VCC side of the device power
supply.
VCCS
VCCS
SDA (I2C bus line)
SCL (I2C bus line)
VCC
VCC
VCC
MB88141A
7
MB88141A
■ DATA CONFIGURATION
The MB88141A has the following data configuration the two operating modes (D/A converter (12-channel) and
I/O expander plus D/A converter), selected by the MOD pin.
1. For D/A Converter (12-channel) Operation (MOD = “L”)
(1) I2C Bus Format
First S6
S0 R/W
0
C7
C0
D7
D0
Last
P
Channel selection
(8 bits)
S
Slave address (7 bits)
A
A
D/A data (8 bits)
A
: Sent from master device
: “Start” condition
: Sent from MB88141A (slave device)
: “Stop” condition
S
P
A
: “Acknowledge” output
(2) Slave Address Comparison (7 bits)
Slave address input (7 bits)
Internally fixed
Externally set
S6 S5 S4 S3 S2 S1 S0
CS6 CS5 CS4 CS3 CS2 CS1 CS0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
=
=
=
=
=
=
=
=
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Address comparison: Operates only for devices whose own slave address (internally fixed CS6 to CS3 and
externally set CS2 to CS0) matches the slave address input value.
(3) R/W Selection (1 bit)
Fixed at “0” (the D/A converter performs write operations only) .
8
MB88141A
(4) Channel Selection (8 bits)
C7 C6 C5 C4 C3 C2 C1 C0
Channel select
All channels selected *1
AO1 selected
×
×
×
×
×
×
×
×
0
0
0
0
0
0
0
1
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
AO12 selected
Don’t Care
Don’t Care
All channels selected *2
× : Don’t Care
*1: The 1 byte of data following the channel selection is set on all channels (all channels set to same data value) .
Slave address (7 bits) X X X X 0 0 0 0 D/A data (8 bits)
S
0
A
A
A
P
*2: The 12 bytes of data following the channel selection are set on all channels (all channels set to separate data
values) .
Slave
address
S
0
A
X X X X1 1 1 1
A
AO1 data
A
AO12 data
A
P
: Sent from master device
: “Start” condition
: Sent from MB88141A (slave device)
: “Stop” condition
S
P
A
: “Acknowledge” output
Note: Setting will repeat, continuing in order from ch1, until the start and stop conditions are acknowledged.
(5) D/A Data (8 bits)
D7 D6 D5 D4 D3 D2 D1 D0
D/A output
VSS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
(VREF / 256) × 1 + VSS
(VREF / 256) × 2 + VSS
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
(VREF / 256) × 254 + VSS
(VREF / 256) × 255 + VSS
Note: VREF = VDD − VSS
9
MB88141A
2. For D/A Converter + I/O Expander Operation (MOD = “H”)
(1) I2C Bus Format
First S6
S0 R/W
1
D7
D0
C0
Last
P
S
Slave address (7 bits)
A
A
Digital data (8 bits)
A
A
First S6
S0 R/W
C7
D7
D0
Last
P
Channel selection
(8 bits)
S
Slave address (7 bits)
0
Digital data (8 bits)
A
: Sent from master device
: “Start” condition
: Sent from MB88141A (slave device)
: “Stop” condition
S
P
A
: “Acknowledge” output
(2) Slave Address Comparison (7 bits)
Slave address comparison is the same as for D/A converter (12-channel) operation (see “1. (2) “Slave Address
Comparison”), with the exception that the CS2 setting determines the number of D/A converter channels and
the number of I/O expander bits.
CS2
0
D/A converter
I/O expander
8 bits (D7 to D0)
4 bits (D3 to D0)
4 channels (AO1 to AO4)
8 channels (AO1 to AO8)
1
When CS2 = “1” is selected, the upper 4 bits (D7 to D4) of write operations (I2C bus to parallel interface) are
ignored, and the upper 4 bits of read operations (parallel interface to I2C bus) are output at “0” (low) .
(3) R/W Selection (1 bit)
R/W
0
I/O expander operation
D/A converter operation
I2C bus input → parallel data output
Parallel data input → I2C bus output
I2C bus input → analog output
1
10
MB88141A
(4) Channel Selection (8 bits)
C7 C6 C5 C4 C3 C2 C1 C0
Channel select
I/O expander operation
AO1 selected
×
×
×
×
×
×
×
×
0
0
0
0
0
0
0
1
×
×
×
×
×
×
×
×
0
0
1
1
0
0
0
1
AO4 selected
Don’t care (AO5 selected)
×
×
×
×
×
×
×
×
1
1
0
0
0
0
0
1
Don’t care (AO8 selected)
Don’t Care
×
×
×
×
×
×
×
×
1
1
1
1
1
1
0
1
Don’t Care
I/O expander continuous operation
( ): When using D/A converter 8 channel, I/O expander 4 bit operation.
× : Don’t Care
(5) D/A Data (8 bits)
Same as “1 (5) D/A Data (8 bits)”.
(6) I/O Expander Continuous Operation
I2C bus input → parallel data output
Slave
address
S
0
A
X X X X1 1 1 1
A
Digital data
A
Digital data
A
A
P
P
Note: In continuous operation, operation continues until start and stop conditions are acknowledged.
Parallel data input → I2C bus output
Slave
address
S
S
1
A
Digital data
A
Digital data
A
Digital data
: Sent from master device
: “Start” condition
: Sent from MB88141A (slave device)
: “Stop” condition
P
A
: “Acknowledge” output
11
MB88141A
■ TIMING DIAGRAM (I2C BUS SPECIFICATIONS)
"Start"
condition
Data
change
"Acknowledge"
response
"Acknowledge"
response
"Acknowledge" "Stop"
response
condition
SDA
input
S6 S5 S4 S3 S2
S1 S0 R/W ACK C7 C6 C5
C0 ACK D7 D6
D0 ACK
SCL
input
1
2
3
4
5
6
7
8
9
10
11
12
17
18
19
20
26
27
Delay
AO1
to
AO12
Analog output
HiZ state
Delay
Digital output
D0 to D7
output
Load data
Load data
D7 D6
D0 to D7
input
HiZ input
HiZ state
DX
"Acknowledge"
response
SDA
output
ACK D7 D6 D5
D0
D0
D7
Note:
• The SDA input acknowledge response (ACK) is an output signal from the MB88141A.
• The D0-D7 input and output timing represent the timing of switching to write and read operations respectively.
Also, D0-D7 input remains in HiZ state between the end of a read operation and the acknowledgment of the
next I/O write signal.
■ ANALOG OUTPUT VOLTAGE RANGE
R-2R ladder circuit
VDD1&VDD2
Operating Amp circuit
VCC ( = VDD1, VDD2)
Analog output range
VSS1&VSS2
GND ( = VSS1, VSS2)
12
MB88141A
■ ABSOLUTE MAXIMUM RATINGS
Rating
Parameter
Symbol
Conditions
Unit
Min.
−0.3
−0.3
−0.3
−0.3
−0.3
Max.
VCC
VDD
VSS
VIN
+7.0 *
+7.0 *
+7.0 *
V
V
Supply voltage
With reference to GND,
at Ta = +25 °C
V
Input voltage
VCC + 0.3
VCC + 0.3
250
V
Output voltage
VOUT
PD
V
Power consumption
Operating temperature
Storage temperature
mW
°C
°C
Ta
−20
−55
+85
Tstg
+120
*: VCC ≥ VDD1 ≥ VSS1, VCC ≥ VDD2 ≥ VSS2
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Conditions
Unit
Min.
Typ.
5.00
0
Max.
VCC
GND
VDD1
VSS1
VDD2
VSS2
IAL
4.50
5.50
V
V
Supply voltage 1
2.00
0.00
2.00
0.00
0
VCC
3.50
VCC
V
VCC ≥ VDD1 > VSS1
VDD1 − VSS1 ≥ 2.0 V
Supply voltage 2
Supply voltage 3
Analog output current
V
V
VCC ≥ VDD2 > VSS2
VDD2 − VSS2 ≥ 2.0 V
3.50
1.00
1.00
1.00
#FF
+85
V
Source current
Sink current
mA
mA
µF
IAH
0
Oscillator limit output capacitance
Digital data setting range
Operating temperature
COL
#00
Ta
−20
°C
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
13
MB88141A
■ ELECTRICAL CHARACTERISTICS
1. DC Characteristics
(1) Digital Circuits
(VCC = +5 V ± 10%, GND = 0 V, Ta = −20 °C to +85 °C)
Value
Parameter
Supply voltage
Symbol
Pin name
Conditions
Unit
Min.
Typ.
Max.
VCC
ICC
4.50
5.00
5.50
V
VCC
SCL = 400 kHz,
no load
Supply current
1.00
3.70
mA
Input leak current
IILK
VIL
SDA, SCL
CS0, CS1
CS2, MOD
D0 to D7
VIN = 0 to VCC
−10
0
+10
0.30 VCC
VCC
µA
V
“L” level input voltage
“H” level input voltage
Input hysteresis width
“H” level output voltage
VIH
0.70 VCC
0.05 VCC
VCC − 0.4
V
VHYS
VOH
VOL1
VOL2
VOL3
SDA, SCL
V
IOH = −400 µA
IOL = 2.5 mA
IOL = 3.0 mA
IOL = 6.0 mA
D0 to D7
V
V
0.40
0.40
0.60
“L” level output voltage
SDA
(2) Analog Circuits 1
(VCC = +5 V ± 10%, GND = 0 V, Ta = −20 °C to +85 °C)
Value
Parameter
Symbol Pinname
Conditions
Unit
Min.
Typ.
Max.
2.50
VCC
No load
IDD = IDD1 + IDD2
Current consumption
IDD
VDD
VSS
1.20
mA
VDD1,
VDD2
2.0
VDD1 − VSS1 ≥ 2.0 V
VDD2 − VSS2 ≥ 2.0 V
Analog voltage
V
VSS1,
VSS2
GND
3.5
Resolution
Res
Rem
LE
8
8
bit
bit
AO1
to
AO12
No load
VDD1,VDD2 ≤ VCC − 0.1 V
VSS1,VSS2 ≥ 0.1 V
Monotonic increase
Non-linearity error
Differential linearity error
−1.5
−1.0
+1.5
+1.0
LSB
LSB
DLE
14
MB88141A
Non-linearity error :
Error in the input/output curve with respect to a straight line connecting output voltage at “00” and output voltage
at “FF” levels.
Differential linearity error :
Deviation from ideal voltage with respect to a 1-bit increase in digital value.
Analog output
Ideal linearity
VAOH
Non-linearity error
VAOL
Digital setting
#00
#FF
Note: VAOH and VDD, as well as VAOL and Vss are not necessarily the same values.
(3) Analog Circuits 2
(VCC = VDD1 = VDD2 = +5 V, GND = VSS1 = VSS2 = 0 V, Ta = −20 °C to +85 °C)
Value
Typ.
Symbol Pin name
Parameter
Conditions
Unit
Min.
VSS
Max.
VSS + 0.1
VSS + 0.2
VSS + 0.2
VSS + 0.3
VSS + 0.3
VDD
Output minimum voltage 1
Output minimum voltage 2
Output minimum voltage 3
Output minimum voltage 4
Output minimum voltage 5
Output maximum voltage1
Output maximum voltage2
Output maximum voltage3
Output maximum voltage4
Output maximum voltage5
VAOL1
VAOL2
VAOL3
VAOL4
IAL = 0 µA
V
V
V
V
V
V
V
V
V
V
IAL = 500 µA
IAH = 500 µA
IAL = 1.0 mA
IAH = 1.0 mA
IAL = 0 µA
VSS − 0.2
VSS
VSS
VSS
Digital data
“00”
VSS − 0.3
VSS
AO1
to
AO12
VAOL5
VAOH1
VDD − 0.1
VDD − 0.2
VDD − 0.2
VDD − 0.3
VDD − 0.3
VAOH2
VAOH3
VAOH4
VAOH5
IAL = 500 µA
IAH = 500 µA
IAL = 1.0 mA
IAH = 1.0 mA
VDD
Digital data
“FF”
VDD
VDD
VDD + 0.2
VDD
VDD + 0.3
15
MB88141A
2. AC Characteristics
Parameter
Value
High-speed mode
Con-
dition
Symbol
Standard mode
Unit
Min.
Max.
Min.
Max.
SCL clock frequency
fSCL
0
100
0
400
kHz
Bus free time between “stop” condition
and “start” condition
tBUF
4.7
1.3
Hold time (resend) “start” condition.
The first clock pulse is generated after
this interval.
tHD ; STA
4.0
0.6
µs
SCL clock low hold time
SCL clock high hold time
Resend “start” condition setup time
Data hold time
tLOW
tHIGH
4.7
4.0
4.7
0
1.3
0.6
0.6
0
tSU ; STA
tHD ; DAT
tSU ; DAT
tR
0.9
Data setup time
250
100
SDA and SCL signal fall time
SDA and SCL signal rise time
“Stop” condition setup time
1000
300
20 + 0.1 Cb
20 + 0.1 Cb
0.6
300
300
ns
tF
tSU ; STO
4.0
µs
Pulse width of spike suppressed by input
filter
tSP
0
50
Output fall time when Sink current 3mA
bus capacitance is
250
20 + 0.1 Cb
250
ns
tOF
between 10 pF and
400 pF
Sink current 6mA
20 + 0.1 Cb
250
I2C bus line capacitance load
Cb
400
100
300
400
100
300
pF
D/A
Analog output settling time
tDL ; AO
tDL ; DO
tDZ ; DI
tSU ; DI
tHD ; DI
*1
*2
*3
µs
Digital output delay time
Input open time
200
250
0.9
200
100
0.9
ns
I/O
expander
Digital input setup time
Digital input hold time
µs
*1: Load condition 1
*2: Load condition 2
Measurement point
Measurement point
DUT
DUT
RAL = 10 kΩ
CAL = 50 pF
CAL = 50 pF
*3 : The I/O expander input open time value applies to a read operation following an I/O write operation, or to an
I/O write operation following a read operation.
16
MB88141A
• Input/Output Timing
tBUF
tHD ; STA
Acknowl-
edge
SDA
SCL
Acknowl-
edge
tSU ; DAT
tHD ; DAT
tSP
tSU ; STA
tHD ; STA
P
S
9
18
Sr
P
tLOW
tHIGH
tR
tF
tSU ; STO
tDZ ; DI
tSU ; DI
tHD ; DI
D0
to
Digital input
D7
tDZ ; DI
tDL ; DO
D0
to
Digital input
Digital output
D7
tDL ; AO
AO1
to
AO12
90%
10%
Analog output
Note: The discrimination levels are 70% and 30% of VCC.
17
MB88141A
■ ORDERING INFORMATION
Part number
Package
Remarks
24-pin plastic DIP
(DIP-24P-M02)
MB88141AP
24-pin plastic SOP
(FPT-24P-M01)
MB88141APF
MB88141APFV
24-pin plastic SSOP
(FPT-24P-M03)
18
MB88141A
■ PACKAGE DIMENSIONS
24-pin plastic DIP
(DIP-24P-M02)
+0.20
+.008
30.20
–0.30 1.189 –.012
INDEX-1
13.55±0.25
(.533±.010)
INDEX-2
0.51(.020)MIN
4.96(.195)
MAX
3.00(.118)
MIN
0.25±0.05
(.010±.002)
+0.50
–0
+0.50
0.98
1.50
–0
0.45±0.08
(.018±.003)
.039 +–0.020
.059 +–0.020
15°MAX
15.24(.600)
1.27(.050)
MAX
2.54(.100)
TYP
TYP
C
1994 FUJITSU LIMITED D24015S-2C-3
Dimensions in mm (inches)
(Continued)
19
MB88141A
(Continued)
24-pin plastic SOP
(FPT-24P-M01)
2.25(.089)MAX
(Mounting height)
15.24 +–00..2205 .600 –+..000180
0.05(.002)MIN
(STAND OFF)
6.80 –+00..2400
5.30±0.30
(.209±.012) (.307±.016)
7.80±0.40
INDEX
.268 –+..000186
1.27(.050)
TYP
0.45±0.10
(.018±.004)
0.15 –+00..0025
0.50±0.20
(.020±.008)
M
Ø0.13(.005)
.006 +–..000012
Details of "A" part
0.20(.008)
"A"
0.50(.020)
0.10(.004)
13.97(.550)REF
0.18(.007)MAX
0.68(.027)MAX
C
2000 FUJITSU LIMITED F24007S-3C-5
Dimensions in mm (inches)
(Continued)
20
MB88141A
(Continued)
24-pin plastic SSOP
Note) * marked dimensions do not include resin residues.
(FPT-24P-M03)
1.25 –+00..1200
*
7.75±0.10(.305±.004)
(Mounting height)
.049 +–..000048
0.10(.004)
*
5.60±0.10
7.60±0.20
6.60(.260)
NOM
(.220±.004) (.299±.008)
INDEX
"A"
0.22 –+00..0150
0.15 –+00..0025
Details of "A" part
0.10±0.10(.004±.004)
0.65±0.12(.0256±.0047)
.009 +–..000024
.006 +–..000012
(STAND OFF)
7.15(.281)REF
0
10°
0.50±0.20
(.020±.008)
C
2000 FUJITSU LIMITED F24018S-2C-3
Dimensions in mm (inches)
21
MB88141A
FUJITSU LIMITED
For further information please contact:
Japan
All Rights Reserved.
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
Shinjuku Dai-Ichi Seimei Bldg. 7-1,
Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0721, Japan
Tel: +81-3-5322-3347
Fax: +81-3-5322-3386
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
http://edevice.fujitsu.com/
North and South America
FUJITSU MICROELECTRONICS, INC.
3545 North First Street,
San Jose, CA 95134-1804, U.S.A.
Tel: +1-408-922-9000
Fax: +1-408-922-9179
The contents of this document may not be reproduced or copied
without the permission of FUJITSU LIMITED.
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Mon. - Fri.: 7 am - 5 pm (PST)
Tel: +1-800-866-8608
FUJITSU semiconductor devices are intended for use in standard
applications (computers, office automation and other office
equipments, industrial, communications, and measurement
equipments, personal or household devices, etc.).
Fax: +1-408-922-9179
http://www.fujitsumicro.com/
CAUTION:
Europe
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or
where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters,
vehicle operating controls, medical devices for life support, etc.)
are requested to consult with FUJITSU sales representatives before
such use. The company will not be responsible for damages arising
from such use without prior approval.
FUJITSU MICROELECTRONICS EUROPE GmbH
Am Siebenstein 6-10,
D-63303 Dreieich-Buchschlag,
Germany
Tel: +49-6103-690-0
Fax: +49-6103-690-122
http://www.fujitsu-fme.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
#05-08, 151 Lorong Chuan,
New Tech Park,
Any semiconductor devices have inherently a certain rate of failure.
You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
Singapore 556741
Tel: +65-281-0770
Fax: +65-281-0220
http://www.fmap.com.sg/
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required for
export of those products from Japan.
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
1702 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Tel: +82-2-3484-7100
Fax: +82-2-3484-7111
F0101
FUJITSU LIMITED Printed in Japan
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MB88146AP
D/A Converter for Digital Tuning (12-channel, 8-bit, on-chip OP amp., low-voltage)
FUJITSU
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MB88146APFV
D/A Converter for Digital Tuning (12-channel, 8-bit, on-chip OP amp., low-voltage)
FUJITSU
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