MB88153-101 [FUJITSU]

Spread Spectrum Clock Generator; 扩频时钟发生器
MB88153-101
型号: MB88153-101
厂家: FUJITSU    FUJITSU
描述:

Spread Spectrum Clock Generator
扩频时钟发生器

时钟发生器
文件: 总19页 (文件大小:152K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
FUJITSU SEMICONDUCTOR  
DATA SHEET  
DS04-29118-2E  
Spread Spectrum Clock Generator  
MB88153  
DESCRIPTION  
MB88153 is a clock generator for EMI (Electro Magnetic Interference) reduction. The peak of unnecessary (EMI)  
can be attenuated by making the oscillation frequency slightly modulate periodically with the internal modulator.  
It corresponds to both of the center spread which modulates input frequency as Middle Centered and down spread  
which modulates so as not to exceed input frequency.  
FEATURE  
• Power down pin : 600 µA (Max) consumption current at power down  
• Input frequency : 16.6 MHz to 134 MHz  
• Output frequency : 16.6 MHz to 134 MHz (One-fold input frequency)  
• Modulation rate can select from 0.5%, 1.5% − 1.0% or 3.0%. (For center spread / down spread.)  
• Modulation clock output Duty : 40% to 60%  
• Modulation clock Cycle-Cycle Jitter : Less than 100 ps  
• Low current consumption by CMOS process : 4.0 mA (24 MHz : Typ-sample, no load)  
• Power supply voltage : 3.3 V 0.3 V  
• Operating temperature : 40 °C to +85 °C  
• Package : SOP 8-pin  
PACKAGE  
8-pin plastic SOP  
(FPT-8P-M02)  
MB88153  
PRODUCT LINEUP  
MB88153 has four kinds of modulation rate and modulation type (center/down spread).  
Product  
MB88153-100  
Modulation rate  
1.0%  
Modulation type  
Down  
MB88153-101  
MB88153-110  
MB88153-111  
3.0%  
0.5%  
1.5%  
Center  
PIN ASSIGNMENT  
TOP VIEW  
CKIN  
1
2
3
4
8
7
6
5
XPD  
VDD  
FREQ0  
FREQ1  
ENS  
MB88153  
V
SS  
CKOUT  
FPT-8P-M02  
PIN DESCRIPTION  
Pin name  
CKIN  
VDD  
I/O  
I
Pin no.  
Description  
1
2
3
Clock input pin  
Power supply voltage pin  
GND pin  
VSS  
Modulated clock output pin  
“L” output at power down  
CKOUT  
O
4
ENS  
I
I
I
5
6
7
Modulation enable setting pin  
Frequency setting pin  
FREQ1  
FREQ0  
Frequency setting pin (with pull-up resistor)  
Power down pin (with pull-up resistor)  
Power down at “L” input  
XPD  
I
8
2
MB88153  
I/O CIRCUIT TYPE  
Pin  
Circuit type  
Remarks  
• CMOS hysteresis input  
CKIN,  
ENS,  
FREQ1  
• CMOS hysteresis input with pull-up  
resistor 50 k(typ)  
50 k  
FREQ0,  
XPD  
• CMOS output  
• “L” output at power down  
CKOUT  
3
MB88153  
HANDLING DEVICES  
Preventing Latchup  
A latchup can occur if, on this device, (a) a voltage higher than VDD or a voltage lower than VSS is applied to an  
input or output pin or (b) a voltage higher than the rating is applied between VDD and VSS. The latchup, if it occurs,  
significantly increases the power supply current and may cause thermal destruction of an element. When you  
use this device, be very careful not to exceed the maximum rating.  
Handling unused pins  
Do not leave an unused input pin open, since it may cause a malfunction. Handle by, using a pull-up or  
pull-down resistor.  
Unused output pin should be opened.  
Power supply pins  
Please design connecting the power supply pin of this device by as low impedance as possible from the current  
supply source.  
We recommend connecting electrolytic capacitor (about 10 µF) and the ceramic capacitor (about 0.01 µF) in  
parallel between VSS and VDD near the device, as a bypass capacitor.  
Clock I/O circuit  
Noise near the CKIN pin may cause the device to malfunction. Design the printed circuit board so that the wiring  
for the clock input does not intersect any other wiring.  
Please pay attention so that an overshoot and an undershoot do not occur to an input clock of CKIN pin.  
Design the printed circuit board that surrounds the CKIN and CKOUT pins with ground.  
4
MB88153  
BLOCK DIAGRAM  
V
DD  
Power down  
setting  
XPD  
FREQ0  
FREQ1  
ENS  
Frequency setting  
Frequency setting  
Clock output  
PLL block  
CKOUT  
Modulation enable  
setting  
Reference clock  
CKIN  
V
SS  
Frequency setting  
1
M
V/I  
conversion  
Charge  
pump  
Phase  
compare  
IDAC  
ICO  
Modulation  
clock output  
1
N
Reference  
clock  
Loop filter  
Modulation rate  
setting  
Modulation enable  
setting  
1
L
Modulation logic  
MB88153 PLL block  
A glitchless IDAC (current output D/A converter) provides precise modulation, thereby dramatically reducing  
EMI.  
5
MB88153  
PIN SETTING  
When changing the pin setting, the stabilization wait time for the modulation clock required. The stabilization  
wait time for the modulation clock takes the maximum value of Lock-Up time in “ELECTRICAL CHARACTER-  
ISTICS AC characteristics”.  
ENS modulation enable setting  
ENS  
L
Modulation  
No modulation  
Modulation  
H
Note : Spectrum does not spread when “L” is set to ENS. The clock with low jitter can be obtained.  
FREQ0, FREQ1 frequency setting  
FREQ0  
FREQ1  
Input frequency range  
16.6 MHz to 40 MHz  
66 MHz to 134 MHz  
33 MHz to 67 MHz  
40 MHz to 80 MHz  
L
L
L
H
L
H
H
H
Note : It is set according to the frequency of the clock input to the device. Set FREQ0 pin to “H” for the pin opened  
because FREQ0 pin has pull-up resistor.  
XPD power down setting  
XPD  
L
Power down  
Power down  
H
Normal operation  
Note : When “L” is set to XPD pin, the power down operation is implemented and “L” is output to CKOUT pin. When  
“H” is input to XPD pin or XPD pin is opened, normal operation is implemented because the XPD pin has  
pull-up resistor.  
6
MB88153  
Center spread  
Spectrum is spread (modulated) by centering on the input frequency.  
3.0% modulation width  
Radiation level  
1.5%  
+1.5%  
Frequency  
Input frequency  
Center spread example of 1.5% modulation rate  
Down spread  
Spectrum is spread (modulated) below the input frequency.  
3.0% modulation width  
Radiation level  
3.0%  
Frequency  
Input frequency  
Down spread example of 3.0% modulation rate  
7
MB88153  
ABSOLUTE MAXIMUM RATINGS  
Rating  
Parameter  
Symbol  
Unit  
Min  
0.5  
Max  
+ 4.0  
Power supply voltage*  
Input voltage*  
VDD  
VI  
V
V
VSS 0.5  
VSS 0.5  
55  
VDD + 0.5  
VDD + 0.5  
+ 125  
Output voltage*  
VO  
TST  
V
Storage temperature  
°C  
Operation junction  
temperature  
TJ  
40  
+ 125  
°C  
Output current  
Overshoot  
IO  
14  
+ 14  
mA  
V
VIOVER  
VIUNDER  
VDD + 1.0 (tOVER 50 ns)  
Undershoot  
VSS 1.0 (tUNDER 50 ns)  
V
* : The parameter is based on VSS = 0.0 V.  
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,  
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.  
Overshoot/Undershoot  
tUNDER 50 ns  
VIOVER VDD + 1.0 V  
VDD  
Input pin  
VSS  
VIUNDER VSS 1.0 V  
tOVER 50 ns  
8
MB88153  
RECOMMENDED OPERATING CONDITIONS  
(VSS = 0.0 V)  
Value  
Typ  
Sym-  
bol  
Parameter  
Pin  
Conditions  
Unit  
Max  
Min  
Power supply voltage  
VDD  
VDD  
3.0  
3.3  
3.6  
V
CKIN, ENS,  
FREQ0, FREQ1,  
XPD  
“H” level input voltage  
“L” level input voltage  
VIH  
VIL  
VDD × 0.80  
VDD + 0.3  
V
CKIN, ENS,  
FREQ0, FREQ1,  
XPD  
VSS  
VDD × 0.20  
V
16.6 MHz to  
134 MHz  
Input clock duty cycle  
Operating temperature  
tDCI  
Ta  
CKIN  
40  
50  
60  
%
40  
+ 85  
°C  
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the  
semiconductor device. All of the device’s electrical characteristics are warranted when the device is  
operated within these ranges.  
Always use semiconductor devices within their recommended operating condition ranges. Operation  
outside these ranges may adversely affect reliability and could result in device failure.  
No warranty is made with respect to uses, operating conditions, or combinations not represented on  
the data sheet. Users considering application outside the listed conditions are advised to contact their  
FUJITSU representatives beforehand.  
Input clock duty cycle (tDCI = tb/ta)  
t
a
t
b
1.5 V  
CKIN  
9
MB88153  
ELECTRICAL CHARACTERISTICS  
• DC Characteristics  
(Ta = − 40 °C to + 85 °C, VDD = 3.3 V 0.3 V, VSS = 0.0 V)  
Value  
Parameter  
Symbol  
Pin  
Conditions  
Unit  
Min  
Typ  
Max  
“H” level output  
IOH = − 4 mA  
VOH  
CKOUT  
CKOUT  
VDD 0.5  
VDD  
V
Output voltage  
“L” level output  
IOL = 4 mA  
VOL  
ZO  
VSS  
0.4  
V
Output impedance  
Input capacitance  
CKOUT 16.6 MHz to 134 MHz  
45  
CKIN,  
ENS, Ta = + 25 °C,  
FREQ0, VDD = VI = 0.0 V,  
FREQ1, f = 1 MHz  
XPD  
CIN  
16  
pF  
16.6 MHz to 67 MHz  
CKOUT 67 MHz to 100 MHz  
100 MHz to 134 MHz  
15  
10  
7
Load capacitance  
CL  
pF  
FREQ0,  
VIL = 0.0 V  
XPD  
Input Pull-up resistance  
RPU  
25  
50  
200  
kΩ  
No load capacitance  
VDD  
Power supply current  
Power down current  
ICC  
4.0  
6.0  
mA  
at 24 MHz output  
Ipd  
VDD  
Input clock stopping  
600  
µA  
• AC Characteristics  
(Ta = − 40 °C to + 85 °C, VDD = 3.3 V 0.3 V, VSS = 0.0 V)  
Value  
Parameter  
Symbol  
Pin  
Conditions  
Unit  
Min  
16.6  
16.6  
Typ  
Max  
134  
134  
Input frequency  
fin  
CKIN  
MHz  
MHz  
Output frequency  
fOUT  
CKOUT  
Load capacitance 15 pF  
0.4 V to 2.4 V  
Output slew rate  
SR  
CKOUT  
0.4  
4.0  
V/ns  
Output clock duty cycle  
Modulation frequency  
Lock-up time  
tDCC  
fMOD  
tLK  
CKOUT 1.5 V  
CKOUT  
40  
12.5  
2
60  
5
%
kHz  
ms  
CKOUT  
No load capacitance,  
Ta = + 25 °C,  
Cycle-cycle jitter  
tJC  
CKOUT  
100  
ps  
VDD = 3.3 V,  
Standard deviation σ  
Note : The modulation clock stabilization wait time is required after the power is turned on, the IC recovers from  
power saving, or after FREQ (frequency range) or ENS (modulation ON/OFF) setting is changed. For the  
modulation clock stabilization wait time, assign the maximum value for lock-up time.  
10  
MB88153  
OUTPUT CLOCK DUTY CYCLE (tDCC = tb/ta)  
t
a
t
b
1.5 V  
CKOUT  
INPUT FREQUENCY (fin = 1/tin)  
t
in  
0.8 VDD  
CKIN  
OUTPUT SLEW RATE (SR)  
2.4 V  
0.4 V  
CKOUT  
tr  
tf  
Note : SR = (2.40.4) /tr, SR = (2.40.4) /tf  
CYCLE-CYCLE JITTER  
CKOUT  
tn  
tn+1  
Note : Cycle-cycle jitter is defined the difference between a certain cycle and immediately after  
(or, immediately before) .  
11  
MB88153  
MODULATION WAVEFORM  
1.5% modulation rate, Example of center spread  
CKOUT  
output frequency  
+ 1.5 %  
Frequency at modulation OFF  
Time  
1.5 %  
fMOD = 12.5 kHz (Typ)  
• −1.0% modulation rate, Example of down spread  
CKOUT  
output frequency  
Frequency at modulation OFF  
Time  
0.5 %  
1.0 %  
fMOD = 12.5 kHz (Typ)  
12  
MB88153  
LOCK-UP TIME  
3.0 V  
VDD  
External clock  
stabilization wait time  
CKIN  
VIH  
VIH  
XPD  
Setting pin  
FREQ0,  
FREQ1,  
ENS  
tLK  
(lock-up time )  
CKOUT  
If the XPD pin is fixed at the “H” level, the maximum time after the power is turned on until the set clock signal is  
output from CKOUT pin is (the stabilization wait time of input clock to CKIN pin) + (the lock-up time “tLK”). For the  
input clock stabilization time, check the characteristics of the resonator or oscillator used.  
3.0 V  
V
DD  
External clock stabilization wait time  
CKIN  
XPD  
V
IH  
Setting pin  
FREQ0,  
FREQ1,  
ENS  
V
IH  
tLK  
(lock-up time )  
CKOUT  
When XPD pin controls the power-down, stable clock is output from CKOUT pin after becoming XPD pin = “H” level  
(in the maximum after lock-Up time (tLK) ).  
13  
MB88153  
(Continued)  
CKIN  
XPD  
VIH  
VIH  
ENS  
VIL  
tLK  
tLK  
(lock-up time )  
(lock-up time )  
CKOUT  
When ENS pin is controlled for enable modulation, it is necessary for the stably clock output from CKOUT pin to  
wait lock-up time (tLK) .  
Note : In the following cases, it is necessary for the stably clock output from CKOUT pin, to wait lock-up time (tLK) .  
- After releasing power-down  
- When you change other terminal settings  
Output frequency, output clock duty cycle, modulation frequency, and cycle-cycle jitter are not guaranteed  
until the output clock is stable. It is recommended to take procedure to release of reset after. lock-up time  
(tLK) on the device using the modulation clock or etc.  
14  
MB88153  
INTERCONNECTION CIRCUIT EXAMPLE  
CKIN  
1
XPD  
8
7
6
5
VDD  
2
FREQ0  
FREQ1  
ENS  
MB88153  
VSS  
3
4
R1  
CKOUT  
C1  
C2  
C1 : Capacitor of 10 µF or higher  
C2 : Capacitor of approximately 0.01 µF (connect a capacitor of good high frequency  
property (ex. laminated ceramic capacitor) to close to this device)  
R1 : Impedance matching resistor for a circuit on a board  
15  
MB88153  
SPECTRUM EXAMPLE CHARACTERISTICS  
The condition of the examples of the characteristic is shown as follows: Input frequency = 20 MHz (Output  
frequency = 20 MHz), use for MB88153-111.  
Power-supply voltage = 3.3 V, None load capacity. Modulation rate = 1.5% (center spread).  
Spectrum analyzer HP4396B is connected with CKOUT. The result of the measurement with RBW = 1 kHz (ATT  
use for 6 dB) .  
CH B Spectrum  
10 dB /REF 0 dBm  
No modulation  
8.86 dBm  
Avg  
4
1.5% modulation  
26.54 dBm  
SWP 2.505 s  
SPAN 4 MHZ  
RBW# 1 kHZ  
CENTER 20 MHZ  
VBW 1 kHZ  
ATT 6 dB  
16  
MB88153  
ORDERING INFORMATION  
Part number  
modulation rate  
modulation type  
Down  
Package  
Remarks  
MB88153PNF-G-100-JNE1  
MB88153PNF-G-101-JNE1  
MB88153PNF-G-110-JNE1  
MB88153PNF-G-111-JNE1  
MB88153PNF-G-100-JN-EFE1  
MB88153PNF-G-101-JN-EFE1  
MB88153PNF-G-110-JN-EFE1  
MB88153PNF-G-111-JN-EFE1  
MB88153PNF-G-100-JN-ERE1  
MB88153PNF-G-101-JN-ERE1  
MB88153PNF-G-110-JN-ERE1  
MB88153PNF-G-111-JN-ERE1  
1.0%  
3.0%  
0.5%  
Down  
8-pin plastic SOP  
(FPT-8P-M02)  
Center  
Center  
Down  
1.5%  
1.0%  
3.0%  
0.5%  
Down  
8-pin plastic SOP Emboss taping  
(FPT-8P-M02)  
(EF type)  
Center  
Center  
Down  
1.5%  
1.0%  
3.0%  
0.5%  
Down  
8-pin plastic SOP Emboss taping  
(FPT-8P-M02) (ER type)  
Center  
Center  
1.5%  
17  
MB88153  
PACKAGE DIMENSION  
Note 1) *1 : These dimensions include resin protrusion.  
Note 2) *2 : These dimensions do not include resin protrusion.  
Note 3) Pins width and pins thickness include plating thickness.  
Note 4) Pins width do not include tie bar cutting remainder.  
8-pin plastic SOP  
(FPT-8P-M02)  
+0.25  
1 5.05 –0.20 .199 +..000180  
0.22 +00..0073  
*
.009 +..000031  
8
5
*2 3.90±0.30 6.00±0.40  
(.154±.012) (.236±.016)  
Details of "A" part  
1.55±0.20  
45˚  
(Mounting height)  
(.061±.008)  
0.25(.010)  
0.40(.016)  
0~8˚  
"A"  
1
4
1.27(.050)  
0.44±0.08  
(.017±.003)  
M
0.13(.005)  
0.50±0.20  
(.020±.008)  
0.15±0.10  
(.006±.004)  
(Stand off)  
0.60±0.15  
(.024±.006)  
0.10(.004)  
C
2002 FUJITSU LIMITED F08004S-c-4-7  
Dimensions in mm (inches)  
Note : The values in parentheses are reference values.  
18  
MB88153  
FUJITSU LIMITED  
All Rights Reserved.  
The contents of this document are subject to change without notice.  
Customers are advised to consult with FUJITSU sales  
representatives before ordering.  
The information, such as descriptions of function and application  
circuit examples, in this document are presented solely for the  
purpose of reference to show examples of operations and uses of  
Fujitsu semiconductor device; Fujitsu does not warrant proper  
operation of the device with respect to use based on such  
information. When you develop equipment incorporating the  
device based on such information, you must assume any  
responsibility arising out of such use of the information. Fujitsu  
assumes no liability for any damages whatsoever arising out of  
the use of the information.  
Any information in this document, including descriptions of  
function and schematic diagrams, shall not be construed as license  
of the use or exercise of any intellectual property right, such as  
patent right or copyright, or any other right of Fujitsu or any third  
party or does Fujitsu warrant non-infringement of any third-party’s  
intellectual property right or other right by using such information.  
Fujitsu assumes no liability for any infringement of the intellectual  
property rights or other rights of third parties which would result  
from the use of information contained herein.  
The products described in this document are designed, developed  
and manufactured as contemplated for general use, including  
without limitation, ordinary industrial use, general office use,  
personal use, and household use, but are not designed, developed  
and manufactured as contemplated (1) for use accompanying fatal  
risks or dangers that, unless extremely high safety is secured, could  
have a serious effect to the public, and could lead directly to death,  
personal injury, severe physical damage or other loss (i.e., nuclear  
reaction control in nuclear facility, aircraft flight control, air traffic  
control, mass transport control, medical life support system, missile  
launch control in weapon system), or (2) for use requiring  
extremely high reliability (i.e., submersible repeater and artificial  
satellite).  
Please note that Fujitsu will not be liable against you and/or any  
third party for any claims or damages arising in connection with  
above-mentioned uses of the products.  
Any semiconductor devices have an inherent chance of failure. You  
must protect against injury, damage or loss from such failures by  
incorporating safety design measures into your facility and  
equipment such as redundancy, fire protection, and prevention of  
over-current levels and other abnormal operating conditions.  
If any products described in this document represent goods or  
technologies subject to certain restrictions on export under the  
Foreign Exchange and Foreign Trade Law of Japan, the prior  
authorization by Japanese government will be required for export  
of those products from Japan.  
F0502  
© 2005 FUJITSU LIMITED Printed in Japan  

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