MB89183FM [FUJITSU]
8-bit Proprietary Microcontroller; 8位微控制器专有
| 型号： | MB89183FM |
| 厂家： | 
FUJITSU |
| 描述： | 8-bit Proprietary Microcontroller |
| 文件： | 总50页 (文件大小：319K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12404-2E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89180 Series
MB89181/182/183/P185/PV180
■ DESCRIPTION
The MB89180 series has been developed as a general-purpose version of the F2MC*-8L family consisting of
proprietary 8-bit, single-chip microcontrollers.
In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such as
dual-clock control system, five operating speed control stages, timers, a serial interface, a remote control
transmission output, external interrupts, an LCD controller/driver, and a watch prescaler.
*: F2MC stands for FUJITSU Flexible Microcontroller.
■ FEATURES
• F2MC-8L family CPU core
• Dual-clock control system
• High speed operation at low voltage
• Minimum execution time: 0.95 µs/2.7 V, 1.33 µs/2.2 V
• I/O ports: max. 64 channels
• 21-bit time-base timer
• 8/16-bit timer/counter: 1 channel (8 bits × 2 channels)
• 8-bit serial I/O: 1 channel
• LCD controller/driver: max. 32 segments outputs × 4 commons
(Continued)
■ PACKAGE
64-pin Plastic QFP
64-pin Ceramic MQFP
64-pin Plastic QFP
64-pin Plastic SQFP
(FPT-64P-M06)
(FPT-64P-M09)
(MQP-64C-P01)
(FPT-64P-M03)
MB89180 Series
(Continued)
• Remote control transmission output
• Buzzer output
• Watch prescaler (15 bits)
• External interrupts (wake-up function)
Four independent channels with edge detection function plus eight “L” level-interrupt channels
■ PRODUCT LINEUP
Part number
MB89181
MB89182
MB89183
MB89P185
MB89PV180
Parameter
Classification
Piggyback/
evaluation
product (for
evaluation and
development)
Mass production products
(mask ROM products)
One-time
PROM product
ROM size
4 K × 8 bits
(internal mask
ROM)
6 K × 8 bits
(internal mask
ROM)
8 K × 8 bits
(internal mask
ROM)
16K × 8 bits
(internal PROM, (external ROM)
programming
32 K × 8 bits
with general-
purpose
EPROM
programmer)
RAM size
128 × 8 bits
256 × 8 bits
512 × 8 bits
CPU functions
Number of instructions:
Instruction bit length:
Instruction length:
Data bit length:
Minimum execution time:
Interrupt processing time:
136
8 bits
1 to 3 bytes
1, 8, 16 bits
0.95 µs/4.2 MHz
8.57 µs/4.2 MHz
Ports
I/O ports (N-ch open drain):
8 (6 ports also serve as peripherals, and 3 ports are a
heavy-current drive type.)
Output ports (N-ch open drain): 18 (16 ports also serve as segment pins*1, and 2 ports
serve as booster capacitor connection pins.)
I/O ports (CMOS):
16 (12 ports also serve as an external interrupt, and
8 ports also serve as segment pins*1.)
1 (also serves as a remote control pin.)
43 (max.)
Output port (CMOS):
Total:
8/16-bit timer/
counter
8-bit timer/counter × 2 channels or 16-bit event counter × 1 channel
8-bit serial I/O
8 bits
LSB first/MSB first selectability
LDC controller/driver
Common output:
Segment output:
Bias power supply pins:
LCD display RAM size:
4 (COM2 and COM3 also serve as output ports.)
32 (max.)*1
3
32 × 4 bits
Dividing resistor for LCD driving (external resistor selectability)
4 channels (edge selection, also serve as segment pins.)*1
8 channels (only for a level interrupt)
External interrupt
(wake-up function)
(Continued)
2
MB89180 Series
(Continued)
Part number
MB89181
MB89182
MB89183
MB89P185
MB89PV180
Parameter
Buzzer output
1 (7 frequency types are selectable by software.)
1 (pulse width and cycle are selectable by software.)
Remote control
transmission output
Standby mode
Process
Sleep mode, stop mode, and watch mode
CMOS
Operating voltage*2
2.2 V*3 to 6.0 V
2.7 V to 6.0 V
MBM27C256A-20TV
(LCC package)
EPROM for use
*1: Selected by the mask option. See section “■ Mask Options.”
*2: Varies with conditions such as the operating frequency and the connected ICE. (See section “■ Electrical
Characteristics.”)
*3: The operation at less than 2.2 V is assured separately. Please contact FUJITSU LIMITED.
3
MB89180 Series
■ PACKAGE AND CORRESPONDING PRODUCTS
MB89181
MB89182
MB89183
Package
MB89P185
MB89PV180
FPT-64P-M06
FPT-64P-M09
FPT-64P-M03
MQP-64C-P01
×
×
×
×
×
×
: Available
× : Not available
Note: For more information about each package, see section “■ Package Dimensions.”
■ DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggyback product, verify its differences from the product that will actually be used.
Take particular care on the following points:
• On the MB89181, addresses 0140H and later of the register bank cannot be used. On the MB89182, MB89183,
and MB89P185 microcontrollers, addresses 0180H and later of the register bank cannot be used.
• On the MB89P185, addresses BFF0H to BFF5H comprise the option setting area, option settings can be read
by reading these addresses.
• The stack area, etc., is set at the upper limit of the RAM.
2. Current Consumption
• In the case of the MB89PV180, add the current consumed by the EPROM which is connected to the top
socket.
• When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume
more current than the product with a mask ROM.
However, the current consumption in sleep/stop modes is the same. (For more information, see section
“■ Electrical Characteristics.” )
3. Mask Options
Functions that can be selected as options and how to designate these options vary by the product.
Before using options check section “■ Mask Options.”
Take particular care on the following point:
• Options are fixed on the MB89PV180 except the segment output selection.
4
MB89180 Series
■ PIN ASSIGNMENT
(Top view)
SEG4
SEG5
SEG6
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P03/INT23
P04/INT24
P05/INT25
P06/INT26
P07/INT27
RST
X0A
X1A
MODA
X0
X1
P20/EC
P21 *2
P22/TO
P23/SI
P24/SO
SEG7
1
*
*
*
*
*
*
*
*
*
*
*
*
SEG8/P40
SEG9/P41
1
1
1
1
1
1
1
1
1
1
1
SEG10/P42
SEG11/P43
SEG12/P44
SEG13/P45
SEG14/P46
SEG15/P47
SEG16/P50
SEG17/P51
SEG18/P52
SEG19/P53
9
10
11
12
13
14
15
16
(FPT-64P-M03)
*1: Selected using the mask option (in units of 4 pins).
*2: N-ch open drain heavy-current drive type
5
MB89180 Series
(Top view)
SEG4
SEG5
SEG6
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P03/INT23
P04/INT24
P05/INT25
P06/INT26
P07/INT27
RST
X0A
X1A
MODA
X0
X1
P20/EC
P21 *2
P22/TO
P23/SI
P24/SO
SEG7
1
1
*
*
SEG8/P40
SEG9/P41
*1 SEG10/P42
*1 SEG11/P43
*1 SEG12/P44
*1 SEG13/P45
*1 SEG14/P46
*1 SEG15/P47
*1 SEG16/P50
*1 SEG17/P51
*1 SEG18/P52
*1 SEG19/P53
9
10
11
12
13
14
15
16
(FPT-64P-M09)
*1: Selected using the mask option (in units of 4 pins).
*2: N-ch open drain heavy-current drive type
6
MB89180 Series
(Top view)
SEG3
SEG4
SEG5
SEG6
SEG7
1
2
3
4
5
6
7
8
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P01/INT21
P02/INT22
P03/INT23
P04/INT24
P05/INT25
P06/INT26
P07/INT27
RST
X0A
X1A
MODA
X0
X1
P20/EC
P21*2
P22/TO
P23/SI
P24/SO
P25/SCK
1
1
*
*
SEG8/P40
SEG9/P41
*1 SEG10/P42
*1 SEG11/P43
*1 SEG12/P44
*1 SEG13/P45
*1 SEG14/P46
*1 SEG15/P47
*1 SEG16/P50
*1 SEG17/P51
*1 SEG18/P52
*1 SEG19/P53
9
10
11
12
13
14
15
16
17
18
19
1 SEG20/P54
1 SEG21/P55
*
*
(FPT-64P-M06)
*1: Selected using the mask option (in units of 4 pins).
*2: N-ch open drain heavy-current drive type
7
MB89180 Series
(Top view)
SEG3
SEG4
SEG5
SEG6
1
2
3
4
5
6
7
8
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P01/INT21
P02/INT22
P03/INT23
P04/INT24
P05/INT25
P06/INT26
P07/INT27
RST
X0A
X1A
MODA
X0
X1
P20/EC
P21*2
P22/TO
P23/SI
P24/SO
P25/SCK
SEG7
1
*
*
*
*
*
*
*
*
*
*
*
*
*
*
SEG8/P40
SEG9/P41
85
86
87
88
89
90
91
92
93
77
76
75
74
73
72
71
70
69
1
1
1
1
1
1
1
1
1
1
1
1
1
SEG10/P42
SEG11/P43
SEG12/P44
SEG13/P45
SEG14/P46
SEG15/P47
SEG16/P50
SEG17/P51
SEG18/P52
SEG19/P53
SEG20/P54
SEG21/P55
9
10
11
12
13
14
15
16
17
18
19
(MQP-64C-P01)
*1: Selected using the mask option (in units of 4 pins).
*2: N-ch open drain heavy-current drive type
• Pin assignment on package top (MB89PV180 only)
Pin no.
65
Pin name
N.C.
VPP
Pin no.
73
Pin name
A2
Pin no.
81
Pin name
N.C.
O4
Pin no.
89
Pin name
OE
66
74
A1
82
90
N.C.
A11
A9
67
A12
A7
75
A0
83
O5
91
68
76
N.C.
O1
84
O6
92
69
A6
77
85
O7
93
A8
70
A5
78
O2
86
O8
94
A13
A14
VCC
71
A4
79
O3
87
CE
95
72
A3
80
VSS
88
A10
96
N.C.: Internally connected. Do not use.
8
MB89180 Series
■ PIN DESCRIPTION
Pin no.
Circuit
type
Pin name
Function
QFP*1
QFP*2
SQFP*3
MQFP*4
39
38
40
39
X0
X1
A
C
Main clock crystal oscillator pins
CR oscillation selectability (only for the mask ROM
products)
40
43
41
44
MODA
Operating mode selection pin
Connect directly to VSS.
RST
Reset I/O pin
This pin is an N-ch open drain output type with a pull-
up resistor, and hysteresis input type. “L” is output
from this pin by an internal reset source. The internal
circuit is initialized by the input of “L”.
D
E
44 to 51
21 to 23
45 to 52
22 to 24
P07/INT27 to
P00/INT20
General-purpose I/O ports
Also serve as external interrupt 2 input (wake-up
function).
External interrupt 2 input is hysteresis input.
P10/INT10/
SEG24 to
P12/INT12/
SEG26
E/K
General-purpose I/O ports
Also serve as external interrupt 1 input.
The interrupt 1 input is a hysteresis type.
Also serve as LCD controller/driver segment output.
Switching is done by the mask option.
25
26
P13/INT13/
SEG27
26 to 29
27 to 30
P14/SEG28 to
P17/SEG31
F/K
H
General-purpose I/O ports
Also serve as LCD controller/driver segment output.
Switching is done by the mask option.
37
38
P20/EC
General-purpose N-ch open-drain I/O port
Also serves as the external clock input for the 8-bit
timer counter. The resource is a hysteresis input type.
36
35
37
36
P21
I
I
General-purpose N-ch open-drain I/O port
P22/TO
General-purpose N-ch open-drain I/O port
Also serves as the 8-bit timer/counter output
34
35
P23/SI
H
General-purpose N-ch open-drain I/O port
Also serves as the data input for the 8-bit serial I/O.
The resource is a hysteresis input type.
33
32
34
33
P24/SO
I
General-purpose N-ch open-drain I/O port
Also serves as the data output for the 8-bit serial I/O.
P25/SCK
H
General-purpose N-ch open-drain I/O port
Also serves as the clock I/O for the 8-bit serial I/O.
The resource is a hysteresis input type.
(Continued)
*1: FPT-64P-M09
*2: FPT-64P-M06
*3: FPT-64P-M03
*4: MQP-64C-P01
9
MB89180 Series
(Continued)
Pin no.
Circuit
type
Pin name
P26
Function
QFP*1
QFP*2
SQFP*3
MQFP*4
31
30
32
31
I
I
General-purpose N-ch open-drain I/O port
P27/BUZ
General-purpose N-ch open-drain I/O port
Also serves as a buzzer output.
52
53
P30/RCO
G
General-purpose output-only port
Also serves as a remote control transmission output
pin.
13 to 20
5 to 12
14 to 21 P50/SEG16 to
P57/SEG23
J/K
J/K
K
N-ch open-drain type general-purpose output ports
Also serve as LCD controller/driver segment output
pins.
6 to 13
P40/SEG8 to
P47/SEG15
Switching is done by the mask option.
61 to 64,
1 to 4
62 to 64, SEG7 to SEG0
1 to 5
LCD controller/driver segment output-only pins
57,
58
58,
59
COM3/P32,
COM2/P31
L
N-ch open-drain type general-purpose output ports
Also serve as LCD controller/driver common output
pins.
59,
60
60,
61
COM1,
COM0
K
LCD controller/driver common output-only pins
53,
54,
55
54,
55,
56
V1,
V2,
V3
—
LCD driving power supply pins
42
41
56
24
43
42
57
25
X0A
X1A
VCC
B
Subclock crystal oscillator pins (32.768 kHz)
Power supply pin
VSS
Power supply (GND) pin
*1: FPT-64P-M09
*2: FPT-64P-M06
*3: FPT-64P-M03
*4: MQP-64C-P01
10
MB89180 Series
• External EPROM pins (MB89PV180 only)
Pin no.
Pin name
VPP
I/O
O
Function
66
“H” level output pin
Address output pins
67
68
69
70
71
72
73
74
75
A12
A7
A6
A5
A4
A3
A2
A1
A0
O
77
78
79
O1
O2
O3
I
Data input pins
80
VSS
O
I
Power supply (GND) pin
Data input pins
82
83
84
85
86
O4
O5
O6
O7
O8
87
CE
O
ROM chip enable pin
Outputs “H” during standby.
88
89
A10
OE
O
O
Address output pin
ROM output enable pin
Outputs “L” at all times.
91
92
93
A11
A9
A8
O
Address output pins
94
95
96
A13
A14
VCC
O
O
O
EPROM power supply pin
65
76
81
90
N.C.
—
Internally connected pins
Be sure to leave them open.
11
MB89180 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Standby control signal
Standby control signal
Remarks
A
X1
X0
• Crystal or ceramic oscillation type (main clock)
At an oscillation feedback resistor of approximately
1 MΩ/5.0 V
• CR oscillation type (main clock)
(Selectable only for the MB89181/182/183)
X1
X0
B
• Crystal or ceramic oscillation type (subclock)
• At an oscillation feedback resistor of approximately
4.5 MΩ/5.0 V
X1A
X0A
Standby control signal
C
D
• Output pull-up resistor
• P-ch of approximately 50 KΩ/5.0 V
• Hysteresis input
R
P-ch
N-ch
E
• CMOS I/O
R
The resource is a hysteresis input type.
P-ch
P-ch
N-ch
• Pull-up resistor optional
(MB89181/182/183/P185)
Port
Resource
F
• CMOS I/O
R
P-ch
P-ch
N-ch
• Pull-up resistor optional
(MB89181/182/183/P185)
(Continued)
12
MB89180 Series
(Continued)
Type
Circuit
Remarks
G
• CMOS output
• The P-ch output is a heavy-current drive type.
P-ch
N-ch
H
• N-ch open-drain I/O
R
• CMOS input
P-ch
• The resource is a hysteresis input type.
N-ch
Port
• Pull-up resistor optional
(MB89181/182/183)
Resource
I
• N-ch open-drain I/O
• CMOS input
R
P-ch
• P21, P26, and P27 are a heavy-current drive type.
N-ch
• Pull-up resistor optional
(MB89181/182/183)
J
• N-ch open-drain output
R
P-ch
• Pull-up resistor optional
(MB89181/182/183)
N-ch
K
L
• LCD controller/driver segment output
P-ch
N-ch
P-ch
N-ch
• N-ch open-drain output
• Common output
N-ch
P-ch
N-ch
P-ch
N-ch
13
MB89180 Series
■ HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum
Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS.
When latchup occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.
Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital
power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters
Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.
4. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
5. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage
couldcausemalfunctions, evenifitoccurswithintheratedrange. StabilizingvoltagesuppliedtotheICistherefore
important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P
value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient
fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.
6. Precautions when Using an External Clock
Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and
wake-up from stop mode.
14
MB89180 Series
■ PROGRAMMING TO THE EPROM ON THE MB89P875
The MB89P185 is an OTPROM version of the MB89180 series.
1. Features
• 16-Kbyte PROM on chip
• Options can be set using the EPROM programmer.
• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)
2. Memory Space
Memory space in the EPROM mode is diagrammed below.
Normal operating mode
I/O
EPROM mode
(Corresponding address on the EPROM programmer)
0000H
0080H
0180H
RAM
Not available
8000H
0000H
Vacancy
(Read value undefined)
3FF0H
Option area
3FF6H
Not available
Vacancy
(Read value undefined)
4000H
C000H
Program area
(EPROM)
16 KB
ROM
16 KB
FFFFH
7FFFH
15
MB89180 Series
3. Programming to the EPROM
In EPROM mode, the MB89P185 functions equivalent to the MBM27C256A. This allows the PROM to be
programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by
using the dedicated socket adapter.
• Programming procedure
(1) Set the EPROM programmer to the MBM27C256A.
(2) Load program data into the EPROM programmer at 4000H to 7FFFH (note that addresses C000H to FFFFH
in operating mode assign to 4000H to 7FFFH in EPROM mode).
Program to 4000H to 7FFFH with the EPROM programmer.
(3) Load option data into addresses 3FF0H to 3FF5H of the EPROM programmer. (For information about each
corresponding option, see “7. PROM Option Bit Map.”)
Program to 3FF0H to 3FF5H with the EPROM programmer.
4. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked
OTPROM microcomputer program.
Program, verify
Aging
+150°C, 48 Hrs.
Data verification
Assembly
5. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.
For this reason, a programming yield of 100% cannot be assured at all times.
6. EPROM Programmer Socket Adapter
Package
Compatible socket adapter
ROM-64QF2-28DP-8L2
FPT-64P-M09
FPT-64P-M06
ROM-64QF-28DP-8L3
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760
Note: Depending on the EPROM programmer, inserting a capacitor of about 0.1 µF between VPP and VSS or
VCC and VSS can stabilize programming operations.
16
MB89180 Series
7. PROM Option Bit Map
The programming procedure is the same as that for the PROM. Options can be set by programming values at
the addresses shown on the memory map. The relationship between bits and options is shown on the following
bit map:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Oscillation stabilization delay time
Clock mode
selection
1: Dual clock
0: Single clock
Vacancy
Vacancy
Vacancy
Reset pin
output
1: Yes
Power-on
reset
1: Yes
0: No
3FF0H
3FF1H
3FF2H
3FF3H
3FF4H
3FF5H
WTM1
WTM0
Readable
Readable
Readable
See “■ Mask Options”
0: No
P07
P06
P05
Pull-up
1: No
P04
P03
P02
P01
P00
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
0: Yes
P17
P16
P15
P14
P13
P12
P11
P10
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Readable
Readable
Readable
Readable
Readable
Readable
Readable
Readable
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Readable
Readable
Readable
Readable
Readable
Readable
Readable
Readable
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Readable
Readable
Readable
Readable
Readable
Readable
Readable
Readable
Notes: • Set each bit to 1 to erase.
• Do not write 0 to the vacant bit.
The read value of the vacant bit is 1, unless 0 is written to it.
• Address 3FF6H cannot be read and should not be accessed.
17
MB89180 Series
■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C256A-20TV
2. Programming Socket Adapter
To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato
Co., Ltd.) listed below.
Package
LCC-32(Rectangle) ROM-32LC-28DP-YG
LCC-32(Square) ROM-32LC-28DP-S
Adapter socket part number
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760
3. Memory Space
Memory space in each mode is diagrammed below.
Normal operating mode
0000H
Corresponding address in ROM programmer
I/O
0080H
RAM
0180H
Not available
8000H
0000H
Not available
Not available
4000H
C000H
PROM
16KB
EPROM
16KB
FFFFH
7FFFH
4. Programming to the EPROM
(1) Set the EPROM programmer to the MBM27C256A.
(2) Load program data into the EPROM programmer at 4000H to 7FFFH.
(3) Program to 4000H to 7FFFH with the EPROM programmer.
18
MB89180 Series
■ BLOCK DIAGRAM
N-ch open-drain I/O port
8-bit timer/counter
X0
X1
Main clock oscillator
Clock controller
P26 *2
P22/TO
P21 *2
Subclock oscillator
(32.768 kHz)
X0A
X1A
8-bit timer/counter
8-bit serial I/O
P20/EC
P25/SCK
P24/SO
P23/SI
21-bit time-base timer
8
8
External interrupt 2
(wake-up function)
P00/INT20
to P07/INT27
P27 *2 /BUZ
Buzzer output
CMOS I/O port
4
P14 to P17
CMOS I/O port
4
External interrupt 1
(wake-up function)
4
Remote control
P10/INT10 to
P13/INT13
P30/RCO
transmission output
P31/COM2
P32/COM3
4
N-ch open-drain output port
(Only P30 for CMOS output port)
SEG28 to SEG31 *1
(Also serve as P14 to P17.)
8
4
SEG24 to SEG27 *1
(Also serve as P10 to P13.)
RST
Reset circuit
RAM
8
SEG0 to SEG7
(256 × 8 bits max.)
2
LCD controller/driver
COM0, COM1
F2MC-8L
CPU
COM2 (Also serves as P31.)
COM3 (Also serves as P32.)
3
V1 to V3
ROM
(8 K × 8 bits max.)
4
P57/SEG23 *1
to P54/SEG20 *1
4
16
P53/SEG19 *1
to P50/SEG16 *1
4
32 × 4 bits
VRAM
P47/SEG15 *1
Other pins
MODA
VCC
to P44/SEG12 *1
MODA
VCC
4
P43/SEG11 *1
to P40/SEG8 *1
N-ch open-drain output port
VSS
VSS
*1: The segment or port function is selected by the mask option.
*2: N-ch open-drain heavy-current drive type
19
MB89180 Series
■ CPU CORE
1. Memory Space
The microcontrollers of the MB89180 series offer a memory space of 64 Kbytes for storing all of I/O, data, and
program areas. The I/O area is located at the lowest address. The data area is provided immediately above the
I/O area. The data area can be divided into register, stack, and direct areas according to the application. The
program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of
interrupt reset vectors and vector call instructions toward the highest address within the program area. The
memory space of the MB89180 series is structured as illustrated below.
Memory Space
MB89PV180
I/O
MB89181
I/O
MB89182
I/O
MB89183
I/O
MB89P185
I/O
0000H
0080H
0000H
0080H
0000H
0000H
0080H
0000H
0080H
0080H
00C0H
Unused
RAM
RAM
RAM
RAM
256 B
256 B
256 B
512 B
RAM
128 B
0100H
0180H
0100H
0100H
0140H
0100H
0180H
0100H
0180H
Register
Register
Register
Register
Register
0200H
0280H
8000H
Unused
Unused
Unused
Unused
Unused
C000H
FFFFH
E000H
FFFFH
External ROM
32 KB
ROM
16 KB
E800H
FFFFH
ROM
8 KB
F000H
FFFFH
ROM
6KB
ROM
4 KB
FFFFH
20
MB89180 Series
2. Registers
The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The following dedicated registers are provided:
Program counter (PC):
Accumulator (A):
A 16-bit register for indicating instruction storage positions
A 16-bit temporary register for storing arithmetic operations, etc. When the
instruction is an 8-bit data processing instruction, the lower byte is used.
Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator
Whenthe instructionisan8-bitdataprocessinginstruction, thelowerbyteisused.
Index register (IX):
Extra pointer (EP):
Stack pointer (SP):
Program status (PS):
A 16-bit register for index modification
A 16-bit pointer for indicating a memory address
A 16-bit register for indicating a stack area
A 16-bit register for storing a register pointer, a condition code
Initial value
16 bits
PC
A
: Program counter
: Accumulator
FFFDH
Undefined
Undefined
Undefined
Undefined
Undefined
T
: Temporary accumulator
: Index register
IX
EP
SP
PS
: Extra pointer
: Stack pointer
: Program status
I-flag = 0, IL1, 0 = 11
Other bits are undefined.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for
use as a condition code register (CCR). (See the diagram below.)
Structure of the Program Status Register
15
14
13
12
11
10
9
8
7
6
I
5
4
3
2
Z
1
0
PS
RP
Vacancy Vacancy Vacancy
H
IL1, 0
N
V
C
RP
CCR
21
MB89180 Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
Rule for Conversion of Actual Addresses of the General-purpose Register Area
Lower OP codes
RP
“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 b1 b0
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and
bits for control of CPU operations at the time of an interrupt.
H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared
otherwise. This flag is for decimal adjustment instructions.
I-flag: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0
when reset.
IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is
higher than the value indicated by this bit.
IL1
0
IL0
0
Interrupt level
High-low
High
1
0
1
1
0
2
3
1
1
Low = no interrupt
N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0.
Z-flag: Set when an arithmetic operation results in 0. Cleared otherwise.
V-flag: Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does
not occur.
C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise.
Set to the shift-out value in the case of a shift instruction.
22
MB89180 Series
The following general-purpose registers are provided:
General-purpose registers: An 8-bit register for storing data
The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains
eight registers. Up to a total of 8 banks can be used on the MB89181 (RAM 128 × 8 bits) and a total of 16 banks
can be used on the MB89182/183 (RAM 256 × 8 bits). The bank currently in use is indicated by the register
bank pointer (RP).
Note: The number of register banks that can be used varies with the RAM size.
Register Bank Configuration
This address = 0100H + 8 × (RP)
R 0
R 1
R 2
R 3
R 4
R 5
R 6
R 7
8 banks (MB89181)
16 banks (MB89182/183)
Memory area
23
MB89180 Series
■ I/O MAP
Address
00H
Read/write
(R/W)
(W)
Register name
PDR0
Register description
Port 0 data register
01H
DDR0
Port 0 data direction register
Port 1 data register
02H
(R/W)
(W)
PDR1
03H
DDR1
Port 1 data direction register
Port 2 data register
04H
(R/W)
(W)
PDR2
05H
DDR2
Port 2 data direction register
Vacancy
06H
07H
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
SYCC
STBC
WDTC
TBTC
WPCR
PDR3
System clock control register
Standby control register
Watchdog timer control register
Time-base timer control register
Watch prescaler control register
Port 3 data register
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
Vacancy
(R/W)
(R/W)
(R/W)
PDR4
PDR5
BZCR
Port 4 data register
Port 5 data register
10H
Buzzer register
11H
Vacancy
12H
Vacancy
13H
Vacancy
14H
(R/W)
(R/W)
RCR1
RCR2
Remote control transmission control register 1
Remote control transmission control register 2
Vacancy
15H
16H
17H
Vacancy
18H
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
T2CR
T1CR
T2DR
T1DR
SMR1
SDR1
Timer 2 control register
Timer 1 control register
Timer 2 data register
Timer 1 data register
Serial mode register
Serial mode register
Vacancy
19H
1AH
1BH
1CH
1DH
1EH to 2FH
(Continued)
24
MB89180 Series
(Continued)
Address
Read/write
(R/W)
Register name
EIE1
Register description
30H
31H
External interrupt 1 enable register
(R/W)
EIF1
External interrupt 1 flag register
External interrupt 2 enable register
External interrupt 2 flag register
Vacancy
32H
(R/W)
EIE2
33H
(R/W)
EIF2
34H to 5FH
60H to 6FH
70H to 71H
72H
(R/W)
(R/W)
VRAM
LCR1
Display data RAM
Vacancy
LCD controller/driver control register 1
Vacancy
73H to 7BH
7CH
(W)
(W)
(W)
ILR1
ILR2
ILR3
Interrupt level setting register 1
Interrupt level setting register 2
Interrupt level setting register 3
Vacancy
7DH
7EH
7FH
Note: Do not use vacancies.
25
MB89180 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = 0.0 V)
Value
Symbol
Unit
Remarks
Parameter
Min.
Max.
Power supply voltage
VCC
VSS – 0.3
VSS – 0.3
VSS + 7.0
VSS + 7.0
V
V
LCD power supply voltage
V1 to V3
V1 to V3 must not exceed VCC.
VI1 must not exceed Vss + 7.0 V.
Except P20 to P27 without a pull-
up resistor
VI1
VSS – 0.3
VSS – 0.3
VCC + 0.3
VSS + 7.0
V
V
Input voltage
P20 to P27 without a pull-up
resistor
VI2
VO1 must not exceed Vss + 7.0 V.
Except P20 to P27, P40 to P47,
and P50 to P57 without a pull-up
resistor
VO1
VO2
VSS – 0.3
VSS – 0.3
VCC + 0.3
VSS + 7.0
V
Output voltage
P20 to P27, P40 to P47, and P50
to P57 without a pull-up resistor
V
Except P21, P26, P27, and power
supply pins
IOL1
IOL2
10
20
mA
“L” level output current
mA P21, P26, and P27
Average value (operating
current × operating rate)
Except P21, P26, P27, and power
supply pins
IOLAV1
4
8
mA
“L” level average output current
“L” level total output current
Average value (operating
mA current × operating rate)
P21, P26, and P27
IOLAV2
∑IOL
80
40
mA
“L” level total average output
current
Average value (operating
mA
∑IOLAV
current × operating rate)
IOH1
–5
mA Except P30 and power supply pins
“H” level output current
IOH2
–10
mA P30
(Continued)
26
MB89180 Series
(Continued)
(VSS = 0.0 V)
Value
Symbol
Unit
Remarks
Parameter
Min.
Max.
Average value (operating
mA current × operating rate)
IOHAV1
–2
Except P30 and power supply pins
“H” level average output current
“H” level total output current
Average value (operating
mA current × operating rate)
P30
IOHAV2
–4
∑IOH
–20
–10
mA
“H” level total average output
current
Average value (operating
mA
∑IOHAV
current × operating rate)
Power consumption
Operating temperature
Storage temperature
PD
300
+85
mW
°C
TA
–40
–55
Tstg
+150
°C
Precautions: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded.
Functional operation should be restricted to the conditions as detailed in the operational sections of
this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
2. Recommended Operating Conditions
(VSS = 0.0 V)
Value
Symbol
Unit
Remarks
Parameter
Min.
Max.
Guaranteed normal operation range,
applicable to the mask ROM products
2.2*1
6.0
V
Power supply voltage
VCC
2.7*1
1.5
6.0
6.0
V
V
MB89P185/PV180
RAM data holding assurance range in
stop mode
VCC*2
Power supply voltage for LCD
Operating temperature
V1 to V3
TA
VSS
V
V1 to V3 pins
–40
+85
°C
*1: The minimum operating power supply voltage varies with the operating frequency and execution time (instruction
cycle).
*2: The liquid-crystal power supply range and optimum value vary depending on the characteristics of the liquid-
crystal display element used.
27
MB89180 Series
6
5
Operation assurance range
4
3
2
1
0
1
2
3
4
5
Main clock operating frequency (MHz)
0.8
1.0
4.0
2.0
Minimum execution time (instruction cycle) (µs)
Note: The shaded area is assured only for the MB89181/182/183.
Figure 1 Operating Voltage vs. Main Clock Operating Frequency
28
MB89180 Series
3. DC Characteristics
(VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Parameter
Symbol
Pin
Condition
Unit Remarks
Min.
Typ.
Max.
P00 to P07,
P10 to P17,
P20 to P27
VCC +
0.3
CMOS
input
VIH
0.7 VCC
—
V
“H” level input
voltage
RST, MODA, EC,
SI, SCK,
INT10 to INT13,
INT20 to INT27
Hysteresis
input
VCC +
VIHS
0.8 VCC
—
—
V
0.3
P00 to P07,
P10 to P17,
P20 to P27
VSS –
0.3
CMOS
input
VIL
0.3 VCC
V
—
“L” level input
voltage
RST, MODA,
EC, SI, SCK,
INT10 to
INT13, INT20
to INT27
Hysteresis
input
VSS –
0.3
VILS
—
—
0.2 VCC
V
P20 to P27,
P40 to P47,
P50 to P57
Open-drain output
pin application
voltage
VSS +
6.0
Without pull-
up resistor
VSS –
0.3
VD
V
P00 to P07,
P10 to P17
VOH1
VOH2
IOH = –2.0 mA
IOH = –6.0 mA
2.4
4.0
—
—
—
—
V
V
“H” level output
voltage
P30
P00 to P07,
P10 to P17,
P20, P22 to P25,
P30 to P32,
P40 to P47,
P50 to P57
VOL
IOL = +1.8 mA
—
—
0.4
V
“L” level output
voltage
VOL2
VOL3
P21, P26, P27 IOL = +8.0 mA
—
—
—
—
0.4
0.4
V
V
RST
IOL = +4.0 mA
MODA,
Without pull-
µA
P00to P07,
P10 to P17,
P30 to P32
ILI1
0.0 V < VI < VCC
—
—
25
—
—
50
±5
±1
Input leakage
current
(Hi-z output
leakagecurrent)
up resistor
P20 to P27,
P40 to P47,
P50 to P57
Without pull-
µA
ILI2
0.0 V < VI < 6 V
VI = 0.0 V
up resistor
P00 to P07,
P10 to P17,
P20 to P27,
P40 to P47,
P50 to P57, RST
Without pull-
kΩ
Pull-up
resistance
RPULL
100
up resistor
COM0 to
COM3
V1 to V3 = 5.0
V
Common output
impedance
RVCOM
RVSEG
—
—
—
—
2.5
15
kΩ
SEG0 to
SEG31
V1 to V3 = 5.0
V
Segment output
impedance
kΩ
(Continued)
29
MB89180 Series
(Continued)
(VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Parameter
Symbol
Pin
Condition
Unit Remarks
Min.
Typ.
Max.
LCD divided
resistor value
Between
VCC and VSS
RLCD
—
300
500
750
kΩ
LCD controller/
driver leakage
current
V1 to V3,
COM0 to COM3,
SEG0 to SEG31
ILCDL
—
—
—
±1
µA
FCH = 4.2 MHz
VCC = 5.0 V
MB89181/
mA 182/183/
PV180
—
—
3.0
3.8
4.5
6.0
tinst*2 = 0.95 µs
ICC1
• Main clock
operation mode
mA MB89P185
MB89181/
mA 182/183/
PV180
FCH = 4.2 MHz
VCC = 3.0 V
—
—
—
0.25
0.85
0.05
0.4
1.4
0.1
tinst*2 = 15.2 µs
• Main clock
ICC2
operation mode
mA MB89P185
FCL = 32.768
kHz
VCC = 3.0 V
tinst*2 = 61 µs
• Subclock
operation mode
MB89181/
mA 182/183/
PV180
ICCL
—
—
0.65
0.8
1.1
1.2
mA MB89P185
FCH = 4.2 MHz
VCC = 5.0 V
tinst*2 = 0.95 µs
• Main clock
sleep mode
mA
Power supply
current*2
ICCS1
VCC
FCH = 4.2 MHz
VCC = 3.0 V
tinst*2 = 15.2 µs
• Main clock
sleep mode
ICCS2
—
—
0.2
25
0.3
50
mA
FCL = 32.768 kHz
VCC = 3.0 V
ICCSL
µA
µA
tinst*2 = 61 µs
• Subclock mode
FCL = 32.768 kHz
VCC = 3.0 V
• Watch mode
ICCT
—
—
10
15
1
MB89181/
µA
0.1
TA = +25°C
VCC = 5.0 V
• Stop mode
182/183
ICCH
MB89PV18
0/P185
—
—
0.1
10
10
—
µA
Input capacitance
Other V
CC and VSS
f = 1 MHz
CIN
pF
*1: The measurement conditions of power supply current are as follows: the external clock, open output pins, and
the external LCD dividing resistor. In the case of the MB89PV180, the current consumed by the connected
EPROM and ICE is not included.
*2: For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.”
Note: For pins which serve as the segment (SEG8 to SEG31) and ports (P10 to P17, P40 to P47, and P50 to P57),
see the port parameter when these pins are used as ports and the segment parameter when they are used
as segment pins.
30
MB89180 Series
4. AC Characteristics
(1) Reset Timing
(VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Condition
Unit
Remarks
Parameter
Min.
Max.
RST “L” pulse width
tZLZH
—
48 tHCYL
—
ns
tZLZH
RST
0.2 VCC
0.2 VCC
(2) Power-on Reset
Parameter
(VSS = 0.0 V, TA = –40°C to +85°C)
Value
Min. Max.
Symbol Condition
Unit
Remarks
Power supply rising time
Power supply cut-off time
tR
—
1
50
—
ms
ms
Power-on reset function only
Due to repeated operations
—
tOFF
Note: Make sure that power supply rises within the selected oscillation stabilization time.
If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is
recommended.
tOFF
tR
2.0 V
0.2 V
0.2 V
0.2 V
V
CC
31
MB89180 Series
(3) Clock Timing
(VSS = 0.0 V, TA = –40°C to +85°C)
Value
Typ.
—
Parameter
Clock frequency
Clock cycle time
Symbol
Pin
X0, X1
Unit
Remarks
Min.
1
Max.
4.2
FCH
MHz Main clock
kHz Subclock
FCL
X0A, X1A
X0, X1
—
32.768
—
—
tHCYL
tLCYL
238
—
1000
—
ns
Main clock
Subclock
X0A, X1A
30.5
µs
PWH
PWL
X0
20
—
—
—
15.2
—
—
—
10
ns
µs
ns
Input clock pulse width
PWHL
PWLL
X0A
External clock
Input clock pulse rising/
falling time
tCR
tCF
X0, X0A
X0 and X1 Timing and Conditions
tHCYL
0.8 VCC
0.2 VCC
X0
PWH
PWL
tCF
tCR
Main clock Conditions
When crystal
or
ceramic resonator is used
When CR oscillation
option is used
When an external clock is used
X 0
X 1
X 0
X 1
X 0
X 1
FCH
FCH
Open
R1
FCH
C
C1
C2
32
MB89180 Series
X0A and X1A Timing and Conditions
tLCYL
0.8 VCC
0.2 VCC
X0A
PWHL
PWLL
tCF
tCR
Subclock Conditions
When crystal
or
ceramic resonator is used
When single-clock
option is used
When an external clock is used
X0A
X1A
X0A
X1A
X0A
X1A
Open
R2
Open
FCL
FCL
C1
C2
(4) Instruction Cycle
Symbol
Value (typical)
Unit
Remarks
Parameter
(4/FCH) tinst = 0.95 µs when operating
at FCH = 4.2 MHz
4/FCH, 8/FCH, 16/FCH, 64/FCH µs
Instruction cycle
(minimum execution time)
tinst
tinst = 61.036 µs when operating at
FCL = 32.768 kHz
2/FCL
µs
33
MB89180 Series
(5) Serial I/O Timing
(VCC = +5.0 V±10%, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin
SCK
Condition
Unit Remarks
Parameter
Min.
2 tinst*
–200
Max.
—
Serial clock cycle time
SCK ↓ → SO time
tSCYC
tSLOV
tIVSH
tSHIX
tSHSL
tSLSH
tSLOV
tIVSH
tSHIX
µs
ns
µs
µs
µs
µs
ns
µs
µs
SCK, SO
SI, SCK
SCK, SI
SCK
200
—
Internal shift
clock mode
Valid SI → SCK ↑
0.5 tinst*
0.5 tinst*
1 tinst*
1 tinst*
0
SCK ↑ → valid SI hold time
Serial clock “H” pulse width
Serial clock “L” pulse width
SCK ↓ → SO time
—
—
SCK
—
External shift
clock mode
SCK, SO
SI, SCK
SCK, SI
200
—
Valid SI → SCK ↑
0.5 tinst*
0.5 tinst*
SCK ↑ → valid SI hold time
—
* : For information on tinst, see “(4) Instruction Cycle.”
Internal Shift Clock Mode
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSLOV
2.4 V
SO
0.8 V
tIVSH
tSHIX
0.8 V cc
0.2 V cc
0.8 V cc
0.2 V cc
SI
External Shift Clock Mode
tSLSH
tSHSL
0.8 VCC
0.8 VCC
SCK
0.2 VCC
0.2 VCC
tSLOV
2.4 V
0.8 V
SO
SI
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
34
MB89180 Series
(6) Peripheral Input Timing
Parameter
(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin
Unit Remarks
Min.
1 tinst*
1 tinst*
2 tinst*
2 tinst*
Max.
—
Peripheral input “H” pulse width 1
Peripheral input “L” pulse width 1
Peripheral input “H” pulse width 2
Peripheral input “L” pulse width 2
tILIH1
tIHIL1
tILIH2
tIHIL2
INT10 to INT13, EC
INT10 to INT13, EC
INT20 to INT27
µs
µs
µs
µs
—
—
INT20 to INT27
—
* : For information on tinst, see “(4) Instruction Cycle.”
tIHIL1
tILIH1
INT10 to INT13,
0.8 VCC
0.2 VCC
0.8 VCC
EC
0.2 VCC
tIHIL2
tILIH2
INT20 to INT27
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
35
MB89180 Series
■ EXAMPLE CHARACTERISTICS
(1) “L” level Output Voltage
VOL2 vs.IOL
VCC = 2.0 V VCC = 2.5 V
VOL1 vs. IOL
VCC = 2.5 V
VOL2 (V)
1.0
VOL1 (V)
VCC = 3.0 V
VCC = 2.0 V
VCC = 3.0 V
0.6
0.5
0.4
0.3
0.2
0.1
0
VCC = 4.0 V
TA = +25°C
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
TA = +25°C
VCC = 5.0 V
VCC = 6.0 V
VCC = 4.0 V
VCC = 5.0 V
VCC = 6.0 V
0
2
4
6
8
10 12 14 16 18 20
IOL (mA)
0
1
2
3
4
5
6
7
8
9
10
IOL (mA)
(2) “H” level Output Voltage
VCC vs.VOH1 vs. IOH
VCC vs. VOH1 (V)
VCC vs. VOH2 vs. IOH
VCC = 2.5 V VCC = 3.0 V
VCC vs. VOH2 (V)
VCC = 2.5 V
VCC = 3.0 V
VCC = 2.0 V
VCC = 2.0 V
1.0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
TA = +25°C
TA = +25°C
0.9
VCC = 4.0 V
VCC = 4.0 V
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
VCC = 5.0 V
VCC = 6.0 V
VCC = 5.0 V
VCC = 6.0 V
0
–1 –2 –3 –4 –5 –6 –7 –8 –9 –10
IOH (mA)
0
–1
–2
–3
–4
–5
IOH (mA)
36
MB89180 Series
(3) “H” Level Input Voltage/“L” Level Input
Voltage (CMOS Input)
(4) “H” Level Input Voltage/“L” Level Input
Voltage (Hysteresis Input)
VIN vs. VCC
VIN (V)
5.0
VIN vs. VCC
VIN (V)
5.0
TA = +25°C
TA = +25°C
4.5
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
4.0
VIHS
3.5
3.0
2.5
2.0
VILS
1.5
1.0
0.5
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
VCC (V)
VCC (V)
VIHS: Threshold when input voltage in hysteresis
characteristics is set to “H” level
VILS: Threshold when input voltage in hysteresis
characteristics is set to “L” level
(5) Power Supply Current (External Clock)
ICC2 vs. VCC (Mask ROM products)
ICC1 vs. VCC (Mask ROM products)
ICC2 (mA)
1.0
ICC1 (mA)
5.0
TA = +25°C
TA = +25°C
0.9
4.5
0.8
4.0
FCH = 4.2 MHz
FCH = 4.2 MHz
0.7
3.5
FCH = 3 MHz
0.6
3.0
2.5
2.0
1.5
1.0
0.5
0
FCH = 3 MHz
0.5
FCH = 1 MHz
0.4
0.3
0.2
0.1
0
FCH = 1 MHz
1
2
3
4
5
6
7
1
2
3
4
5
6
7
VCC (V)
VCC (V)
(Continued)
37
MB89180 Series
(Continued)
ICCS1 vs. VCC
ICCS2 vs. VCC
TA = +25°C
ICCS1 (mA)
1.2
ICCS2 (mA)
1.0
TA = +25°C
1.1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
FCH = 4.2 MHz
FCH = 3 MHz
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
FCH = 4.2 MHz
FCH = 3 MHz
FCH = 1 MHz
FCH = 1 MHz
0.1
0
0
1
1
2
3
4
5
6
7
2
3
4
5
6
7
VCC (V)
VCC (V)
ICCT vs. VCC
ICCL vs. VCC (Mask ROM units)
ICCT (µA)
ICCL (µA)
30
200
TA = +25°C
TA = +25°C
180
160
140
120
100
80
25
20
15
10
5
FCL = 32.768 kHz
FCL = 32.768 kHz
60
40
20
0
1
0
1
2
3
4
5
6
7
2
3
4
5
6
7
VCC (V)
VCC (V)
(Continued)
38
MB89180 Series
(Continued)
ICCSL vs. VCC
ICCSL (µA)
200
TA = +25°C
180
160
140
120
100
80
FCL = 32.768 kHz
60
40
20
0
1
2
3
4
5
6
7
VCC (V)
(6) Pull-up Resistance Value
RPULL vs. VCC
RPULL (kΩ)
1,000
500
100
50
TA = +85°C
TA = +25°C
TA = –40°C
10
1
2
3
4
5
6
7
VCC (V)
39
MB89180 Series
■ INSTRUCTIONS
Execution instructions can be divided into the following four groups:
• Transfer
• Arithmetic operation
• Branch
• Others
Table 1 lists symbols used for notation of instructions.
Table 1 Instruction Symbols
Symbol
dir
Meaning
Direct address (8 bits)
off
Offset (8 bits)
ext
Extended address (16 bits)
Vector table number (3 bits)
Immediate data (8 bits)
Immediate data (16 bits)
Bit direct address (8:3 bits)
Branch relative address (8 bits)
#vct
#d8
#d16
dir: b
rel
@
Register indirect (Example: @A, @IX, @EP)
A
Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)
Upper 8 bits of accumulator A (8 bits)
AH
AL
Lower 8 bits of accumulator A (8 bits)
Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the
instruction in use.)
T
TH
TL
IX
Upper 8 bits of temporary accumulator T (8 bits)
Lower 8 bits of temporary accumulator T (8 bits)
Index register IX (16 bits)
(Continued)
40
MB89180 Series
(Continued)
Symbol
Meaning
EP
PC
SP
PS
dr
Extra pointer EP (16 bits)
Program counter PC (16 bits)
Stack pointer SP (16 bits)
Program status PS (16 bits)
Accumulator A or index register IX (16 bits)
Condition code register CCR (8 bits)
CCR
RP
Ri
Register bank pointer RP (5 bits)
General-purpose register Ri (8 bits, i = 0 to 7)
Indicates that the very × is the immediate data.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
×
Indicates that the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
( × )
(( × ))
The address indicated by the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
Columns indicate the following:
Mnemonic:
~:
Assembler notation of an instruction
Number of instructions
Number of bytes
#:
Operation:
TL, TH, AH:
Operation of an instruction
A content change when each of the TL, TH, and AH instructions is executed. Symbols in
the column indicate the following:
• “–” indicates no change.
• dH is the 8 upper bits of operation description data.
• AL and AH must become the contents of AL and AH immediately before the instruction
is executed.
• 00 becomes 00.
N, Z, V, C:
OP code:
An instruction of which the corresponding flag will change. If + is written in this column,
the relevant instruction will change its corresponding flag.
Code of an instruction. If an instruction is more than one code, it is written according to
the following rule:
Example: 48 to 4F ← This indicates 48, 49, ... 4F.
41
MB89180 Series
Table 2 Transfer Instructions (48 instructions)
Mnemonic
MOV dir,A
MOV @IX +off,A
MOV ext,A
MOV @EP,A
MOV Ri,A
MOV A,#d8
MOV A,dir
MOV A,@IX +off
MOV A,ext
MOV A,@A
MOV A,@EP
MOV A,Ri
MOV dir,#d8
MOV @IX +off,#d8
MOV @EP,#d8
MOV Ri,#d8
MOVW dir,A
MOVW @IX +off,A
~
#
Operation
TL
TH AH NZVC OP code
3
4
4
3
3
2
3
4
4
3
3
3
4
5
4
4
4
5
2
2
3
1
1
2
2
2
3
1
1
1
3
3
2
2
2
2
(dir) ← (A)
–
–
–
–
–
AL
AL
AL
AL
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– – – –
– – – –
– – – –
– – – –
– – – –
+ + – –
+ + – –
+ + – –
+ + – –
+ + – –
+ + – –
+ + – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
45
46
61
( (IX) +off ) ← (A)
(ext) ← (A)
( (EP) ) ← (A)
47
(Ri) ← (A)
(A) ← d8
(A) ← (dir)
48 to 4F
04
05
06
60
92
(A) ← ( (IX) +off)
(A) ← (ext)
(A) ← ( (A) )
(A) ← ( (EP) )
07
(A) ← (Ri)
(dir) ← d8
08 to 0F
85
86
87
88 to 8F
D5
( (IX) +off ) ← d8
( (EP) ) ← d8
–
–
–
–
(Ri) ← d8
(dir) ← (AH),(dir + 1) ← (AL)
( (IX) +off) ← (AH),
( (IX) +off + 1) ← (AL)
(ext) ← (AH), (ext + 1) ← (AL)
( (EP) ) ← (AH),( (EP) + 1) ← (AL)
(EP) ← (A)
–
D6
MOVW ext,A
MOVW @EP,A
MOVW EP,A
MOVW A,#d16
MOVW A,dir
MOVW A,@IX +off
5
4
2
3
4
5
3
1
1
3
2
2
–
–
–
AL
AL
AL
–
–
–
AH
AH
AH
–
–
–
dH
dH
dH
– – – –
– – – –
– – – –
+ + – –
+ + – –
+ + – –
D4
D7
E3
E4
C5
C6
(A) ← d16
(AH) ← (dir), (AL) ← (dir + 1)
(AH) ← ( (IX) +off),
(AL) ← ( (IX) +off + 1)
(AH) ← (ext), (AL) ← (ext + 1)
(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)
MOVW A,ext
MOVW A,@A
MOVW A,@EP
MOVW A,EP
MOVW EP,#d16
MOVW IX,A
MOVW A,IX
MOVW SP,A
MOVW A,SP
MOV @A,T
MOVW @A,T
MOVW IX,#d16
MOVW A,PS
MOVW PS,A
MOVW SP,#d16
SWAP
5
4
4
2
3
2
2
2
2
3
4
3
2
2
3
2
4
4
2
3
3
3
3
2
3
1
1
1
3
1
1
1
1
1
1
3
1
1
3
1
2
2
1
1
1
1
1
1
AL
AL
AH
AH
AH
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
dH
dH
dH
–
–
dH
–
dH
–
–
–
dH
–
–
AL
–
–
–
dH
dH
dH
dH
dH
+ + – –
+ + – –
+ + – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
+ + + +
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
C4
93
C7
F3
E7
E2
F2
E1
F1
82
83
E6
70
71
E5
10
(AH) ← ( (EP) ), (AL) ← ( (EP) + 1) AL
(A) ← (EP)
(EP) ← d16
(IX) ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AL
AL
–
(A) ← (IX)
(SP) ← (A)
(A) ← (SP)
( (A) ) ← (T)
( (A) ) ← (TH),( (A) + 1) ← (TL)
(IX) ← d16
(A) ← (PS)
(PS) ← (A)
(SP) ← d16
(AH) ↔ (AL)
(dir): b ← 1
(dir): b ← 0
(AL) ↔ (TL)
(A) ↔ (T)
SETB dir: b
CLRB dir: b
XCH A,T
A8 to AF
A0 to A7
42
–
AH
–
–
–
XCHW A,T
43
F7
F6
F5
XCHW A,EP
XCHW A,IX
XCHW A,SP
MOVW A,PC
(A) ↔ (EP)
(A) ↔ (IX)
(A) ↔ (SP)
(A) ← (PC)
–
–
–
–
F0
Notes: • During byte transfer to A, T ← A is restricted to low bytes.
• Operands in more than one operand instruction must be stored in the order in which their mnemonics
are written. (Reverse arrangement of F2MC-8 family)
42
MB89180 Series
Table 3 Arithmetic Operation Instructions (62 instructions)
Mnemonic
ADDC A,Ri
ADDC A,#d8
ADDC A,dir
ADDC A,@IX +off
ADDC A,@EP
ADDCW A
ADDC A
SUBC A,Ri
SUBC A,#d8
SUBC A,dir
SUBC A,@IX +off
SUBC A,@EP
SUBCW A
SUBC A
INC Ri
INCW EP
INCW IX
INCW A
DEC Ri
DECW EP
DECW IX
DECW A
MULU A
DIVU A
~
#
Operation
(A) ← (A) + (Ri) + C
TL
TH AH NZVC OP code
3
2
3
4
3
3
2
3
2
3
4
3
3
2
4
3
3
3
4
3
3
3
19
21
3
3
3
2
3
2
1
2
2
2
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
00
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
dH
–
–
–
–
dH
–
–
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + –
– – – –
– – – –
+ + – –
+ + + –
– – – –
– – – –
+ + – –
– – – –
– – – –
+ + R –
+ + R –
+ + R –
+ + + +
+ + + +
+ + – +
28 to 2F
24
(A) ← (A) + d8 + C
(A) ← (A) + (dir) + C
(A) ← (A) + ( (IX) +off) + C
(A) ← (A) + ( (EP) ) + C
(A) ← (A) + (T) + C
(AL) ← (AL) + (TL) + C
(A) ← (A) − (Ri) − C
(A) ← (A) − d8 − C
(A) ← (A) − (dir) − C
(A) ← (A) − ( (IX) +off) − C
(A) ← (A) − ( (EP) ) − C
(A) ← (T) − (A) − C
(AL) ← (TL) − (AL) − C
(Ri) ← (Ri) + 1
(EP) ← (EP) + 1
(IX) ← (IX) + 1
(A) ← (A) + 1
(Ri) ← (Ri) − 1
(EP) ← (EP) − 1
(IX) ← (IX) − 1
(A) ← (A) − 1
25
26
27
23
22
38 to 3F
34
35
36
37
33
32
C8 to CF
C3
C2
C0
D8 to DF
D3
–
D2
D0
01
11
63
73
53
12
dH
dH
00
dH
dH
dH
–
(A) ← (AL) × (TL)
(A) ← (T) / (AL),MOD → (T)
(A) ← (A) (T)
(A) ← (A) (T)
(A) ← (A) (T)
ANDW A
ORW A
XORW A
CMP A
CMPW A
RORC A
(TL) − (AL)
(T) − (A)
–
–
13
03
→
→
A
C
←
C ← A
ROLC A
2
1
–
–
–
+ + – +
02
(A) − d8
(A) − (dir)
(A) − ( (EP) )
(A) − ( (IX) +off)
(A) − (Ri)
CMP A,#d8
CMP A,dir
CMP A,@EP
CMP A,@IX +off
CMP A,Ri
DAA
2
3
3
4
3
2
2
2
2
3
3
4
3
2
2
3
2
2
1
2
1
1
1
1
2
2
1
2
1
1
2
2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
14
15
17
16
18 to 1F
84
Decimal adjust for addition
Decimal adjust for subtraction
(A) ← (AL) (TL)
(A) ← (AL) d8
(A) ← (AL) (dir)
(A) ← (AL) ( (EP) )
(A) ← (AL) ( (IX) +off)
(A) ← (AL) (Ri)
(A) ← (AL) (TL)
(A) ← (AL) d8
DAS
XOR A
94
52
54
55
57
56
XOR A,#d8
XOR A,dir
XOR A,@EP
XOR A,@IX +off
XOR A,Ri
AND A
58 to 5F
62
AND A,#d8
AND A,dir
64
65
(A) ← (AL) (dir)
(Continued)
43
MB89180 Series
(Continued)
Mnemonic
~
#
Operation
TL
TH AH NZVC OP code
AND A,@EP
AND A,@IX +off
AND A,Ri
OR A
OR A,#d8
3
4
3
2
2
3
3
4
3
5
4
5
4
3
3
1
2
1
1
2
2
1
2
1
3
2
3
2
1
1
(A) ← (AL) ( (EP) )
(A) ← (AL) ( (IX) +off)
(A) ← (AL) (Ri)
(A) ← (AL) (TL)
(A) ← (AL) d8
(A) ← (AL) (dir)
(A) ← (AL) ( (EP) )
(A) ← (AL) ( (IX) +off)
(A) ← (AL) (Ri)
(dir) – d8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + + +
+ + + +
+ + + +
+ + + +
– – – –
– – – –
67
66
68 to 6F
72
74
75
77
76
OR A,dir
OR A,@EP
OR A,@IX +off
OR A,Ri
CMP dir,#d8
CMP @EP,#d8
CMP @IX +off,#d8
CMP Ri,#d8
INCW SP
78 to 7F
95
97
96
98 to 9F
C1
( (EP) ) – d8
( (IX) + off) – d8
(Ri) – d8
(SP) ← (SP) + 1
(SP) ← (SP) – 1
DECW SP
D1
Table 4 Branch Instructions (17 instructions)
Mnemonic
~
#
Operation
TL
TH AH NZVC OP code
BZ/BEQ rel
BNZ/BNE rel
BC/BLO rel
BNC/BHS rel
BN rel
BP rel
BLT rel
3
3
3
3
3
3
3
3
5
5
2
3
6
6
3
4
6
2
2
2
2
2
2
2
2
3
3
1
3
1
3
1
1
1
If Z = 1 then PC ← PC + rel
If Z = 0 then PC ← PC + rel
If C = 1 then PC ← PC + rel
If C = 0 then PC ← PC + rel
If N = 1 then PC ← PC + rel
If N = 0 then PC ← PC + rel
If V N = 1 then PC ← PC + rel
If V N = 0 then PC ← PC + reI
If (dir: b) = 0 then PC ← PC + rel
If (dir: b) = 1 then PC ← PC + rel
(PC) ← (A)
(PC) ← ext
Vector call
Subroutine call
(PC) ← (A),(A) ← (PC) + 1
Return from subrountine
Return form interrupt
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– + – –
– + – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
Restore
FD
FC
F9
F8
FB
FA
FF
FE
BGE rel
BBC dir: b,rel
BBS dir: b,rel
JMP @A
JMP ext
CALLV #vct
CALL ext
XCHW A,PC
RET
B0 to B7
B8 to BF
E0
21
E8 to EF
31
F4
20
30
RETI
–
Table 5 Other Instructions (9 instructions)
Mnemonic
~
#
Operation
TL
TH AH NZVC OP code
PUSHW A
POPW A
PUSHW IX
POPW IX
NOP
CLRC
SETC
4
4
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
–
– – – –
– – – –
– – – –
– – – –
– – – –
– – – R
– – – S
– – – –
– – – –
40
50
41
51
00
81
91
80
90
CLRI
SETI
44
L H
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
PUSHW
0
NOP
SWAP RET
RETI
POPW MOV
MOVW CLRI
A,PS
SETI
CLRB BBC
INCW
DECW JMP
@A
MOVW
A,PC
A
dir: 0,rel
A
A,ext
dir: 0
A
A
PUSHW
1
2
MULU DIVU
A
JMP
addr16 addr16
CALL
POPW MOV
MOVW CLRC SETC
PS,A
CLRB BBC
INCW
DECW MOVW MOVW
SP SP,A A,SP
IX
dir: 1,rel
A
A
IX
ext,A
dir: 1
SP
ROLC CMP
A
ADDC SUBC XCH
A, T
XOR
AND
OR
MOV
@A,T
MOV
A,@A
CLRB BBC
INCW
DECW MOVW MOVW
IX IX,A A,IX
dir: 2,rel
A
A
A
A
A
A
dir: 2
IX
INCW
ADDCW SUBCW
3
RORC CMPW
XCHW XORW ANDW ORW
MOVW MOVW CLRB BBC
DECW MOVW MOVW
EP EP EP,A A,EP
A
A
dir: 3,rel
A
A
A, T
A
A
@A,T
A,@A
dir: 3
4
MOV
A,#d8
CMP
A,#d8
ADDC SUBC
XOR
A,#d8
AND
A,#d8
OR
A,#d8
DAA
DAS
CLRB BBC
MOVW MOVW MOVW XCHW
dir: 4,rel
A,#d8
A,#d8
dir: 4
A,ext
ext,A A,#d16
A,PC
5
MOV
A,dir
CMP
A,dir
ADDC SUBC MOV
A,dir A,dir dir,A
XOR
A,dir
AND
A,dir
OR
MOV
CMP
CLRB BBC
MOVW MOVW MOVW XCHW
dir: 5,rel
SP,#d16
A,dir dir,#d8 dir,#d8
dir: 5
A,dir
dir,A
A,SP
MOV
CMP
ADDC
SUBC
MOV @IX XOR
AND
OR
MOV
CMP
MOVW
A,@IX +d @IX +d,A
MOVW
6
CLRB BBC
MOVW XCHW
IX,#d16 A,IX
A,@IX +d A,@IX +d A,@IX +d A,@IX +d +d,A
A,@IX +d A,@IX +d A,@IX +d @IX +d,#d8 @IX +d,#d8
dir: 6,rel
dir: 6
7
MOV
CMP
ADDC SUBC MOV
XOR
AND
OR
MOV
CMP
CLRB BBC
MOVW MOVW MOVW XCHW
@EP,#d8 @EP,#d8
dir: 7,rel
EP,#d16
A,@EP A,@EP A,@EP A,@EP @EP,A A,@EP A,@EP A,@EP
dir: 7
A,@EP @EP,A
A,EP
8
MOV
A,R0
CMP
A,R0
ADDC SUBC MOV
A,R0 A,R0 R0,A
XOR
A,R0
AND
A,R0
OR
MOV
CMP
SETB
dir: 0
BBS
dir: 0,rel
INC
INC
INC
INC
INC
INC
INC
INC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
CALLV BNC
#0
A,R0 R0,#d8 R0,#d8
R0
R1
R2
R3
R4
R5
R6
R7
R0
R1
R2
R3
R4
R5
R6
R7
rel
rel
rel
rel
rel
rel
rel
rel
9
MOV
A,R1
CMP
A,R1
ADDC SUBC MOV
A,R1 A,R1 R1,A
XOR
A,R1
AND
A,R1
OR
MOV
CMP
SETB
dir: 1
BBS
dir: 1,rel
CALLV BC
#1
A,R1 R1,#d8 R1,#d8
A
B
C
D
E
F
MOV
A,R2
CMP
A,R2
ADDC SUBC MOV
A,R2 A,R2 R2,A
XOR
A,R2
AND
A,R2
OR
MOV
CMP
SETB
dir: 2
BBS
dir: 2,rel
CALLV BP
#2
A,R2 R2,#d8 R2,#d8
MOV
A,R3
CMP
A,R3
ADDC SUBC MOV
A,R3 A,R3 R3,A
XOR
A,R3
AND
A,R3
OR
MOV
CMP
SETB
dir: 3
BBS
dir: 3,rel
CALLV BN
#3
A,R3 R3,#d8 R3,#d8
MOV
A,R4
CMP
A,R4
ADDC SUBC MOV
A,R4 A,R4 R4,A
XOR
A,R4
AND
A,R4
OR
MOV
CMP
SETB
dir: 4
BBS
dir: 4,rel
CALLV BNZ
#4
A,R4 R4,#d8 R4,#d8
MOV A CMP
A,R5 A,R5
ADDC SUBC MOV
A,R5 A,R5 R5,A
XOR
A,R5
AND
A,R5
OR
MOV
CMP
SETB
dir: 5
BBS
dir: 5,rel
CALLV BZ
#5
A,R5 R5,#d8 R5,#d8
MOV
A,R6
CMP
A,R6
ADDC SUBC MOV
A,R6 A,R6 R6,A
XOR
A,R6
AND
A,R6
OR
MOV
CMP
SETB
dir: 6
BBS
dir: 6,rel
CALLV BGE
#6
A,R6 R6,#d8 R6,#d8
MOV
A,R7
CMP
A,R7
ADDC SUBC MOV
A,R7 A,R7 R7,A
XOR
A,R7
AND
A,R7
OR
MOV
CMP
SETB
dir: 7
BBS
dir: 7,rel
CALLV BLT
#7
A,R7 R7,#d8 R7,#d8
MB89180 Series
■ MASK OPTIONS
Part number
MB89181/182/183
MB89P185
MB89PV180
No.
Specify when
ordering masking
Set with EPROM
programmer
Setting not
possible
Specifying procedure
Can be set per pin
(P10 to P17 are
available only when
segment output is not
selected.)
Can be set per pin
(P10 to P17 are
available only when
segment output is not
selected.)
Pull-up resistors
P00 to P07, P10 to P17
1
Fixed to without pull-
up resistor
Can be set per pin
(Available only when Fixed to without pull-
segment output is
not selected.)
Pull-up resistors
P40 to P47, P50 to P57
2
up resistor
Pull-up resistors
P20 to P27
Fixed to without pull-
up resistor
3
Can be set per pin
Selectable
Power-on reset
With power-on reset
Fixed to with power-
on reset
4
Selectable
Without power-on reset
Selectable
WTM1 WTM0
Selection of oscillation stabilization
delay time
The initial value of the main clock
oscillation stabilization time is
selectable by bit value of WTM1
and WTM0.
Fixed to oscillation
stabilization time of
216/FCH
0
0
1
1
0: 22/FCH
1: 212/FCH
0: 216/FCH
1: 218/FCH
5
Main clock oscillation type
Crystal or ceramic oscillator
CR
Crystal or ceramic
oscillator
Crystal or ceramic
oscillator
6
7
8
Selectable
Selectable
Selectable
Reset pin output
With reset output
Without reset output
Selectable
Selectable
With reset output
Clock mode selection
Dual-clock mode
Single-clock mode
Fixed to dual-clock
mode
Segment output selection
32 segments:No port selection
28 segments:Selection of P17 to
P14
24 segments: Selection of P17 to
P10
20 segments:Selection of P17 to
P10,and P57 to P54
16 segments:Selection of P17 to
P10,and P57 to P50
-101: 32 segments
-102: 28 segments
-103: 24 segments
-104: 20 segments
-105: 16 segments
-106: 12 segments
-107: 8 segments
Selectable
Selects the number
of segments.
9
12 segments:Selection of P17 to
P10,P57 to P50, and P47 to P44
8 segments:Selection of P17 to
P10,P57 to P50, and P47 to P40
46
MB89180 Series
■ ORDERING INFORMATION
Part number
Package
Remarks
MB89181PF
MB89182PF
MB89183PF
MB89P185PF-101
MB89P185PF-102
MB89P185PF-103
MB89P185PF-104
MB89P185PF-105
MB89P185PF-106
MB89P185PF-107
64-pin Plastic QFP
(FPT-64P-M06)
MB89181FM
MB89182FM
MB89183FM
MB89P185PFM-101
MB89P185PFM-102
MB89P185PFM-103
MB89P185PFM-104
MB89P185PFM-105
MB89P185PFM-106
MB89P185PFM-107
64-pin Plastic QFP
(FPT-64P-M09)
MB89181PFV
MB89182PFV
MB89183PFV
64-pin Plastic SQFP
(FPT-64P-M03)
MB89PV180CF-101
MB89PV180CF-102
MB89PV180CF-103
MB89PV180CF-104
MB89PV180CF-105
MB89PV180CF-106
MB89PV180CF-107
64-pin Ceramic MQFP
(MQP-64C-P01)
47
MB89180 Series
■ PACKAGE DIMENSIONS
64-pin Plastic QFP
(FPT-64P-M06)
24.70±0.40(.972±.016)
20.00±0.20(.787±.008)
3.35(.132)MAX
51
33
0.05(.002)MIN
(STAND OFF)
(Mounting height)
52
32
14.00±0.20 18.70±0.40
(.551±.008) (.736±.016)
12.00(.472)
REF
16.30±0.40
(.642±.016)
INDEX
64
20
"A"
1
19
LEAD No.
0.15±0.05(.006±.002)
Details of "B" part
1.00(.0394)
TYP
0.40±0.10
(.016±.004)
M
0.20(.008)
Details of "A" part
0.25(.010)
"B"
0.30(.012)
0.18(.007)MAX
0.10(.004)
18.00(.709)REF
22.30±0.40(.878±.016)
0
10°
1.20±0.20
(.047±.008)
0.63(.025)MAX
Dimensions in mm (inches)
C
1994 FUJITSU LIMITED F64013S-3C-2
64 pin, Plastic QFP
(FPT-64P-M09)
14.00±0.20(.551±.008)SQ
1.50 +–00..1200
.059+–..000048
48
33
32
12.00±0.10(.472±.004)SQ
49
9.75
(.384)
REF
13.00
(.512)
NOM
1 PIN INDEX
64
17
M
1
16
Details of "A" part
LEAD No.
"A"
0.65(.0256)TYP
0.30±0.10
(.012±.004)
0.127 +–00..0025
.005–+..000012
0.10±0.10
(.004±.004)
0.13(.005)
(STAND OFF)
0.50±0.20
(.020±.008)
0.10(.004)
0
10°
Dimensions in mm (inches).
48
MB89180 Series
(Continued)
64 pin, PlasticLQFP
(FPT-64P-M03)
1.50−+00..2100
.059 −+..000048
12.00±0.20(.472±.008)SQ
(Mounting Height)
48
49
10.00±0.10(.394±.004)SQ
33
32
11.00
(.433)
NOM
7.50
(.295)
REF
INDEX
Details of "A" part
64
17
1
16
"A"
LEAD No.
0.10±0.10
(.004±.004)
0.18−+00..0038
.007 −+..000013
0.127+−00..0025
.005 −+..000012
(STAND OFF)
0.50±0.08
(.0197±.0031)
0.50±0.20
(.020±.008)
0.10(.004)
0
10˚
C
1995 FUJITSU LIMITED F64009S-2C-5
Dimensions in mm (inches).
64-pin Ceramic MQFP
(MQP-64C-P01)
18.70(.736)TYP
16.30±0.33
(.642±.013)
15.58±0.20
(.613±.008)
12.00(.472)TYP
INDEX AREA
1.00±0.25
(.039±.010)
1.20+–00..2400
.047+–..000186
1.00±0.25
(.039±.010)
1.27±0.13
(.050±.005)
18.12±0.20
(.713±.008)
22.30±0.33
(.878±.013)
12.02(.473)
TYP
18.00(.709)
TYP
10.16(.400)
TYP
14.22(.560)
TYP
0.30(.012)
TYP
24.70(.972)
TYP
0.40±0.10
(.016±.004)
1.27±0.13
(.050±.005)
0.30(.012)TYP
7.62(.300)TYP
9.48(.373)TYP
11.68(.460)TYP
0.40±0.10
(.016±.004)
1.20+–00..2400
.047+–..000186
10.82(.426)
MAX
0.15±0.05
(.006±.002)
0.50(.020)TYP
Dimensions in mm (inches)
C
1994 FUJITSU LIMITED M64004SC-1-3
49
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-88, Japan
Tel: (044) 754-3763
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
Fax: (044) 754-3329
The information and circuit diagrams in this document presented
as examples of semiconductor device applications, and are not
intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the
use of this information or circuit diagrams.
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, U.S.A.
Tel: (408) 922-9000
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Fax: (408) 432-9044/9045
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LIMITED
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
Any semiconductor devices have inherently a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required
for export of those products from Japan.
F9703
FUJITSU LIMITED Printed in Japan
相关型号：
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